diff -Nru gcc-13-13.1.0/debian/ada/check_ali_update.sh gcc-13-13.1.0/debian/ada/check_ali_update.sh --- gcc-13-13.1.0/debian/ada/check_ali_update.sh 2021-10-10 17:12:38.000000000 +0000 +++ gcc-13-13.1.0/debian/ada/check_ali_update.sh 2023-06-30 15:42:25.000000000 +0000 @@ -34,9 +34,9 @@ continue fi - pattern="^D $unit\.ad" - lines1=`grep "$pattern" "$ali1"` - lines2=`grep "$pattern" "$ali2"` + # Strip the timestamp field, we are only interested in checksums. + lines1=`sed -En "s/^D $unit[.]ad[bs]\t+[0-9]{14} //p" "$ali1"` + lines2=`sed -En "s/^D $unit[.]ad[bs]\t+[0-9]{14} //p" "$ali2"` if [ "$lines1" != "$lines2" ]; then changed="$changed $unit.ali" fi diff -Nru gcc-13-13.1.0/debian/changelog gcc-13-13.1.0/debian/changelog --- gcc-13-13.1.0/debian/changelog 2023-05-13 07:12:01.000000000 +0000 +++ gcc-13-13.1.0/debian/changelog 2023-07-11 08:50:18.000000000 +0000 @@ -1,8 +1,130 @@ -gcc-13 (13.1.0-2ubuntu2~22.04) jammy-proposed; urgency=medium +gcc-13 (13.1.0-8ubuntu1~22.04) jammy; urgency=medium - * Backport GCC 13.1.0 release. + * PPA upload, backport to 22.04 LTS. - -- Matthias Klose Sat, 13 May 2023 09:12:01 +0200 + -- Matthias Klose Tue, 11 Jul 2023 10:50:18 +0200 + +gcc-13 (13.1.0-8ubuntu1) mantic; urgency=medium + + * Merge with Debian; remaining changes: + - Build from upstream sources. + + -- Matthias Klose Tue, 11 Jul 2023 10:28:29 +0200 + +gcc-13 (13.1.0-8) unstable; urgency=medium + + * Update to git 20230711 from the gcc-13 branch. + - Fix PR tree-optimization/110557, PR c++/110595, + PR tree-optimization/110556, PR tree-optimization/110515, + PR tree-optimization/110392, PR tree-optimization/110381, + PR target/110560 (RISCV), PR target/105325 (PPC), + PR tree-optimization/110228, PR c++/110468, PR c++/110463, + PR d/108842, PR d/110516, PR d/110514, PR d/110471, PR fortran/110585, + PR testsuite/108835, PR d/103944, PR libstdc++/104299. + * Apply proposed patch for PR target/106966. Addresses: #1019011. + + -- Matthias Klose Tue, 11 Jul 2023 10:25:56 +0200 + +gcc-13 (13.1.0-7ubuntu1) mantic; urgency=medium + + * Merge with Debian; remaining changes: + - Build from upstream sources. + + -- Matthias Klose Fri, 30 Jun 2023 17:42:41 +0200 + +gcc-13 (13.1.0-7) unstable; urgency=medium + + * Update to git 20230630 from the gcc-13 branch. + - Fix PR tree-optimization/110298, PR debug/110295, PR middle-end/110055, + PR ipa/109983, PR tree-optimization/109143, PR target/110132 (AArch64), + PR target/110100 (AArch64), PR target/110100 (AArch64), + PR target/109932 (PPC), PR target/110011 (PPC), PR c++/110102, + PR c++/109247, PR rtl-optimization/110237, PR target/110309 (x86), + PR testsuite/66005, PR middle-end/110420, PR middle-end/103979, + PR middle-end/98619, PR ipa/110276, + PR target/110264 (RISCV, closes: #1038774), PR d/106977, + PR target/110406, PR d/110359, PR d/110113, PR fortran/86277, + PR libstdc++/110239, PR libstdc++/110149, PR libstdc++/109741, + PR libstdc++/100285. + + [ Nicolas Boulenguez ] + * ada/check_ali_update.sh: report checksum changes but ignore timestamps + + [Matthias Klose] + * Fix PR tree-optimization/110280, taken from the trunk. Closes: #1038768. + + -- Matthias Klose Fri, 30 Jun 2023 14:36:39 +0200 + +gcc-13 (13.1.0-6ubuntu1) mantic; urgency=medium + + * Merge with Debian; remaining changes: + - Build from upstream sources. + + -- Matthias Klose Sun, 18 Jun 2023 09:45:32 +0200 + +gcc-13 (13.1.0-6) unstable; urgency=medium + + * Update to git 20230617 from the gcc-13 branch. + - Fix PR target/110136 (loongarch), PR target/110227 (X86), + PR middle-end/110200. + * Ignore gccrs bootstrap comparison failures on mipsel. + * Remove obsolete gcn assembler patch. + * Mark libgcc-sN packages as protected/important for newer releases. + * Apply proposed patch for PR ipa/110276. Closes: #1037640. + + -- Matthias Klose Sat, 17 Jun 2023 11:34:12 +0200 + +gcc-13 (13.1.0-5ubuntu1) mantic; urgency=medium + + * Update to git 20230613 from the gcc-13 branch. + - Fix PR middle-end/110200. + * Ignore gccrs bootstrap comparison failures on mipsel. + * Remove obsolete gcn assembler patch. + * Mark libgcc-sN packages as protected/important for newer releases. + + -- Matthias Klose Tue, 13 Jun 2023 09:54:20 +0200 + +gcc-13 (13.1.0-5) unstable; urgency=medium + + * Re-enable building gccrs. + + -- Matthias Klose Sun, 11 Jun 2023 17:12:06 +0200 + +gcc-13 (13.1.0-4) unstable; urgency=medium + + * Update to git 20230611 from the gcc-13 branch. + - Fix PR target/109650 (AVR), PR target/92729 (AVR), + PR tree-optimization/110165, PR tree-optimization/110166, + PR target/110044 (PPC), PR target/110108 (X86), PR target/109939 (ARM), + PR target/106907 (PPC), PR target/109800 (ARM), PR bootstrap/110085, + PR target/110088 (AVR), PR target/109954 (X86), PR target/110036 (RISCV), + PR target/109547 (RISCV), PR target/104327 (AVR), PR target/82931 (AVR), + PR tree-optimization/109505, PR target/105753 (AVR), PR fortran/96024, + PR fortran/100607, PR libgcc/109670, PR libgcc/109685, + PR libstdc++/108178, PR libstdc++/110139, PR libstdc++/109758, + PR libstdc++/109822, PR libstdc++/109261, PR libstdc++/109949, + PR libstdc++/109261. + * Configure --with-cpu=ev56 instead of --with-arch=ev56 for alpha. + * Also provide the liblto_plugin.so symlink in the old place. + Closes: #1036566. + + -- Matthias Klose Sun, 11 Jun 2023 13:48:04 +0200 + +gcc-13 (13.1.0-3) experimental; urgency=medium + + * Update to git 20230520 from the gcc-13 branch. + - PR c++/109884, PR target/104338 (RISCV), PR libstdc++/109816, + Fix PR target/109661 (AArch64), PR c++/109871, PR c++/109868, + PR c++/109774, PR c++/109745, PR c++/83258, PR c++/80488, PR c++/97700, + PR c++/109761, PR c++/109651, PR fortran/109846, PR fortran/109641, + PR target/104338 (RISCV), PR libstdc++/109816, PR libstdc++/109883, + PR libstdc++/109883. + * Update libgcc-s, libhwasan and libstdc++ symbols files. + * Patch libstdc++ to support SOURCE_DATE_EPOCH in documentation (Vagrant + Cascadian). Closes: #1036367. + * Configure --with-arch=ev56 for alpha. Closes: #1036158. + + -- Matthias Klose Sat, 20 May 2023 11:42:17 +0200 gcc-13 (13.1.0-2ubuntu2) mantic; urgency=medium diff -Nru gcc-13-13.1.0/debian/control gcc-13-13.1.0/debian/control --- gcc-13-13.1.0/debian/control 2023-05-13 07:12:01.000000000 +0000 +++ gcc-13-13.1.0/debian/control 2023-07-11 08:50:18.000000000 +0000 @@ -47,6 +47,8 @@ Provides: libgcc1 (= ${gcc:EpochVersion}), libgcc-s1-armel [armel], libgcc-s1-armhf [armhf] Multi-Arch: same Pre-Depends: ${misc:Pre-Depends} +XB-Important: yes +Protected: yes Breaks: ${libgcc:Breaks} Replaces: libgcc1 (<< 1:10) Description: GCC support library @@ -61,6 +63,8 @@ Priority: optional Multi-Arch: same Pre-Depends: ${misc:Pre-Depends} +XB-Important: yes +Protected: yes Depends: gcc-13-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} Provides: libgcc2 (= ${gcc:EpochVersion}), Breaks: ${libgcc:Breaks} @@ -74,6 +78,8 @@ X-DH-Build-For-Type: target Architecture: hppa Multi-Arch: same +XB-Important: yes +Protected: yes Pre-Depends: ${misc:Pre-Depends} Provides: libgcc4 (= ${gcc:EpochVersion}) Breaks: ${libgcc:Breaks} diff -Nru gcc-13-13.1.0/debian/patches/gccrs-bootstrap-mipsel.diff gcc-13-13.1.0/debian/patches/gccrs-bootstrap-mipsel.diff --- gcc-13-13.1.0/debian/patches/gccrs-bootstrap-mipsel.diff 1970-01-01 00:00:00.000000000 +0000 +++ gcc-13-13.1.0/debian/patches/gccrs-bootstrap-mipsel.diff 2023-06-13 07:54:11.000000000 +0000 @@ -0,0 +1,12 @@ +# DP: Ignore gccrs bootstrap comparison failures on mipsel. + +--- a/src/configure.ac ++++ b/src/configure.ac +@@ -3799,6 +3799,7 @@ + compare_exclusions="$compare_exclusions | gcc/m2/gm2version*" + case "$target" in + hppa*64*-*-hpux*) ;; ++ mipsel-*linux-gnu) compare_exclusions="$compare_exclusions | gcc/rust/rust-macro-builtins.o | gcc/rust/rust-session-manager.o | gcc/rust/rust-cfg-parser.o | gcc/rust/rust-lex.o" ;; + powerpc*-ibm-aix*) compare_exclusions="$compare_exclusions | *libgomp*\$(objext)" ;; + esac + AC_SUBST(compare_exclusions) diff -Nru gcc-13-13.1.0/debian/patches/git-doc-updates.diff gcc-13-13.1.0/debian/patches/git-doc-updates.diff --- gcc-13-13.1.0/debian/patches/git-doc-updates.diff 2023-05-10 11:53:08.000000000 +0000 +++ gcc-13-13.1.0/debian/patches/git-doc-updates.diff 2023-07-11 08:28:24.000000000 +0000 @@ -1,13 +1,86 @@ -# DP: updates from the 13 branch upto 20230510 (documentation). +# DP: updates from the 13 branch upto 20230711 (documentation). LANG=C git diff --no-renames --src-prefix=a/src/ --dst-prefix=b/src/ \ - cc035c5d8672f87dc8c2756d9f8367903aa72d93 7c7eac06c3b2258265933246ea6299a245541bde \ + cc035c5d8672f87dc8c2756d9f8367903aa72d93 7f6d86180247d75f3774e3b7c8f825e06270edc9 \ | awk '/^diff .*\.texi/ {skip=0; print; next} /^diff / {skip=1; next} skip==0' \ | grep -v -E '^(diff|index)' +--- a/src/gcc/d/gdc.texi ++++ b/src/gcc/d/gdc.texi +@@ -699,6 +699,23 @@ Do not warn about usage of deprecated features and symbols with + @item -Werror + Turns all warnings into errors. + ++@opindex Wextra ++@opindex Wno-extra ++@item -Wextra ++This enables some extra warning flags that are not enabled by ++@option{-Wall}. ++ ++@gccoptlist{-Waddress ++-Wcast-result ++-Wmismatched-special-enum ++-Wunknown-pragmas} ++ ++@opindex Wmismatched-special-enum ++@opindex Wno-mismatched-special-enum ++@item -Wmismatched-special-enum ++Warn when an enum the compiler recognizes as special is declared with a ++different size to the built-in type it is representing. ++ + @opindex Wspeculative + @opindex Wno-speculative + @item -Wspeculative +--- a/src/gcc/d/implement-d.texi ++++ b/src/gcc/d/implement-d.texi +@@ -2085,6 +2085,11 @@ for convenience: @code{c_complex_double}, @code{c_complex_float}, + @code{c_complex_real}, @code{cpp_long}, @code{cpp_longlong}, + @code{c_long_double}, @code{cpp_ulong}, @code{cpp_ulonglong}. + ++It may cause undefined behavior at runtime if a special enum is declared with a ++base type that has a different size to the target C/C++ type it is ++representing. The GNU D compiler will catch such declarations and emit a ++warning when the @option{-Wmismatched-special-enum} option is seen on the ++command-line. + + @c -------------------------------------------------------- + +--- a/src/gcc/doc/extend.texi ++++ b/src/gcc/doc/extend.texi +@@ -13660,7 +13660,7 @@ an extension. @xref{Variable Length}, for details. + + @enddefbuiltin + +-@defbuiltin{{void *}__builtin_alloca_with_align_and_max (size_t size, size_t alignment, size_t max_size)} ++@defbuiltin{{void *} __builtin_alloca_with_align_and_max (size_t size, size_t alignment, size_t max_size)} + Similar to @code{__builtin_alloca_with_align} but takes an extra argument + specifying an upper bound for @var{size} in case its value cannot be computed + at compile time, for use by @option{-fstack-usage}, @option{-Wstack-usage} +--- a/src/gcc/doc/install.texi ++++ b/src/gcc/doc/install.texi +@@ -382,6 +382,9 @@ tables. + + Used by @command{automake}. + ++If available, enables parallel testing of @samp{libgomp} in case that ++@command{flock} is not available. ++ + @end table + + Several support libraries are necessary to build GCC, some are required, --- a/src/gcc/doc/invoke.texi +++ b/src/gcc/doc/invoke.texi -@@ -3781,7 +3781,7 @@ where @code{std::minmax} returns @code{std::pair}, and +@@ -1226,7 +1226,8 @@ See RS/6000 and PowerPC Options. + -mbig-endian -mlittle-endian + -mstack-protector-guard=@var{guard} -mstack-protector-guard-reg=@var{reg} + -mstack-protector-guard-offset=@var{offset} +--mcsr-check -mno-csr-check} ++-mcsr-check -mno-csr-check ++-minline-atomics -mno-inline-atomics} + + @emph{RL78 Options} + @gccoptlist{-msim -mmul=none -mmul=g13 -mmul=g14 -mallregs +@@ -3781,7 +3782,7 @@ where @code{std::minmax} returns @code{std::pair}, and both references dangle after the end of the full expression that contains the call to @code{std::minmax}. @@ -16,7 +89,24 @@ @opindex Wdelete-non-virtual-dtor @opindex Wno-delete-non-virtual-dtor -@@ -6126,6 +6126,7 @@ name is still supported, but the newer name is more descriptive.) +@@ -4800,10 +4801,12 @@ and Objective-C++ programs: + Use @var{class-name} as the name of the class to instantiate for each + literal string specified with the syntax @code{@@"@dots{}"}. The default + class name is @code{NXConstantString} if the GNU runtime is being used, and +-@code{NSConstantString} if the NeXT runtime is being used (see below). The +-@option{-fconstant-cfstrings} option, if also present, overrides the +-@option{-fconstant-string-class} setting and cause @code{@@"@dots{}"} literals +-to be laid out as constant CoreFoundation strings. ++@code{NSConstantString} if the NeXT runtime is being used (see below). On ++Darwin (macOS, MacOS X) platforms, the @option{-fconstant-cfstrings} option, if ++also present, overrides the @option{-fconstant-string-class} setting and cause ++@code{@@"@dots{}"} literals to be laid out as constant CoreFoundation strings. ++Note that @option{-fconstant-cfstrings} is an alias for the target-specific ++@option{-mconstant-cfstrings} equivalent. + + @opindex fgnu-runtime + @item -fgnu-runtime +@@ -6126,6 +6129,7 @@ name is still supported, but the newer name is more descriptive.) @gccoptlist{-Wclobbered -Wcast-function-type @@ -24,6 +114,84 @@ -Wdeprecated-copy @r{(C++ only)} -Wempty-body -Wenum-conversion @r{(C only)} +@@ -6978,7 +6982,7 @@ This warning is enabled by @option{-Wall}. + @opindex Wmissing-include-dirs + @opindex Wno-missing-include-dirs + @item -Wmissing-include-dirs @r{(C, C++, Objective-C, Objective-C++ and Fortran only)} +-Warn if a user-supplied include directory does not exist. This opions is disabled ++Warn if a user-supplied include directory does not exist. This option is disabled + by default for C, C++, Objective-C and Objective-C++. For Fortran, it is partially + enabled by default by warning for -I and -J, only. + +@@ -23945,10 +23949,21 @@ This is by default ON@. + @item -gfull + Emit debugging information for all symbols and types. + ++@opindex fconstant-cfstrings ++@item -fconstant-cfstrings ++The @option{-fconstant-cfstrings} is an alias for @option{-mconstant-cfstrings}. ++ ++@opindex mconstant-cfstrings ++@item -mconstant-cfstrings ++When the NeXT runtime is being used (the default on these systems), override ++any @option{-fconstant-string-class} setting and cause @code{@@"@dots{}"} ++literals to be laid out as constant CoreFoundation strings. ++ ++@opindex mmacosx-version-min + @item -mmacosx-version-min=@var{version} +-The earliest version of MacOS X that this executable will run on +-is @var{version}. Typical values of @var{version} include @code{10.1}, +-@code{10.2}, and @code{10.3.9}. ++The earliest version of MacOS X that this executable will run on is ++@var{version}. Typical values supported for @var{version} include @code{12}, ++@code{10.12}, and @code{10.5.8}. + + If the compiler was built to use the system's headers by default, + then the default for this option is the system version on which the +@@ -29006,6 +29021,13 @@ Do or don't use smaller but slower prologue and epilogue code that uses + library function calls. The default is to use fast inline prologues and + epilogues. + ++@opindex minline-atomics ++@item -minline-atomics ++@itemx -mno-inline-atomics ++Do or don't use smaller but slower subword atomic emulation code that uses ++libatomic function calls. The default is to use fast inline subword atomics ++that do not require libatomic. ++ + @opindex mshorten-memrefs + @item -mshorten-memrefs + @itemx -mno-shorten-memrefs +@@ -32366,7 +32388,8 @@ SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, + XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI, + MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, + PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, +-AVXIFMA, AVXVNNIINT8, AVXNECONVERT and CMPCCXADD instruction set support. ++AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, ENQCMD and UINTR instruction set ++support. + + @item grandridge + Intel Grand Ridge CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, +@@ -32374,8 +32397,8 @@ SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, + XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI, + MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, + PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, +-AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD and RAOINT instruction set +-support. ++AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, ENQCMD, UINTR and RAOINT ++instruction set support. + + @item knl + Intel Knight's Landing CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, +@@ -34056,7 +34079,7 @@ on x86-64 processors in 64-bit environments. + Generate code for a 16-bit, 32-bit or 64-bit environment. + The @option{-m32} option sets @code{int}, @code{long}, and pointer types + to 32 bits, and +-generates code that runs on any i386 system. ++generates code that runs in 32-bit mode. + + The @option{-m64} option sets @code{int} to 32 bits and @code{long} and pointer + types to 64 bits, and generates code for the x86-64 architecture. --- a/src/gcc/doc/md.texi +++ b/src/gcc/doc/md.texi @@ -3535,6 +3535,15 @@ An address that is held in a general-purpose register. diff -Nru gcc-13-13.1.0/debian/patches/git-updates.diff gcc-13-13.1.0/debian/patches/git-updates.diff --- gcc-13-13.1.0/debian/patches/git-updates.diff 2023-05-12 10:37:40.000000000 +0000 +++ gcc-13-13.1.0/debian/patches/git-updates.diff 2023-07-11 08:28:24.000000000 +0000 @@ -1,7 +1,7 @@ -# DP: updates from the 13 branch upto 20230512 (7e0e213f3e9). +# DP: updates from the 13 branch upto 20230711 (7f6d8618024). LANG=C git diff --no-renames --src-prefix=a/src/ --dst-prefix=b/src/ \ - cc035c5d8672f87dc8c2756d9f8367903aa72d93 7e0e213f3e98939bfe3942194d5e8314fd3a0448 \ + cc035c5d8672f87dc8c2756d9f8367903aa72d93 7f6d86180247d75f3774e3b7c8f825e06270edc9 \ | awk '/^diff .*\.texi/ {skip=1; next} /^diff / { skip=0 } skip==0' \ | grep -v -E '^(diff|index)' @@ -20,7 +20,873 @@ * GCC 13.1.0 released. --- a/src/gcc/ChangeLog +++ b/src/gcc/ChangeLog -@@ -1,3 +1,174 @@ +@@ -1,3 +1,1040 @@ ++2023-07-10 Xi Ruoyao ++ ++ Backported from master: ++ 2023-07-10 Xi Ruoyao ++ ++ PR tree-optimization/110557 ++ * tree-vect-patterns.cc (vect_recog_bitfield_ref_pattern): ++ Ensure the output sign-extended if necessary. ++ ++2023-07-08 Jonathan Wakely ++ ++ PR c++/110595 ++ * doc/invoke.texi (Warning Options): Fix typo. ++ ++2023-07-07 Richard Biener ++ ++ Backported from master: ++ 2023-07-06 Richard Biener ++ ++ PR tree-optimization/110556 ++ * tree-ssa-tail-merge.cc (gimple_equal_p): Check ++ assign code and all operands of non-stores. ++ ++2023-07-07 Richard Biener ++ ++ Backported from master: ++ 2023-07-06 Richard Biener ++ ++ PR tree-optimization/110515 ++ * tree-ssa-pre.cc (compute_avail): Make code dealing ++ with hoisting loads with different alias-sets more ++ robust. ++ ++2023-07-07 Richard Biener ++ ++ Backported from master: ++ 2023-06-26 Richard Biener ++ ++ PR tree-optimization/110392 ++ * gimple-predicate-analysis.cc (uninit_analysis::is_use_guarded): ++ Do early exits on true/false predicate only after normalization. ++ ++2023-07-07 Richard Biener ++ ++ Backported from master: ++ 2023-06-26 Richard Biener ++ ++ PR tree-optimization/110381 ++ * tree-vect-slp.cc (vect_optimize_slp_pass::start_choosing_layouts): ++ Materialize permutes before fold-left reductions. ++ ++2023-07-07 Li Xu ++ ++ PR target/110560 ++ * config/riscv/riscv-vsetvl.cc (local_eliminate_vsetvl_insn): Fix bug. ++ ++2023-07-05 Michael Meissner ++ ++ Backported from master: ++ 2023-06-23 Michael Meissner ++ Aaron Sawdey ++ ++ PR target/105325 ++ * config/rs6000/genfusion.pl (gen_ld_cmpi_p10_one): Fix problems that ++ allowed prefixed lwa to be generated. ++ * config/rs6000/fusion.md: Regenerate. ++ * config/rs6000/predicates.md (ds_form_mem_operand): Delete. ++ * config/rs6000/rs6000.md (prefixed attribute): Add support for load ++ plus compare immediate fused insns. ++ (maybe_prefixed): Likewise. ++ ++2023-07-05 Segher Boessenkool ++ ++ Backported from master: ++ 2023-06-06 Segher Boessenkool ++ ++ * config/rs6000/genfusion.pl (gen_ld_cmpi_p10_one): New, rewritten and ++ split out from... ++ (gen_ld_cmpi_p10): ... this. ++ ++2023-07-05 Richard Biener ++ ++ Backported from master: ++ 2023-07-04 Richard Biener ++ ++ PR tree-optimization/110228 ++ * tree-ssa-ifcombine.cc (pass_tree_ifcombine::execute): ++ Mark SSA may-undefs. ++ (bb_no_side_effects_p): Check stmt uses for undefs. ++ ++2023-07-04 Lili Cui ++ ++ * config/i386/i386.h: Add PTA_ENQCMD and PTA_UINTR to PTA_SIERRAFOREST. ++ * doc/invoke.texi: Update new isa to march=sierraforest and grandridge. ++ ++2023-07-03 Eric Botcazou ++ ++ * gimple-fold.cc (fold_array_ctor_reference): Fix head comment. ++ (fold_nonarray_ctor_reference): Likewise. Specifically deal ++ with integral bit-fields. ++ (fold_ctor_reference): Make sure that the constructor uses the ++ native storage order. ++ ++2023-07-03 Iain Sandoe ++ ++ Backported from master: ++ 2023-07-02 Iain Sandoe ++ ++ PR target/108743 ++ * config/darwin.opt: Add fconstant-cfstrings alias to ++ mconstant-cfstrings. ++ * doc/invoke.texi: Amend invocation descriptions to reflect ++ that the fconstant-cfstrings is a target-option alias and to ++ add the missing mconstant-cfstrings option description to the ++ Darwin section. ++ ++2023-06-29 liuhongt ++ ++ PR rtl-optimization/110237 ++ * config/i386/sse.md (_store_mask): Refine with ++ UNSPEC_MASKMOV. ++ (maskstore_store_mask): New define_insn, it's renamed ++ from original _store_mask. ++ ++2023-06-29 liuhongt ++ ++ PR target/110309 ++ * config/i386/sse.md (maskload): ++ Refine pattern with UNSPEC_MASKLOAD. ++ (maskload): Ditto. ++ (*_load_mask): Extend mode iterator to ++ VI12HFBF_AVX512VL. ++ (*_load): Ditto. ++ ++2023-06-28 Hongyu Wang ++ ++ Backported from master: ++ 2023-06-26 Hongyu Wang ++ ++ * config/i386/i386-options.cc (ix86_valid_target_attribute_tree): ++ Override tune_string with arch_string if tune_string is not ++ explicitly specified. ++ ++2023-06-28 Thomas Schwinge ++ ++ Backported from master: ++ 2023-06-02 Thomas Schwinge ++ ++ PR testsuite/66005 ++ * doc/install.texi: Document (optional) Perl usage for parallel ++ testing of libgomp. ++ ++2023-06-28 liuhongt ++ ++ * config/i386/i386-features.cc (pass_insert_vzeroupper:gate): ++ Move flag_expensive_optimizations && !optimize_size to .. ++ * config/i386/i386-options.cc (ix86_option_override_internal): ++ .. this, it makes -mvzeroupper independent of optimization ++ level, but still keeps the behavior of architecture ++ tuning(emit_vzeroupper) unchanged. ++ ++2023-06-28 liuhongt ++ ++ * config/i386/i386.cc (ix86_invalid_conversion): New function. ++ (TARGET_INVALID_CONVERSION): Define as ++ ix86_invalid_conversion. ++ ++2023-06-27 Andrew Pinski ++ ++ Backported from master: ++ 2023-06-27 Andrew Pinski ++ ++ PR middle-end/110420 ++ PR middle-end/103979 ++ PR middle-end/98619 ++ * gimplify.cc (gimplify_asm_expr): Mark asm with labels as volatile. ++ ++2023-06-27 Martin Jambor ++ ++ Backported from master: ++ 2023-06-27 Martin Jambor ++ ++ PR ipa/110276 ++ * ipa-sra.cc (struct caller_issues): New field there_is_one. ++ (check_for_caller_issues): Set it. ++ (check_all_callers_for_issues): Check it. ++ ++2023-06-27 Juzhe-Zhong ++ ++ Backported from master: ++ 2023-06-16 Juzhe-Zhong ++ ++ PR target/110264 ++ * config/riscv/riscv-vsetvl.cc (insert_vsetvl): Fix bug. ++ ++2023-06-27 Andrew Pinski ++ ++ Backported from master: ++ 2023-06-27 Andrew Pinski ++ ++ * doc/extend.texi (__builtin_alloca_with_align_and_max): Fix ++ defbuiltin usage. ++ ++2023-06-23 Richard Biener ++ ++ Backported from master: ++ 2023-06-19 Richard Biener ++ ++ PR tree-optimization/110298 ++ * tree-ssa-loop-ivcanon.cc (tree_unroll_loops_completely): ++ Clear number of iterations info before cleaning up the CFG. ++ ++2023-06-23 Richard Biener ++ ++ Backported from master: ++ 2023-06-20 Richard Biener ++ ++ PR debug/110295 ++ * dwarf2out.cc (process_scope_var): Continue processing ++ the decl after setting a parent in case the existing DIE ++ was in limbo. ++ ++2023-06-23 Richard Biener ++ ++ Backported from master: ++ 2023-06-06 Richard Biener ++ ++ PR middle-end/110055 ++ * gimplify.cc (gimplify_target_expr): Do not emit ++ CLOBBERs for variables which have static storage duration ++ after gimplifying their initializers. ++ ++2023-06-23 Richard Biener ++ ++ Backported from master: ++ 2023-05-31 Richard Biener ++ ++ PR ipa/109983 ++ PR tree-optimization/109143 ++ * tree-ssa-structalias.cc (struct topo_info): Remove. ++ (init_topo_info): Likewise. ++ (free_topo_info): Likewise. ++ (compute_topo_order): Simplify API, put the component ++ with ESCAPED last so it's processed first. ++ (topo_visit): Adjust. ++ (solve_graph): Likewise. ++ ++2023-06-20 Alex Coplan ++ ++ Backported from master: ++ 2023-06-07 Alex Coplan ++ ++ PR target/110132 ++ * config/aarch64/aarch64-builtins.cc (aarch64_general_simulate_builtin): ++ New. Use it ... ++ (aarch64_init_ls64_builtins): ... here. Switch to declaring public ACLE ++ names for builtins. ++ (aarch64_general_init_builtins): Ensure we invoke the arm_acle.h ++ setup if in_lto_p, just like we do for SVE. ++ * config/aarch64/arm_acle.h: (__arm_ld64b): Delete. ++ (__arm_st64b): Delete. ++ (__arm_st64bv): Delete. ++ (__arm_st64bv0): Delete. ++ ++2023-06-20 Alex Coplan ++ ++ Backported from master: ++ 2023-06-07 Alex Coplan ++ ++ PR target/110100 ++ * config/aarch64/aarch64-builtins.cc (aarch64_expand_builtin_ls64): ++ Use input operand for the destination address. ++ * config/aarch64/aarch64.md (st64b): Fix constraint on address ++ operand. ++ ++2023-06-20 Alex Coplan ++ ++ Backported from master: ++ 2023-06-07 Alex Coplan ++ ++ PR target/110100 ++ * config/aarch64/aarch64-builtins.cc (aarch64_init_ls64_builtins_types): ++ Replace eight consecutive spaces with tabs. ++ (aarch64_init_ls64_builtins): Likewise. ++ (aarch64_expand_builtin_ls64): Likewise. ++ * config/aarch64/aarch64.md (ld64b): Likewise. ++ (st64b): Likewise. ++ (st64bv): Likewise ++ (st64bv0): Likewise. ++ ++2023-06-20 Kewen Lin ++ ++ Backported from master: ++ 2023-06-12 Kewen Lin ++ ++ PR target/109932 ++ * config/rs6000/rs6000-builtins.def (__builtin_pack_vector_int128, ++ __builtin_unpack_vector_int128): Move from stanza power7 to vsx. ++ ++2023-06-20 Kewen Lin ++ ++ Backported from master: ++ 2023-06-12 Kewen Lin ++ ++ PR target/110011 ++ * config/rs6000/rs6000.cc (output_toc): Use the mode of the 128-bit ++ floating constant itself for real_to_target call. ++ ++2023-06-16 Vladimir N. Makarov ++ ++ * ira-costs.cc: (find_costs_and_classes): Constrain classes of pic ++ offset table pseudo to a general reg subset. ++ ++2023-06-15 Lulu Cheng ++ ++ Backported from master: ++ 2023-06-15 Lulu Cheng ++ Andrew Pinski ++ ++ PR target/110136 ++ * config/loongarch/loongarch.md: Modify the register constraints for template ++ "jumptable" and "indirect_jump" from "r" to "e". ++ ++2023-06-14 Jakub Jelinek ++ ++ Backported from master: ++ 2023-06-13 Jakub Jelinek ++ ++ * config/i386/i386.cc (standard_sse_constant_opcode): Remove ++ superfluous spaces around \t for vpcmpeqd. ++ ++2023-06-14 liuhongt ++ ++ PR target/110227 ++ * config/i386/sse.md (mov_internal>): Use x instead of v ++ for alternative 2 since there's no evex version for vpcmpeqd ++ ymm, ymm, ymm. ++ ++2023-06-13 Richard Biener ++ ++ Backported from master: ++ 2023-06-13 Richard Biener ++ ++ * tree-ssa-alias.cc (ref_maybe_used_by_call_p_1): For ++ .MASK_LOAD and friends set the size of the access to unknown. ++ ++2023-06-13 Richard Biener ++ ++ Backported from master: ++ 2023-06-12 Richard Biener ++ ++ * tree-ssa-alias.cc (call_may_clobber_ref_p_1): For ++ .MASK_STORE and friend set the size of the access to ++ unknown. ++ ++2023-06-13 Alexandre Oliva ++ ++ Backported from master: ++ 2023-06-13 Alexandre Oliva ++ ++ * range-op-float.cc (frange_nextafter): Drop inline. ++ (frelop_early_resolve): Add static. ++ (frange_float): Likewise. ++ ++2023-06-12 Richard Biener ++ ++ Backported from master: ++ 2023-06-12 Richard Biener ++ ++ PR middle-end/110200 ++ * genmatch.cc (expr::gen_transform): Put braces around ++ the if arm for the (convert ...) short-cut. ++ ++2023-06-10 Georg-Johann Lay ++ ++ PR target/109650 ++ PR target/92729 ++ Backport from 2023-05-10 master r14-1688. ++ * config/avr/avr-passes.def (avr_pass_ifelse): Insert new pass. ++ * config/avr/avr.cc (avr_pass_ifelse): New RTL pass. ++ (avr_pass_data_ifelse): New pass_data for it. ++ (make_avr_pass_ifelse, avr_redundant_compare, avr_cbranch_cost) ++ (avr_canonicalize_comparison, avr_out_plus_set_ZN) ++ (avr_out_cmp_ext): New functions. ++ (compare_condtition): Make sure REG_CC dies in the branch insn. ++ (avr_rtx_costs_1): Add computation of cbranch costs. ++ (avr_adjust_insn_length) [ADJUST_LEN_ADD_SET_ZN, ADJUST_LEN_CMP_ZEXT]: ++ [ADJUST_LEN_CMP_SEXT]Handle them. ++ (TARGET_CANONICALIZE_COMPARISON): New define. ++ (avr_simplify_comparison_p, compare_diff_p, avr_compare_pattern) ++ (avr_reorg_remove_redundant_compare, avr_reorg): Remove functions. ++ (TARGET_MACHINE_DEPENDENT_REORG): Remove define. ++ * config/avr/avr-protos.h (avr_simplify_comparison_p): Remove proto. ++ (make_avr_pass_ifelse, avr_out_plus_set_ZN, cc_reg_rtx) ++ (avr_out_cmp_zext): New Protos ++ * config/avr/avr.md (branch, difficult_branch): Don't split insns. ++ (*cbranchhi.zero-extend.0", *cbranchhi.zero-extend.1") ++ (*swapped_tst, *add.for.eqne.): New insns. ++ (*cbranch4): Rename to cbranch4_insn. ++ (define_peephole): Add dead_or_set_regno_p(insn,REG_CC) as needed. ++ (define_deephole2): Add peep2_regno_dead_p(*,REG_CC) as needed. ++ Add new RTL peepholes for decrement-and-branch and *swapped_tst. ++ Rework signtest-and-branch peepholes for *sbrx_branch. ++ (adjust_len) [add_set_ZN, cmp_zext]: New. ++ (QIPSI): New mode iterator. ++ (ALLs1, ALLs2, ALLs4, ALLs234): New mode iterators. ++ (gelt): New code iterator. ++ (gelt_eqne): New code attribute. ++ (rvbranch, *rvbranch, difficult_rvbranch, *difficult_rvbranch) ++ (branch_unspec, *negated_tst, *reversed_tst) ++ (*cmpqi_sign_extend): Remove insns. ++ (define_c_enum "unspec") [UNSPEC_IDENTITY]: Remove. ++ * config/avr/avr-dimode.md (cbranch4): Canonicalize comparisons. ++ * config/avr/predicates.md (scratch_or_d_register_operand): New. ++ * config/avr/constraints.md (Yxx): New constraint. ++ ++2023-06-09 Andrew Pinski ++ ++ Backported from master: ++ 2023-06-09 Andrew Pinski ++ ++ PR tree-optimization/110165 ++ PR tree-optimization/110166 ++ * match.pd (zero_one_valued_p): Don't accept ++ signed 1-bit integers. ++ ++2023-06-09 Richard Biener ++ ++ Backported from master: ++ 2023-06-09 Richard Biener ++ ++ * match.pd (two conversions in a row): Use element_precision ++ to DTRT for VECTOR_TYPE. ++ ++2023-06-09 Iain Sandoe ++ ++ Backported from master: ++ 2023-06-02 Iain Sandoe ++ ++ PR target/110044 ++ * config/rs6000/rs6000.cc (darwin_rs6000_special_round_type_align): ++ Make sure that we do not have a cap on field alignment before altering ++ the struct layout based on the type alignment of the first entry. ++ ++2023-06-09 liuhongt ++ ++ PR target/110108 ++ * config/i386/i386.cc (ix86_gimple_fold_builtin): Explicitly ++ view_convert_expr mask to signed type when folding pblendvb ++ builtins. ++ ++2023-06-08 Kyrylo Tkachov ++ ++ Backported from master: ++ 2023-05-24 Kyrylo Tkachov ++ ++ PR target/109939 ++ * config/arm/arm-builtins.cc (SAT_BINOP_UNSIGNED_IMM_QUALIFIERS): Use ++ qualifier_none for the return operand. ++ ++2023-06-07 Jeevitha Palanisamy ++ ++ Backported from master: ++ 2023-06-06 Jeevitha Palanisamy ++ ++ PR target/106907 ++ * config/rs6000/rs6000.cc (vec_const_128bit_to_bytes): Remove ++ duplicate expression. ++ ++2023-06-07 Alex Coplan ++ ++ Backported from master: ++ 2023-05-25 Alex Coplan ++ ++ PR target/109800 ++ * config/arm/arm.md (movdf): Generate temporary pseudo in DImode ++ instead of DFmode. ++ * config/arm/vfp.md (no_literal_pool_df_immediate): Rather than punning an ++ lvalue DFmode pseudo into DImode, use a DImode pseudo and pun it into ++ DFmode as an rvalue. ++ ++2023-06-06 Andrew Pinski ++ ++ Backported from master: ++ 2023-06-05 Andrew Pinski ++ ++ PR bootstrap/110085 ++ * Makefile.in (clean): Remove the removing of ++ MULTILIB_DIR/MULTILIB_OPTIONS directories. ++ ++2023-06-02 Georg-Johann Lay ++ ++ PR target/110088 ++ * config/avr/avr.md: Add an RTL peephole to optimize operations on ++ non-LD_REGS after a move from LD_REGS. ++ (piaop): New code iterator. ++ ++2023-06-01 Jonathan Wakely ++ ++ Backported from master: ++ 2023-06-01 Jonathan Wakely ++ ++ PR target/109954 ++ * doc/invoke.texi (x86 Options): Fix description of -m32 option. ++ ++2023-05-30 Andreas Schwab ++ ++ PR target/110036 ++ * config/riscv/riscv.cc (riscv_asan_shadow_offset): Update to ++ match libsanitizer. ++ ++2023-05-29 Juzhe-Zhong ++ ++ Backported from master: ++ 2023-04-21 Juzhe-Zhong ++ ++ PR target/109547 ++ * config/riscv/riscv-vsetvl.cc (local_eliminate_vsetvl_insn): New function. ++ (vector_insn_info::skip_avl_compatible_p): Ditto. ++ (vector_insn_info::merge): Remove default value. ++ (pass_vsetvl::compute_local_backward_infos): Ditto. ++ (pass_vsetvl::cleanup_insns): Add local vsetvl elimination. ++ * config/riscv/riscv-vsetvl.h: Ditto. ++ ++2023-05-29 Kito Cheng ++ ++ Backported from master: ++ 2023-05-16 Kito Cheng ++ ++ * common/config/riscv/riscv-common.cc (riscv_compute_multilib): ++ Fix wrong select_kind... ++ ++2023-05-29 Kito Cheng ++ ++ Backported from master: ++ 2023-05-12 Kito Cheng ++ ++ * common/config/riscv/riscv-common.cc (riscv_select_multilib_by_abi): ++ Drop unused parameter. ++ (riscv_select_multilib): Ditto. ++ (riscv_compute_multilib): Update call site of ++ riscv_select_multilib_by_abi and riscv_select_multilib_by_abi. ++ ++2023-05-29 Kito Cheng ++ ++ Backported from master: ++ 2023-05-08 Kito Cheng ++ ++ * common/config/riscv/riscv-common.cc (riscv_select_multilib_by_abi): New. ++ (riscv_select_multilib): New. ++ (riscv_compute_multilib): Extract logic to riscv_select_multilib and ++ also handle select_by_abi. ++ * config/riscv/elf.h (RISCV_USE_CUSTOMISED_MULTI_LIB): Change it ++ to select_by_abi_arch_cmodel from 1. ++ * config/riscv/linux.h (RISCV_USE_CUSTOMISED_MULTI_LIB): Define. ++ * config/riscv/riscv-opts.h (enum riscv_multilib_select_kind): New. ++ ++2023-05-29 Juzhe-Zhong ++ ++ Backported from master: ++ 2023-05-29 Juzhe-Zhong ++ ++ * config/riscv/vector.md: Fix vimuladd instruction bug. ++ ++2023-05-25 Georg-Johann Lay ++ ++ PR target/104327 ++ * config/avr/avr.cc (avr_can_inline_p): New static function. ++ (TARGET_CAN_INLINE_P): Define to that function. ++ ++2023-05-25 Georg-Johann Lay ++ ++ PR target/82931 ++ * config/avr/avr.md (*movbitqi.0): Rename to *movbit.0-6. ++ Handle any bit position and use mode QISI. ++ * config/avr/avr.cc (avr_rtx_costs_1) [IOR]: Return a cost ++ of 2 insns for bit-transfer of respective style. ++ ++2023-05-23 Georg-Johann Lay ++ ++ * config/avr/avr.cc (avr_insn_cost): New static function. ++ (TARGET_INSN_COST): Define to that function. ++ ++2023-05-23 Eric Botcazou ++ ++ * fold-const.cc (native_encode_initializer) : Apply the ++ specific treatment for bit-fields only if they have an integral type ++ and filter out non-integral bit-fields that do not start and end on ++ a byte boundary. ++ ++2023-05-22 Jakub Jelinek ++ ++ Backported from master: ++ 2023-05-21 Jakub Jelinek ++ ++ PR tree-optimization/109505 ++ * match.pd ((x | CST1) & CST2 -> (x & CST2) | (CST1 & CST2), ++ Combine successive equal operations with constants, ++ (A +- CST1) +- CST2 -> A + CST3, (CST1 - A) +- CST2 -> CST3 - A, ++ CST1 - (CST2 - A) -> CST3 + A): Use ! on ops with 2 CONSTANT_CLASS_P ++ operands. ++ ++2023-05-22 Kewen Lin ++ ++ Backported from master: ++ 2023-05-17 Kewen Lin ++ ++ * tree-vect-loop.cc (vect_analyze_loop_1): Don't retry analysis with ++ suggested unroll factor once the previous analysis fails. ++ ++2023-05-20 Triffid Hunter ++ ++ PR target/105753 ++ Backport from 2023-05-20 https://gcc.gnu.org/r14-1016 ++ * config/avr/avr.md (divmodpsi, udivmodpsi, divmodsi, udivmodsi): ++ Remove superfluous "parallel" in insn pattern. ++ ([u]divmod4): Tidy code. Use gcc_unreachable() instead of ++ printing error text to assembly. ++ ++2023-05-19 Andreas Schwab ++ ++ * config/riscv/linux.h (LIB_SPEC): Don't redefine. ++ ++2023-05-18 Stam Markianos-Wright ++ ++ * config/arm/arm_mve.h: (__ARM_mve_typeid): Add more pointer types. ++ (__ARM_mve_coerce1): Remove. ++ (__ARM_mve_coerce2): Remove. ++ (__ARM_mve_coerce3): Remove. ++ (__ARM_mve_coerce_i_scalar): New. ++ (__ARM_mve_coerce_s8_ptr): New. ++ (__ARM_mve_coerce_u8_ptr): New. ++ (__ARM_mve_coerce_s16_ptr): New. ++ (__ARM_mve_coerce_u16_ptr): New. ++ (__ARM_mve_coerce_s32_ptr): New. ++ (__ARM_mve_coerce_u32_ptr): New. ++ (__ARM_mve_coerce_s64_ptr): New. ++ (__ARM_mve_coerce_u64_ptr): New. ++ (__ARM_mve_coerce_f_scalar): New. ++ (__ARM_mve_coerce_f16_ptr): New. ++ (__ARM_mve_coerce_f32_ptr): New. ++ (__arm_vst4q): Change _coerce_ overloads. ++ (__arm_vbicq): Change _coerce_ overloads. ++ (__arm_vmulq): Change _coerce_ overloads. ++ (__arm_vcmpeqq): Change _coerce_ overloads. ++ (__arm_vcmpneq): Change _coerce_ overloads. ++ (__arm_vmaxnmavq): Change _coerce_ overloads. ++ (__arm_vmaxnmvq): Change _coerce_ overloads. ++ (__arm_vminnmavq): Change _coerce_ overloads. ++ (__arm_vsubq): Change _coerce_ overloads. ++ (__arm_vminnmvq): Change _coerce_ overloads. ++ (__arm_vrshlq): Change _coerce_ overloads. ++ (__arm_vqsubq): Change _coerce_ overloads. ++ (__arm_vqdmulltq): Change _coerce_ overloads. ++ (__arm_vqdmullbq): Change _coerce_ overloads. ++ (__arm_vqdmulhq): Change _coerce_ overloads. ++ (__arm_vqaddq): Change _coerce_ overloads. ++ (__arm_vhaddq): Change _coerce_ overloads. ++ (__arm_vhsubq): Change _coerce_ overloads. ++ (__arm_vqdmlashq): Change _coerce_ overloads. ++ (__arm_vqrdmlahq): Change _coerce_ overloads. ++ (__arm_vmlasq): Change _coerce_ overloads. ++ (__arm_vqdmlahq): Change _coerce_ overloads. ++ (__arm_vmaxnmavq_p): Change _coerce_ overloads. ++ (__arm_vmaxnmvq_p): Change _coerce_ overloads. ++ (__arm_vminnmavq_p): Change _coerce_ overloads. ++ (__arm_vminnmvq_p): Change _coerce_ overloads. ++ (__arm_vfmasq_m): Change _coerce_ overloads. ++ (__arm_vld1q): Change _coerce_ overloads. ++ (__arm_vld1q_z): Change _coerce_ overloads. ++ (__arm_vld2q): Change _coerce_ overloads. ++ (__arm_vld4q): Change _coerce_ overloads. ++ (__arm_vldrhq_gather_offset): Change _coerce_ overloads. ++ (__arm_vldrhq_gather_offset_z): Change _coerce_ overloads. ++ (__arm_vldrhq_gather_shifted_offset): Change _coerce_ overloads. ++ (__arm_vldrhq_gather_shifted_offset_z): Change _coerce_ overloads. ++ (__arm_vldrwq_gather_offset): Change _coerce_ overloads. ++ (__arm_vldrwq_gather_offset_z): Change _coerce_ overloads. ++ (__arm_vldrwq_gather_shifted_offset): Change _coerce_ overloads. ++ (__arm_vldrwq_gather_shifted_offset_z): Change _coerce_ overloads. ++ (__arm_vst1q_p): Change _coerce_ overloads. ++ (__arm_vst2q): Change _coerce_ overloads. ++ (__arm_vst1q): Change _coerce_ overloads. ++ (__arm_vstrhq): Change _coerce_ overloads. ++ (__arm_vstrhq_p): Change _coerce_ overloads. ++ (__arm_vstrhq_scatter_offset_p): Change _coerce_ overloads. ++ (__arm_vstrhq_scatter_offset): Change _coerce_ overloads. ++ (__arm_vstrhq_scatter_shifted_offset_p): Change _coerce_ overloads. ++ (__arm_vstrhq_scatter_shifted_offset): Change _coerce_ overloads. ++ (__arm_vstrwq_p): Change _coerce_ overloads. ++ (__arm_vstrwq): Change _coerce_ overloads. ++ (__arm_vstrwq_scatter_offset): Change _coerce_ overloads. ++ (__arm_vstrwq_scatter_offset_p): Change _coerce_ overloads. ++ (__arm_vstrwq_scatter_shifted_offset): Change _coerce_ overloads. ++ (__arm_vstrwq_scatter_shifted_offset_p): Change _coerce_ overloads. ++ (__arm_vsetq_lane): Change _coerce_ overloads. ++ (__arm_vcmpneq_m): Change _coerce_ overloads. ++ (__arm_vldrbq_gather_offset): Change _coerce_ overloads. ++ (__arm_vdwdupq_x_u8): Change _coerce_ overloads. ++ (__arm_vdwdupq_x_u16): Change _coerce_ overloads. ++ (__arm_vdwdupq_x_u32): Change _coerce_ overloads. ++ (__arm_viwdupq_x_u8): Change _coerce_ overloads. ++ (__arm_viwdupq_x_u16): Change _coerce_ overloads. ++ (__arm_viwdupq_x_u32): Change _coerce_ overloads. ++ (__arm_vidupq_x_u8): Change _coerce_ overloads. ++ (__arm_vddupq_x_u8): Change _coerce_ overloads. ++ (__arm_vidupq_x_u16): Change _coerce_ overloads. ++ (__arm_vddupq_x_u16): Change _coerce_ overloads. ++ (__arm_vidupq_x_u32): Change _coerce_ overloads. ++ (__arm_vddupq_x_u32): Change _coerce_ overloads. ++ (__arm_vhaddq_x): Change _coerce_ overloads. ++ (__arm_vhsubq_x): Change _coerce_ overloads. ++ (__arm_vldrdq_gather_offset): Change _coerce_ overloads. ++ (__arm_vldrdq_gather_offset_z): Change _coerce_ overloads. ++ (__arm_vldrdq_gather_shifted_offset): Change _coerce_ overloads. ++ (__arm_vldrdq_gather_shifted_offset_z): Change _coerce_ overloads. ++ (__arm_vldrbq_gather_offset_z): Change _coerce_ overloads. ++ (__arm_vqrdmlahq_m): Change _coerce_ overloads. ++ (__arm_vqrdmlashq_m): Change _coerce_ overloads. ++ (__arm_vqdmlashq_m): Change _coerce_ overloads. ++ (__arm_vmlaldavaxq_p): Change _coerce_ overloads. ++ (__arm_vmlasq_m): Change _coerce_ overloads. ++ (__arm_vqdmulhq_m): Change _coerce_ overloads. ++ (__arm_vqdmulltq_m): Change _coerce_ overloads. ++ (__arm_vidupq_u16): Change _coerce_ overloads. ++ (__arm_vidupq_u32): Change _coerce_ overloads. ++ (__arm_vidupq_u8): Change _coerce_ overloads. ++ (__arm_vddupq_u16): Change _coerce_ overloads. ++ (__arm_vddupq_u32): Change _coerce_ overloads. ++ (__arm_vddupq_u8): Change _coerce_ overloads. ++ (__arm_viwdupq_m): Change _coerce_ overloads. ++ (__arm_viwdupq_u16): Change _coerce_ overloads. ++ (__arm_viwdupq_u32): Change _coerce_ overloads. ++ (__arm_viwdupq_u8): Change _coerce_ overloads. ++ (__arm_vdwdupq_m): Change _coerce_ overloads. ++ (__arm_vdwdupq_u16): Change _coerce_ overloads. ++ (__arm_vdwdupq_u32): Change _coerce_ overloads. ++ (__arm_vdwdupq_u8): Change _coerce_ overloads. ++ (__arm_vaddlvaq): Change _coerce_ overloads. ++ (__arm_vaddlvaq_p): Change _coerce_ overloads. ++ (__arm_vaddvaq): Change _coerce_ overloads. ++ (__arm_vaddvaq_p): Change _coerce_ overloads. ++ (__arm_vcmphiq_m): Change _coerce_ overloads. ++ (__arm_vmladavaq_p): Change _coerce_ overloads. ++ (__arm_vmladavaxq): Change _coerce_ overloads. ++ (__arm_vmlaldavaxq): Change _coerce_ overloads. ++ (__arm_vstrbq): Change _coerce_ overloads. ++ (__arm_vstrbq_p): Change _coerce_ overloads. ++ (__arm_vrmlaldavhaq_p): Change _coerce_ overloads. ++ (__arm_vstrbq_scatter_offset): Change _coerce_ overloads. ++ (__arm_vstrbq_scatter_offset_p): Change _coerce_ overloads. ++ (__arm_vstrdq_scatter_offset_p): Change _coerce_ overloads. ++ (__arm_vstrdq_scatter_offset): Change _coerce_ overloads. ++ (__arm_vstrdq_scatter_shifted_offset_p): Change _coerce_ overloads. ++ (__arm_vstrdq_scatter_shifted_offset): Change _coerce_ overloads. ++ ++2023-05-18 Stam Markianos-Wright ++ ++ * config/arm/arm_mve.h (__arm_vbicq): Change coerce on ++ scalar constant. ++ (__arm_vmvnq_m): Likewise. ++ ++2023-05-18 Stam Markianos-Wright ++ ++ * config/arm/arm_mve.h (__arm_vorrq): Add _n variant. ++ ++2023-05-18 Stam Markianos-Wright ++ ++ * config/arm/arm_mve.h (__arm_vadcq_s32): Fix arithmetic. ++ (__arm_vadcq_u32): Likewise. ++ (__arm_vadcq_m_s32): Likewise. ++ (__arm_vadcq_m_u32): Likewise. ++ (__arm_vsbcq_s32): Likewise. ++ (__arm_vsbcq_u32): Likewise. ++ (__arm_vsbcq_m_s32): Likewise. ++ (__arm_vsbcq_m_u32): Likewise. ++ * config/arm/mve.md (get_fpscr_nzcvqc): Make unspec_volatile. ++ ++2023-05-18 Andrea Corallo ++ ++ * config/arm/mve.md (mve_vrndq_m_f, mve_vrev64q_f) ++ (mve_vrev32q_fv8hf, mve_vcvttq_f32_f16v4sf) ++ (mve_vcvtbq_f32_f16v4sf, mve_vcvtq_to_f_) ++ (mve_vrev64q_, mve_vcvtq_from_f_) ++ (mve_vmovltq_, mve_vmovlbq_) ++ (mve_vcvtpq_, mve_vcvtnq_) ++ (mve_vcvtmq_, mve_vcvtaq_) ++ (mve_vmvnq_n_, mve_vrev16q_v16qi) ++ (mve_vctpq, mve_vbrsrq_n_f) ++ (mve_vbrsrq_n_, mve_vandq_f, mve_vbicq_f) ++ (mve_vbicq_n_, mve_vctpq_m) ++ (mve_vcvtbq_f16_f32v8hf, mve_vcvttq_f16_f32v8hf) ++ (mve_veorq_f, mve_vmlaldavxq_s, mve_vmlsldavq_s) ++ (mve_vmlsldavxq_s, mve_vornq_f, mve_vorrq_f) ++ (mve_vrmlaldavhxq_sv4si, mve_vbicq_m_n_) ++ (mve_vcvtq_m_to_f_, mve_vshlcq_) ++ (mve_vmvnq_m_, mve_vpselq_) ++ (mve_vcvtbq_m_f16_f32v8hf, mve_vcvtbq_m_f32_f16v4sf) ++ (mve_vcvttq_m_f16_f32v8hf, mve_vcvttq_m_f32_f16v4sf) ++ (mve_vmlaldavq_p_, mve_vmlsldavaq_s) ++ (mve_vmlsldavaxq_s, mve_vmlsldavq_p_s) ++ (mve_vmlsldavxq_p_s, mve_vmvnq_m_n_) ++ (mve_vorrq_m_n_, mve_vpselq_f) ++ (mve_vrev32q_m_fv8hf, mve_vrev32q_m_) ++ (mve_vrev64q_m_f, mve_vrmlaldavhaxq_sv4si) ++ (mve_vrmlaldavhxq_p_sv4si, mve_vrmlsldavhaxq_sv4si) ++ (mve_vrmlsldavhq_p_sv4si, mve_vrmlsldavhxq_p_sv4si) ++ (mve_vrev16q_m_v16qi, mve_vrmlaldavhq_p_v4si) ++ (mve_vrmlsldavhaq_sv4si, mve_vandq_m_) ++ (mve_vbicq_m_, mve_veorq_m_) ++ (mve_vornq_m_, mve_vorrq_m_) ++ (mve_vandq_m_f, mve_vbicq_m_f, mve_veorq_m_f) ++ (mve_vornq_m_f, mve_vorrq_m_f) ++ (mve_vstrdq_scatter_shifted_offset_p_v2di_insn) ++ (mve_vstrdq_scatter_shifted_offset_v2di_insn) ++ (mve_vstrdq_scatter_base_wb_p_v2di) : Fix spacing and ++ capitalization in the emitted asm. ++ ++2023-05-18 Andrea Corallo ++ ++ * config/arm/constraints.md (mve_vldrd_immediate): Move it to ++ predicates.md. ++ (Ri): Move constraint definition from predicates.md. ++ (Rl): Define new constraint. ++ * config/arm/mve.md (mve_vstrwq_scatter_base_wb_p_v4si): Add ++ missing constraint. ++ (mve_vstrwq_scatter_base_wb_p_fv4sf): Add missing Up constraint ++ for op 1, use mve_vstrw_immediate predicate and Rl constraint for ++ op 2. Fix asm output spacing. ++ (mve_vstrdq_scatter_base_wb_p_v2di): Add missing constraint. ++ * config/arm/predicates.md (Ri) Move constraint to constraints.md ++ (mve_vldrd_immediate): Move it from ++ constraints.md. ++ (mve_vstrw_immediate): New predicate. ++ ++2023-05-17 Jakub Jelinek ++ ++ Backported from master: ++ 2023-05-17 Jakub Jelinek ++ ++ PR c++/109884 ++ * config/i386/i386-builtin-types.def (FLOAT128): Use ++ float128t_type_node rather than float128_type_node. ++ ++2023-05-16 Patrick O'Neill ++ ++ PR target/104338 ++ * config/riscv/riscv-protos.h: Add helper function stubs. ++ * config/riscv/riscv.cc: Add helper functions for subword masking. ++ * config/riscv/riscv.opt: Add command-line flags ++ -minline-atomics and -mno-inline-atomics. ++ * config/riscv/sync.md: Add masking logic and inline asm for ++ fetch_and_op, fetch_and_nand, CAS, and exchange ops. ++ * doc/invoke.texi: Add blurb regarding new command-line flags ++ -minline-atomics and -mno-inline-atomics. ++ ++2023-05-16 Tobias Burnus ++ ++ Backported from master: ++ 2023-05-12 Tobias Burnus ++ ++ PR libstdc++/109816 ++ * lto-cgraph.cc (output_symtab): Guard lto_output_toplevel_asms by ++ '!lto_stream_offload_p'. ++ +2023-05-11 Richard Sandiford + + PR target/109661 @@ -199,7 +1065,186 @@ +++ b/src/gcc/DATESTAMP @@ -1 +1 @@ -20230426 -+20230512 ++20230711 +--- a/src/gcc/Makefile.in ++++ b/src/gcc/Makefile.in +@@ -3585,13 +3585,6 @@ clean: mostlyclean lang.clean + -rm -f doc/*.pdf + # Delete the include directories. + -rm -rf include include-fixed +-# Delete files used by the "multilib" facility (including libgcc subdirs). +- -rm -f multilib.h tmpmultilib* +- -if [ "x$(MULTILIB_DIRNAMES)" != x ] ; then \ +- rm -rf $(MULTILIB_DIRNAMES); \ +- else if [ "x$(MULTILIB_OPTIONS)" != x ] ; then \ +- rm -rf `echo $(MULTILIB_OPTIONS) | sed -e 's/\// /g'`; \ +- fi ; fi + + # Delete all files that users would normally create + # while building and installing GCC. +--- a/src/gcc/ada/ChangeLog ++++ b/src/gcc/ada/ChangeLog +@@ -1,3 +1,32 @@ ++2023-07-07 Viljar Indus ++ ++ * exp_aggr.adb (Expand_N_Aggregate): Ensure that container ++ aggregate expressions do not get expanded as records but instead ++ as container aggregates. ++ ++2023-07-07 Eric Botcazou ++ ++ * exp_aggr.adb (Convert_To_Assignments): Tweak comment. ++ (Expand_Array_Aggregate): Do not delay the expansion if the parent ++ node is a container aggregate. ++ ++2023-07-07 Marc Poulhiès ++ ++ * exp_aggr.adb (Convert_To_Assignments): Do not mark node for ++ delayed expansion if parent type has the Aggregate aspect. ++ * sem_util.adb (Is_Container_Aggregate): Move... ++ * sem_util.ads (Is_Container_Aggregate): ... here and make it ++ public. ++ ++2023-06-15 Eric Botcazou ++ ++ * sinfo.ads (Iterator_Filter): Document field. ++ * sem_ch5.adb (Analyze_Iterator_Specification): Move comment around. ++ (Analyze_Loop_Parameter_Specification): Only preanalyze the iterator ++ filter, if any. ++ * exp_ch5.adb (Expand_N_Loop_Statement): Analyze the new list built ++ when an iterator filter is present. ++ + 2023-04-26 Release Manager + + * GCC 13.1.0 released. +--- a/src/gcc/ada/exp_aggr.adb ++++ b/src/gcc/ada/exp_aggr.adb +@@ -5016,10 +5016,13 @@ package body Exp_Aggr is + -- done top down from above. + + if +- -- Internal aggregate (transformed when expanding the parent) ++ -- Internal aggregates (transformed when expanding the parent), ++ -- excluding container aggregates as these are transformed into ++ -- subprogram calls later. + +- Parent_Kind in +- N_Aggregate | N_Extension_Aggregate | N_Component_Association ++ (Parent_Kind in ++ N_Component_Association | N_Aggregate | N_Extension_Aggregate ++ and then not Is_Container_Aggregate (Parent_Node)) + + -- Allocator (see Convert_Aggr_In_Allocator) + +@@ -6886,7 +6889,8 @@ package body Exp_Aggr is + -- STEP 3 + + -- Delay expansion for nested aggregates: it will be taken care of when +- -- the parent aggregate is expanded. ++ -- the parent aggregate is expanded, excluding container aggregates as ++ -- these are transformed into subprogram calls later. + + Parent_Node := Parent (N); + Parent_Kind := Nkind (Parent_Node); +@@ -6896,9 +6900,10 @@ package body Exp_Aggr is + Parent_Kind := Nkind (Parent_Node); + end if; + +- if Parent_Kind = N_Aggregate +- or else Parent_Kind = N_Extension_Aggregate +- or else Parent_Kind = N_Component_Association ++ if ((Parent_Kind = N_Component_Association ++ or else Parent_Kind = N_Aggregate ++ or else Parent_Kind = N_Extension_Aggregate) ++ and then not Is_Container_Aggregate (Parent_Node)) + or else (Parent_Kind = N_Object_Declaration + and then (Needs_Finalization (Typ) + or else Is_Special_Return_Object +@@ -7231,6 +7236,7 @@ package body Exp_Aggr is + + if Is_Record_Type (T) + and then not Is_Private_Type (T) ++ and then not Is_Homogeneous_Aggregate (N) + then + Expand_Record_Aggregate (N); + +--- a/src/gcc/ada/exp_ch5.adb ++++ b/src/gcc/ada/exp_ch5.adb +@@ -5610,6 +5610,7 @@ package body Exp_Ch5 is + New_List (Make_If_Statement (Loc, + Condition => Iterator_Filter (LPS), + Then_Statements => Stats))); ++ Analyze_List (Statements (N)); + end if; + + -- Deal with loop over predicates +--- a/src/gcc/ada/sem_ch5.adb ++++ b/src/gcc/ada/sem_ch5.adb +@@ -2853,10 +2853,10 @@ package body Sem_Ch5 is + end if; + end if; + +- if Present (Iterator_Filter (N)) then +- -- Preanalyze the filter. Expansion will take place when enclosing +- -- loop is expanded. ++ -- Preanalyze the filter. Expansion will take place when enclosing ++ -- loop is expanded. + ++ if Present (Iterator_Filter (N)) then + Preanalyze_And_Resolve (Iterator_Filter (N), Standard_Boolean); + end if; + end Analyze_Iterator_Specification; +@@ -3570,8 +3570,11 @@ package body Sem_Ch5 is + end; + end if; + ++ -- Preanalyze the filter. Expansion will take place when enclosing ++ -- loop is expanded. ++ + if Present (Iterator_Filter (N)) then +- Analyze_And_Resolve (Iterator_Filter (N), Standard_Boolean); ++ Preanalyze_And_Resolve (Iterator_Filter (N), Standard_Boolean); + end if; + + -- A loop parameter cannot be effectively volatile (SPARK RM 7.1.3(4)). +--- a/src/gcc/ada/sem_util.adb ++++ b/src/gcc/ada/sem_util.adb +@@ -132,9 +132,6 @@ package body Sem_Util is + -- Determine whether arbitrary entity Id denotes an atomic object as per + -- RM C.6(7). + +- function Is_Container_Aggregate (Exp : Node_Id) return Boolean; +- -- Is the given expression a container aggregate? +- + generic + with function Is_Effectively_Volatile_Entity + (Id : Entity_Id) return Boolean; +--- a/src/gcc/ada/sem_util.ads ++++ b/src/gcc/ada/sem_util.ads +@@ -1474,6 +1474,9 @@ package Sem_Util is + -- Return True if the loop has no side effect and can therefore be + -- marked for removal. Return False if N is not a N_Loop_Statement. + ++ function Is_Container_Aggregate (Exp : Node_Id) return Boolean; ++ -- Is the given expression a container aggregate? ++ + function Is_Newly_Constructed + (Exp : Node_Id; Context_Requires_NC : Boolean) return Boolean; + -- Indicates whether a given expression is "newly constructed" (RM 4.4). +--- a/src/gcc/ada/sinfo.ads ++++ b/src/gcc/ada/sinfo.ads +@@ -1899,6 +1899,11 @@ package Sinfo is + -- Present in variable reference markers. Set when the original variable + -- reference constitutes a write of the variable. + ++ -- Iterator_Filter ++ -- Present in N_Loop_Parameter_Specification and N_Iterator_Specification ++ -- nodes for Ada 2022. It is used to store the condition present in the ++ -- eponymous Ada 2022 construct. ++ + -- Itype + -- Used in N_Itype_Reference node to reference an itype for which it is + -- important to ensure that it is defined. See description of this node --- a/src/gcc/attr-fnspec.h +++ b/src/gcc/attr-fnspec.h @@ -54,7 +54,7 @@ @@ -222,7 +1267,15 @@ arg_max_access_size_given_by_arg_p (unsigned int i, unsigned int *arg) --- a/src/gcc/c-family/ChangeLog +++ b/src/gcc/c-family/ChangeLog -@@ -1,3 +1,10 @@ +@@ -1,3 +1,18 @@ ++2023-05-19 Patrick Palka ++ ++ Backported from master: ++ 2023-05-15 Patrick Palka ++ ++ * c-cppbuiltin.cc (c_cpp_builtins): Predefine __cpp_auto_cast ++ for C++23. ++ +2023-05-02 Marek Polacek + + PR c++/109642 @@ -233,6 +1286,16 @@ 2023-04-26 Release Manager * GCC 13.1.0 released. +--- a/src/gcc/c-family/c-cppbuiltin.cc ++++ b/src/gcc/c-family/c-cppbuiltin.cc +@@ -1074,6 +1074,7 @@ c_cpp_builtins (cpp_reader *pfile) + /* Set feature test macros for C++23. */ + cpp_define (pfile, "__cpp_size_t_suffix=202011L"); + cpp_define (pfile, "__cpp_if_consteval=202106L"); ++ cpp_define (pfile, "__cpp_auto_cast=202110L"); + cpp_define (pfile, "__cpp_constexpr=202211L"); + cpp_define (pfile, "__cpp_multidimensional_subscript=202211L"); + cpp_define (pfile, "__cpp_named_character_escapes=202207L"); --- a/src/gcc/c-family/c.opt +++ b/src/gcc/c-family/c.opt @@ -560,7 +560,7 @@ C ObjC C++ ObjC++ Joined RejectNegative UInteger Var(warn_dangling_pointer) Warn @@ -332,9 +1395,191 @@ else if (TREE_CODE (constructor_type) == POINTER_TYPE) /* Ensure this is a null pointer constant in the case of a 'constexpr' object initialized with {}. */ +--- a/src/gcc/common/config/riscv/riscv-common.cc ++++ b/src/gcc/common/config/riscv/riscv-common.cc +@@ -1441,9 +1441,6 @@ riscv_multi_lib_check (int argc ATTRIBUTE_UNUSED, + return ""; + } + +-/* We only override this in bare-metal toolchain. */ +-#ifdef RISCV_USE_CUSTOMISED_MULTI_LIB +- + /* Find last switch with the prefix, options are take last one in general, + return NULL if not found, and return the option value if found, it could + return empty string if the option has no value. */ +@@ -1597,6 +1594,65 @@ riscv_check_conds ( + return match_score + ok_count * 100; + } + ++static const char * ++riscv_select_multilib_by_abi ( ++ const std::string &riscv_current_abi_str, ++ const std::vector &multilib_infos) ++{ ++ for (size_t i = 0; i < multilib_infos.size (); ++i) ++ if (riscv_current_abi_str == multilib_infos[i].abi_str) ++ return xstrdup (multilib_infos[i].path.c_str ()); ++ ++ return NULL; ++} ++ ++static const char * ++riscv_select_multilib ( ++ const std::string &riscv_current_abi_str, ++ const riscv_subset_list *subset_list, const struct switchstr *switches, ++ int n_switches, const std::vector &multilib_infos) ++{ ++ int match_score = 0; ++ int max_match_score = 0; ++ int best_match_multi_lib = -1; ++ /* Try to decision which set we should used. */ ++ /* We have 3 level decision tree here, ABI, check input arch/ABI must ++ be superset of multi-lib arch, and other rest option checking. */ ++ for (size_t i = 0; i < multilib_infos.size (); ++i) ++ { ++ /* Check ABI is same first. */ ++ if (riscv_current_abi_str != multilib_infos[i].abi_str) ++ continue; ++ ++ /* Found a potential compatible multi-lib setting! ++ Calculate the match score. */ ++ match_score = subset_list->match_score (multilib_infos[i].subset_list); ++ ++ /* Checking other cond in the multi-lib setting. */ ++ match_score = riscv_check_conds (switches, n_switches, match_score, ++ multilib_infos[i].conds); ++ ++ /* Record highest match score multi-lib setting. */ ++ if (match_score > max_match_score) ++ { ++ best_match_multi_lib = i; ++ max_match_score = match_score; ++ } ++ } ++ ++ if (best_match_multi_lib == -1) ++ { ++ riscv_no_matched_multi_lib = true; ++ return NULL; ++ } ++ else ++ return xstrdup (multilib_infos[best_match_multi_lib].path.c_str ()); ++} ++ ++#ifndef RISCV_USE_CUSTOMISED_MULTI_LIB ++#define RISCV_USE_CUSTOMISED_MULTI_LIB select_by_builtin ++#endif ++ + /* Implement TARGET_COMPUTE_MULTILIB. */ + static const char * + riscv_compute_multilib ( +@@ -1609,6 +1665,11 @@ riscv_compute_multilib ( + const char *multilib_exclusions ATTRIBUTE_UNUSED, + const char *multilib_reuse ATTRIBUTE_UNUSED) + { ++ enum riscv_multilib_select_kind select_kind = RISCV_USE_CUSTOMISED_MULTI_LIB; ++ ++ if (select_kind == select_by_builtin) ++ return multilib_dir; ++ + const char *p; + const char *this_path; + size_t this_path_len; +@@ -1672,7 +1733,13 @@ riscv_compute_multilib ( + } + + this_path_len = p - this_path; +- multilib_info.path = std::string (this_path, this_path_len); ++ const char *multi_os_dir_pos ++ = (const char *) memchr (this_path, ':', this_path_len); ++ if (multi_os_dir_pos) ++ multilib_info.path ++ = std::string (this_path, multi_os_dir_pos - this_path); ++ else ++ multilib_info.path = std::string (this_path, this_path_len); + + option_conds.clear (); + /* Pasrse option check list into vector. +@@ -1707,48 +1774,23 @@ riscv_compute_multilib ( + p++; + } + +- int match_score = 0; +- int max_match_score = 0; +- int best_match_multi_lib = -1; +- /* Try to decision which set we should used. */ +- /* We have 3 level decision tree here, ABI, check input arch/ABI must +- be superset of multi-lib arch, and other rest option checking. */ +- for (size_t i = 0; i < multilib_infos.size (); ++i) ++ switch (select_kind) + { +- /* Check ABI is same first. */ +- if (riscv_current_abi_str != multilib_infos[i].abi_str) +- continue; +- +- /* Found a potential compatible multi-lib setting! +- Calculate the match score. */ +- match_score = subset_list->match_score (multilib_infos[i].subset_list); +- +- /* Checking other cond in the multi-lib setting. */ +- match_score = riscv_check_conds (switches, +- n_switches, +- match_score, +- multilib_infos[i].conds); +- +- /* Record highest match score multi-lib setting. */ +- if (match_score > max_match_score) +- { +- best_match_multi_lib = i; +- max_match_score = match_score; +- } +- } +- +- if (best_match_multi_lib == -1) +- { +- riscv_no_matched_multi_lib = true; +- return multilib_dir; ++ case select_by_abi: ++ return riscv_select_multilib_by_abi (riscv_current_abi_str, ++ multilib_infos); ++ case select_by_abi_arch_cmodel: ++ return riscv_select_multilib (riscv_current_abi_str, subset_list, ++ switches, n_switches, multilib_infos); ++ case select_by_builtin: ++ gcc_unreachable (); ++ default: ++ gcc_unreachable (); + } +- else +- return xstrdup (multilib_infos[best_match_multi_lib].path.c_str ()); + } + + #undef TARGET_COMPUTE_MULTILIB + #define TARGET_COMPUTE_MULTILIB riscv_compute_multilib +-#endif + + vec + riscv_get_valid_option_values (int option_code, --- a/src/gcc/config/aarch64/aarch64-builtins.cc +++ b/src/gcc/config/aarch64/aarch64-builtins.cc -@@ -1547,7 +1547,7 @@ aarch64_scalar_builtin_type_p (aarch64_simd_type t) +@@ -933,6 +933,16 @@ aarch64_general_add_builtin (const char *name, tree type, unsigned int code, + NULL, attrs); + } + ++static tree ++aarch64_general_simulate_builtin (const char *name, tree fntype, ++ unsigned int code, ++ tree attrs = NULL_TREE) ++{ ++ code = (code << AARCH64_BUILTIN_SHIFT) | AARCH64_BUILTIN_GENERAL; ++ return simulate_builtin_function_decl (input_location, name, fntype, ++ code, NULL, attrs); ++} ++ + static const char * + aarch64_mangle_builtin_scalar_type (const_tree type) + { +@@ -1547,7 +1557,7 @@ aarch64_scalar_builtin_type_p (aarch64_simd_type t) /* Enable AARCH64_FL_* flags EXTRA_FLAGS on top of the base Advanced SIMD set. */ @@ -343,6 +1588,131 @@ : m_old_asm_isa_flags (aarch64_asm_isa_flags), m_old_general_regs_only (TARGET_GENERAL_REGS_ONLY) { +@@ -1839,11 +1849,11 @@ aarch64_init_ls64_builtins_types (void) + gcc_assert (TYPE_ALIGN (array_type) == 64); + + tree field = build_decl (input_location, FIELD_DECL, +- get_identifier ("val"), array_type); ++ get_identifier ("val"), array_type); + + ls64_arm_data_t = lang_hooks.types.simulate_record_decl (input_location, +- tuple_type_name, +- make_array_slice (&field, 1)); ++ tuple_type_name, ++ make_array_slice (&field, 1)); + + gcc_assert (TYPE_MODE (ls64_arm_data_t) == V8DImode); + gcc_assert (TYPE_MODE_RAW (ls64_arm_data_t) == TYPE_MODE (ls64_arm_data_t)); +@@ -1856,23 +1866,24 @@ aarch64_init_ls64_builtins (void) + aarch64_init_ls64_builtins_types (); + + ls64_builtins_data data[4] = { +- {"__builtin_aarch64_ld64b", AARCH64_LS64_BUILTIN_LD64B, ++ {"__arm_ld64b", AARCH64_LS64_BUILTIN_LD64B, + build_function_type_list (ls64_arm_data_t, +- const_ptr_type_node, NULL_TREE)}, +- {"__builtin_aarch64_st64b", AARCH64_LS64_BUILTIN_ST64B, ++ const_ptr_type_node, NULL_TREE)}, ++ {"__arm_st64b", AARCH64_LS64_BUILTIN_ST64B, + build_function_type_list (void_type_node, ptr_type_node, +- ls64_arm_data_t, NULL_TREE)}, +- {"__builtin_aarch64_st64bv", AARCH64_LS64_BUILTIN_ST64BV, ++ ls64_arm_data_t, NULL_TREE)}, ++ {"__arm_st64bv", AARCH64_LS64_BUILTIN_ST64BV, + build_function_type_list (uint64_type_node, ptr_type_node, +- ls64_arm_data_t, NULL_TREE)}, +- {"__builtin_aarch64_st64bv0", AARCH64_LS64_BUILTIN_ST64BV0, ++ ls64_arm_data_t, NULL_TREE)}, ++ {"__arm_st64bv0", AARCH64_LS64_BUILTIN_ST64BV0, + build_function_type_list (uint64_type_node, ptr_type_node, +- ls64_arm_data_t, NULL_TREE)}, ++ ls64_arm_data_t, NULL_TREE)}, + }; + + for (size_t i = 0; i < ARRAY_SIZE (data); ++i) + aarch64_builtin_decls[data[i].code] +- = aarch64_general_add_builtin (data[i].name, data[i].type, data[i].code); ++ = aarch64_general_simulate_builtin (data[i].name, data[i].type, ++ data[i].code); + } + + static void +@@ -2005,6 +2016,9 @@ aarch64_general_init_builtins (void) + + if (TARGET_MEMTAG) + aarch64_init_memtag_builtins (); ++ ++ if (in_lto_p) ++ handle_arm_acle_h (); + } + + /* Implement TARGET_BUILTIN_DECL for the AARCH64_BUILTIN_GENERAL group. */ +@@ -2486,40 +2500,40 @@ aarch64_expand_builtin_ls64 (int fcode, tree exp, rtx target) + { + case AARCH64_LS64_BUILTIN_LD64B: + { +- rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); +- create_output_operand (&ops[0], target, V8DImode); +- create_input_operand (&ops[1], op0, DImode); +- expand_insn (CODE_FOR_ld64b, 2, ops); +- return ops[0].value; ++ rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); ++ create_output_operand (&ops[0], target, V8DImode); ++ create_input_operand (&ops[1], op0, DImode); ++ expand_insn (CODE_FOR_ld64b, 2, ops); ++ return ops[0].value; + } + case AARCH64_LS64_BUILTIN_ST64B: + { +- rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); +- rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1)); +- create_output_operand (&ops[0], op0, DImode); +- create_input_operand (&ops[1], op1, V8DImode); +- expand_insn (CODE_FOR_st64b, 2, ops); +- return const0_rtx; ++ rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); ++ rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1)); ++ create_input_operand (&ops[0], op0, DImode); ++ create_input_operand (&ops[1], op1, V8DImode); ++ expand_insn (CODE_FOR_st64b, 2, ops); ++ return const0_rtx; + } + case AARCH64_LS64_BUILTIN_ST64BV: + { +- rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); +- rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1)); +- create_output_operand (&ops[0], target, DImode); +- create_input_operand (&ops[1], op0, DImode); +- create_input_operand (&ops[2], op1, V8DImode); +- expand_insn (CODE_FOR_st64bv, 3, ops); +- return ops[0].value; ++ rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); ++ rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1)); ++ create_output_operand (&ops[0], target, DImode); ++ create_input_operand (&ops[1], op0, DImode); ++ create_input_operand (&ops[2], op1, V8DImode); ++ expand_insn (CODE_FOR_st64bv, 3, ops); ++ return ops[0].value; + } + case AARCH64_LS64_BUILTIN_ST64BV0: + { +- rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); +- rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1)); +- create_output_operand (&ops[0], target, DImode); +- create_input_operand (&ops[1], op0, DImode); +- create_input_operand (&ops[2], op1, V8DImode); +- expand_insn (CODE_FOR_st64bv0, 3, ops); +- return ops[0].value; ++ rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); ++ rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1)); ++ create_output_operand (&ops[0], target, DImode); ++ create_input_operand (&ops[1], op0, DImode); ++ create_input_operand (&ops[2], op1, V8DImode); ++ expand_insn (CODE_FOR_st64bv0, 3, ops); ++ return ops[0].value; + } + } + --- a/src/gcc/config/aarch64/aarch64-protos.h +++ b/src/gcc/config/aarch64/aarch64-protos.h @@ -733,11 +733,11 @@ const unsigned int AARCH64_BUILTIN_CLASS = (1 << AARCH64_BUILTIN_SHIFT) - 1; @@ -380,6 +1750,7454 @@ /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable. The following code thus handles passing by SIMD/FP registers first. */ +--- a/src/gcc/config/aarch64/aarch64.md ++++ b/src/gcc/config/aarch64/aarch64.md +@@ -7824,9 +7824,9 @@ (define_insn "stg" + ;; Load/Store 64-bit (LS64) instructions. + (define_insn "ld64b" + [(set (match_operand:V8DI 0 "register_operand" "=r") +- (unspec_volatile:V8DI +- [(mem:V8DI (match_operand:DI 1 "register_operand" "r"))] +- UNSPEC_LD64B) ++ (unspec_volatile:V8DI ++ [(mem:V8DI (match_operand:DI 1 "register_operand" "r"))] ++ UNSPEC_LD64B) + )] + "TARGET_LS64" + "ld64b\\t%0, [%1]" +@@ -7834,9 +7834,9 @@ (define_insn "ld64b" + ) + + (define_insn "st64b" +- [(set (mem:V8DI (match_operand:DI 0 "register_operand" "=r")) +- (unspec_volatile:V8DI [(match_operand:V8DI 1 "register_operand" "r")] +- UNSPEC_ST64B) ++ [(set (mem:V8DI (match_operand:DI 0 "register_operand" "r")) ++ (unspec_volatile:V8DI [(match_operand:V8DI 1 "register_operand" "r")] ++ UNSPEC_ST64B) + )] + "TARGET_LS64" + "st64b\\t%1, [%0]" +@@ -7845,10 +7845,10 @@ (define_insn "st64b" + + (define_insn "st64bv" + [(set (match_operand:DI 0 "register_operand" "=r") +- (unspec_volatile:DI [(const_int 0)] UNSPEC_ST64BV_RET)) ++ (unspec_volatile:DI [(const_int 0)] UNSPEC_ST64BV_RET)) + (set (mem:V8DI (match_operand:DI 1 "register_operand" "r")) +- (unspec_volatile:V8DI [(match_operand:V8DI 2 "register_operand" "r")] +- UNSPEC_ST64BV) ++ (unspec_volatile:V8DI [(match_operand:V8DI 2 "register_operand" "r")] ++ UNSPEC_ST64BV) + )] + "TARGET_LS64" + "st64bv\\t%0, %2, [%1]" +@@ -7857,10 +7857,10 @@ (define_insn "st64bv" + + (define_insn "st64bv0" + [(set (match_operand:DI 0 "register_operand" "=r") +- (unspec_volatile:DI [(const_int 0)] UNSPEC_ST64BV0_RET)) ++ (unspec_volatile:DI [(const_int 0)] UNSPEC_ST64BV0_RET)) + (set (mem:V8DI (match_operand:DI 1 "register_operand" "r")) +- (unspec_volatile:V8DI [(match_operand:V8DI 2 "register_operand" "r")] +- UNSPEC_ST64BV0) ++ (unspec_volatile:V8DI [(match_operand:V8DI 2 "register_operand" "r")] ++ UNSPEC_ST64BV0) + )] + "TARGET_LS64" + "st64bv0\\t%0, %2, [%1]" +--- a/src/gcc/config/aarch64/arm_acle.h ++++ b/src/gcc/config/aarch64/arm_acle.h +@@ -270,40 +270,7 @@ __ttest (void) + #endif + + #ifdef __ARM_FEATURE_LS64 +-#pragma GCC push_options +-#pragma GCC target ("+nothing+ls64") +- + typedef __arm_data512_t data512_t; +- +-__extension__ extern __inline data512_t +-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +-__arm_ld64b (const void *__addr) +-{ +- return __builtin_aarch64_ld64b (__addr); +-} +- +-__extension__ extern __inline void +-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +-__arm_st64b (void *__addr, data512_t __value) +-{ +- __builtin_aarch64_st64b (__addr, __value); +-} +- +-__extension__ extern __inline uint64_t +-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +-__arm_st64bv (void *__addr, data512_t __value) +-{ +- return __builtin_aarch64_st64bv (__addr, __value); +-} +- +-__extension__ extern __inline uint64_t +-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +-__arm_st64bv0 (void *__addr, data512_t __value) +-{ +- return __builtin_aarch64_st64bv0 (__addr, __value); +-} +- +-#pragma GCC pop_options + #endif + + #pragma GCC push_options +--- a/src/gcc/config/arm/arm-builtins.cc ++++ b/src/gcc/config/arm/arm-builtins.cc +@@ -97,7 +97,7 @@ arm_binop_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] + /* T (T, unsigned immediate). */ + static enum arm_type_qualifiers + arm_sat_binop_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] +- = { qualifier_unsigned, qualifier_none, qualifier_unsigned_immediate }; ++ = { qualifier_none, qualifier_none, qualifier_unsigned_immediate }; + #define SAT_BINOP_UNSIGNED_IMM_QUALIFIERS \ + (arm_sat_binop_imm_qualifiers) + +--- a/src/gcc/config/arm/arm.md ++++ b/src/gcc/config/arm/arm.md +@@ -7555,7 +7555,7 @@ (define_expand "movdf" + && !arm_const_double_rtx (operands[1]) + && !(TARGET_VFP_DOUBLE && vfp3_const_double_rtx (operands[1]))) + { +- rtx clobreg = gen_reg_rtx (DFmode); ++ rtx clobreg = gen_reg_rtx (DImode); + emit_insn (gen_no_literal_pool_df_immediate (operands[0], operands[1], + clobreg)); + DONE; +--- a/src/gcc/config/arm/arm_mve.h ++++ b/src/gcc/config/arm/arm_mve.h +@@ -16055,7 +16055,7 @@ __extension__ extern __inline int32x4_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vadcq_s32 (int32x4_t __a, int32x4_t __b, unsigned * __carry) + { +- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); ++ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29)); + int32x4_t __res = __builtin_mve_vadcq_sv4si (__a, __b); + *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +@@ -16065,7 +16065,7 @@ __extension__ extern __inline uint32x4_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vadcq_u32 (uint32x4_t __a, uint32x4_t __b, unsigned * __carry) + { +- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); ++ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29)); + uint32x4_t __res = __builtin_mve_vadcq_uv4si (__a, __b); + *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +@@ -16075,7 +16075,7 @@ __extension__ extern __inline int32x4_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vadcq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, unsigned * __carry, mve_pred16_t __p) + { +- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); ++ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29)); + int32x4_t __res = __builtin_mve_vadcq_m_sv4si (__inactive, __a, __b, __p); + *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +@@ -16085,7 +16085,7 @@ __extension__ extern __inline uint32x4_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vadcq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, unsigned * __carry, mve_pred16_t __p) + { +- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); ++ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29)); + uint32x4_t __res = __builtin_mve_vadcq_m_uv4si (__inactive, __a, __b, __p); + *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +@@ -16131,7 +16131,7 @@ __extension__ extern __inline int32x4_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vsbcq_s32 (int32x4_t __a, int32x4_t __b, unsigned * __carry) + { +- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); ++ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29)); + int32x4_t __res = __builtin_mve_vsbcq_sv4si (__a, __b); + *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +@@ -16141,7 +16141,7 @@ __extension__ extern __inline uint32x4_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vsbcq_u32 (uint32x4_t __a, uint32x4_t __b, unsigned * __carry) + { +- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); ++ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29)); + uint32x4_t __res = __builtin_mve_vsbcq_uv4si (__a, __b); + *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +@@ -16151,7 +16151,7 @@ __extension__ extern __inline int32x4_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vsbcq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, unsigned * __carry, mve_pred16_t __p) + { +- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); ++ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29)); + int32x4_t __res = __builtin_mve_vsbcq_m_sv4si (__inactive, __a, __b, __p); + *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +@@ -16161,7 +16161,7 @@ __extension__ extern __inline uint32x4_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vsbcq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, unsigned * __carry, mve_pred16_t __p) + { +- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); ++ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29)); + uint32x4_t __res = __builtin_mve_vsbcq_m_uv4si (__inactive, __a, __b, __p); + *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +@@ -35582,16 +35582,29 @@ enum { + short: __ARM_mve_type_int_n, \ + int: __ARM_mve_type_int_n, \ + long: __ARM_mve_type_int_n, \ ++ long long: __ARM_mve_type_int_n, \ + _Float16: __ARM_mve_type_fp_n, \ + __fp16: __ARM_mve_type_fp_n, \ + float: __ARM_mve_type_fp_n, \ + double: __ARM_mve_type_fp_n, \ +- long long: __ARM_mve_type_int_n, \ + unsigned char: __ARM_mve_type_int_n, \ + unsigned short: __ARM_mve_type_int_n, \ + unsigned int: __ARM_mve_type_int_n, \ + unsigned long: __ARM_mve_type_int_n, \ + unsigned long long: __ARM_mve_type_int_n, \ ++ signed char*: __ARM_mve_type_int8_t_ptr, \ ++ short*: __ARM_mve_type_int16_t_ptr, \ ++ int*: __ARM_mve_type_int32_t_ptr, \ ++ long*: __ARM_mve_type_int32_t_ptr, \ ++ long long*: __ARM_mve_type_int64_t_ptr, \ ++ _Float16*: __ARM_mve_type_float16_t_ptr, \ ++ __fp16*: __ARM_mve_type_float16_t_ptr, \ ++ float*: __ARM_mve_type_float32_t_ptr, \ ++ unsigned char*: __ARM_mve_type_uint8_t_ptr, \ ++ unsigned short*: __ARM_mve_type_uint16_t_ptr, \ ++ unsigned int*: __ARM_mve_type_uint32_t_ptr, \ ++ unsigned long*: __ARM_mve_type_uint32_t_ptr, \ ++ unsigned long long*: __ARM_mve_type_uint64_t_ptr, \ + default: __ARM_mve_unsupported_type)) + #else + #define __ARM_mve_typeid(x) _Generic(x, \ +@@ -35650,32 +35663,67 @@ enum { + unsigned int: __ARM_mve_type_int_n, \ + unsigned long: __ARM_mve_type_int_n, \ + unsigned long long: __ARM_mve_type_int_n, \ ++ signed char*: __ARM_mve_type_int8_t_ptr, \ ++ short*: __ARM_mve_type_int16_t_ptr, \ ++ int*: __ARM_mve_type_int32_t_ptr, \ ++ long*: __ARM_mve_type_int32_t_ptr, \ ++ long long*: __ARM_mve_type_int64_t_ptr, \ ++ unsigned char*: __ARM_mve_type_uint8_t_ptr, \ ++ unsigned short*: __ARM_mve_type_uint16_t_ptr, \ ++ unsigned int*: __ARM_mve_type_uint32_t_ptr, \ ++ unsigned long*: __ARM_mve_type_uint32_t_ptr, \ ++ unsigned long long*: __ARM_mve_type_uint64_t_ptr, \ + default: __ARM_mve_unsupported_type)) + #endif /* MVE Floating point. */ + + extern void *__ARM_undef; + #define __ARM_mve_coerce(param, type) \ + _Generic(param, type: param, default: *(type *)__ARM_undef) +-#define __ARM_mve_coerce1(param, type) \ +- _Generic(param, type: param, const type: param, default: *(type *)__ARM_undef) +-#define __ARM_mve_coerce2(param, type) \ +- _Generic(param, type: param, __fp16: param, default: _Generic (param, _Float16: param, float16_t: param, float32_t: param, default: *(type *)__ARM_undef)) +-#define __ARM_mve_coerce3(param, type) \ +- _Generic(param, type: param, default: _Generic (param, int8_t: param, int16_t: param, int32_t: param, int64_t: param, uint8_t: param, uint16_t: param, uint32_t: param, uint64_t: param, default: *(type *)__ARM_undef)) ++#define __ARM_mve_coerce_i_scalar(param, type) \ ++ _Generic(param, type: param, const type: param, default: _Generic (param, int8_t: param, int16_t: param, int32_t: param, int64_t: param, uint8_t: param, uint16_t: param, uint32_t: param, uint64_t: param, default: *(type *)__ARM_undef)) ++ ++#define __ARM_mve_coerce_s8_ptr(param, type) \ ++ _Generic(param, type: param, const type: param, default: _Generic (param, signed char*: param, default: *(type *)__ARM_undef)) ++#define __ARM_mve_coerce_u8_ptr(param, type) \ ++ _Generic(param, type: param, const type: param, default: _Generic (param, unsigned char*: param, default: *(type *)__ARM_undef)) ++ ++#define __ARM_mve_coerce_s16_ptr(param, type) \ ++ _Generic(param, type: param, const type: param, default: _Generic (param, short*: param, default: *(type *)__ARM_undef)) ++#define __ARM_mve_coerce_u16_ptr(param, type) \ ++ _Generic(param, type: param, const type: param, default: _Generic (param, unsigned short*: param, default: *(type *)__ARM_undef)) ++ ++#define __ARM_mve_coerce_s32_ptr(param, type) \ ++ _Generic(param, type: param, const type: param, default: _Generic (param, int*: param, long*: param, default: *(type *)__ARM_undef)) ++#define __ARM_mve_coerce_u32_ptr(param, type) \ ++ _Generic(param, type: param, const type: param, default: _Generic (param, unsigned int*: param, unsigned long*: param, default: *(type *)__ARM_undef)) ++ ++#define __ARM_mve_coerce_s64_ptr(param, type) \ ++ _Generic(param, type: param, const type: param, default: _Generic (param, long long*: param, default: *(type *)__ARM_undef)) ++#define __ARM_mve_coerce_u64_ptr(param, type) \ ++ _Generic(param, type: param, const type: param, default: _Generic (param, unsigned long long*: param, default: *(type *)__ARM_undef)) ++ ++#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ ++#define __ARM_mve_coerce_f_scalar(param, type) \ ++ _Generic(param, type: param, const type: param, __fp16: param, default: _Generic (param, _Float16: param, float16_t: param, float32_t: param, default: *(type *)__ARM_undef)) ++#define __ARM_mve_coerce_f16_ptr(param, type) \ ++ _Generic(param, type: param, const type: param, default: _Generic (param, __fp16*: param, _Float16*: param, default: *(type *)__ARM_undef)) ++#define __ARM_mve_coerce_f32_ptr(param, type) \ ++ _Generic(param, type: param, const type: param, default: _Generic (param, float*: param, default: *(type *)__ARM_undef)) ++#endif + + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ + + #define __arm_vst4q(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vst4q_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_vst4q_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x4_t)), \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_vst4q_s32 (__ARM_mve_coerce(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x4_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_vst4q_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x4_t]: __arm_vst4q_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x4_t)), \ +- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x4_t]: __arm_vst4q_f32 (__ARM_mve_coerce(__p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x4_t)));}) ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vst4q_s8 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_vst4q_s16 (__ARM_mve_coerce_s16_ptr(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x4_t)), \ ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_vst4q_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x4_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_vst4q_u8 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce_u16_ptr(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x4_t]: __arm_vst4q_f16 (__ARM_mve_coerce_f16_ptr(__p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x4_t)), \ ++ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x4_t]: __arm_vst4q_f32 (__ARM_mve_coerce_f32_ptr(__p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x4_t)));}) + + #define __arm_vrndxq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +@@ -35852,6 +35900,10 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vorrq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vorrq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vorrq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vorrq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +@@ -35878,14 +35930,14 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vaddq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vaddq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)));}) ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)));}) + + #define __arm_vandq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -35902,10 +35954,10 @@ extern void *__ARM_undef; + #define __arm_vbicq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce1 (__p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce1 (__p1, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce1 (__p1, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce1 (__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar (__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar (__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar (__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar (__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -35930,14 +35982,14 @@ extern void *__ARM_undef; + #define __arm_vmulq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -35962,14 +36014,14 @@ extern void *__ARM_undef; + #define __arm_vcmpeqq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpeqq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpeqq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpeqq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -36000,16 +36052,16 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpeqq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpeqq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double), p2), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double), p2));}) ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double), p2));}) + + #define __arm_vcmpgtq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -36017,13 +36069,13 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgtq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgtq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)));}) ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)));}) + + #define __arm_vcmpleq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -36033,11 +36085,11 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpleq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpleq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)));}) + + #define __arm_vcmpltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -36045,25 +36097,25 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpltq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpltq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpltq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)));}) ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)));}) + + #define __arm_vcmpneq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -36118,8 +36170,8 @@ extern void *__ARM_undef; + #define __arm_vmaxnmavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));}) ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \ ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));}) + + #define __arm_vmaxnmq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -36130,14 +36182,14 @@ extern void *__ARM_undef; + #define __arm_vmaxnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));}) ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \ ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));}) + + #define __arm_vmaxnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));}) ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \ ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));}) + + #define __arm_vminnmaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -36148,8 +36200,8 @@ extern void *__ARM_undef; + #define __arm_vminnmavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));}) ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \ ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));}) + + #define __arm_vbrsrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +@@ -36171,14 +36223,14 @@ extern void *__ARM_undef; + #define __arm_vsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -36191,8 +36243,8 @@ extern void *__ARM_undef; + #define __arm_vminnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));}) ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \ ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));}) + + #define __arm_vshlq_r(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +@@ -36247,12 +36299,12 @@ extern void *__ARM_undef; + #define __arm_vrshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -36283,12 +36335,12 @@ extern void *__ARM_undef; + #define __arm_vqsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -36339,12 +36391,12 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));}) + + #define __arm_vqrdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -36352,9 +36404,9 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));}) + + #define __arm_vmlaldavxq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -36387,8 +36439,8 @@ extern void *__ARM_undef; + #define __arm_vqdmulltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + +@@ -36401,17 +36453,17 @@ extern void *__ARM_undef; + #define __arm_vqdmullbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmullbq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmullbq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + + #define __arm_vqdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) +@@ -36419,12 +36471,12 @@ extern void *__ARM_undef; + #define __arm_vqaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -36457,12 +36509,12 @@ extern void *__ARM_undef; + #define __arm_vhaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -36487,12 +36539,12 @@ extern void *__ARM_undef; + #define __arm_vhsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -36635,12 +36687,12 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));}) + + #define __arm_vsriq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -36719,44 +36771,44 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));}) + + #define __arm_vqdmlashq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));}) + + #define __arm_vqrdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));}) + + #define __arm_vmlasq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));}) + + #define __arm_vqdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));}) + + #define __arm_vqrdmladhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -36946,11 +36998,11 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double), p2), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double), p2), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgtq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgtq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + +@@ -36962,11 +37014,11 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpleq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpleq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double), p2), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double), p2));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double), p2));}) + + #define __arm_vcmpltq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -36976,11 +37028,11 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpltq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpltq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double), p2), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double), p2));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double), p2));}) + + #define __arm_vcmpneq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -36993,14 +37045,14 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpneq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpneq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpneq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double), p2), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double), p2));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double), p2));}) + + #define __arm_vcvtbq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -37054,8 +37106,8 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmaq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double)), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmaq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double)), \ ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmaq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double)), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmaq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vfmaq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vfmaq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t)));}) + +@@ -37070,8 +37122,8 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double)), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double)));}) ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double)), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double)));}) + + #define __arm_vmaxnmaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -37094,14 +37146,14 @@ extern void *__ARM_undef; + #define __arm_vmaxnmavq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_p_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_p_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_p_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_p_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + + #define __arm_vmaxnmvq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_p_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_p_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_p_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_p_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + + #define __arm_vminnmaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -37112,14 +37164,14 @@ extern void *__ARM_undef; + #define __arm_vminnmavq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_p_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_p_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_p_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_p_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + + #define __arm_vminnmvq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_p_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_p_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_p_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_p_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + + #define __arm_vrndnq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -37181,13 +37233,13 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgeq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgeq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)));}) ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)));}) + + #define __arm_vrshrnbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -37288,11 +37340,11 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double), p2), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double), p2), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgeq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgeq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + +@@ -37321,14 +37373,14 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vaddq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vaddq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));}) + + #define __arm_vandq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -37469,15 +37521,15 @@ extern void *__ARM_undef; + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vfmaq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vfmaq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmaq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmaq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));}) ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmaq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmaq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));}) + + #define __arm_vfmasq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmasq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmasq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));}) ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmasq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmasq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));}) + + #define __arm_vfmsq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -37512,14 +37564,14 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmulq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmulq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));}) + + #define __arm_vornq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -37546,14 +37598,14 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vsubq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vsubq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));}) + + #define __arm_vorrq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -37570,236 +37622,236 @@ extern void *__ARM_undef; + + #define __arm_vld1q(p0) (\ + _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \ +- int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce1(p0, uint32_t *)), \ +- int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_f16 (__ARM_mve_coerce1(p0, float16_t *)), \ +- int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_f32 (__ARM_mve_coerce1(p0, float32_t *)))) ++ int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \ ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *)), \ ++ int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *)), \ ++ int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *)))) + + #define __arm_vld1q_z(p0,p1) ( \ + _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce1(p0, int8_t *), p1), \ +- int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce1(p0, int16_t *), p1), \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce1(p0, int32_t *), p1), \ +- int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce1(p0, uint8_t *), p1), \ +- int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), p1), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1), \ +- int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_z_f16 (__ARM_mve_coerce1(p0, float16_t *), p1), \ +- int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_z_f32 (__ARM_mve_coerce1(p0, float32_t *), p1))) ++ int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), p1), \ ++ int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), p1), \ ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), p1), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), p1), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1), \ ++ int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_z_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), p1), \ ++ int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_z_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1))) + + #define __arm_vld2q(p0) ( \ + _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \ +- int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld2q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld2q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld2q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld2q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld2q_u32 (__ARM_mve_coerce1(p0, uint32_t *)), \ +- int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld2q_f16 (__ARM_mve_coerce1(p0, float16_t *)), \ +- int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld2q_f32 (__ARM_mve_coerce1(p0, float32_t *)))) ++ int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld2q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \ ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld2q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld2q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld2q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld2q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *)), \ ++ int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld2q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *)), \ ++ int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld2q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *)))) + + #define __arm_vld4q(p0) ( \ + _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld4q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \ +- int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld4q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld4q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld4q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld4q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld4q_u32 (__ARM_mve_coerce1(p0, uint32_t *)), \ +- int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld4q_f16 (__ARM_mve_coerce1(p0, float16_t *)), \ +- int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld4q_f32 (__ARM_mve_coerce1(p0, float32_t *)))) ++ int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld4q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld4q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \ ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld4q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld4q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld4q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld4q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *)), \ ++ int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld4q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *)), \ ++ int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld4q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *)))) + + #define __arm_vldrhq_gather_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_f16 (__ARM_mve_coerce1(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t)));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t)));}) + + #define __arm_vldrhq_gather_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_f16 (__ARM_mve_coerce1(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2));}) + + #define __arm_vldrhq_gather_shifted_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_f16 (__ARM_mve_coerce1(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t)));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t)));}) + + #define __arm_vldrhq_gather_shifted_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_f16 (__ARM_mve_coerce1(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2));}) + + #define __arm_vldrwq_gather_offset(p0,p1) ( \ + _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_s32 (__ARM_mve_coerce1(p0, int32_t *), p1), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1), \ +- int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_offset_f32 (__ARM_mve_coerce1(p0, float32_t *), p1))) ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1), \ ++ int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_offset_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1))) + + #define __arm_vldrwq_gather_offset_z(p0,p1,p2) ( \ + _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_z_s32 (__ARM_mve_coerce1(p0, int32_t *), p1, p2), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_z_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1, p2), \ +- int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_offset_z_f32 (__ARM_mve_coerce1(p0, float32_t *), p1, p2))) ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_z_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1, p2), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_z_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1, p2), \ ++ int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_offset_z_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1, p2))) + + #define __arm_vldrwq_gather_shifted_offset(p0,p1) ( \ + _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_s32 (__ARM_mve_coerce1(p0, int32_t *), p1), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1), \ +- int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_shifted_offset_f32 (__ARM_mve_coerce1(p0, float32_t *), p1))) ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1), \ ++ int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_shifted_offset_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1))) + + #define __arm_vldrwq_gather_shifted_offset_z(p0,p1,p2) ( \ + _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_s32 (__ARM_mve_coerce1(p0, int32_t *), p1, p2), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1, p2), \ +- int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_f32 (__ARM_mve_coerce1(p0, float32_t *), p1, p2))) ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1, p2), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1, p2), \ ++ int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1, p2))) + + #define __arm_vst1q_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_p_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_p_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_p_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vst1q_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t), p2), \ +- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vst1q_p_f32 (__ARM_mve_coerce(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t), p2));}) ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_p_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_p_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vst1q_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t), p2), \ ++ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vst1q_p_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + + #define __arm_vst2q(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]: __arm_vst2q_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x2_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]: __arm_vst2q_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x2_t)), \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]: __arm_vst2q_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x2_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]: __arm_vst2q_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x2_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]: __arm_vst2q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x2_t)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]: __arm_vst2q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x2_t)), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x2_t]: __arm_vst2q_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x2_t)), \ +- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x2_t]: __arm_vst2q_f32 (__ARM_mve_coerce(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x2_t)));}) ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]: __arm_vst2q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x2_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]: __arm_vst2q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x2_t)), \ ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]: __arm_vst2q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x2_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]: __arm_vst2q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x2_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]: __arm_vst2q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x2_t)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]: __arm_vst2q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x2_t)), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x2_t]: __arm_vst2q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x2_t)), \ ++ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x2_t]: __arm_vst2q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x2_t)));}) + + #define __arm_vst1q(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vst1q_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t)), \ +- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vst1q_f32 (__ARM_mve_coerce(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t)));}) ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vst1q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t)), \ ++ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vst1q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t)));}) + + #define __arm_vstrhq(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vstrhq_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t)));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vstrhq_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t)));}) + + #define __arm_vstrhq_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vstrhq_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t), p2));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vstrhq_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t), p2));}) + + #define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));}) + + #define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));}) + + #define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));}) + + #define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));}) + + #define __arm_vstrwq_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_p_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_p_f32 (__ARM_mve_coerce(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t), p2));}) ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ ++ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_p_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + + #define __arm_vstrwq(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_f32 (__ARM_mve_coerce(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t)));}) ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t)));}) + + #define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));}) + + #define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));}) + + #define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));}) + + #define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));}) + + #define __arm_vstrwq_scatter_base(p0,p1,p2) ({ __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \ +@@ -37816,44 +37868,44 @@ extern void *__ARM_undef; + #define __arm_vstrwq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t)), \ +- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_offset_f32 (__ARM_mve_coerce(__p0, float32_t *), p1, __ARM_mve_coerce(__p2, float32x4_t)));}) ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_offset_f32 (__ARM_mve_coerce_f32_ptr(__p0, float32_t *), p1, __ARM_mve_coerce(__p2, float32x4_t)));}) + + #define __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \ +- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_offset_p_f32 (__ARM_mve_coerce(__p0, float32_t *), p1, __ARM_mve_coerce(__p2, float32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \ ++ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_offset_p_f32 (__ARM_mve_coerce_f32_ptr(__p0, float32_t *), p1, __ARM_mve_coerce(__p2, float32x4_t), p3));}) + + #define __arm_vstrwq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \ +- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));}) ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));}) + + #define __arm_vstrwq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \ +- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_f32 (__ARM_mve_coerce(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \ ++ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t), p3));}) + + #define __arm_vstrwq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \ +- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_f32 (__ARM_mve_coerce(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \ ++ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t), p3));}) + + #define __arm_vstrwq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \ +- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));}) ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));}) + + #define __arm_vuninitializedq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +@@ -38026,19 +38078,19 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vaddq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vaddq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));}) ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));}) + + #define __arm_vandq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ +@@ -38161,19 +38213,19 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmulq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmulq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));}) ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));}) + + #define __arm_vnegq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ +@@ -38262,19 +38314,19 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsubq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsubq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vsubq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vsubq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));}) ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));}) + + #define __arm_vcmulq_rot90_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ +@@ -38298,16 +38350,16 @@ extern void *__ARM_undef; + #define __arm_vsetq_lane(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int64x2_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint64x2_t), p2), \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vsetq_lane_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vsetq_lane_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int64x2_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint64x2_t), p2), \ ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vsetq_lane_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vsetq_lane_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + + #else /* MVE Integer. */ + +@@ -38323,12 +38375,12 @@ extern void *__ARM_undef; + + #define __arm_vst4q(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vst4q_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_vst4q_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x4_t)), \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_vst4q_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x4_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_vst4q_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)));}) ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vst4q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_vst4q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x4_t)), \ ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_vst4q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x4_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_vst4q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)));}) + + #define __arm_vabsq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +@@ -38425,12 +38477,12 @@ extern void *__ARM_undef; + #define __arm_vcmpneq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -38457,12 +38509,12 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsubq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsubq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));}) + + #define __arm_vshlq_r(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +@@ -38476,12 +38528,12 @@ extern void *__ARM_undef; + #define __arm_vrshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -38512,12 +38564,12 @@ extern void *__ARM_undef; + #define __arm_vqsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -38586,12 +38638,12 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));}) + + #define __arm_vqrdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -38599,16 +38651,16 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));}) + + #define __arm_vqdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) +@@ -38616,12 +38668,12 @@ extern void *__ARM_undef; + #define __arm_vqaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -38637,7 +38689,11 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vorrq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vorrq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vorrq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));}) + + #define __arm_vornq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -38652,12 +38708,12 @@ extern void *__ARM_undef; + #define __arm_vmulq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -38732,12 +38788,12 @@ extern void *__ARM_undef; + #define __arm_vhsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -38762,12 +38818,12 @@ extern void *__ARM_undef; + #define __arm_vhaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -38817,10 +38873,10 @@ extern void *__ARM_undef; + #define __arm_vbicq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce1 (__p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce1 (__p1, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce1 (__p1, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce1 (__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar (__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar (__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar (__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar (__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -38837,12 +38893,12 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));}) ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));}) + + #define __arm_vandq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -38873,12 +38929,12 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));}) + + #define __arm_vqmovntq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -38959,16 +39015,16 @@ extern void *__ARM_undef; + #define __arm_vqdmulltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + + #define __arm_vqdmullbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmullbq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmullbq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + +@@ -38978,9 +39034,9 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));}) + + #define __arm_vcmpgtq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -38988,9 +39044,9 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));}) + + #define __arm_vcmpleq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -38998,9 +39054,9 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpleq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpleq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));}) + + #define __arm_vcmpltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -39008,20 +39064,20 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpltq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));}) + + #define __arm_vcmpneq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpneq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ +@@ -39046,12 +39102,12 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));}) + + #define __arm_vbicq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +@@ -39161,25 +39217,25 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));}) + + #define __arm_vqdmlashq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));}) + + #define __arm_vqrdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));}) + + #define __arm_vqrdmladhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -39242,9 +39298,9 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));}) + + + #define __arm_vcmpgtq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +@@ -39253,9 +39309,9 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));}) + + #define __arm_vcmpleq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -39263,9 +39319,9 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpleq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpleq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));}) + + #define __arm_vcmpltq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -39273,9 +39329,9 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpltq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpltq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));}) + + #define __arm_vcmpneq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -39286,12 +39342,12 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpneq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpneq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpneq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));}) + + #define __arm_vdupq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -39314,23 +39370,23 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));}) + + #define __arm_vmlasq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));}) + + #define __arm_vnegq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -39355,9 +39411,9 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));}) + + #define __arm_vqdmlsdhq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -39520,12 +39576,12 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +@@ -39625,12 +39681,12 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + + #define __arm_vornq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -39658,12 +39714,12 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +@@ -39675,12 +39731,12 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +@@ -39695,12 +39751,12 @@ extern void *__ARM_undef; + + #define __arm_vldrbq_gather_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_s8 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_s16 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_s32 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_u8 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_u16 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_u32 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_s16 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_s32 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_u16 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_u32 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + + #define __arm_vstrwq_scatter_base_p(p0,p1,p2,p3) ({ __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \ +@@ -39709,144 +39765,144 @@ extern void *__ARM_undef; + + #define __arm_vld1q(p0) (\ + _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \ +- int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce1(p0, uint32_t *)))) ++ int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \ ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *)))) + + #define __arm_vldrhq_gather_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + + #define __arm_vldrhq_gather_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + + #define __arm_vldrhq_gather_shifted_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + + #define __arm_vldrhq_gather_shifted_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + + #define __arm_vldrwq_gather_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_s32 (__ARM_mve_coerce1(__p0, int32_t *), p1), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_u32 (__ARM_mve_coerce1(__p0, uint32_t *), p1));}) ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));}) + + #define __arm_vldrwq_gather_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_z_s32 (__ARM_mve_coerce1(__p0, int32_t *), p1, p2), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_z_u32 (__ARM_mve_coerce1(__p0, uint32_t *), p1, p2));}) ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_z_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, p2), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_z_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));}) + + #define __arm_vldrwq_gather_shifted_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_s32 (__ARM_mve_coerce1(__p0, int32_t *), p1), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_u32 (__ARM_mve_coerce1(__p0, uint32_t *), p1));}) ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));}) + + #define __arm_vldrwq_gather_shifted_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_s32 (__ARM_mve_coerce1(__p0, int32_t *), p1, p2), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce1(__p0, uint32_t *), p1, p2));}) ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, p2), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));}) + + #define __arm_vst1q(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + + #define __arm_vst1q_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_p_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_p_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_p_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_p_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_p_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + + #define __arm_vst2q(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]: __arm_vst2q_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x2_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]: __arm_vst2q_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x2_t)), \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]: __arm_vst2q_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x2_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]: __arm_vst2q_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x2_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]: __arm_vst2q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x2_t)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]: __arm_vst2q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x2_t)));}) ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]: __arm_vst2q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x2_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]: __arm_vst2q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x2_t)), \ ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]: __arm_vst2q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x2_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]: __arm_vst2q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x2_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]: __arm_vst2q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x2_t)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]: __arm_vst2q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x2_t)));}) + + #define __arm_vstrhq(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + + #define __arm_vstrhq_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + + #define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + + #define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + + #define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + + #define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + + + #define __arm_vstrwq(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + + #define __arm_vstrwq_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_p_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + + #define __arm_vstrdq_scatter_base_p(p0,p1,p2,p3) ({ __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \ +@@ -39861,58 +39917,58 @@ extern void *__ARM_undef; + #define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + + #define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + + #define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + + #define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + + #define __arm_vstrwq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t)));}) + + #define __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + + #define __arm_vstrwq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)));}) + + #define __arm_vstrwq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + + #define __arm_vuninitializedq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +@@ -40017,15 +40073,15 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3));}) ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));}) + + #define __arm_vcaddq_rot270_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ +@@ -40119,15 +40175,15 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3));}) ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));}) + + #define __arm_vnegq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ +@@ -40211,29 +40267,29 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vbrsrq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + + #define __arm_vld1q_z(p0,p1) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce1(p0, int8_t *), p1), \ +- int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce1(p0, int16_t *), p1), \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce1(p0, int32_t *), p1), \ +- int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce1(p0, uint8_t *), p1), \ +- int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), p1), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1))) ++ int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), p1), \ ++ int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), p1), \ ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), p1), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), p1), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1))) + + #define __arm_vld2q(p0) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \ +- int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld2q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld2q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld2q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld2q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld2q_u32 (__ARM_mve_coerce1(p0, uint32_t *)))) ++ int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld2q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \ ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld2q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld2q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld2q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld2q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *)))) + + + #define __arm_vld4q(p0) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld4q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \ +- int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld4q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld4q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld4q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld4q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld4q_u32 (__ARM_mve_coerce1(p0, uint32_t *)))) ++ int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld4q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld4q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \ ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld4q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld4q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld4q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld4q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *)))) + + #define __arm_vsubq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ +@@ -40241,15 +40297,15 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsubq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsubq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3));}) ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));}) + + #define __arm_vgetq_lane(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +@@ -40265,14 +40321,14 @@ extern void *__ARM_undef; + #define __arm_vsetq_lane(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int64x2_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint64x2_t), p2));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int64x2_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint64x2_t), p2));}) + + #endif /* MVE Integer. */ + +@@ -40383,62 +40439,62 @@ extern void *__ARM_undef; + #define __arm_vdwdupq_x_u8(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_x_n_u8 ((uint32_t) __p1, p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u8 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));}) + + #define __arm_vdwdupq_x_u16(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_x_n_u16 ((uint32_t) __p1, p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u16 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));}) + + #define __arm_vdwdupq_x_u32(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_x_n_u32 ((uint32_t) __p1, p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u32 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));}) + + #define __arm_viwdupq_x_u8(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_x_n_u8 ((uint32_t) __p1, p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u8 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));}) + + #define __arm_viwdupq_x_u16(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_x_n_u16 ((uint32_t) __p1, p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u16 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));}) + + #define __arm_viwdupq_x_u32(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_x_n_u32 ((uint32_t) __p1, p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u32 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));}) + + #define __arm_vidupq_x_u8(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_vidupq_x_n_u8 ((uint32_t) __p1, p2, p3), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u8 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));}) + + #define __arm_vddupq_x_u8(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_vddupq_x_n_u8 ((uint32_t) __p1, p2, p3), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u8 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));}) + + #define __arm_vidupq_x_u16(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_vidupq_x_n_u16 ((uint32_t) __p1, p2, p3), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u16 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));}) + + #define __arm_vddupq_x_u16(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_vddupq_x_n_u16 ((uint32_t) __p1, p2, p3), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u16 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));}) + + #define __arm_vidupq_x_u32(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_vidupq_x_n_u32 ((uint32_t) __p1, p2, p3), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u32 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));}) + + #define __arm_vddupq_x_u32(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_vddupq_x_n_u32 ((uint32_t) __p1, p2, p3), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u32 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));}) + + #define __arm_vshrq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ +@@ -40452,12 +40508,12 @@ extern void *__ARM_undef; + #define __arm_vhaddq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u8( __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u16( __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u32( __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u8( __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u16( __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u32( __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +@@ -40482,12 +40538,12 @@ extern void *__ARM_undef; + #define __arm_vhsubq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +@@ -40527,20 +40583,20 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_base_wb_u64 (p0, p1, __ARM_mve_coerce(__p2, uint64x2_t)));}) + + #define __arm_vldrdq_gather_offset(p0,p1) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_offset_s64 (__ARM_mve_coerce1(p0, int64_t *), p1), \ +- int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_offset_u64 (__ARM_mve_coerce1(p0, uint64_t *), p1))) ++ int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_offset_s64 (__ARM_mve_coerce_s64_ptr(p0, int64_t *), p1), \ ++ int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_offset_u64 (__ARM_mve_coerce_u64_ptr(p0, uint64_t *), p1))) + + #define __arm_vldrdq_gather_offset_z(p0,p1,p2) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_offset_z_s64 (__ARM_mve_coerce1(p0, int64_t *), p1, p2), \ +- int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_offset_z_u64 (__ARM_mve_coerce1(p0, uint64_t *), p1, p2))) ++ int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_offset_z_s64 (__ARM_mve_coerce_s64_ptr(p0, int64_t *), p1, p2), \ ++ int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_offset_z_u64 (__ARM_mve_coerce_u64_ptr(p0, uint64_t *), p1, p2))) + + #define __arm_vldrdq_gather_shifted_offset(p0,p1) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_shifted_offset_s64 (__ARM_mve_coerce1(p0, int64_t *), p1), \ +- int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_shifted_offset_u64 (__ARM_mve_coerce1(p0, uint64_t *), p1))) ++ int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_shifted_offset_s64 (__ARM_mve_coerce_s64_ptr(p0, int64_t *), p1), \ ++ int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_shifted_offset_u64 (__ARM_mve_coerce_u64_ptr(p0, uint64_t *), p1))) + + #define __arm_vldrdq_gather_shifted_offset_z(p0,p1,p2) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_shifted_offset_z_s64 (__ARM_mve_coerce1(p0, int64_t *), p1, p2), \ +- int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_shifted_offset_z_u64 (__ARM_mve_coerce1(p0, uint64_t *), p1, p2))) ++ int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_shifted_offset_z_s64 (__ARM_mve_coerce_s64_ptr(p0, int64_t *), p1, p2), \ ++ int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_shifted_offset_z_u64 (__ARM_mve_coerce_u64_ptr(p0, uint64_t *), p1, p2))) + + #define __arm_vadciq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -40596,36 +40652,36 @@ extern void *__ARM_undef; + + #define __arm_vldrbq_gather_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_z_s8 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_s16 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_s32 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_z_u8 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_u16 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_u32 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_z_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_s16 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_s32 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_z_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_u16 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_u32 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + + #define __arm_vqrdmlahq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));}) + + #define __arm_vqrdmlashq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));}) + + #define __arm_vqdmlashq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));}) + + #define __arm_vqrshlq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -40726,12 +40782,12 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqsubq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqsubq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqsubq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +@@ -40746,9 +40802,9 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmulhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmulhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmulhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));}) + + #define __arm_vqrdmlsdhxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -40874,17 +40930,17 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaq_p_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaq_p_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaq_p_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaq_p_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + + #define __arm_vmlaldavaxq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaxq_p_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaxq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaxq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaxq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + + #define __arm_vmlsldavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -40954,10 +41010,10 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmvnq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmvnq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmvnq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce1(__p1, int) , p2), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce1(__p1, int) , p2), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce1(__p1, int) , p2), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce1(__p1, int) , p2));}) ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int) , p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int) , p2), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int) , p2), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int) , p2));}) + + #define __arm_vorrq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +@@ -41023,12 +41079,12 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +@@ -41062,12 +41118,12 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vhsubq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vhsubq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vhsubq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));}) + + #define __arm_vmaxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -41095,23 +41151,23 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));}) + + #define __arm_vmlasq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));}) + + #define __arm_vmulhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -41157,12 +41213,12 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +@@ -41174,17 +41230,17 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));}) + + #define __arm_vqdmulhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmulhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) +@@ -41195,15 +41251,15 @@ extern void *__ARM_undef; + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmullbq_m_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmullbq_m_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_m_n_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3));}) ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_m_n_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));}) + + #define __arm_vqdmulltq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ +- int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_m_n_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_m_n_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulltq_m_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulltq_m_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + +@@ -41269,9 +41325,9 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaxq_p_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaxq_p_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaxq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaxq_p_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaxq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaxq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + + #define __arm_vmullbq_poly_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -41282,12 +41338,12 @@ extern void *__ARM_undef; + + #define __arm_vldrbq_gather_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_s8(__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_s16(__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_s32(__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_u8(__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_u16(__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_u32(__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_s8(__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_s16(__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_s32(__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_u8(__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_u16(__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_u32(__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + + #define __arm_vidupq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -41295,9 +41351,9 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vidupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), (uint32_t) __p1, p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vidupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), (uint32_t) __p1, p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vidupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), (uint32_t) __p1, p2, p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));}) + + #define __arm_vddupq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -41305,89 +41361,89 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vddupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), (uint32_t) __p1, p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vddupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), (uint32_t) __p1, p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vddupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), (uint32_t) __p1, p2, p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));}) + + #define __arm_vidupq_u16(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_vidupq_n_u16 ((uint32_t) __p0, p1), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u16 (__ARM_mve_coerce(__p0, uint32_t *), p1));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u16 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));}) + + #define __arm_vidupq_u32(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_vidupq_n_u32 ((uint32_t) __p0, p1), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));}) + + #define __arm_vidupq_u8(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_vidupq_n_u8 ((uint32_t) __p0, p1), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u8 (__ARM_mve_coerce(__p0, uint32_t *), p1));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u8 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));}) + + #define __arm_vddupq_u16(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_vddupq_n_u16 ((uint32_t) __p0, p1), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u16 (__ARM_mve_coerce(__p0, uint32_t *), p1));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u16 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));}) + + #define __arm_vddupq_u32(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_vddupq_n_u32 ((uint32_t) __p0, p1), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));}) + + #define __arm_vddupq_u8(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_vddupq_n_u8 ((uint32_t) __p0, p1), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u8 (__ARM_mve_coerce(__p0, uint32_t *), p1));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u8 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));}) + + #define __arm_viwdupq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));}) + + #define __arm_viwdupq_u16(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +- int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u16 (__ARM_mve_coerce3(p0, int), p1, (const int) p2), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u16 (__ARM_mve_coerce(__p0, uint32_t *), p1, (const int) p2));}) ++ int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u16 (__ARM_mve_coerce_i_scalar(__p0, int), p1, (const int) p2), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u16 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, (const int) p2));}) + + #define __arm_viwdupq_u32(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +- int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u32 (__ARM_mve_coerce3(p0, int), p1, p2), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));}) ++ int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u32 (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));}) + + #define __arm_viwdupq_u8(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +- int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u8 (__ARM_mve_coerce3(p0, int), p1, p2), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u8 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));}) ++ int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u8 (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u8 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));}) + + #define __arm_vdwdupq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));}) + + #define __arm_vdwdupq_u16(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +- int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u16 (__ARM_mve_coerce3(p0, int), p1, p2), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u16 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));}) ++ int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u16 (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u16 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));}) + + #define __arm_vdwdupq_u32(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +- int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u32 (__ARM_mve_coerce3(p0, int), p1, p2), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));}) ++ int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u32 (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));}) + + #define __arm_vdwdupq_u8(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +- int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u8 (__ARM_mve_coerce3(p0, int), p1, p2), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u8 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));}) ++ int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u8 (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u8 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));}) + + #define __arm_vshlcq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +@@ -41423,14 +41479,14 @@ extern void *__ARM_undef; + #define __arm_vaddlvaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddlvaq_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddlvaq_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddlvaq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddlvaq_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t)));}) + + #define __arm_vaddlvaq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddlvaq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddlvaq_p_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddlvaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddlvaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + + #define __arm_vaddlvq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +@@ -41445,22 +41501,22 @@ extern void *__ARM_undef; + #define __arm_vaddvaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vaddvaq_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vaddvaq_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddvaq_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vaddvaq_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vaddvaq_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddvaq_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vaddvaq_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vaddvaq_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddvaq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vaddvaq_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vaddvaq_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddvaq_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t)));}) + + #define __arm_vaddvaq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vaddvaq_p_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vaddvaq_p_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddvaq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vaddvaq_p_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vaddvaq_p_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddvaq_p_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vaddvaq_p_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vaddvaq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddvaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vaddvaq_p_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vaddvaq_p_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddvaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + + #define __arm_vaddvq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +@@ -41486,9 +41542,9 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpcsq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpcsq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpcsq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)));}) ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));}) + + #define __arm_vcmpcsq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -41496,9 +41552,9 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpcsq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpcsq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpcsq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2));}) ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));}) + + #define __arm_vcmphiq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -41506,16 +41562,16 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmphiq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmphiq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmphiq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)));}) ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));}) + + #define __arm_vcmphiq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmphiq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmphiq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmphiq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) +@@ -41612,34 +41668,34 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + + #define __arm_vmladavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + + #define __arm_vmladavaxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaxq_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaxq_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaxq_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaxq_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaxq_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaxq_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaxq_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaxq_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaxq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaxq_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaxq_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaxq_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + + #define __arm_vmladavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -41682,17 +41738,17 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaq_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaq_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaq_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaq_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaq_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaq_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaq_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + + #define __arm_vmlaldavaxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaxq_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaxq_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaxq_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaxq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + + #define __arm_vmlaldavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -41856,22 +41912,22 @@ extern void *__ARM_undef; + + #define __arm_vstrbq(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vstrbq_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrbq_s16 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrbq_s32 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_u16 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_u32 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vstrbq_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \ ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrbq_s16 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrbq_s32 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_u16 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_u32 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + + #define __arm_vstrbq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vstrbq_p_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrbq_p_s16 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrbq_p_s32 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_p_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_p_u16 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_p_u32 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vstrbq_p_s8 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \ ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrbq_p_s16 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrbq_p_s32 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_p_u8 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_p_u16 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_p_u32 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + + #define __arm_vstrdq_scatter_base(p0,p1,p2) ({ __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \ +@@ -41887,61 +41943,61 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhaq_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhaq_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhaq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhaq_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + + #define __arm_vrmlaldavhaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhaq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhaq_p_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + + #define __arm_vstrbq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vstrbq_scatter_offset_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrbq_scatter_offset_s16 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrbq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_u16 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vstrbq_scatter_offset_s8 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrbq_scatter_offset_s16 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrbq_scatter_offset_s32 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_u8 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_u16 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_u32 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + + #define __arm_vstrbq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vstrbq_scatter_offset_p_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrbq_scatter_offset_p_s16 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrbq_scatter_offset_p_s32 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_p_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_p_u16 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_p_u32 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vstrbq_scatter_offset_p_s8 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrbq_scatter_offset_p_s16 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrbq_scatter_offset_p_s32 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_p_u8 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_p_u16 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_p_u32 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + + #define __arm_vstrdq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_offset_p_s64 (__ARM_mve_coerce(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \ +- int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_offset_p_u64 (__ARM_mve_coerce(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));}) ++ int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_offset_p_s64 (__ARM_mve_coerce_s64_ptr(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \ ++ int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_offset_p_u64 (__ARM_mve_coerce_u64_ptr(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));}) + + #define __arm_vstrdq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_offset_s64 (__ARM_mve_coerce(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t)), \ +- int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_offset_u64 (__ARM_mve_coerce(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t)));}) ++ int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_offset_s64 (__ARM_mve_coerce_s64_ptr(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t)), \ ++ int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_offset_u64 (__ARM_mve_coerce_u64_ptr(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t)));}) + + #define __arm_vstrdq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_shifted_offset_p_s64 (__ARM_mve_coerce(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \ +- int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_shifted_offset_p_u64 (__ARM_mve_coerce(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));}) ++ int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_shifted_offset_p_s64 (__ARM_mve_coerce_s64_ptr(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \ ++ int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_shifted_offset_p_u64 (__ARM_mve_coerce_u64_ptr(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));}) + + #define __arm_vstrdq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_shifted_offset_s64 (__ARM_mve_coerce(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t)), \ +- int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_shifted_offset_u64 (__ARM_mve_coerce(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t)));}) ++ int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_shifted_offset_s64 (__ARM_mve_coerce_s64_ptr(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t)), \ ++ int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_shifted_offset_u64 (__ARM_mve_coerce_u64_ptr(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t)));}) + + #endif /* __cplusplus */ + #endif /* __ARM_FEATURE_MVE */ +--- a/src/gcc/config/arm/constraints.md ++++ b/src/gcc/config/arm/constraints.md +@@ -102,10 +102,6 @@ (define_constraint "Rg" + (match_test "TARGET_HAVE_MVE && ((ival == 1) || (ival == 2) + || (ival == 4) || (ival == 8))"))) + +-;; True if the immediate is multiple of 8 and in range of -/+ 1016 for MVE. +-(define_predicate "mve_vldrd_immediate" +- (match_test "satisfies_constraint_Ri (op)")) +- + (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS" + "The VFP registers @code{s0}-@code{s31}.") + +@@ -574,6 +570,22 @@ (define_constraint "US" + (match_code "symbol_ref") + ) + ++;; True if the immediate is the range +/- 1016 and multiple of 8 for MVE. ++(define_constraint "Ri" ++ "@internal In Thumb-2 state a constant is multiple of 8 and in range ++ of -/+ 1016 for MVE" ++ (and (match_code "const_int") ++ (match_test "TARGET_HAVE_MVE && (-1016 <= ival) && (ival <= 1016) ++ && ((ival % 8) == 0)"))) ++ ++;; True if the immediate is multiple of 2 and in range of -/+ 252 for MVE. ++(define_constraint "Rl" ++ "@internal In Thumb-2 state a constant is multiple of 2 and in range ++ of -/+ 252 for MVE" ++ (and (match_code "const_int") ++ (match_test "TARGET_HAVE_MVE && (-252 <= ival) && (ival <= 252) ++ && ((ival % 2) == 0)"))) ++ + (define_memory_constraint "Uz" + "@internal + A memory access that is accessible as an LDC/STC operand" +--- a/src/gcc/config/arm/mve.md ++++ b/src/gcc/config/arm/mve.md +@@ -141,7 +141,7 @@ (define_insn "mve_vrndq_m_f" + VRNDQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vpst\;vrintzt.f%# %q0, %q2" ++ "vpst\;vrintzt.f%#\t%q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -239,7 +239,7 @@ (define_insn "mve_vrev64q_f" + VREV64Q_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vrev64.%# %q0, %q1" ++ "vrev64.%#\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -293,7 +293,7 @@ (define_insn "mve_vrev32q_fv8hf" + VREV32Q_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vrev32.16 %q0, %q1" ++ "vrev32.16\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + ;; +@@ -306,7 +306,7 @@ (define_insn "mve_vcvttq_f32_f16v4sf" + VCVTTQ_F32_F16)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vcvtt.f32.f16 %q0, %q1" ++ "vcvtt.f32.f16\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -320,7 +320,7 @@ (define_insn "mve_vcvtbq_f32_f16v4sf" + VCVTBQ_F32_F16)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vcvtb.f32.f16 %q0, %q1" ++ "vcvtb.f32.f16\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -334,7 +334,7 @@ (define_insn "mve_vcvtq_to_f_" + VCVTQ_TO_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vcvt.f%#.%# %q0, %q1" ++ "vcvt.f%#.%#\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -348,7 +348,7 @@ (define_insn "mve_vrev64q_" + VREV64Q)) + ] + "TARGET_HAVE_MVE" +- "vrev64.%# %q0, %q1" ++ "vrev64.%#\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -362,7 +362,7 @@ (define_insn "mve_vcvtq_from_f_" + VCVTQ_FROM_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vcvt.%#.f%# %q0, %q1" ++ "vcvt.%#.f%#\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + ;; [vqnegq_s]) +@@ -524,7 +524,7 @@ (define_insn "mve_vmovltq_" + VMOVLTQ)) + ] + "TARGET_HAVE_MVE" +- "vmovlt.%# %q0, %q1" ++ "vmovlt.%#\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -538,7 +538,7 @@ (define_insn "mve_vmovlbq_" + VMOVLBQ)) + ] + "TARGET_HAVE_MVE" +- "vmovlb.%# %q0, %q1" ++ "vmovlb.%#\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -552,7 +552,7 @@ (define_insn "mve_vcvtpq_" + VCVTPQ)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vcvtp.%#.f%# %q0, %q1" ++ "vcvtp.%#.f%#\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -566,7 +566,7 @@ (define_insn "mve_vcvtnq_" + VCVTNQ)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vcvtn.%#.f%# %q0, %q1" ++ "vcvtn.%#.f%#\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -580,7 +580,7 @@ (define_insn "mve_vcvtmq_" + VCVTMQ)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vcvtm.%#.f%# %q0, %q1" ++ "vcvtm.%#.f%#\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -594,7 +594,7 @@ (define_insn "mve_vcvtaq_" + VCVTAQ)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vcvta.%#.f%# %q0, %q1" ++ "vcvta.%#.f%#\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -608,7 +608,7 @@ (define_insn "mve_vmvnq_n_" + VMVNQ_N)) + ] + "TARGET_HAVE_MVE" +- "vmvn.i%# %q0, %1" ++ "vmvn.i%#\t%q0, %1" + [(set_attr "type" "mve_move") + ]) + +@@ -622,7 +622,7 @@ (define_insn "mve_vrev16q_v16qi" + VREV16Q)) + ] + "TARGET_HAVE_MVE" +- "vrev16.8 %q0, %q1" ++ "vrev16.8\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -650,7 +650,7 @@ (define_insn "mve_vctpq" + VCTP)) + ] + "TARGET_HAVE_MVE" +- "vctp. %1" ++ "vctp.\t%1" + [(set_attr "type" "mve_move") + ]) + +@@ -694,7 +694,7 @@ (define_insn "mve_vbrsrq_n_f" + VBRSRQ_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vbrsr. %q0, %q1, %2" ++ "vbrsr.\t%q0, %q1, %2" + [(set_attr "type" "mve_move") + ]) + +@@ -976,7 +976,7 @@ (define_insn "mve_vbrsrq_n_" + VBRSRQ_N)) + ] + "TARGET_HAVE_MVE" +- "vbrsr.%# %q0, %q1, %2" ++ "vbrsr.%#\t%q0, %q1, %2" + [(set_attr "type" "mve_move") + ]) + +@@ -1864,7 +1864,7 @@ (define_insn "mve_vandq_f" + (match_operand:MVE_0 2 "s_register_operand" "w"))) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vand %q0, %q1, %q2" ++ "vand\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -1878,7 +1878,7 @@ (define_insn "mve_vbicq_f" + (match_operand:MVE_0 2 "s_register_operand" "w"))) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vbic %q0, %q1, %q2" ++ "vbic\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -1893,7 +1893,7 @@ (define_insn "mve_vbicq_n_" + VBICQ_N)) + ] + "TARGET_HAVE_MVE" +- "vbic.i%# %q0, %2" ++ "vbic.i%#\t%q0, %2" + [(set_attr "type" "mve_move") + ]) + +@@ -1967,7 +1967,7 @@ (define_insn "mve_vctpq_m" + VCTP_M)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vctpt. %1" ++ "vpst\;vctpt.\t%1" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -1982,7 +1982,7 @@ (define_insn "mve_vcvtbq_f16_f32v8hf" + VCVTBQ_F16_F32)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vcvtb.f16.f32 %q0, %q2" ++ "vcvtb.f16.f32\t%q0, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -1997,7 +1997,7 @@ (define_insn "mve_vcvttq_f16_f32v8hf" + VCVTTQ_F16_F32)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vcvtt.f16.f32 %q0, %q2" ++ "vcvtt.f16.f32\t%q0, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -2011,7 +2011,7 @@ (define_insn "mve_veorq_f" + (match_operand:MVE_0 2 "s_register_operand" "w"))) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "veor %q0, %q1, %q2" ++ "veor\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -2159,7 +2159,7 @@ (define_insn "mve_vmlaldavxq_s" + VMLALDAVXQ_S)) + ] + "TARGET_HAVE_MVE" +- "vmlaldavx.s%# %Q0, %R0, %q1, %q2" ++ "vmlaldavx.s%#\t%Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -2174,7 +2174,7 @@ (define_insn "mve_vmlsldavq_s" + VMLSLDAVQ_S)) + ] + "TARGET_HAVE_MVE" +- "vmlsldav.s%# %Q0, %R0, %q1, %q2" ++ "vmlsldav.s%#\t%Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -2189,7 +2189,7 @@ (define_insn "mve_vmlsldavxq_s" + VMLSLDAVXQ_S)) + ] + "TARGET_HAVE_MVE" +- "vmlsldavx.s%# %Q0, %R0, %q1, %q2" ++ "vmlsldavx.s%#\t%Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -2262,7 +2262,7 @@ (define_insn "mve_vornq_f" + (match_operand:MVE_0 1 "s_register_operand" "w"))) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vorn %q0, %q1, %q2" ++ "vorn\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -2276,7 +2276,7 @@ (define_insn "mve_vorrq_f" + (match_operand:MVE_0 2 "s_register_operand" "w"))) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vorr %q0, %q1, %q2" ++ "vorr\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -2426,7 +2426,7 @@ (define_insn "mve_vrmlaldavhxq_sv4si" + VRMLALDAVHXQ_S)) + ] + "TARGET_HAVE_MVE" +- "vrmlaldavhx.s32 %Q0, %R0, %q1, %q2" ++ "vrmlaldavhx.s32\t%Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -2561,7 +2561,7 @@ (define_insn "mve_vbicq_m_n_" + VBICQ_M_N)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vbict.i%# %q0, %2" ++ "vpst\;vbict.i%#\t%q0, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + ;; +@@ -2606,7 +2606,7 @@ (define_insn "mve_vcvtq_m_to_f_" + VCVTQ_M_TO_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vpst\;vcvtt.f%#.%# %q0, %q2" ++ "vpst\;vcvtt.f%#.%#\t%q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + ;; +@@ -2714,7 +2714,7 @@ (define_insn "mve_vshlcq_" + (match_dup 4)] + VSHLCQ))] + "TARGET_HAVE_MVE" +- "vshlc %q0, %1, %4") ++ "vshlc\t%q0, %1, %4") + + ;; + ;; [vabsq_m_s]) +@@ -3272,7 +3272,7 @@ (define_insn "mve_vmvnq_m_" + VMVNQ_M)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vmvnt %q0, %q2" ++ "vpst\;vmvnt\t%q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -3304,7 +3304,7 @@ (define_insn "@mve_vpselq_" + VPSELQ)) + ] + "TARGET_HAVE_MVE" +- "vpsel %q0, %q1, %q2" ++ "vpsel\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -3929,7 +3929,7 @@ (define_insn "mve_vcvtbq_m_f16_f32v8hf" + VCVTBQ_M_F16_F32)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vpst\;vcvtbt.f16.f32 %q0, %q2" ++ "vpst\;vcvtbt.f16.f32\t%q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -3945,7 +3945,7 @@ (define_insn "mve_vcvtbq_m_f32_f16v4sf" + VCVTBQ_M_F32_F16)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vpst\;vcvtbt.f32.f16 %q0, %q2" ++ "vpst\;vcvtbt.f32.f16\t%q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -3961,7 +3961,7 @@ (define_insn "mve_vcvttq_m_f16_f32v8hf" + VCVTTQ_M_F16_F32)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vpst\;vcvttt.f16.f32 %q0, %q2" ++ "vpst\;vcvttt.f16.f32\t%q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -3977,7 +3977,7 @@ (define_insn "mve_vcvttq_m_f32_f16v4sf" + VCVTTQ_M_F32_F16)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vpst\;vcvttt.f32.f16 %q0, %q2" ++ "vpst\;vcvttt.f32.f16\t%q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -4197,7 +4197,7 @@ (define_insn "mve_vmlaldavq_p_" + VMLALDAVQ_P)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vmlaldavt.%# %Q0, %R0, %q1, %q2" ++ "vpst\;vmlaldavt.%#\t%Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -4228,7 +4228,7 @@ (define_insn "mve_vmlsldavaq_s" + VMLSLDAVAQ_S)) + ] + "TARGET_HAVE_MVE" +- "vmlsldava.s%# %Q0, %R0, %q2, %q3" ++ "vmlsldava.s%#\t%Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") + ]) + +@@ -4244,7 +4244,7 @@ (define_insn "mve_vmlsldavaxq_s" + VMLSLDAVAXQ_S)) + ] + "TARGET_HAVE_MVE" +- "vmlsldavax.s%# %Q0, %R0, %q2, %q3" ++ "vmlsldavax.s%#\t%Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") + ]) + +@@ -4260,7 +4260,7 @@ (define_insn "mve_vmlsldavq_p_s" + VMLSLDAVQ_P_S)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vmlsldavt.s%# %Q0, %R0, %q1, %q2" ++ "vpst\;vmlsldavt.s%#\t%Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -4276,7 +4276,7 @@ (define_insn "mve_vmlsldavxq_p_s" + VMLSLDAVXQ_P_S)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vmlsldavxt.s%# %Q0, %R0, %q1, %q2" ++ "vpst\;vmlsldavxt.s%#\t%Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + ;; +@@ -4353,7 +4353,7 @@ (define_insn "mve_vmvnq_m_n_" + VMVNQ_M_N)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vmvnt.i%# %q0, %2" ++ "vpst\;vmvnt.i%#\t%q0, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + ;; +@@ -4384,7 +4384,7 @@ (define_insn "mve_vorrq_m_n_" + VORRQ_M_N)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vorrt.i%# %q0, %2" ++ "vpst\;vorrt.i%#\t%q0, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + ;; +@@ -4399,7 +4399,7 @@ (define_insn "@mve_vpselq_f" + VPSELQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vpsel %q0, %q1, %q2" ++ "vpsel\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -4575,7 +4575,7 @@ (define_insn "mve_vrev32q_m_fv8hf" + VREV32Q_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vpst\;vrev32t.16 %q0, %q2" ++ "vpst\;vrev32t.16\t%q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -4591,7 +4591,7 @@ (define_insn "mve_vrev32q_m_" + VREV32Q_M)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vrev32t.%# %q0, %q2" ++ "vpst\;vrev32t.%#\t%q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -4607,7 +4607,7 @@ (define_insn "mve_vrev64q_m_f" + VREV64Q_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vpst\;vrev64t.%# %q0, %q2" ++ "vpst\;vrev64t.%#\t%q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -4623,7 +4623,7 @@ (define_insn "mve_vrmlaldavhaxq_sv4si" + VRMLALDAVHAXQ_S)) + ] + "TARGET_HAVE_MVE" +- "vrmlaldavhax.s32 %Q0, %R0, %q2, %q3" ++ "vrmlaldavhax.s32\t%Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") + ]) + +@@ -4639,7 +4639,7 @@ (define_insn "mve_vrmlaldavhxq_p_sv4si" + VRMLALDAVHXQ_P_S)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vrmlaldavhxt.s32 %Q0, %R0, %q1, %q2" ++ "vpst\;vrmlaldavhxt.s32\t%Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -4655,7 +4655,7 @@ (define_insn "mve_vrmlsldavhaxq_sv4si" + VRMLSLDAVHAXQ_S)) + ] + "TARGET_HAVE_MVE" +- "vrmlsldavhax.s32 %Q0, %R0, %q2, %q3" ++ "vrmlsldavhax.s32\t%Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") + ]) + +@@ -4671,7 +4671,7 @@ (define_insn "mve_vrmlsldavhq_p_sv4si" + VRMLSLDAVHQ_P_S)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vrmlsldavht.s32 %Q0, %R0, %q1, %q2" ++ "vpst\;vrmlsldavht.s32\t%Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -4687,7 +4687,7 @@ (define_insn "mve_vrmlsldavhxq_p_sv4si" + VRMLSLDAVHXQ_P_S)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vrmlsldavhxt.s32 %Q0, %R0, %q1, %q2" ++ "vpst\;vrmlsldavhxt.s32\t%Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -4912,7 +4912,7 @@ (define_insn "mve_vrev16q_m_v16qi" + VREV16Q_M)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vrev16t.8 %q0, %q2" ++ "vpst\;vrev16t.8\t%q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -4944,7 +4944,7 @@ (define_insn "mve_vrmlaldavhq_p_v4si" + VRMLALDAVHQ_P)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vrmlaldavht.32 %Q0, %R0, %q1, %q2" ++ "vpst\;vrmlaldavht.32\t%Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -4960,7 +4960,7 @@ (define_insn "mve_vrmlsldavhaq_sv4si" + VRMLSLDAVHAQ_S)) + ] + "TARGET_HAVE_MVE" +- "vrmlsldavha.s32 %Q0, %R0, %q2, %q3" ++ "vrmlsldavha.s32\t%Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") + ]) + +@@ -5129,7 +5129,7 @@ (define_insn "mve_vandq_m_" + VANDQ_M)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vandt %q0, %q2, %q3" ++ "vpst\;vandt\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -5146,7 +5146,7 @@ (define_insn "mve_vbicq_m_" + VBICQ_M)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vbict %q0, %q2, %q3" ++ "vpst\;vbict\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -5214,7 +5214,7 @@ (define_insn "mve_veorq_m_" + VEORQ_M)) + ] + "TARGET_HAVE_MVE" +- "vpst\;veort %q0, %q2, %q3" ++ "vpst\;veort\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -5469,7 +5469,7 @@ (define_insn "mve_vornq_m_" + VORNQ_M)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vornt %q0, %q2, %q3" ++ "vpst\;vornt\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -5486,7 +5486,7 @@ (define_insn "mve_vorrq_m_" + VORRQ_M)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vorrt %q0, %q2, %q3" ++ "vpst\;vorrt\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -6658,7 +6658,7 @@ (define_insn "mve_vandq_m_f" + VANDQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vpst\;vandt %q0, %q2, %q3" ++ "vpst\;vandt\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -6675,7 +6675,7 @@ (define_insn "mve_vbicq_m_f" + VBICQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vpst\;vbict %q0, %q2, %q3" ++ "vpst\;vbict\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -6879,7 +6879,7 @@ (define_insn "mve_veorq_m_f" + VEORQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vpst\;veort %q0, %q2, %q3" ++ "vpst\;veort\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -7032,7 +7032,7 @@ (define_insn "mve_vornq_m_f" + VORNQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vpst\;vornt %q0, %q2, %q3" ++ "vpst\;vornt\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -7049,7 +7049,7 @@ (define_insn "mve_vorrq_m_f" + VORRQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vpst\;vorrt %q0, %q2, %q3" ++ "vpst\;vorrt\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -8492,7 +8492,7 @@ (define_insn "mve_vstrdq_scatter_shifted_offset_p_v2di_insn" + (match_operand:V2QI 3 "vpr_register_operand" "Up")] + VSTRDSSOQ))] + "TARGET_HAVE_MVE" +- "vpst\;vstrdt.64\t%q2, [%0, %q1, UXTW #3]" ++ "vpst\;vstrdt.64\t%q2, [%0, %q1, uxtw #3]" + [(set_attr "length" "8")]) + + ;; +@@ -8521,7 +8521,7 @@ (define_insn "mve_vstrdq_scatter_shifted_offset_v2di_insn" + (match_operand:V2DI 2 "s_register_operand" "w")] + VSTRDSSOQ))] + "TARGET_HAVE_MVE" +- "vstrd.64\t%q2, [%0, %q1, UXTW #3]" ++ "vstrd.64\t%q2, [%0, %q1, uxtw #3]" + [(set_attr "length" "4")]) + + ;; +@@ -9359,7 +9359,7 @@ (define_insn "mve_vstrwq_scatter_base_wb_p_v4si" + [(match_operand:V4SI 1 "s_register_operand" "0") + (match_operand:SI 2 "mve_vldrd_immediate" "Ri") + (match_operand:V4SI 3 "s_register_operand" "w") +- (match_operand:V4BI 4 "vpr_register_operand")] ++ (match_operand:V4BI 4 "vpr_register_operand" "Up")] + VSTRWSBWBQ)) + (set (match_operand:V4SI 0 "s_register_operand" "=w") + (unspec:V4SI [(match_dup 1) (match_dup 2)] +@@ -9408,9 +9408,9 @@ (define_insn "mve_vstrwq_scatter_base_wb_p_fv4sf" + [(set (mem:BLK (scratch)) + (unspec:BLK + [(match_operand:V4SI 1 "s_register_operand" "0") +- (match_operand:SI 2 "mve_vldrd_immediate" "Ri") ++ (match_operand:SI 2 "mve_vstrw_immediate" "Rl") + (match_operand:V4SF 3 "s_register_operand" "w") +- (match_operand:V4BI 4 "vpr_register_operand")] ++ (match_operand:V4BI 4 "vpr_register_operand" "Up")] + VSTRWQSBWB_F)) + (set (match_operand:V4SI 0 "s_register_operand" "=w") + (unspec:V4SI [(match_dup 1) (match_dup 2)] +@@ -9422,7 +9422,7 @@ (define_insn "mve_vstrwq_scatter_base_wb_p_fv4sf" + ops[0] = operands[1]; + ops[1] = operands[2]; + ops[2] = operands[3]; +- output_asm_insn ("vpst\;\tvstrwt.u32\t%q2, [%q0, %1]!",ops); ++ output_asm_insn ("vpst\;vstrwt.u32\t%q2, [%q0, %1]!",ops); + return ""; + } + [(set_attr "length" "8")]) +@@ -9461,7 +9461,7 @@ (define_insn "mve_vstrdq_scatter_base_wb_p_v2di" + [(match_operand:V2DI 1 "s_register_operand" "0") + (match_operand:SI 2 "mve_vldrd_immediate" "Ri") + (match_operand:V2DI 3 "s_register_operand" "w") +- (match_operand:V2QI 4 "vpr_register_operand")] ++ (match_operand:V2QI 4 "vpr_register_operand" "Up")] + VSTRDSBWBQ)) + (set (match_operand:V2DI 0 "s_register_operand" "=w") + (unspec:V2DI [(match_dup 1) (match_dup 2)] +@@ -9473,7 +9473,7 @@ (define_insn "mve_vstrdq_scatter_base_wb_p_v2di" + ops[0] = operands[1]; + ops[1] = operands[2]; + ops[2] = operands[3]; +- output_asm_insn ("vpst;vstrdt.u64\t%q2, [%q0, %1]!",ops); ++ output_asm_insn ("vpst\;vstrdt.u64\t%q2, [%q0, %1]!",ops); + return ""; + } + [(set_attr "length" "8")]) +@@ -9782,7 +9782,7 @@ (define_expand "mve_vldrdq_gather_base_nowb_z_v2di" + + (define_insn "get_fpscr_nzcvqc" + [(set (match_operand:SI 0 "register_operand" "=r") +- (unspec:SI [(reg:SI VFPCC_REGNUM)] UNSPEC_GET_FPSCR_NZCVQC))] ++ (unspec_volatile:SI [(reg:SI VFPCC_REGNUM)] UNSPEC_GET_FPSCR_NZCVQC))] + "TARGET_HAVE_MVE" + "vmrs\\t%0, FPSCR_nzcvqc" + [(set_attr "type" "mve_move")]) +--- a/src/gcc/config/arm/predicates.md ++++ b/src/gcc/config/arm/predicates.md +@@ -73,13 +73,13 @@ (define_predicate "mve_imm_32" + (define_predicate "mve_imm_selective_upto_8" + (match_test "satisfies_constraint_Rg (op)")) + +-;; True if the immediate is the range +/- 1016 and multiple of 8 for MVE. +-(define_constraint "Ri" +- "@internal In Thumb-2 state a constant is multiple of 8 and in range +- of -/+ 1016 for MVE" +- (and (match_code "const_int") +- (match_test "TARGET_HAVE_MVE && (-1016 <= ival) && (ival <= 1016) +- && ((ival % 8) == 0)"))) ++;; True if the immediate is multiple of 8 and in range of -/+ 1016 for MVE. ++(define_predicate "mve_vldrd_immediate" ++ (match_test "satisfies_constraint_Ri (op)")) ++ ++;; True if the immediate is multiple of 2 and in range of -/+ 252 for MVE. ++(define_predicate "mve_vstrw_immediate" ++ (match_test "satisfies_constraint_Rl (op)")) + + ; Predicate for stack protector guard's address in + ; stack_protect_combined_set_insn and stack_protect_combined_test_insn patterns +--- a/src/gcc/config/arm/vfp.md ++++ b/src/gcc/config/arm/vfp.md +@@ -2138,7 +2138,7 @@ (define_insn "get_fpscr" + (define_insn_and_split "no_literal_pool_df_immediate" + [(set (match_operand:DF 0 "s_register_operand" "=w") + (match_operand:DF 1 "const_double_operand" "F")) +- (clobber (match_operand:DF 2 "s_register_operand" "=r"))] ++ (clobber (match_operand:DI 2 "s_register_operand" "=r"))] + "arm_disable_literal_pool + && TARGET_VFP_BASE + && !arm_const_double_rtx (operands[1]) +@@ -2153,8 +2153,9 @@ (define_insn_and_split "no_literal_pool_df_immediate" + unsigned HOST_WIDE_INT ival = zext_hwi (buf[order], 32); + ival |= (zext_hwi (buf[1 - order], 32) << 32); + rtx cst = gen_int_mode (ival, DImode); +- emit_move_insn (simplify_gen_subreg (DImode, operands[2], DFmode, 0), cst); +- emit_move_insn (operands[0], operands[2]); ++ emit_move_insn (operands[2], cst); ++ emit_move_insn (operands[0], ++ simplify_gen_subreg (DFmode, operands[2], DImode, 0)); + DONE; + } + ) +--- a/src/gcc/config/avr/avr-dimode.md ++++ b/src/gcc/config/avr/avr-dimode.md +@@ -455,12 +455,18 @@ (define_expand "conditional_jump" + (define_expand "cbranch4" + [(set (pc) + (if_then_else (match_operator 0 "ordered_comparison_operator" +- [(match_operand:ALL8 1 "register_operand" "") +- (match_operand:ALL8 2 "nonmemory_operand" "")]) +- (label_ref (match_operand 3 "" "")) +- (pc)))] ++ [(match_operand:ALL8 1 "register_operand") ++ (match_operand:ALL8 2 "nonmemory_operand")]) ++ (label_ref (match_operand 3)) ++ (pc)))] + "avr_have_dimode" + { ++ int icode = (int) GET_CODE (operands[0]); ++ ++ targetm.canonicalize_comparison (&icode, &operands[1], &operands[2], false); ++ operands[0] = gen_rtx_fmt_ee ((enum rtx_code) icode, ++ VOIDmode, operands[1], operands[2]); ++ + rtx acc_a = gen_rtx_REG (mode, ACC_A); + + avr_fix_inputs (operands, 1 << 2, regmask (mode, ACC_A)); +@@ -490,8 +496,8 @@ (define_insn_and_split "cbranch_2_split" + (if_then_else (match_operator 0 "ordered_comparison_operator" + [(reg:ALL8 ACC_A) + (reg:ALL8 ACC_B)]) +- (label_ref (match_operand 1 "" "")) +- (pc)))] ++ (label_ref (match_operand 1)) ++ (pc)))] + "avr_have_dimode" + "#" + "&& reload_completed" +@@ -544,8 +550,8 @@ (define_insn_and_split "cbranch_const_2_split" + (if_then_else (match_operator 0 "ordered_comparison_operator" + [(reg:ALL8 ACC_A) + (match_operand:ALL8 1 "const_operand" "n Ynn")]) +- (label_ref (match_operand 2 "" "")) +- (pc))) ++ (label_ref (match_operand 2 "" "")) ++ (pc))) + (clobber (match_scratch:QI 3 "=&d"))] + "avr_have_dimode + && !s8_operand (operands[1], VOIDmode)" +--- a/src/gcc/config/avr/avr-passes.def ++++ b/src/gcc/config/avr/avr-passes.def +@@ -43,3 +43,23 @@ INSERT_PASS_BEFORE (pass_free_cfg, 1, avr_pass_recompute_notes); + insns withaout any insns in between. */ + + INSERT_PASS_AFTER (pass_expand, 1, avr_pass_casesi); ++ ++/* If-else decision trees generated for switch / case may produce sequences ++ like ++ ++ SREG = compare (reg, val); ++ if (SREG == 0) goto label1; ++ SREG = compare (reg, 1 + val); ++ if (SREG >= 0) goto label2; ++ ++ which can be optimized to ++ ++ SREG = compare (reg, val); ++ if (SREG == 0) goto label1; ++ if (SREG >= 0) goto label2; ++ ++ The optimal place for such a pass would be directly after expand, but ++ it's not possible for a jump insn to target more than one code label. ++ Hence, run a mini pass right before split2 which introduces REG_CC. */ ++ ++INSERT_PASS_BEFORE (pass_split_after_reload, 1, avr_pass_ifelse); +--- a/src/gcc/config/avr/avr-protos.h ++++ b/src/gcc/config/avr/avr-protos.h +@@ -58,6 +58,8 @@ extern const char *ret_cond_branch (rtx x, int len, int reverse); + extern const char *avr_out_movpsi (rtx_insn *, rtx*, int*); + extern const char *avr_out_sign_extend (rtx_insn *, rtx*, int*); + extern const char *avr_out_insert_notbit (rtx_insn *, rtx*, rtx, int*); ++extern const char *avr_out_plus_set_ZN (rtx*, int*); ++extern const char *avr_out_cmp_ext (rtx*, enum rtx_code, int*); + + extern const char *ashlqi3_out (rtx_insn *insn, rtx operands[], int *len); + extern const char *ashlhi3_out (rtx_insn *insn, rtx operands[], int *len); +@@ -112,8 +114,6 @@ extern int jump_over_one_insn_p (rtx_insn *insn, rtx dest); + + extern void avr_final_prescan_insn (rtx_insn *insn, rtx *operand, + int num_operands); +-extern int avr_simplify_comparison_p (machine_mode mode, +- RTX_CODE op, rtx x); + extern RTX_CODE avr_normalize_condition (RTX_CODE condition); + extern void out_shift_with_cnt (const char *templ, rtx_insn *insn, + rtx operands[], int *len, int t_len); +@@ -145,6 +145,7 @@ extern rtx tmp_reg_rtx; + extern rtx zero_reg_rtx; + extern rtx all_regs_rtx[32]; + extern rtx rampz_rtx; ++extern rtx cc_reg_rtx; + + #endif /* RTX_CODE */ + +@@ -160,6 +161,7 @@ class rtl_opt_pass; + extern rtl_opt_pass *make_avr_pass_pre_proep (gcc::context *); + extern rtl_opt_pass *make_avr_pass_recompute_notes (gcc::context *); + extern rtl_opt_pass *make_avr_pass_casesi (gcc::context *); ++extern rtl_opt_pass *make_avr_pass_ifelse (gcc::context *); + + /* From avr-log.cc */ + +--- a/src/gcc/config/avr/avr.cc ++++ b/src/gcc/config/avr/avr.cc +@@ -359,6 +359,41 @@ public: + } + }; // avr_pass_casesi + ++ ++static const pass_data avr_pass_data_ifelse = ++{ ++ RTL_PASS, // type ++ "", // name (will be patched) ++ OPTGROUP_NONE, // optinfo_flags ++ TV_DF_SCAN, // tv_id ++ 0, // properties_required ++ 0, // properties_provided ++ 0, // properties_destroyed ++ 0, // todo_flags_start ++ TODO_df_finish | TODO_df_verify // todo_flags_finish ++}; ++ ++class avr_pass_ifelse : public rtl_opt_pass ++{ ++public: ++ avr_pass_ifelse (gcc::context *ctxt, const char *name) ++ : rtl_opt_pass (avr_pass_data_ifelse, ctxt) ++ { ++ this->name = name; ++ } ++ ++ void avr_rest_of_handle_ifelse (function*); ++ ++ virtual bool gate (function*) { return optimize > 0; } ++ ++ virtual unsigned int execute (function *func) ++ { ++ avr_rest_of_handle_ifelse (func); ++ ++ return 0; ++ } ++}; // avr_pass_ifelse ++ + } // anon namespace + + rtl_opt_pass* +@@ -373,6 +408,12 @@ make_avr_pass_casesi (gcc::context *ctxt) + return new avr_pass_casesi (ctxt, "avr-casesi"); + } + ++rtl_opt_pass* ++make_avr_pass_ifelse (gcc::context *ctxt) ++{ ++ return new avr_pass_ifelse (ctxt, "avr-ifelse"); ++} ++ + + /* Make one parallel insn with all the patterns from insns i[0]..i[5]. */ + +@@ -686,6 +727,304 @@ avr_pass_casesi::avr_rest_of_handle_casesi (function *func) + } + + ++/* A helper for the next method. Suppose we have two conditional branches ++ ++ if (reg xval1) goto label1; ++ if (reg xval2) goto label2; ++ ++ If the second comparison is redundant and there is a code such ++ that the sequence can be performed as ++ ++ REG_CC = compare (reg, xval1); ++ if (REG_CC 0) goto label1; ++ if (REG_CC 0) goto label2; ++ ++ then return . Otherwise, return UNKNOWN. ++ xval1 and xval2 are CONST_INT, and mode is the scalar int mode in which ++ the comparison will be carried out. reverse_cond1 can be set to reverse ++ condition cond1. This is useful if the second comparison does not follow ++ the first one, but is located after label1 like in: ++ ++ if (reg xval1) goto label1; ++ ... ++ label1: ++ if (reg xval2) goto label2; */ ++ ++static enum rtx_code ++avr_redundant_compare (enum rtx_code cond1, rtx xval1, ++ enum rtx_code cond2, rtx xval2, ++ machine_mode mode, bool reverse_cond1) ++{ ++ HOST_WIDE_INT ival1 = INTVAL (xval1); ++ HOST_WIDE_INT ival2 = INTVAL (xval2); ++ ++ unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); ++ unsigned HOST_WIDE_INT uval1 = mask & UINTVAL (xval1); ++ unsigned HOST_WIDE_INT uval2 = mask & UINTVAL (xval2); ++ ++ if (reverse_cond1) ++ cond1 = reverse_condition (cond1); ++ ++ if (cond1 == EQ) ++ { ++ //////////////////////////////////////////////// ++ // A sequence like ++ // if (reg == val) goto label1; ++ // if (reg > val) goto label2; ++ // can be re-written using the same, simple comparison like in: ++ // REG_CC = compare (reg, val) ++ // if (REG_CC == 0) goto label1; ++ // if (REG_CC >= 0) goto label2; ++ if (ival1 == ival2 ++ && (cond2 == GT || cond2 == GTU)) ++ return avr_normalize_condition (cond2); ++ ++ // Similar, but the input sequence is like ++ // if (reg == val) goto label1; ++ // if (reg >= val) goto label2; ++ if (ival1 == ival2 ++ && (cond2 == GE || cond2 == GEU)) ++ return cond2; ++ ++ // Similar, but the input sequence is like ++ // if (reg == val) goto label1; ++ // if (reg >= val + 1) goto label2; ++ if ((cond2 == GE && ival2 == 1 + ival1) ++ || (cond2 == GEU && uval2 == 1 + uval1)) ++ return cond2; ++ ++ // Similar, but the input sequence is like ++ // if (reg == val) goto label1; ++ // if (reg > val - 1) goto label2; ++ if ((cond2 == GT && ival2 == ival1 - 1) ++ || (cond2 == GTU && uval2 == uval1 - 1)) ++ return avr_normalize_condition (cond2); ++ ++ ///////////////////////////////////////////////////////// ++ // A sequence like ++ // if (reg == val) goto label1; ++ // if (reg < 1 + val) goto label2; ++ // can be re-written as ++ // REG_CC = compare (reg, val) ++ // if (REG_CC == 0) goto label1; ++ // if (REG_CC < 0) goto label2; ++ if ((cond2 == LT && ival2 == 1 + ival1) ++ || (cond2 == LTU && uval2 == 1 + uval1)) ++ return cond2; ++ ++ // Similar, but with an input sequence like ++ // if (reg == val) goto label1; ++ // if (reg <= val) goto label2; ++ if (ival1 == ival2 ++ && (cond2 == LE || cond2 == LEU)) ++ return avr_normalize_condition (cond2); ++ ++ // Similar, but with an input sequence like ++ // if (reg == val) goto label1; ++ // if (reg < val) goto label2; ++ if (ival1 == ival2 ++ && (cond2 == LT || cond2 == LTU)) ++ return cond2; ++ ++ // Similar, but with an input sequence like ++ // if (reg == val) goto label1; ++ // if (reg <= val - 1) goto label2; ++ if ((cond2 == LE && ival2 == ival1 - 1) ++ || (cond2 == LEU && uval2 == uval1 - 1)) ++ return avr_normalize_condition (cond2); ++ ++ } // cond1 == EQ ++ ++ return UNKNOWN; ++} ++ ++ ++/* If-else decision trees generated for switch / case may produce sequences ++ like ++ ++ SREG = compare (reg, val); ++ if (SREG == 0) goto label1; ++ SREG = compare (reg, 1 + val); ++ if (SREG >= 0) goto label2; ++ ++ which can be optimized to ++ ++ SREG = compare (reg, val); ++ if (SREG == 0) goto label1; ++ if (SREG >= 0) goto label2; ++ ++ The optimal place for such a pass would be directly after expand, but ++ it's not possible for a jump insn to target more than one code label. ++ Hence, run a mini pass right before split2 which introduces REG_CC. */ ++ ++void ++avr_pass_ifelse::avr_rest_of_handle_ifelse (function*) ++{ ++ rtx_insn *next_insn; ++ ++ for (rtx_insn *insn = get_insns(); insn; insn = next_insn) ++ { ++ next_insn = next_nonnote_nondebug_insn (insn); ++ ++ if (! next_insn) ++ break; ++ ++ // Search for two cbranch insns. The first one is a cbranch. ++ // Filter for "cbranch4_insn" with mode in QI, HI, PSI, SI. ++ ++ if (! JUMP_P (insn)) ++ continue; ++ ++ int icode1 = recog_memoized (insn); ++ ++ if (icode1 != CODE_FOR_cbranchqi4_insn ++ && icode1 != CODE_FOR_cbranchhi4_insn ++ && icode1 != CODE_FOR_cbranchpsi4_insn ++ && icode1 != CODE_FOR_cbranchsi4_insn) ++ continue; ++ ++ rtx_jump_insn *insn1 = as_a (insn); ++ rtx_jump_insn *insn2 = nullptr; ++ bool follow_label1 = false; ++ ++ // Extract the operands of the first insn: ++ // $0 = comparison operator ($1, $2) ++ // $1 = reg ++ // $2 = reg or const_int ++ // $3 = code_label ++ // $4 = optional SCRATCH for HI, PSI, SI cases. ++ ++ const auto &op = recog_data.operand; ++ ++ extract_insn (insn1); ++ rtx xop1[5] = { op[0], op[1], op[2], op[3], op[4] }; ++ int n_operands = recog_data.n_operands; ++ ++ // For now, we can optimize cbranches that follow an EQ cbranch, ++ // and cbranches that follow the label of a NE cbranch. ++ ++ if (GET_CODE (xop1[0]) == EQ ++ && JUMP_P (next_insn) ++ && recog_memoized (next_insn) == icode1) ++ { ++ // The 2nd cbranch insn follows insn1, i.e. is located in the ++ // fallthrough path of insn1. ++ ++ insn2 = as_a (next_insn); ++ } ++ else if (GET_CODE (xop1[0]) == NE) ++ { ++ // insn1 might branch to a label followed by a cbranch. ++ ++ rtx target1 = JUMP_LABEL (insn1); ++ rtx_insn *code_label1 = JUMP_LABEL_AS_INSN (insn1); ++ rtx_insn *next = next_nonnote_nondebug_insn (code_label1); ++ rtx_insn *barrier = prev_nonnote_nondebug_insn (code_label1); ++ ++ if (// Target label of insn1 is used exactly once and ++ // is not a fallthru, i.e. is preceded by a barrier. ++ LABEL_NUSES (target1) == 1 ++ && barrier ++ && BARRIER_P (barrier) ++ // Following the target label is a cbranch of the same kind. ++ && next ++ && JUMP_P (next) ++ && recog_memoized (next) == icode1) ++ { ++ follow_label1 = true; ++ insn2 = as_a (next); ++ } ++ } ++ ++ if (! insn2) ++ continue; ++ ++ // Also extract operands of insn2, and filter for REG + CONST_INT ++ // comparsons against the same register. ++ ++ extract_insn (insn2); ++ rtx xop2[5] = { op[0], op[1], op[2], op[3], op[4] }; ++ ++ if (! rtx_equal_p (xop1[1], xop2[1]) ++ || ! CONST_INT_P (xop1[2]) ++ || ! CONST_INT_P (xop2[2])) ++ continue; ++ ++ machine_mode mode = GET_MODE (xop1[1]); ++ enum rtx_code code1 = GET_CODE (xop1[0]); ++ enum rtx_code code2 = GET_CODE (xop2[0]); ++ ++ code2 = avr_redundant_compare (code1, xop1[2], code2, xop2[2], ++ mode, follow_label1); ++ if (code2 == UNKNOWN) ++ continue; ++ ++ ////////////////////////////////////////////////////// ++ // Found a replacement. ++ ++ if (dump_file) ++ { ++ fprintf (dump_file, "\n;; Found chain of jump_insn %d and" ++ " jump_insn %d, follow_label1=%d:\n", ++ INSN_UID (insn1), INSN_UID (insn2), follow_label1); ++ print_rtl_single (dump_file, PATTERN (insn1)); ++ print_rtl_single (dump_file, PATTERN (insn2)); ++ } ++ ++ if (! follow_label1) ++ next_insn = next_nonnote_nondebug_insn (insn2); ++ ++ // Pop the new branch conditions and the new comparison. ++ // Prematurely split into compare + branch so that we can drop ++ // the 2nd comparison. The following pass, split2, splits all ++ // insns for REG_CC, and it should still work as usual even when ++ // there are already some REG_CC insns around. ++ ++ rtx xcond1 = gen_rtx_fmt_ee (code1, VOIDmode, cc_reg_rtx, const0_rtx); ++ rtx xcond2 = gen_rtx_fmt_ee (code2, VOIDmode, cc_reg_rtx, const0_rtx); ++ rtx xpat1 = gen_branch (xop1[3], xcond1); ++ rtx xpat2 = gen_branch (xop2[3], xcond2); ++ rtx xcompare = NULL_RTX; ++ ++ if (mode == QImode) ++ { ++ gcc_assert (n_operands == 4); ++ xcompare = gen_cmpqi3 (xop1[1], xop1[2]); ++ } ++ else ++ { ++ gcc_assert (n_operands == 5); ++ rtx (*gen_cmp)(rtx,rtx,rtx) ++ = mode == HImode ? gen_gen_comparehi ++ : mode == PSImode ? gen_gen_comparepsi ++ : gen_gen_comparesi; // SImode ++ xcompare = gen_cmp (xop1[1], xop1[2], xop1[4]); ++ } ++ ++ // Emit that stuff. ++ ++ rtx_insn *cmp = emit_insn_before (xcompare, insn1); ++ rtx_jump_insn *branch1 = emit_jump_insn_before (xpat1, insn1); ++ rtx_jump_insn *branch2 = emit_jump_insn_before (xpat2, insn2); ++ ++ JUMP_LABEL (branch1) = xop1[3]; ++ JUMP_LABEL (branch2) = xop2[3]; ++ // delete_insn() decrements LABEL_NUSES when deleting a JUMP_INSN, but ++ // when we pop a new JUMP_INSN, do it by hand. ++ ++LABEL_NUSES (xop1[3]); ++ ++LABEL_NUSES (xop2[3]); ++ ++ delete_insn (insn1); ++ delete_insn (insn2); ++ ++ // As a side effect, also recog the new insns. ++ gcc_assert (valid_insn_p (cmp)); ++ gcc_assert (valid_insn_p (branch1)); ++ gcc_assert (valid_insn_p (branch2)); ++ } // loop insns ++} ++ ++ + /* Set `avr_arch' as specified by `-mmcu='. + Return true on success. */ + +@@ -1019,6 +1358,19 @@ avr_no_gccisr_function_p (tree func) + return avr_lookup_function_attribute1 (func, "no_gccisr"); + } + ++ ++/* Implement `TARGET_CAN_INLINE_P'. */ ++/* Some options like -mgas_isr_prologues depend on optimization level, ++ and the inliner might think that due to different options, inlining ++ is not permitted; see PR104327. */ ++ ++static bool ++avr_can_inline_p (tree /* caller */, tree /* callee */) ++{ ++ // No restrictions whatsoever. ++ return true; ++} ++ + /* Implement `TARGET_SET_CURRENT_FUNCTION'. */ + /* Sanity cheching for above function attributes. */ + +@@ -3173,28 +3525,6 @@ avr_asm_final_postscan_insn (FILE *stream, rtx_insn *insn, rtx*, int) + } + + +-/* Return 0 if undefined, 1 if always true or always false. */ +- +-int +-avr_simplify_comparison_p (machine_mode mode, RTX_CODE op, rtx x) +-{ +- unsigned int max = (mode == QImode ? 0xff : +- mode == HImode ? 0xffff : +- mode == PSImode ? 0xffffff : +- mode == SImode ? 0xffffffff : 0); +- if (max && op && CONST_INT_P (x)) +- { +- if (unsigned_condition (op) != op) +- max >>= 1; +- +- if (max != (INTVAL (x) & max) +- && INTVAL (x) != 0xff) +- return 1; +- } +- return 0; +-} +- +- + /* Worker function for `FUNCTION_ARG_REGNO_P'. */ + /* Returns nonzero if REGNO is the number of a hard + register in which function arguments are sometimes passed. */ +@@ -5677,29 +6007,36 @@ avr_frame_pointer_required_p (void) + || get_frame_size () > 0); + } + +-/* Returns the condition of compare insn INSN, or UNKNOWN. */ ++ ++/* Returns the condition of the branch following INSN, where INSN is some ++ comparison. If the next insn is not a branch or the condition code set ++ by INSN might be used by more insns than the next one, return UNKNOWN. ++ For now, just look at the next insn, which misses some opportunities like ++ following jumps. */ + + static RTX_CODE + compare_condition (rtx_insn *insn) + { +- rtx_insn *next = next_real_insn (insn); ++ rtx set; ++ rtx_insn *next = next_real_nondebug_insn (insn); + +- if (next && JUMP_P (next)) ++ if (next ++ && JUMP_P (next) ++ // If SREG does not die in the next insn, it is used in more than one ++ // branch. This can happen due to pass .avr-ifelse optimizations. ++ && dead_or_set_regno_p (next, REG_CC) ++ // Branches are (set (pc) (if_then_else (COND (...)))). ++ && (set = single_set (next)) ++ && GET_CODE (SET_SRC (set)) == IF_THEN_ELSE) + { +- rtx pat = PATTERN (next); +- if (GET_CODE (pat) == PARALLEL) +- pat = XVECEXP (pat, 0, 0); +- rtx src = SET_SRC (pat); +- +- if (IF_THEN_ELSE == GET_CODE (src)) +- return GET_CODE (XEXP (src, 0)); ++ return GET_CODE (XEXP (SET_SRC (set), 0)); + } + + return UNKNOWN; + } + + +-/* Returns true iff INSN is a tst insn that only tests the sign. */ ++/* Returns true if INSN is a tst insn that only tests the sign. */ + + static bool + compare_sign_p (rtx_insn *insn) +@@ -5709,23 +6046,95 @@ compare_sign_p (rtx_insn *insn) + } + + +-/* Returns true iff the next insn is a JUMP_INSN with a condition +- that needs to be swapped (GT, GTU, LE, LEU). */ ++/* Returns true if INSN is a compare insn with the EQ or NE condition. */ + + static bool +-compare_diff_p (rtx_insn *insn) ++compare_eq_p (rtx_insn *insn) + { + RTX_CODE cond = compare_condition (insn); +- return (cond == GT || cond == GTU || cond == LE || cond == LEU) ? cond : 0; ++ return (cond == EQ || cond == NE); + } + +-/* Returns true iff INSN is a compare insn with the EQ or NE condition. */ + +-static bool +-compare_eq_p (rtx_insn *insn) ++/* Implement `TARGET_CANONICALIZE_COMPARISON'. */ ++/* Basically tries to convert "difficult" comparisons like GT[U] ++ and LE[U] to simple ones. Some asymmetric comparisons can be ++ transformed to EQ or NE against zero. */ ++ ++static void ++avr_canonicalize_comparison (int *icode, rtx *op0, rtx *op1, bool op0_fixed) + { +- RTX_CODE cond = compare_condition (insn); +- return (cond == EQ || cond == NE); ++ enum rtx_code code = (enum rtx_code) *icode; ++ machine_mode mode = GET_MODE (*op0); ++ ++ bool signed_p = code == GT || code == LE; ++ bool unsigned_p = code == GTU || code == LEU; ++ bool difficult_p = signed_p || unsigned_p; ++ ++ if (// Only do integers and fixed-points. ++ (! SCALAR_INT_MODE_P (mode) ++ && ! ALL_SCALAR_FIXED_POINT_MODE_P (mode)) ++ // Only do comparisons against a register. ++ || ! register_operand (*op0, mode)) ++ return; ++ ++ // Canonicalize "difficult" reg-reg comparisons. ++ ++ if (! op0_fixed ++ && difficult_p ++ && register_operand (*op1, mode)) ++ { ++ std::swap (*op0, *op1); ++ *icode = (int) swap_condition (code); ++ return; ++ } ++ ++ // Canonicalize comparisons against compile-time constants. ++ ++ if (CONST_INT_P (*op1) ++ || CONST_FIXED_P (*op1)) ++ { ++ // INT_MODE of the same size. ++ scalar_int_mode imode = int_mode_for_mode (mode).require (); ++ ++ unsigned HOST_WIDE_INT mask = GET_MODE_MASK (imode); ++ unsigned HOST_WIDE_INT maxval = signed_p ? mask >> 1 : mask; ++ ++ // Convert value *op1 to imode. ++ rtx xval = simplify_gen_subreg (imode, *op1, mode, 0); ++ ++ // Canonicalize difficult comparisons against const. ++ if (difficult_p ++ && (UINTVAL (xval) & mask) != maxval) ++ { ++ // Convert *op0 > *op1 to *op0 >= 1 + *op1. ++ // Convert *op0 <= *op1 to *op0 < 1 + *op1. ++ xval = simplify_binary_operation (PLUS, imode, xval, const1_rtx); ++ ++ // Convert value back to its original mode. ++ *op1 = simplify_gen_subreg (mode, xval, imode, 0); ++ ++ // Map > to >= and <= to <. ++ *icode = (int) avr_normalize_condition (code); ++ ++ return; ++ } ++ ++ // Some asymmetric comparisons can be turned into EQ or NE. ++ if (code == LTU && xval == const1_rtx) ++ { ++ *icode = (int) EQ; ++ *op1 = CONST0_RTX (mode); ++ return; ++ } ++ ++ if (code == GEU && xval == const1_rtx) ++ { ++ *icode = (int) NE; ++ *op1 = CONST0_RTX (mode); ++ return; ++ } ++ } + } + + +@@ -6018,6 +6427,68 @@ avr_out_tstsi (rtx_insn *insn, rtx *op, int *plen) + } + + ++/* Output a comparison of a zero- or sign-extended register against a ++ plain register. CODE is SIGN_EXTEND or ZERO_EXTEND. Return "". ++ ++ PLEN != 0: Set *PLEN to the code length in words. Don't output anything. ++ PLEN == 0: Print instructions. */ ++ ++const char* ++avr_out_cmp_ext (rtx xop[], enum rtx_code code, int *plen) ++{ ++ // The smaller reg is the one that's to be extended. Get its index as z. ++ int z = GET_MODE_SIZE (GET_MODE (xop[1])) < GET_MODE_SIZE (GET_MODE (xop[0])); ++ rtx zreg = xop[z]; ++ rtx reg = xop[1 - z]; ++ machine_mode mode = GET_MODE (reg); ++ machine_mode zmode = GET_MODE (zreg); ++ rtx zex; ++ ++ if (plen) ++ *plen = 0; ++ ++ // zex holds the extended bytes above zreg. This is 0 for ZERO_EXTEND, ++ // and 0 or -1 for SIGN_EXTEND. ++ ++ if (code == SIGN_EXTEND) ++ { ++ // Sign-extend the high-byte of zreg to tmp_reg. ++ int zmsb = GET_MODE_SIZE (zmode) - 1; ++ rtx xzmsb = simplify_gen_subreg (QImode, zreg, zmode, zmsb); ++ ++ avr_asm_len ("mov __tmp_reg__,%0" CR_TAB ++ "rol __tmp_reg__" CR_TAB ++ "sbc __tmp_reg__,__tmp_reg__", &xzmsb, plen, 3); ++ zex = tmp_reg_rtx; ++ } ++ else if (code == ZERO_EXTEND) ++ { ++ zex = zero_reg_rtx; ++ } ++ else ++ gcc_unreachable(); ++ ++ // Now output n_bytes bytes of the very comparison. ++ ++ int n_bytes = GET_MODE_SIZE (mode); ++ ++ avr_asm_len ("cp %0,%1", xop, plen, 1); ++ ++ for (int b = 1; b < n_bytes; ++b) ++ { ++ rtx regs[2]; ++ regs[1 - z] = simplify_gen_subreg (QImode, reg, mode, b); ++ regs[z] = (b < GET_MODE_SIZE (zmode) ++ ? simplify_gen_subreg (QImode, zreg, zmode, b) ++ : zex); ++ ++ avr_asm_len ("cpc %0,%1", regs, plen, 1); ++ } ++ ++ return ""; ++} ++ ++ + /* Generate asm equivalent for various shifts. This only handles cases + that are not already carefully hand-optimized in ?sh??i3_out. + +@@ -8160,6 +8631,122 @@ avr_out_plus (rtx insn, rtx *xop, int *plen, int *pcc, bool out_label) + } + + ++/* Output an instruction sequence for addition of REG in XOP[0] and CONST_INT ++ in XOP[1] in such a way that SREG.Z and SREG.N are set according to the ++ result. XOP[2] might be a d-regs clobber register. If XOP[2] is SCRATCH, ++ then the addition can be performed without a clobber reg. Return "". ++ ++ If PLEN == NULL, then output the instructions. ++ If PLEN != NULL, then set *PLEN to the length of the sequence in words. */ ++ ++const char* ++avr_out_plus_set_ZN (rtx *xop, int *plen) ++{ ++ if (plen) ++ *plen = 0; ++ ++ // Register to compare and value to compare against. ++ rtx xreg = xop[0]; ++ rtx xval = xop[1]; ++ ++ machine_mode mode = GET_MODE (xreg); ++ ++ // Number of bytes to operate on. ++ int n_bytes = GET_MODE_SIZE (mode); ++ ++ if (n_bytes == 1) ++ { ++ if (INTVAL (xval) == 1) ++ return avr_asm_len ("inc %0", xop, plen, 1); ++ ++ if (INTVAL (xval) == -1) ++ return avr_asm_len ("dec %0", xop, plen, 1); ++ } ++ ++ if (n_bytes == 2 ++ && test_hard_reg_class (ADDW_REGS, xreg) ++ && IN_RANGE (INTVAL (xval), 1, 63)) ++ { ++ // Add 16-bit value in [1..63] to a w register. ++ return avr_asm_len ("adiw %0, %1", xop, plen, 1); ++ } ++ ++ // Addition won't work; subtract the negative of XVAL instead. ++ xval = simplify_unary_operation (NEG, mode, xval, mode); ++ ++ // Value (0..0xff) held in clobber register xop[2] or -1 if unknown. ++ int clobber_val = -1; ++ ++ // [0] = Current sub-register. ++ // [1] = Current partial xval. ++ // [2] = 8-bit clobber d-register or SCRATCH. ++ rtx op[3]; ++ op[2] = xop[2]; ++ ++ // Work byte-wise from LSB to MSB. The lower two bytes might be ++ // SBIW'ed in one go. ++ for (int i = 0; i < n_bytes; ++i) ++ { ++ op[0] = simplify_gen_subreg (QImode, xreg, mode, i); ++ ++ if (i == 0 ++ && n_bytes >= 2 ++ && test_hard_reg_class (ADDW_REGS, op[0])) ++ { ++ op[1] = simplify_gen_subreg (HImode, xval, mode, 0); ++ if (IN_RANGE (INTVAL (op[1]), 0, 63)) ++ { ++ // SBIW can handle the lower 16 bits. ++ avr_asm_len ("sbiw %0, %1", op, plen, 1); ++ ++ // Next byte has already been handled: Skip it. ++ ++i; ++ continue; ++ } ++ } ++ ++ op[1] = simplify_gen_subreg (QImode, xval, mode, i); ++ ++ if (test_hard_reg_class (LD_REGS, op[0])) ++ { ++ // d-regs can subtract immediates. ++ avr_asm_len (i == 0 ++ ? "subi %0, %1" ++ : "sbci %0, %1", op, plen, 1); ++ } ++ else ++ { ++ int val8 = 0xff & INTVAL (op[1]); ++ if (val8 == 0) ++ { ++ // Any register can subtract 0. ++ avr_asm_len (i == 0 ++ ? "sub %0, __zero_reg__" ++ : "sbc %0, __zero_reg__", op, plen, 1); ++ } ++ else ++ { ++ // Use d-register to hold partial xval. ++ ++ if (val8 != clobber_val) ++ { ++ // Load partial xval to QI clobber reg and memoize for later. ++ gcc_assert (REG_P (op[2])); ++ avr_asm_len ("ldi %2, %1", op, plen, 1); ++ clobber_val = val8; ++ } ++ ++ avr_asm_len (i == 0 ++ ? "sub %0, %2" ++ : "sbc %0, %2", op, plen, 1); ++ } ++ } ++ } // Loop bytes. ++ ++ return ""; ++} ++ ++ + /* Output bit operation (IOR, AND, XOR) with register XOP[0] and compile + time constant XOP[2]: + +@@ -9291,6 +9878,8 @@ avr_adjust_insn_length (rtx_insn *insn, int len) + case ADJUST_LEN_TSTSI: avr_out_tstsi (insn, op, &len); break; + case ADJUST_LEN_COMPARE: avr_out_compare (insn, op, &len); break; + case ADJUST_LEN_COMPARE64: avr_out_compare64 (insn, op, &len); break; ++ case ADJUST_LEN_CMP_UEXT: avr_out_cmp_ext (op, ZERO_EXTEND, &len); break; ++ case ADJUST_LEN_CMP_SEXT: avr_out_cmp_ext (op, SIGN_EXTEND, &len); break; + + case ADJUST_LEN_LSHRQI: lshrqi3_out (insn, op, &len); break; + case ADJUST_LEN_LSHRHI: lshrhi3_out (insn, op, &len); break; +@@ -9311,6 +9900,7 @@ avr_adjust_insn_length (rtx_insn *insn, int len) + case ADJUST_LEN_CALL: len = AVR_HAVE_JMP_CALL ? 2 : 1; break; + + case ADJUST_LEN_INSERT_BITS: avr_out_insert_bits (op, &len); break; ++ case ADJUST_LEN_ADD_SET_ZN: avr_out_plus_set_ZN (op, &len); break; + + case ADJUST_LEN_INSV_NOTBIT: + avr_out_insert_notbit (insn, op, NULL_RTX, &len); +@@ -10607,6 +11197,58 @@ avr_mul_highpart_cost (rtx x, int) + } + + ++/* Return the expected cost of a conditional branch like ++ (set (pc) ++ (if_then_else (X) ++ (label_ref *) ++ (pc))) ++ where X is some comparison operator. */ ++ ++static int ++avr_cbranch_cost (rtx x) ++{ ++ bool difficult_p = difficult_comparison_operator (x, VOIDmode); ++ ++ if (reload_completed) ++ { ++ // After reload, we basically just have plain branches. ++ return COSTS_N_INSNS (1 + difficult_p); ++ } ++ ++ rtx xreg = XEXP (x, 0); ++ rtx xval = XEXP (x, 1); ++ machine_mode mode = GET_MODE (xreg); ++ if (mode == VOIDmode) ++ mode = GET_MODE (xval); ++ int size = GET_MODE_SIZE (mode); ++ ++ if (GET_CODE (xreg) == ZERO_EXTEND ++ || GET_CODE (xval) == ZERO_EXTEND) ++ { ++ // *cbranch..0/1, code = zero_extend. ++ return COSTS_N_INSNS (size + 1); ++ } ++ ++ if (GET_CODE (xreg) == SIGN_EXTEND ++ || GET_CODE (xval) == SIGN_EXTEND) ++ { ++ // *cbranch..0/1, code = sign_extend. ++ // Make it a bit cheaper than it actually is (less reg pressure). ++ return COSTS_N_INSNS (size + 1 + 1); ++ } ++ ++ bool reg_p = register_operand (xreg, mode); ++ bool reg_or_0_p = reg_or_0_operand (xval, mode); ++ ++ return COSTS_N_INSNS (size ++ // For the branch ++ + 1 + difficult_p ++ // Combine might propagate constants other than zero ++ // into the 2nd operand. Make that more expensive. ++ + 1 * (!reg_p || !reg_or_0_p)); ++} ++ ++ + /* Mutually recursive subroutine of avr_rtx_cost for calculating the + cost of an RTX operand given its context. X is the rtx of the + operand, MODE is its mode, and OUTER is the rtx_code of this +@@ -10844,6 +11486,15 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code, + *total += COSTS_N_INSNS (1); + return true; + } ++ if (IOR == code ++ && AND == GET_CODE (XEXP (x, 0)) ++ && AND == GET_CODE (XEXP (x, 1)) ++ && single_zero_operand (XEXP (XEXP (x, 0), 1), mode)) ++ { ++ // Open-coded bit transfer. ++ *total = COSTS_N_INSNS (2); ++ return true; ++ } + *total = COSTS_N_INSNS (GET_MODE_SIZE (mode)); + *total += avr_operand_rtx_cost (XEXP (x, 0), mode, code, 0, speed); + if (!CONST_INT_P (XEXP (x, 1))) +@@ -11490,6 +12141,15 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code, + } + break; + ++ case IF_THEN_ELSE: ++ if (outer_code == SET ++ && XEXP (x, 2) == pc_rtx ++ && ordered_comparison_operator (XEXP (x, 0), VOIDmode)) ++ { ++ *total = avr_cbranch_cost (XEXP (x, 0)); ++ return true; ++ } ++ + default: + break; + } +@@ -11515,6 +12175,52 @@ avr_rtx_costs (rtx x, machine_mode mode, int outer_code, + } + + ++/* Implement `TARGET_INSN_COST'. */ ++/* For some insns, it is not enough to look at the cost of the SET_SRC. ++ In that case, have a look at the entire insn, e.g. during insn combine. */ ++ ++static int ++avr_insn_cost (rtx_insn *insn, bool speed) ++{ ++ const int unknown_cost = -1; ++ int cost = unknown_cost; ++ ++ rtx set = single_set (insn); ++ ++ if (set ++ && ZERO_EXTRACT == GET_CODE (SET_DEST (set))) ++ { ++ // Try find anything that would flip the extracted bit. ++ bool not_bit_p = false; ++ ++ subrtx_iterator::array_type array; ++ FOR_EACH_SUBRTX (iter, array, SET_SRC (set), NONCONST) ++ { ++ enum rtx_code code = GET_CODE (*iter); ++ not_bit_p |= code == NOT || code == XOR || code == GE; ++ } ++ ++ // Don't go too deep into the analysis. In almost all cases, ++ // using BLD/BST is the best we can do for single-bit moves, ++ // even considering CSE. ++ cost = COSTS_N_INSNS (2 + not_bit_p); ++ } ++ ++ if (cost != unknown_cost) ++ { ++ if (avr_log.rtx_costs) ++ avr_edump ("\n%? (%s) insn_cost=%d\n%r\n", ++ speed ? "speed" : "size", cost, insn); ++ return cost; ++ } ++ ++ // Resort to what rtlanal.cc::insn_cost() implements as a default ++ // when targetm.insn_cost() is not implemented. ++ ++ return pattern_cost (PATTERN (insn), speed); ++} ++ ++ + /* Implement `TARGET_ADDRESS_COST'. */ + + static int +@@ -11602,281 +12308,6 @@ avr_normalize_condition (RTX_CODE condition) + } + } + +-/* Helper function for `avr_reorg'. */ +- +-static rtx +-avr_compare_pattern (rtx_insn *insn) +-{ +- rtx pattern = single_set (insn); +- +- if (pattern +- && NONJUMP_INSN_P (insn) +- && REG_P (SET_DEST (pattern)) +- && REGNO (SET_DEST (pattern)) == REG_CC +- && GET_CODE (SET_SRC (pattern)) == COMPARE) +- { +- machine_mode mode0 = GET_MODE (XEXP (SET_SRC (pattern), 0)); +- machine_mode mode1 = GET_MODE (XEXP (SET_SRC (pattern), 1)); +- +- /* The 64-bit comparisons have fixed operands ACC_A and ACC_B. +- They must not be swapped, thus skip them. */ +- +- if ((mode0 == VOIDmode || GET_MODE_SIZE (mode0) <= 4) +- && (mode1 == VOIDmode || GET_MODE_SIZE (mode1) <= 4)) +- return pattern; +- } +- +- return NULL_RTX; +-} +- +-/* Helper function for `avr_reorg'. */ +- +-/* Expansion of switch/case decision trees leads to code like +- +- REG_CC = compare (Reg, Num) +- if (REG_CC == 0) +- goto L1 +- +- REG_CC = compare (Reg, Num) +- if (REG_CC > 0) +- goto L2 +- +- The second comparison is superfluous and can be deleted. +- The second jump condition can be transformed from a +- "difficult" one to a "simple" one because "REG_CC > 0" and +- "REG_CC >= 0" will have the same effect here. +- +- This function relies on the way switch/case is being expaned +- as binary decision tree. For example code see PR 49903. +- +- Return TRUE if optimization performed. +- Return FALSE if nothing changed. +- +- INSN1 is a comparison, i.e. avr_compare_pattern != 0. +- +- We don't want to do this in text peephole because it is +- tedious to work out jump offsets there and the second comparison +- might have been transormed by `avr_reorg'. +- +- RTL peephole won't do because peephole2 does not scan across +- basic blocks. */ +- +-static bool +-avr_reorg_remove_redundant_compare (rtx_insn *insn1) +-{ +- rtx comp1, ifelse1, xcond1; +- rtx_insn *branch1; +- rtx comp2, ifelse2, xcond2; +- rtx_insn *branch2, *insn2; +- enum rtx_code code; +- rtx_insn *jump; +- rtx target, cond; +- +- /* Look out for: compare1 - branch1 - compare2 - branch2 */ +- +- branch1 = next_nonnote_nondebug_insn (insn1); +- if (!branch1 || !JUMP_P (branch1)) +- return false; +- +- insn2 = next_nonnote_nondebug_insn (branch1); +- if (!insn2 || !avr_compare_pattern (insn2)) +- return false; +- +- branch2 = next_nonnote_nondebug_insn (insn2); +- if (!branch2 || !JUMP_P (branch2)) +- return false; +- +- comp1 = avr_compare_pattern (insn1); +- comp2 = avr_compare_pattern (insn2); +- xcond1 = single_set (branch1); +- xcond2 = single_set (branch2); +- +- if (!comp1 || !comp2 +- || !rtx_equal_p (comp1, comp2) +- || !xcond1 || SET_DEST (xcond1) != pc_rtx +- || !xcond2 || SET_DEST (xcond2) != pc_rtx +- || IF_THEN_ELSE != GET_CODE (SET_SRC (xcond1)) +- || IF_THEN_ELSE != GET_CODE (SET_SRC (xcond2))) +- { +- return false; +- } +- +- comp1 = SET_SRC (comp1); +- ifelse1 = SET_SRC (xcond1); +- ifelse2 = SET_SRC (xcond2); +- +- /* comp is COMPARE now and ifelse is IF_THEN_ELSE. */ +- +- if (EQ != GET_CODE (XEXP (ifelse1, 0)) +- || !REG_P (XEXP (comp1, 0)) +- || !CONST_INT_P (XEXP (comp1, 1)) +- || XEXP (ifelse1, 2) != pc_rtx +- || XEXP (ifelse2, 2) != pc_rtx +- || LABEL_REF != GET_CODE (XEXP (ifelse1, 1)) +- || LABEL_REF != GET_CODE (XEXP (ifelse2, 1)) +- || !COMPARISON_P (XEXP (ifelse2, 0)) +- || REG_CC != REGNO (XEXP (XEXP (ifelse1, 0), 0)) +- || REG_CC != REGNO (XEXP (XEXP (ifelse2, 0), 0)) +- || const0_rtx != XEXP (XEXP (ifelse1, 0), 1) +- || const0_rtx != XEXP (XEXP (ifelse2, 0), 1)) +- { +- return false; +- } +- +- /* We filtered the insn sequence to look like +- +- (set (reg:CC cc) +- (compare (reg:M N) +- (const_int VAL))) +- (set (pc) +- (if_then_else (eq (reg:CC cc) +- (const_int 0)) +- (label_ref L1) +- (pc))) +- +- (set (reg:CC cc) +- (compare (reg:M N) +- (const_int VAL))) +- (set (pc) +- (if_then_else (CODE (reg:CC cc) +- (const_int 0)) +- (label_ref L2) +- (pc))) +- */ +- +- code = GET_CODE (XEXP (ifelse2, 0)); +- +- /* Map GT/GTU to GE/GEU which is easier for AVR. +- The first two instructions compare/branch on EQ +- so we may replace the difficult +- +- if (x == VAL) goto L1; +- if (x > VAL) goto L2; +- +- with easy +- +- if (x == VAL) goto L1; +- if (x >= VAL) goto L2; +- +- Similarly, replace LE/LEU by LT/LTU. */ +- +- switch (code) +- { +- case EQ: +- case LT: case LTU: +- case GE: case GEU: +- break; +- +- case LE: case LEU: +- case GT: case GTU: +- code = avr_normalize_condition (code); +- break; +- +- default: +- return false; +- } +- +- /* Wrap the branches into UNSPECs so they won't be changed or +- optimized in the remainder. */ +- +- target = XEXP (XEXP (ifelse1, 1), 0); +- cond = XEXP (ifelse1, 0); +- jump = emit_jump_insn_after (gen_branch_unspec (target, cond), insn1); +- +- JUMP_LABEL (jump) = JUMP_LABEL (branch1); +- +- target = XEXP (XEXP (ifelse2, 1), 0); +- cond = gen_rtx_fmt_ee (code, VOIDmode, cc_reg_rtx, const0_rtx); +- jump = emit_jump_insn_after (gen_branch_unspec (target, cond), insn2); +- +- JUMP_LABEL (jump) = JUMP_LABEL (branch2); +- +- /* The comparisons in insn1 and insn2 are exactly the same; +- insn2 is superfluous so delete it. */ +- +- delete_insn (insn2); +- delete_insn (branch1); +- delete_insn (branch2); +- +- return true; +-} +- +- +-/* Implement `TARGET_MACHINE_DEPENDENT_REORG'. */ +-/* Optimize conditional jumps. */ +- +-static void +-avr_reorg (void) +-{ +- rtx_insn *insn = get_insns(); +- +- for (insn = next_real_insn (insn); insn; insn = next_real_insn (insn)) +- { +- rtx pattern = avr_compare_pattern (insn); +- +- if (!pattern) +- continue; +- +- if (optimize +- && avr_reorg_remove_redundant_compare (insn)) +- { +- continue; +- } +- +- if (compare_diff_p (insn)) +- { +- /* Now we work under compare insn with difficult branch. */ +- +- rtx_insn *next = next_real_insn (insn); +- rtx pat = PATTERN (next); +- if (GET_CODE (pat) == PARALLEL) +- pat = XVECEXP (pat, 0, 0); +- +- pattern = SET_SRC (pattern); +- +- if (true_regnum (XEXP (pattern, 0)) >= 0 +- && true_regnum (XEXP (pattern, 1)) >= 0) +- { +- rtx x = XEXP (pattern, 0); +- rtx src = SET_SRC (pat); +- rtx t = XEXP (src, 0); +- PUT_CODE (t, swap_condition (GET_CODE (t))); +- XEXP (pattern, 0) = XEXP (pattern, 1); +- XEXP (pattern, 1) = x; +- INSN_CODE (next) = -1; +- } +- else if (true_regnum (XEXP (pattern, 0)) >= 0 +- && XEXP (pattern, 1) == const0_rtx) +- { +- /* This is a tst insn, we can reverse it. */ +- rtx src = SET_SRC (pat); +- rtx t = XEXP (src, 0); +- +- PUT_CODE (t, swap_condition (GET_CODE (t))); +- XEXP (pattern, 1) = XEXP (pattern, 0); +- XEXP (pattern, 0) = const0_rtx; +- INSN_CODE (next) = -1; +- INSN_CODE (insn) = -1; +- } +- else if (true_regnum (XEXP (pattern, 0)) >= 0 +- && CONST_INT_P (XEXP (pattern, 1))) +- { +- rtx x = XEXP (pattern, 1); +- rtx src = SET_SRC (pat); +- rtx t = XEXP (src, 0); +- machine_mode mode = GET_MODE (XEXP (pattern, 0)); +- +- if (avr_simplify_comparison_p (mode, GET_CODE (t), x)) +- { +- XEXP (pattern, 1) = gen_int_mode (INTVAL (x) + 1, mode); +- PUT_CODE (t, avr_normalize_condition (GET_CODE (t))); +- INSN_CODE (next) = -1; +- INSN_CODE (insn) = -1; +- } +- } +- } +- } +-} + + /* Returns register number for function return value.*/ + +@@ -14572,6 +15003,8 @@ avr_float_lib_compare_returns_bool (machine_mode mode, enum rtx_code) + #undef TARGET_ASM_FINAL_POSTSCAN_INSN + #define TARGET_ASM_FINAL_POSTSCAN_INSN avr_asm_final_postscan_insn + ++#undef TARGET_INSN_COST ++#define TARGET_INSN_COST avr_insn_cost + #undef TARGET_REGISTER_MOVE_COST + #define TARGET_REGISTER_MOVE_COST avr_register_move_cost + #undef TARGET_MEMORY_MOVE_COST +@@ -14580,8 +15013,6 @@ avr_float_lib_compare_returns_bool (machine_mode mode, enum rtx_code) + #define TARGET_RTX_COSTS avr_rtx_costs + #undef TARGET_ADDRESS_COST + #define TARGET_ADDRESS_COST avr_address_cost +-#undef TARGET_MACHINE_DEPENDENT_REORG +-#define TARGET_MACHINE_DEPENDENT_REORG avr_reorg + #undef TARGET_FUNCTION_ARG + #define TARGET_FUNCTION_ARG avr_function_arg + #undef TARGET_FUNCTION_ARG_ADVANCE +@@ -14711,6 +15142,12 @@ avr_float_lib_compare_returns_bool (machine_mode mode, enum rtx_code) + #undef TARGET_MD_ASM_ADJUST + #define TARGET_MD_ASM_ADJUST avr_md_asm_adjust + ++#undef TARGET_CAN_INLINE_P ++#define TARGET_CAN_INLINE_P avr_can_inline_p ++ ++#undef TARGET_CANONICALIZE_COMPARISON ++#define TARGET_CANONICALIZE_COMPARISON avr_canonicalize_comparison ++ + struct gcc_target targetm = TARGET_INITIALIZER; + + +--- a/src/gcc/config/avr/avr.md ++++ b/src/gcc/config/avr/avr.md +@@ -77,7 +77,6 @@ (define_c_enum "unspec" + UNSPEC_FMULS + UNSPEC_FMULSU + UNSPEC_COPYSIGN +- UNSPEC_IDENTITY + UNSPEC_INSERT_BITS + UNSPEC_ROUND + ]) +@@ -165,6 +164,7 @@ (define_attr "adjust_len" + ashlsi, ashrsi, lshrsi, + ashlpsi, ashrpsi, lshrpsi, + insert_bits, insv_notbit, insv_notbit_0, insv_notbit_7, ++ add_set_ZN, cmp_uext, cmp_sext, + no" + (const_string "no")) + +@@ -251,11 +251,23 @@ (define_mode_iterator QIHI [QI HI]) + (define_mode_iterator QIHI2 [QI HI]) + (define_mode_iterator QISI [QI HI PSI SI]) + (define_mode_iterator QIDI [QI HI PSI SI DI]) ++(define_mode_iterator QIPSI [QI HI PSI]) + (define_mode_iterator HISI [HI PSI SI]) + ++;; Ordered integral and fixed-point modes of specific sizes. + (define_mode_iterator ALL1 [QI QQ UQQ]) + (define_mode_iterator ALL2 [HI HQ UHQ HA UHA]) + (define_mode_iterator ALL4 [SI SQ USQ SA USA]) ++(define_mode_iterator ALL234 [HI SI PSI ++ HQ UHQ HA UHA ++ SQ USQ SA USA]) ++ ++;; Ordered signed integral and signed fixed-point modes of specific sizes. ++(define_mode_iterator ALLs1 [QI QQ]) ++(define_mode_iterator ALLs2 [HI HQ HA]) ++(define_mode_iterator ALLs4 [SI SQ SA]) ++(define_mode_iterator ALLs234 [HI SI PSI ++ HQ HA SQ SA]) + + ;; All supported move-modes + (define_mode_iterator MOVMODE [QI QQ UQQ +@@ -273,15 +285,17 @@ (define_mode_iterator SPLIT34 [SI SF PSI + SQ USQ SA USA]) + + ;; Define code iterators +-;; Define two incarnations so that we can build the cross product. ++;; Define two incarnations so that we can build the cartesian product. + (define_code_iterator any_extend [sign_extend zero_extend]) + (define_code_iterator any_extend2 [sign_extend zero_extend]) + (define_code_iterator any_extract [sign_extract zero_extract]) + (define_code_iterator any_shiftrt [lshiftrt ashiftrt]) + ++(define_code_iterator piaop [plus ior and]) + (define_code_iterator bitop [xor ior and]) + (define_code_iterator xior [xor ior]) + (define_code_iterator eqne [eq ne]) ++(define_code_iterator gelt [ge lt]) + + (define_code_iterator ss_addsub [ss_plus ss_minus]) + (define_code_iterator us_addsub [us_plus us_minus]) +@@ -309,6 +323,10 @@ (define_code_attr abelian + [(ss_minus "") (us_minus "") + (ss_plus "%") (us_plus "%")]) + ++(define_code_attr gelt_eqne ++ [(ge "eq") ++ (lt "ne")]) ++ + ;; Map RTX code to its standard insn name + (define_code_attr code_stdname + [(ashift "ashl") +@@ -1529,9 +1547,8 @@ (define_insn_and_split "*usum_widenqihi3_split" + "#" + "&& reload_completed" + [(parallel [(set (match_dup 0) +- (plus:HI +- (zero_extend:HI (match_dup 1)) +- (zero_extend:HI (match_dup 2)))) ++ (plus:HI (zero_extend:HI (match_dup 1)) ++ (zero_extend:HI (match_dup 2)))) + (clobber (reg:CC REG_CC))])]) + + +@@ -2152,7 +2169,8 @@ (define_insn "*mulqi3_enh" + (define_expand "mulqi3_call" + [(set (reg:QI 24) (match_operand:QI 1 "register_operand" "")) + (set (reg:QI 22) (match_operand:QI 2 "register_operand" "")) +- (parallel [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22))) ++ (parallel [(set (reg:QI 24) ++ (mult:QI (reg:QI 24) (reg:QI 22))) + (clobber (reg:QI 22))]) + (set (match_operand:QI 0 "register_operand" "") (reg:QI 24))] + "" +@@ -2166,12 +2184,14 @@ (define_insn_and_split "*mulqi3_call_split" + "!AVR_HAVE_MUL" + "#" + "&& reload_completed" +- [(parallel [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22))) ++ [(parallel [(set (reg:QI 24) ++ (mult:QI (reg:QI 24) (reg:QI 22))) + (clobber (reg:QI 22)) + (clobber (reg:CC REG_CC))])]) + + (define_insn "*mulqi3_call" +- [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22))) ++ [(set (reg:QI 24) ++ (mult:QI (reg:QI 24) (reg:QI 22))) + (clobber (reg:QI 22)) + (clobber (reg:CC REG_CC))] + "!AVR_HAVE_MUL && reload_completed" +@@ -2307,7 +2327,7 @@ (define_insn "*addpsi3.lt0" + [(set (match_operand:PSI 0 "register_operand" "=r") + (plus:PSI (lshiftrt:PSI (match_operand:PSI 1 "register_operand" "r") + (const_int 23)) +- (match_operand:PSI 2 "register_operand" "0"))) ++ (match_operand:PSI 2 "register_operand" "0"))) + (clobber (reg:CC REG_CC))] + "reload_completed" + "mov __tmp_reg__,%C1\;lsl __tmp_reg__ +@@ -2433,7 +2453,7 @@ (define_insn "*sumulqihi3" + [(set (match_operand:HI 0 "register_operand" "=r") + (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "a")) + (zero_extend:HI (match_operand:QI 2 "register_operand" "a")))) +- (clobber (reg:CC REG_CC))] ++ (clobber (reg:CC REG_CC))] + "AVR_HAVE_MUL && reload_completed" + "mulsu %1,%2 + movw %0,r0 +@@ -3088,7 +3108,7 @@ (define_insn_and_split "muluqihi3" + [(parallel [(set (match_dup 0) + (mult:HI (zero_extend:HI (match_dup 1)) + (match_dup 2))) +- (clobber (reg:CC REG_CC))])]) ++ (clobber (reg:CC REG_CC))])]) + + (define_insn "*muluqihi3" + [(set (match_operand:HI 0 "register_operand" "=&r") +@@ -3706,17 +3726,17 @@ (define_insn "*mulohisi3_call" + ;; CSE has problems to operate on hard regs. + ;; + (define_insn_and_split "divmodqi4" +- [(set (match_operand:QI 0 "pseudo_register_operand" "") +- (div:QI (match_operand:QI 1 "pseudo_register_operand" "") +- (match_operand:QI 2 "pseudo_register_operand" ""))) +- (set (match_operand:QI 3 "pseudo_register_operand" "") ++ [(set (match_operand:QI 0 "pseudo_register_operand") ++ (div:QI (match_operand:QI 1 "pseudo_register_operand") ++ (match_operand:QI 2 "pseudo_register_operand"))) ++ (set (match_operand:QI 3 "pseudo_register_operand") + (mod:QI (match_dup 1) (match_dup 2))) + (clobber (reg:QI 22)) + (clobber (reg:QI 23)) + (clobber (reg:QI 24)) + (clobber (reg:QI 25))] + "" +- "this divmodqi4 pattern should have been splitted;" ++ { gcc_unreachable(); } + "" + [(set (reg:QI 24) (match_dup 1)) + (set (reg:QI 22) (match_dup 2)) +@@ -3752,17 +3772,17 @@ (define_insn "*divmodqi4_call" + [(set_attr "type" "xcall")]) + + (define_insn_and_split "udivmodqi4" +- [(set (match_operand:QI 0 "pseudo_register_operand" "") +- (udiv:QI (match_operand:QI 1 "pseudo_register_operand" "") +- (match_operand:QI 2 "pseudo_register_operand" ""))) +- (set (match_operand:QI 3 "pseudo_register_operand" "") +- (umod:QI (match_dup 1) (match_dup 2))) +- (clobber (reg:QI 22)) +- (clobber (reg:QI 23)) +- (clobber (reg:QI 24)) +- (clobber (reg:QI 25))] +- "" +- "this udivmodqi4 pattern should have been splitted;" ++ [(set (match_operand:QI 0 "pseudo_register_operand") ++ (udiv:QI (match_operand:QI 1 "pseudo_register_operand") ++ (match_operand:QI 2 "pseudo_register_operand"))) ++ (set (match_operand:QI 3 "pseudo_register_operand") ++ (umod:QI (match_dup 1) (match_dup 2))) ++ (clobber (reg:QI 22)) ++ (clobber (reg:QI 23)) ++ (clobber (reg:QI 24)) ++ (clobber (reg:QI 25))] ++ "" ++ { gcc_unreachable(); } + "" + [(set (reg:QI 24) (match_dup 1)) + (set (reg:QI 22) (match_dup 2)) +@@ -3794,17 +3814,17 @@ (define_insn "*udivmodqi4_call" + [(set_attr "type" "xcall")]) + + (define_insn_and_split "divmodhi4" +- [(set (match_operand:HI 0 "pseudo_register_operand" "") +- (div:HI (match_operand:HI 1 "pseudo_register_operand" "") +- (match_operand:HI 2 "pseudo_register_operand" ""))) +- (set (match_operand:HI 3 "pseudo_register_operand" "") ++ [(set (match_operand:HI 0 "pseudo_register_operand") ++ (div:HI (match_operand:HI 1 "pseudo_register_operand") ++ (match_operand:HI 2 "pseudo_register_operand"))) ++ (set (match_operand:HI 3 "pseudo_register_operand") + (mod:HI (match_dup 1) (match_dup 2))) + (clobber (reg:QI 21)) + (clobber (reg:HI 22)) + (clobber (reg:HI 24)) + (clobber (reg:HI 26))] + "" +- "this should have been splitted;" ++ { gcc_unreachable(); } + "" + [(set (reg:HI 24) (match_dup 1)) + (set (reg:HI 22) (match_dup 2)) +@@ -3840,17 +3860,17 @@ (define_insn "*divmodhi4_call" + [(set_attr "type" "xcall")]) + + (define_insn_and_split "udivmodhi4" +- [(set (match_operand:HI 0 "pseudo_register_operand" "") +- (udiv:HI (match_operand:HI 1 "pseudo_register_operand" "") +- (match_operand:HI 2 "pseudo_register_operand" ""))) +- (set (match_operand:HI 3 "pseudo_register_operand" "") ++ [(set (match_operand:HI 0 "pseudo_register_operand") ++ (udiv:HI (match_operand:HI 1 "pseudo_register_operand") ++ (match_operand:HI 2 "pseudo_register_operand"))) ++ (set (match_operand:HI 3 "pseudo_register_operand") + (umod:HI (match_dup 1) (match_dup 2))) + (clobber (reg:QI 21)) + (clobber (reg:HI 22)) + (clobber (reg:HI 24)) + (clobber (reg:HI 26))] + "" +- "this udivmodhi4 pattern should have been splitted.;" ++ { gcc_unreachable(); } + "" + [(set (reg:HI 24) (match_dup 1)) + (set (reg:HI 22) (match_dup 2)) +@@ -3925,7 +3945,7 @@ (define_insn_and_split "*umulqihipsi3_split" + [(parallel [(set (match_dup 0) + (mult:PSI (zero_extend:PSI (match_dup 1)) + (zero_extend:PSI (match_dup 2)))) +- (clobber (reg:CC REG_CC))])]) ++ (clobber (reg:CC REG_CC))])]) + + (define_insn "*umulqihipsi3" + [(set (match_operand:PSI 0 "register_operand" "=&r") +@@ -4091,14 +4111,14 @@ (define_insn "*mulpsi3.libgcc" + ;; implementation works the other way round. + + (define_insn_and_split "divmodpsi4" +- [(parallel [(set (match_operand:PSI 0 "pseudo_register_operand" "") +- (div:PSI (match_operand:PSI 1 "pseudo_register_operand" "") +- (match_operand:PSI 2 "pseudo_register_operand" ""))) +- (set (match_operand:PSI 3 "pseudo_register_operand" "") +- (mod:PSI (match_dup 1) +- (match_dup 2))) +- (clobber (reg:DI 18)) +- (clobber (reg:QI 26))])] ++ [(set (match_operand:PSI 0 "pseudo_register_operand") ++ (div:PSI (match_operand:PSI 1 "pseudo_register_operand") ++ (match_operand:PSI 2 "pseudo_register_operand"))) ++ (set (match_operand:PSI 3 "pseudo_register_operand") ++ (mod:PSI (match_dup 1) ++ (match_dup 2))) ++ (clobber (reg:DI 18)) ++ (clobber (reg:QI 26))] + "" + { gcc_unreachable(); } + "" +@@ -4140,14 +4160,14 @@ (define_insn "*divmodpsi4_call" + [(set_attr "type" "xcall")]) + + (define_insn_and_split "udivmodpsi4" +- [(parallel [(set (match_operand:PSI 0 "pseudo_register_operand" "") +- (udiv:PSI (match_operand:PSI 1 "pseudo_register_operand" "") +- (match_operand:PSI 2 "pseudo_register_operand" ""))) +- (set (match_operand:PSI 3 "pseudo_register_operand" "") +- (umod:PSI (match_dup 1) +- (match_dup 2))) +- (clobber (reg:DI 18)) +- (clobber (reg:QI 26))])] ++ [(set (match_operand:PSI 0 "pseudo_register_operand") ++ (udiv:PSI (match_operand:PSI 1 "pseudo_register_operand") ++ (match_operand:PSI 2 "pseudo_register_operand"))) ++ (set (match_operand:PSI 3 "pseudo_register_operand") ++ (umod:PSI (match_dup 1) ++ (match_dup 2))) ++ (clobber (reg:DI 18)) ++ (clobber (reg:QI 26))] + "" + { gcc_unreachable(); } + "" +@@ -4191,17 +4211,18 @@ (define_insn "*udivmodpsi4_call" + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + (define_insn_and_split "divmodsi4" +- [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "") +- (div:SI (match_operand:SI 1 "pseudo_register_operand" "") +- (match_operand:SI 2 "pseudo_register_operand" ""))) +- (set (match_operand:SI 3 "pseudo_register_operand" "") +- (mod:SI (match_dup 1) (match_dup 2))) +- (clobber (reg:SI 18)) +- (clobber (reg:SI 22)) +- (clobber (reg:HI 26)) +- (clobber (reg:HI 30))])] ++ [(set (match_operand:SI 0 "pseudo_register_operand") ++ (div:SI (match_operand:SI 1 "pseudo_register_operand") ++ (match_operand:SI 2 "pseudo_register_operand"))) ++ (set (match_operand:SI 3 "pseudo_register_operand") ++ (mod:SI (match_dup 1) ++ (match_dup 2))) ++ (clobber (reg:SI 18)) ++ (clobber (reg:SI 22)) ++ (clobber (reg:HI 26)) ++ (clobber (reg:HI 30))] + "" +- "this divmodsi4 pattern should have been splitted;" ++ { gcc_unreachable(); } + "" + [(set (reg:SI 22) (match_dup 1)) + (set (reg:SI 18) (match_dup 2)) +@@ -4237,17 +4258,18 @@ (define_insn "*divmodsi4_call" + [(set_attr "type" "xcall")]) + + (define_insn_and_split "udivmodsi4" +- [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "") +- (udiv:SI (match_operand:SI 1 "pseudo_register_operand" "") +- (match_operand:SI 2 "pseudo_register_operand" ""))) +- (set (match_operand:SI 3 "pseudo_register_operand" "") +- (umod:SI (match_dup 1) (match_dup 2))) +- (clobber (reg:SI 18)) +- (clobber (reg:SI 22)) +- (clobber (reg:HI 26)) +- (clobber (reg:HI 30))])] ++ [(set (match_operand:SI 0 "pseudo_register_operand") ++ (udiv:SI (match_operand:SI 1 "pseudo_register_operand") ++ (match_operand:SI 2 "pseudo_register_operand"))) ++ (set (match_operand:SI 3 "pseudo_register_operand") ++ (umod:SI (match_dup 1) ++ (match_dup 2))) ++ (clobber (reg:SI 18)) ++ (clobber (reg:SI 22)) ++ (clobber (reg:HI 26)) ++ (clobber (reg:HI 30))] + "" +- "this udivmodsi4 pattern should have been splitted;" ++ { gcc_unreachable(); } + "" + [(set (reg:SI 22) (match_dup 1)) + (set (reg:SI 18) (match_dup 2)) +@@ -4712,7 +4734,8 @@ (define_split + [(parallel [(set (match_operand:HISI 0 "register_operand") + (bitop:HISI (match_dup 0) + (match_operand:HISI 1 "register_operand"))) +- (clobber (scratch:QI))])] ++ (clobber (scratch:QI)) ++ (clobber (reg:CC REG_CC))])] + "optimize + && reload_completed" + [(const_int 1)] +@@ -4726,6 +4749,43 @@ (define_split + DONE; + }) + ++;; If $0 = $0 const requires a QI scratch, and d-reg $1 dies after ++;; the first insn, then we can replace ++;; $0 = $1 ++;; $0 = $0 const ++;; by ++;; $1 = $1 const ++;; $0 = $1 ++;; This transorms constraint alternative "r,0,n,&d" of the first operation ++;; to alternative "d,0,n,X". ++;; "*addhi3_clobber" "*addpsi3" "*addsi3" ++;; "*addhq3" "*adduhq3" "*addha3" "*adduha3" ++;; "*addsq3" "*addusq3" "*addsa3" "*addusa3" ++;; "*iorhi3" "*iorpsi3" "*iorsi3" ++;; "*andhi3" "*andpsi3" "*andsi3" ++(define_peephole2 ++ [(parallel [(set (match_operand:ORDERED234 0 "register_operand") ++ (match_operand:ORDERED234 1 "d_register_operand")) ++ (clobber (reg:CC REG_CC))]) ++ (parallel [(set (match_dup 0) ++ (piaop:ORDERED234 (match_dup 0) ++ (match_operand:ORDERED234 2 "const_operand"))) ++ ; A d-reg as scratch tells that this insn is expensive, and ++ ; that $0 is not a d-register: l-reg or something like SI:14 etc. ++ (clobber (match_operand:QI 3 "d_register_operand")) ++ (clobber (reg:CC REG_CC))])] ++ "peep2_reg_dead_p (1, operands[1])" ++ [(parallel [(set (match_dup 1) ++ (piaop:ORDERED234 (match_dup 1) ++ (match_dup 2))) ++ (clobber (scratch:QI)) ++ (clobber (reg:CC REG_CC))]) ++ ; Unfortunately, the following insn misses a REG_DEAD note for $1, ++ ; so this peep2 works only once. ++ (parallel [(set (match_dup 0) ++ (match_dup 1)) ++ (clobber (reg:CC REG_CC))])]) ++ + + ;; swap swap swap swap swap swap swap swap swap swap swap swap swap swap swap + ;; swap +@@ -5684,7 +5744,7 @@ (define_insn "*lshr3" + ;; "lshrha3" "lshruha3" + (define_insn_and_split "lshr3" + [(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r,r,r") +- (lshiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,0,r,0,0,0") ++ (lshiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,0,r,0,0,0") + (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))] + "" + "#" +@@ -5696,7 +5756,7 @@ (define_insn_and_split "lshr3" + + (define_insn "*lshr3" + [(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r,r,r") +- (lshiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,0,r,0,0,0") ++ (lshiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,0,r,0,0,0") + (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm"))) + (clobber (reg:CC REG_CC))] + "reload_completed" +@@ -6449,80 +6509,41 @@ (define_insn_and_split "zero_extendsidi2" + ;;<=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=> + ;; compare + +-; Optimize negated tests into reverse compare if overflow is undefined. +-(define_insn "*negated_tstqi" ++;; "*swapped_tstqi" "*swapped_tstqq" ++(define_insn "*swapped_tst" + [(set (reg:CC REG_CC) +- (compare:CC (neg:QI (match_operand:QI 0 "register_operand" "r")) +- (const_int 0)))] +- "reload_completed && !flag_wrapv && !flag_trapv" +- "cp __zero_reg__,%0" +- [(set_attr "length" "1")]) +- +-(define_insn "*reversed_tstqi" +- [(set (reg:CC REG_CC) +- (compare:CC (const_int 0) +- (match_operand:QI 0 "register_operand" "r")))] ++ (compare:CC (match_operand:ALLs1 0 "const0_operand" "Y00") ++ (match_operand:ALLs1 1 "register_operand" "r")))] + "reload_completed" +- "cp __zero_reg__,%0" +-[(set_attr "length" "2")]) ++ "cp __zero_reg__,%1" ++[(set_attr "length" "1")]) + +-(define_insn "*negated_tsthi" +- [(set (reg:CC REG_CC) +- (compare:CC (neg:HI (match_operand:HI 0 "register_operand" "r")) +- (const_int 0)))] +- "reload_completed && !flag_wrapv && !flag_trapv" +- "cp __zero_reg__,%A0 +- cpc __zero_reg__,%B0" +-[(set_attr "length" "2")]) +- +-;; Leave here the clobber used by the cmphi pattern for simplicity, even +-;; though it is unused, because this pattern is synthesized by avr_reorg. +-(define_insn "*reversed_tsthi" ++ ++;; "*swapped_tsthi" "*swapped_tsthq" "*swapped_tstha" ++(define_insn "*swapped_tst" + [(set (reg:CC REG_CC) +- (compare:CC (const_int 0) +- (match_operand:HI 0 "register_operand" "r"))) +- (clobber (match_scratch:QI 1 "=X"))] ++ (compare:CC (match_operand:ALLs2 0 "const0_operand" "Y00") ++ (match_operand:ALLs2 1 "register_operand" "r")))] + "reload_completed" +- "cp __zero_reg__,%A0 +- cpc __zero_reg__,%B0" +-[(set_attr "length" "2")]) ++ "cp __zero_reg__,%A1 ++ cpc __zero_reg__,%B1" ++ [(set_attr "length" "2")]) + +-(define_insn "*negated_tstpsi" +- [(set (reg:CC REG_CC) +- (compare:CC (neg:PSI (match_operand:PSI 0 "register_operand" "r")) +- (const_int 0)))] +- "reload_completed && !flag_wrapv && !flag_trapv" +- "cp __zero_reg__,%A0\;cpc __zero_reg__,%B0\;cpc __zero_reg__,%C0" +- [(set_attr "length" "3")]) + +-(define_insn "*reversed_tstpsi" ++(define_insn "*swapped_tstpsi" + [(set (reg:CC REG_CC) + (compare:CC (const_int 0) +- (match_operand:PSI 0 "register_operand" "r"))) +- (clobber (match_scratch:QI 1 "=X"))] ++ (match_operand:PSI 0 "register_operand" "r")))] + "reload_completed" + "cp __zero_reg__,%A0\;cpc __zero_reg__,%B0\;cpc __zero_reg__,%C0" + [(set_attr "length" "3")]) + +-(define_insn "*negated_tstsi" +- [(set (reg:CC REG_CC) +- (compare:CC (neg:SI (match_operand:SI 0 "register_operand" "r")) +- (const_int 0)))] +- "reload_completed && !flag_wrapv && !flag_trapv" +- "cp __zero_reg__,%A0 +- cpc __zero_reg__,%B0 +- cpc __zero_reg__,%C0 +- cpc __zero_reg__,%D0" +- [(set_attr "length" "4")]) + +-;; "*reversed_tstsi" +-;; "*reversed_tstsq" "*reversed_tstusq" +-;; "*reversed_tstsa" "*reversed_tstusa" +-(define_insn "*reversed_tst" ++;; "*swapped_tstsi" "*swapped_tstsq" "*swapped_tstsa" ++(define_insn "*swapped_tst" + [(set (reg:CC REG_CC) +- (compare:CC (match_operand:ALL4 0 "const0_operand" "Y00") +- (match_operand:ALL4 1 "register_operand" "r"))) +- (clobber (match_scratch:QI 2 "=X"))] ++ (compare:CC (match_operand:ALLs4 0 "const0_operand" "Y00") ++ (match_operand:ALLs4 1 "register_operand" "r")))] + "reload_completed" + "cp __zero_reg__,%A1 + cpc __zero_reg__,%B1 +@@ -6536,38 +6557,40 @@ (define_insn "*reversed_tst" + (define_insn "cmp3" + [(set (reg:CC REG_CC) + (compare:CC (match_operand:ALL1 0 "register_operand" "r ,r,d") +- (match_operand:ALL1 1 "nonmemory_operand" "Y00,r,i")))] ++ (match_operand:ALL1 1 "nonmemory_operand" "Y00,r,i")))] + "reload_completed" + "@ +- tst %0 ++ cp %0, __zero_reg__ + cp %0,%1 + cpi %0,lo8(%1)" + [(set_attr "length" "1,1,1")]) + +-(define_insn "*cmpqi_sign_extend" +- [(set (reg:CC REG_CC) +- (compare:CC (sign_extend:HI (match_operand:QI 0 "register_operand" "d")) +- (match_operand:HI 1 "s8_operand" "n")))] +- "reload_completed" +- "cpi %0,lo8(%1)" +- [(set_attr "length" "1")]) + +- +-(define_insn "*cmphi.zero-extend.0" ++;; May be generated by "*cbranch..0/1". ++(define_insn "*cmp..0" + [(set (reg:CC REG_CC) +- (compare:CC (zero_extend:HI (match_operand:QI 0 "register_operand" "r")) +- (match_operand:HI 1 "register_operand" "r")))] +- "reload_completed" +- "cp %0,%A1\;cpc __zero_reg__,%B1" +- [(set_attr "length" "2")]) ++ (compare:CC (any_extend:HISI (match_operand:QIPSI 0 "register_operand" "r")) ++ (match_operand:HISI 1 "register_operand" "r")))] ++ "reload_completed ++ && GET_MODE_SIZE (mode) > GET_MODE_SIZE (mode)" ++ { ++ return avr_out_cmp_ext (operands, , nullptr); ++ } ++ [(set_attr "adjust_len" "cmp_ext")]) + +-(define_insn "*cmphi.zero-extend.1" ++;; Swapped version of the above. ++;; May be generated by "*cbranch..0/1". ++(define_insn "*cmp..1" + [(set (reg:CC REG_CC) +- (compare:CC (match_operand:HI 0 "register_operand" "r") +- (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))))] +- "reload_completed" +- "cp %A0,%1\;cpc %B0,__zero_reg__" +- [(set_attr "length" "2")]) ++ (compare:CC (match_operand:HISI 0 "register_operand" "r") ++ (any_extend:HISI (match_operand:QIPSI 1 "register_operand" "r"))))] ++ "reload_completed ++ && GET_MODE_SIZE (mode) > GET_MODE_SIZE (mode)" ++ { ++ return avr_out_cmp_ext (operands, , nullptr); ++ } ++ [(set_attr "adjust_len" "cmp_ext")]) ++ + + ;; "cmphi3" + ;; "cmphq3" "cmpuhq3" +@@ -6575,8 +6598,8 @@ (define_insn "*cmphi.zero-extend.1" + (define_insn "cmp3" + [(set (reg:CC REG_CC) + (compare:CC (match_operand:ALL2 0 "register_operand" "!w ,r ,r,d ,r ,d,r") +- (match_operand:ALL2 1 "nonmemory_operand" "Y00,Y00,r,s ,s ,M,n Ynn"))) +- (clobber (match_scratch:QI 2 "=X ,X ,X,&d,&d ,X,&d"))] ++ (match_operand:ALL2 1 "nonmemory_operand" "Y00,Y00,r,s ,s ,M,n Ynn"))) ++ (clobber (match_scratch:QI 2 "=X ,X ,X,&d,&d ,X,&d"))] + "reload_completed" + { + switch (which_alternative) +@@ -6603,14 +6626,14 @@ (define_insn "cmp3" + + return avr_out_compare (insn, operands, NULL); + } +- [(set_attr "length" "1,2,2,3,4,2,4") ++ [(set_attr "length" "2,2,2,3,4,2,4") + (set_attr "adjust_len" "tsthi,tsthi,*,*,*,compare,compare")]) + + (define_insn "*cmppsi" + [(set (reg:CC REG_CC) + (compare:CC (match_operand:PSI 0 "register_operand" "r,r,d ,r ,d,r") +- (match_operand:PSI 1 "nonmemory_operand" "L,r,s ,s ,M,n"))) +- (clobber (match_scratch:QI 2 "=X,X,&d,&d ,X,&d"))] ++ (match_operand:PSI 1 "nonmemory_operand" "L,r,s ,s ,M,n"))) ++ (clobber (match_scratch:QI 2 "=X,X,&d,&d ,X,&d"))] + "reload_completed" + { + switch (which_alternative) +@@ -6641,8 +6664,8 @@ (define_insn "*cmppsi" + (define_insn "*cmp" + [(set (reg:CC REG_CC) + (compare:CC (match_operand:ALL4 0 "register_operand" "r ,r ,d,r ,r") +- (match_operand:ALL4 1 "nonmemory_operand" "Y00,r ,M,M ,n Ynn"))) +- (clobber (match_scratch:QI 2 "=X ,X ,X,&d,&d"))] ++ (match_operand:ALL4 1 "nonmemory_operand" "Y00,r ,M,M ,n Ynn"))) ++ (clobber (match_scratch:QI 2 "=X ,X ,X,&d,&d"))] + "reload_completed" + { + if (0 == which_alternative) +@@ -6656,6 +6679,13 @@ (define_insn "*cmp" + (set_attr "adjust_len" "tstsi,*,compare,compare,compare")]) + + ++;; A helper for avr_pass_ifelse::avr_rest_of_handle_ifelse(). ++(define_expand "gen_compare" ++ [(parallel [(set (reg:CC REG_CC) ++ (compare:CC (match_operand:HISI 0 "register_operand") ++ (match_operand:HISI 1 "const_int_operand"))) ++ (clobber (match_operand:QI 2 "scratch_operand"))])]) ++ + ;; ---------------------------------------------------------------------- + ;; JUMP INSTRUCTIONS + ;; ---------------------------------------------------------------------- +@@ -6664,53 +6694,67 @@ (define_insn "*cmp" + (define_expand "cbranch4" + [(set (pc) + (if_then_else (match_operator 0 "ordered_comparison_operator" +- [(match_operand:ALL1 1 "register_operand" "") +- (match_operand:ALL1 2 "nonmemory_operand" "")]) +- (label_ref (match_operand 3 "" "")) +- (pc)))]) ++ [(match_operand:ALL1 1 "register_operand") ++ (match_operand:ALL1 2 "nonmemory_operand")]) ++ (label_ref (match_operand 3)) ++ (pc)))] ++ "" ++ { ++ int icode = (int) GET_CODE (operands[0]); ++ ++ targetm.canonicalize_comparison (&icode, &operands[1], &operands[2], false); ++ PUT_CODE (operands[0], (enum rtx_code) icode); ++ }) + + (define_expand "cbranch4" + [(parallel + [(set (pc) +- (if_then_else +- (match_operator 0 "ordered_comparison_operator" +- [(match_operand:ORDERED234 1 "register_operand" "") +- (match_operand:ORDERED234 2 "nonmemory_operand" "")]) +- (label_ref (match_operand 3 "" "")) +- (pc))) +- (clobber (match_scratch:QI 4 ""))])]) +- +-;; "*cbranchqi4" +-;; "*cbranchqq4" "*cbranchuqq4" +-(define_insn_and_split "*cbranch4" ++ (if_then_else (match_operator 0 "ordered_comparison_operator" ++ [(match_operand:ALL234 1 "register_operand") ++ (match_operand:ALL234 2 "nonmemory_operand")]) ++ (label_ref (match_operand 3)) ++ (pc))) ++ (clobber (match_scratch:QI 4))])] ++ "" ++ { ++ int icode = (int) GET_CODE (operands[0]); ++ ++ targetm.canonicalize_comparison (&icode, &operands[1], &operands[2], false); ++ PUT_CODE (operands[0], (enum rtx_code) icode); ++ }) ++ ++ ++;; "cbranchqi4_insn" ++;; "cbranchqq4_insn" "cbranchuqq4_insn" ++(define_insn_and_split "cbranch4_insn" + [(set (pc) + (if_then_else (match_operator 0 "ordered_comparison_operator" +- [(match_operand:ALL1 1 "register_operand" "r ,r,d") ++ [(match_operand:ALL1 1 "register_operand" "r ,r,d") + (match_operand:ALL1 2 "nonmemory_operand" "Y00,r,i")]) +- (label_ref (match_operand 3 "" "")) +- (pc)))] ++ (label_ref (match_operand 3)) ++ (pc)))] + "" + "#" + "reload_completed" + [(set (reg:CC REG_CC) +- (compare:CC (match_dup 1) (match_dup 2))) ++ (compare:CC (match_dup 1) (match_dup 2))) + (set (pc) + (if_then_else (match_op_dup 0 + [(reg:CC REG_CC) (const_int 0)]) + (label_ref (match_dup 3)) +- (pc)))] +- "") ++ (pc)))]) + +-;; "*cbranchsi4" "*cbranchsq4" "*cbranchusq4" "*cbranchsa4" "*cbranchusa4" +-(define_insn_and_split "*cbranch4" ++;; "cbranchsi4_insn" ++;; "cbranchsq4_insn" "cbranchusq4_insn" "cbranchsa4_insn" "cbranchusa4_insn" ++(define_insn_and_split "cbranch4_insn" + [(set (pc) +- (if_then_else +- (match_operator 0 "ordered_comparison_operator" +- [(match_operand:ALL4 1 "register_operand" "r ,r ,d,r ,r") +- (match_operand:ALL4 2 "nonmemory_operand" "Y00,r ,M,M ,n Ynn")]) +- (label_ref (match_operand 3 "" "")) +- (pc))) +- (clobber (match_scratch:QI 4 "=X ,X ,X,&d,&d"))] ++ (if_then_else ++ (match_operator 0 "ordered_comparison_operator" ++ [(match_operand:ALL4 1 "register_operand" "r ,r,d,r ,r") ++ (match_operand:ALL4 2 "nonmemory_operand" "Y00,r,M,M ,n Ynn")]) ++ (label_ref (match_operand 3)) ++ (pc))) ++ (clobber (match_scratch:QI 4 "=X ,X,X,&d,&d"))] + "" + "#" + "reload_completed" +@@ -6721,19 +6765,18 @@ (define_insn_and_split "*cbranch4" + (if_then_else (match_op_dup 0 + [(reg:CC REG_CC) (const_int 0)]) + (label_ref (match_dup 3)) +- (pc)))] +- "") ++ (pc)))]) + +-;; "*cbranchpsi4" +-(define_insn_and_split "*cbranchpsi4" ++;; "cbranchpsi4_insn" ++(define_insn_and_split "cbranchpsi4_insn" + [(set (pc) +- (if_then_else +- (match_operator 0 "ordered_comparison_operator" +- [(match_operand:PSI 1 "register_operand" "r,r,d ,r ,d,r") +- (match_operand:PSI 2 "nonmemory_operand" "L,r,s ,s ,M,n")]) +- (label_ref (match_operand 3 "" "")) +- (pc))) +- (clobber (match_scratch:QI 4 "=X,X,&d,&d ,X,&d"))] ++ (if_then_else ++ (match_operator 0 "ordered_comparison_operator" ++ [(match_operand:PSI 1 "register_operand" "r,r,d ,r ,d,r") ++ (match_operand:PSI 2 "nonmemory_operand" "L,r,s ,s ,M,n")]) ++ (label_ref (match_operand 3)) ++ (pc))) ++ (clobber (match_scratch:QI 4 "=X,X,&d,&d,X,&d"))] + "" + "#" + "reload_completed" +@@ -6744,19 +6787,19 @@ (define_insn_and_split "*cbranchpsi4" + (if_then_else (match_op_dup 0 + [(reg:CC REG_CC) (const_int 0)]) + (label_ref (match_dup 3)) +- (pc)))] +- "") ++ (pc)))]) + +-;; "*cbranchhi4" "*cbranchhq4" "*cbranchuhq4" "*cbranchha4" "*cbranchuha4" +-(define_insn_and_split "*cbranch4" ++;; "cbranchhi4_insn" ++;; "cbranchhq4_insn" "cbranchuhq4_insn" "cbranchha4_insn" "cbranchuha4_insn" ++(define_insn_and_split "cbranch4_insn" + [(set (pc) +- (if_then_else +- (match_operator 0 "ordered_comparison_operator" +- [(match_operand:ALL2 1 "register_operand" "!w ,r ,r,d ,r ,d,r") +- (match_operand:ALL2 2 "nonmemory_operand" "Y00,Y00,r,s ,s ,M,n Ynn")]) +- (label_ref (match_operand 3 "" "")) +- (pc))) +- (clobber (match_scratch:QI 4 "=X ,X ,X,&d,&d ,X,&d"))] ++ (if_then_else ++ (match_operator 0 "ordered_comparison_operator" ++ [(match_operand:ALL2 1 "register_operand" "!w ,r ,r,d ,r ,d,r") ++ (match_operand:ALL2 2 "nonmemory_operand" "Y00,Y00,r,s ,s ,M,n Ynn")]) ++ (label_ref (match_operand 3)) ++ (pc))) ++ (clobber (match_scratch:QI 4 "=X ,X ,X,&d,&d,X,&d"))] + "" + "#" + "reload_completed" +@@ -6767,8 +6810,71 @@ (define_insn_and_split "*cbranch4" + (if_then_else (match_op_dup 0 + [(reg:CC REG_CC) (const_int 0)]) + (label_ref (match_dup 3)) +- (pc)))] +- "") ++ (pc)))]) ++ ++;; Combiner pattern to compare sign- or zero-extended register against ++;; a wider register, like comparing uint8_t against uint16_t. ++(define_insn_and_split "*cbranch..0" ++ [(set (pc) ++ (if_then_else (match_operator 0 "ordered_comparison_operator" ++ [(any_extend:HISI (match_operand:QIPSI 1 "register_operand" "r")) ++ (match_operand:HISI 2 "register_operand" "r")]) ++ (label_ref (match_operand 3)) ++ (pc)))] ++ "optimize ++ && GET_MODE_SIZE (mode) > GET_MODE_SIZE (mode)" ++ "#" ++ "&& reload_completed" ++ [; "*cmp..0" ++ (set (reg:CC REG_CC) ++ (compare:CC (match_dup 1) ++ (match_dup 2))) ++ ; "branch" ++ (set (pc) ++ (if_then_else (match_op_dup 0 [(reg:CC REG_CC) ++ (const_int 0)]) ++ (label_ref (match_dup 3)) ++ (pc)))] ++ { ++ operands[1] = gen_rtx_ (mode, operands[1]); ++ if (difficult_comparison_operator (operands[0], VOIDmode)) ++ { ++ PUT_CODE (operands[0], swap_condition (GET_CODE (operands[0]))); ++ std::swap (operands[1], operands[2]); ++ } ++ }) ++ ++;; Same combiner pattern, but with swapped operands. ++(define_insn_and_split "*cbranch..0" ++ [(set (pc) ++ (if_then_else (match_operator 0 "ordered_comparison_operator" ++ [(match_operand:HISI 1 "register_operand" "r") ++ (any_extend:HISI (match_operand:QIPSI 2 "register_operand" "r"))]) ++ (label_ref (match_operand 3)) ++ (pc)))] ++ "optimize ++ && GET_MODE_SIZE (mode) > GET_MODE_SIZE (mode)" ++ "#" ++ "&& reload_completed" ++ [; "*cmp..0" ++ (set (reg:CC REG_CC) ++ (compare:CC (match_dup 1) ++ (match_dup 2))) ++ ; "branch" ++ (set (pc) ++ (if_then_else (match_op_dup 0 [(reg:CC REG_CC) ++ (const_int 0)]) ++ (label_ref (match_dup 3)) ++ (pc)))] ++ { ++ operands[2] = gen_rtx_ (mode, operands[2]); ++ if (difficult_comparison_operator (operands[0], VOIDmode)) ++ { ++ PUT_CODE (operands[0], swap_condition (GET_CODE (operands[0]))); ++ std::swap (operands[1], operands[2]); ++ } ++ }) ++ + + ;; Test a single bit in a QI/HI/SImode register. + ;; Combine will create zero extract patterns for single bit tests. +@@ -6842,14 +6948,11 @@ (define_insn_and_split "*sbrx_and_branch_split" + "#" + "&& reload_completed" + [(parallel [(set (pc) +- (if_then_else +- (match_op_dup 0 +- [(and:QISI +- (match_dup 1) +- (match_dup 2)) +- (const_int 0)]) +- (label_ref (match_dup 3)) +- (pc))) ++ (if_then_else (match_op_dup 0 [(and:QISI (match_dup 1) ++ (match_dup 2)) ++ (const_int 0)]) ++ (label_ref (match_dup 3)) ++ (pc))) + (clobber (reg:CC REG_CC))])]) + + (define_insn "*sbrx_and_branch" +@@ -6878,163 +6981,77 @@ (define_insn "*sbrx_and_branch" + (const_int 2) + (const_int 4))))]) + +-;; Convert sign tests to bit 7/15/31 tests that match the above insns. +-(define_peephole2 +- [(set (reg:CC REG_CC) (compare:CC (match_operand:QI 0 "register_operand" "") +- (const_int 0))) +- (parallel [(set (pc) (if_then_else (ge (reg:CC REG_CC) (const_int 0)) +- (label_ref (match_operand 1 "" "")) +- (pc))) +- (clobber (reg:CC REG_CC))])] +- "" +- [(parallel [(set (pc) (if_then_else (eq (zero_extract:HI (match_dup 0) +- (const_int 1) +- (const_int 7)) +- (const_int 0)) +- (label_ref (match_dup 1)) +- (pc))) +- (clobber (reg:CC REG_CC))])]) + +-(define_peephole2 +- [(set (reg:CC REG_CC) (compare:CC (match_operand:QI 0 "register_operand" "") +- (const_int 0))) +- (parallel [(set (pc) (if_then_else (lt (reg:CC REG_CC) (const_int 0)) +- (label_ref (match_operand 1 "" "")) +- (pc))) +- (clobber (reg:CC REG_CC))])] +- "" +- [(parallel [(set (pc) (if_then_else (ne (zero_extract:HI (match_dup 0) +- (const_int 1) +- (const_int 7)) +- (const_int 0)) +- (label_ref (match_dup 1)) +- (pc))) +- (clobber (reg:CC REG_CC))])]) +- +-(define_peephole2 +- [(parallel [(set (reg:CC REG_CC) (compare:CC (match_operand:HI 0 "register_operand" "") +- (const_int 0))) +- (clobber (match_operand:HI 2 ""))]) +- (parallel [(set (pc) (if_then_else (ge (reg:CC REG_CC) (const_int 0)) +- (label_ref (match_operand 1 "" "")) +- (pc))) +- (clobber (reg:CC REG_CC))])] +- "" +- [(parallel [(set (pc) (if_then_else (eq (and:HI (match_dup 0) (const_int -32768)) +- (const_int 0)) +- (label_ref (match_dup 1)) +- (pc))) +- (clobber (reg:CC REG_CC))])]) +- +-(define_peephole2 +- [(parallel [(set (reg:CC REG_CC) (compare:CC (match_operand:HI 0 "register_operand" "") +- (const_int 0))) +- (clobber (match_operand:HI 2 ""))]) +- (parallel [(set (pc) (if_then_else (lt (reg:CC REG_CC) (const_int 0)) +- (label_ref (match_operand 1 "" "")) +- (pc))) ++;; Convert sign tests to bit 7 tests that match the above insns. ++(define_peephole2 ; "*sbrx_branch" ++ [(set (reg:CC REG_CC) ++ (compare:CC (match_operand:ALLs1 0 "register_operand") ++ (match_operand:ALLs1 1 "const0_operand"))) ++ (set (pc) ++ (if_then_else (gelt (reg:CC REG_CC) ++ (const_int 0)) ++ (label_ref (match_operand 2)) ++ (pc)))] ++ "peep2_regno_dead_p (2, REG_CC)" ++ [(parallel [(set (pc) ++ (if_then_else ( (zero_extract:HI (match_dup 0) ++ (const_int 1) ++ (match_dup 1)) ++ (const_int 0)) ++ (label_ref (match_dup 2)) ++ (pc))) + (clobber (reg:CC REG_CC))])] +- "" +- [(parallel [(set (pc) (if_then_else (ne (and:HI (match_dup 0) (const_int -32768)) +- (const_int 0)) +- (label_ref (match_dup 1)) +- (pc))) +- (clobber (reg:CC REG_CC))])]) ++ { ++ operands[0] = avr_to_int_mode (operands[0]); ++ operands[1] = GEN_INT (GET_MODE_BITSIZE (mode) - 1); ++ }) + +-(define_peephole2 +- [(parallel [(set (reg:CC REG_CC) (compare:CC (match_operand:SI 0 "register_operand" "") +- (const_int 0))) +- (clobber (match_operand:SI 2 ""))]) +- (parallel [(set (pc) (if_then_else (ge (reg:CC REG_CC) (const_int 0)) +- (label_ref (match_operand 1 "" "")) +- (pc))) +- (clobber (reg:CC REG_CC))])] +- "" +- [(parallel [(set (pc) (if_then_else (eq (and:SI (match_dup 0) (match_dup 2)) +- (const_int 0)) +- (label_ref (match_dup 1)) +- (pc))) ++;; Convert sign tests to bit 15/23/31 tests that match the above insns. ++(define_peephole2 ; "*sbrx_branch" ++ [(parallel [(set (reg:CC REG_CC) ++ (compare:CC (match_operand:ALLs234 0 "register_operand") ++ (match_operand:ALLs234 1 "const0_operand"))) ++ (clobber (match_operand:QI 3 "scratch_operand"))]) ++ (set (pc) ++ (if_then_else (gelt (reg:CC REG_CC) ++ (const_int 0)) ++ (label_ref (match_operand 2)) ++ (pc)))] ++ "peep2_regno_dead_p (2, REG_CC)" ++ [(parallel [(set (pc) ++ (if_then_else ( (zero_extract:HI (match_dup 0) ++ (const_int 1) ++ (match_dup 1)) ++ (const_int 0)) ++ (label_ref (match_dup 2)) ++ (pc))) + (clobber (reg:CC REG_CC))])] +- "operands[2] = gen_int_mode (-2147483647 - 1, SImode);") ++ { ++ operands[0] = avr_to_int_mode (operands[0]); ++ operands[1] = GEN_INT (GET_MODE_BITSIZE (mode) - 1); ++ }) + +-(define_peephole2 +- [(parallel [(set (reg:CC REG_CC) (compare:CC (match_operand:SI 0 "register_operand" "") +- (const_int 0))) +- (clobber (match_operand:SI 2 ""))]) +- (parallel [(set (pc) (if_then_else (lt (reg:CC REG_CC) (const_int 0)) +- (label_ref (match_operand 1 "" "")) +- (pc))) +- (clobber (reg:CC REG_CC))])] +- "" +- [(parallel [(set (pc) (if_then_else (ne (and:SI (match_dup 0) (match_dup 2)) +- (const_int 0)) +- (label_ref (match_dup 1)) +- (pc))) +- (clobber (reg:CC REG_CC))])] +- "operands[2] = gen_int_mode (-2147483647 - 1, SImode);") + + ;; ************************************************************************ + ;; Implementation of conditional jumps here. + ;; Compare with 0 (test) jumps + ;; ************************************************************************ + +-(define_insn_and_split "branch" ++(define_insn "branch" + [(set (pc) + (if_then_else (match_operator 1 "simple_comparison_operator" +- [(reg:CC REG_CC) +- (const_int 0)]) +- (label_ref (match_operand 0 "" "")) ++ [(reg:CC REG_CC) ++ (const_int 0)]) ++ (label_ref (match_operand 0)) + (pc)))] + "reload_completed" +- "#" +- "&& reload_completed" +- [(parallel [(set (pc) +- (if_then_else (match_op_dup 1 +- [(reg:CC REG_CC) +- (const_int 0)]) +- (label_ref (match_dup 0)) +- (pc))) +- (clobber (reg:CC REG_CC))])]) +- +-(define_insn "*branch" +- [(set (pc) +- (if_then_else (match_operator 1 "simple_comparison_operator" +- [(reg:CC REG_CC) +- (const_int 0)]) +- (label_ref (match_operand 0 "" "")) +- (pc))) +- (clobber (reg:CC REG_CC))] +- "reload_completed" +- { +- return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 0); +- } +- [(set_attr "type" "branch")]) +- +- +-;; Same as above but wrap SET_SRC so that this branch won't be transformed +-;; or optimized in the remainder. +- +-(define_insn "branch_unspec" +- [(set (pc) +- (unspec [(if_then_else (match_operator 1 "simple_comparison_operator" +- [(reg:CC REG_CC) +- (const_int 0)]) +- (label_ref (match_operand 0 "" "")) +- (pc)) +- ] UNSPEC_IDENTITY)) +- (clobber (reg:CC REG_CC))] +- "reload_completed" + { + return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 0); + } + [(set_attr "type" "branch")]) + +-;; **************************************************************** +-;; AVR does not have following conditional jumps: LE,LEU,GT,GTU. +-;; Convert them all to proper jumps. +-;; ****************************************************************/ + +-(define_insn_and_split "difficult_branch" ++(define_insn "difficult_branch" + [(set (pc) + (if_then_else (match_operator 1 "difficult_comparison_operator" + [(reg:CC REG_CC) +@@ -7042,95 +7059,11 @@ (define_insn_and_split "difficult_branch" + (label_ref (match_operand 0 "" "")) + (pc)))] + "reload_completed" +- "#" +- "&& reload_completed" +- [(parallel [(set (pc) +- (if_then_else (match_op_dup 1 +- [(reg:CC REG_CC) +- (const_int 0)]) +- (label_ref (match_dup 0)) +- (pc))) +- (clobber (reg:CC REG_CC))])]) +- +-(define_insn "*difficult_branch" +- [(set (pc) +- (if_then_else (match_operator 1 "difficult_comparison_operator" +- [(reg:CC REG_CC) +- (const_int 0)]) +- (label_ref (match_operand 0 "" "")) +- (pc))) +- (clobber (reg:CC REG_CC))] +- "reload_completed" + { + return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 0); + } + [(set_attr "type" "branch1")]) + +-;; revers branch +- +-(define_insn_and_split "rvbranch" +- [(set (pc) +- (if_then_else (match_operator 1 "simple_comparison_operator" +- [(reg:CC REG_CC) +- (const_int 0)]) +- (pc) +- (label_ref (match_operand 0 "" ""))))] +- "reload_completed" +- "#" +- "&& reload_completed" +- [(parallel [(set (pc) +- (if_then_else (match_op_dup 1 +- [(reg:CC REG_CC) +- (const_int 0)]) +- (pc) +- (label_ref (match_dup 0)))) +- (clobber (reg:CC REG_CC))])]) +- +-(define_insn "*rvbranch" +- [(set (pc) +- (if_then_else (match_operator 1 "simple_comparison_operator" +- [(reg:CC REG_CC) +- (const_int 0)]) +- (pc) +- (label_ref (match_operand 0 "" "")))) +- (clobber (reg:CC REG_CC))] +- "reload_completed" +- { +- return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1); +- } +- [(set_attr "type" "branch1")]) +- +-(define_insn_and_split "difficult_rvbranch" +- [(set (pc) +- (if_then_else (match_operator 1 "difficult_comparison_operator" +- [(reg:CC REG_CC) +- (const_int 0)]) +- (pc) +- (label_ref (match_operand 0 "" ""))))] +- "reload_completed" +- "#" +- "&& reload_completed" +- [(parallel [(set (pc) +- (if_then_else (match_op_dup 1 +- [(reg:CC REG_CC) +- (const_int 0)]) +- (pc) +- (label_ref (match_dup 0)))) +- (clobber (reg:CC REG_CC))])]) +- +-(define_insn "*difficult_rvbranch" +- [(set (pc) +- (if_then_else (match_operator 1 "difficult_comparison_operator" +- [(reg:CC REG_CC) +- (const_int 0)]) +- (pc) +- (label_ref (match_operand 0 "" "")))) +- (clobber (reg:CC REG_CC))] +- "reload_completed" +- { +- return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1); +- } +- [(set_attr "type" "branch")]) + + ;; ************************************************************************** + ;; Unconditional and other jump instructions. +@@ -7656,15 +7589,14 @@ (define_peephole ; "*dec-and-branchsi!=-1.d.clobber" + (clobber (reg:CC REG_CC))]) + (parallel [(set (reg:CC REG_CC) + (compare:CC (match_dup 0) +- (const_int -1))) +- (clobber (match_operand:QI 1 "d_register_operand" ""))]) +- (parallel [(set (pc) +- (if_then_else (eqne (reg:CC REG_CC) +- (const_int 0)) +- (label_ref (match_operand 2 "" "")) +- (pc))) +- (clobber (reg:CC REG_CC))])] +- "" ++ (const_int -1))) ++ (clobber (match_operand:QI 1 "scratch_or_d_register_operand"))]) ++ (set (pc) ++ (if_then_else (eqne (reg:CC REG_CC) ++ (const_int 0)) ++ (label_ref (match_operand 2)) ++ (pc)))] ++ "dead_or_set_regno_p (insn, REG_CC)" + { + const char *op; + int jump_mode; +@@ -7700,15 +7632,14 @@ (define_peephole ; "*dec-and-branchhi!=-1" + (clobber (reg:CC REG_CC))]) + (parallel [(set (reg:CC REG_CC) + (compare:CC (match_dup 0) +- (const_int -1))) ++ (const_int -1))) + (clobber (match_operand:QI 1 "d_register_operand" ""))]) +- (parallel [(set (pc) +- (if_then_else (eqne (reg:CC REG_CC) +- (const_int 0)) +- (label_ref (match_operand 2 "" "")) +- (pc))) +- (clobber (reg:CC REG_CC))])] +- "" ++ (set (pc) ++ (if_then_else (eqne (reg:CC REG_CC) ++ (const_int 0)) ++ (label_ref (match_operand 2)) ++ (pc)))] ++ "dead_or_set_regno_p (insn, REG_CC)" + { + const char *op; + int jump_mode; +@@ -7742,15 +7673,14 @@ (define_peephole ; "*dec-and-branchhi!=-1.d.clobber" + (clobber (reg:CC REG_CC))]) + (parallel [(set (reg:CC REG_CC) + (compare:CC (match_dup 0) +- (const_int -1))) +- (clobber (match_operand:QI 1 "d_register_operand" ""))]) +- (parallel [(set (pc) +- (if_then_else (eqne (reg:CC REG_CC) +- (const_int 0)) +- (label_ref (match_operand 2 "" "")) +- (pc))) +- (clobber (reg:CC REG_CC))])] +- "" ++ (const_int -1))) ++ (clobber (match_operand:QI 1 "scratch_or_d_register_operand"))]) ++ (set (pc) ++ (if_then_else (eqne (reg:CC REG_CC) ++ (const_int 0)) ++ (label_ref (match_operand 2)) ++ (pc)))] ++ "dead_or_set_regno_p (insn, REG_CC)" + { + const char *op; + int jump_mode; +@@ -7784,15 +7714,14 @@ (define_peephole ; "*dec-and-branchhi!=-1.l.clobber" + (clobber (reg:CC REG_CC))]) + (parallel [(set (reg:CC REG_CC) + (compare:CC (match_dup 0) +- (const_int -1))) ++ (const_int -1))) + (clobber (match_operand:QI 1 "d_register_operand" ""))]) +- (parallel [(set (pc) +- (if_then_else (eqne (reg:CC REG_CC) +- (const_int 0)) +- (label_ref (match_operand 2 "" "")) +- (pc))) +- (clobber (reg:CC REG_CC))])] +- "" ++ (set (pc) ++ (if_then_else (eqne (reg:CC REG_CC) ++ (const_int 0)) ++ (label_ref (match_operand 2)) ++ (pc)))] ++ "dead_or_set_regno_p (insn, REG_CC)" + { + const char *op; + int jump_mode; +@@ -7822,14 +7751,13 @@ (define_peephole ; "*dec-and-branchqi!=-1" + (clobber (reg:CC REG_CC))]) + (set (reg:CC REG_CC) + (compare:CC (match_dup 0) +- (const_int -1))) +- (parallel [(set (pc) +- (if_then_else (eqne (reg:CC REG_CC) +- (const_int 0)) +- (label_ref (match_operand 1 "" "")) +- (pc))) +- (clobber (reg:CC REG_CC))])] +- "" ++ (const_int -1))) ++ (set (pc) ++ (if_then_else (eqne (reg:CC REG_CC) ++ (const_int 0)) ++ (label_ref (match_operand 1)) ++ (pc)))] ++ "dead_or_set_regno_p (insn, REG_CC)" + { + const char *op; + int jump_mode; +@@ -7855,14 +7783,14 @@ (define_peephole ; "*dec-and-branchqi!=-1" + (define_peephole ; "*cpse.eq" + [(set (reg:CC REG_CC) + (compare:CC (match_operand:ALL1 1 "register_operand" "r,r") +- (match_operand:ALL1 2 "reg_or_0_operand" "r,Y00"))) +- (parallel [(set (pc) +- (if_then_else (eq (reg:CC REG_CC) +- (const_int 0)) +- (label_ref (match_operand 0 "" "")) +- (pc))) +- (clobber (reg:CC REG_CC))])] +- "jump_over_one_insn_p (insn, operands[0])" ++ (match_operand:ALL1 2 "reg_or_0_operand" "r,Y00"))) ++ (set (pc) ++ (if_then_else (eq (reg:CC REG_CC) ++ (const_int 0)) ++ (label_ref (match_operand 0)) ++ (pc)))] ++ "jump_over_one_insn_p (insn, operands[0]) ++ && dead_or_set_regno_p (insn, REG_CC)" + "@ + cpse %1,%2 + cpse %1,__zero_reg__") +@@ -7890,16 +7818,16 @@ (define_peephole ; "*cpse.eq" + + (define_peephole ; "*cpse.ne" + [(set (reg:CC REG_CC) +- (compare:CC (match_operand:ALL1 1 "register_operand" "") +- (match_operand:ALL1 2 "reg_or_0_operand" ""))) +- (parallel [(set (pc) +- (if_then_else (ne (reg:CC REG_CC) +- (const_int 0)) +- (label_ref (match_operand 0 "" "")) +- (pc))) +- (clobber (reg:CC REG_CC))])] +- "!AVR_HAVE_JMP_CALL +- || !TARGET_SKIP_BUG" ++ (compare:CC (match_operand:ALL1 1 "register_operand") ++ (match_operand:ALL1 2 "reg_or_0_operand"))) ++ (set (pc) ++ (if_then_else (ne (reg:CC REG_CC) ++ (const_int 0)) ++ (label_ref (match_operand 0)) ++ (pc)))] ++ "(!AVR_HAVE_JMP_CALL ++ || !TARGET_SKIP_BUG) ++ && dead_or_set_regno_p (insn, REG_CC)" + { + if (operands[2] == CONST0_RTX (mode)) + operands[2] = zero_reg_rtx; +@@ -8094,7 +8022,7 @@ (define_insn_and_split "delay_cycles_1" + (const_int 1)] + UNSPECV_DELAY_CYCLES) + (set (match_dup 1) +- (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) ++ (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) + (clobber (match_dup 2)) + (clobber (reg:CC REG_CC))])]) + +@@ -8126,7 +8054,7 @@ (define_insn_and_split "delay_cycles_2" + (const_int 2)] + UNSPECV_DELAY_CYCLES) + (set (match_dup 1) +- (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) ++ (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) + (clobber (match_dup 2)) + (clobber (reg:CC REG_CC))])] + "" +@@ -8163,7 +8091,7 @@ (define_insn_and_split "delay_cycles_3" + (const_int 3)] + UNSPECV_DELAY_CYCLES) + (set (match_dup 1) +- (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) ++ (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) + (clobber (match_dup 2)) + (clobber (match_dup 3)) + (clobber (match_dup 4)) +@@ -8206,7 +8134,7 @@ (define_insn_and_split "delay_cycles_4" + (const_int 4)] + UNSPECV_DELAY_CYCLES) + (set (match_dup 1) +- (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) ++ (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) + (clobber (match_dup 2)) + (clobber (match_dup 3)) + (clobber (match_dup 4)) +@@ -9095,16 +9023,20 @@ (define_insn "*movbitqi.1-6.b" + "bst %3,0\;bld %0,%4" + [(set_attr "length" "2")]) + +-;; Move bit $3.0 into bit $0.0. +-;; For bit 0, combiner generates slightly different pattern. +-(define_insn "*movbitqi.0" +- [(set (match_operand:QI 0 "register_operand" "=r") +- (ior:QI (and:QI (match_operand:QI 1 "register_operand" "0") +- (match_operand:QI 2 "single_zero_operand" "n")) +- (and:QI (match_operand:QI 3 "register_operand" "r") +- (const_int 1))))] +- "0 == exact_log2 (~INTVAL(operands[2]) & GET_MODE_MASK (QImode))" +- "bst %3,0\;bld %0,0" ++;; Move bit $3.x into bit $0.x. ++(define_insn "*movbit.0-6" ++ [(set (match_operand:QISI 0 "register_operand" "=r") ++ (ior:QISI (and:QISI (match_operand:QISI 1 "register_operand" "0") ++ (match_operand:QISI 2 "single_zero_operand" "n")) ++ (and:QISI (match_operand:QISI 3 "register_operand" "r") ++ (match_operand:QISI 4 "single_one_operand" "n"))))] ++ "GET_MODE_MASK(mode) ++ == (GET_MODE_MASK(mode) & (INTVAL(operands[2]) ^ INTVAL(operands[4])))" ++ { ++ auto bitmask = GET_MODE_MASK (mode) & UINTVAL (operands[4]); ++ operands[4] = GEN_INT (exact_log2 (bitmask)); ++ return "bst %T3%T4" CR_TAB "bld %T0%T4"; ++ } + [(set_attr "length" "2")]) + + ;; Move bit $2.0 into bit $0.7. +@@ -9489,6 +9421,258 @@ (define_peephole2 + (clobber (reg:CC REG_CC))])]) + + ++;; Try optimize decrement-and-branch. When we have an addition followed ++;; by a comparison of the result against zero, we can output the addition ++;; in such a way that SREG.N and SREG.Z are set according to the result. ++ ++;; { -1, +1 } for QImode, otherwise the empty set. ++(define_mode_attr p1m1 [(QI "N P") ++ (HI "Yxx") (PSI "Yxx") (SI "Yxx")]) ++ ++;; FIXME: reload1.cc::do_output_reload() does not support output reloads ++;; for JUMP_INSNs, hence letting combine doing decrement-and-branch like ++;; the following might run into ICE. Doing reloads by hand is too painful... ++; ++; (define_insn_and_split "*add.for.eqne..cbranch" ++; [(set (pc) ++; (if_then_else (eqne (match_operand:QISI 1 "register_operand" "0") ++; (match_operand:QISI 2 "const_int_operand" "n")) ++; (label_ref (match_operand 4)) ++; (pc))) ++; (set (match_operand:QISI 0 "register_operand" "=r") ++; (plus:QISI (match_dup 1) ++; (match_operand:QISI 3 "const_int_operand" "n")))] ++; ;; No clobber for now as combine might not have one handy. ++; ;; We pop a scatch in split1. ++; "!reload_completed ++; && const0_rtx == simplify_binary_operation (PLUS, mode, ++; operands[2], operands[3])" ++; { gcc_unreachable(); } ++; "&& 1" ++; [(parallel [(set (pc) ++; (if_then_else (eqne (match_dup 1) ++; (match_dup 2)) ++; (label_ref (match_dup 4)) ++; (pc))) ++; (set (match_dup 0) ++; (plus:QISI (match_dup 1) ++; (match_dup 3))) ++; (clobber (scratch:QI))])]) ++; ++;; ...Hence, stick with RTL peepholes for now. Unfortunately, there is no ++;; canonical form, and if reload shuffles registers around, we might miss ++;; opportunities to match a decrement-and-branch. ++;; doloop_end doesn't reload either, so doloop_end also won't work. ++ ++(define_expand "gen_add_for__" ++ ; "*add.for.eqne." ++ [(parallel [(set (reg:CC REG_CC) ++ (compare:CC (plus:QISI (match_operand:QISI 0 "register_operand") ++ (match_operand:QISI 1 "const_int_operand")) ++ (const_int 0))) ++ (set (match_dup 0) ++ (plus:QISI (match_dup 0) ++ (match_dup 1))) ++ (clobber (match_operand:QI 3))]) ++ ; "branch" ++ (set (pc) ++ (if_then_else (eqne (reg:CC REG_CC) ++ (const_int 0)) ++ (label_ref (match_dup 2)) ++ (pc)))]) ++ ++ ++;; 1/3: A version without clobber: d-reg or 8-bit adds +/-1. ++(define_peephole2 ++ [(parallel [(set (match_operand:QISI 0 "register_operand") ++ (plus:QISI (match_dup 0) ++ (match_operand:QISI 1 "const_int_operand"))) ++ (clobber (reg:CC REG_CC))]) ++ (set (reg:CC REG_CC) ++ (compare:CC (match_dup 0) ++ (const_int 0))) ++ (set (pc) ++ (if_then_else (eqne (reg:CC REG_CC) ++ (const_int 0)) ++ (label_ref (match_operand 2)) ++ (pc)))] ++ "peep2_regno_dead_p (3, REG_CC) ++ && (d_register_operand (operands[0], mode) ++ || (mode == QImode ++ && (INTVAL (operands[1]) == 1 ++ || INTVAL (operands[1]) == -1)))" ++ [(scratch)] ++ { ++ emit (gen_gen_add_for__ (operands[0], operands[1], operands[2], ++ gen_rtx_SCRATCH (QImode))); ++ DONE; ++ }) ++ ++;; 2/3: A version with clobber from the insn. ++(define_peephole2 ++ [(parallel [(set (match_operand:QISI 0 "register_operand") ++ (plus:QISI (match_dup 0) ++ (match_operand:QISI 1 "const_int_operand"))) ++ (clobber (match_operand:QI 3 "scratch_or_d_register_operand")) ++ (clobber (reg:CC REG_CC))]) ++ (parallel [(set (reg:CC REG_CC) ++ (compare:CC (match_dup 0) ++ (const_int 0))) ++ (clobber (match_operand:QI 4 "scratch_or_d_register_operand"))]) ++ (set (pc) ++ (if_then_else (eqne (reg:CC REG_CC) ++ (const_int 0)) ++ (label_ref (match_operand 2)) ++ (pc)))] ++ "peep2_regno_dead_p (3, REG_CC)" ++ [(scratch)] ++ { ++ rtx scratch = REG_P (operands[3]) ? operands[3] : operands[4]; ++ ++ // We need either a d-register or a scratch register to clobber. ++ if (! REG_P (scratch) ++ && ! d_register_operand (operands[0], mode) ++ && ! (QImode == mode ++ && (INTVAL (operands[1]) == 1 ++ || INTVAL (operands[1]) == -1))) ++ { ++ FAIL; ++ } ++ emit (gen_gen_add_for__ (operands[0], operands[1], operands[2], ++ scratch)); ++ DONE; ++ }) ++ ++;; 3/3 A version with a clobber from peephole2. ++(define_peephole2 ++ [(match_scratch:QI 3 "d") ++ (parallel [(set (match_operand:QISI 0 "register_operand") ++ (plus:QISI (match_dup 0) ++ (match_operand:QISI 1 "const_int_operand"))) ++ (clobber (reg:CC REG_CC))]) ++ (set (reg:CC REG_CC) ++ (compare:CC (match_dup 0) ++ (const_int 0))) ++ (set (pc) ++ (if_then_else (eqne (reg:CC REG_CC) ++ (const_int 0)) ++ (label_ref (match_operand 2)) ++ (pc)))] ++ "peep2_regno_dead_p (3, REG_CC)" ++ [(scratch)] ++ { ++ emit (gen_gen_add_for__ (operands[0], operands[1], operands[2], ++ operands[3])); ++ DONE; ++ }) ++ ++;; Result of the above three peepholes is an addition that also ++;; performs an EQ or NE comparison (of the result) against zero. ++;; FIXME: Using (match_dup 0) instead of operands[3/4] makes rnregs ++;; barf in regrename.cc::merge_overlapping_regs(). For now, use the ++;; fix from PR50788: Constrain as "0". ++(define_insn "*add.for.eqne." ++ [(set (reg:CC REG_CC) ++ (compare:CC ++ (plus:QISI (match_operand:QISI 3 "register_operand" "0,0 ,0") ++ (match_operand:QISI 1 "const_int_operand" "n,,n")) ++ (const_int 0))) ++ (set (match_operand:QISI 0 "register_operand" "=d,*r ,r") ++ (plus:QISI (match_operand:QISI 4 "register_operand" "0,0 ,0") ++ (match_dup 1))) ++ (clobber (match_scratch:QI 2 "=X,X ,&d"))] ++ "reload_completed" ++ { ++ return avr_out_plus_set_ZN (operands, nullptr); ++ } ++ [(set_attr "adjust_len" "add_set_ZN")]) ++ ++ ++;; Swapping both comparison and branch condition. This can turn difficult ++;; branches to easy ones. And in some cases, a comparison against one can ++;; be turned into a comparison against zero. ++ ++(define_peephole2 ; "*swapped_tst" ++ [(parallel [(set (reg:CC REG_CC) ++ (compare:CC (match_operand:ALLs234 1 "register_operand") ++ (match_operand:ALLs234 2 "const_operand"))) ++ (clobber (match_operand:QI 3 "scratch_operand"))]) ++ (set (pc) ++ (if_then_else (match_operator 0 "ordered_comparison_operator" ++ [(reg:CC REG_CC) ++ (const_int 0)]) ++ (label_ref (match_operand 4)) ++ (pc)))] ++ "peep2_regno_dead_p (2, REG_CC)" ++ [(set (reg:CC REG_CC) ++ (compare:CC (match_dup 2) ++ (match_dup 1))) ++ ; "branch" ++ (set (pc) ++ (if_then_else (match_op_dup 0 [(reg:CC REG_CC) ++ (const_int 0)]) ++ (label_ref (match_dup 4)) ++ (pc)))] ++ { ++ rtx xval = avr_to_int_mode (operands[2]); ++ enum rtx_code code = GET_CODE (operands[0]); ++ ++ if (code == GT && xval == const0_rtx) ++ code = LT; ++ else if (code == GE && xval == const1_rtx) ++ code = LT; ++ else if (code == LE && xval == const0_rtx) ++ code = GE; ++ else if (code == LT && xval == const1_rtx) ++ code = GE; ++ else ++ FAIL; ++ ++ operands[2] = CONST0_RTX (mode); ++ PUT_CODE (operands[0], code); ++ }) ++ ++;; Same, but for 8-bit modes which have no scratch reg. ++(define_peephole2 ; "*swapped_tst" ++ [(set (reg:CC REG_CC) ++ (compare:CC (match_operand:ALLs1 1 "register_operand") ++ (match_operand:ALLs1 2 "const_operand"))) ++ (set (pc) ++ (if_then_else (match_operator 0 "ordered_comparison_operator" ++ [(reg:CC REG_CC) ++ (const_int 0)]) ++ (label_ref (match_operand 4)) ++ (pc)))] ++ "peep2_regno_dead_p (2, REG_CC)" ++ [(set (reg:CC REG_CC) ++ (compare:CC (match_dup 2) ++ (match_dup 1))) ++ ; "branch" ++ (set (pc) ++ (if_then_else (match_op_dup 0 [(reg:CC REG_CC) ++ (const_int 0)]) ++ (label_ref (match_dup 4)) ++ (pc)))] ++ { ++ rtx xval = avr_to_int_mode (operands[2]); ++ enum rtx_code code = GET_CODE (operands[0]); ++ ++ if (code == GT && xval == const0_rtx) ++ code = LT; ++ else if (code == GE && xval == const1_rtx) ++ code = LT; ++ else if (code == LE && xval == const0_rtx) ++ code = GE; ++ else if (code == LT && xval == const1_rtx) ++ code = GE; ++ else ++ FAIL; ++ ++ operands[2] = CONST0_RTX (mode); ++ PUT_CODE (operands[0], code); ++ }) ++ ++ + (define_expand "extzv" + [(set (match_operand:QI 0 "register_operand" "") + (zero_extract:QI (match_operand:QI 1 "register_operand" "") +--- a/src/gcc/config/avr/constraints.md ++++ b/src/gcc/config/avr/constraints.md +@@ -245,6 +245,11 @@ (define_constraint "Ym2" + (match_test "INTVAL (avr_to_int_mode (op)) == -2")) + (match_test "satisfies_constraint_Cm2 (op)"))) + ++;; Constraint that's the empty set. Useful with mode and code iterators. ++(define_constraint "Yxx" ++ "A constraints that is always false" ++ (match_test "false")) ++ + (define_constraint "Yx2" + "Fixed-point or integer constant not in the range @minus{}2 @dots{} 2" + (and (ior (match_code "const_int") +--- a/src/gcc/config/avr/predicates.md ++++ b/src/gcc/config/avr/predicates.md +@@ -27,6 +27,11 @@ (define_predicate "d_register_operand" + (and (match_code "reg") + (match_test "REGNO (op) >= 16 && REGNO (op) <= 31"))) + ++(define_predicate "scratch_or_d_register_operand" ++ (ior (match_operand 0 "d_register_operand") ++ (and (match_code ("scratch")) ++ (match_operand 0 "scratch_operand")))) ++ + (define_predicate "even_register_operand" + (and (match_code "reg") + (and (match_test "REGNO (op) <= 31") +--- a/src/gcc/config/darwin.opt ++++ b/src/gcc/config/darwin.opt +@@ -33,6 +33,10 @@ fapple-kext + Target C++ Var(flag_apple_kext) + Generate code for darwin loadable kernel extensions. + ++fconstant-cfstrings ++ObjC ObjC++ Alias(mconstant-cfstrings) ++Generate compile-time CFString objects. ++ + iframework + Target RejectNegative C ObjC C++ ObjC++ Joined Separate + -iframework Add to the end of the system framework include path. --- a/src/gcc/config/gcn/gcn-valu.md +++ b/src/gcc/config/gcn/gcn-valu.md @@ -15,6 +15,7 @@ @@ -819,6 +9637,17 @@ ;; }}} ;; {{{ Iterators useful across the wole machine description +--- a/src/gcc/config/i386/i386-builtin-types.def ++++ b/src/gcc/config/i386/i386-builtin-types.def +@@ -73,7 +73,7 @@ DEF_PRIMITIVE_TYPE (BFLOAT16, ix86_bf16_type_node) + DEF_PRIMITIVE_TYPE (FLOAT, float_type_node) + DEF_PRIMITIVE_TYPE (DOUBLE, double_type_node) + DEF_PRIMITIVE_TYPE (FLOAT80, float80_type_node) +-DEF_PRIMITIVE_TYPE (FLOAT128, float128_type_node) ++DEF_PRIMITIVE_TYPE (FLOAT128, float128t_type_node) + DEF_PRIMITIVE_TYPE (CONST_STRING, const_string_type_node) + + # MMX vectors --- a/src/gcc/config/i386/i386-features.cc +++ b/src/gcc/config/i386/i386-features.cc @@ -1635,10 +1635,11 @@ timode_scalar_chain::convert_insn (rtx_insn *insn) @@ -837,6 +9666,332 @@ break; case MEM: +@@ -2455,8 +2456,7 @@ public: + /* opt_pass methods: */ + bool gate (function *) final override + { +- return TARGET_AVX && TARGET_VZEROUPPER +- && flag_expensive_optimizations && !optimize_size; ++ return TARGET_AVX && TARGET_VZEROUPPER; + } + + unsigned int execute (function *) final override +--- a/src/gcc/config/i386/i386-options.cc ++++ b/src/gcc/config/i386/i386-options.cc +@@ -1400,7 +1400,11 @@ ix86_valid_target_attribute_tree (tree fndecl, tree args, + if (option_strings[IX86_FUNCTION_SPECIFIC_TUNE]) + opts->x_ix86_tune_string + = ggc_strdup (option_strings[IX86_FUNCTION_SPECIFIC_TUNE]); +- else if (orig_tune_defaulted) ++ /* If we have explicit arch string and no tune string specified, set ++ tune_string to NULL and later it will be overriden by arch_string ++ so target clones can get proper optimization. */ ++ else if (option_strings[IX86_FUNCTION_SPECIFIC_ARCH] ++ || orig_tune_defaulted) + opts->x_ix86_tune_string = NULL; + + /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */ +@@ -2727,7 +2731,9 @@ ix86_option_override_internal (bool main_args_p, + sorry ("%<-mcall-ms2sysv-xlogues%> isn%'t currently supported with SEH"); + + if (!(opts_set->x_target_flags & MASK_VZEROUPPER) +- && TARGET_EMIT_VZEROUPPER) ++ && TARGET_EMIT_VZEROUPPER ++ && flag_expensive_optimizations ++ && !optimize_size) + opts->x_target_flags |= MASK_VZEROUPPER; + if (!(opts_set->x_target_flags & MASK_STV)) + opts->x_target_flags |= MASK_STV; +--- a/src/gcc/config/i386/i386.cc ++++ b/src/gcc/config/i386/i386.cc +@@ -5358,19 +5358,19 @@ standard_sse_constant_opcode (rtx_insn *insn, rtx *operands) + if (GET_MODE_SIZE (mode) == 64) + { + gcc_assert (TARGET_AVX512F); +- return "vpcmpeqd \t %t0, %t0, %t0"; ++ return "vpcmpeqd\t%t0, %t0, %t0"; + } + else if (GET_MODE_SIZE (mode) == 32) + { + gcc_assert (TARGET_AVX); +- return "vpcmpeqd \t %x0, %x0, %x0"; ++ return "vpcmpeqd\t%x0, %x0, %x0"; + } + gcc_unreachable (); + } + else if (vector_all_ones_zero_extend_quarter_operand (x, mode)) + { + gcc_assert (TARGET_AVX512F); +- return "vpcmpeqd \t %x0, %x0, %x0"; ++ return "vpcmpeqd\t%x0, %x0, %x0"; + } + + gcc_unreachable (); +@@ -18537,8 +18537,10 @@ ix86_gimple_fold_builtin (gimple_stmt_iterator *gsi) + tree itype = GET_MODE_INNER (TYPE_MODE (type)) == E_SFmode + ? intSI_type_node : intDI_type_node; + type = get_same_sized_vectype (itype, type); +- arg2 = gimple_build (&stmts, VIEW_CONVERT_EXPR, type, arg2); + } ++ else ++ type = signed_type_for (type); ++ arg2 = gimple_build (&stmts, VIEW_CONVERT_EXPR, type, arg2); + tree zero_vec = build_zero_cst (type); + tree cmp_type = truth_type_for (type); + tree cmp = gimple_build (&stmts, LT_EXPR, cmp_type, arg2, zero_vec); +@@ -22450,6 +22452,35 @@ x86_emit_floatuns (rtx operands[2]) + + emit_label (donelab); + } ++ ++/* Return the diagnostic message string if conversion from FROMTYPE to ++ TOTYPE is not allowed, NULL otherwise. ++ Currently it's used to warn for silent implicit conversion between __bf16 ++ and short, since __bfloat16 is refined as real __bf16 instead of short ++ since GCC13. */ ++ ++static const char * ++ix86_invalid_conversion (const_tree fromtype, const_tree totype) ++{ ++ if (element_mode (fromtype) != element_mode (totype) ++ && (TARGET_AVX512BF16 || TARGET_AVXNECONVERT)) ++ { ++ /* Warn for silent implicit conversion where user may expect ++ a bitcast. */ ++ if ((TYPE_MODE (fromtype) == BFmode ++ && TYPE_MODE (totype) == HImode) ++ || (TYPE_MODE (totype) == BFmode ++ && TYPE_MODE (fromtype) == HImode)) ++ warning (0, "%<__bfloat16%> is redefined from typedef % " ++ "to real %<__bf16%> since GCC V13, be careful of " ++ "implicit conversion between %<__bf16%> and %; " ++ "a explicit bitcast may be needed here"); ++ } ++ ++ /* Conversion allowed. */ ++ return NULL; ++} ++ + + /* Target hook for scalar_mode_supported_p. */ + static bool +@@ -24711,6 +24742,9 @@ ix86_run_selftests (void) + # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes + #endif + ++#undef TARGET_INVALID_CONVERSION ++#define TARGET_INVALID_CONVERSION ix86_invalid_conversion ++ + #undef TARGET_COMP_TYPE_ATTRIBUTES + #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes + +--- a/src/gcc/config/i386/i386.h ++++ b/src/gcc/config/i386/i386.h +@@ -2359,7 +2359,7 @@ constexpr wide_int_bitmask PTA_ALDERLAKE = PTA_TREMONT | PTA_ADX | PTA_AVX + | PTA_PCONFIG | PTA_PKU | PTA_VAES | PTA_VPCLMULQDQ | PTA_SERIALIZE + | PTA_HRESET | PTA_KL | PTA_WIDEKL | PTA_AVXVNNI; + constexpr wide_int_bitmask PTA_SIERRAFOREST = PTA_ALDERLAKE | PTA_AVXIFMA +- | PTA_AVXVNNIINT8 | PTA_AVXNECONVERT | PTA_CMPCCXADD; ++ | PTA_AVXVNNIINT8 | PTA_AVXNECONVERT | PTA_CMPCCXADD | PTA_ENQCMD | PTA_UINTR; + constexpr wide_int_bitmask PTA_GRANITERAPIDS = PTA_SAPPHIRERAPIDS | PTA_AMX_FP16 + | PTA_PREFETCHI | PTA_AMX_COMPLEX; + constexpr wide_int_bitmask PTA_GRANDRIDGE = PTA_SIERRAFOREST | PTA_RAOINT; +--- a/src/gcc/config/i386/sse.md ++++ b/src/gcc/config/i386/sse.md +@@ -1335,7 +1335,7 @@ (define_expand "mov" + + (define_insn "mov_internal" + [(set (match_operand:VMOVE 0 "nonimmediate_operand" +- "=v,v ,v,v ,m") ++ "=v,v ,x,v ,m") + (match_operand:VMOVE 1 "nonimmediate_or_sse_const_operand" + " C,,BH,vm,v"))] + "TARGET_SSE +@@ -1467,12 +1467,12 @@ (define_expand "_load_mask" + }) + + (define_insn "*_load_mask" +- [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v") +- (vec_merge:VI12_AVX512VL +- (unspec:VI12_AVX512VL +- [(match_operand:VI12_AVX512VL 1 "memory_operand" "m")] ++ [(set (match_operand:VI12HFBF_AVX512VL 0 "register_operand" "=v") ++ (vec_merge:VI12HFBF_AVX512VL ++ (unspec:VI12HFBF_AVX512VL ++ [(match_operand:VI12HFBF_AVX512VL 1 "memory_operand" "m")] + UNSPEC_MASKLOAD) +- (match_operand:VI12_AVX512VL 2 "nonimm_or_0_operand" "0C") ++ (match_operand:VI12HFBF_AVX512VL 2 "nonimm_or_0_operand" "0C") + (match_operand: 3 "register_operand" "Yk")))] + "TARGET_AVX512BW" + "vmovdqu\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" +@@ -1481,9 +1481,9 @@ (define_insn "*_load_mask" + (set_attr "mode" "")]) + + (define_insn_and_split "*_load" +- [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v") +- (unspec:VI12_AVX512VL +- [(match_operand:VI12_AVX512VL 1 "memory_operand" "m")] ++ [(set (match_operand:VI12HFBF_AVX512VL 0 "register_operand" "=v") ++ (unspec:VI12HFBF_AVX512VL ++ [(match_operand:VI12HFBF_AVX512VL 1 "memory_operand" "m")] + UNSPEC_MASKLOAD))] + "TARGET_AVX512BW" + "#" +@@ -1610,7 +1610,7 @@ (define_insn "_blendm" + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +-(define_insn "_store_mask" ++(define_insn "*_store_mask" + [(set (match_operand:V48_AVX512VL 0 "memory_operand" "=m") + (vec_merge:V48_AVX512VL + (match_operand:V48_AVX512VL 1 "register_operand" "v") +@@ -1638,7 +1638,7 @@ (define_insn "_store_mask" + (set_attr "memory" "store") + (set_attr "mode" "")]) + +-(define_insn "_store_mask" ++(define_insn "*_store_mask" + [(set (match_operand:VI12HFBF_AVX512VL 0 "memory_operand" "=m") + (vec_merge:VI12HFBF_AVX512VL + (match_operand:VI12HFBF_AVX512VL 1 "register_operand" "v") +@@ -26533,17 +26533,21 @@ (define_expand "maskload" + "TARGET_AVX") + + (define_expand "maskload" +- [(set (match_operand:V48H_AVX512VL 0 "register_operand") +- (vec_merge:V48H_AVX512VL +- (match_operand:V48H_AVX512VL 1 "memory_operand") ++ [(set (match_operand:V48_AVX512VL 0 "register_operand") ++ (vec_merge:V48_AVX512VL ++ (unspec:V48_AVX512VL ++ [(match_operand:V48_AVX512VL 1 "memory_operand")] ++ UNSPEC_MASKLOAD) + (match_dup 0) + (match_operand: 2 "register_operand")))] + "TARGET_AVX512F") + + (define_expand "maskload" +- [(set (match_operand:VI12_AVX512VL 0 "register_operand") +- (vec_merge:VI12_AVX512VL +- (match_operand:VI12_AVX512VL 1 "memory_operand") ++ [(set (match_operand:VI12HFBF_AVX512VL 0 "register_operand") ++ (vec_merge:VI12HFBF_AVX512VL ++ (unspec:VI12HFBF_AVX512VL ++ [(match_operand:VI12HFBF_AVX512VL 1 "memory_operand")] ++ UNSPEC_MASKLOAD) + (match_dup 0) + (match_operand: 2 "register_operand")))] + "TARGET_AVX512BW") +@@ -26558,21 +26562,66 @@ (define_expand "maskstore" + "TARGET_AVX") + + (define_expand "maskstore" +- [(set (match_operand:V48H_AVX512VL 0 "memory_operand") +- (vec_merge:V48H_AVX512VL +- (match_operand:V48H_AVX512VL 1 "register_operand") +- (match_dup 0) +- (match_operand: 2 "register_operand")))] ++ [(set (match_operand:V48_AVX512VL 0 "memory_operand") ++ (unspec:V48_AVX512VL ++ [(match_operand:V48_AVX512VL 1 "register_operand") ++ (match_dup 0) ++ (match_operand: 2 "register_operand")] ++ UNSPEC_MASKMOV))] + "TARGET_AVX512F") + + (define_expand "maskstore" +- [(set (match_operand:VI12_AVX512VL 0 "memory_operand") +- (vec_merge:VI12_AVX512VL +- (match_operand:VI12_AVX512VL 1 "register_operand") +- (match_dup 0) +- (match_operand: 2 "register_operand")))] ++ [(set (match_operand:VI12HFBF_AVX512VL 0 "memory_operand") ++ (unspec:VI12HFBF_AVX512VL ++ [(match_operand:VI12HFBF_AVX512VL 1 "register_operand") ++ (match_dup 0) ++ (match_operand: 2 "register_operand")] ++ UNSPEC_MASKMOV))] + "TARGET_AVX512BW") + ++(define_insn "_store_mask" ++ [(set (match_operand:V48_AVX512VL 0 "memory_operand" "=m") ++ (unspec:V48_AVX512VL ++ [(match_operand:V48_AVX512VL 1 "register_operand" "v") ++ (match_dup 0) ++ (match_operand: 2 "register_operand" "Yk")] ++ UNSPEC_MASKMOV))] ++ "TARGET_AVX512F" ++{ ++ if (FLOAT_MODE_P (GET_MODE_INNER (mode))) ++ { ++ if (misaligned_operand (operands[0], mode)) ++ return "vmovu\t{%1, %0%{%2%}|%0%{%2%}, %1}"; ++ else ++ return "vmova\t{%1, %0%{%2%}|%0%{%2%}, %1}"; ++ } ++ else ++ { ++ if (misaligned_operand (operands[0], mode)) ++ return "vmovdqu\t{%1, %0%{%2%}|%0%{%2%}, %1}"; ++ else ++ return "vmovdqa\t{%1, %0%{%2%}|%0%{%2%}, %1}"; ++ } ++} ++ [(set_attr "type" "ssemov") ++ (set_attr "prefix" "evex") ++ (set_attr "memory" "store") ++ (set_attr "mode" "")]) ++ ++(define_insn "_store_mask" ++ [(set (match_operand:VI12HFBF_AVX512VL 0 "memory_operand" "=m") ++ (unspec:VI12HFBF_AVX512VL ++ [(match_operand:VI12HFBF_AVX512VL 1 "register_operand" "v") ++ (match_dup 0) ++ (match_operand: 2 "register_operand" "Yk")] ++ UNSPEC_MASKMOV))] ++ "TARGET_AVX512BW" ++ "vmovdqu\t{%1, %0%{%2%}|%0%{%2%}, %1}" ++ [(set_attr "type" "ssemov") ++ (set_attr "prefix" "evex") ++ (set_attr "memory" "store") ++ (set_attr "mode" "")]) ++ + (define_expand "cbranch4" + [(set (reg:CC FLAGS_REG) + (compare:CC (match_operand:VI48_AVX 1 "register_operand") +--- a/src/gcc/config/loongarch/loongarch.md ++++ b/src/gcc/config/loongarch/loongarch.md +@@ -2854,6 +2854,10 @@ (define_insn "*jump_pic" + } + [(set_attr "type" "branch")]) + ++;; Micro-architecture unconditionally treats a "jr $ra" as "return from subroutine", ++;; non-returning indirect jumps through $ra would interfere with both subroutine ++;; return prediction and the more general indirect branch prediction. ++ + (define_expand "indirect_jump" + [(set (pc) (match_operand 0 "register_operand"))] + "" +@@ -2864,7 +2868,7 @@ (define_expand "indirect_jump" + }) + + (define_insn "@indirect_jump" +- [(set (pc) (match_operand:P 0 "register_operand" "r"))] ++ [(set (pc) (match_operand:P 0 "register_operand" "e"))] + "" + "jr\t%0" + [(set_attr "type" "jump") +@@ -2887,7 +2891,7 @@ (define_expand "tablejump" + + (define_insn "@tablejump" + [(set (pc) +- (match_operand:P 0 "register_operand" "r")) ++ (match_operand:P 0 "register_operand" "e")) + (use (label_ref (match_operand 1 "" "")))] + "" + "jr\t%0" --- a/src/gcc/config/nvptx/mkoffload.cc +++ b/src/gcc/config/nvptx/mkoffload.cc @@ -357,6 +357,20 @@ process (FILE *in, FILE *out, uint32_t omp_requires) @@ -860,9 +10015,139 @@ size_t fidx = 0; for (id = func_ids; id; id = id->next) { +--- a/src/gcc/config/riscv/elf.h ++++ b/src/gcc/config/riscv/elf.h +@@ -37,4 +37,4 @@ along with GCC; see the file COPYING3. If not see + #undef ENDFILE_SPEC + #define ENDFILE_SPEC "crtend%O%s" + +-#define RISCV_USE_CUSTOMISED_MULTI_LIB 1 ++#define RISCV_USE_CUSTOMISED_MULTI_LIB select_by_abi_arch_cmodel +--- a/src/gcc/config/riscv/linux.h ++++ b/src/gcc/config/riscv/linux.h +@@ -35,16 +35,6 @@ along with GCC; see the file COPYING3. If not see + #undef MUSL_DYNAMIC_LINKER + #define MUSL_DYNAMIC_LINKER "/lib/ld-musl-riscv" XLEN_SPEC MUSL_ABI_SUFFIX ".so.1" + +-/* Because RISC-V only has word-sized atomics, it requries libatomic where +- others do not. So link libatomic by default, as needed. */ +-#undef LIB_SPEC +-#ifdef LD_AS_NEEDED_OPTION +-#define LIB_SPEC GNU_USER_TARGET_LIB_SPEC \ +- " %{pthread:" LD_AS_NEEDED_OPTION " -latomic " LD_NO_AS_NEEDED_OPTION "}" +-#else +-#define LIB_SPEC GNU_USER_TARGET_LIB_SPEC " -latomic " +-#endif +- + #define ICACHE_FLUSH_FUNC "__riscv_flush_icache" + + #define CPP_SPEC "%{pthread:-D_REENTRANT}" +@@ -76,3 +66,5 @@ along with GCC; see the file COPYING3. If not see + "/usr/lib" XLEN_SPEC "/" ABI_SPEC "/ " \ + "/lib/ " \ + "/usr/lib/ " ++ ++#define RISCV_USE_CUSTOMISED_MULTI_LIB select_by_abi +--- a/src/gcc/config/riscv/riscv-opts.h ++++ b/src/gcc/config/riscv/riscv-opts.h +@@ -67,6 +67,15 @@ enum stack_protector_guard { + SSP_GLOBAL /* global canary */ + }; + ++enum riscv_multilib_select_kind { ++ /* Select multilib by builtin way. */ ++ select_by_builtin, ++ /* Select multilib by ABI, arch and code model. */ ++ select_by_abi_arch_cmodel, ++ /* Select multilib by ABI only. */ ++ select_by_abi, ++}; ++ + #define MASK_ZICSR (1 << 0) + #define MASK_ZIFENCEI (1 << 1) + +--- a/src/gcc/config/riscv/riscv-protos.h ++++ b/src/gcc/config/riscv/riscv-protos.h +@@ -79,6 +79,8 @@ extern void riscv_reinit (void); + extern poly_uint64 riscv_regmode_natural_size (machine_mode); + extern bool riscv_v_ext_vector_mode_p (machine_mode); + extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT); ++extern void riscv_subword_address (rtx, rtx *, rtx *, rtx *, rtx *); ++extern void riscv_lshift_subword (machine_mode, rtx, rtx, rtx *); + + /* Routines implemented in riscv-c.cc. */ + void riscv_cpu_cpp_builtins (cpp_reader *); --- a/src/gcc/config/riscv/riscv-vsetvl.cc +++ b/src/gcc/config/riscv/riscv-vsetvl.cc -@@ -1592,6 +1592,18 @@ backward_propagate_worthwhile_p (const basic_block cfg_bb, +@@ -732,7 +732,10 @@ insert_vsetvl (enum emit_type emit_type, rtx_insn *rinsn, + if (vlmax_avl_p (info.get_avl ())) + { + gcc_assert (has_vtype_op (rinsn) || vsetvl_insn_p (rinsn)); +- rtx vl_op = info.get_avl_reg_rtx (); ++ /* For user vsetvli a5, zero, we should use get_vl to get the VL ++ operand "a5". */ ++ rtx vl_op ++ = vsetvl_insn_p (rinsn) ? get_vl (rinsn) : info.get_avl_reg_rtx (); + gcc_assert (!vlmax_avl_p (vl_op)); + emit_vsetvl_insn (VSETVL_NORMAL, emit_type, info, vl_op, rinsn); + return VSETVL_NORMAL; +@@ -1054,6 +1057,55 @@ change_vsetvl_insn (const insn_info *insn, const vector_insn_info &info) + change_insn (rinsn, new_pat); + } + ++static void ++local_eliminate_vsetvl_insn (const vector_insn_info &dem) ++{ ++ const insn_info *insn = dem.get_insn (); ++ if (!insn || insn->is_artificial ()) ++ return; ++ rtx_insn *rinsn = insn->rtl (); ++ const bb_info *bb = insn->bb (); ++ if (vsetvl_insn_p (rinsn)) ++ { ++ rtx vl = get_vl (rinsn); ++ for (insn_info *i = insn->next_nondebug_insn (); ++ real_insn_and_same_bb_p (i, bb); i = i->next_nondebug_insn ()) ++ { ++ if (i->is_call () || i->is_asm () ++ || find_access (i->defs (), VL_REGNUM) ++ || find_access (i->defs (), VTYPE_REGNUM)) ++ return; ++ ++ if (has_vtype_op (i->rtl ())) ++ { ++ if (!PREV_INSN (i->rtl ())) ++ return; ++ if (!NONJUMP_INSN_P (PREV_INSN (i->rtl ()))) ++ return; ++ if (!vsetvl_discard_result_insn_p (PREV_INSN (i->rtl ()))) ++ return; ++ rtx avl = get_avl (i->rtl ()); ++ if (avl != vl) ++ return; ++ set_info *def = find_access (i->uses (), REGNO (avl))->def (); ++ if (def->insn () != insn) ++ return; ++ ++ vector_insn_info new_info; ++ new_info.parse_insn (i); ++ if (!new_info.skip_avl_compatible_p (dem)) ++ return; ++ ++ new_info.set_avl_info (dem.get_avl_info ()); ++ new_info = dem.merge (new_info, LOCAL_MERGE); ++ change_vsetvl_insn (insn, new_info); ++ eliminate_insn (PREV_INSN (i->rtl ())); ++ return; ++ } ++ } ++ } ++} ++ + static bool + source_equal_p (insn_info *insn1, insn_info *insn2) + { +@@ -1592,6 +1644,18 @@ backward_propagate_worthwhile_p (const basic_block cfg_bb, return true; } @@ -881,7 +10166,61 @@ avl_info::avl_info (const avl_info &other) { m_value = other.get_value (); -@@ -3924,7 +3936,7 @@ pass_vsetvl::cleanup_insns (void) const +@@ -1984,6 +2048,19 @@ vector_insn_info::compatible_p (const vector_insn_info &other) const + return true; + } + ++bool ++vector_insn_info::skip_avl_compatible_p (const vector_insn_info &other) const ++{ ++ gcc_assert (valid_or_dirty_p () && other.valid_or_dirty_p () ++ && "Can't compare invalid demanded infos"); ++ unsigned array_size = sizeof (incompatible_conds) / sizeof (demands_cond); ++ /* Bypass AVL incompatible cases. */ ++ for (unsigned i = 1; i < array_size; i++) ++ if (incompatible_conds[i].dual_incompatible_p (*this, other)) ++ return false; ++ return true; ++} ++ + bool + vector_insn_info::compatible_avl_p (const vl_vtype_info &other) const + { +@@ -2178,7 +2255,7 @@ vector_insn_info::fuse_mask_policy (const vector_insn_info &info1, + + vector_insn_info + vector_insn_info::merge (const vector_insn_info &merge_info, +- enum merge_type type = LOCAL_MERGE) const ++ enum merge_type type) const + { + if (!vsetvl_insn_p (get_insn ()->rtl ())) + gcc_assert (this->compatible_p (merge_info) +@@ -2684,7 +2761,7 @@ pass_vsetvl::compute_local_backward_infos (const bb_info *bb) + && !reg_available_p (insn, change)) + && change.compatible_p (info)) + { +- info = change.merge (info); ++ info = change.merge (info, LOCAL_MERGE); + /* Fix PR109399, we should update user vsetvl instruction + if there is a change in demand fusion. */ + if (vsetvl_insn_p (insn->rtl ())) +@@ -3913,6 +3990,15 @@ pass_vsetvl::cleanup_insns (void) const + for (insn_info *insn : bb->real_nondebug_insns ()) + { + rtx_insn *rinsn = insn->rtl (); ++ const auto &dem = m_vector_manager->vector_insn_infos[insn->uid ()]; ++ /* Eliminate local vsetvl: ++ bb 0: ++ vsetvl a5,a6,... ++ vsetvl zero,a5. ++ ++ Eliminate vsetvl in bb2 when a5 is only coming from ++ bb 0. */ ++ local_eliminate_vsetvl_insn (dem); + + if (vlmax_avl_insn_p (rinsn)) + { +@@ -3924,7 +4010,7 @@ pass_vsetvl::cleanup_insns (void) const if (!has_vl_op (rinsn) || !REG_P (get_vl (rinsn))) continue; rtx avl = get_vl (rinsn); @@ -890,6 +10229,451 @@ { /* Get the list of uses for the new instruction. */ auto attempt = crtl->ssa->new_change_attempt (); +--- a/src/gcc/config/riscv/riscv-vsetvl.h ++++ b/src/gcc/config/riscv/riscv-vsetvl.h +@@ -380,6 +380,7 @@ public: + void fuse_mask_policy (const vector_insn_info &, const vector_insn_info &); + + bool compatible_p (const vector_insn_info &) const; ++ bool skip_avl_compatible_p (const vector_insn_info &) const; + bool compatible_avl_p (const vl_vtype_info &) const; + bool compatible_avl_p (const avl_info &) const; + bool compatible_vtype_p (const vl_vtype_info &) const; +--- a/src/gcc/config/riscv/riscv.cc ++++ b/src/gcc/config/riscv/riscv.cc +@@ -6857,10 +6857,9 @@ riscv_asan_shadow_offset (void) + { + /* We only have libsanitizer support for RV64 at present. + +- This number must match kRiscv*_ShadowOffset* in the file +- libsanitizer/asan/asan_mapping.h which is currently 1<<29 for rv64, +- even though 1<<36 makes more sense. */ +- return TARGET_64BIT ? (HOST_WIDE_INT_1 << 29) : 0; ++ This number must match ASAN_SHADOW_OFFSET_CONST in the file ++ libsanitizer/asan/asan_mapping.h. */ ++ return TARGET_64BIT ? HOST_WIDE_INT_UC (0xd55550000) : 0; + } + + /* Implement TARGET_MANGLE_TYPE. */ +@@ -7143,6 +7142,55 @@ riscv_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) + & ~zeroed_hardregs); + } + ++/* Given memory reference MEM, expand code to compute the aligned ++ memory address, shift and mask values and store them into ++ *ALIGNED_MEM, *SHIFT, *MASK and *NOT_MASK. */ ++ ++void ++riscv_subword_address (rtx mem, rtx *aligned_mem, rtx *shift, rtx *mask, ++ rtx *not_mask) ++{ ++ /* Align the memory address to a word. */ ++ rtx addr = force_reg (Pmode, XEXP (mem, 0)); ++ ++ rtx addr_mask = gen_int_mode (-4, Pmode); ++ ++ rtx aligned_addr = gen_reg_rtx (Pmode); ++ emit_move_insn (aligned_addr, gen_rtx_AND (Pmode, addr, addr_mask)); ++ ++ *aligned_mem = change_address (mem, SImode, aligned_addr); ++ ++ /* Calculate the shift amount. */ ++ emit_move_insn (*shift, gen_rtx_AND (SImode, gen_lowpart (SImode, addr), ++ gen_int_mode (3, SImode))); ++ emit_move_insn (*shift, gen_rtx_ASHIFT (SImode, *shift, ++ gen_int_mode (3, SImode))); ++ ++ /* Calculate the mask. */ ++ int unshifted_mask = GET_MODE_MASK (GET_MODE (mem)); ++ ++ emit_move_insn (*mask, gen_int_mode (unshifted_mask, SImode)); ++ ++ emit_move_insn (*mask, gen_rtx_ASHIFT (SImode, *mask, ++ gen_lowpart (QImode, *shift))); ++ ++ emit_move_insn (*not_mask, gen_rtx_NOT (SImode, *mask)); ++} ++ ++/* Leftshift a subword within an SImode register. */ ++ ++void ++riscv_lshift_subword (machine_mode mode, rtx value, rtx shift, ++ rtx *shifted_value) ++{ ++ rtx value_reg = gen_reg_rtx (SImode); ++ emit_move_insn (value_reg, simplify_gen_subreg (SImode, value, ++ mode, 0)); ++ ++ emit_move_insn (*shifted_value, gen_rtx_ASHIFT (SImode, value_reg, ++ gen_lowpart (QImode, shift))); ++} ++ + /* Initialize the GCC target structure. */ + #undef TARGET_ASM_ALIGNED_HI_OP + #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" +--- a/src/gcc/config/riscv/riscv.opt ++++ b/src/gcc/config/riscv/riscv.opt +@@ -254,3 +254,7 @@ Enum(isa_spec_class) String(20191213) Value(ISA_SPEC_CLASS_20191213) + misa-spec= + Target RejectNegative Joined Enum(isa_spec_class) Var(riscv_isa_spec) Init(TARGET_DEFAULT_ISA_SPEC) + Set the version of RISC-V ISA spec. ++ ++minline-atomics ++Target Var(TARGET_INLINE_SUBWORD_ATOMIC) Init(1) ++Always inline subword atomic operations. +--- a/src/gcc/config/riscv/sync.md ++++ b/src/gcc/config/riscv/sync.md +@@ -21,8 +21,11 @@ + + (define_c_enum "unspec" [ + UNSPEC_COMPARE_AND_SWAP ++ UNSPEC_COMPARE_AND_SWAP_SUBWORD + UNSPEC_SYNC_OLD_OP ++ UNSPEC_SYNC_OLD_OP_SUBWORD + UNSPEC_SYNC_EXCHANGE ++ UNSPEC_SYNC_EXCHANGE_SUBWORD + UNSPEC_ATOMIC_STORE + UNSPEC_MEMORY_BARRIER + ]) +@@ -91,6 +94,135 @@ (define_insn "atomic_fetch_" + [(set_attr "type" "atomic") + (set (attr "length") (const_int 8))]) + ++(define_insn "subword_atomic_fetch_strong_" ++ [(set (match_operand:SI 0 "register_operand" "=&r") ;; old value at mem ++ (match_operand:SI 1 "memory_operand" "+A")) ;; mem location ++ (set (match_dup 1) ++ (unspec_volatile:SI ++ [(any_atomic:SI (match_dup 1) ++ (match_operand:SI 2 "register_operand" "rI")) ;; value for op ++ (match_operand:SI 3 "register_operand" "rI")] ;; mask ++ UNSPEC_SYNC_OLD_OP_SUBWORD)) ++ (match_operand:SI 4 "register_operand" "rI") ;; not_mask ++ (clobber (match_scratch:SI 5 "=&r")) ;; tmp_1 ++ (clobber (match_scratch:SI 6 "=&r"))] ;; tmp_2 ++ "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" ++ { ++ return "1:\;" ++ "lr.w.aq\t%0, %1\;" ++ "\t%5, %0, %2\;" ++ "and\t%5, %5, %3\;" ++ "and\t%6, %0, %4\;" ++ "or\t%6, %6, %5\;" ++ "sc.w.rl\t%5, %6, %1\;" ++ "bnez\t%5, 1b"; ++ } ++ [(set (attr "length") (const_int 28))]) ++ ++(define_expand "atomic_fetch_nand" ++ [(match_operand:SHORT 0 "register_operand") ;; old value at mem ++ (not:SHORT (and:SHORT (match_operand:SHORT 1 "memory_operand") ;; mem location ++ (match_operand:SHORT 2 "reg_or_0_operand"))) ;; value for op ++ (match_operand:SI 3 "const_int_operand")] ;; model ++ "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" ++{ ++ /* We have no QImode/HImode atomics, so form a mask, then use ++ subword_atomic_fetch_strong_nand to implement a LR/SC version of the ++ operation. */ ++ ++ /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining ++ is disabled. */ ++ ++ rtx old = gen_reg_rtx (SImode); ++ rtx mem = operands[1]; ++ rtx value = operands[2]; ++ rtx aligned_mem = gen_reg_rtx (SImode); ++ rtx shift = gen_reg_rtx (SImode); ++ rtx mask = gen_reg_rtx (SImode); ++ rtx not_mask = gen_reg_rtx (SImode); ++ ++ riscv_subword_address (mem, &aligned_mem, &shift, &mask, ¬_mask); ++ ++ rtx shifted_value = gen_reg_rtx (SImode); ++ riscv_lshift_subword (mode, value, shift, &shifted_value); ++ ++ emit_insn (gen_subword_atomic_fetch_strong_nand (old, aligned_mem, ++ shifted_value, ++ mask, not_mask)); ++ ++ emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old, ++ gen_lowpart (QImode, shift))); ++ ++ emit_move_insn (operands[0], gen_lowpart (mode, old)); ++ ++ DONE; ++}) ++ ++(define_insn "subword_atomic_fetch_strong_nand" ++ [(set (match_operand:SI 0 "register_operand" "=&r") ;; old value at mem ++ (match_operand:SI 1 "memory_operand" "+A")) ;; mem location ++ (set (match_dup 1) ++ (unspec_volatile:SI ++ [(not:SI (and:SI (match_dup 1) ++ (match_operand:SI 2 "register_operand" "rI"))) ;; value for op ++ (match_operand:SI 3 "register_operand" "rI")] ;; mask ++ UNSPEC_SYNC_OLD_OP_SUBWORD)) ++ (match_operand:SI 4 "register_operand" "rI") ;; not_mask ++ (clobber (match_scratch:SI 5 "=&r")) ;; tmp_1 ++ (clobber (match_scratch:SI 6 "=&r"))] ;; tmp_2 ++ "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" ++ { ++ return "1:\;" ++ "lr.w.aq\t%0, %1\;" ++ "and\t%5, %0, %2\;" ++ "not\t%5, %5\;" ++ "and\t%5, %5, %3\;" ++ "and\t%6, %0, %4\;" ++ "or\t%6, %6, %5\;" ++ "sc.w.rl\t%5, %6, %1\;" ++ "bnez\t%5, 1b"; ++ } ++ [(set (attr "length") (const_int 32))]) ++ ++(define_expand "atomic_fetch_" ++ [(match_operand:SHORT 0 "register_operand") ;; old value at mem ++ (any_atomic:SHORT (match_operand:SHORT 1 "memory_operand") ;; mem location ++ (match_operand:SHORT 2 "reg_or_0_operand")) ;; value for op ++ (match_operand:SI 3 "const_int_operand")] ;; model ++ "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" ++{ ++ /* We have no QImode/HImode atomics, so form a mask, then use ++ subword_atomic_fetch_strong_ to implement a LR/SC version of the ++ operation. */ ++ ++ /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining ++ is disabled. */ ++ ++ rtx old = gen_reg_rtx (SImode); ++ rtx mem = operands[1]; ++ rtx value = operands[2]; ++ rtx aligned_mem = gen_reg_rtx (SImode); ++ rtx shift = gen_reg_rtx (SImode); ++ rtx mask = gen_reg_rtx (SImode); ++ rtx not_mask = gen_reg_rtx (SImode); ++ ++ riscv_subword_address (mem, &aligned_mem, &shift, &mask, ¬_mask); ++ ++ rtx shifted_value = gen_reg_rtx (SImode); ++ riscv_lshift_subword (mode, value, shift, &shifted_value); ++ ++ emit_insn (gen_subword_atomic_fetch_strong_ (old, aligned_mem, ++ shifted_value, ++ mask, not_mask)); ++ ++ emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old, ++ gen_lowpart (QImode, shift))); ++ ++ emit_move_insn (operands[0], gen_lowpart (mode, old)); ++ ++ DONE; ++}) ++ + (define_insn "atomic_exchange" + [(set (match_operand:GPR 0 "register_operand" "=&r") + (unspec_volatile:GPR +@@ -104,6 +236,56 @@ (define_insn "atomic_exchange" + [(set_attr "type" "atomic") + (set (attr "length") (const_int 8))]) + ++(define_expand "atomic_exchange" ++ [(match_operand:SHORT 0 "register_operand") ;; old value at mem ++ (match_operand:SHORT 1 "memory_operand") ;; mem location ++ (match_operand:SHORT 2 "register_operand") ;; value ++ (match_operand:SI 3 "const_int_operand")] ;; model ++ "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" ++{ ++ rtx old = gen_reg_rtx (SImode); ++ rtx mem = operands[1]; ++ rtx value = operands[2]; ++ rtx aligned_mem = gen_reg_rtx (SImode); ++ rtx shift = gen_reg_rtx (SImode); ++ rtx mask = gen_reg_rtx (SImode); ++ rtx not_mask = gen_reg_rtx (SImode); ++ ++ riscv_subword_address (mem, &aligned_mem, &shift, &mask, ¬_mask); ++ ++ rtx shifted_value = gen_reg_rtx (SImode); ++ riscv_lshift_subword (mode, value, shift, &shifted_value); ++ ++ emit_insn (gen_subword_atomic_exchange_strong (old, aligned_mem, ++ shifted_value, not_mask)); ++ ++ emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old, ++ gen_lowpart (QImode, shift))); ++ ++ emit_move_insn (operands[0], gen_lowpart (mode, old)); ++ DONE; ++}) ++ ++(define_insn "subword_atomic_exchange_strong" ++ [(set (match_operand:SI 0 "register_operand" "=&r") ;; old value at mem ++ (match_operand:SI 1 "memory_operand" "+A")) ;; mem location ++ (set (match_dup 1) ++ (unspec_volatile:SI ++ [(match_operand:SI 2 "reg_or_0_operand" "rI") ;; value ++ (match_operand:SI 3 "reg_or_0_operand" "rI")] ;; not_mask ++ UNSPEC_SYNC_EXCHANGE_SUBWORD)) ++ (clobber (match_scratch:SI 4 "=&r"))] ;; tmp_1 ++ "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" ++ { ++ return "1:\;" ++ "lr.w.aq\t%0, %1\;" ++ "and\t%4, %0, %3\;" ++ "or\t%4, %4, %2\;" ++ "sc.w.rl\t%4, %4, %1\;" ++ "bnez\t%4, 1b"; ++ } ++ [(set (attr "length") (const_int 20))]) ++ + (define_insn "atomic_cas_value_strong" + [(set (match_operand:GPR 0 "register_operand" "=&r") + (match_operand:GPR 1 "memory_operand" "+A")) +@@ -153,6 +335,125 @@ (define_expand "atomic_compare_and_swap" + DONE; + }) + ++(define_expand "atomic_compare_and_swap" ++ [(match_operand:SI 0 "register_operand") ;; bool output ++ (match_operand:SHORT 1 "register_operand") ;; val output ++ (match_operand:SHORT 2 "memory_operand") ;; memory ++ (match_operand:SHORT 3 "reg_or_0_operand") ;; expected value ++ (match_operand:SHORT 4 "reg_or_0_operand") ;; desired value ++ (match_operand:SI 5 "const_int_operand") ;; is_weak ++ (match_operand:SI 6 "const_int_operand") ;; mod_s ++ (match_operand:SI 7 "const_int_operand")] ;; mod_f ++ "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" ++{ ++ emit_insn (gen_atomic_cas_value_strong (operands[1], operands[2], ++ operands[3], operands[4], ++ operands[6], operands[7])); ++ ++ rtx val = gen_reg_rtx (SImode); ++ if (operands[1] != const0_rtx) ++ emit_move_insn (val, gen_rtx_SIGN_EXTEND (SImode, operands[1])); ++ else ++ emit_move_insn (val, const0_rtx); ++ ++ rtx exp = gen_reg_rtx (SImode); ++ if (operands[3] != const0_rtx) ++ emit_move_insn (exp, gen_rtx_SIGN_EXTEND (SImode, operands[3])); ++ else ++ emit_move_insn (exp, const0_rtx); ++ ++ rtx compare = val; ++ if (exp != const0_rtx) ++ { ++ rtx difference = gen_rtx_MINUS (SImode, val, exp); ++ compare = gen_reg_rtx (SImode); ++ emit_move_insn (compare, difference); ++ } ++ ++ if (word_mode != SImode) ++ { ++ rtx reg = gen_reg_rtx (word_mode); ++ emit_move_insn (reg, gen_rtx_SIGN_EXTEND (word_mode, compare)); ++ compare = reg; ++ } ++ ++ emit_move_insn (operands[0], gen_rtx_EQ (SImode, compare, const0_rtx)); ++ DONE; ++}) ++ ++(define_expand "atomic_cas_value_strong" ++ [(match_operand:SHORT 0 "register_operand") ;; val output ++ (match_operand:SHORT 1 "memory_operand") ;; memory ++ (match_operand:SHORT 2 "reg_or_0_operand") ;; expected value ++ (match_operand:SHORT 3 "reg_or_0_operand") ;; desired value ++ (match_operand:SI 4 "const_int_operand") ;; mod_s ++ (match_operand:SI 5 "const_int_operand") ;; mod_f ++ (match_scratch:SHORT 6)] ++ "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" ++{ ++ /* We have no QImode/HImode atomics, so form a mask, then use ++ subword_atomic_cas_strong to implement a LR/SC version of the ++ operation. */ ++ ++ /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining ++ is disabled. */ ++ ++ rtx old = gen_reg_rtx (SImode); ++ rtx mem = operands[1]; ++ rtx aligned_mem = gen_reg_rtx (SImode); ++ rtx shift = gen_reg_rtx (SImode); ++ rtx mask = gen_reg_rtx (SImode); ++ rtx not_mask = gen_reg_rtx (SImode); ++ ++ riscv_subword_address (mem, &aligned_mem, &shift, &mask, ¬_mask); ++ ++ rtx o = operands[2]; ++ rtx n = operands[3]; ++ rtx shifted_o = gen_reg_rtx (SImode); ++ rtx shifted_n = gen_reg_rtx (SImode); ++ ++ riscv_lshift_subword (mode, o, shift, &shifted_o); ++ riscv_lshift_subword (mode, n, shift, &shifted_n); ++ ++ emit_move_insn (shifted_o, gen_rtx_AND (SImode, shifted_o, mask)); ++ emit_move_insn (shifted_n, gen_rtx_AND (SImode, shifted_n, mask)); ++ ++ emit_insn (gen_subword_atomic_cas_strong (old, aligned_mem, ++ shifted_o, shifted_n, ++ mask, not_mask)); ++ ++ emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old, ++ gen_lowpart (QImode, shift))); ++ ++ emit_move_insn (operands[0], gen_lowpart (mode, old)); ++ ++ DONE; ++}) ++ ++(define_insn "subword_atomic_cas_strong" ++ [(set (match_operand:SI 0 "register_operand" "=&r") ;; old value at mem ++ (match_operand:SI 1 "memory_operand" "+A")) ;; mem location ++ (set (match_dup 1) ++ (unspec_volatile:SI [(match_operand:SI 2 "reg_or_0_operand" "rJ") ;; expected value ++ (match_operand:SI 3 "reg_or_0_operand" "rJ")] ;; desired value ++ UNSPEC_COMPARE_AND_SWAP_SUBWORD)) ++ (match_operand:SI 4 "register_operand" "rI") ;; mask ++ (match_operand:SI 5 "register_operand" "rI") ;; not_mask ++ (clobber (match_scratch:SI 6 "=&r"))] ;; tmp_1 ++ "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" ++ { ++ return "1:\;" ++ "lr.w.aq\t%0, %1\;" ++ "and\t%6, %0, %4\;" ++ "bne\t%6, %z2, 1f\;" ++ "and\t%6, %0, %5\;" ++ "or\t%6, %6, %3\;" ++ "sc.w.rl\t%6, %6, %1\;" ++ "bnez\t%6, 1b\;" ++ "1:"; ++ } ++ [(set (attr "length") (const_int 28))]) ++ + (define_expand "atomic_test_and_set" + [(match_operand:QI 0 "register_operand" "") ;; bool output + (match_operand:QI 1 "memory_operand" "+A") ;; memory +@@ -160,7 +461,7 @@ (define_expand "atomic_test_and_set" + "TARGET_ATOMIC" + { + /* We have no QImode atomics, so use the address LSBs to form a mask, +- then use an aligned SImode atomic. */ ++ then use an aligned SImode atomic. */ + rtx result = operands[0]; + rtx mem = operands[1]; + rtx model = operands[2]; +--- a/src/gcc/config/riscv/vector.md ++++ b/src/gcc/config/riscv/vector.md +@@ -333,7 +333,7 @@ (define_attr "avl_type" "" + (symbol_ref "INTVAL (operands[7])")) + + (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\ +- viwalu,viwmul,vnshift,vimuladd,vaalu,vsmul,vsshift,\ ++ viwalu,viwmul,vnshift,vaalu,vsmul,vsshift,\ + vnclip,vicmp,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\ + vfsgnj,vfcmp,vfmuladd,vslideup,vslidedown,vislide1up,\ + vislide1down,vfslide1up,vfslide1down,vgather,viwmuladd,vfwmuladd") --- a/src/gcc/config/rs6000/altivec.md +++ b/src/gcc/config/rs6000/altivec.md @@ -385,14 +385,22 @@ (define_split @@ -918,6 +10702,328 @@ (define_insn "get_vrsave_internal" [(set (match_operand:SI 0 "register_operand" "=r") +--- a/src/gcc/config/rs6000/fusion.md ++++ b/src/gcc/config/rs6000/fusion.md +@@ -22,7 +22,7 @@ + ;; load mode is DI result mode is clobber compare mode is CC extend is none + (define_insn_and_split "*ld_cmpdi_cr0_DI_clobber_CC_none" + [(set (match_operand:CC 2 "cc_reg_operand" "=x") +- (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "m") ++ (compare:CC (match_operand:DI 1 "non_update_memory_operand" "YZ") + (match_operand:DI 3 "const_m1_to_1_operand" "n"))) + (clobber (match_scratch:DI 0 "=r"))] + "(TARGET_P10_FUSION)" +@@ -43,7 +43,7 @@ (define_insn_and_split "*ld_cmpdi_cr0_DI_clobber_CC_none" + ;; load mode is DI result mode is clobber compare mode is CCUNS extend is none + (define_insn_and_split "*ld_cmpldi_cr0_DI_clobber_CCUNS_none" + [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") +- (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "m") ++ (compare:CCUNS (match_operand:DI 1 "non_update_memory_operand" "YZ") + (match_operand:DI 3 "const_0_to_1_operand" "n"))) + (clobber (match_scratch:DI 0 "=r"))] + "(TARGET_P10_FUSION)" +@@ -64,7 +64,7 @@ (define_insn_and_split "*ld_cmpldi_cr0_DI_clobber_CCUNS_none" + ;; load mode is DI result mode is DI compare mode is CC extend is none + (define_insn_and_split "*ld_cmpdi_cr0_DI_DI_CC_none" + [(set (match_operand:CC 2 "cc_reg_operand" "=x") +- (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "m") ++ (compare:CC (match_operand:DI 1 "non_update_memory_operand" "YZ") + (match_operand:DI 3 "const_m1_to_1_operand" "n"))) + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))] + "(TARGET_P10_FUSION)" +@@ -85,7 +85,7 @@ (define_insn_and_split "*ld_cmpdi_cr0_DI_DI_CC_none" + ;; load mode is DI result mode is DI compare mode is CCUNS extend is none + (define_insn_and_split "*ld_cmpldi_cr0_DI_DI_CCUNS_none" + [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") +- (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "m") ++ (compare:CCUNS (match_operand:DI 1 "non_update_memory_operand" "YZ") + (match_operand:DI 3 "const_0_to_1_operand" "n"))) + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))] + "(TARGET_P10_FUSION)" +@@ -104,17 +104,17 @@ (define_insn_and_split "*ld_cmpldi_cr0_DI_DI_CCUNS_none" + + ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 + ;; load mode is SI result mode is clobber compare mode is CC extend is none +-(define_insn_and_split "*lwa_cmpdi_cr0_SI_clobber_CC_none" ++(define_insn_and_split "*lwz_cmpwi_cr0_SI_clobber_CC_none" + [(set (match_operand:CC 2 "cc_reg_operand" "=x") +- (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m") ++ (compare:CC (match_operand:SI 1 "non_update_memory_operand" "m") + (match_operand:SI 3 "const_m1_to_1_operand" "n"))) + (clobber (match_scratch:SI 0 "=r"))] + "(TARGET_P10_FUSION)" +- "lwa%X1 %0,%1\;cmpdi %2,%0,%3" ++ "lwz%X1 %0,%1\;cmpwi %2,%0,%3" + "&& reload_completed + && (cc_reg_not_cr0_operand (operands[2], CCmode) + || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), +- SImode, NON_PREFIXED_DS))" ++ SImode, NON_PREFIXED_D))" + [(set (match_dup 0) (match_dup 1)) + (set (match_dup 2) + (compare:CC (match_dup 0) (match_dup 3)))] +@@ -146,17 +146,17 @@ (define_insn_and_split "*lwz_cmpldi_cr0_SI_clobber_CCUNS_none" + + ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 + ;; load mode is SI result mode is SI compare mode is CC extend is none +-(define_insn_and_split "*lwa_cmpdi_cr0_SI_SI_CC_none" ++(define_insn_and_split "*lwz_cmpwi_cr0_SI_SI_CC_none" + [(set (match_operand:CC 2 "cc_reg_operand" "=x") +- (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m") ++ (compare:CC (match_operand:SI 1 "non_update_memory_operand" "m") + (match_operand:SI 3 "const_m1_to_1_operand" "n"))) + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))] + "(TARGET_P10_FUSION)" +- "lwa%X1 %0,%1\;cmpdi %2,%0,%3" ++ "lwz%X1 %0,%1\;cmpwi %2,%0,%3" + "&& reload_completed + && (cc_reg_not_cr0_operand (operands[2], CCmode) + || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), +- SImode, NON_PREFIXED_DS))" ++ SImode, NON_PREFIXED_D))" + [(set (match_dup 0) (match_dup 1)) + (set (match_dup 2) + (compare:CC (match_dup 0) (match_dup 3)))] +@@ -190,7 +190,7 @@ (define_insn_and_split "*lwz_cmpldi_cr0_SI_SI_CCUNS_none" + ;; load mode is SI result mode is EXTSI compare mode is CC extend is sign + (define_insn_and_split "*lwa_cmpdi_cr0_SI_EXTSI_CC_sign" + [(set (match_operand:CC 2 "cc_reg_operand" "=x") +- (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m") ++ (compare:CC (match_operand:SI 1 "non_update_memory_operand" "YZ") + (match_operand:SI 3 "const_m1_to_1_operand" "n"))) + (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r") (sign_extend:EXTSI (match_dup 1)))] + "(TARGET_P10_FUSION)" +@@ -205,6 +205,7 @@ (define_insn_and_split "*lwa_cmpdi_cr0_SI_EXTSI_CC_sign" + "" + [(set_attr "type" "fused_load_cmpi") + (set_attr "cost" "8") ++ (set_attr "sign_extend" "yes") + (set_attr "length" "8")]) + + ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 +--- a/src/gcc/config/rs6000/genfusion.pl ++++ b/src/gcc/config/rs6000/genfusion.pl +@@ -53,92 +53,136 @@ sub mode_to_ldst_char + return '?'; + } + ++sub gen_ld_cmpi_p10_one ++{ ++ my ($lmode, $result, $ccmode) = @_; ++ ++ my $np = "NON_PREFIXED_D"; ++ my $mempred = "non_update_memory_operand"; ++ my $extend; ++ ++ # We need to special case lwa. The prefixed_load_p function in rs6000.cc ++ # (which determines if a load instruction is prefixed) uses the fact that the ++ # register mode is different from the memory mode, and that the sign_extend ++ # attribute is set to use DS-form rules for the address instead of D-form. ++ # If the register size is the same, prefixed_load_p assumes we are doing a ++ # lwz. We change to use an lwz and word compare if we don't need to sign ++ # extend the SImode value. Otherwise if we need the value, we need to ++ # make sure the insn is marked as ds-form. ++ my $cmp_size_char = ($lmode eq "SI" ++ && $ccmode eq "CC" ++ && $result !~ /^EXT|^DI$/) ? "w" : "d"; ++ ++ if ($ccmode eq "CC") { ++ # ld and lwa are both DS-FORM. ++ ($lmode eq "DI") and $np = "NON_PREFIXED_DS"; ++ ($lmode eq "SI" && $cmp_size_char eq "d") and $np = "NON_PREFIXED_DS"; ++ } else { ++ if ($lmode eq "DI") { ++ # ld is DS-form, but lwz is not. ++ $np = "NON_PREFIXED_DS"; ++ } ++ } ++ ++ my $cmpl = ($ccmode eq "CC") ? "" : "l"; ++ my $echr = ($ccmode eq "CC" && $cmp_size_char eq "d") ? "a" : "z"; ++ if ($lmode eq "DI") { $echr = ""; } ++ my $constpred = ($ccmode eq "CC") ? "const_m1_to_1_operand" ++ : "const_0_to_1_operand"; ++ ++ # For clobber, we need a SI/DI reg in case we ++ # split because we have to sign/zero extend. ++ my $clobbermode = ($lmode =~ /^[QH]I$/) ? "GPR" : $lmode; ++ if ($result =~ /^EXT/ || $result eq "GPR" || $clobbermode eq "GPR") { ++ # We always need extension if result > lmode. ++ $extend = ($ccmode eq "CC") ? "sign" : "zero"; ++ } else { ++ # Result of SI/DI does not need sign extension. ++ $extend = "none"; ++ } ++ ++ my $ldst = mode_to_ldst_char($lmode); ++ ++ # DS-form addresses need YZ, and not m. ++ my $constraint = ($np eq "NON_PREFIXED_DS") ? "YZ" : "m"; ++ print < lmode. +- if ( $ccmode eq 'CC' ) { +- $extend = "sign"; +- } else { +- $extend = "zero"; +- } +- } else { +- # Result of SI/DI does not need sign extension. +- $extend = "none"; +- } +- print ";; load-cmpi fusion pattern generated by gen_ld_cmpi_p10\n"; +- print ";; load mode is $lmode result mode is $result compare mode is $ccmode extend is $extend\n"; +- +- print "(define_insn_and_split \"*l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}_${result}_${ccmode}_${extend}\"\n"; +- print " [(set (match_operand:${ccmode} 2 \"cc_reg_operand\" \"=x\")\n"; +- print " (compare:${ccmode} (match_operand:${lmode} 1 \"${mempred}\" \"m\")\n"; +- if ($ccmode eq 'CCUNS') { print " "; } +- print " (match_operand:${lmode} 3 \"${constpred}\" \"n\")))\n"; +- if ($result eq 'clobber') { +- print " (clobber (match_scratch:${clobbermode} 0 \"=r\"))]\n"; +- } elsif ($result eq $lmode) { +- print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (match_dup 1))]\n"; +- } else { +- print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (${extend}_extend:${result} (match_dup 1)))]\n"; +- } +- print " \"(TARGET_P10_FUSION)\"\n"; +- print " \"l${ldst}${echr}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3\"\n"; +- print " \"&& reload_completed\n"; +- print " && (cc_reg_not_cr0_operand (operands[2], CCmode)\n"; +- print " || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),\n"; +- print " ${lmode}mode, ${np}))\"\n"; +- +- if ($extend eq "none") { +- print " [(set (match_dup 0) (match_dup 1))\n"; +- } else { +- $resultmode = $result; +- if ( $result eq 'clobber' ) { $resultmode = $clobbermode } +- print " [(set (match_dup 0) (${extend}_extend:${resultmode} (match_dup 1)))\n"; +- } +- print " (set (match_dup 2)\n"; +- print " (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n"; +- print " \"\"\n"; +- print " [(set_attr \"type\" \"fused_load_cmpi\")\n"; +- print " (set_attr \"cost\" \"8\")\n"; +- print " (set_attr \"length\" \"8\")])\n"; +- print "\n"; ++ foreach my $lmode (qw/DI SI HI QI/) { ++ foreach my $result ("clobber", $lmode, "EXT$lmode") { ++ # EXTDI does not exist, and we cannot directly produce HI/QI results. ++ next if $result =~ /^(QI|HI|EXTDI)$/; ++ ++ # Don't allow EXTQI because that would allow HI result which we can't do. ++ $result = "GPR" if $result eq "EXTQI"; ++ ++ foreach my $ccmode (qw/CC CCUNS/) { ++ # We do not have signed single-byte loads. ++ next if ($lmode eq "QI" and $ccmode eq "CC"); ++ ++ gen_ld_cmpi_p10_one($lmode, $result, $ccmode); + } + } + } --- a/src/gcc/config/rs6000/predicates.md +++ b/src/gcc/config/rs6000/predicates.md @@ -798,6 +798,43 @@ (define_predicate "easy_vector_constant_vsldoi" @@ -964,11 +11070,63 @@ ;; Return 1 if operand is a vector int register or is either a vector constant ;; of all 0 bits of a vector constant of all 1 bits. (define_predicate "vector_int_reg_or_same_bit" +@@ -1088,20 +1125,6 @@ (define_predicate "lwa_operand" + return INTVAL (offset) % 4 == 0; + }) + +-;; Return 1 if the operand is a memory operand that has a valid address for +-;; a DS-form instruction. I.e. the address has to be either just a register, +-;; or register + const where the two low order bits of const are zero. +-(define_predicate "ds_form_mem_operand" +- (match_code "subreg,mem") +-{ +- if (!any_memory_operand (op, mode)) +- return false; +- +- rtx addr = XEXP (op, 0); +- +- return address_to_insn_form (addr, mode, NON_PREFIXED_DS) == INSN_FORM_DS; +-}) +- + ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. + (define_predicate "symbol_ref_operand" + (and (match_code "symbol_ref") --- a/src/gcc/config/rs6000/rs6000-builtins.def +++ b/src/gcc/config/rs6000/rs6000-builtins.def -@@ -2797,6 +2797,19 @@ - const vsi __builtin_vsx_xxbrw_v4si (vsi); - XXBRW_V4SI p9_xxbrw_v4si {} +@@ -2009,6 +2009,13 @@ + const vsll __builtin_vsx_xxspltd_2di (vsll, const int<1>); + XXSPLTD_V2DI vsx_xxspltd_v2di {} + ++ const vsq __builtin_pack_vector_int128 (unsigned long long, \ ++ unsigned long long); ++ PACK_V1TI packv1ti {} ++ ++ const unsigned long __builtin_unpack_vector_int128 (vsq, const int<1>); ++ UNPACK_V1TI unpackv1ti {} ++ + + ; Power7 builtins (ISA 2.06). + [power7] +@@ -2030,16 +2037,9 @@ + const unsigned int __builtin_divweu (unsigned int, unsigned int); + DIVWEU diveu_si {} + +- const vsq __builtin_pack_vector_int128 (unsigned long long, \ +- unsigned long long); +- PACK_V1TI packv1ti {} +- + void __builtin_ppc_speculation_barrier (); + SPECBARR speculation_barrier {} + +- const unsigned long __builtin_unpack_vector_int128 (vsq, const int<1>); +- UNPACK_V1TI unpackv1ti {} +- + + ; Power7 builtins requiring 64-bit GPRs (even with 32-bit addressing). + [power7-64] +@@ -2797,6 +2797,19 @@ + const vsi __builtin_vsx_xxbrw_v4si (vsi); + XXBRW_V4SI p9_xxbrw_v4si {} + const signed int __builtin_vsx_scalar_cmp_exp_qp_eq (_Float128, _Float128); + VSCEQPEQ xscmpexpqp_eq_kf {} @@ -1006,9 +11164,173 @@ fpmath _Float128 __builtin_sqrtf128_round_to_odd (_Float128); SQRTF128_ODD sqrtkf2_odd {} +--- a/src/gcc/config/rs6000/rs6000.cc ++++ b/src/gcc/config/rs6000/rs6000.cc +@@ -8209,7 +8209,8 @@ darwin_rs6000_special_round_type_align (tree type, unsigned int computed, + type = TREE_TYPE (type); + } while (AGGREGATE_TYPE_P (type)); + +- if (! AGGREGATE_TYPE_P (type) && type != error_mark_node) ++ if (type != error_mark_node && ! AGGREGATE_TYPE_P (type) ++ && ! TYPE_PACKED (type) && maximum_field_alignment == 0) + align = MAX (align, TYPE_ALIGN (type)); + + return align; +@@ -17299,7 +17300,7 @@ output_toc (FILE *file, rtx x, int labelno, machine_mode mode) + if (DECIMAL_FLOAT_MODE_P (GET_MODE (x))) + REAL_VALUE_TO_TARGET_DECIMAL128 (*CONST_DOUBLE_REAL_VALUE (x), k); + else +- REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), k); ++ real_to_target (k, CONST_DOUBLE_REAL_VALUE (x), GET_MODE (x)); + + if (TARGET_64BIT) + { +@@ -28762,7 +28763,6 @@ vec_const_128bit_to_bytes (rtx op, + + info->all_words_same + = (info->words[0] == info->words[1] +- && info->words[0] == info->words[1] + && info->words[0] == info->words[2] + && info->words[0] == info->words[3]); + +--- a/src/gcc/config/rs6000/rs6000.md ++++ b/src/gcc/config/rs6000/rs6000.md +@@ -287,7 +287,7 @@ (define_attr "cannot_copy" "no,yes" (const_string "no")) + ;; Whether this insn has a prefixed form and a non-prefixed form. + (define_attr "maybe_prefixed" "no,yes" + (if_then_else (eq_attr "type" "load,fpload,vecload,store,fpstore,vecstore, +- integer,add") ++ integer,add,fused_load_cmpi") + (const_string "yes") + (const_string "no"))) + +@@ -302,7 +302,7 @@ (define_attr "prefixed" "no,yes" + (eq_attr "maybe_prefixed" "no")) + (const_string "no") + +- (eq_attr "type" "load,fpload,vecload") ++ (eq_attr "type" "load,fpload,vecload,fused_load_cmpi") + (if_then_else (match_test "prefixed_load_p (insn)") + (const_string "yes") + (const_string "no")) --- a/src/gcc/cp/ChangeLog +++ b/src/gcc/cp/ChangeLog -@@ -1,3 +1,57 @@ +@@ -1,3 +1,172 @@ ++2023-07-01 Patrick Palka ++ ++ Backported from master: ++ 2023-06-29 Patrick Palka ++ ++ PR c++/110468 ++ * init.cc (maybe_instantiate_nsdmi_init): Mask out all ++ tsubst flags except for tf_warning_or_error. ++ ++2023-07-01 Patrick Palka ++ ++ Backported from master: ++ 2023-06-29 Patrick Palka ++ ++ PR c++/110463 ++ * cp-gimplify.cc (cp_fold) : Propagate ++ CONSTRUCTOR_MUTABLE_POISON. ++ ++2023-06-23 Jason Merrill ++ ++ * call.cc (maybe_init_list_as_array): Build a list. ++ ++2023-06-23 Jason Merrill ++ ++ PR c++/110102 ++ * call.cc (maybe_init_list_as_array): Check that the element type is ++ copyable. ++ ++2023-06-23 Jason Merrill ++ ++ DR 2735 ++ PR c++/109247 ++ * call.cc (sfk_copy_or_move): New. ++ (joust): Add tiebreaker for explicit conv and copy ctor. ++ ++2023-05-19 Patrick Palka ++ ++ Backported from master: ++ 2023-05-16 Patrick Palka ++ ++ PR c++/109871 ++ * call.cc (add_list_candidates): Check for invalid designated ++ initialization sooner and even for types that have a list ++ constructor. ++ ++2023-05-17 Jakub Jelinek ++ ++ Backported from master: ++ 2023-05-17 Jakub Jelinek ++ ++ PR c++/109868 ++ * init.cc (build_zero_init_1): Don't initialize zero-width bitfields. ++ For unions only initialize the first FIELD_DECL. ++ ++2023-05-16 Marek Polacek ++ ++ Backported from master: ++ 2023-05-16 Marek Polacek ++ ++ PR c++/109774 ++ * typeck.cc (check_return_expr): In a template, return only after ++ suppressing -Wdangling-reference. ++ ++2023-05-12 Patrick Palka ++ ++ Backported from master: ++ 2023-05-11 Patrick Palka ++ ++ PR c++/109745 ++ * typeck2.cc (poison_mutable_constructors): Define. ++ (store_init_value): Use it instead of setting ++ CONSTRUCTOR_MUTABLE_POISON directly. ++ ++2023-05-12 Patrick Palka ++ ++ Backported from master: ++ 2023-05-11 Patrick Palka ++ Jonathan Wakely ++ ++ PR c++/83258 ++ PR c++/80488 ++ PR c++/97700 ++ * pt.cc (convert_nontype_argument_function): Remove linkage ++ requirement for C++17 and later. ++ (invalid_tparm_referent_p) : Restrict ++ DECL_ARTIFICIAL rejection test to VAR_DECL. ++ ++2023-05-12 Patrick Palka ++ ++ Backported from master: ++ 2023-05-09 Patrick Palka ++ ++ PR c++/109761 ++ * parser.cc (cp_parser_class_specifier): Don't pass a class ++ context to noexcept_override_late_checks. ++ (noexcept_override_late_checks): Remove 'type' parameter ++ and use DECL_CONTEXT of 'fndecl' instead. ++ ++2023-05-12 Patrick Palka ++ ++ Backported from master: ++ 2023-05-07 Patrick Palka ++ ++ PR c++/109651 ++ * pt.cc (coerce_template_args_for_ttp): Mention we can hit the ++ current_template_parms fallback when level-lowering a bound ttp. ++ (tsubst_template_decl): Add lambda_tparms parameter. Prefer to ++ use lambda_tparms instead of substituting DECL_TEMPLATE_PARMS. ++ (tsubst_decl) : Pass NULL_TREE as lambda_tparms ++ to tsubst_template_decl. ++ (tsubst_lambda_expr): For a generic lambda, substitute ++ DECL_TEMPLATE_PARMS and set current_template_parms to it ++ before substituting the function type. Pass the substituted ++ DECL_TEMPLATE_PARMS as lambda_tparms to tsubst_template_decl. ++ +2023-05-09 Jakub Jelinek + + Backported from master: @@ -1066,6 +11388,97 @@ 2023-04-26 Release Manager * GCC 13.1.0 released. +--- a/src/gcc/cp/call.cc ++++ b/src/gcc/cp/call.cc +@@ -4128,6 +4128,14 @@ add_list_candidates (tree fns, tree first_arg, + if (CONSTRUCTOR_NELTS (init_list) == 0 + && TYPE_HAS_DEFAULT_CONSTRUCTOR (totype)) + ; ++ else if (CONSTRUCTOR_IS_DESIGNATED_INIT (init_list) ++ && !CP_AGGREGATE_TYPE_P (totype)) ++ { ++ if (complain & tf_error) ++ error ("designated initializers cannot be used with a " ++ "non-aggregate type %qT", totype); ++ return; ++ } + /* If the class has a list ctor, try passing the list as a single + argument first, but only consider list ctors. */ + else if (TYPE_HAS_LIST_CTOR (totype)) +@@ -4139,14 +4147,6 @@ add_list_candidates (tree fns, tree first_arg, + if (any_strictly_viable (*candidates)) + return; + } +- else if (CONSTRUCTOR_IS_DESIGNATED_INIT (init_list) +- && !CP_AGGREGATE_TYPE_P (totype)) +- { +- if (complain & tf_error) +- error ("designated initializers cannot be used with a " +- "non-aggregate type %qT", totype); +- return; +- } + + /* Expand the CONSTRUCTOR into a new argument vec. */ + vec *new_args; +@@ -4271,6 +4271,13 @@ maybe_init_list_as_array (tree elttype, tree init) + if (has_non_trivial_temporaries (first)) + return NULL_TREE; + ++ /* We can't do this if copying from the initializer_list would be ++ ill-formed. */ ++ tree copy_argtypes = build_tree_list ++ (NULL_TREE, cp_build_qualified_type (elttype, TYPE_QUAL_CONST)); ++ if (!is_xible (INIT_EXPR, elttype, copy_argtypes)) ++ return NULL_TREE; ++ + init_elttype = cp_build_qualified_type (init_elttype, TYPE_QUAL_CONST); + tree arr = build_array_of_n_type (init_elttype, CONSTRUCTOR_NELTS (init)); + return finish_compound_literal (arr, init, tf_none); +@@ -12608,6 +12615,17 @@ cand_parms_match (z_candidate *c1, z_candidate *c2) + return compparms (parms1, parms2); + } + ++/* True iff FN is a copy or move constructor or assignment operator. */ ++ ++static bool ++sfk_copy_or_move (tree fn) ++{ ++ if (TREE_CODE (fn) != FUNCTION_DECL) ++ return false; ++ special_function_kind sfk = special_function_p (fn); ++ return sfk >= sfk_copy_constructor && sfk <= sfk_move_assignment; ++} ++ + /* Compare two candidates for overloading as described in + [over.match.best]. Return values: + +@@ -12907,6 +12925,26 @@ joust (struct z_candidate *cand1, struct z_candidate *cand2, bool warn, + return winner; + } + ++ /* CWG2735 (PR109247): A copy/move ctor/op= for which its operand uses an ++ explicit conversion (due to list-initialization) is worse. */ ++ { ++ z_candidate *sp = nullptr; ++ if (sfk_copy_or_move (cand1->fn)) ++ sp = cand1; ++ if (sfk_copy_or_move (cand2->fn)) ++ sp = sp ? nullptr : cand2; ++ if (sp) ++ { ++ conversion *conv = sp->convs[!DECL_CONSTRUCTOR_P (sp->fn)]; ++ if (conv->user_conv_p) ++ for (; conv; conv = next_conversion (conv)) ++ if (conv->kind == ck_user ++ && DECL_P (conv->cand->fn) ++ && DECL_NONCONVERTING_P (conv->cand->fn)) ++ return (sp == cand1) ? -1 : 1; ++ } ++ } ++ + /* or, if not that, + F1 is a non-template function and F2 is a template function + specialization. */ --- a/src/gcc/cp/constexpr.cc +++ b/src/gcc/cp/constexpr.cc @@ -1440,8 +1440,6 @@ enum value_cat { @@ -1148,7 +11561,16 @@ static tree cp_fold_r (tree *stmt_p, int *walk_subtrees, void *data_) { -@@ -3267,6 +3267,16 @@ process_stmt_assume_attribute (tree std_attrs, tree statement, +@@ -3079,6 +3079,8 @@ cp_fold (tree x, fold_flags_t flags) + x = build_constructor (TREE_TYPE (x), nelts); + CONSTRUCTOR_PLACEHOLDER_BOUNDARY (x) + = CONSTRUCTOR_PLACEHOLDER_BOUNDARY (org_x); ++ CONSTRUCTOR_MUTABLE_POISON (x) ++ = CONSTRUCTOR_MUTABLE_POISON (org_x); + } + if (VECTOR_TYPE_P (TREE_TYPE (x))) + x = fold (x); +@@ -3267,6 +3269,16 @@ process_stmt_assume_attribute (tree std_attrs, tree statement, for (; attr; attr = lookup_attribute ("gnu", "assume", TREE_CHAIN (attr))) { tree args = TREE_VALUE (attr); @@ -1392,7 +11814,65 @@ } --- a/src/gcc/cp/init.cc +++ b/src/gcc/cp/init.cc -@@ -599,32 +599,14 @@ maybe_instantiate_nsdmi_init (tree member, tsubst_flags_t complain) +@@ -189,15 +189,21 @@ build_zero_init_1 (tree type, tree nelts, bool static_storage_p, + init = build_zero_cst (type); + else if (RECORD_OR_UNION_CODE_P (TREE_CODE (type))) + { +- tree field; ++ tree field, next; + vec *v = NULL; + + /* Iterate over the fields, building initializations. */ +- for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) ++ for (field = TYPE_FIELDS (type); field; field = next) + { ++ next = DECL_CHAIN (field); ++ + if (TREE_CODE (field) != FIELD_DECL) + continue; + ++ /* For unions, only the first field is initialized. */ ++ if (TREE_CODE (type) == UNION_TYPE) ++ next = NULL_TREE; ++ + if (TREE_TYPE (field) == error_mark_node) + continue; + +@@ -212,6 +218,11 @@ build_zero_init_1 (tree type, tree nelts, bool static_storage_p, + continue; + } + ++ /* Don't add zero width bitfields. */ ++ if (DECL_C_BIT_FIELD (field) ++ && integer_zerop (DECL_SIZE (field))) ++ continue; ++ + /* Note that for class types there will be FIELD_DECLs + corresponding to base classes as well. Thus, iterating + over TYPE_FIELDs will result in correct initialization of +@@ -230,10 +241,6 @@ build_zero_init_1 (tree type, tree nelts, bool static_storage_p, + if (value) + CONSTRUCTOR_APPEND_ELT(v, field, value); + } +- +- /* For unions, only the first field is initialized. */ +- if (TREE_CODE (type) == UNION_TYPE) +- break; + } + + /* Build a constructor to contain the initializations. */ +@@ -572,6 +579,10 @@ maybe_instantiate_nsdmi_init (tree member, tsubst_flags_t complain) + tree init = DECL_INITIAL (member); + if (init && DECL_LANG_SPECIFIC (member) && DECL_TEMPLATE_INFO (member)) + { ++ /* Clear any special tsubst flags; the result of NSDMI instantiation ++ should be independent of the substitution context. */ ++ complain &= tf_warning_or_error; ++ + init = DECL_INITIAL (DECL_TI_TEMPLATE (member)); + location_t expr_loc + = cp_expr_loc_or_loc (init, DECL_SOURCE_LOCATION (member)); +@@ -599,32 +610,14 @@ maybe_instantiate_nsdmi_init (tree member, tsubst_flags_t complain) bool pushed = false; tree ctx = type_context_for_name_lookup (member); @@ -1426,7 +11906,7 @@ inject_this_parameter (ctx, TYPE_UNQUALIFIED); start_lambda_scope (member); -@@ -641,15 +623,12 @@ maybe_instantiate_nsdmi_init (tree member, tsubst_flags_t complain) +@@ -641,15 +634,12 @@ maybe_instantiate_nsdmi_init (tree member, tsubst_flags_t complain) if (init != error_mark_node) hash_map_safe_put (nsdmi_inst, member, init); @@ -1500,9 +11980,147 @@ extern void push_using_decl_bindings (tree, tree); /* Lower level interface for modules. */ +--- a/src/gcc/cp/parser.cc ++++ b/src/gcc/cp/parser.cc +@@ -251,7 +251,7 @@ static cp_token_cache *cp_token_cache_new + static tree cp_parser_late_noexcept_specifier + (cp_parser *, tree); + static void noexcept_override_late_checks +- (tree, tree); ++ (tree); + + static void cp_parser_initial_pragma + (cp_token *); +@@ -26426,7 +26426,7 @@ cp_parser_class_specifier (cp_parser* parser) + /* The finish_struct call above performed various override checking, + but it skipped unparsed noexcept-specifier operands. Now that we + have resolved them, check again. */ +- noexcept_override_late_checks (type, decl); ++ noexcept_override_late_checks (decl); + + /* Remove any member-function parameters from the symbol table. */ + pop_injected_parms (); +@@ -28208,14 +28208,13 @@ cp_parser_late_noexcept_specifier (cp_parser *parser, tree default_arg) + } + + /* Perform late checking of overriding function with respect to their +- noexcept-specifiers. TYPE is the class and FNDECL is the function +- that potentially overrides some virtual function with the same +- signature. */ ++ noexcept-specifiers. FNDECL is the member function that potentially ++ overrides some virtual function with the same signature. */ + + static void +-noexcept_override_late_checks (tree type, tree fndecl) ++noexcept_override_late_checks (tree fndecl) + { +- tree binfo = TYPE_BINFO (type); ++ tree binfo = TYPE_BINFO (DECL_CONTEXT (fndecl)); + tree base_binfo; + + if (DECL_STATIC_FUNCTION_P (fndecl)) --- a/src/gcc/cp/pt.cc +++ b/src/gcc/cp/pt.cc -@@ -26813,20 +26813,7 @@ instantiate_body (tree pattern, tree args, tree d, bool nested_p) +@@ -6780,7 +6780,8 @@ convert_nontype_argument_function (tree type, tree expr, + } + + linkage = decl_linkage (fn_no_ptr); +- if (cxx_dialect >= cxx11 ? linkage == lk_none : linkage != lk_external) ++ if ((cxx_dialect < cxx11 && linkage != lk_external) ++ || (cxx_dialect < cxx17 && linkage == lk_none)) + { + if (complain & tf_error) + { +@@ -7178,7 +7179,7 @@ invalid_tparm_referent_p (tree type, tree expr, tsubst_flags_t complain) + * a string literal (5.13.5), + * the result of a typeid expression (8.2.8), or + * a predefined __func__ variable (11.4.1). */ +- else if (DECL_ARTIFICIAL (decl)) ++ else if (VAR_P (decl) && DECL_ARTIFICIAL (decl)) + { + if (complain & tf_error) + error ("the address of %qD is not a valid template argument", +@@ -7876,7 +7877,8 @@ coerce_template_args_for_ttp (tree templ, tree arglist, + else if (current_template_parms) + { + /* This is an argument of the current template, so we haven't set +- DECL_CONTEXT yet. */ ++ DECL_CONTEXT yet. We can also get here when level-lowering a ++ bound ttp. */ + tree relevant_template_parms; + + /* Parameter levels that are greater than the level of the given +@@ -14630,7 +14632,7 @@ tsubst_function_decl (tree t, tree args, tsubst_flags_t complain, + + static tree + tsubst_template_decl (tree t, tree args, tsubst_flags_t complain, +- tree lambda_fntype) ++ tree lambda_fntype, tree lambda_tparms) + { + /* We can get here when processing a member function template, + member class template, or template template parameter. */ +@@ -14720,8 +14722,10 @@ tsubst_template_decl (tree t, tree args, tsubst_flags_t complain, + auto tparm_guard = make_temp_override (current_template_parms); + DECL_TEMPLATE_PARMS (r) + = current_template_parms +- = tsubst_template_parms (DECL_TEMPLATE_PARMS (t), args, +- complain); ++ = (lambda_tparms ++ ? lambda_tparms ++ : tsubst_template_parms (DECL_TEMPLATE_PARMS (t), args, ++ complain)); + + bool class_p = false; + tree inner = decl; +@@ -14889,7 +14893,9 @@ tsubst_decl (tree t, tree args, tsubst_flags_t complain) + switch (TREE_CODE (t)) + { + case TEMPLATE_DECL: +- r = tsubst_template_decl (t, args, complain, /*lambda*/NULL_TREE); ++ r = tsubst_template_decl (t, args, complain, ++ /*lambda_fntype=*/NULL_TREE, ++ /*lambda_tparms=*/NULL_TREE); + break; + + case FUNCTION_DECL: +@@ -20132,12 +20138,24 @@ tsubst_lambda_expr (tree t, tree args, tsubst_flags_t complain, tree in_decl) + ? DECL_TI_TEMPLATE (oldfn) + : NULL_TREE); + ++ tree tparms = NULL_TREE; ++ if (oldtmpl) ++ tparms = tsubst_template_parms (DECL_TEMPLATE_PARMS (oldtmpl), args, complain); ++ + tree fntype = static_fn_type (oldfn); ++ ++ tree saved_ctp = current_template_parms; + if (oldtmpl) +- ++processing_template_decl; ++ { ++ ++processing_template_decl; ++ current_template_parms = tparms; ++ } + fntype = tsubst (fntype, args, complain, in_decl); + if (oldtmpl) +- --processing_template_decl; ++ { ++ current_template_parms = saved_ctp; ++ --processing_template_decl; ++ } + + if (fntype == error_mark_node) + r = error_mark_node; +@@ -20153,7 +20171,8 @@ tsubst_lambda_expr (tree t, tree args, tsubst_flags_t complain, tree in_decl) + type_memfn_quals (fntype), + type_memfn_rqual (fntype)); + tree inst = (oldtmpl +- ? tsubst_template_decl (oldtmpl, args, complain, fntype) ++ ? tsubst_template_decl (oldtmpl, args, complain, ++ fntype, tparms) + : tsubst_function_decl (oldfn, args, complain, fntype)); + if (inst == error_mark_node) + { +@@ -26813,20 +26832,7 @@ instantiate_body (tree pattern, tree args, tree d, bool nested_p) if (current_function_decl) save_omp_privatization_clauses (omp_privatization_save); @@ -1524,7 +12142,7 @@ mark_template_arguments_used (pattern, args); -@@ -26940,10 +26927,7 @@ instantiate_body (tree pattern, tree args, tree d, bool nested_p) +@@ -26940,10 +26946,7 @@ instantiate_body (tree pattern, tree args, tree d, bool nested_p) if (!nested_p) TI_PENDING_TEMPLATE_FLAG (DECL_TEMPLATE_INFO (d)) = 0; @@ -1536,9 +12154,1759 @@ if (current_function_decl) restore_omp_privatization_clauses (omp_privatization_save); +--- a/src/gcc/cp/typeck.cc ++++ b/src/gcc/cp/typeck.cc +@@ -11236,9 +11236,6 @@ check_return_expr (tree retval, bool *no_warning) + build_zero_cst (TREE_TYPE (retval))); + } + +- if (processing_template_decl) +- return saved_retval; +- + /* A naive attempt to reduce the number of -Wdangling-reference false + positives: if we know that this function can return a variable with + static storage duration rather than one of its parameters, suppress +@@ -11250,6 +11247,9 @@ check_return_expr (tree retval, bool *no_warning) + && TREE_STATIC (bare_retval)) + suppress_warning (current_function_decl, OPT_Wdangling_reference); + ++ if (processing_template_decl) ++ return saved_retval; ++ + /* Actually copy the value returned into the appropriate location. */ + if (retval && retval != result) + { +--- a/src/gcc/cp/typeck2.cc ++++ b/src/gcc/cp/typeck2.cc +@@ -776,6 +776,27 @@ split_nonconstant_init (tree dest, tree init) + return code; + } + ++/* T is the initializer of a constexpr variable. Set CONSTRUCTOR_MUTABLE_POISON ++ for any CONSTRUCTOR within T that contains (directly or indirectly) a mutable ++ member, thereby poisoning it so it can't be copied to another a constexpr ++ variable or read during constexpr evaluation. */ ++ ++static void ++poison_mutable_constructors (tree t) ++{ ++ if (TREE_CODE (t) != CONSTRUCTOR) ++ return; ++ ++ if (cp_has_mutable_p (TREE_TYPE (t))) ++ { ++ CONSTRUCTOR_MUTABLE_POISON (t) = true; ++ ++ if (vec *elts = CONSTRUCTOR_ELTS (t)) ++ for (const constructor_elt &ce : *elts) ++ poison_mutable_constructors (ce.value); ++ } ++} ++ + /* Perform appropriate conversions on the initial value of a variable, + store it in the declaration DECL, + and print any error messages that are appropriate. +@@ -864,10 +885,7 @@ store_init_value (tree decl, tree init, vec** cleanups, int flags) + else + value = fold_non_dependent_init (value, tf_warning_or_error, + /*manifestly_const_eval=*/true, decl); +- if (TREE_CODE (value) == CONSTRUCTOR && cp_has_mutable_p (type)) +- /* Poison this CONSTRUCTOR so it can't be copied to another +- constexpr variable. */ +- CONSTRUCTOR_MUTABLE_POISON (value) = true; ++ poison_mutable_constructors (value); + const_init = (reduced_constant_expression_p (value) + || error_operand_p (value)); + DECL_INITIALIZED_BY_CONSTANT_EXPRESSION_P (decl) = const_init; +--- a/src/gcc/d/ChangeLog ++++ b/src/gcc/d/ChangeLog +@@ -1,3 +1,94 @@ ++2023-07-07 Iain Buclaw ++ ++ Backported from master: ++ 2023-07-07 Iain Buclaw ++ ++ PR d/108842 ++ * decl.cc (DeclVisitor::visit (VarDeclaration *)): Only emit scalar ++ manifest constants. ++ (get_symbol_decl): Don't generate CONST_DECL for non-scalar manifest ++ constants. ++ * imports.cc (ImportVisitor::visit (VarDeclaration *)): New method. ++ ++2023-07-02 Iain Buclaw ++ ++ Backported from master: ++ 2023-07-02 Iain Buclaw ++ ++ PR d/110516 ++ * intrinsics.cc (expand_volatile_load): Set TREE_SIDE_EFFECTS on the ++ expanded expression. ++ (expand_volatile_store): Likewise. ++ ++2023-07-01 Iain Buclaw ++ ++ Backported from master: ++ 2023-07-01 Iain Buclaw ++ ++ PR d/110514 ++ * decl.cc (get_symbol_decl): Set TREE_READONLY on certain kinds of ++ const and immutable variables. ++ * expr.cc (ExprVisitor::visit (ArrayLiteralExp *)): Set TREE_READONLY ++ on immutable dynamic array literals. ++ ++2023-07-01 Iain Buclaw ++ ++ Backported from master: ++ 2023-07-01 Iain Buclaw ++ ++ PR d/110471 ++ * d-builtins.cc (d_init_versions): Predefine D_ModuleInfo, ++ D_Exceptions, and D_TypeInfo only if feature is enabled. ++ * lang.opt: Add -fexceptions. ++ ++2023-06-28 Iain Buclaw ++ ++ Backported from master: ++ 2023-06-28 Iain Buclaw ++ ++ PR d/106977 ++ PR target/110406 ++ * types.cc (finish_aggregate_mode): New function. ++ (finish_incomplete_fields): Call finish_aggregate_mode. ++ (finish_aggregate_type): Replace call to compute_record_mode with ++ finish_aggregate_mode. ++ ++2023-06-26 Iain Buclaw ++ ++ Backported from master: ++ 2023-06-26 Iain Buclaw ++ ++ PR d/110359 ++ * d-convert.cc (convert_for_rvalue): Only apply the @safe boolean ++ conversion to boolean fields of a union. ++ (convert_for_condition): Call convert_for_rvalue in the default case. ++ ++2023-06-26 Iain Buclaw ++ ++ PR d/110113 ++ * dmd/escape.d (checkMutableArguments): Always allocate new buffer for ++ computing escapeBy. ++ ++2023-06-26 Iain Buclaw ++ ++ Backported from master: ++ 2023-06-25 Iain Buclaw ++ ++ * dmd/MERGE: Merge upstream dmd a45f4e9f43. ++ * dmd/VERSION: Bump version to v2.103.1. ++ ++2023-06-05 Iain Buclaw ++ ++ Backported from master: ++ 2023-06-05 Iain Buclaw ++ ++ * gdc.texi (Warnings): Document -Wextra and -Wmismatched-special-enum. ++ * implement-d.texi (Special Enums): Add reference to warning option ++ -Wmismatched-special-enum. ++ * lang.opt: Add -Wextra and -Wmismatched-special-enum. ++ * types.cc (TypeVisitor::visit (TypeEnum *)): Warn when declared ++ special enum size mismatches its intrinsic type. ++ + 2023-04-26 Release Manager + + * GCC 13.1.0 released. +--- a/src/gcc/d/d-builtins.cc ++++ b/src/gcc/d/d-builtins.cc +@@ -500,9 +500,12 @@ d_init_versions (void) + VersionCondition::addPredefinedGlobalIdent ("D_BetterC"); + else + { +- VersionCondition::addPredefinedGlobalIdent ("D_ModuleInfo"); +- VersionCondition::addPredefinedGlobalIdent ("D_Exceptions"); +- VersionCondition::addPredefinedGlobalIdent ("D_TypeInfo"); ++ if (global.params.useModuleInfo) ++ VersionCondition::addPredefinedGlobalIdent ("D_ModuleInfo"); ++ if (global.params.useExceptions) ++ VersionCondition::addPredefinedGlobalIdent ("D_Exceptions"); ++ if (global.params.useTypeInfo) ++ VersionCondition::addPredefinedGlobalIdent ("D_TypeInfo"); + } + + if (optimize) +--- a/src/gcc/d/d-convert.cc ++++ b/src/gcc/d/d-convert.cc +@@ -620,7 +620,7 @@ convert_expr (tree exp, Type *etype, Type *totype) + return result ? result : convert (build_ctype (totype), exp); + } + +-/* Return a TREE represenwation of EXPR, whose type has been converted from ++/* Return a TREE representation of EXPR, whose type has been converted from + * ETYPE to TOTYPE, and is being used in an rvalue context. */ + + tree +@@ -635,20 +635,27 @@ convert_for_rvalue (tree expr, Type *etype, Type *totype) + { + /* If casting from bool, the result is either 0 or 1, any other value + violates @safe code, so enforce that it is never invalid. */ +- if (CONSTANT_CLASS_P (expr)) +- result = d_truthvalue_conversion (expr); +- else ++ for (tree ref = expr; TREE_CODE (ref) == COMPONENT_REF; ++ ref = TREE_OPERAND (ref, 0)) + { +- /* Reinterpret the boolean as an integer and test the first bit. +- The generated code should end up being equivalent to: ++ /* If the expression is a field that's part of a union, reinterpret ++ the boolean as an integer and test the first bit. The generated ++ code should end up being equivalent to: + *cast(ubyte *)&expr & 1; */ +- machine_mode bool_mode = TYPE_MODE (TREE_TYPE (expr)); +- tree mtype = lang_hooks.types.type_for_mode (bool_mode, 1); +- result = fold_build2 (BIT_AND_EXPR, mtype, +- build_vconvert (mtype, expr), +- build_one_cst (mtype)); ++ if (TREE_CODE (TREE_TYPE (TREE_OPERAND (ref, 0))) == UNION_TYPE) ++ { ++ machine_mode bool_mode = TYPE_MODE (TREE_TYPE (expr)); ++ tree mtype = lang_hooks.types.type_for_mode (bool_mode, 1); ++ result = fold_build2 (BIT_AND_EXPR, mtype, ++ build_vconvert (mtype, expr), ++ build_one_cst (mtype)); ++ break; ++ } + } + ++ if (result == NULL_TREE) ++ result = d_truthvalue_conversion (expr); ++ + result = convert (build_ctype (tbtype), result); + } + +@@ -845,7 +852,7 @@ convert_for_condition (tree expr, Type *type) + break; + + default: +- result = expr; ++ result = convert_for_rvalue (expr, type, type); + break; + } + +--- a/src/gcc/d/decl.cc ++++ b/src/gcc/d/decl.cc +@@ -782,7 +782,7 @@ public: + { + /* Do not store variables we cannot take the address of, + but keep the values for purposes of debugging. */ +- if (!d->type->isscalar ()) ++ if (d->type->isscalar () && !d->type->hasPointers ()) + { + tree decl = get_symbol_decl (d); + d_pushdecl (decl); +@@ -1212,6 +1212,20 @@ get_symbol_decl (Declaration *decl) + return decl->csym; + } + ++ if (VarDeclaration *vd = decl->isVarDeclaration ()) ++ { ++ /* CONST_DECL was initially intended for enumerals and may be used for ++ scalars in general, but not for aggregates. Here a non-constant ++ value is generated anyway so as its value can be used. */ ++ if (!vd->canTakeAddressOf () && !vd->type->isscalar ()) ++ { ++ gcc_assert (vd->_init && !vd->_init->isVoidInitializer ()); ++ Expression *ie = initializerToExpression (vd->_init); ++ decl->csym = build_expr (ie, false); ++ return decl->csym; ++ } ++ } ++ + /* Build the tree for the symbol. */ + FuncDeclaration *fd = decl->isFuncDeclaration (); + if (fd) +@@ -1259,24 +1273,30 @@ get_symbol_decl (Declaration *decl) + if (vd->storage_class & STCextern) + DECL_EXTERNAL (decl->csym) = 1; + +- /* CONST_DECL was initially intended for enumerals and may be used for +- scalars in general, but not for aggregates. Here a non-constant +- value is generated anyway so as the CONST_DECL only serves as a +- placeholder for the value, however the DECL itself should never be +- referenced in any generated code, or passed to the back-end. */ +- if (vd->storage_class & STCmanifest) ++ if (!vd->canTakeAddressOf ()) + { + /* Cannot make an expression out of a void initializer. */ +- if (vd->_init && !vd->_init->isVoidInitializer ()) +- { +- Expression *ie = initializerToExpression (vd->_init); ++ gcc_assert (vd->_init && !vd->_init->isVoidInitializer ()); ++ /* Non-scalar manifest constants have already been dealt with. */ ++ gcc_assert (vd->type->isscalar ()); + +- if (!vd->type->isscalar ()) +- DECL_INITIAL (decl->csym) = build_expr (ie, false); +- else +- DECL_INITIAL (decl->csym) = build_expr (ie, true); +- } ++ Expression *ie = initializerToExpression (vd->_init); ++ DECL_INITIAL (decl->csym) = build_expr (ie, true); + } ++ ++ /* [type-qualifiers/const-and-immutable] ++ ++ `immutable` applies to data that cannot change. Immutable data values, ++ once constructed, remain the same for the duration of the program's ++ execution. */ ++ if (vd->isImmutable () && !vd->setInCtorOnly ()) ++ TREE_READONLY (decl->csym) = 1; ++ ++ /* `const` applies to data that cannot be changed by the const reference ++ to that data. It may, however, be changed by another reference to that ++ same data. */ ++ if (vd->isConst () && !vd->isDataseg ()) ++ TREE_READONLY (decl->csym) = 1; + } + + /* Set the declaration mangled identifier if static. */ +--- a/src/gcc/d/dmd/MERGE ++++ b/src/gcc/d/dmd/MERGE +@@ -1,4 +1,4 @@ +-5f7552bb2829b75d5e36cc767a476e1ab35147b7 ++a45f4e9f43e9fdbf0b666175e5e66b1ce4f561f6 + + The first line of this file holds the git revision number of the last + merge done from the dlang/dmd repository. +--- a/src/gcc/d/dmd/VERSION ++++ b/src/gcc/d/dmd/VERSION +@@ -1 +1 @@ +-v2.103.0-rc.1 ++v2.103.1 +--- a/src/gcc/d/dmd/aggregate.h ++++ b/src/gcc/d/dmd/aggregate.h +@@ -108,8 +108,8 @@ public: + Expression *getRTInfo; // pointer to GC info generated by object.RTInfo(this) + + Visibility visibility; +- bool noDefaultCtor; // no default construction +- bool disableNew; // disallow allocations using `new` ++ d_bool noDefaultCtor; // no default construction ++ d_bool disableNew; // disallow allocations using `new` + Sizeok sizeok; // set when structsize contains valid data + + virtual Scope *newScope(Scope *sc); +@@ -269,10 +269,10 @@ public: + // their own vtbl[] + + TypeInfoClassDeclaration *vclassinfo; // the ClassInfo object for this ClassDeclaration +- bool com; // true if this is a COM class (meaning it derives from IUnknown) +- bool stack; // true if this is a scope class ++ d_bool com; // true if this is a COM class (meaning it derives from IUnknown) ++ d_bool stack; // true if this is a scope class + int cppDtorVtblIndex; // slot reserved for the virtual destructor [extern(C++)] +- bool inuse; // to prevent recursive attempts ++ d_bool inuse; // to prevent recursive attempts + + ThreeState isabstract; // if abstract class + Baseok baseok; // set the progress of base classes resolving +--- a/src/gcc/d/dmd/attrib.h ++++ b/src/gcc/d/dmd/attrib.h +@@ -132,7 +132,7 @@ public: + class AnonDeclaration final : public AttribDeclaration + { + public: +- bool isunion; ++ d_bool isunion; + int sem; // 1 if successful semantic() + unsigned anonoffset; // offset of anonymous struct + unsigned anonstructsize; // size of anonymous struct +@@ -175,8 +175,8 @@ class StaticIfDeclaration final : public ConditionalDeclaration + { + public: + ScopeDsymbol *scopesym; +- bool addisdone; +- bool onStack; ++ d_bool addisdone; ++ d_bool onStack; + + StaticIfDeclaration *syntaxCopy(Dsymbol *s) override; + Dsymbols *include(Scope *sc) override; +@@ -193,8 +193,8 @@ class StaticForeachDeclaration final : public AttribDeclaration + public: + StaticForeach *sfe; + ScopeDsymbol *scopesym; +- bool onStack; +- bool cached; ++ d_bool onStack; ++ d_bool cached; + Dsymbols *cache; + + StaticForeachDeclaration *syntaxCopy(Dsymbol *s) override; +@@ -227,7 +227,7 @@ public: + Expressions *exps; + + ScopeDsymbol *scopesym; +- bool compiled; ++ d_bool compiled; + + CompileDeclaration *syntaxCopy(Dsymbol *s) override; + void addMember(Scope *sc, ScopeDsymbol *sds) override; +--- a/src/gcc/d/dmd/common/outbuffer.h ++++ b/src/gcc/d/dmd/common/outbuffer.h +@@ -21,11 +21,11 @@ struct OutBuffer + private: + DArray data; + d_size_t offset; +- bool notlinehead; ++ d_bool notlinehead; + void *fileMapping; // pointer to a file mapping object not used on the C++ side + public: +- bool doindent; +- bool spaces; ++ d_bool doindent; ++ d_bool spaces; + int level; + + OutBuffer() +--- a/src/gcc/d/dmd/cond.d ++++ b/src/gcc/d/dmd/cond.d +@@ -935,9 +935,6 @@ extern (C++) final class StaticIfCondition : Condition + import dmd.staticcond; + bool errors; + +- if (!exp) +- return errorReturn(); +- + bool result = evalStaticCondition(sc, exp, exp, errors); + + // Prevent repeated condition evaluation. +--- a/src/gcc/d/dmd/cond.h ++++ b/src/gcc/d/dmd/cond.h +@@ -52,7 +52,7 @@ public: + ForeachStatement *aggrfe; + ForeachRangeStatement *rangefe; + +- bool needExpansion; ++ d_bool needExpansion; + + StaticForeach *syntaxCopy(); + }; +--- a/src/gcc/d/dmd/cppmangle.d ++++ b/src/gcc/d/dmd/cppmangle.d +@@ -213,6 +213,11 @@ private final class CppMangleVisitor : Visitor + { + auto tf = cast(TypeFunction)this.context.res.asFuncDecl().type; + Type rt = preSemantic.nextOf(); ++ // https://issues.dlang.org/show_bug.cgi?id=22739 ++ // auto return type means that rt is null. ++ // if so, just pick up the type from the instance ++ if (!rt) ++ rt = tf.nextOf(); + if (tf.isref) + rt = rt.referenceTo(); + auto prev = this.context.push(tf.nextOf()); +@@ -560,7 +565,11 @@ private final class CppMangleVisitor : Visitor + foreach (j; i .. (*ti.tiargs).length) + { + Type t = isType((*ti.tiargs)[j]); +- assert(t); ++ if (t is null) ++ { ++ ti.error("internal compiler error: C++ `%s` template value parameter is not supported", (*ti.tiargs)[j].toChars()); ++ fatal(); ++ } + t.accept(this); + } + +--- a/src/gcc/d/dmd/declaration.h ++++ b/src/gcc/d/dmd/declaration.h +@@ -167,8 +167,8 @@ class TupleDeclaration final : public Declaration + public: + Objects *objects; + TypeTuple *tupletype; // !=NULL if this is a type tuple +- bool isexp; // true: expression tuple +- bool building; // it's growing in AliasAssign semantic ++ d_bool isexp; // true: expression tuple ++ d_bool building; // it's growing in AliasAssign semantic + + TupleDeclaration *syntaxCopy(Dsymbol *) override; + const char *kind() const override; +@@ -607,7 +607,7 @@ public: + + // set if someone took the address of this function + int tookAddressOf; +- bool requiresClosure; // this function needs a closure ++ d_bool requiresClosure; // this function needs a closure + + // local variables in this function which are referenced by nested functions + VarDeclarations closureVars; +@@ -742,7 +742,7 @@ class FuncAliasDeclaration final : public FuncDeclaration + { + public: + FuncDeclaration *funcalias; +- bool hasOverloads; ++ d_bool hasOverloads; + + FuncAliasDeclaration *isFuncAliasDeclaration() override { return this; } + const char *kind() const override; +@@ -758,7 +758,7 @@ public: + Type *treq; // target of return type inference + + // backend +- bool deferToObj; ++ d_bool deferToObj; + + FuncLiteralDeclaration *syntaxCopy(Dsymbol *) override; + bool isNested() const override; +@@ -778,7 +778,7 @@ public: + class CtorDeclaration final : public FuncDeclaration + { + public: +- bool isCpCtor; ++ d_bool isCpCtor; + CtorDeclaration *syntaxCopy(Dsymbol *) override; + const char *kind() const override; + const char *toChars() const override; +--- a/src/gcc/d/dmd/dsymbol.h ++++ b/src/gcc/d/dmd/dsymbol.h +@@ -172,7 +172,7 @@ struct FieldState + unsigned fieldAlign; + unsigned bitOffset; + +- bool inFlight; ++ d_bool inFlight; + }; + + struct DsymbolAttributes; +@@ -189,7 +189,7 @@ public: + private: + DsymbolAttributes* atts; + public: +- bool errors; // this symbol failed to pass semantic() ++ d_bool errors; // this symbol failed to pass semantic() + PASS semanticRun; + unsigned short localNum; // perturb mangled name to avoid collisions with those in FuncDeclaration.localsymtab + static Dsymbol *create(Identifier *); +--- a/src/gcc/d/dmd/dsymbolsem.d ++++ b/src/gcc/d/dmd/dsymbolsem.d +@@ -1383,10 +1383,14 @@ private extern(C++) final class DsymbolSemanticVisitor : Visitor + imp.semanticRun = PASS.semantic; + + // Load if not already done so +- bool loadErrored = false; + if (!imp.mod) + { +- loadErrored = imp.load(sc); ++ // https://issues.dlang.org/show_bug.cgi?id=22857 ++ // if parser errors occur when loading a module ++ // we should just stop compilation ++ if (imp.load(sc)) ++ return; ++ + if (imp.mod) + { + imp.mod.importAll(null); +@@ -1427,10 +1431,7 @@ private extern(C++) final class DsymbolSemanticVisitor : Visitor + imp.addPackageAccess(scopesym); + } + +- if (!loadErrored) +- { +- imp.mod.dsymbolSemantic(null); +- } ++ imp.mod.dsymbolSemantic(null); + + if (imp.mod.needmoduleinfo) + { +--- a/src/gcc/d/dmd/escape.d ++++ b/src/gcc/d/dmd/escape.d +@@ -93,22 +93,7 @@ bool checkMutableArguments(Scope* sc, FuncDeclaration fd, TypeFunction tf, + bool isMutable; // true if reference to mutable + } + +- /* Store escapeBy as static data escapeByStorage so we can keep reusing the same +- * arrays rather than reallocating them. +- */ +- __gshared EscapeBy[] escapeByStorage; +- auto escapeBy = escapeByStorage; +- if (escapeBy.length < len) +- { +- auto newPtr = cast(EscapeBy*)mem.xrealloc(escapeBy.ptr, len * EscapeBy.sizeof); +- // Clear the new section +- memset(newPtr + escapeBy.length, 0, (len - escapeBy.length) * EscapeBy.sizeof); +- escapeBy = newPtr[0 .. len]; +- escapeByStorage = escapeBy; +- } +- else +- escapeBy = escapeBy[0 .. len]; +- ++ auto escapeBy = new EscapeBy[len]; + const paramLength = tf.parameterList.length; + + // Fill in escapeBy[] with arguments[], ethis, and outerVars[] +@@ -228,13 +213,6 @@ bool checkMutableArguments(Scope* sc, FuncDeclaration fd, TypeFunction tf, + escape(i, eb, false); + } + +- /* Reset the arrays in escapeBy[] so we can reuse them next time through +- */ +- foreach (ref eb; escapeBy) +- { +- eb.er.reset(); +- } +- + return errors; + } + +--- a/src/gcc/d/dmd/expression.h ++++ b/src/gcc/d/dmd/expression.h +@@ -81,7 +81,7 @@ class Expression : public ASTNode + public: + EXP op; // to minimize use of dynamic_cast + unsigned char size; // # of bytes in Expression so we can copy() it +- bool parens; // if this is a parenthesized expression ++ d_bool parens; // if this is a parenthesized expression + Type *type; // !=NULL means that semantic() has been run + Loc loc; // file location + +@@ -331,7 +331,7 @@ class DsymbolExp final : public Expression + { + public: + Dsymbol *s; +- bool hasOverloads; ++ d_bool hasOverloads; + + DsymbolExp *syntaxCopy() override; + bool isLvalue() override; +@@ -422,7 +422,7 @@ public: + Expression *basis; + Expressions *elements; + OwnedBy ownedByCtfe; +- bool onstack; ++ d_bool onstack; + + static ArrayLiteralExp *create(const Loc &loc, Expressions *elements); + static void emplace(UnionExp *pue, const Loc &loc, Expressions *elements); +@@ -476,8 +476,8 @@ public: + */ + int stageflags; + +- bool useStaticInit; // if this is true, use the StructDeclaration's init symbol +- bool isOriginal; // used when moving instances to indicate `this is this.origin` ++ d_bool useStaticInit; // if this is true, use the StructDeclaration's init symbol ++ d_bool isOriginal; // used when moving instances to indicate `this is this.origin` + OwnedBy ownedByCtfe; + + static StructLiteralExp *create(const Loc &loc, StructDeclaration *sd, void *elements, Type *stype = NULL); +@@ -537,8 +537,8 @@ public: + Expression *argprefix; // expression to be evaluated just before arguments[] + + CtorDeclaration *member; // constructor function +- bool onstack; // allocate on stack +- bool thrownew; // this NewExp is the expression of a ThrowStatement ++ d_bool onstack; // allocate on stack ++ d_bool thrownew; // this NewExp is the expression of a ThrowStatement + + Expression *lowering; // lowered druntime hook: `_d_newclass` + +@@ -566,7 +566,7 @@ class SymbolExp : public Expression + public: + Declaration *var; + Dsymbol *originalScope; +- bool hasOverloads; ++ d_bool hasOverloads; + + void accept(Visitor *v) override { v->visit(this); } + }; +@@ -588,7 +588,7 @@ public: + class VarExp final : public SymbolExp + { + public: +- bool delegateWasExtracted; ++ d_bool delegateWasExtracted; + static VarExp *create(const Loc &loc, Declaration *var, bool hasOverloads = true); + bool equals(const RootObject * const o) const override; + bool isLvalue() override; +@@ -764,9 +764,9 @@ class DotIdExp final : public UnaExp + { + public: + Identifier *ident; +- bool noderef; // true if the result of the expression will never be dereferenced +- bool wantsym; // do not replace Symbol with its initializer during semantic() +- bool arrow; // ImportC: if -> instead of . ++ d_bool noderef; // true if the result of the expression will never be dereferenced ++ d_bool wantsym; // do not replace Symbol with its initializer during semantic() ++ d_bool arrow; // ImportC: if -> instead of . + + static DotIdExp *create(const Loc &loc, Expression *e, Identifier *ident); + void accept(Visitor *v) override { v->visit(this); } +@@ -786,7 +786,7 @@ class DotVarExp final : public UnaExp + { + public: + Declaration *var; +- bool hasOverloads; ++ d_bool hasOverloads; + + bool isLvalue() override; + Expression *toLvalue(Scope *sc, Expression *e) override; +@@ -810,7 +810,7 @@ class DelegateExp final : public UnaExp + { + public: + FuncDeclaration *func; +- bool hasOverloads; ++ d_bool hasOverloads; + VarDeclaration *vthis2; // container for multi-context + + +@@ -831,9 +831,9 @@ public: + Expressions *arguments; // function arguments + Identifiers *names; + FuncDeclaration *f; // symbol to call +- bool directcall; // true if a virtual call is devirtualized +- bool inDebugStatement; // true if this was in a debug statement +- bool ignoreAttributes; // don't enforce attributes (e.g. call @gc function in @nogc code) ++ d_bool directcall; // true if a virtual call is devirtualized ++ d_bool inDebugStatement; // true if this was in a debug statement ++ d_bool ignoreAttributes; // don't enforce attributes (e.g. call @gc function in @nogc code) + VarDeclaration *vthis2; // container for multi-context + + static CallExp *create(const Loc &loc, Expression *e, Expressions *exps); +@@ -892,7 +892,7 @@ public: + class DeleteExp final : public UnaExp + { + public: +- bool isRAII; ++ d_bool isRAII; + void accept(Visitor *v) override { v->visit(this); } + }; + +@@ -937,9 +937,9 @@ public: + Expression *upr; // NULL if implicit 0 + Expression *lwr; // NULL if implicit [length - 1] + VarDeclaration *lengthVar; +- bool upperIsInBounds; // true if upr <= e1.length +- bool lowerIsLessThanUpper; // true if lwr <= upr +- bool arrayop; // an array operation, rather than a slice ++ d_bool upperIsInBounds; // true if upr <= e1.length ++ d_bool lowerIsLessThanUpper; // true if lwr <= upr ++ d_bool arrayop; // an array operation, rather than a slice + + SliceExp *syntaxCopy() override; + bool isLvalue() override; +@@ -1011,8 +1011,8 @@ public: + class CommaExp final : public BinExp + { + public: +- bool isGenerated; +- bool allowCommaExp; ++ d_bool isGenerated; ++ d_bool allowCommaExp; + bool isLvalue() override; + Expression *toLvalue(Scope *sc, Expression *e) override; + Expression *modifiableLvalue(Scope *sc, Expression *e) override; +@@ -1025,8 +1025,8 @@ class IndexExp final : public BinExp + { + public: + VarDeclaration *lengthVar; +- bool modifiable; +- bool indexIsInBounds; // true if 0 <= e2 && e2 <= e1.length - 1 ++ d_bool modifiable; ++ d_bool indexIsInBounds; // true if 0 <= e2 && e2 <= e1.length - 1 + + IndexExp *syntaxCopy() override; + bool isLvalue() override; +--- a/src/gcc/d/dmd/expressionsem.d ++++ b/src/gcc/d/dmd/expressionsem.d +@@ -12158,6 +12158,9 @@ private extern (C++) final class ExpressionSemanticVisitor : Visitor + + if (!needsArrayLowering) + { ++ // https://issues.dlang.org/show_bug.cgi?id=23783 ++ if (exp.e1.checkSharedAccess(sc) || exp.e2.checkSharedAccess(sc)) ++ return setError(); + if (auto e = typeCombine(exp, sc)) + { + result = e; +@@ -13372,6 +13375,12 @@ bool checkSharedAccess(Expression e, Scope* sc, bool returnRef = false) + + bool visitVar(VarExp e) + { ++ // https://issues.dlang.org/show_bug.cgi?id=20908 ++ // direct access to init symbols is ok as they ++ // cannot be modified. ++ if (e.var.isSymbolDeclaration()) ++ return false; ++ + // https://issues.dlang.org/show_bug.cgi?id=22626 + // Synchronized functions don't need to use core.atomic + // when accessing `this`. +@@ -13409,9 +13418,16 @@ bool checkSharedAccess(Expression e, Scope* sc, bool returnRef = false) + //printf("dotvarexp = %s\n", e.toChars()); + if (e.type.isShared()) + { +- // / https://issues.dlang.org/show_bug.cgi?id=22626 +- if (e.e1.isThisExp() && sc.func && sc.func.isSynchronized()) +- return false; ++ if (e.e1.isThisExp()) ++ { ++ // https://issues.dlang.org/show_bug.cgi?id=22626 ++ if (sc.func && sc.func.isSynchronized()) ++ return false; ++ ++ // https://issues.dlang.org/show_bug.cgi?id=23790 ++ if (e.e1.type.isTypeStruct()) ++ return false; ++ } + + auto fd = e.var.isFuncDeclaration(); + const sharedFunc = fd && fd.type.isShared; +--- a/src/gcc/d/dmd/globals.h ++++ b/src/gcc/d/dmd/globals.h +@@ -85,8 +85,8 @@ enum class FeatureState : signed char + struct Output + { + /// Configuration for the compiler generator +- bool doOutput; // Output is enabled +- bool fullOutput; // Generate comments for hidden declarations (for -HC), ++ d_bool doOutput; // Output is enabled ++ d_bool fullOutput; // Generate comments for hidden declarations (for -HC), + // and don't strip the bodies of plain (non-template) functions (for -H) + DString dir; // write to directory 'dir' + DString name; // write to file 'name' +@@ -99,71 +99,71 @@ struct Output + // Put command line switches in here + struct Param + { +- bool obj; // write object file +- bool multiobj; // break one object file into multiple ones +- bool trace; // insert profiling hooks +- bool tracegc; // instrument calls to 'new' +- bool verbose; // verbose compile +- bool vcg_ast; // write-out codegen-ast +- bool showColumns; // print character (column) numbers in diagnostics +- bool vtls; // identify thread local variables +- bool vtemplates; // collect and list statistics on template instantiations +- bool vtemplatesListInstances; // collect and list statistics on template instantiations origins +- bool vgc; // identify gc usage +- bool vfield; // identify non-mutable field variables +- bool vcomplex; // identify complex/imaginary type usage +- bool vin; // identify 'in' parameters ++ d_bool obj; // write object file ++ d_bool multiobj; // break one object file into multiple ones ++ d_bool trace; // insert profiling hooks ++ d_bool tracegc; // instrument calls to 'new' ++ d_bool verbose; // verbose compile ++ d_bool vcg_ast; // write-out codegen-ast ++ d_bool showColumns; // print character (column) numbers in diagnostics ++ d_bool vtls; // identify thread local variables ++ d_bool vtemplates; // collect and list statistics on template instantiations ++ d_bool vtemplatesListInstances; // collect and list statistics on template instantiations origins ++ d_bool vgc; // identify gc usage ++ d_bool vfield; // identify non-mutable field variables ++ d_bool vcomplex; // identify complex/imaginary type usage ++ d_bool vin; // identify 'in' parameters + Diagnostic useDeprecated; +- bool useUnitTests; // generate unittest code +- bool useInline; // inline expand functions +- bool release; // build release version +- bool preservePaths; // true means don't strip path from source file ++ d_bool useUnitTests; // generate unittest code ++ d_bool useInline; // inline expand functions ++ d_bool release; // build release version ++ d_bool preservePaths; // true means don't strip path from source file + Diagnostic warnings; +- bool color; // use ANSI colors in console output +- bool cov; // generate code coverage data ++ d_bool color; // use ANSI colors in console output ++ d_bool cov; // generate code coverage data + unsigned char covPercent; // 0..100 code coverage percentage required +- bool ctfe_cov; // generate coverage data for ctfe +- bool ignoreUnsupportedPragmas; // rather than error on them +- bool useModuleInfo; // generate runtime module information +- bool useTypeInfo; // generate runtime type information +- bool useExceptions; // support exception handling +- bool betterC; // be a "better C" compiler; no dependency on D runtime +- bool addMain; // add a default main() function +- bool allInst; // generate code for all template instantiations +- bool bitfields; // support C style bit fields ++ d_bool ctfe_cov; // generate coverage data for ctfe ++ d_bool ignoreUnsupportedPragmas; // rather than error on them ++ d_bool useModuleInfo; // generate runtime module information ++ d_bool useTypeInfo; // generate runtime type information ++ d_bool useExceptions; // support exception handling ++ d_bool betterC; // be a "better C" compiler; no dependency on D runtime ++ d_bool addMain; // add a default main() function ++ d_bool allInst; // generate code for all template instantiations ++ d_bool bitfields; // support C style bit fields + CppStdRevision cplusplus; // version of C++ name mangling to support +- bool showGaggedErrors; // print gagged errors anyway +- bool printErrorContext; // print errors with the error context (the error line in the source file) +- bool manual; // open browser on compiler manual +- bool usage; // print usage and exit +- bool mcpuUsage; // print help on -mcpu switch +- bool transitionUsage; // print help on -transition switch +- bool checkUsage; // print help on -check switch +- bool checkActionUsage; // print help on -checkaction switch +- bool revertUsage; // print help on -revert switch +- bool previewUsage; // print help on -preview switch +- bool externStdUsage; // print help on -extern-std switch +- bool hcUsage; // print help on -HC switch +- bool logo; // print logo; ++ d_bool showGaggedErrors; // print gagged errors anyway ++ d_bool printErrorContext; // print errors with the error context (the error line in the source file) ++ d_bool manual; // open browser on compiler manual ++ d_bool usage; // print usage and exit ++ d_bool mcpuUsage; // print help on -mcpu switch ++ d_bool transitionUsage; // print help on -transition switch ++ d_bool checkUsage; // print help on -check switch ++ d_bool checkActionUsage; // print help on -checkaction switch ++ d_bool revertUsage; // print help on -revert switch ++ d_bool previewUsage; // print help on -preview switch ++ d_bool externStdUsage; // print help on -extern-std switch ++ d_bool hcUsage; // print help on -HC switch ++ d_bool logo; // print logo; + + // Options for `-preview=/-revert=` + FeatureState useDIP25; // implement https://wiki.dlang.org/DIP25 + FeatureState useDIP1000; // implement https://dlang.org/spec/memory-safe-d.html#scope-return-params +- bool ehnogc; // use @nogc exception handling +- bool useDIP1021; // implement https://github.com/dlang/DIPs/blob/master/DIPs/accepted/DIP1021.md +- bool fieldwise; // do struct equality testing field-wise rather than by memcmp() +- bool fixAliasThis; // if the current scope has an alias this, check it before searching upper scopes ++ d_bool ehnogc; // use @nogc exception handling ++ d_bool useDIP1021; // implement https://github.com/dlang/DIPs/blob/master/DIPs/accepted/DIP1021.md ++ d_bool fieldwise; // do struct equality testing field-wise rather than by memcmp() ++ d_bool fixAliasThis; // if the current scope has an alias this, check it before searching upper scopes + FeatureState rvalueRefParam; // allow rvalues to be arguments to ref parameters + // https://dconf.org/2019/talks/alexandrescu.html + // https://gist.github.com/andralex/e5405a5d773f07f73196c05f8339435a + // https://digitalmars.com/d/archives/digitalmars/D/Binding_rvalues_to_ref_parameters_redux_325087.html + // Implementation: https://github.com/dlang/dmd/pull/9817 + FeatureState noSharedAccess; // read/write access to shared memory objects +- bool previewIn; // `in` means `[ref] scope const`, accepts rvalues +- bool inclusiveInContracts; // 'in' contracts of overridden methods must be a superset of parent contract +- bool shortenedMethods; // allow => in normal function declarations +- bool fixImmutableConv; // error on unsound immutable conversion - https://github.com/dlang/dmd/pull/14070 +- bool fix16997; // fix integral promotions for unary + - ~ operators ++ d_bool previewIn; // `in` means `[ref] scope const`, accepts rvalues ++ d_bool inclusiveInContracts; // 'in' contracts of overridden methods must be a superset of parent contract ++ d_bool shortenedMethods; // allow => in normal function declarations ++ d_bool fixImmutableConv; // error on unsound immutable conversion - https://github.com/dlang/dmd/pull/14070 ++ d_bool fix16997; // fix integral promotions for unary + - ~ operators + // https://issues.dlang.org/show_bug.cgi?id=16997 + FeatureState dtorFields; // destruct fields of partially constructed objects + // https://issues.dlang.org/show_bug.cgi?id=14246 +@@ -208,7 +208,7 @@ struct Param + + MessageStyle messageStyle; // style of file/line annotations on messages + +- bool run; // run resulting executable ++ d_bool run; // run resulting executable + Strings runargs; // arguments for executable + + Array cppswitches; // preprocessor switches +@@ -228,7 +228,7 @@ struct Param + struct structalign_t + { + unsigned short value; +- bool pack; ++ d_bool pack; + + bool isDefault() const; + void setDefault(); +@@ -275,7 +275,7 @@ struct Global + Array* versionids; // command line versions and predefined versions + Array* debugids; // command line debug versions and predefined versions + +- bool hasMainFunction; ++ d_bool hasMainFunction; + unsigned varSequenceNumber; + + FileManager* fileManager; +--- a/src/gcc/d/dmd/hdrgen.d ++++ b/src/gcc/d/dmd/hdrgen.d +@@ -1586,7 +1586,10 @@ public: + if (hgs.hdrgen) + { + // if the return type is missing (e.g. ref functions or auto) +- if (!tf.next || f.storage_class & STC.auto_) ++ // https://issues.dlang.org/show_bug.cgi?id=20090 ++ // constructors are an exception: they don't have an explicit return ++ // type but we still don't output the body. ++ if ((!f.isCtorDeclaration() && !tf.next) || f.storage_class & STC.auto_) + { + hgs.autoMember++; + bodyToBuffer(f); +--- a/src/gcc/d/dmd/identifier.h ++++ b/src/gcc/d/dmd/identifier.h +@@ -17,7 +17,7 @@ class Identifier final : public RootObject + { + private: + int value; +- bool isAnonymous_; ++ d_bool isAnonymous_; + DString string; + + public: +--- a/src/gcc/d/dmd/init.h ++++ b/src/gcc/d/dmd/init.h +@@ -77,8 +77,8 @@ public: + Initializers value; // of Initializer *'s + unsigned dim; // length of array being initialized + Type *type; // type that array will be used to initialize +- bool sem; // true if semantic() is run +- bool isCarray; // C array semantics ++ d_bool sem; // true if semantic() is run ++ d_bool isCarray; // C array semantics + + bool isAssociativeArray() const; + Expression *toAssocArrayLiteral(); +@@ -89,7 +89,7 @@ public: + class ExpInitializer final : public Initializer + { + public: +- bool expandTuples; ++ d_bool expandTuples; + Expression *exp; + + void accept(Visitor *v) override { v->visit(this); } +@@ -112,7 +112,7 @@ class CInitializer final : public Initializer + public: + DesigInits initializerList; + Type *type; // type that array will be used to initialize +- bool sem; // true if semantic() is run ++ d_bool sem; // true if semantic() is run + + void accept(Visitor *v) override { v->visit(this); } + }; +--- a/src/gcc/d/dmd/lexer.d ++++ b/src/gcc/d/dmd/lexer.d +@@ -2664,14 +2664,19 @@ class Lexer + eSink.error(loc, format, args); + } + +- final void deprecation(const(char)* format) ++ void deprecation(T...)(const ref Loc loc, const(char)* format, T args) + { +- eSink.deprecation(token.loc, format); ++ eSink.deprecation(loc, format, args); + } + +- final void deprecationSupplemental(const(char)* format) ++ void deprecation(T...)(const(char)* format, T args) + { +- eSink.deprecationSupplemental(token.loc, format); ++ eSink.deprecation(token.loc, format, args); ++ } ++ ++ void deprecationSupplemental(T...)(const(char)* format, T args) ++ { ++ eSink.deprecationSupplemental(token.loc, format, args); + } + + /*************************************** +@@ -2695,12 +2700,21 @@ class Lexer + else + { + const locx = loc(); +- eSink.warning(locx, "C preprocessor directive `#%s` is not supported", n.ident.toChars()); ++ // @@@DEPRECATED_2.103@@@ ++ // Turn into an error in 2.113 ++ if (inTokenStringConstant) ++ deprecation(locx, "token string requires valid D tokens, not `#%s`", n.ident.toChars()); ++ else ++ error(locx, "C preprocessor directive `#%s` is not supported", n.ident.toChars()); + } + } + else if (n.value == TOK.if_) + { +- error("C preprocessor directive `#if` is not supported, use `version` or `static if`"); ++ const locx = loc(); ++ if (inTokenStringConstant) ++ error(locx, "token string requires valid D tokens, not `#if`"); ++ else ++ error(locx, "C preprocessor directive `#if` is not supported, use `version` or `static if`"); + } + return false; + } +--- a/src/gcc/d/dmd/module.h ++++ b/src/gcc/d/dmd/module.h +@@ -74,8 +74,8 @@ public: + unsigned errors; // if any errors in file + unsigned numlines; // number of lines in source file + FileType filetype; // source file type +- bool hasAlwaysInlines; // contains references to functions that must be inlined +- bool isPackageFile; // if it is a package.d ++ d_bool hasAlwaysInlines; // contains references to functions that must be inlined ++ d_bool isPackageFile; // if it is a package.d + Package *pkg; // if isPackageFile is true, the Package that contains this package.d + Strings contentImportedFiles; // array of files whose content was imported + int needmoduleinfo; +@@ -90,7 +90,7 @@ public: + Identifier *searchCacheIdent; + Dsymbol *searchCacheSymbol; // cached value of search + int searchCacheFlags; // cached flags +- bool insearch; ++ d_bool insearch; + + // module from command line we're imported from, + // i.e. a module that will be taken all the +@@ -165,7 +165,7 @@ struct ModuleDeclaration + Loc loc; + Identifier *id; + DArray packages; // array of Identifier's representing packages +- bool isdeprecated; // if it is a deprecated module ++ d_bool isdeprecated; // if it is a deprecated module + Expression *msg; + + const char *toChars() const; +--- a/src/gcc/d/dmd/mtype.h ++++ b/src/gcc/d/dmd/mtype.h +@@ -589,7 +589,7 @@ struct ParameterList + Parameters* parameters; + StorageClass stc; + VarArg varargs; +- bool hasIdentifierList; // true if C identifier-list style ++ d_bool hasIdentifierList; // true if C identifier-list style + + size_t length(); + Parameter *operator[](size_t i) { return Parameter::getNth(parameters, i); } +@@ -779,7 +779,7 @@ class TypeStruct final : public Type + public: + StructDeclaration *sym; + AliasThisRec att; +- bool inuse; ++ d_bool inuse; + + static TypeStruct *create(StructDeclaration *sym); + const char *kind() override; +--- a/src/gcc/d/dmd/objc.h ++++ b/src/gcc/d/dmd/objc.h +@@ -37,8 +37,8 @@ struct ObjcSelector + + struct ObjcClassDeclaration + { +- bool isMeta; +- bool isExtern; ++ d_bool isMeta; ++ d_bool isExtern; + + Identifier* identifier; + ClassDeclaration* classDeclaration; +@@ -52,7 +52,7 @@ struct ObjcFuncDeclaration + { + ObjcSelector* selector; + VarDeclaration* selectorParameter; +- bool isOptional; ++ d_bool isOptional; + }; + + class Objc +--- a/src/gcc/d/dmd/root/array.d ++++ b/src/gcc/d/dmd/root/array.d +@@ -574,7 +574,7 @@ unittest + private template arraySortWrapper(T, alias fn) + { + pragma(mangle, "arraySortWrapper_" ~ T.mangleof ~ "_" ~ fn.mangleof) +- extern(C) int arraySortWrapper(scope const void* e1, scope const void* e2) nothrow ++ extern(C) int arraySortWrapper(scope const void* e1, scope const void* e2) + { + return fn(cast(const(T*))e1, cast(const(T*))e2); + } +--- a/src/gcc/d/dmd/root/dcompat.h ++++ b/src/gcc/d/dmd/root/dcompat.h +@@ -36,7 +36,7 @@ struct DString : public DArray + }; + + /// Corresponding C++ type that maps to D size_t +-#if __APPLE__ && __i386__ ++#if __APPLE__ && (__i386__ || __ppc__) + // size_t is 'unsigned long', which makes it mangle differently than D's 'uint' + typedef unsigned d_size_t; + #elif MARS && DMD_VERSION >= 2079 && DMD_VERSION <= 2081 && \ +@@ -49,3 +49,11 @@ typedef unsigned d_size_t; + #else + typedef size_t d_size_t; + #endif ++ ++/// Corresponding C++ type that maps to D bool ++#if __APPLE__ && __ppc__ ++// bool is defined as an 'int', which does not match same size as D ++typedef uint8_t d_bool; ++#else ++typedef bool d_bool; ++#endif +--- a/src/gcc/d/dmd/root/optional.h ++++ b/src/gcc/d/dmd/root/optional.h +@@ -11,6 +11,8 @@ + * Coverage: https://codecov.io/gh/dlang/dmd/src/master/src/dmd/root/optional.h + */ + ++#include "dcompat.h" // for d_bool ++ + /// Optional type that is either `empty` or contains a value of type `T` + template + struct Optional final +@@ -20,7 +22,7 @@ private: + T value; + + /** whether `value` is set **/ +- bool present; ++ d_bool present; + + public: + /** Creates an `Optional` with the given value **/ +--- a/src/gcc/d/dmd/scope.h ++++ b/src/gcc/d/dmd/scope.h +@@ -81,8 +81,8 @@ struct Scope + ForeachStatement *fes; // if nested function for ForeachStatement, this is it + Scope *callsc; // used for __FUNCTION__, __PRETTY_FUNCTION__ and __MODULE__ + Dsymbol *inunion; // !=null if processing members of a union +- bool nofree; // true if shouldn't free it +- bool inLoop; // true if inside a loop (where constructor calls aren't allowed) ++ d_bool nofree; // true if shouldn't free it ++ d_bool inLoop; // true if inside a loop (where constructor calls aren't allowed) + int intypeof; // in typeof(exp) + VarDeclaration *lastVar; // Previous symbol used to prevent goto-skips-init + +--- a/src/gcc/d/dmd/semantic2.d ++++ b/src/gcc/d/dmd/semantic2.d +@@ -807,9 +807,8 @@ private void doGNUABITagSemantic(ref Expression e, ref Expression* lastTag) + // but it's a concession to practicality. + // Casts are unfortunately necessary as `implicitConvTo` is not + // `const` (and nor is `StringExp`, by extension). +- static int predicate(const scope Expression* e1, const scope Expression* e2) nothrow ++ static int predicate(const scope Expression* e1, const scope Expression* e2) + { +- scope(failure) assert(0, "An exception was thrown"); + return (cast(Expression*)e1).toStringExp().compare((cast(Expression*)e2).toStringExp()); + } + ale.elements.sort!predicate; +--- a/src/gcc/d/dmd/semantic3.d ++++ b/src/gcc/d/dmd/semantic3.d +@@ -1420,7 +1420,7 @@ private extern(C++) final class Semantic3Visitor : Visitor + * https://issues.dlang.org/show_bug.cgi?id=14246 + */ + AggregateDeclaration ad = ctor.isMemberDecl(); +- if (!ctor.fbody || !ad || !ad.fieldDtor || !global.params.dtorFields || global.params.betterC || ctor.type.toTypeFunction.isnothrow) ++ if (!ctor.fbody || !ad || !ad.fieldDtor || !global.params.dtorFields || !global.params.useExceptions || ctor.type.toTypeFunction.isnothrow) + return visit(cast(FuncDeclaration)ctor); + + /* Generate: +--- a/src/gcc/d/dmd/statement.h ++++ b/src/gcc/d/dmd/statement.h +@@ -433,7 +433,7 @@ class SwitchStatement final : public Statement + public: + Expression *condition; + Statement *_body; +- bool isFinal; ++ d_bool isFinal; + + DefaultStatement *sdefault; + Statement *tryBody; // set to TryCatchStatement or TryFinallyStatement if in _body portion +@@ -600,11 +600,11 @@ public: + + VarDeclaration *var; + // set if semantic processing errors +- bool errors; ++ d_bool errors; + + // was generated by the compiler, + // wasn't present in source code +- bool internalCatch; ++ d_bool internalCatch; + + Catch *syntaxCopy(); + }; +@@ -616,7 +616,7 @@ public: + Statement *finalbody; + + Statement *tryBody; // set to enclosing TryCatchStatement or TryFinallyStatement if in _body portion +- bool bodyFallsThru; // true if _body falls through to finally ++ d_bool bodyFallsThru; // true if _body falls through to finally + + static TryFinallyStatement *create(const Loc &loc, Statement *body, Statement *finalbody); + TryFinallyStatement *syntaxCopy() override; +@@ -643,7 +643,7 @@ public: + Expression *exp; + // was generated by the compiler, + // wasn't present in source code +- bool internalThrow; ++ d_bool internalThrow; + + ThrowStatement *syntaxCopy() override; + +@@ -668,7 +668,7 @@ public: + TryFinallyStatement *tf; + ScopeGuardStatement *os; + VarDeclaration *lastVar; +- bool inCtfeBlock; ++ d_bool inCtfeBlock; + GotoStatement *syntaxCopy() override; + + void accept(Visitor *v) override { v->visit(this); } +@@ -685,8 +685,8 @@ public: + VarDeclaration *lastVar; + Statement *gotoTarget; // interpret + void* extra; // used by Statement_toIR() +- bool breaks; // someone did a 'break ident' +- bool inCtfeBlock; ++ d_bool breaks; // someone did a 'break ident' ++ d_bool inCtfeBlock; + LabelStatement *syntaxCopy() override; + + void accept(Visitor *v) override { v->visit(this); } +@@ -697,8 +697,8 @@ class LabelDsymbol final : public Dsymbol + public: + LabelStatement *statement; + +- bool deleted; // set if rewritten to return in foreach delegate +- bool iasm; // set if used by inline assembler ++ d_bool deleted; // set if rewritten to return in foreach delegate ++ d_bool iasm; // set if used by inline assembler + + static LabelDsymbol *create(Identifier *ident); + LabelDsymbol *isLabel() override; +@@ -722,8 +722,8 @@ public: + code *asmcode; + unsigned asmalign; // alignment of this statement + unsigned regs; // mask of registers modified (must match regm_t in back end) +- bool refparam; // true if function parameter is referenced +- bool naked; // true if function is to be naked ++ d_bool refparam; // true if function parameter is referenced ++ d_bool naked; // true if function is to be naked + + InlineAsmStatement *syntaxCopy() override; + void accept(Visitor *v) override { v->visit(this); } +--- a/src/gcc/d/dmd/statementsem.d ++++ b/src/gcc/d/dmd/statementsem.d +@@ -1941,7 +1941,6 @@ package (dmd) extern (C++) final class StatementSemanticVisitor : Visitor + } + if (checkNonAssignmentArrayOp(ifs.condition)) + ifs.condition = ErrorExp.get(); +- ifs.condition = checkGC(scd, ifs.condition); + + // Convert to boolean after declaring prm so this works: + // if (S prm = S()) {} +@@ -1953,6 +1952,10 @@ package (dmd) extern (C++) final class StatementSemanticVisitor : Visitor + // This feature allows a limited form of conditional compilation. + ifs.condition = ifs.condition.optimize(WANTvalue); + ++ // checkGC after optimizing the condition so that ++ // compile time constants are reduced. ++ ifs.condition = checkGC(scd, ifs.condition); ++ + // Save 'root' of two branches (then and else) at the point where it forks + CtorFlow ctorflow_root = scd.ctorflow.clone(); + +@@ -4525,8 +4528,7 @@ public auto makeTupleForeach(Scope* sc, bool isStatic, bool isDecl, ForeachState + decls.append(Dsymbol.arraySyntaxCopy(dbody)); + else + { +- if (fs._body) // https://issues.dlang.org/show_bug.cgi?id=17646 +- stmts.push(fs._body.syntaxCopy()); ++ stmts.push(fs._body.syntaxCopy()); + s = new CompoundStatement(loc, stmts); + } + +--- a/src/gcc/d/dmd/target.h ++++ b/src/gcc/d/dmd/target.h +@@ -92,11 +92,11 @@ struct TargetCPP + Microsoft, + Sun + }; +- bool reverseOverloads; // with dmc and cl, overloaded functions are grouped and in reverse order +- bool exceptions; // set if catching C++ exceptions is supported +- bool twoDtorInVtable; // target C++ ABI puts deleting and non-deleting destructor into vtable +- bool splitVBasetable; // set if C++ ABI uses separate tables for virtual functions and virtual bases +- bool wrapDtorInExternD; // set if C++ dtors require a D wrapper to be callable from runtime ++ d_bool reverseOverloads; // with dmc and cl, overloaded functions are grouped and in reverse order ++ d_bool exceptions; // set if catching C++ exceptions is supported ++ d_bool twoDtorInVtable; // target C++ ABI puts deleting and non-deleting destructor into vtable ++ d_bool splitVBasetable; // set if C++ ABI uses separate tables for virtual functions and virtual bases ++ d_bool wrapDtorInExternD; // set if C++ dtors require a D wrapper to be callable from runtime + Runtime runtime; + + const char *toMangle(Dsymbol *s); +@@ -110,7 +110,7 @@ struct TargetCPP + + struct TargetObjC + { +- bool supported; // set if compiler can interface with Objective-C ++ d_bool supported; // set if compiler can interface with Objective-C + }; + + struct Target +@@ -156,15 +156,15 @@ struct Target + + DString architectureName; // name of the platform architecture (e.g. X86_64) + CPU cpu; // CPU instruction set to target +- bool is64bit; // generate 64 bit code for x86_64; true by default for 64 bit dmd +- bool isLP64; // pointers are 64 bits ++ d_bool is64bit; // generate 64 bit code for x86_64; true by default for 64 bit dmd ++ d_bool isLP64; // pointers are 64 bits + + // Environmental + DString obj_ext; /// extension for object files + DString lib_ext; /// extension for static library files + DString dll_ext; /// extension for dynamic library files +- bool run_noext; /// allow -run sources without extensions +- bool omfobj; /// for Win32: write OMF object files instead of COFF ++ d_bool run_noext; /// allow -run sources without extensions ++ d_bool omfobj; /// for Win32: write OMF object files instead of COFF + + template + struct FPTypeProperties +--- a/src/gcc/d/dmd/template.h ++++ b/src/gcc/d/dmd/template.h +@@ -78,12 +78,12 @@ public: + + Dsymbol *onemember; // if !=NULL then one member of this template + +- bool literal; // this template declaration is a literal +- bool ismixin; // template declaration is only to be used as a mixin +- bool isstatic; // this is static template declaration +- bool isTrivialAliasSeq; // matches `template AliasSeq(T...) { alias AliasSeq = T; } +- bool isTrivialAlias; // matches pattern `template Alias(T) { alias Alias = qualifiers(T); }` +- bool deprecated_; // this template declaration is deprecated ++ d_bool literal; // this template declaration is a literal ++ d_bool ismixin; // template declaration is only to be used as a mixin ++ d_bool isstatic; // this is static template declaration ++ d_bool isTrivialAliasSeq; // matches `template AliasSeq(T...) { alias AliasSeq = T; } ++ d_bool isTrivialAlias; // matches pattern `template Alias(T) { alias Alias = qualifiers(T); }` ++ d_bool deprecated_; // this template declaration is deprecated + Visibility visibility; + + TemplatePrevious *previous; // threaded list of previous instantiation attempts on stack +@@ -133,7 +133,7 @@ public: + * A dependent template parameter should return MATCHexact in matchArg() + * to respect the match level of the corresponding precedent parameter. + */ +- bool dependent; ++ d_bool dependent; + + virtual TemplateTypeParameter *isTemplateTypeParameter(); + virtual TemplateValueParameter *isTemplateValueParameter(); +--- a/src/gcc/d/dmd/visitor.h ++++ b/src/gcc/d/dmd/visitor.h +@@ -10,6 +10,7 @@ + #pragma once + + #include "root/dsystem.h" ++#include "root/dcompat.h" // for d_bool + + class Statement; + class ErrorStatement; +@@ -663,6 +664,6 @@ public: + class StoppableVisitor : public Visitor + { + public: +- bool stop; ++ d_bool stop; + StoppableVisitor() : stop(false) {} + }; +--- a/src/gcc/d/expr.cc ++++ b/src/gcc/d/expr.cc +@@ -2701,6 +2701,10 @@ public: + if (tb->ty == TY::Tarray) + ctor = d_array_value (type, size_int (e->elements->length), ctor); + ++ /* Immutable literals can be placed in rodata. */ ++ if (tb->isImmutable ()) ++ TREE_READONLY (decl) = 1; ++ + d_pushdecl (decl); + rest_of_decl_compilation (decl, 1, 0); + } +--- a/src/gcc/d/imports.cc ++++ b/src/gcc/d/imports.cc +@@ -127,6 +127,15 @@ public: + this->result_ = this->make_import (TYPE_STUB_DECL (type)); + } + ++ void visit (VarDeclaration *d) final override ++ { ++ /* Not all kinds of manifest constants create a CONST_DECL. */ ++ if (!d->canTakeAddressOf () && !d->type->isscalar ()) ++ return; ++ ++ visit ((Declaration *) d); ++ } ++ + /* For now, ignore importing other kinds of dsymbols. */ + void visit (ScopeDsymbol *) final override + { +--- a/src/gcc/d/intrinsics.cc ++++ b/src/gcc/d/intrinsics.cc +@@ -1007,6 +1007,7 @@ expand_volatile_load (tree callexp) + tree type = build_qualified_type (TREE_TYPE (ptrtype), TYPE_QUAL_VOLATILE); + tree result = indirect_ref (type, ptr); + TREE_THIS_VOLATILE (result) = 1; ++ TREE_SIDE_EFFECTS (result) = 1; + + return result; + } +@@ -1034,6 +1035,7 @@ expand_volatile_store (tree callexp) + tree type = build_qualified_type (TREE_TYPE (ptrtype), TYPE_QUAL_VOLATILE); + tree result = indirect_ref (type, ptr); + TREE_THIS_VOLATILE (result) = 1; ++ TREE_SIDE_EFFECTS (result) = 1; + + /* (*(volatile T *) ptr) = value; */ + tree value = CALL_EXPR_ARG (callexp, 1); +--- a/src/gcc/d/lang.opt ++++ b/src/gcc/d/lang.opt +@@ -134,6 +134,14 @@ Werror + D + ; Documented in common.opt + ++Wextra ++D Warning ++; Documented in common.opt ++ ++Wmismatched-special-enum ++D Warning Var(warn_mismatched_special_enum) LangEnabledBy(D, Wextra) ++Warn when a special enum is declared with the wrong base type. ++ + Wpsabi + D + ; Documented in C +@@ -283,6 +291,10 @@ fdump-d-original + D + Display the frontend AST after parsing and semantic passes. + ++fexceptions ++D ++; Documented in common.opt ++ + fextern-std= + D Joined RejectNegative Enum(extern_stdcpp) Var(flag_extern_stdcpp) + -fextern-std= Set C++ name mangling compatibility with . +--- a/src/gcc/d/types.cc ++++ b/src/gcc/d/types.cc +@@ -573,6 +573,35 @@ layout_aggregate_type (AggregateDeclaration *decl, tree type, + } + } + ++/* Given a record type TYPE compute the finalized record mode if all fields have ++ had their types resolved and sizes determined. */ ++ ++void ++finish_aggregate_mode (tree type) ++{ ++ for (tree field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) ++ { ++ /* Fields of type `typeof(*null)' have no size, so let them force the ++ record type mode to be computed as BLKmode. */ ++ if (TYPE_MAIN_VARIANT (TREE_TYPE (field)) == noreturn_type_node) ++ break; ++ ++ if (DECL_SIZE (field) == NULL_TREE) ++ return; ++ } ++ ++ compute_record_mode (type); ++ ++ /* Propagate computed mode to all variants of this aggregate type. */ ++ for (tree t = TYPE_MAIN_VARIANT (type); t; t = TYPE_NEXT_VARIANT (t)) ++ { ++ if (t == type) ++ continue; ++ ++ SET_TYPE_MODE (t, TYPE_MODE (type)); ++ } ++} ++ + /* If the aggregate type TYPE completes the type of any previous field + declarations, lay them out now. */ + +@@ -596,6 +625,9 @@ finish_incomplete_fields (tree type) + } + + relayout_decl (field); ++ ++ /* Relayout of field may change the mode of its RECORD_TYPE. */ ++ finish_aggregate_mode (DECL_FIELD_CONTEXT (field)); + } + + /* No more forward references to process. */ +@@ -615,9 +647,6 @@ finish_aggregate_type (unsigned structsize, unsigned alignsize, tree type) + SET_TYPE_ALIGN (type, alignsize * BITS_PER_UNIT); + TYPE_PACKED (type) = (alignsize == 1); + +- /* Set the back-end type mode. */ +- compute_record_mode (type); +- + /* Layout all fields now the type is complete. */ + for (tree field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) + { +@@ -662,6 +691,9 @@ finish_aggregate_type (unsigned structsize, unsigned alignsize, tree type) + } + } + ++ /* Set the back-end type mode after all fields have had their size set. */ ++ finish_aggregate_mode (type); ++ + /* Fix up all forward-referenced variants of this aggregate type. */ + for (tree t = TYPE_MAIN_VARIANT (type); t; t = TYPE_NEXT_VARIANT (t)) + { +@@ -673,7 +705,6 @@ finish_aggregate_type (unsigned structsize, unsigned alignsize, tree type) + TYPE_SIZE (t) = TYPE_SIZE (type); + TYPE_SIZE_UNIT (t) = TYPE_SIZE_UNIT (type); + TYPE_PACKED (type) = TYPE_PACKED (type); +- SET_TYPE_MODE (t, TYPE_MODE (type)); + SET_TYPE_ALIGN (t, TYPE_ALIGN (type)); + TYPE_USER_ALIGN (t) = TYPE_USER_ALIGN (type); + } +@@ -1067,6 +1098,21 @@ public: + gcc_assert (underlying != NULL); + + t->ctype = build_variant_type_copy (build_ctype (underlying)); ++ ++ /* When the size of the declared enum base type doesn't match the target ++ C type that this enum is being used as a placeholder for, we can't ++ use the generated underlying type as it'll conflict with all sizes ++ the front-end has computed during semantic. */ ++ if (TYPE_SIZE (t->ctype) != TYPE_SIZE (basetype)) ++ { ++ warning_at (make_location_t (t->sym->loc), ++ OPT_Wmismatched_special_enum, ++ "size of %qs (%wd) differ from its declared size (%wd)", ++ t->sym->ident->toChars (), int_size_in_bytes (t->ctype), ++ int_size_in_bytes (basetype)); ++ t->ctype = basetype; ++ } ++ + build_type_decl (t->ctype, t->sym); + } + else if (t->sym->ident == NULL +--- a/src/gcc/dwarf2out.cc ++++ b/src/gcc/dwarf2out.cc +@@ -26534,7 +26534,8 @@ process_scope_var (tree stmt, tree decl, tree origin, dw_die_ref context_die) + + if (die != NULL && die->die_parent == NULL) + add_child_die (context_die, die); +- else if (TREE_CODE (decl_or_origin) == IMPORTED_DECL) ++ ++ if (TREE_CODE (decl_or_origin) == IMPORTED_DECL) + { + if (early_dwarf) + dwarf2out_imported_module_or_decl_1 (decl_or_origin, DECL_NAME (decl_or_origin), +--- a/src/gcc/fold-const.cc ++++ b/src/gcc/fold-const.cc +@@ -8428,20 +8428,26 @@ native_encode_initializer (tree init, unsigned char *ptr, int len, + if (fieldsize == 0) + continue; + ++ /* Prepare to deal with integral bit-fields and filter out other ++ bit-fields that do not start and end on a byte boundary. */ + if (DECL_BIT_FIELD (field)) + { + if (!tree_fits_uhwi_p (DECL_FIELD_BIT_OFFSET (field))) + return 0; +- fieldsize = TYPE_PRECISION (TREE_TYPE (field)); + bpos = tree_to_uhwi (DECL_FIELD_BIT_OFFSET (field)); +- if (bpos % BITS_PER_UNIT) +- bpos %= BITS_PER_UNIT; +- else +- bpos = 0; +- fieldsize += bpos; +- epos = fieldsize % BITS_PER_UNIT; +- fieldsize += BITS_PER_UNIT - 1; +- fieldsize /= BITS_PER_UNIT; ++ if (INTEGRAL_TYPE_P (TREE_TYPE (field))) ++ { ++ bpos %= BITS_PER_UNIT; ++ fieldsize = TYPE_PRECISION (TREE_TYPE (field)) + bpos; ++ epos = fieldsize % BITS_PER_UNIT; ++ fieldsize += BITS_PER_UNIT - 1; ++ fieldsize /= BITS_PER_UNIT; ++ } ++ else if (bpos % BITS_PER_UNIT ++ || DECL_SIZE (field) == NULL_TREE ++ || !tree_fits_shwi_p (DECL_SIZE (field)) ++ || tree_to_shwi (DECL_SIZE (field)) % BITS_PER_UNIT) ++ return 0; + } + + if (off != -1 && pos + fieldsize <= off) +@@ -8450,7 +8456,8 @@ native_encode_initializer (tree init, unsigned char *ptr, int len, + if (val == NULL_TREE) + continue; + +- if (DECL_BIT_FIELD (field)) ++ if (DECL_BIT_FIELD (field) ++ && INTEGRAL_TYPE_P (TREE_TYPE (field))) + { + /* FIXME: Handle PDP endian. */ + if (BYTES_BIG_ENDIAN != WORDS_BIG_ENDIAN) --- a/src/gcc/fortran/ChangeLog +++ b/src/gcc/fortran/ChangeLog -@@ -1,3 +1,23 @@ +@@ -1,3 +1,88 @@ ++2023-07-08 Harald Anlauf ++ ++ Backported from master: ++ 2023-07-08 Harald Anlauf ++ ++ PR fortran/110585 ++ * arith.cc (gfc_compare_expr): Handle equality comparison of constant ++ complex gfc_expr arguments. ++ ++2023-06-29 Harald Anlauf ++ ++ Backported from master: ++ 2023-06-13 Harald Anlauf ++ Mikael Morin ++ ++ PR fortran/86277 ++ * trans-array.cc (gfc_trans_allocate_array_storage): When passing a ++ zero-sized array with fixed (= non-dynamic) size, allocate temporary ++ by the caller, not by the callee. ++ ++2023-06-09 Jakub Jelinek ++ ++ Backported from master: ++ 2023-06-09 Jakub Jelinek ++ ++ PR fortran/96024 ++ * primary.cc (gfc_convert_to_structure_constructor): Only do ++ constant string ctor length verification and truncation/padding ++ if constant length has INTEGER type. ++ ++2023-06-03 Steve Kargl ++ ++ Backported from master: ++ 2023-06-02 Steve Kargl ++ ++ PR fortran/100607 ++ * resolve.cc (resolve_select_rank): Remove duplicate error. ++ (resolve_fl_var_and_proc): Prevent NULL pointer dereference and ++ suppress error message for temporary. ++ ++2023-05-18 Harald Anlauf ++ ++ Backported from master: ++ 2023-05-15 Harald Anlauf ++ ++ PR fortran/109846 ++ * expr.cc (gfc_check_vardef_context): Check appropriate pointer ++ attribute for CLASS vs. non-CLASS function result in variable ++ definition context. ++ ++2023-05-18 Harald Anlauf ++ ++ Backported from master: ++ 2023-05-05 Harald Anlauf ++ ++ PR fortran/109641 ++ * arith.cc (eval_intrinsic): Check conformability of ranks of operands ++ for intrinsic binary operators before performing type conversions. ++ * gfortran.h (gfc_op_rank_conformable): Add prototype. ++ * resolve.cc (resolve_operator): Check conformability of ranks of ++ operands for intrinsic binary operators before performing type ++ conversions. ++ (gfc_op_rank_conformable): New helper function to compare ranks of ++ operands of binary operator. ++ +2023-05-05 Julian Brown + + Backported from master: @@ -1562,6 +13930,54 @@ 2023-04-26 Release Manager * GCC 13.1.0 released. +--- a/src/gcc/fortran/arith.cc ++++ b/src/gcc/fortran/arith.cc +@@ -1120,6 +1120,11 @@ gfc_compare_expr (gfc_expr *op1, gfc_expr *op2, gfc_intrinsic_op op) + || (op1->value.logical && !op2->value.logical)); + break; + ++ case BT_COMPLEX: ++ gcc_assert (op == INTRINSIC_EQ); ++ rc = mpc_cmp (op1->value.complex, op2->value.complex); ++ break; ++ + default: + gfc_internal_error ("gfc_compare_expr(): Bad basic type"); + } +@@ -1663,6 +1668,12 @@ eval_intrinsic (gfc_intrinsic_op op, + if (!gfc_numeric_ts (&op1->ts) || !gfc_numeric_ts (&op2->ts)) + goto runtime; + ++ /* Do not perform conversions if operands are not conformable as ++ required for the binary intrinsic operators (F2018:10.1.5). ++ Defer to a possibly overloading user-defined operator. */ ++ if (!gfc_op_rank_conformable (op1, op2)) ++ goto runtime; ++ + /* Insert any necessary type conversions to make the operands + compatible. */ + +--- a/src/gcc/fortran/expr.cc ++++ b/src/gcc/fortran/expr.cc +@@ -6256,7 +6256,7 @@ gfc_check_vardef_context (gfc_expr* e, bool pointer, bool alloc_obj, + && !(sym->attr.flavor == FL_PROCEDURE && sym == sym->result) + && !(sym->attr.flavor == FL_PROCEDURE && sym->attr.proc_pointer) + && !(sym->attr.flavor == FL_PROCEDURE +- && sym->attr.function && sym->attr.pointer)) ++ && sym->attr.function && attr.pointer)) + { + if (context) + gfc_error ("%qs in variable definition context (%s) at %L is not" +--- a/src/gcc/fortran/gfortran.h ++++ b/src/gcc/fortran/gfortran.h +@@ -3730,6 +3730,7 @@ void gfc_free_association_list (gfc_association_list *); + + /* resolve.cc */ + void gfc_expression_rank (gfc_expr *); ++bool gfc_op_rank_conformable (gfc_expr *, gfc_expr *); + bool gfc_resolve_ref (gfc_expr *); + bool gfc_resolve_expr (gfc_expr *); + void gfc_resolve (gfc_namespace *); --- a/src/gcc/fortran/openmp.cc +++ b/src/gcc/fortran/openmp.cc @@ -7711,6 +7711,22 @@ resolve_omp_clauses (gfc_code *code, gfc_omp_clauses *omp_clauses, @@ -1587,6 +14003,116 @@ if (lastref || (n->expr && (!resolved || n->expr->expr_type != EXPR_VARIABLE))) +--- a/src/gcc/fortran/primary.cc ++++ b/src/gcc/fortran/primary.cc +@@ -3188,10 +3188,11 @@ gfc_convert_to_structure_constructor (gfc_expr *e, gfc_symbol *sym, gfc_expr **c + goto cleanup; + + /* For a constant string constructor, make sure the length is +- correct; truncate of fill with blanks if needed. */ ++ correct; truncate or fill with blanks if needed. */ + if (this_comp->ts.type == BT_CHARACTER && !this_comp->attr.allocatable + && this_comp->ts.u.cl && this_comp->ts.u.cl->length + && this_comp->ts.u.cl->length->expr_type == EXPR_CONSTANT ++ && this_comp->ts.u.cl->length->ts.type == BT_INTEGER + && actual->expr->ts.type == BT_CHARACTER + && actual->expr->expr_type == EXPR_CONSTANT) + { +--- a/src/gcc/fortran/resolve.cc ++++ b/src/gcc/fortran/resolve.cc +@@ -4200,6 +4200,17 @@ resolve_operator (gfc_expr *e) + case INTRINSIC_POWER: + if (gfc_numeric_ts (&op1->ts) && gfc_numeric_ts (&op2->ts)) + { ++ /* Do not perform conversions if operands are not conformable as ++ required for the binary intrinsic operators (F2018:10.1.5). ++ Defer to a possibly overloading user-defined operator. */ ++ if (!gfc_op_rank_conformable (op1, op2)) ++ { ++ dual_locus_error = true; ++ snprintf (msg, sizeof (msg), ++ _("Inconsistent ranks for operator at %%L and %%L")); ++ goto bad_op; ++ } ++ + gfc_type_convert_binary (e, 1); + break; + } +@@ -4372,6 +4383,17 @@ resolve_operator (gfc_expr *e) + + if (gfc_numeric_ts (&op1->ts) && gfc_numeric_ts (&op2->ts)) + { ++ /* Do not perform conversions if operands are not conformable as ++ required for the binary intrinsic operators (F2018:10.1.5). ++ Defer to a possibly overloading user-defined operator. */ ++ if (!gfc_op_rank_conformable (op1, op2)) ++ { ++ dual_locus_error = true; ++ snprintf (msg, sizeof (msg), ++ _("Inconsistent ranks for operator at %%L and %%L")); ++ goto bad_op; ++ } ++ + gfc_type_convert_binary (e, 1); + + e->ts.type = BT_LOGICAL; +@@ -5644,6 +5666,21 @@ done: + } + + ++/* Given two expressions, check that their rank is conformable, i.e. either ++ both have the same rank or at least one is a scalar. */ ++ ++bool ++gfc_op_rank_conformable (gfc_expr *op1, gfc_expr *op2) ++{ ++ if (op1->expr_type == EXPR_VARIABLE) ++ gfc_expression_rank (op1); ++ if (op2->expr_type == EXPR_VARIABLE) ++ gfc_expression_rank (op2); ++ ++ return (op1->rank == 0 || op2->rank == 0 || op1->rank == op2->rank); ++} ++ ++ + static void + add_caf_get_intrinsic (gfc_expr *e) + { +@@ -9982,11 +10019,6 @@ resolve_select_rank (gfc_code *code, gfc_namespace *old_ns) + || gfc_expr_attr (code->expr1).pointer)) + gfc_error ("RANK (*) at %L cannot be used with the pointer or " + "allocatable selector at %L", &c->where, &code->expr1->where); +- +- if (case_value == -1 && (gfc_expr_attr (code->expr1).allocatable +- || gfc_expr_attr (code->expr1).pointer)) +- gfc_error ("RANK (*) at %L cannot be used with the pointer or " +- "allocatable selector at %L", &c->where, &code->expr1->where); + } + + /* Add EXEC_SELECT to switch on rank. */ +@@ -13209,7 +13241,10 @@ resolve_fl_var_and_proc (gfc_symbol *sym, int mp_flag) + + if (allocatable) + { +- if (dimension && as->type != AS_ASSUMED_RANK) ++ if (dimension ++ && as ++ && as->type != AS_ASSUMED_RANK ++ && !sym->attr.select_rank_temporary) + { + gfc_error ("Allocatable array %qs at %L must have a deferred " + "shape or assumed rank", sym->name, &sym->declared_at); +--- a/src/gcc/fortran/trans-array.cc ++++ b/src/gcc/fortran/trans-array.cc +@@ -1117,7 +1117,7 @@ gfc_trans_allocate_array_storage (stmtblock_t * pre, stmtblock_t * post, + + desc = info->descriptor; + info->offset = gfc_index_zero_node; +- if (size == NULL_TREE || integer_zerop (size)) ++ if (size == NULL_TREE || (dynamic && integer_zerop (size))) + { + /* A callee allocated array. */ + gfc_conv_descriptor_data_set (pre, desc, null_pointer_node); --- a/src/gcc/fortran/trans-openmp.cc +++ b/src/gcc/fortran/trans-openmp.cc @@ -3388,6 +3388,19 @@ gfc_trans_omp_clauses (stmtblock_t *block, gfc_omp_clauses *clauses, @@ -1655,6 +14181,643 @@ OMP_CLAUSE_SIZE (node) = size_zero_node; goto finalize_map_clause; } +--- a/src/gcc/genmatch.cc ++++ b/src/gcc/genmatch.cc +@@ -2568,7 +2568,8 @@ expr::gen_transform (FILE *f, int indent, const char *dest, bool gimple, + { + fprintf_indent (f, indent, "if (TREE_TYPE (_o%d[0]) != %s)\n", + depth, type); +- indent += 2; ++ fprintf_indent (f, indent + 2, "{\n"); ++ indent += 4; + } + if (opr->kind == id_base::CODE) + fprintf_indent (f, indent, "_r%d = fold_build%d_loc (loc, %s, %s", +@@ -2591,7 +2592,8 @@ expr::gen_transform (FILE *f, int indent, const char *dest, bool gimple, + } + if (*opr == CONVERT_EXPR) + { +- indent -= 2; ++ fprintf_indent (f, indent - 2, "}\n"); ++ indent -= 4; + fprintf_indent (f, indent, "else\n"); + fprintf_indent (f, indent, " _r%d = _o%d[0];\n", depth, depth); + } +--- a/src/gcc/gimple-fold.cc ++++ b/src/gcc/gimple-fold.cc +@@ -7823,12 +7823,11 @@ get_base_constructor (tree base, poly_int64_pod *bit_offset, + } + } + +-/* CTOR is CONSTRUCTOR of an array type. Fold a reference of SIZE bits +- to the memory at bit OFFSET. When non-null, TYPE is the expected +- type of the reference; otherwise the type of the referenced element +- is used instead. When SIZE is zero, attempt to fold a reference to +- the entire element which OFFSET refers to. Increment *SUBOFF by +- the bit offset of the accessed element. */ ++/* CTOR is a CONSTRUCTOR of an array or vector type. Fold a reference of SIZE ++ bits to the memory at bit OFFSET. If non-null, TYPE is the expected type of ++ the reference; otherwise the type of the referenced element is used instead. ++ When SIZE is zero, attempt to fold a reference to the entire element OFFSET ++ refers to. Increment *SUBOFF by the bit offset of the accessed element. */ + + static tree + fold_array_ctor_reference (tree type, tree ctor, +@@ -7993,13 +7992,11 @@ fold_array_ctor_reference (tree type, tree ctor, + return type ? build_zero_cst (type) : NULL_TREE; + } + +-/* CTOR is CONSTRUCTOR of an aggregate or vector. Fold a reference +- of SIZE bits to the memory at bit OFFSET. When non-null, TYPE +- is the expected type of the reference; otherwise the type of +- the referenced member is used instead. When SIZE is zero, +- attempt to fold a reference to the entire member which OFFSET +- refers to; in this case. Increment *SUBOFF by the bit offset +- of the accessed member. */ ++/* CTOR is a CONSTRUCTOR of a record or union type. Fold a reference of SIZE ++ bits to the memory at bit OFFSET. If non-null, TYPE is the expected type of ++ the reference; otherwise the type of the referenced member is used instead. ++ When SIZE is zero, attempt to fold a reference to the entire member OFFSET ++ refers to. Increment *SUBOFF by the bit offset of the accessed member. */ + + static tree + fold_nonarray_ctor_reference (tree type, tree ctor, +@@ -8011,8 +8008,7 @@ fold_nonarray_ctor_reference (tree type, tree ctor, + unsigned HOST_WIDE_INT cnt; + tree cfield, cval; + +- FOR_EACH_CONSTRUCTOR_ELT (CONSTRUCTOR_ELTS (ctor), cnt, cfield, +- cval) ++ FOR_EACH_CONSTRUCTOR_ELT (CONSTRUCTOR_ELTS (ctor), cnt, cfield, cval) + { + tree byte_offset = DECL_FIELD_OFFSET (cfield); + tree field_offset = DECL_FIELD_BIT_OFFSET (cfield); +@@ -8084,6 +8080,19 @@ fold_nonarray_ctor_reference (tree type, tree ctor, + return NULL_TREE; + + offset_int inner_offset = offset_int (offset) - bitoffset; ++ ++ /* Integral bit-fields are left-justified on big-endian targets, so ++ we must arrange for native_encode_int to start at their MSB. */ ++ if (DECL_BIT_FIELD (cfield) && INTEGRAL_TYPE_P (TREE_TYPE (cfield))) ++ { ++ if (BYTES_BIG_ENDIAN != WORDS_BIG_ENDIAN) ++ return NULL_TREE; ++ const unsigned int encoding_size ++ = GET_MODE_BITSIZE (SCALAR_INT_TYPE_MODE (TREE_TYPE (cfield))); ++ if (BYTES_BIG_ENDIAN) ++ inner_offset += encoding_size - wi::to_offset (field_size); ++ } ++ + return fold_ctor_reference (type, cval, + inner_offset.to_uhwi (), size, + from_decl, suboff); +@@ -8096,7 +8105,7 @@ fold_nonarray_ctor_reference (tree type, tree ctor, + return build_zero_cst (type); + } + +-/* CTOR is value initializing memory. Fold a reference of TYPE and ++/* CTOR is a value initializing memory. Fold a reference of TYPE and + bit size POLY_SIZE to the memory at bit POLY_OFFSET. When POLY_SIZE + is zero, attempt to fold a reference to the entire subobject + which OFFSET refers to. This is used when folding accesses to +@@ -8137,7 +8146,8 @@ fold_ctor_reference (tree type, tree ctor, const poly_uint64 &poly_offset, + } + return ret; + } +- /* For constants and byte-aligned/sized reads try to go through ++ ++ /* For constants and byte-aligned/sized reads, try to go through + native_encode/interpret. */ + if (CONSTANT_CLASS_P (ctor) + && BITS_PER_UNIT == 8 +@@ -8153,7 +8163,12 @@ fold_ctor_reference (tree type, tree ctor, const poly_uint64 &poly_offset, + if (len > 0) + return native_interpret_expr (type, buf, len); + } +- if (TREE_CODE (ctor) == CONSTRUCTOR) ++ ++ /* For constructors, try first a recursive local processing, but in any case ++ this requires the native storage order. */ ++ if (TREE_CODE (ctor) == CONSTRUCTOR ++ && !(AGGREGATE_TYPE_P (TREE_TYPE (ctor)) ++ && TYPE_REVERSE_STORAGE_ORDER (TREE_TYPE (ctor)))) + { + unsigned HOST_WIDE_INT dummy = 0; + if (!suboff) +@@ -8168,9 +8183,9 @@ fold_ctor_reference (tree type, tree ctor, const poly_uint64 &poly_offset, + ret = fold_nonarray_ctor_reference (type, ctor, offset, size, + from_decl, suboff); + +- /* Fall back to native_encode_initializer. Needs to be done +- only in the outermost fold_ctor_reference call (because it itself +- recurses into CONSTRUCTORs) and doesn't update suboff. */ ++ /* Otherwise fall back to native_encode_initializer. This may be done ++ only from the outermost fold_ctor_reference call (because it itself ++ recurses into CONSTRUCTORs and doesn't update suboff). */ + if (ret == NULL_TREE + && suboff == &dummy + && BITS_PER_UNIT == 8 +--- a/src/gcc/gimple-predicate-analysis.cc ++++ b/src/gcc/gimple-predicate-analysis.cc +@@ -2215,11 +2215,11 @@ uninit_analysis::is_use_guarded (gimple *use_stmt, basic_block use_bb, + return false; + + use_preds.simplify (use_stmt, /*is_use=*/true); ++ use_preds.normalize (use_stmt, /*is_use=*/true); + if (use_preds.is_false ()) + return true; + if (use_preds.is_true ()) + return false; +- use_preds.normalize (use_stmt, /*is_use=*/true); + + /* Try to prune the dead incoming phi edges. */ + if (!overlap (phi, opnds, visited, use_preds)) +@@ -2237,11 +2237,11 @@ uninit_analysis::is_use_guarded (gimple *use_stmt, basic_block use_bb, + return false; + + m_phi_def_preds.simplify (phi); ++ m_phi_def_preds.normalize (phi); + if (m_phi_def_preds.is_false ()) + return false; + if (m_phi_def_preds.is_true ()) + return true; +- m_phi_def_preds.normalize (phi); + } + + /* Return true if the predicate guarding the valid definition (i.e., +--- a/src/gcc/gimplify.cc ++++ b/src/gcc/gimplify.cc +@@ -6915,7 +6915,12 @@ gimplify_asm_expr (tree *expr_p, gimple_seq *pre_p, gimple_seq *post_p) + stmt = gimple_build_asm_vec (TREE_STRING_POINTER (ASM_STRING (expr)), + inputs, outputs, clobbers, labels); + +- gimple_asm_set_volatile (stmt, ASM_VOLATILE_P (expr) || noutputs == 0); ++ /* asm is volatile if it was marked by the user as volatile or ++ there are no outputs or this is an asm goto. */ ++ gimple_asm_set_volatile (stmt, ++ ASM_VOLATILE_P (expr) ++ || noutputs == 0 ++ || labels); + gimple_asm_set_input (stmt, ASM_INPUT_P (expr)); + gimple_asm_set_inline (stmt, ASM_INLINE_P (expr)); + +@@ -7154,8 +7159,10 @@ gimplify_target_expr (tree *expr_p, gimple_seq *pre_p, gimple_seq *post_p) + gimplify_and_add (init, &init_pre_p); + + /* Add a clobber for the temporary going out of scope, like +- gimplify_bind_expr. */ ++ gimplify_bind_expr. But only if we did not promote the ++ temporary to static storage. */ + if (gimplify_ctxp->in_cleanup_point_expr ++ && !TREE_STATIC (temp) + && needs_to_live_in_memory (temp)) + { + if (flag_stack_reuse == SR_ALL) +--- a/src/gcc/go/ChangeLog ++++ b/src/gcc/go/ChangeLog +@@ -1,3 +1,11 @@ ++2023-06-28 Paul E. Murphy ++ ++ Backported from master: ++ 2023-06-22 Paul E. Murphy ++ ++ * go-backend.cc [TARGET_AIX]: Rename and update usage to TARGET_AIX_OS. ++ * go-lang.cc: Likewise. ++ + 2023-04-26 Release Manager + + * GCC 13.1.0 released. +--- a/src/gcc/go/go-backend.cc ++++ b/src/gcc/go/go-backend.cc +@@ -45,8 +45,8 @@ along with GCC; see the file COPYING3. If not see + #define GO_EXPORT_SECTION_NAME ".go_export" + #endif + +-#ifndef TARGET_AIX +-#define TARGET_AIX 0 ++#ifndef TARGET_AIX_OS ++#define TARGET_AIX_OS 0 + #endif + + /* This file holds all the cases where the Go frontend needs +@@ -107,7 +107,7 @@ go_write_export_data (const char *bytes, unsigned int size) + { + gcc_assert (targetm_common.have_named_sections); + sec = get_section (GO_EXPORT_SECTION_NAME, +- TARGET_AIX ? SECTION_EXCLUDE : SECTION_DEBUG, ++ TARGET_AIX_OS ? SECTION_EXCLUDE : SECTION_DEBUG, + NULL); + } + +--- a/src/gcc/go/go-lang.cc ++++ b/src/gcc/go/go-lang.cc +@@ -39,8 +39,8 @@ along with GCC; see the file COPYING3. If not see + #include "go-c.h" + #include "go-gcc.h" + +-#ifndef TARGET_AIX +-#define TARGET_AIX 0 ++#ifndef TARGET_AIX_OS ++#define TARGET_AIX_OS 0 + #endif + + /* Language-dependent contents of a type. */ +@@ -116,9 +116,9 @@ go_langhook_init (void) + args.compiling_runtime = go_compiling_runtime; + args.debug_escape_level = go_debug_escape_level; + args.debug_escape_hash = go_debug_escape_hash; +- args.nil_check_size_threshold = TARGET_AIX ? -1 : 4096; ++ args.nil_check_size_threshold = TARGET_AIX_OS ? -1 : 4096; + args.debug_optimization = go_debug_optimization; +- args.need_eqtype = TARGET_AIX ? true : false; ++ args.need_eqtype = TARGET_AIX_OS ? true : false; + args.linemap = go_get_linemap(); + args.backend = go_get_backend(); + go_create_gogo (&args); +--- a/src/gcc/go/gofrontend/expressions.cc ++++ b/src/gcc/go/gofrontend/expressions.cc +@@ -12272,7 +12272,8 @@ Call_expression::intrinsify(Gogo* gogo, + return Runtime::make_call(code, loc, 3, a1, a2, a3); + } + } +- else if (package == "internal/abi") ++ else if (package == "internal/abi" ++ || package == "bootstrap/internal/abi") // for bootstrapping gc + { + if (is_method) + return NULL; +--- a/src/gcc/go/gofrontend/gogo.cc ++++ b/src/gcc/go/gofrontend/gogo.cc +@@ -3296,6 +3296,9 @@ class Create_function_descriptors : public Traverse + int + expression(Expression**); + ++ static bool ++ skip_descriptor(Gogo* gogo, const Named_object*); ++ + private: + Gogo* gogo_; + }; +@@ -3306,6 +3309,9 @@ class Create_function_descriptors : public Traverse + int + Create_function_descriptors::function(Named_object* no) + { ++ if (Create_function_descriptors::skip_descriptor(this->gogo_, no)) ++ return TRAVERSE_CONTINUE; ++ + if (no->is_function() + && no->func_value()->enclosing() == NULL + && !no->func_value()->is_method() +@@ -3393,6 +3399,28 @@ Create_function_descriptors::expression(Expression** pexpr) + return TRAVERSE_CONTINUE; + } + ++// The gc compiler has some special cases that it always compiles as ++// intrinsics. For those we don't want to generate a function ++// descriptor, as there will be no code for it to refer to. ++ ++bool ++Create_function_descriptors::skip_descriptor(Gogo* gogo, ++ const Named_object* no) ++{ ++ const std::string& pkgpath(no->package() == NULL ++ ? gogo->pkgpath() ++ : no->package()->pkgpath()); ++ ++ // internal/abi is the standard library package, ++ // bootstrap/internal/abi is the name used when bootstrapping the gc ++ // compiler. ++ ++ return ((pkgpath == "internal/abi" ++ || pkgpath == "bootstrap/internal/abi") ++ && (no->name() == "FuncPCABI0" ++ || no->name() == "FuncPCABIInternal")); ++} ++ + // Create function descriptors as needed. We need a function + // descriptor for all exported functions and for all functions that + // are referenced without being called. +@@ -3414,7 +3442,8 @@ Gogo::create_function_descriptors() + if (no->is_function_declaration() + && !no->func_declaration_value()->type()->is_method() + && !Linemap::is_predeclared_location(no->location()) +- && !Gogo::is_hidden_name(no->name())) ++ && !Gogo::is_hidden_name(no->name()) ++ && !Create_function_descriptors::skip_descriptor(this, no)) + fndecls.push_back(no); + } + for (std::vector::const_iterator p = fndecls.begin(); +--- a/src/gcc/ipa-sra.cc ++++ b/src/gcc/ipa-sra.cc +@@ -3074,6 +3074,8 @@ struct caller_issues + cgraph_node *candidate; + /* There is a thunk among callers. */ + bool thunk; ++ /* Set if there is at least one caller that is OK. */ ++ bool there_is_one; + /* Call site with no available information. */ + bool unknown_callsite; + /* Call from outside the candidate's comdat group. */ +@@ -3116,6 +3118,8 @@ check_for_caller_issues (struct cgraph_node *node, void *data) + + if (csum->m_bit_aligned_arg) + issues->bit_aligned_aggregate_argument = true; ++ ++ issues->there_is_one = true; + } + return false; + } +@@ -3170,6 +3174,13 @@ check_all_callers_for_issues (cgraph_node *node) + for (unsigned i = 0; i < param_count; i++) + (*ifs->m_parameters)[i].split_candidate = false; + } ++ if (!issues.there_is_one) ++ { ++ if (dump_file && (dump_flags & TDF_DETAILS)) ++ fprintf (dump_file, "There is no call to %s that we can modify. " ++ "Disabling all modifications.\n", node->dump_name ()); ++ return true; ++ } + return false; + } + +--- a/src/gcc/ira-costs.cc ++++ b/src/gcc/ira-costs.cc +@@ -2009,6 +2009,16 @@ find_costs_and_classes (FILE *dump_file) + ira_assert (regno_aclass[i] != NO_REGS + && ira_reg_allocno_class_p[regno_aclass[i]]); + } ++ if (pic_offset_table_rtx != NULL ++ && i == (int) REGNO (pic_offset_table_rtx)) ++ { ++ /* For some targets, integer pseudos can be assigned to fp ++ regs. As we don't want reload pic offset table pseudo, we ++ should avoid using non-integer regs. */ ++ regno_aclass[i] ++ = ira_reg_class_intersect[regno_aclass[i]][GENERAL_REGS]; ++ alt_class = ira_reg_class_intersect[alt_class][GENERAL_REGS]; ++ } + if ((new_class + = (reg_class) (targetm.ira_change_pseudo_allocno_class + (i, regno_aclass[i], best))) != regno_aclass[i]) +--- a/src/gcc/lto-cgraph.cc ++++ b/src/gcc/lto-cgraph.cc +@@ -1020,7 +1020,7 @@ output_symtab (void) + When doing WPA we must output every asm just once. Since we do not partition asm + nodes at all, output them to first output. This is kind of hack, but should work + well. */ +- if (!asm_nodes_output) ++ if (!asm_nodes_output && !lto_stream_offload_p) + { + asm_nodes_output = true; + lto_output_toplevel_asms (); +--- a/src/gcc/m2/ChangeLog ++++ b/src/gcc/m2/ChangeLog +@@ -1,3 +1,12 @@ ++2023-07-03 Iain Sandoe ++ ++ Backported from master: ++ 2023-06-30 Iain Sandoe ++ ++ PR testsuite/108835 ++ * gm2-libs/RTint.mod: Do not use NIL timeout setting on select, ++ test failures sequentially, finishing on the first success. ++ + 2023-04-26 Release Manager + + * GCC 13.1.0 released. +--- a/src/gcc/m2/gm2-libs/RTint.mod ++++ b/src/gcc/m2/gm2-libs/RTint.mod +@@ -441,6 +441,10 @@ END ExcludeVector ; + + PROCEDURE AddFd (VAR set: SetOfFd; VAR max: INTEGER; fd: INTEGER) ; + BEGIN ++ IF (fd<0) ++ THEN ++ RETURN ++ END ; + max := Max (fd, max) ; + IF set = NIL + THEN +@@ -667,6 +671,7 @@ PROCEDURE Listen (untilInterrupt: BOOLEAN; + VAR + found : BOOLEAN ; + result : INTEGER ; ++ zero, + after, + b4, + timeval: Timeval ; +@@ -722,14 +727,14 @@ BEGIN + THEN + SetTime (timeval, 0, 0) + END ; +- IF untilInterrupt AND (inSet=NIL) AND (outSet=NIL) AND (NOT found) ++ IF untilInterrupt AND (((inSet=NIL) AND (outSet=NIL)) OR (maxFd=-1)) AND (NOT found) + THEN + Halt ('deadlock found, no more processes to run and no interrupts active', + __FILE__, __FUNCTION__, __LINE__) + END ; + (* printf('timeval = 0x%x\n', timeval) ; *) + (* printf('}\n') ; *) +- IF (NOT found) AND (maxFd=-1) AND (inSet=NIL) AND (outSet=NIL) ++ IF (NOT found) AND (maxFd=-1) + THEN + (* no file descriptors to be selected upon. *) + timeval := KillTime (timeval) ; +@@ -738,6 +743,7 @@ BEGIN + ELSE + GetTime (timeval, sec, micro) ; + Assert (micro < Microseconds) ; ++ zero := InitTime (0, 0) ; + b4 := InitTime (0, 0) ; + after := InitTime (0, 0) ; + result := GetTimeOfDay (b4) ; +@@ -754,26 +760,54 @@ BEGIN + THEN + printf ("select (.., .., .., %u.%06u)\n", sec, micro) + END ; +- result := select (maxFd+1, inSet, outSet, NIL, timeval) ; ++ IF maxFd<0 ++ THEN ++ result := select (0, NIL, NIL, NIL, timeval) ++ ELSE ++ result := select (maxFd+1, inSet, outSet, NIL, timeval) ++ END ; + IF result=-1 + THEN +- perror ("select") ; +- result := select (maxFd+1, inSet, outSet, NIL, NIL) ; +- IF result=-1 ++ IF Debugging + THEN +- perror ("select timeout argument is faulty") ++ perror ("select failed : ") ; + END ; +- result := select (maxFd+1, inSet, NIL, NIL, timeval) ; +- IF result=-1 ++ result := select (maxFd+1, inSet, outSet, NIL, zero) ; ++ IF result#-1 + THEN +- perror ("select output fd argument is faulty") +- END ; +- result := select (maxFd+1, NIL, outSet, NIL, timeval) ; +- IF result=-1 +- THEN +- perror ("select input fd argument is faulty") ++ GetTime (timeval, sec, micro) ; ++ IF Debugging ++ THEN ++ printf ("(nfds : %d timeval: %u.%06u) : \n", maxFd, sec, micro) ; ++ END ; ++ perror ("select timeout argument was faulty : ") + ELSE +- perror ("select maxFD+1 argument is faulty") ++ result := select (maxFd+1, inSet, NIL, NIL, timeval) ; ++ IF result#-1 ++ THEN ++ perror ("select output fd argument was faulty : ") ++ ELSE ++ result := select (maxFd+1, NIL, outSet, NIL, timeval) ; ++ IF result#-1 ++ THEN ++ perror ("select input fd argument was faulty : ") ++ ELSE ++ IF maxFd=-1 ++ THEN ++ result := select (0, NIL, NIL, NIL, timeval) ; ++ IF result=-1 ++ THEN ++ IF Debugging ++ THEN ++ perror ("select does not accept nfds == 0 ") ; ++ END ; ++ result := 0 ++ END ++ ELSE ++ perror ("select maxFD+1 argument was faulty : ") ; ++ END ++ END ++ END + END + END + UNTIL result#-1 +@@ -785,6 +819,10 @@ BEGIN + THEN + timeval := KillTime (timeval) + END ; ++ IF zero#NIL ++ THEN ++ zero := KillTime (zero) ++ END ; + IF after#NIL + THEN + after := KillTime (after) +--- a/src/gcc/match.pd ++++ b/src/gcc/match.pd +@@ -1853,7 +1853,7 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) + /* (x | CST1) & CST2 -> (x & CST2) | (CST1 & CST2) */ + (simplify + (bit_and (bit_ior @0 CONSTANT_CLASS_P@1) CONSTANT_CLASS_P@2) +- (bit_ior (bit_and @0 @2) (bit_and @1 @2))) ++ (bit_ior (bit_and @0 @2) (bit_and! @1 @2))) + + /* Combine successive equal operations with constants. */ + (for bitop (bit_and bit_ior bit_xor) +@@ -1862,7 +1862,7 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) + (if (!CONSTANT_CLASS_P (@0)) + /* This is the canonical form regardless of whether (bitop @1 @2) can be + folded to a constant. */ +- (bitop @0 (bitop @1 @2)) ++ (bitop @0 (bitop! @1 @2)) + /* In this case we have three constants and (bitop @0 @1) doesn't fold + to a constant. This can happen if @0 or @1 is a POLY_INT_CST and if + the values involved are such that the operation can't be decided at +@@ -1922,9 +1922,15 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) + + (match zero_one_valued_p + @0 +- (if (INTEGRAL_TYPE_P (type) && tree_nonzero_bits (@0) == 1))) ++ (if (INTEGRAL_TYPE_P (type) ++ && (TYPE_UNSIGNED (type) ++ || TYPE_PRECISION (type) > 1) ++ && tree_nonzero_bits (@0) == 1))) + (match zero_one_valued_p +- truth_valued_p@0) ++ truth_valued_p@0 ++ (if (INTEGRAL_TYPE_P (type) ++ && (TYPE_UNSIGNED (type) ++ || TYPE_PRECISION (type) > 1)))) + + /* Transform { 0 or 1 } * { 0 or 1 } into { 0 or 1 } & { 0 or 1 }. */ + (simplify +@@ -2923,13 +2929,13 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) + forever if something doesn't simplify into a constant. */ + (if (!CONSTANT_CLASS_P (@0)) + (if (outer_op == PLUS_EXPR) +- (plus (view_convert @0) (inner_op @2 (view_convert @1))) +- (minus (view_convert @0) (neg_inner_op @2 (view_convert @1))))) ++ (plus (view_convert @0) (inner_op! @2 (view_convert @1))) ++ (minus (view_convert @0) (neg_inner_op! @2 (view_convert @1))))) + (if (!ANY_INTEGRAL_TYPE_P (TREE_TYPE (@0)) + || TYPE_OVERFLOW_WRAPS (TREE_TYPE (@0))) + (if (outer_op == PLUS_EXPR) +- (view_convert (plus @0 (inner_op (view_convert @2) @1))) +- (view_convert (minus @0 (neg_inner_op (view_convert @2) @1)))) ++ (view_convert (plus @0 (inner_op! (view_convert @2) @1))) ++ (view_convert (minus @0 (neg_inner_op! (view_convert @2) @1)))) + /* If the constant operation overflows we cannot do the transform + directly as we would introduce undefined overflow, for example + with (a - 1) + INT_MIN. */ +@@ -2960,10 +2966,10 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) + /* If all 3 captures are CONSTANT_CLASS_P, punt, as we might recurse + forever if something doesn't simplify into a constant. */ + (if (!CONSTANT_CLASS_P (@0)) +- (minus (outer_op (view_convert @1) @2) (view_convert @0))) ++ (minus (outer_op! (view_convert @1) @2) (view_convert @0))) + (if (!ANY_INTEGRAL_TYPE_P (TREE_TYPE (@0)) + || TYPE_OVERFLOW_WRAPS (TREE_TYPE (@0))) +- (view_convert (minus (outer_op @1 (view_convert @2)) @0)) ++ (view_convert (minus (outer_op! @1 (view_convert @2)) @0)) + (if (types_match (type, @0) && !TYPE_OVERFLOW_SANITIZED (type)) + (with { tree cst = const_binop (outer_op, type, @1, @2); } + (if (cst && !TREE_OVERFLOW (cst)) +@@ -2979,10 +2985,10 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) + /* If all 3 captures are CONSTANT_CLASS_P, punt, as we might recurse + forever if something doesn't simplify into a constant. */ + (if (!CONSTANT_CLASS_P (@0)) +- (plus (view_convert @0) (minus @1 (view_convert @2)))) ++ (plus (view_convert @0) (minus! @1 (view_convert @2)))) + (if (!ANY_INTEGRAL_TYPE_P (TREE_TYPE (@0)) + || TYPE_OVERFLOW_WRAPS (TREE_TYPE (@0))) +- (view_convert (plus @0 (minus (view_convert @1) @2))) ++ (view_convert (plus @0 (minus! (view_convert @1) @2))) + (if (types_match (type, @0) && !TYPE_OVERFLOW_SANITIZED (type)) + (with { tree cst = const_binop (MINUS_EXPR, type, @1, @2); } + (if (cst && !TREE_OVERFLOW (cst)) +@@ -4061,19 +4067,19 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) + int inside_ptr = POINTER_TYPE_P (inside_type); + int inside_float = FLOAT_TYPE_P (inside_type); + int inside_vec = VECTOR_TYPE_P (inside_type); +- unsigned int inside_prec = TYPE_PRECISION (inside_type); ++ unsigned int inside_prec = element_precision (inside_type); + int inside_unsignedp = TYPE_UNSIGNED (inside_type); + int inter_int = INTEGRAL_TYPE_P (inter_type); + int inter_ptr = POINTER_TYPE_P (inter_type); + int inter_float = FLOAT_TYPE_P (inter_type); + int inter_vec = VECTOR_TYPE_P (inter_type); +- unsigned int inter_prec = TYPE_PRECISION (inter_type); ++ unsigned int inter_prec = element_precision (inter_type); + int inter_unsignedp = TYPE_UNSIGNED (inter_type); + int final_int = INTEGRAL_TYPE_P (type); + int final_ptr = POINTER_TYPE_P (type); + int final_float = FLOAT_TYPE_P (type); + int final_vec = VECTOR_TYPE_P (type); +- unsigned int final_prec = TYPE_PRECISION (type); ++ unsigned int final_prec = element_precision (type); + int final_unsignedp = TYPE_UNSIGNED (type); + } + (switch --- a/src/gcc/po/ChangeLog +++ b/src/gcc/po/ChangeLog @@ -1,3 +1,13 @@ @@ -235232,9 +248395,2169 @@ #, fuzzy #~ msgid "operand is not a condition code, invalid operand code 'I'" #~ msgstr "運算元並非條件編碼，無效的運算元編碼『Y』" +--- a/src/gcc/range-op-float.cc ++++ b/src/gcc/range-op-float.cc +@@ -255,7 +255,7 @@ maybe_isnan (const frange &op1, const frange &op2) + // Floating version of relop_early_resolve that takes into account NAN + // and -ffinite-math-only. + +-inline bool ++static inline bool + frelop_early_resolve (irange &r, tree type, + const frange &op1, const frange &op2, + relation_trio rel, relation_kind my_rel) +@@ -272,7 +272,7 @@ frelop_early_resolve (irange &r, tree type, + + // Set VALUE to its next real value, or INF if the operation overflows. + +-inline void ++void + frange_nextafter (enum machine_mode mode, + REAL_VALUE_TYPE &value, + const REAL_VALUE_TYPE &inf) +@@ -2878,7 +2878,7 @@ namespace selftest + + // Build an frange from string endpoints. + +-inline frange ++static inline frange + frange_float (const char *lb, const char *ub, tree type = float_type_node) + { + REAL_VALUE_TYPE min, max; +--- a/src/gcc/rust/ChangeLog ++++ b/src/gcc/rust/ChangeLog +@@ -1,3 +1,11 @@ ++2023-06-28 Paul E. Murphy ++ ++ Backported from master: ++ 2023-06-22 Paul E. Murphy ++ ++ * rust-object-export.cc [TARGET_AIX]: Rename and update usage to ++ TARGET_AIX_OS. ++ + 2023-04-26 Release Manager + + * GCC 13.1.0 released. +--- a/src/gcc/rust/rust-object-export.cc ++++ b/src/gcc/rust/rust-object-export.cc +@@ -46,8 +46,8 @@ + #define RUST_EXPORT_SECTION_NAME ".rust_export" + #endif + +-#ifndef TARGET_AIX +-#define TARGET_AIX 0 ++#ifndef TARGET_AIX_OS ++#define TARGET_AIX_OS 0 + #endif + + /* Return whether or not GCC has reported any errors. */ +@@ -91,7 +91,7 @@ rust_write_export_data (const char *bytes, unsigned int size) + { + gcc_assert (targetm_common.have_named_sections); + sec = get_section (RUST_EXPORT_SECTION_NAME, +- TARGET_AIX ? SECTION_EXCLUDE : SECTION_DEBUG, NULL); ++ TARGET_AIX_OS ? SECTION_EXCLUDE : SECTION_DEBUG, NULL); + } + + switch_to_section (sec); --- a/src/gcc/testsuite/ChangeLog +++ b/src/gcc/testsuite/ChangeLog -@@ -1,3 +1,209 @@ +@@ -1,3 +1,2304 @@ ++2023-07-10 Xi Ruoyao ++ ++ Backported from master: ++ 2023-07-10 Xi Ruoyao ++ ++ PR tree-optimization/110557 ++ * g++.dg/vect/pr110557.cc: New test. ++ ++2023-07-08 Harald Anlauf ++ ++ Backported from master: ++ 2023-07-08 Harald Anlauf ++ ++ PR fortran/110585 ++ * gfortran.dg/findloc_9.f90: New test. ++ ++2023-07-07 Iain Buclaw ++ ++ Backported from master: ++ 2023-07-07 Iain Buclaw ++ ++ PR d/108842 ++ * gdc.dg/pr98277.d: Add more tests. ++ * gdc.dg/pr108842.d: New test. ++ ++2023-07-07 Richard Biener ++ ++ Backported from master: ++ 2023-07-06 Richard Biener ++ ++ PR tree-optimization/110556 ++ * gcc.dg/torture/pr110556.c: New testcase. ++ ++2023-07-07 Richard Biener ++ ++ Backported from master: ++ 2023-07-06 Richard Biener ++ ++ PR tree-optimization/110515 ++ * g++.dg/opt/pr110515.C: New testcase. ++ ++2023-07-07 Richard Biener ++ ++ Backported from master: ++ 2023-06-26 Richard Biener ++ ++ PR tree-optimization/110381 ++ * gcc.dg/vect/pr110381.c: New testcase. ++ ++2023-07-05 Michael Meissner ++ ++ Backported from master: ++ 2023-06-23 Michael Meissner ++ Aaron Sawdey ++ ++ PR target/105325 ++ * g++.target/powerpc/pr105325.C: New test. ++ * gcc.target/powerpc/fusion-p10-ldcmpi.c: Update insn counts. ++ ++2023-07-05 Richard Biener ++ ++ Backported from master: ++ 2023-07-04 Richard Biener ++ ++ PR tree-optimization/110228 ++ * gcc.dg/torture/pr110228.c: New testcase. ++ * gcc.dg/uninit-pr101912.c: Un-XFAIL. ++ ++2023-07-03 Eric Botcazou ++ ++ * gcc.c-torture/execute/20230630-1.c: New test. ++ * gcc.c-torture/execute/20230630-2.c: Likewise. ++ * gcc.c-torture/execute/20230630-3.c: Likewise ++ * gcc.c-torture/execute/20230630-4.c: Likewise ++ ++2023-07-02 Iain Buclaw ++ ++ Backported from master: ++ 2023-07-02 Iain Buclaw ++ ++ * gdc.dg/Wbuiltin_declaration_mismatch2.d: Fix failed tests. ++ ++2023-07-02 Iain Buclaw ++ ++ Backported from master: ++ 2023-07-02 Iain Buclaw ++ ++ PR d/108962 ++ * gdc.dg/pr108962.d: New test. ++ ++2023-07-02 Iain Buclaw ++ ++ Backported from master: ++ 2023-07-02 Iain Buclaw ++ ++ PR d/110516 ++ * gdc.dg/torture/pr110516a.d: New test. ++ * gdc.dg/torture/pr110516b.d: New test. ++ ++2023-07-01 Iain Buclaw ++ ++ Backported from master: ++ 2023-07-01 Iain Buclaw ++ ++ PR d/110514 ++ * gdc.dg/pr110514a.d: New test. ++ * gdc.dg/pr110514b.d: New test. ++ * gdc.dg/pr110514c.d: New test. ++ * gdc.dg/pr110514d.d: New test. ++ ++2023-07-01 Iain Buclaw ++ ++ Backported from master: ++ 2023-07-01 Iain Buclaw ++ ++ PR d/110471 ++ * gdc.dg/pr110471a.d: New test. ++ * gdc.dg/pr110471b.d: New test. ++ * gdc.dg/pr110471c.d: New test. ++ ++2023-07-01 Patrick Palka ++ ++ Backported from master: ++ 2023-06-29 Patrick Palka ++ ++ PR c++/110468 ++ * g++.dg/cpp0x/noexcept79.C: New test. ++ ++2023-07-01 Patrick Palka ++ ++ Backported from master: ++ 2023-06-29 Patrick Palka ++ ++ PR c++/110463 ++ * g++.dg/cpp0x/constexpr-mutable6.C: New test. ++ ++2023-06-29 Marek Polacek ++ ++ Backported from master: ++ 2023-06-29 Marek Polacek ++ ++ * gcc.dg/plugin/crash-test-ice-sarif.c: Use -fno-report-bug. Adjust ++ scan-sarif-file. ++ * gcc.dg/plugin/crash-test-ice-stderr.c: Use -fno-report-bug. ++ * gcc.dg/plugin/crash-test-write-though-null-sarif.c: Use ++ -fno-report-bug. Adjust scan-sarif-file. ++ * gcc.dg/plugin/crash-test-write-though-null-stderr.c: Use ++ -fno-report-bug. ++ ++2023-06-29 Marek Polacek ++ ++ Backported from master: ++ 2023-06-29 Marek Polacek ++ ++ * gcc.target/i386/pr104610.c: Use -fno-stack-protector. ++ * gcc.target/i386/pr69482-1.c: Likewise. ++ ++2023-06-29 Harald Anlauf ++ ++ Backported from master: ++ 2023-06-13 Harald Anlauf ++ Mikael Morin ++ ++ PR fortran/86277 ++ * gfortran.dg/zero_sized_14.f90: New test. ++ * gfortran.dg/zero_sized_15.f90: New test. ++ ++2023-06-29 Harald Anlauf ++ ++ Backported from master: ++ 2023-04-19 Harald Anlauf ++ ++ PR testsuite/83904 ++ PR fortran/100297 ++ * gfortran.dg/allocatable_function_1.f90: Use "__builtin_free " ++ instead of the naive "free". ++ * gfortran.dg/reshape_8.f90: Extend pattern from a simple "data". ++ ++2023-06-29 liuhongt ++ ++ * gcc.target/i386/pr110309.c: New test. ++ ++2023-06-28 Hongyu Wang ++ ++ Backported from master: ++ 2023-06-26 Hongyu Wang ++ ++ * gcc.target/i386/mvc17.c: New test. ++ ++2023-06-28 Iain Buclaw ++ ++ Backported from master: ++ 2023-06-28 Iain Buclaw ++ ++ PR d/106977 ++ PR target/110406 ++ * gdc.dg/torture/pr110406.d: New test. ++ ++2023-06-28 liuhongt ++ ++ * gcc.target/i386/avx-vzeroupper-29.c: New testcase. ++ * gcc.target/i386/avx-vzeroupper-12.c: Adjust testcase. ++ * gcc.target/i386/avx-vzeroupper-7.c: Ditto. ++ * gcc.target/i386/avx-vzeroupper-9.c: Ditto. ++ ++2023-06-28 liuhongt ++ ++ * gcc.target/i386/bf16_short_warn.c: New test. ++ ++2023-06-27 Andrew Pinski ++ ++ Backported from master: ++ 2023-06-27 Andrew Pinski ++ ++ PR middle-end/110420 ++ PR middle-end/103979 ++ PR middle-end/98619 ++ * gcc.c-torture/compile/asmgoto-6.c: New test. ++ ++2023-06-27 Martin Jambor ++ ++ Backported from master: ++ 2023-06-27 Martin Jambor ++ ++ PR ipa/110276 ++ * gcc.dg/ipa/pr110276.c: New test. ++ ++2023-06-26 Iain Buclaw ++ ++ Backported from master: ++ 2023-06-26 Iain Buclaw ++ ++ PR d/110359 ++ * gdc.dg/pr110359.d: New test. ++ ++2023-06-26 Iain Buclaw ++ ++ PR d/110113 ++ * gdc.test/compilable/test23978.d: New test. ++ ++2023-06-23 Jason Merrill ++ ++ PR c++/110102 ++ * g++.dg/cpp0x/initlist-opt1.C: New test. ++ ++2023-06-23 Jason Merrill ++ ++ DR 2735 ++ PR c++/109247 ++ * g++.dg/cpp0x/initlist-explicit3.C: New test. ++ ++2023-06-23 Richard Biener ++ ++ Backported from master: ++ 2023-06-19 Richard Biener ++ ++ PR tree-optimization/110298 ++ * gcc.dg/torture/pr110298.c: New testcase. ++ ++2023-06-23 Richard Biener ++ ++ Backported from master: ++ 2023-06-20 Richard Biener ++ ++ PR debug/110295 ++ * g++.dg/debug/pr110295.C: New testcase. ++ ++2023-06-23 Richard Biener ++ ++ Backported from master: ++ 2023-06-06 Richard Biener ++ ++ PR middle-end/110055 ++ * g++.dg/warn/Wdangling-pointer-pr110055.C: New testcase. ++ ++2023-06-20 Alex Coplan ++ ++ Backported from master: ++ 2023-06-07 Alex Coplan ++ ++ PR target/110132 ++ * lib/target-supports.exp (check_effective_target_aarch64_asm_FUNC_ok): ++ Extend to ls64. ++ * g++.target/aarch64/acle/acle.exp: New. ++ * g++.target/aarch64/acle/ls64.C: New test. ++ * g++.target/aarch64/acle/ls64_lto.C: New test. ++ * gcc.target/aarch64/acle/ls64_lto.c: New test. ++ * gcc.target/aarch64/acle/pr110132.c: New test. ++ ++2023-06-20 Alex Coplan ++ ++ Backported from master: ++ 2023-06-07 Alex Coplan ++ ++ PR target/110100 ++ * gcc.target/aarch64/acle/pr110100.c: New test. ++ ++2023-06-20 Kewen Lin ++ ++ Backported from master: ++ 2023-06-13 Kewen Lin ++ ++ PR testsuite/110230 ++ PR target/109932 ++ * gcc.target/powerpc/pr109932-1.c: Adjust with int128 effective target. ++ * gcc.target/powerpc/pr109932-2.c: Ditto. ++ ++2023-06-20 Kewen Lin ++ ++ Backported from master: ++ 2023-06-12 Kewen Lin ++ ++ PR target/109932 ++ * gcc.target/powerpc/pr109932-1.c: New test. ++ * gcc.target/powerpc/pr109932-2.c: New test. ++ ++2023-06-20 Kewen Lin ++ ++ Backported from master: ++ 2023-06-12 Kewen Lin ++ ++ PR target/110011 ++ * gcc.target/powerpc/pr110011.c: New test. ++ ++2023-06-16 Vladimir N. Makarov ++ ++ * gcc.target/sparc/pr109541.c: New. ++ ++2023-06-14 liuhongt ++ ++ * gcc.target/i386/pr110227.c: New test. ++ ++2023-06-10 Georg-Johann Lay ++ ++ PR target/109650 ++ Backport from 2023-05-10 master r14-1688. ++ * gcc.target/avr/torture/pr109650-1.c: New test. ++ * gcc.target/avr/torture/pr109650-2.c: New test. ++ ++2023-06-09 Andrew Pinski ++ ++ Backported from master: ++ 2023-06-09 Andrew Pinski ++ ++ PR tree-optimization/110165 ++ PR tree-optimization/110166 ++ * gcc.c-torture/execute/pr110165-1.c: New test. ++ * gcc.c-torture/execute/pr110166-1.c: New test. ++ ++2023-06-09 Iain Sandoe ++ ++ Backported from master: ++ 2023-06-02 Iain Sandoe ++ ++ PR target/110044 ++ * gcc.target/powerpc/darwin-abi-13-0.c: New test. ++ * gcc.target/powerpc/darwin-abi-13-1.c: New test. ++ * gcc.target/powerpc/darwin-abi-13-2.c: New test. ++ * gcc.target/powerpc/darwin-structs-0.h: New test. ++ ++2023-06-09 liuhongt ++ ++ * gcc.target/i386/pr110108-2.c: New test. ++ ++2023-06-08 Kyrylo Tkachov ++ ++ Backported from master: ++ 2023-05-24 Kyrylo Tkachov ++ ++ PR target/109939 ++ * gcc.target/arm/pr109939.c: New test. ++ ++2023-06-07 Alex Coplan ++ ++ Backported from master: ++ 2023-05-25 Alex Coplan ++ ++ PR target/109800 ++ * gcc.target/arm/pure-code/pr109800.c: New test. ++ ++2023-06-05 Iain Buclaw ++ ++ Backported from master: ++ 2023-06-05 Iain Buclaw ++ ++ * gdc.dg/Wmismatched_enum.d: New test. ++ ++2023-06-03 Steve Kargl ++ ++ Backported from master: ++ 2023-06-02 Steve Kargl ++ ++ PR fortran/100607 ++ * gfortran.dg/select_rank_6.f90: New test. ++ ++2023-05-30 Christophe Lyon ++ ++ Backported from master: ++ 2023-05-30 Christophe Lyon ++ ++ * gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c: ++ Support both definitions of int32_t. ++ ++2023-05-29 Juzhe-Zhong ++ ++ Backported from master: ++ 2023-04-21 Juzhe-Zhong ++ ++ PR target/109547 ++ * gcc.target/riscv/rvv/vsetvl/pr109547.c: New. ++ * gcc.target/riscv/rvv/vsetvl/vsetvl-17.c: Update scan ++ condition. ++ ++2023-05-25 Georg-Johann Lay ++ ++ PR target/82931 ++ * gcc.target/avr/pr82931.c: New test. ++ ++2023-05-23 Eric Botcazou ++ ++ * gnat.dg/opt101.adb: New test. ++ * gnat.dg/opt101_pkg.ads: New helper. ++ ++2023-05-22 Jakub Jelinek ++ ++ Backported from master: ++ 2023-05-21 Jakub Jelinek ++ ++ PR tree-optimization/109505 ++ * gcc.target/aarch64/sve/pr109505.c: New test. ++ ++2023-05-20 Triffid Hunter ++ ++ PR target/105753 ++ Backport from 2023-05-20 https://gcc.gnu.org/r14-1016 ++ * gcc.target/avr/torture/pr105753.c: New test. ++ ++2023-05-19 Patrick Palka ++ ++ Backported from master: ++ 2023-05-16 Patrick Palka ++ ++ PR c++/109871 ++ * g++.dg/cpp2a/desig27.C: New test. ++ ++2023-05-19 Patrick Palka ++ ++ Backported from master: ++ 2023-05-15 Patrick Palka ++ ++ * g++.dg/cpp23/feat-cxx2b.C: Test __cpp_auto_cast. ++ ++2023-05-18 Harald Anlauf ++ ++ Backported from master: ++ 2023-05-15 Harald Anlauf ++ ++ PR fortran/109846 ++ * gfortran.dg/ptr-func-5.f90: New test. ++ ++2023-05-18 Harald Anlauf ++ ++ Backported from master: ++ 2023-05-05 Harald Anlauf ++ ++ PR fortran/109641 ++ * gfortran.dg/overload_5.f90: New test. ++ ++2023-05-18 Stam Markianos-Wright ++ ++ * gcc.target/arm/mve/intrinsics/srshr.c: Update shift value. ++ * gcc.target/arm/mve/intrinsics/srshrl.c: Update shift value. ++ * gcc.target/arm/mve/intrinsics/uqshl.c: Update shift value. ++ * gcc.target/arm/mve/intrinsics/uqshll.c: Update shift value. ++ * gcc.target/arm/mve/intrinsics/urshr.c: Update shift value. ++ * gcc.target/arm/mve/intrinsics/urshrl.c: Update shift value. ++ * gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: Update to ubfx. ++ * gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: Update to ubfx. ++ * gcc.target/arm/mve/intrinsics/vadciq_s32.c: Update to ubfx. ++ * gcc.target/arm/mve/intrinsics/vadciq_u32.c: Update to ubfx. ++ * gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: Update to ubfx. ++ * gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: Update to ubfx. ++ * gcc.target/arm/mve/intrinsics/vadcq_s32.c: Update to ubfx. ++ * gcc.target/arm/mve/intrinsics/vadcq_u32.c: Update to ubfx. ++ * gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: Update to ubfx. ++ * gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: Update to ubfx. ++ * gcc.target/arm/mve/intrinsics/vsbciq_s32.c: Update to ubfx. ++ * gcc.target/arm/mve/intrinsics/vsbciq_u32.c: Update to ubfx. ++ * gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: Update to ubfx. ++ * gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: Update to ubfx. ++ * gcc.target/arm/mve/intrinsics/vsbcq_s32.c: Update to ubfx. ++ * gcc.target/arm/mve/intrinsics/vsbcq_u32.c: Update to ubfx. ++ * gcc.target/arm/mve/mve_const_shifts.c: New test. ++ ++2023-05-18 Stam Markianos-Wright ++ ++ PR target/109697 ++ * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c: XFAIL check. ++ * gcc.target/arm/mve/pr108177-1.c: Relax registers. ++ * gcc.target/arm/mve/pr108177-10.c: Relax registers. ++ * gcc.target/arm/mve/pr108177-11.c: Relax registers. ++ * gcc.target/arm/mve/pr108177-12.c: Relax registers. ++ * gcc.target/arm/mve/pr108177-13.c: Relax registers. ++ * gcc.target/arm/mve/pr108177-13-run.c: use mve_fp ++ * gcc.target/arm/mve/pr108177-14.c: Relax registers. ++ * gcc.target/arm/mve/pr108177-14-run.c: use mve_fp ++ * gcc.target/arm/mve/pr108177-2.c: Relax registers. ++ * gcc.target/arm/mve/pr108177-3.c: Relax registers. ++ * gcc.target/arm/mve/pr108177-4.c: Relax registers. ++ * gcc.target/arm/mve/pr108177-5.c: Relax registers. ++ * gcc.target/arm/mve/pr108177-6.c: Relax registers. ++ * gcc.target/arm/mve/pr108177-7.c: Relax registers. ++ * gcc.target/arm/mve/pr108177-8.c: Relax registers. ++ * gcc.target/arm/mve/pr108177-9.c: Relax registers. ++ ++2023-05-18 Stam Markianos-Wright ++ ++ * gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vaddq_m.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vaddq_n.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u8.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vddupq_n_u16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vddupq_n_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vddupq_n_u8.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u8.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u8.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vidupq_n_u16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vidupq_n_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vidupq_n_u8.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u8.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u8.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_s64.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_u64.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_s64.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_u64.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_s64.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_u64.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_s64.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_u64.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_f16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_f16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_f16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_f16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_f32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_s32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_f32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_s32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_f32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_s32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_f32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_s32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset_p.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vmaxnmavq_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vminnmavq_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vminnmavq_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vminnmavq_p_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vminnmavq_p_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vminnmvq_p_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vminnmvq_p_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vsetq_lane_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vsetq_lane_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_n_f32-1.c: Removed. ++ ++2023-05-18 Stam Markianos-Wright ++ ++ * gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c: Add testcases. ++ * gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c: Add testcases. ++ ++2023-05-18 Stam Markianos-Wright ++ ++ * gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c: New. ++ ++2023-05-18 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/asrl.c: Use ++ check-function-bodies instead of scan-assembler checks. Use ++ extern "C" for C++ testing. ++ * gcc.target/arm/mve/intrinsics/lsll.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/sqrshr.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/sqshl.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/sqshll.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/srshr.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/srshrl.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/uqrshl.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/uqrshll_sat48.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/uqshl.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/uqshll.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/urshr.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/urshrl.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vadciq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vadciq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vadcq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vadcq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vctp16q.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vctp16q_m.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vctp32q.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vctp32q_m.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vctp64q.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vctp64q_m.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vctp8q.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vctp8q_m.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmaq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmaq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmsq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmsq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavxq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavxq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovlbq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovlbq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovlbq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovlbq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovltq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovltq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovltq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovltq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovnbq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovnbq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovnbq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovnbq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovntq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovntq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovntq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovntq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vpnot.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vpselq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vpselq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vpselq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vpselq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vpselq_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vpselq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vpselq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vpselq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vpselq_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vpselq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovntq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovntq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovntq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovntq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev16q_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev16q_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev32q_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev32q_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev32q_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev32q_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev32q_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndaq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndaq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndmq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndmq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndnq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndnq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndpq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndpq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndxq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndxq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsbciq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsbciq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsbcq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsbcq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlcq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlcq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlcq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlcq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlcq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlcq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_r_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_r_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_r_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_r_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_r_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_r_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsliq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsliq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsliq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsliq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsliq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsliq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsriq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsriq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsriq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsriq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsriq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsriq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_p_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_p_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_p_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_p_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vstrwq_f32.c: Use ++ check-function-bodies instead of scan-assembler checks. Use ++ extern "C" for C++ testing. ++ * gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_u32.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vld1q_f16.c: Use ++ check-function-bodies instead of scan-assembler checks. Use ++ extern "C" for C++ testing. ++ * gcc.target/arm/mve/intrinsics/vld1q_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld1q_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld1q_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld1q_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld1q_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld1q_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld1q_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld1q_z_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld1q_z_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld1q_z_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld1q_z_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld1q_z_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld1q_z_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld1q_z_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld1q_z_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld4q_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld4q_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld4q_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld4q_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld4q_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld4q_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld4q_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld4q_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst2q_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst2q_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst2q_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst2q_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst2q_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst2q_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst2q_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst2q_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst4q_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst4q_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst4q_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst4q_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst4q_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst4q_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst4q_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst4q_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_u32.c: Likewise. ++ ++2023-05-17 Jakub Jelinek ++ ++ Backported from master: ++ 2023-05-17 Jakub Jelinek ++ ++ PR c++/109884 ++ * c-c++-common/pr109884.c: New test. ++ ++2023-05-17 Jakub Jelinek ++ ++ Backported from master: ++ 2023-05-17 Jakub Jelinek ++ ++ PR c++/109868 ++ * g++.dg/init/pr109868.C: New test. ++ ++2023-05-16 Marek Polacek ++ ++ Backported from master: ++ 2023-05-16 Marek Polacek ++ ++ PR c++/109774 ++ * g++.dg/warn/Wdangling-reference13.C: New test. ++ ++2023-05-16 Patrick O'Neill ++ ++ PR target/104338 ++ * gcc.target/riscv/inline-atomics-1.c: New test. ++ * gcc.target/riscv/inline-atomics-2.c: New test. ++ * gcc.target/riscv/inline-atomics-3.c: New test. ++ * gcc.target/riscv/inline-atomics-4.c: New test. ++ * gcc.target/riscv/inline-atomics-5.c: New test. ++ * gcc.target/riscv/inline-atomics-6.c: New test. ++ * gcc.target/riscv/inline-atomics-7.c: New test. ++ * gcc.target/riscv/inline-atomics-8.c: New test. ++ ++2023-05-15 Richard Biener ++ ++ Backported from master: ++ 2023-05-15 Richard Biener ++ ++ * gcc.dg/vect/pr108950.c: Re-order dg-require-effective-target ++ and dg-do. ++ ++2023-05-12 Patrick Palka ++ ++ Backported from master: ++ 2023-05-12 Patrick Palka ++ ++ PR c++/83258 ++ * g++.dg/ext/visibility/anon8.C: Mention PR83258. ++ * g++.dg/template/function2.C: Removed. ++ ++2023-05-12 Patrick Palka ++ ++ Backported from master: ++ 2023-05-11 Patrick Palka ++ ++ PR c++/109745 ++ * g++.dg/cpp0x/constexpr-mutable4.C: New test. ++ * g++.dg/cpp0x/constexpr-mutable5.C: New test. ++ * g++.dg/cpp1y/constexpr-mutable2.C: New test. ++ ++2023-05-12 Patrick Palka ++ ++ Backported from master: ++ 2023-05-11 Patrick Palka ++ ++ PR c++/103807 ++ * g++.dg/cpp2a/lambda-targ1.C: New test. ++ ++2023-05-12 Patrick Palka ++ ++ Backported from master: ++ 2023-05-11 Patrick Palka ++ Jonathan Wakely ++ ++ PR c++/83258 ++ PR c++/80488 ++ PR c++/97700 ++ * g++.dg/ext/visibility/anon8.C: Don't expect a "no linkage" ++ error for the template argument &B2:fn in C++17 mode. ++ * g++.dg/cpp0x/lambda/lambda-conv15.C: New test. ++ * g++.dg/cpp2a/nontype-class56.C: New test. ++ * g++.dg/template/function2.C: New test. ++ ++2023-05-12 Patrick Palka ++ ++ Backported from master: ++ 2023-05-09 Patrick Palka ++ ++ PR c++/109761 ++ * g++.dg/cpp0x/noexcept78.C: New test. ++ ++2023-05-12 Patrick Palka ++ ++ Backported from master: ++ 2023-05-07 Patrick Palka ++ ++ PR c++/109651 ++ * g++.dg/cpp2a/lambda-generic-ttp1.C: New test. ++ * g++.dg/cpp2a/lambda-generic-ttp2.C: New test. ++ +2023-05-11 Richard Sandiford + + PR target/109661 @@ -235485,6 +250808,221 @@ new file mode 100644 --- /dev/null ++++ b/src/gcc/testsuite/c-c++-common/pr109884.c +@@ -0,0 +1,32 @@ ++/* PR c++/109884 */ ++/* PowerPC doesn't define these as builtins, but macros expanding to ++ *f128 builtins. */ ++/* { dg-do compile { target { __float128 && { { c || c++11 } && { ! powerpc*-*-* } } } } } */ ++/* { dg-add-options __float128 } */ ++ ++#ifdef __cplusplus ++template ++struct is_same { ++ static const bool value = false; ++}; ++ ++template ++struct is_same { ++ static const bool value = true; ++}; ++#define HAS_TYPE(E, U) static_assert (is_same ::value, "") ++#else ++#define HAS_TYPE(E, U) _Static_assert (_Generic (E, default : 0, U : 1), "") ++#endif ++ ++void ++foo () ++{ ++ __float128 a = 0; ++ HAS_TYPE (__builtin_infq (), __float128); ++ HAS_TYPE (__builtin_huge_valq (), __float128); ++ HAS_TYPE (__builtin_nanq (""), __float128); ++ HAS_TYPE (__builtin_nansq (""), __float128); ++ HAS_TYPE (__builtin_fabsq (a), __float128); ++ HAS_TYPE (__builtin_copysignq (a, a), __float128); ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/g++.dg/cpp0x/constexpr-mutable4.C +@@ -0,0 +1,15 @@ ++// PR c++/109745 ++// Similar to constexpr-mutable1.C, but with nested 'mutable' accesses. ++// { dg-do compile { target c++11 } } ++ ++struct A { mutable int m = 0; }; ++ ++struct B { A a; }; ++ ++struct C { B b; }; ++ ++constexpr B b; ++constexpr int bam = b.a.m; // { dg-error "mutable" } ++ ++constexpr C c; ++constexpr int cbam = c.b.a.m; // { dg-error "mutable" } +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/g++.dg/cpp0x/constexpr-mutable5.C +@@ -0,0 +1,39 @@ ++// PR c++/109745 ++// { dg-do run { target c++11 } } ++// { dg-additional-options "-O" } ++ ++struct A { ++ mutable int m = 0; ++ void f() const { ++m; }; ++ constexpr int get_m() const { return m; } ++}; ++ ++struct B { A a; }; ++ ++struct C { B b; }; ++ ++int main() { ++ constexpr A a; ++ a.m++; ++ if (a.get_m() != 1 || a.m != 1) ++ __builtin_abort(); ++ a.m++; ++ if (a.get_m() != 2 || a.m != 2) ++ __builtin_abort(); ++ ++ constexpr B b; ++ b.a.m++; ++ if (b.a.get_m() != 1 || b.a.m != 1) ++ __builtin_abort(); ++ b.a.m++; ++ if (b.a.get_m() != 2 || b.a.m != 2) ++ __builtin_abort(); ++ ++ constexpr C c; ++ c.b.a.m++; ++ if (c.b.a.get_m() != 1 || c.b.a.m != 1) ++ __builtin_abort(); ++ c.b.a.m++; ++ if (c.b.a.get_m() != 2 || c.b.a.m != 2) ++ __builtin_abort(); ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/g++.dg/cpp0x/constexpr-mutable6.C +@@ -0,0 +1,18 @@ ++// PR c++/110463 ++// { dg-do compile { target c++11 } } ++ ++struct U { ++ mutable int x = 1; ++}; ++ ++struct V { ++ mutable int y = 1+1; ++}; ++ ++int main() { ++ constexpr U u = {}; ++ constexpr int x = u.x; // { dg-error "mutable" } ++ ++ constexpr V v = {}; ++ constexpr int y = v.y; // { dg-error "mutable" } ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/g++.dg/cpp0x/initlist-explicit3.C +@@ -0,0 +1,15 @@ ++// PR c++/109247 ++// { dg-do compile { target c++11 } } ++ ++template struct optional { ++ template explicit optional(_Up); ++ template void operator=(_Up); ++}; ++int setPattern_pattern; ++struct SourceBrush { ++ struct Brush { ++ int brush; ++ }; ++ void setPattern() { m_brush = {setPattern_pattern}; } ++ optional m_brush; ++}; +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/g++.dg/cpp0x/initlist-opt1.C +@@ -0,0 +1,15 @@ ++// PR c++/110102 ++// { dg-do compile { target c++11 } } ++ ++// { dg-error "deleted|construct_at" "" { target *-*-* } 0 } ++ ++#include ++ ++struct A { ++ A(int) {} ++ A(const A&) = delete; // { dg-message "declared here" } ++ A(A&&) {} ++}; ++int main() { ++ std::list v = {1,2,3}; ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-conv15.C +@@ -0,0 +1,11 @@ ++// PR c++/83258 ++// PR c++/80488 ++// { dg-do compile { target c++11 } } ++ ++template struct A { }; ++ ++int main() { ++ constexpr auto fp = +[]{}; // { dg-error "non-'constexpr' function" "" { target c++14_down } } ++ A a1; // { dg-error "not a valid template argument" "" { target c++14_down } } ++ A<[]{}> a2; // { dg-error "lambda-expression in template-argument|invalid" "" { target c++17_down } } ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/g++.dg/cpp0x/noexcept78.C +@@ -0,0 +1,16 @@ ++// PR c++/109761 ++// { dg-do compile { target c++11 } } ++ ++struct base { ++ virtual void foo() noexcept { } ++ virtual ~base() { } ++}; ++ ++struct outer : base { ++ struct nested { ++ void foo() noexcept(noexcept(g())); // { dg-bogus "looser" } ++ ~nested() noexcept(noexcept(g())); // { dg-bogus "looser" } ++ }; ++ static void g(); ++}; ++ +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/g++.dg/cpp0x/noexcept79.C +@@ -0,0 +1,18 @@ ++// PR c++/110468 ++// { dg-do compile { target c++11 } } ++ ++template ++struct variant { ++ variant() noexcept(T > 0); ++}; ++ ++template ++struct A { ++ variant m = {}; ++}; ++ ++struct B { ++ B(A<1>); ++}; ++ ++B b = {{}}; +new file mode 100644 +--- /dev/null +++ b/src/gcc/testsuite/g++.dg/cpp0x/nsdmi-array2.C @@ -0,0 +1,15 @@ +// PR c++/109666 @@ -235530,6 +251068,30 @@ +} new file mode 100644 --- /dev/null ++++ b/src/gcc/testsuite/g++.dg/cpp1y/constexpr-mutable2.C +@@ -0,0 +1,20 @@ ++// PR c++/109745 ++// { dg-do run { target c++14 } } ++// { dg-additional-options "-O" } ++ ++template ++struct Foo { T val; }; ++ ++struct Bar { ++ constexpr Bar() = default; ++ constexpr Bar(Bar const& other) { other.val_ = 42; } ++ constexpr int val() const { return val_; } ++ mutable int val_{}; ++}; ++ ++int main() { ++ constexpr Foo x{}; ++ Foo y{x}; ++ if (x.val.val() != 42 || x.val.val_ != 42) ++ __builtin_abort(); ++} +new file mode 100644 +--- /dev/null +++ b/src/gcc/testsuite/g++.dg/cpp23/attr-assume11.C @@ -0,0 +1,22 @@ +// PR c++/109756 @@ -235577,6 +251139,123 @@ #include "ext-floating.h" +--- a/src/gcc/testsuite/g++.dg/cpp23/feat-cxx2b.C ++++ b/src/gcc/testsuite/g++.dg/cpp23/feat-cxx2b.C +@@ -578,6 +578,12 @@ + # error "__cpp_implicit_move != 202207" + #endif + ++#ifndef __cpp_auto_cast ++# error "__cpp_auto_cast" ++#elif __cpp_auto_cast != 202110 ++# error "__cpp_auto_cast != 202110" ++#endif ++ + // C++23 attributes: + + #ifdef __has_cpp_attribute +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/g++.dg/cpp2a/desig27.C +@@ -0,0 +1,16 @@ ++// PR c++/109871 ++// { dg-do compile { target c++11 } } ++// { dg-options "" } ++ ++#include ++ ++struct vector { ++ vector(std::initializer_list); // #1 ++ vector(int); // #2 ++}; ++ ++void f(vector); ++ ++int main() { ++ f({.blah = 42}); // { dg-error "designated" } previously incorrectly selected #2 ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/g++.dg/cpp2a/lambda-generic-ttp1.C +@@ -0,0 +1,11 @@ ++// PR c++/109651 ++// { dg-do compile { target c++20 } } ++ ++template ++void f() { ++ [](U) { ++ [] class TT>(TT) { }; ++ }(0); ++} ++ ++template void f(); +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/g++.dg/cpp2a/lambda-generic-ttp2.C +@@ -0,0 +1,13 @@ ++// PR c++/109651 ++// { dg-do compile { target c++20 } } ++ ++template ++auto f() { ++ return [] class TT>(U, TT) { }; ++} ++ ++template struct A { }; ++ ++int main() { ++ f()(0, A{}); ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/g++.dg/cpp2a/lambda-targ1.C +@@ -0,0 +1,11 @@ ++// PR c++/103807 ++// { dg-do compile { target c++20 } } ++ ++template ++struct A { }; ++ ++A x; ++ ++int main() { ++ A y; ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/g++.dg/cpp2a/nontype-class56.C +@@ -0,0 +1,8 @@ ++// PR c++/97700 ++// { dg-do compile { target c++20 } } ++ ++struct S { void (*f)(); }; ++ ++template struct X { }; ++ ++X x; +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/g++.dg/debug/pr110295.C +@@ -0,0 +1,19 @@ ++// { dg-do compile } ++// { dg-options "-g" } ++ ++template ++struct QCachedT ++{ ++ void operator delete(void *, T *) {} ++}; ++template ++void exercise() ++{ ++ struct thing_t ++ : QCachedT ++ { ++ }; ++ thing_t *list[1]; ++ new thing_t; // { dg-warning "" } ++} ++int main() { exercise<1>(); } new file mode 100644 --- /dev/null +++ b/src/gcc/testsuite/g++.dg/ext/int128-8.C @@ -235663,70 +251342,334 @@ +static_assert (is_same ::value, ""); +static_assert (sizeof (u64) == sizeof (unsigned long long), ""); +static_assert (u64(-1) > 0, ""); ---- a/src/gcc/testsuite/g++.dg/torture/pr106922.C -+++ b/src/gcc/testsuite/g++.dg/torture/pr106922.C -@@ -4,8 +4,16 @@ - // -O1 doesn't iterate VN and thus has bogus uninit diagnostics - // { dg-skip-if "" { *-*-* } { "-O1" } { "" } } - -+// The testcase still emits bogus diagnostics with the pre-C++11 ABI -+#undef _GLIBCXX_USE_CXX11_ABI -+#define _GLIBCXX_USE_CXX11_ABI 1 -+ - #include - -+// When the library is not dual-ABI and defaults to old just compile -+// an empty TU -+#if _GLIBCXX_USE_CXX11_ABI -+ - #include - template - using Optional = std::optional; -@@ -46,3 +54,4 @@ void test() - externals.external2 = internal2; - } +--- a/src/gcc/testsuite/g++.dg/ext/visibility/anon8.C ++++ b/src/gcc/testsuite/g++.dg/ext/visibility/anon8.C +@@ -2,7 +2,7 @@ + // { dg-do compile } + + template +-void call () // { dg-message "note" } ++void call () // { dg-message "note" "" { target c++14_down } } + { + fn (); } -+#endif +@@ -26,7 +26,7 @@ int main () + static void fn2 () {} + }; + call<&B1::fn1> (); +- call<&B2::fn2> (); // { dg-error "linkage|no matching" } ++ call<&B2::fn2> (); // { dg-error "linkage|no matching" "PR83258" { target c++14_down } } + call<&fn3> (); + call<&B1::fn4> (); + call<&fn5> (); // { dg-error "linkage|no matching" "" { target { ! c++11 } } } new file mode 100644 --- /dev/null -+++ b/src/gcc/testsuite/g++.dg/torture/pr109724.C -@@ -0,0 +1,32 @@ ++++ b/src/gcc/testsuite/g++.dg/init/pr109868.C +@@ -0,0 +1,13 @@ ++// PR c++/109868 +// { dg-do compile } ++// { dg-options "-O2" } + -+double &SkTMax(double &a, double &b) { return a ?: b; } -+struct SkDPoint { -+ double fX; -+}; -+struct SkDCubic { -+ SkDPoint &operator[](int n) { return fPts[n]; } -+ SkDPoint fPts[4]; -+}; -+struct SkDCurve { -+ SkDCubic fCubic; -+ SkDPoint &operator[](int n) { return fCubic[n]; } -+}; -+struct SkDCurveSweep { -+ SkDCurve fCurve; -+}; -+int endsIntersect_rPts; -+double endsIntersect_maxX; -+struct SkOpAngle { -+ void endsIntersect(); -+ SkDCurveSweep fPart; -+} endsIntersect_rh; -+void SkOpAngle::endsIntersect() { -+ for (int index = 0;; ++index) { -+ SkDCurve &curve = index ? endsIntersect_rh.fPart.fCurve : fPart.fCurve; -+ for (int idx2 = 0; endsIntersect_rPts; ++idx2) { -+ SkDPoint &__trans_tmp_1 = curve[idx2]; -+ endsIntersect_maxX = SkTMax(endsIntersect_maxX, __trans_tmp_1.fX); -+ } -+ } ++struct A { virtual void foo (); }; ++struct B { long b; int : 0; }; ++struct C : A { B c; }; ++ ++void ++bar (C *p) ++{ ++ *p = C (); +} new file mode 100644 --- /dev/null -+++ b/src/gcc/testsuite/g++.dg/vect/pr109573.cc -@@ -0,0 +1,91 @@ ++++ b/src/gcc/testsuite/g++.dg/opt/pr110515.C +@@ -0,0 +1,223 @@ ++// { dg-do run } ++// { dg-require-effective-target c++11 } ++// { dg-options "-O2" } ++ ++typedef __UINT64_TYPE__ u64; ++ ++struct SmallDenseMap { ++ static constexpr u64 EmptyKey = 0xC0FFEUL; ++ struct V { u64 v; }; ++ ++ bool contains(u64 Val) { ++ V *TheSlot = nullptr; ++ return (LookupSlotFor(Val, TheSlot) ? 1 : 0); ++ } ++ ++ void try_emplace(u64 Key) { ++ V *TheSlot = nullptr; ++ if (LookupSlotFor(Key, TheSlot)) ++ return; ++ ++ // Otherwise, insert the new element. ++ InsertIntoSlot(TheSlot, Key); ++ } ++ ++ void moveFromOldSlots(V *OldSlotsBegin, V *OldSlotsEnd) { ++ Size = 0; ++ ++ V *B_ = u.o.Slots; ++ V *E_ = B_ + u.o.Capacity; ++ for (; B_ != E_; ++B_) ++ B_->v = EmptyKey; ++ ++ // Insert all the old elements. ++ V *O = OldSlotsBegin; ++ V *E = OldSlotsEnd; ++ for (; O != E; ++O) { ++ if (O->v != EmptyKey) { ++ // Insert the key/value into the new table. ++ V * N = nullptr; ++ LookupSlotFor(O->v, N); ++ N->v = O->v; ++ Size++; ++ } ++ } ++ } ++ ++ void InsertIntoSlot(V *TheSlot, u64 Key) { ++ unsigned NewSize = Size + 1; ++ unsigned Capacity = getCapacity(); ++ // Make sure we always keep at least one Empty value ++ if (NewSize >= Capacity) { ++ //fprintf(stderr, "GROW: size=%u capacity=%u -> ...\n", Size, Capacity); ++ grow(); ++ LookupSlotFor(Key, TheSlot); ++ Capacity = getCapacity(); ++ //fprintf(stderr, "GROW: ... -> size=%u capacity=%u\n", NewSize, Capacity); ++ } ++ ++ Size++; ++ ++ TheSlot->v = Key; ++ } ++ ++ bool LookupSlotFor(u64 Val, ++ V *&FoundSlot) { ++ V *SlotsPtr = getSlots(); ++ const unsigned Capacity = getCapacity(); ++ ++ for (unsigned i = 0; i < Capacity; ++i) { ++ V *ThisSlot = SlotsPtr + i; ++ if (Val == ThisSlot->v) { ++ FoundSlot = ThisSlot; ++ return true; ++ } ++ ++ if (ThisSlot->v == EmptyKey) { ++ FoundSlot = ThisSlot; ++ return false; ++ } ++ } ++ // Guarantee that within an array there is a match ++ // or Empty value where to insert a new vaue. ++ __builtin_trap(); ++ } ++ ++ // Needs to bea at least 1 to hld one empty value ++ static constexpr unsigned InlineSlots = 2; ++ ++ bool Small; ++ unsigned Size; ++ ++ struct LargeRep { ++ V *Slots; ++ unsigned Capacity; ++ }; ++ ++ union { ++ V i[InlineSlots]; // Small = true ++ LargeRep o; // Small = false ++ } u; ++ ++ explicit SmallDenseMap() : Small(true), Size(0) { ++ Size = 0; ++ ++ V *B = u.i; ++ V *E = B + InlineSlots; ++ for (; B != E; ++B) ++ B->v = EmptyKey; ++ } ++ ++ void grow() { ++ // assert: ++ if (!Small) __builtin_trap(); ++ ++ // First move the inline Slots into a temporary storage. ++ V TmpStorage[InlineSlots]; ++ V *TmpBegin = TmpStorage; ++ V *TmpEnd = TmpBegin; ++ ++ // Loop over the Slots, moving non-empty, non-tombstones into the ++ // temporary storage. Have the loop move the TmpEnd forward as it goes. ++ V *P = u.i; ++ V *E = P + InlineSlots; ++ for (; P != E; ++P) { ++ if (P->v != EmptyKey) { ++ TmpEnd->v = P->v; ++ ++TmpEnd; ++ } ++ } ++ ++ Small = false; ++ u.o = LargeRep{new V[128], 128}; ++ moveFromOldSlots(TmpBegin, TmpEnd); ++ } ++ ++ V *getSlots() { ++ if (Small) { ++ V * inl = u.i; ++ return inl; ++ } ++ else { ++ LargeRep * rep = &u.o; ++ return rep->Slots; ++ } ++ } ++ ++ unsigned getCapacity() { ++ if (Small) { ++ return InlineSlots; ++ } ++ else { ++ LargeRep * rep = &u.o; ++ return rep->Capacity; ++ } ++ } ++}; ++ ++#pragma GCC optimize(0) ++ ++struct P { ++ u64 f; ++ bool s; ++}; ++ ++static u64 ws = 0; ++static P WorkList[128]; ++ ++__attribute__((noipa)) ++static void popupateIni() { ++ for (u64 Var : (u64[]){8,7,6,5,4,3,0}) { ++ WorkList[ws++] = P{Var, false}; ++ } ++} ++ ++__attribute__((noipa)) ++static void checkCycle(u64 Var) { ++ // Detect cycles. ++ static bool seen[256]; ++ if (Var >= 256 || seen[Var]) __builtin_trap(); ++ seen[Var] = true; ++} ++ ++ ++__attribute__((noipa)) ++static void populateDeps(u64 Var) { ++ ++ WorkList[ws++] = P{Var, true}; ++ if (Var == 8) ++ WorkList[ws++] = P{0, false}; ++} ++ ++ ++__attribute__((noipa)) __attribute__((optimize(3))) ++static void bug() { ++ ++ // triggers growth on insert ++ SmallDenseMap Visited; ++ ++ popupateIni(); ++ ++ while (ws > 0) { ++ P Item = WorkList[--ws]; ++ u64 Var = Item.f; ++ bool visitedAllDependencies = Item.s; ++ ++ if (Visited.contains(Var)) { ++ continue; ++ } ++ ++ if (visitedAllDependencies) { ++ Visited.try_emplace(Var); ++ continue; ++ } ++ ++ checkCycle(Var); ++ populateDeps(Var); ++ } ++} ++ ++__attribute__((noipa)) ++int main() { ++ bug(); ++} +--- a/src/gcc/testsuite/g++.dg/torture/pr106922.C ++++ b/src/gcc/testsuite/g++.dg/torture/pr106922.C +@@ -4,8 +4,16 @@ + // -O1 doesn't iterate VN and thus has bogus uninit diagnostics + // { dg-skip-if "" { *-*-* } { "-O1" } { "" } } + ++// The testcase still emits bogus diagnostics with the pre-C++11 ABI ++#undef _GLIBCXX_USE_CXX11_ABI ++#define _GLIBCXX_USE_CXX11_ABI 1 ++ + #include + ++// When the library is not dual-ABI and defaults to old just compile ++// an empty TU ++#if _GLIBCXX_USE_CXX11_ABI ++ + #include + template + using Optional = std::optional; +@@ -46,3 +54,4 @@ void test() + externals.external2 = internal2; + } + } ++#endif +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/g++.dg/torture/pr109724.C +@@ -0,0 +1,32 @@ ++// { dg-do compile } ++ ++double &SkTMax(double &a, double &b) { return a ?: b; } ++struct SkDPoint { ++ double fX; ++}; ++struct SkDCubic { ++ SkDPoint &operator[](int n) { return fPts[n]; } ++ SkDPoint fPts[4]; ++}; ++struct SkDCurve { ++ SkDCubic fCubic; ++ SkDPoint &operator[](int n) { return fCubic[n]; } ++}; ++struct SkDCurveSweep { ++ SkDCurve fCurve; ++}; ++int endsIntersect_rPts; ++double endsIntersect_maxX; ++struct SkOpAngle { ++ void endsIntersect(); ++ SkDCurveSweep fPart; ++} endsIntersect_rh; ++void SkOpAngle::endsIntersect() { ++ for (int index = 0;; ++index) { ++ SkDCurve &curve = index ? endsIntersect_rh.fPart.fCurve : fPart.fCurve; ++ for (int idx2 = 0; endsIntersect_rPts; ++idx2) { ++ SkDPoint &__trans_tmp_1 = curve[idx2]; ++ endsIntersect_maxX = SkTMax(endsIntersect_maxX, __trans_tmp_1.fX); ++ } ++ } ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/g++.dg/vect/pr109573.cc +@@ -0,0 +1,91 @@ +// { dg-do compile } +// { dg-require-effective-target c++20 } + @@ -235820,6 +251763,161 @@ +} new file mode 100644 --- /dev/null ++++ b/src/gcc/testsuite/g++.dg/vect/pr110557.cc +@@ -0,0 +1,37 @@ ++// { dg-additional-options "-mavx" { target { avx_runtime } } } ++ ++static inline long ++min (long a, long b) ++{ ++ return a < b ? a : b; ++} ++ ++struct Item ++{ ++ int x : 8; ++ long y : 55; ++ bool z : 1; ++}; ++ ++__attribute__ ((noipa)) long ++test (Item *a, int cnt) ++{ ++ long size = 0; ++ for (int i = 0; i < cnt; i++) ++ size = min ((long)a[i].y, size); ++ return size; ++} ++ ++int ++main () ++{ ++ struct Item items[] = { ++ { 1, -1 }, ++ { 2, -2 }, ++ { 3, -3 }, ++ { 4, -4 }, ++ }; ++ ++ if (test (items, 4) != -4) ++ __builtin_trap (); ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/g++.dg/warn/Wdangling-pointer-pr110055.C +@@ -0,0 +1,16 @@ ++// { dg-do compile } ++// { dg-require-effective-target c++11 } ++// { dg-options "-O3 -fno-exceptions -Wdangling-pointer" } ++ ++#include ++#include ++ ++struct Data { ++ std::vector v = {1, 1}; ++}; ++ ++int main() ++{ ++ Data a; ++ Data b; ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/g++.dg/warn/Wdangling-reference13.C +@@ -0,0 +1,23 @@ ++// PR c++/109774 ++// { dg-do compile } ++// { dg-options "-Wdangling-reference" } ++ ++int y; ++ ++template ++int& get(const char& ) ++{ ++ return y; ++} ++ ++int& get2(const char&) ++{ ++ return y; ++} ++ ++int stuff(void) ++{ ++ const int &h = get(0); // { dg-bogus "dangling reference" } ++ const int &k = get2(0); // { dg-bogus "dangling reference" } ++ return h+k; ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/g++.target/aarch64/acle/acle.exp +@@ -0,0 +1,35 @@ ++# Copyright (C) 2014-2023 Free Software Foundation, Inc. ++ ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of the GNU General Public License as published by ++# the Free Software Foundation; either version 3 of the License, or ++# (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with GCC; see the file COPYING3. If not see ++# . ++ ++# GCC testsuite that uses the `dg.exp' driver. ++ ++# Exit immediately if this isn't an AArch64 target. ++if ![istarget aarch64*-*-*] then { ++ return ++} ++ ++# Load support procs. ++load_lib g++-dg.exp ++ ++# Initialize `dg'. ++dg-init ++ ++# Main loop. ++dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \ ++ "" "" ++ ++# All done. ++dg-finish +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/g++.target/aarch64/acle/ls64.C +@@ -0,0 +1,10 @@ ++/* { dg-do compile } */ ++/* { dg-additional-options "-march=armv8.7-a" } */ ++#include ++int main() ++{ ++ data512_t d = __arm_ld64b ((const void *)0x1000); ++ __arm_st64b ((void *)0x2000, d); ++ uint64_t x = __arm_st64bv ((void *)0x3000, d); ++ x += __arm_st64bv0 ((void *)0x4000, d); ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/g++.target/aarch64/acle/ls64_lto.C +@@ -0,0 +1,10 @@ ++/* { dg-do link { target aarch64_asm_ls64_ok } } */ ++/* { dg-additional-options "-march=armv8.7-a -flto" } */ ++#include ++int main() ++{ ++ data512_t d = __arm_ld64b ((const void *)0x1000); ++ __arm_st64b ((void *)0x2000, d); ++ uint64_t x = __arm_st64bv ((void *)0x3000, d); ++ x += __arm_st64bv0 ((void *)0x4000, d); ++} +new file mode 100644 +--- /dev/null +++ b/src/gcc/testsuite/g++.target/aarch64/pr109661-1.C @@ -0,0 +1,122 @@ +/* { dg-options "-O2 -Wpsabi" } */ @@ -236377,6 +252475,38 @@ +} new file mode 100644 --- /dev/null ++++ b/src/gcc/testsuite/g++.target/powerpc/pr105325.C +@@ -0,0 +1,28 @@ ++/* { dg-do assemble } */ ++/* { dg-require-effective-target lp64 } */ ++/* { dg-require-effective-target power10_ok } */ ++/* { dg-require-effective-target powerpc_prefixed_addr } */ ++/* { dg-options "-O2 -mdejagnu-cpu=power10 -fstack-protector" } */ ++ ++/* PR target/105324. Test that power10 fusion does not generate an LWA/CMPDI ++ with a large offset that the assembler rejects. Instead it should a ++ PLWZ/CMPWI combination. ++ ++ Originally, the code was dying because the fusion load + compare -1/0/1 ++ patterns did not handle the possibility that the load might be prefixed. ++ The -fstack-protector option is needed to show the bug. */ ++ ++struct Ath__array1D { ++ int _current; ++ int getCnt() { return _current; } ++}; ++struct extMeasure { ++ int _mapTable[10000]; ++ Ath__array1D _metRCTable; ++}; ++void measureRC() { ++ extMeasure m; ++ for (; m._metRCTable.getCnt();) ++ for (;;) ++ ; ++} +new file mode 100644 +--- /dev/null +++ b/src/gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C @@ -0,0 +1,144 @@ +/* { dg-do compile } */ @@ -236525,6 +252655,164 @@ +}; new file mode 100644 --- /dev/null ++++ b/src/gcc/testsuite/gcc.c-torture/compile/asmgoto-6.c +@@ -0,0 +1,26 @@ ++ ++/* { dg-do compile } */ ++/* PR middle-end/110420 */ ++/* PR middle-end/103979 */ ++/* PR middle-end/98619 */ ++/* Test that the middle-end does not remove the asm goto ++ with an output. */ ++ ++static int t; ++void g(void); ++ ++void f(void) ++{ ++ int __gu_val; ++ asm goto("#my asm " ++ : "=&r"(__gu_val) ++ : ++ : ++ : Efault); ++ t = __gu_val; ++ g(); ++Efault: ++} ++ ++/* Make sure "my asm " is still in the assembly. */ ++/* { dg-final { scan-assembler "my asm " } } */ +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.c-torture/execute/20230630-1.c +@@ -0,0 +1,23 @@ ++struct S { ++ short int i : 12; ++ char c1 : 1; ++ char c2 : 1; ++ char c3 : 1; ++ char c4 : 1; ++}; ++ ++int main (void) ++{ ++ struct S s0 = { 341, 1, 1, 1, 1 }; ++ char *p = (char *) &s0; ++ ++#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ ++ if (*p != 85) ++ __builtin_abort (); ++#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ ++ if (*p != 21) ++ __builtin_abort (); ++#endif ++ ++ return 0; ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.c-torture/execute/20230630-2.c +@@ -0,0 +1,29 @@ ++#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ ++#define REVERSE_SSO __attribute__((scalar_storage_order("big-endian"))); ++#else ++#define REVERSE_SSO __attribute__((scalar_storage_order("little-endian"))); ++#endif ++ ++struct S { ++ short int i : 12; ++ char c1 : 1; ++ char c2 : 1; ++ char c3 : 1; ++ char c4 : 1; ++} REVERSE_SSO; ++ ++int main (void) ++{ ++ struct S s0 = { 341, 1, 1, 1, 1 }; ++ char *p = (char *) &s0; ++ ++#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ ++ if (*p != 21) ++ __builtin_abort (); ++#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ ++ if (*p != 85) ++ __builtin_abort (); ++#endif ++ ++ return 0; ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.c-torture/execute/20230630-3.c +@@ -0,0 +1,27 @@ ++struct S { ++ int i : 24; ++ char c1 : 1; ++ char c2 : 1; ++ char c3 : 1; ++ char c4 : 1; ++ char c5 : 1; ++ char c6 : 1; ++ char c7 : 1; ++ char c8 : 1; ++}; ++ ++int main (void) ++{ ++ struct S s0 = { 1193046, 1, 1, 1, 1, 1, 1, 1, 1 }; ++ char *p = (char *) &s0; ++ ++#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ ++ if (*p != 86) ++ __builtin_abort (); ++#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ ++ if (*p != 18) ++ __builtin_abort (); ++#endif ++ ++ return 0; ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.c-torture/execute/20230630-4.c +@@ -0,0 +1,33 @@ ++#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ ++#define REVERSE_SSO __attribute__((scalar_storage_order("big-endian"))); ++#else ++#define REVERSE_SSO __attribute__((scalar_storage_order("little-endian"))); ++#endif ++ ++struct S { ++ int i : 24; ++ char c1 : 1; ++ char c2 : 1; ++ char c3 : 1; ++ char c4 : 1; ++ char c5 : 1; ++ char c6 : 1; ++ char c7 : 1; ++ char c8 : 1; ++} REVERSE_SSO; ++ ++int main (void) ++{ ++ struct S s0 = { 1193046, 1, 1, 1, 1, 1, 1, 1, 1 }; ++ char *p = (char *) &s0; ++ ++#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ ++ if (*p != 18) ++ __builtin_abort (); ++#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ ++ if (*p != 86) ++ __builtin_abort (); ++#endif ++ ++ return 0; ++} +new file mode 100644 +--- /dev/null +++ b/src/gcc/testsuite/gcc.c-torture/execute/pr109778.c @@ -0,0 +1,26 @@ +/* PR tree-optimization/109778 */ @@ -236555,6 +252843,75 @@ +} new file mode 100644 --- /dev/null ++++ b/src/gcc/testsuite/gcc.c-torture/execute/pr110165-1.c +@@ -0,0 +1,28 @@ ++struct s ++{ ++ int t : 1; ++}; ++ ++int f(struct s t, int a, int b) __attribute__((noinline)); ++int f(struct s t, int a, int b) ++{ ++ int bd = t.t; ++ if (bd) a|=b; ++ return a; ++} ++ ++int main(void) ++{ ++ struct s t; ++ for(int i = -1;i <= 1; i++) ++ { ++ int a = 0x10; ++ int b = 0x0f; ++ int c = a | b; ++ struct s t = {i}; ++ int r = f(t, a, b); ++ int exp = (i != 0) ? a | b : a; ++ if (exp != r) ++ __builtin_abort(); ++ } ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.c-torture/execute/pr110166-1.c +@@ -0,0 +1,33 @@ ++struct s ++{ ++ int t : 1; ++ int t1 : 1; ++}; ++ ++int f(struct s t) __attribute__((noinline)); ++int f(struct s t) ++{ ++ int c = t.t; ++ int d = t.t1; ++ if (c > d) ++ t.t = d; ++ else ++ t.t = c; ++ return t.t; ++} ++ ++int main(void) ++{ ++ struct s t; ++ for(int i = -1;i <= 0; i++) ++ { ++ for(int j = -1;j <= 0; j++) ++ { ++ struct s t = {i, j}; ++ int r = f(t); ++ int exp = i < j ? i : j; ++ if (exp != r) ++ __builtin_abort(); ++ } ++ } ++} +new file mode 100644 +--- /dev/null +++ b/src/gcc/testsuite/gcc.dg/goacc/pr107041.c @@ -0,0 +1,23 @@ +/* PR c/107041 */ @@ -236582,6 +252939,25 @@ +} new file mode 100644 --- /dev/null ++++ b/src/gcc/testsuite/gcc.dg/ipa/pr110276.c +@@ -0,0 +1,15 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ ++ ++typedef long (*EFI_PCI_IO_PROTOCOL_CONFIG)(); ++typedef struct { ++ EFI_PCI_IO_PROTOCOL_CONFIG Read; ++} EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS; ++typedef struct { ++ EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS Pci; ++} EFI_PCI_IO_PROTOCOL; ++int init_regs_0; ++static void __attribute__((constructor)) init(EFI_PCI_IO_PROTOCOL *pci_io) { ++ if (init_regs_0) ++ pci_io->Pci.Read(); ++} +new file mode 100644 +--- /dev/null +++ b/src/gcc/testsuite/gcc.dg/lto/pr109778_0.c @@ -0,0 +1,22 @@ +/* PR tree-optimization/109778 */ @@ -236617,6 +252993,58 @@ + x |= (int) 0xf1234567U; + return x; +} +--- a/src/gcc/testsuite/gcc.dg/plugin/crash-test-ice-sarif.c ++++ b/src/gcc/testsuite/gcc.dg/plugin/crash-test-ice-sarif.c +@@ -1,5 +1,6 @@ + /* { dg-do compile } */ + /* { dg-options "-fdiagnostics-format=sarif-file" } */ ++/* { dg-additional-options "-fno-report-bug" } */ + + extern void inject_ice (void); + +@@ -56,7 +57,7 @@ void test_inject_ice (void) + { dg-final { scan-sarif-file "\"contextRegion\": " } } + { dg-final { scan-sarif-file "\"artifactLocation\": " } } + { dg-final { scan-sarif-file "\"region\": " } } +- { dg-final { scan-sarif-file "\"startLine\": 8" } } ++ { dg-final { scan-sarif-file "\"startLine\": 9" } } + { dg-final { scan-sarif-file "\"startColumn\": 3" } } + { dg-final { scan-sarif-file "\"endColumn\": 16" } } + { dg-final { scan-sarif-file "\"message\": " } } +--- a/src/gcc/testsuite/gcc.dg/plugin/crash-test-ice-stderr.c ++++ b/src/gcc/testsuite/gcc.dg/plugin/crash-test-ice-stderr.c +@@ -1,4 +1,5 @@ + /* { dg-do compile } */ ++/* { dg-additional-options "-fno-report-bug" } */ + + extern void inject_ice (void); + +--- a/src/gcc/testsuite/gcc.dg/plugin/crash-test-write-though-null-sarif.c ++++ b/src/gcc/testsuite/gcc.dg/plugin/crash-test-write-though-null-sarif.c +@@ -1,5 +1,6 @@ + /* { dg-do compile } */ + /* { dg-options "-fdiagnostics-format=sarif-file" } */ ++/* { dg-additional-options "-fno-report-bug" } */ + + extern void inject_write_through_null (void); + +@@ -56,7 +57,7 @@ void test_inject_write_through_null (void) + { dg-final { scan-sarif-file "\"contextRegion\": " } } + { dg-final { scan-sarif-file "\"artifactLocation\": " } } + { dg-final { scan-sarif-file "\"region\": " } } +- { dg-final { scan-sarif-file "\"startLine\": 8" } } ++ { dg-final { scan-sarif-file "\"startLine\": 9" } } + { dg-final { scan-sarif-file "\"startColumn\": 3" } } + { dg-final { scan-sarif-file "\"endColumn\": 31" } } + { dg-final { scan-sarif-file "\"message\": " } } +--- a/src/gcc/testsuite/gcc.dg/plugin/crash-test-write-though-null-stderr.c ++++ b/src/gcc/testsuite/gcc.dg/plugin/crash-test-write-though-null-stderr.c +@@ -1,4 +1,5 @@ + /* { dg-do compile } */ ++/* { dg-additional-options "-fno-report-bug" } */ + + extern void inject_write_through_null (void); + new file mode 100644 --- /dev/null +++ b/src/gcc/testsuite/gcc.dg/pr109409.c @@ -236724,323 +253152,70036 @@ +} new file mode 100644 --- /dev/null -+++ b/src/gcc/testsuite/gcc.target/aarch64/pr109661-1.c -@@ -0,0 +1,5 @@ -+/* { dg-options "-O2 -Wpsabi" } */ ++++ b/src/gcc/testsuite/gcc.dg/torture/pr110228.c +@@ -0,0 +1,34 @@ ++/* { dg-do run { target x86_64-*-* i?86-*-* } } */ ++/* { dg-require-effective-target lp64 } */ + -+enum __attribute__((aligned(16))) e { E }; ++unsigned a[4] = {1,1,1,1}; ++unsigned tt1 = 0; + -+enum e test (int x, enum e y) { return y; } ---- a/src/gcc/testsuite/gcc.target/gcn/fpdiv.c -+++ b/src/gcc/testsuite/gcc.target/gcn/fpdiv.c -@@ -1,5 +1,4 @@ - /* { dg-do run } */ --/* { dg-options "-ffast-math" } */ - - #include - #include ++__attribute__((noipa)) ++static void bug(unsigned * p, unsigned *t, int n, int t2) ++{ ++ for(int i = 0; i < n; i++) ++ { ++ _Bool LookupFlags ; ++ unsigned v = t[i]; ++ unsigned tt = tt1; ++ if (v == 0) ++ LookupFlags = 0; ++ else if (v == 1) ++ LookupFlags = 1; ++ if (LookupFlags) { ++ tt|=3u; ++ LookupFlags = 0; ++ } ++ asm("movq $-1, %q1":"+a"(LookupFlags)); ++ *p = tt; ++ } ++} ++ ++int main() ++{ ++ unsigned r = 42; ++ bug(&r,a, sizeof(a)/sizeof(a[0]), 1); ++ __builtin_printf("%u\n", r); ++ if (r != 3) __builtin_abort(); ++} new file mode 100644 --- /dev/null -+++ b/src/gcc/testsuite/gcc.target/powerpc/pr109069-1.c -@@ -0,0 +1,25 @@ ++++ b/src/gcc/testsuite/gcc.dg/torture/pr110298.c +@@ -0,0 +1,20 @@ ++/* { dg-do compile } */ ++ ++int a, b, c, d, e; ++int f() { ++ c = 0; ++ for (; c >= 0; c--) { ++ d = 0; ++ for (; d <= 0; d++) { ++ e = 0; ++ for (; d + c + e >= 0; e--) ++ ; ++ a = 1; ++ b = 0; ++ for (; a; ++b) ++ a *= 2; ++ for (; b + d >= 0;) ++ return 0; ++ } ++ } ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.dg/torture/pr110556.c +@@ -0,0 +1,42 @@ +/* { dg-do run } */ -+/* { dg-require-effective-target vmx_hw } */ -+/* { dg-options "-O2 -maltivec" } */ ++/* { dg-require-effective-target lp64 } */ ++/* { dg-additional-options "-fno-tree-fre -fno-delete-dead-exceptions -fnon-call-exceptions" } */ + -+/* Verify it run successfully. */ ++typedef __INT32_TYPE__ int32_t; ++typedef __INT64_TYPE__ int64_t; + -+#include ++static int64_t __attribute__((noinline,noclone)) ++safe_mul_func_int64_t_s_s(int64_t si1, int64_t si2) ++{ ++ return ((((si1 > 0) && (si2 > 0) && (si1 > ( (9223372036854775807L) / si2))) ++ || ((si1 > 0) && (si2 <= 0) && (si2 < ( (-9223372036854775807L -1) / si1))) ++ || ((si1 <= 0) && (si2 > 0) && (si1 < ( (-9223372036854775807L -1) / si2))) ++ || ((si1 <= 0) && (si2 <= 0) && (si1 != 0) && (si2 < ( (9223372036854775807L) / si1)))) ++ ? ((si1)) : si1 * si2); ++} + -+__attribute__ ((noipa)) -+vector signed int -+test () ++static int32_t g_93 = 0x947A4BBFL; ++static int32_t tt = 6; ++int64_t ty, ty1; ++ ++static void func_34(void) +{ -+ vector signed int v = {-16, -16, -16, -16}; -+ vector signed int res = vec_sld (v, v, 3); -+ return res; ++ ty=safe_mul_func_int64_t_s_s (g_93, -1L) ; ++} ++static void func_30(void) ++{ ++ ty1=safe_mul_func_int64_t_s_s(0, tt); ++} ++static void func_6(void) ++{ ++ for (int g_9 = 5; (g_9 >= 0); g_9 -= 1) ++ { ++ func_34(); ++ func_30 (); ++ } +} + -+int -+main () ++int main () +{ -+ vector signed int res = test (); -+ if (res[0] != 0xf0ffffff) -+ __builtin_abort (); -+ return 0; ++ func_6(); +} +--- a/src/gcc/testsuite/gcc.dg/uninit-pr101912.c ++++ b/src/gcc/testsuite/gcc.dg/uninit-pr101912.c +@@ -11,7 +11,7 @@ tzloadbody (void) + for (int i = 0; i < n; i++) + { + int corr = getint (); +- if (corr < 1 || (corr == 1 && !(leapcnt == 0 || (prevcorr < corr ? corr == prevcorr + 1 : (corr == prevcorr || corr == prevcorr - 1))))) /* { dg-bogus "uninitialized" "pr101912" { xfail *-*-* } } */ ++ if (corr < 1 || (corr == 1 && !(leapcnt == 0 || (prevcorr < corr ? corr == prevcorr + 1 : (corr == prevcorr || corr == prevcorr - 1))))) /* { dg-bogus "uninitialized" "pr101912" } */ + return -1; + + prevcorr = corr; +--- a/src/gcc/testsuite/gcc.dg/vect/pr108950.c ++++ b/src/gcc/testsuite/gcc.dg/vect/pr108950.c +@@ -1,5 +1,5 @@ +-/* { dg-require-effective-target vect_simd_clones } */ + /* { dg-do compile } */ ++/* { dg-require-effective-target vect_simd_clones } */ + + int m; + short int n; new file mode 100644 --- /dev/null -+++ b/src/gcc/testsuite/gcc.target/powerpc/pr109069-2-run.c -@@ -0,0 +1,50 @@ ++++ b/src/gcc/testsuite/gcc.dg/vect/pr110381.c +@@ -0,0 +1,45 @@ +/* { dg-do run } */ -+/* { dg-require-effective-target vsx_hw } */ -+/* { dg-options "-O2 -mvsx" } */ ++/* { dg-require-effective-target vect_float_strict } */ + -+/* Verify it doesn't generate wrong code. */ ++#include "tree-vect.h" + -+#include "pr109069-2.h" ++struct FOO { ++ double a; ++ double b; ++ double c; ++}; + -+int -+main () ++double __attribute__((noipa)) ++sum_8_foos(const struct FOO* foos) +{ -+ vector unsigned char res1 = test1 (); -+ for (int i = 0; i < 16; i++) -+ if (res1[i] != 0xd) -+ __builtin_abort (); -+ -+ vector signed short res2 = test2 (); -+ for (int i = 0; i < 8; i++) -+ if (res2[i] != 0x7777) -+ __builtin_abort (); ++ double sum = 0; + -+ vector signed int res3 = test3 (); -+ vector unsigned int res4 = test4 (); -+ vector float res6 = test6 (); -+ for (int i = 0; i < 4; i++) ++ for (int i = 0; i < 8; ++i) + { -+ if (res3[i] != 0xbbbbbbbb) -+ __builtin_abort (); -+ if (res4[i] != 0x7070707) -+ __builtin_abort (); -+ U32b u; -+ u.f = res6[i]; -+ if (u.i != 0x17171717) -+ __builtin_abort (); -+ } ++ struct FOO foo = foos[i]; + -+ vector unsigned long long res5 = test5 (); -+ vector double res7 = test7 (); -+ for (int i = 0; i < 2; i++) -+ { -+ if (res5[i] != 0x4545454545454545ll) -+ __builtin_abort (); -+ U64b u; -+ u.f = res7[i]; -+ if (u.i != 0x5454545454545454ll) -+ __builtin_abort (); ++ /* Need to use an in-order reduction here, preserving ++ the load permutation. */ ++ sum += foo.a; ++ sum += foo.c; ++ sum += foo.b; + } -+ return 0; ++ ++ return sum; +} + ++int main() ++{ ++ struct FOO foos[8]; ++ ++ check_vect (); ++ ++ __builtin_memset (foos, 0, sizeof (foos)); ++ foos[0].a = __DBL_MAX__; ++ foos[0].b = 5; ++ foos[0].c = -__DBL_MAX__; ++ ++ if (sum_8_foos (foos) != 5) ++ __builtin_abort (); ++ return 0; ++} new file mode 100644 --- /dev/null -+++ b/src/gcc/testsuite/gcc.target/powerpc/pr109069-2.c -@@ -0,0 +1,12 @@ ++++ b/src/gcc/testsuite/gcc.target/aarch64/acle/ls64_lto.c +@@ -0,0 +1,10 @@ ++/* { dg-do link { target aarch64_asm_ls64_ok } } */ ++/* { dg-additional-options "-march=armv8.7-a -flto" } */ ++#include ++int main(void) ++{ ++ data512_t d = __arm_ld64b ((const void *)0x1000); ++ __arm_st64b ((void *)0x2000, d); ++ uint64_t x = __arm_st64bv ((void *)0x3000, d); ++ x += __arm_st64bv0 ((void *)0x4000, d); ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/aarch64/acle/pr110100.c +@@ -0,0 +1,7 @@ +/* { dg-do compile } */ -+/* { dg-require-effective-target powerpc_vsx_ok } */ -+/* Disable rs6000 optimize_swaps as it drops some REG_EQUAL -+ notes on const vector and affects test point here. */ -+/* { dg-options "-O2 -mvsx -mno-optimize-swaps" } */ ++/* { dg-options "-march=armv8.7-a -O2" } */ ++#include ++void do_st64b(data512_t data) { ++ __arm_st64b((void*)0x10000000, data); ++} ++/* { dg-final { scan-assembler {mov\tx([123])?[0-9], 268435456} } } */ +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/aarch64/acle/pr110132.c +@@ -0,0 +1,15 @@ ++/* { dg-do compile } */ ++/* { dg-additional-options "-march=armv8.7-a" } */ + -+/* Verify we can optimize away vector shifting if every byte -+ of vector is the same. */ ++/* Check that ls64 builtins can be invoked using a preprocesed testcase ++ without triggering bogus builtin warnings, see PR110132. + -+#include "pr109069-2.h" ++ Note that this is purely to test GCC internals and user code should ++ include arm_acle.h to make use of these builtins. */ + -+/* { dg-final { scan-assembler-not {\mvsldoi\M} } } */ ++#pragma GCC aarch64 "arm_acle.h" ++typedef __arm_data512_t data512_t; ++void f(void *p, data512_t d) ++{ ++ __arm_st64b (p, d); ++} new file mode 100644 --- /dev/null -+++ b/src/gcc/testsuite/gcc.target/powerpc/pr109069-2.h -@@ -0,0 +1,83 @@ -+#include ++++ b/src/gcc/testsuite/gcc.target/aarch64/pr109661-1.c +@@ -0,0 +1,5 @@ ++/* { dg-options "-O2 -Wpsabi" } */ + -+typedef union ++enum __attribute__((aligned(16))) e { E }; ++ ++enum e test (int x, enum e y) { return y; } +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/aarch64/sve/pr109505.c +@@ -0,0 +1,12 @@ ++/* PR tree-optimization/109505 */ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -march=armv8.2-a+sve" } */ ++ ++#pragma GCC aarch64 "arm_sve.h" ++ ++unsigned long ++foo (unsigned long x) +{ -+ unsigned int i; -+ float f; -+} U32b; ++ unsigned long y = svcntb (); ++ return (x | 15) & y; ++} +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/asrl.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/asrl.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif + -+typedef union ++/* ++**foo: ++** ... ++** asrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int64_t +-asrl_reg (int64_t longval3, int32_t x) ++foo (int64_t value, int32_t shift) + { +- return asrl (longval3, x); ++ return asrl (value, shift); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "asrl\\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/lsll.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/lsll.c +@@ -1,13 +1,40 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** lsll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint64_t +-lsll_reg (uint64_t longval3, int32_t x) ++foo (uint64_t value, int32_t shift) + { +- return lsll (longval3, x); ++ return lsll (value, shift); ++} ++ ++/* ++**foo1: ++** ... ++** lsll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint64_t ++foo1 (int32_t shift) +{ -+ unsigned long long i; -+ double f; -+} U64b; ++ return lsll (1, shift); ++} + -+__attribute__ ((noipa)) -+vector unsigned char -+test1 () ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "lsll\\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c ++++ /dev/null +@@ -1,47 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include +-int8x16_t foo (int8x16_t a, int16_t b) +-{ +- return vaddq (a, (b<<3)); +-} +-int16x8_t foo1 (int16x8_t a, int16_t b) +-{ +- return vaddq (a, (b<<3)); +-} +-int32x4_t foo2 (int32x4_t a, int16_t b) +-{ +- return vaddq (a, (b<<3)); +-} +-uint8x16_t foo3 (uint8x16_t a, int16_t b) +-{ +- return vaddq (a, (b<<3)); +-} +-uint16x8_t foo4 (uint16x8_t a, int16_t b) +-{ +- return vaddq (a, (b<<3)); +-} +-uint32x4_t foo5 (uint32x4_t a, int16_t b) +-{ +- return vaddq (a, (b<<3)); +-} +-float16x8_t foo6 (float16x8_t a) +-{ +- return vaddq (a, (float16_t)23.6); +-} +-float32x4_t foo7 (float32x4_t a) +-{ +- return vaddq (a, (float32_t)23.46); +-} +-float16x8_t foo8 (float16x8_t a) +-{ +- return vaddq (a, 23.6); +-} +-float32x4_t foo9 (float32x4_t a) +-{ +- return vaddq (a, 23.46); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c +@@ -1,6 +1,7 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long" } */ ++/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long -Wno-incompatible-pointer-types" { target c } } */ ++/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long -fpermissive" { target c++ } } */ + #include "arm_mve.h" + + float f1; +@@ -10,35 +11,14 @@ float32_t f4; + __fp16 f5; + _Float16 f6; + +-int i1; +-short i2; +-long i3; +-long long i4; +-int8_t i5; +-int16_t i6; +-int32_t i7; +-int64_t i8; +- + float16x8_t floatvec; +-int16x8_t intvec; + +-void test(void) ++/* Test a few different supported ways of passing a scalar int value. ++The intrinsic vmulq was chosen arbitrarily, but it is representative of ++all intrinsics that take a non-const scalar value. */ ++void ++test_scalars (void) + { +- /* Test a few different supported ways of passing an int value. The +- intrinsic vmulq was chosen arbitrarily, but it is representative of +- all intrinsics that take a non-const scalar value. */ +- intvec = vmulq(intvec, 2); +- intvec = vmulq(intvec, (int32_t) 2); +- intvec = vmulq(intvec, (short) 2); +- intvec = vmulq(intvec, i1); +- intvec = vmulq(intvec, i2); +- intvec = vmulq(intvec, i3); +- intvec = vmulq(intvec, i4); +- intvec = vmulq(intvec, i5); +- intvec = vmulq(intvec, i6); +- intvec = vmulq(intvec, i7); +- intvec = vmulq(intvec, i8); +- + /* Test a few different supported ways of passing a float value. */ + floatvec = vmulq(floatvec, 0.5); + floatvec = vmulq(floatvec, 0.5f); +@@ -53,4 +33,25 @@ void test(void) + floatvec = vmulq(floatvec, (_Float16) 0.15); + } + ++/* Next, test a number of valid pointer overloads. */ ++void ++foo11 (__fp16 * addr, float16x8_t value) +{ -+ vector unsigned char v = {0xd, 0xd, 0xd, 0xd, 0xd, 0xd, 0xd, 0xd, -+ 0xd, 0xd, 0xd, 0xd, 0xd, 0xd, 0xd, 0xd}; -+ vector unsigned char res = vec_sld (v, v, 3); -+ return res; ++ vst1q (addr, value); +} + -+__attribute__ ((noipa)) -+vector signed short -+test2 () ++#ifndef __cplusplus ++void ++foo12 (_Float16 * addr, float16x8_t value) +{ -+ vector signed short v -+ = {0x7777, 0x7777, 0x7777, 0x7777, 0x7777, 0x7777, 0x7777, 0x7777}; -+ vector signed short res = vec_sld (v, v, 5); -+ return res; ++ vst1q (addr, value); +} ++#endif + -+__attribute__ ((noipa)) -+vector signed int -+test3 () ++void ++foo13 (float * addr, float32x4_t value) +{ -+ vector signed int v = {0xbbbbbbbb, 0xbbbbbbbb, 0xbbbbbbbb, 0xbbbbbbbb}; -+ vector signed int res = vec_sld (v, v, 7); -+ return res; ++ vst1q (addr, value); +} + -+__attribute__ ((noipa)) -+vector unsigned int -+test4 () + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c +@@ -1,7 +1,7 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long" } */ +- ++/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long -Wno-incompatible-pointer-types" { target c } } */ ++/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long -fpermissive" { target c++ } } */ + #include "arm_mve.h" + + int i1; +@@ -15,11 +15,12 @@ int64_t i8; + + int16x8_t intvec; + +-void test(void) ++/* Test a few different supported ways of passing a scalar int value. ++The intrinsic vmulq was chosen arbitrarily, but it is representative of ++all intrinsics that take a non-const scalar value. */ ++void ++test_scalars (void) + { +- /* Test a few different supported ways of passing an int value. The +- intrinsic vmulq was chosen arbitrarily, but it is representative of +- all intrinsics that take a non-const scalar value. */ + intvec = vmulq(intvec, 2); + intvec = vmulq(intvec, (int32_t) 2); + intvec = vmulq(intvec, (short) 2); +@@ -33,4 +34,67 @@ void test(void) + intvec = vmulq(intvec, i8); + } + ++/* Next, test a number of valid pointer overloads. */ ++void ++foo1 (signed char * addr, int8x16_t value) +{ -+ vector unsigned int v = {0x07070707, 0x07070707, 0x07070707, 0x07070707}; -+ vector unsigned int res = vec_sld (v, v, 9); -+ return res; ++ vst1q (addr, value); +} + -+__attribute__ ((noipa)) -+vector unsigned long long -+test5 () ++void ++foo2 (short * addr, int16x8_t value) +{ -+ vector unsigned long long v = {0x4545454545454545ll, 0x4545454545454545ll}; -+ vector unsigned long long res = vec_sld (v, v, 10); -+ return res; ++ vst1q (addr, value); +} + -+__attribute__ ((noipa)) -+vector float -+test6 () ++/* Glibc defines int32_t as 'int' while newlib defines it as 'long int'. ++ ++ Although these correspond to the same size, g++ complains when using the ++ 'wrong' version: ++ invalid conversion from 'long int*' to 'int32_t*' {aka 'int*'} [-fpermissive] ++ ++ The trick below is to make this test pass whether using glibc-based or ++ newlib-based toolchains. */ ++ ++#if defined(__GLIBC__) ++#define word_type int ++#else ++#define word_type long int ++#endif ++void ++foo3 (word_type * addr, int32x4_t value) +{ -+ U32b u; -+ u.i = 0x17171717; -+ vector float vf = {u.f, u.f, u.f, u.f}; -+ vector float res = vec_sld (vf, vf, 11); -+ return res; ++ vst1q (addr, value); +} + -+__attribute__ ((noipa)) -+vector double -+test7 () ++void ++foo5 (long long * addr, uint64x2_t value) +{ -+ U64b u; -+ u.i = 0x5454545454545454ll; -+ vector double vf = {u.f, u.f}; -+ vector double res = vec_sld (vf, vf, 13); -+ return res; ++ vldrdq_gather_offset (addr, value); +} + -new file mode 100644 ---- /dev/null -+++ b/src/gcc/testsuite/gcc.target/riscv/rvv/base/pr109535.c -@@ -0,0 +1,11 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d" } */ ++void ++foo6 (unsigned char * addr, uint8x16_t value) ++{ ++ vst1q (addr, value); ++} + -+#include "riscv_vector.h" ++void ++foo7 (unsigned short * addr, uint16x8_t value) ++{ ++ vst1q (addr, value); ++} + -+void foo(void *in1, void *in2, void *in3, void *out, size_t vl) { -+ vint8m1_t a = __riscv_vle8_v_i8m1(in1, vl); -+ vint8m1_t b = __riscv_vadd_vx_i8m1 (a, vl, vl); -+ __riscv_vse8_v_i8m1(out, b, vl); ++void ++foo8 (unsigned word_type * addr, uint32x4_t value) ++{ ++ vst1q (addr, value); +} + ---- a/src/gcc/testsuite/gfortran.dg/goacc/attach-descriptor.f90 -+++ b/src/gcc/testsuite/gfortran.dg/goacc/attach-descriptor.f90 -@@ -11,19 +11,19 @@ program att - integer, pointer :: myptr(:) ++void ++foo10 (unsigned long long * addr, uint64x2_t value) ++{ ++ vldrdq_gather_offset (addr, value); ++} ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_m.c ++++ /dev/null +@@ -1,48 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include +-mve_pred16_t p; +- +-int32x4_t fn1 (int32x4_t vecIdx) +-{ +- return vaddq_m(vuninitializedq_s32(), vecIdx, 1, p); +-} +- +-int16x8_t fn2 (int16x8_t vecIdx) +-{ +- return vaddq_m(vuninitializedq_s16(), vecIdx, 1, p); +-} +- +-int8x16_t fn3 (int8x16_t vecIdx) +-{ +- return vaddq_m(vuninitializedq_s8(), vecIdx, 1, p); +-} +- +-uint32x4_t fn4 (uint32x4_t vecIdx) +-{ +- return vaddq_m(vuninitializedq_u32(), vecIdx, 1, p); +-} +- +-uint16x8_t fn5 (uint16x8_t vecIdx) +-{ +- return vaddq_m(vuninitializedq_u16(), vecIdx, 1, p); +-} +- +-uint8x16_t fn6 (uint8x16_t vecIdx) +-{ +- return vaddq_m(vuninitializedq_u8(), vecIdx, 1, p); +-} +- +-float32x4_t fn7 (float32x4_t vecIdx) +-{ +- return vaddq_m(vuninitializedq_f32(), vecIdx, (float32_t) 1.23, p); +-} +- +-float16x8_t fn8 (float16x8_t vecIdx) +-{ +- return vaddq_m(vuninitializedq_f16(), vecIdx, (float16_t) 1.40, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_n.c ++++ /dev/null +@@ -1,31 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include +-int8x16_t foo (int8x16_t a, int16_t b) +-{ +- return vaddq (a, (b<<3)); +-} +-int16x8_t foo1 (int16x8_t a, int16_t b) +-{ +- return vaddq (a, (b<<3)); +-} +-int32x4_t foo2 (int32x4_t a, int16_t b) +-{ +- return vaddq (a, (b<<3)); +-} +-uint8x16_t foo3 (uint8x16_t a, int16_t b) +-{ +- return vaddq (a, (b<<3)); +-} +-uint16x8_t foo4 (uint16x8_t a, int16_t b) +-{ +- return vaddq (a, (b<<3)); +-} +-uint32x4_t foo5 (uint32x4_t a, int16_t b) +-{ +- return vaddq (a, (b<<3)); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u16.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint16x8_t +-foo1 (uint16x8_t inactive, int32_t a, mve_pred16_t p) +-{ +- return vddupq_m (inactive, a, 1, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint32x4_t +-foo1 (uint32x4_t inactive, int32_t a, mve_pred16_t p) +-{ +- return vddupq_m (inactive, a, 4, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u8.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint8x16_t +-foo1 (uint8x16_t inactive, int32_t a, mve_pred16_t p) +-{ +- return vddupq_m (inactive, a, 4, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u16.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint16x8_t +-foo1 (int32_t a) +-{ +- return vddupq_u16 (a, 4); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint32x4_t +-foo1 (int32_t a) +-{ +- return vddupq_u32 (a, 1); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u8.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint8x16_t +-foo1 (int32_t a) +-{ +- return vddupq_u8 (a, 1); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u16.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-uint16x8_t +-foo1 (int32_t a, mve_pred16_t p) +-{ +- return vddupq_x_u16 (a, 1, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u32.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-uint32x4_t +-foo1 (int32_t a, mve_pred16_t p) +-{ +- return vddupq_x_u32 (a, 4, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u8.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-uint8x16_t +-foo1 (int32_t a, mve_pred16_t p) +-{ +- return vddupq_x_u8 (a, 4, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint16x8_t +-foo1 (int32_t a, uint32_t b, mve_pred16_t p) +-{ +- return vdwdupq_x_u16 (a, b, 1, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint32x4_t +-foo1 (int32_t a, uint32_t b, mve_pred16_t p) +-{ +- return vdwdupq_x_u32 (a, b, 4, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint8x16_t +-foo1 (int32_t a, uint32_t b, mve_pred16_t p) +-{ +- return vdwdupq_x_u8 (a, b, 4, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u16.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint16x8_t +-foo1 (uint16x8_t inactive, int32_t a, mve_pred16_t p) +-{ +- return vidupq_m (inactive, a, 4, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u32.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-uint32x4_t +-foo1 (uint32x4_t inactive, int32_t a, mve_pred16_t p) +-{ +- return vidupq_m (inactive, a, 1, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u8.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint8x16_t +-foo1 (uint8x16_t inactive, int32_t a, mve_pred16_t p) +-{ +- return vidupq_m (inactive, a, 1, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u16.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint16x8_t +-foo1 (int32_t a) +-{ +- return vidupq_u16 (a, 4); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u32.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-uint32x4_t +-foo1 (int32_t a) +-{ +- return vidupq_u32 (a, 1); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u8.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint8x16_t +-foo1 (int32_t a) +-{ +- return vidupq_u8 (a, 1); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u16.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-uint16x8_t +-foo1 (int32_t a, mve_pred16_t p) +-{ +- return vidupq_x_u16 (a, 4, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u32.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-uint32x4_t +-foo1 (int32_t a, mve_pred16_t p) +-{ +- return vidupq_x_u32 (a, 1, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u8.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-uint8x16_t +-foo1 (int32_t a, mve_pred16_t p) +-{ +- return vidupq_x_u8 (a, 1, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u16.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint16x8_t +-foo1 (int32_t a, uint32_t b, mve_pred16_t p) +-{ +- return viwdupq_x_u16 (a, b, 2, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint32x4_t +-foo1 (int32_t a, uint32_t b, mve_pred16_t p) +-{ +- return viwdupq_x_u32 (a, b, 4, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u8.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint8x16_t +-foo1 (int32_t a, uint32_t b, mve_pred16_t p) +-{ +- return viwdupq_x_u8 (a, b, 8, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_s64.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-int64x2_t +-foo1 (int64_t * base, uint64x2_t offset) +-{ +- return vldrdq_gather_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_u64.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-uint64x2_t +-foo1 (uint64_t * base, uint64x2_t offset) +-{ +- return vldrdq_gather_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_s64.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-int64x2_t +-foo1 (int64_t * base, uint64x2_t offset, mve_pred16_t p) +-{ +- return vldrdq_gather_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_u64.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-uint64x2_t +-foo1 (uint64_t * base, uint64x2_t offset, mve_pred16_t p) +-{ +- return vldrdq_gather_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_s64.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-int64x2_t +-foo1 (int64_t * base, uint64x2_t offset) +-{ +- return vldrdq_gather_shifted_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_u64.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-uint64x2_t +-foo1 (uint64_t * base, uint64x2_t offset) +-{ +- return vldrdq_gather_shifted_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_s64.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-int64x2_t +-foo1 (int64_t * base, uint64x2_t offset, mve_pred16_t p) +-{ +- return vldrdq_gather_shifted_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_u64.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-uint64x2_t +-foo1 (uint64_t * base, uint64x2_t offset, mve_pred16_t p) +-{ +- return vldrdq_gather_shifted_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_f16.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo1 (float16_t * base, uint16x8_t offset) +-{ +- return vldrhq_gather_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s16.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-int16x8_t +-foo1 (int16_t * base, uint16x8_t offset) +-{ +- return vldrhq_gather_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s32.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-int32x4_t +-foo1 (int16_t * base, uint32x4_t offset) +-{ +- return vldrhq_gather_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u16.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-uint16x8_t +-foo1 (uint16_t * base, uint16x8_t offset) +-{ +- return vldrhq_gather_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint32x4_t +-foo1 (uint16_t * base, uint32x4_t offset) +-{ +- return vldrhq_gather_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_f16.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo1 (float16_t * base, uint16x8_t offset, mve_pred16_t p) +-{ +- return vldrhq_gather_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s16.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-int16x8_t +-foo1 (int16_t * base, uint16x8_t offset, mve_pred16_t p) +-{ +- return vldrhq_gather_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s32.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-int32x4_t +-foo1 (int16_t * base, uint32x4_t offset, mve_pred16_t p) +-{ +- return vldrhq_gather_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u16.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint16x8_t +-foo1 (uint16_t * base, uint16x8_t offset, mve_pred16_t p) +-{ +- return vldrhq_gather_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint32x4_t +-foo1 (uint16_t * base, uint32x4_t offset, mve_pred16_t p) +-{ +- return vldrhq_gather_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_f16.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo1 (float16_t * base, uint16x8_t offset) +-{ +- return vldrhq_gather_shifted_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s16.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-int16x8_t +-foo1 (int16_t * base, uint16x8_t offset) +-{ +- return vldrhq_gather_shifted_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-int32x4_t +-foo1 (int16_t * base, uint32x4_t offset) +-{ +- return vldrhq_gather_shifted_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u16.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint16x8_t +-foo1 (uint16_t * base, uint16x8_t offset) +-{ +- return vldrhq_gather_shifted_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint32x4_t +-foo1 (uint16_t * base, uint32x4_t offset) +-{ +- return vldrhq_gather_shifted_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_f16.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo1 (float16_t * base, uint16x8_t offset, mve_pred16_t p) +-{ +- return vldrhq_gather_shifted_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler "vldrht.f16" } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s16.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-int16x8_t +-foo1 (int16_t * base, uint16x8_t offset, mve_pred16_t p) +-{ +- return vldrhq_gather_shifted_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler "vldrht.u16" } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s32.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-int32x4_t +-foo1 (int16_t * base, uint32x4_t offset, mve_pred16_t p) +-{ +- return vldrhq_gather_shifted_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u16.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-uint16x8_t +-foo1 (uint16_t * base, uint16x8_t offset, mve_pred16_t p) +-{ +- return vldrhq_gather_shifted_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u32.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-uint32x4_t +-foo1 (uint16_t * base, uint32x4_t offset, mve_pred16_t p) +-{ +- return vldrhq_gather_shifted_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_f32.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo1 (float32_t * base, uint32x4_t offset) +-{ +- return vldrwq_gather_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_s32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-int32x4_t +-foo1 (int32_t * base, uint32x4_t offset) +-{ +- return vldrwq_gather_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_u32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint32x4_t +-foo1 (uint32_t * base, uint32x4_t offset) +-{ +- return vldrwq_gather_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_f32.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo1 (float32_t * base, uint32x4_t offset, mve_pred16_t p) +-{ +- return vldrwq_gather_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_s32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-int32x4_t +-foo1 (int32_t * base, uint32x4_t offset, mve_pred16_t p) +-{ +- return vldrwq_gather_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_u32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint32x4_t +-foo1 (uint32_t * base, uint32x4_t offset, mve_pred16_t p) +-{ +- return vldrwq_gather_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_f32.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo1 (float32_t * base, uint32x4_t offset) +-{ +- return vldrwq_gather_shifted_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_s32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-int32x4_t +-foo1 (int32_t * base, uint32x4_t offset) +-{ +- return vldrwq_gather_shifted_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_u32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint32x4_t +-foo1 (uint32_t * base, uint32x4_t offset) +-{ +- return vldrwq_gather_shifted_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_f32.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo1 (float32_t * base, uint32x4_t offset, mve_pred16_t p) +-{ +- return vldrwq_gather_shifted_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_s32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-int32x4_t +-foo1 (int32_t * base, uint32x4_t offset, mve_pred16_t p) +-{ +- return vldrwq_gather_shifted_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_u32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint32x4_t +-foo1 (uint32_t * base, uint32x4_t offset, mve_pred16_t p) +-{ +- return vldrwq_gather_shifted_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset.c ++++ /dev/null +@@ -1,141 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-int +-foowu32( uint32_t * pDataSrc, uint32_t * pDataDest) +-{ +- const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; +- const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; +- uint32x4_t vecIn1 = vldrwq_u32 ((uint32_t const *) pDataSrc); +- uint32x4_t vecIn2 = vldrwq_u32 ((uint32_t const *) &pDataSrc[4]); +- vstrwq_scatter_shifted_offset_u32 (pDataDest, vecOffs1, vecIn1); +- vstrwq_scatter_shifted_offset_u32 (pDataDest, vecOffs2, vecIn2); +- pDataDest[8] = pDataSrc[8]; +- return 0; +-} +- +-int +-foowf32( float32_t * pDataSrc, float32_t * pDataDest) +-{ +- const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; +- const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; +- float32x4_t vecIn1 = vldrwq_f32 ((float32_t const *) pDataSrc); +- float32x4_t vecIn2 = vldrwq_f32 ((float32_t const *) &pDataSrc[4]); +- vstrwq_scatter_shifted_offset_f32 (pDataDest, vecOffs1, vecIn1); +- vstrwq_scatter_shifted_offset_f32 (pDataDest, vecOffs2, vecIn2); +- pDataDest[8] = pDataSrc[8]; +- return 0; +-} +- +-int +-foohu16( uint16_t * pDataSrc, uint16_t * pDataDest) +-{ +- const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5}; +- const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14}; +- uint16x8_t vecIn1 = vldrhq_u16 ((uint16_t const *) pDataSrc); +- uint16x8_t vecIn2 = vldrhq_u16 ((uint16_t const *) &pDataSrc[8]); +- vstrhq_scatter_shifted_offset_u16 (pDataDest, vecOffs1, vecIn1); +- vstrhq_scatter_shifted_offset_u16 (pDataDest, vecOffs2, vecIn2); +- pDataDest[16] = pDataSrc[16]; +- return 0; +-} +- +-int +-foohu32( uint32_t * pDataSrc, uint32_t * pDataDest) +-{ +- const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; +- const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; +- uint32x4_t vecIn1 = vldrhq_u32 ((uint16_t const *) pDataSrc); +- uint32x4_t vecIn2 = vldrhq_u32 ((uint16_t const *) &pDataSrc[4]); +- vstrhq_scatter_shifted_offset_u32 ((uint16_t *)pDataDest, vecOffs1, vecIn1); +- vstrhq_scatter_shifted_offset_u32 ((uint16_t *)pDataDest, vecOffs2, vecIn2); +- pDataDest[8] = pDataSrc[8]; +- return 0; +-} +- +-int +-foohf16( float16_t * pDataSrc, float16_t * pDataDest) +-{ +- const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5}; +- const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14}; +- float16x8_t vecIn1 = vldrhq_f16 ((float16_t const *) pDataSrc); +- float16x8_t vecIn2 = vldrhq_f16 ((float16_t const *) &pDataSrc[8]); +- vstrhq_scatter_shifted_offset_f16 (pDataDest, vecOffs1, vecIn1); +- vstrhq_scatter_shifted_offset_f16 (pDataDest, vecOffs2, vecIn2); +- pDataDest[16] = pDataSrc[16]; +- return 0; +-} +- +-int +-foodu64( uint64_t * pDataSrc, uint64_t * pDataDest) +-{ +- const uint64x2_t vecOffs1 = { 0, 1}; +- const uint64x2_t vecOffs2 = { 2, 3}; +- uint32x4_t vecIn1 = vldrwq_u32 ((uint32_t const *) pDataSrc); +- uint32x4_t vecIn2 = vldrwq_u32 ((uint32_t const *) &pDataSrc[2]); +- +- vstrdq_scatter_shifted_offset_u64 (pDataDest, vecOffs1, (uint64x2_t) vecIn1); +- vstrdq_scatter_shifted_offset_u64 (pDataDest, vecOffs2, (uint64x2_t) vecIn2); +- +- pDataDest[2] = pDataSrc[2]; +- return 0; +-} +- +-int +-foows32( int32_t * pDataSrc, int32_t * pDataDest) +-{ +- const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; +- const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; +- int32x4_t vecIn1 = vldrwq_s32 ((int32_t const *) pDataSrc); +- int32x4_t vecIn2 = vldrwq_s32 ((int32_t const *) &pDataSrc[4]); +- vstrwq_scatter_shifted_offset_s32 (pDataDest, vecOffs1, vecIn1); +- vstrwq_scatter_shifted_offset_s32 (pDataDest, vecOffs2, vecIn2); +- pDataDest[8] = pDataSrc[8]; +- return 0; +-} +- +-int +-foohs16( int16_t * pDataSrc, int16_t * pDataDest) +-{ +- const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5}; +- const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14}; +- int16x8_t vecIn1 = vldrhq_s16 ((int16_t const *) pDataSrc); +- int16x8_t vecIn2 = vldrhq_s16 ((int16_t const *) &pDataSrc[8]); +- vstrhq_scatter_shifted_offset_s16 (pDataDest, vecOffs1, vecIn1); +- vstrhq_scatter_shifted_offset_s16 (pDataDest, vecOffs2, vecIn2); +- pDataDest[16] = pDataSrc[16]; +- return 0; +-} +- +-int +-foohs32( int32_t * pDataSrc, int32_t * pDataDest) +-{ +- const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; +- const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; +- int32x4_t vecIn1 = vldrhq_s32 ((int16_t const *) pDataSrc); +- int32x4_t vecIn2 = vldrhq_s32 ((int16_t const *) &pDataSrc[4]); +- vstrhq_scatter_shifted_offset_s32 ((int16_t *)pDataDest, vecOffs1, vecIn1); +- vstrhq_scatter_shifted_offset_s32 ((int16_t *)pDataDest, vecOffs2, vecIn2); +- pDataDest[8] = pDataSrc[8]; +- return 0; +-} +- +-int +-foods64( int64_t * pDataSrc, int64_t * pDataDest) +-{ +- const uint64x2_t vecOffs1 = { 0, 1}; +- const uint64x2_t vecOffs2 = { 2, 3}; +- int32x4_t vecIn1 = vldrwq_s32 ((int32_t const *) pDataSrc); +- int32x4_t vecIn2 = vldrwq_s32 ((int32_t const *) &pDataSrc[2]); +- +- vstrdq_scatter_shifted_offset_s64 (pDataDest, vecOffs1, (int64x2_t) vecIn1); +- vstrdq_scatter_shifted_offset_s64 (pDataDest, vecOffs2, (int64x2_t) vecIn2); +- +- pDataDest[2] = pDataSrc[2]; +- return 0; +-} +- +-/* { dg-final { scan-assembler-times "vstr\[a-z\]" 20 } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset_p.c ++++ /dev/null +@@ -1,142 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-mve_pred16_t __p; +-int +-foowu32( uint32_t * pDataSrc, uint32_t * pDataDest) +-{ +- const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; +- const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; +- uint32x4_t vecIn1 = vldrwq_z_u32 ((uint32_t const *) pDataSrc, __p); +- uint32x4_t vecIn2 = vldrwq_z_u32 ((uint32_t const *) &pDataSrc[4], __p); +- vstrwq_scatter_shifted_offset_p_u32 (pDataDest, vecOffs1, vecIn1, __p); +- vstrwq_scatter_shifted_offset_p_u32 (pDataDest, vecOffs2, vecIn2, __p); +- pDataDest[8] = pDataSrc[8]; +- return 0; +-} +- +-int +-foowf32( float32_t * pDataSrc, float32_t * pDataDest) +-{ +- const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; +- const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; +- float32x4_t vecIn1 = vldrwq_z_f32 ((float32_t const *) pDataSrc, __p); +- float32x4_t vecIn2 = vldrwq_z_f32 ((float32_t const *) &pDataSrc[4], __p); +- vstrwq_scatter_shifted_offset_p_f32 (pDataDest, vecOffs1, vecIn1, __p); +- vstrwq_scatter_shifted_offset_p_f32 (pDataDest, vecOffs2, vecIn2, __p); +- pDataDest[8] = pDataSrc[8]; +- return 0; +-} +- +-int +-foohu16( uint16_t * pDataSrc, uint16_t * pDataDest) +-{ +- const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5}; +- const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14}; +- uint16x8_t vecIn1 = vldrhq_z_u16 ((uint16_t const *) pDataSrc, __p); +- uint16x8_t vecIn2 = vldrhq_z_u16 ((uint16_t const *) &pDataSrc[8], __p); +- vstrhq_scatter_shifted_offset_p_u16 (pDataDest, vecOffs1, vecIn1, __p); +- vstrhq_scatter_shifted_offset_p_u16 (pDataDest, vecOffs2, vecIn2, __p); +- pDataDest[16] = pDataSrc[16]; +- return 0; +-} +- +-int +-foohu32( uint32_t * pDataSrc, uint32_t * pDataDest) +-{ +- const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; +- const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; +- uint32x4_t vecIn1 = vldrhq_z_u32 ((uint16_t const *) pDataSrc, __p); +- uint32x4_t vecIn2 = vldrhq_z_u32 ((uint16_t const *) &pDataSrc[4], __p); +- vstrhq_scatter_shifted_offset_p_u32 ((uint16_t *)pDataDest, vecOffs1, vecIn1, __p); +- vstrhq_scatter_shifted_offset_p_u32 ((uint16_t *)pDataDest, vecOffs2, vecIn2, __p); +- pDataDest[8] = pDataSrc[8]; +- return 0; +-} +- +-int +-foohf16( float16_t * pDataSrc, float16_t * pDataDest) +-{ +- const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5}; +- const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14}; +- float16x8_t vecIn1 = vldrhq_z_f16 ((float16_t const *) pDataSrc, __p); +- float16x8_t vecIn2 = vldrhq_z_f16 ((float16_t const *) &pDataSrc[8], __p); +- vstrhq_scatter_shifted_offset_p_f16 (pDataDest, vecOffs1, vecIn1, __p); +- vstrhq_scatter_shifted_offset_p_f16 (pDataDest, vecOffs2, vecIn2, __p); +- pDataDest[16] = pDataSrc[16]; +- return 0; +-} +- +-int +-foodu64( uint64_t * pDataSrc, uint64_t * pDataDest) +-{ +- const uint64x2_t vecOffs1 = { 0, 1}; +- const uint64x2_t vecOffs2 = { 2, 3}; +- uint32x4_t vecIn1 = vldrwq_z_u32 ((uint32_t const *) pDataSrc, __p); +- uint32x4_t vecIn2 = vldrwq_z_u32 ((uint32_t const *) &pDataSrc[2], __p); +- +- vstrdq_scatter_shifted_offset_p_u64 (pDataDest, vecOffs1, (uint64x2_t) vecIn1, __p); +- vstrdq_scatter_shifted_offset_p_u64 (pDataDest, vecOffs2, (uint64x2_t) vecIn2, __p); +- +- pDataDest[2] = pDataSrc[2]; +- return 0; +-} +- +-int +-foows32( int32_t * pDataSrc, int32_t * pDataDest) +-{ +- const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; +- const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; +- int32x4_t vecIn1 = vldrwq_z_s32 ((int32_t const *) pDataSrc, __p); +- int32x4_t vecIn2 = vldrwq_z_s32 ((int32_t const *) &pDataSrc[4], __p); +- vstrwq_scatter_shifted_offset_p_s32 (pDataDest, vecOffs1, vecIn1, __p); +- vstrwq_scatter_shifted_offset_p_s32 (pDataDest, vecOffs2, vecIn2, __p); +- pDataDest[8] = pDataSrc[8]; +- return 0; +-} +- +-int +-foohs16( int16_t * pDataSrc, int16_t * pDataDest) +-{ +- const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5}; +- const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14}; +- int16x8_t vecIn1 = vldrhq_z_s16 ((int16_t const *) pDataSrc, __p); +- int16x8_t vecIn2 = vldrhq_z_s16 ((int16_t const *) &pDataSrc[8], __p); +- vstrhq_scatter_shifted_offset_p_s16 (pDataDest, vecOffs1, vecIn1, __p); +- vstrhq_scatter_shifted_offset_p_s16 (pDataDest, vecOffs2, vecIn2, __p); +- pDataDest[16] = pDataSrc[16]; +- return 0; +-} +- +-int +-foohs32( int32_t * pDataSrc, int32_t * pDataDest) +-{ +- const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; +- const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; +- int32x4_t vecIn1 = vldrhq_z_s32 ((int16_t const *) pDataSrc, __p); +- int32x4_t vecIn2 = vldrhq_z_s32 ((int16_t const *) &pDataSrc[4], __p); +- vstrhq_scatter_shifted_offset_p_s32 ((int16_t *)pDataDest, vecOffs1, vecIn1, __p); +- vstrhq_scatter_shifted_offset_p_s32 ((int16_t *)pDataDest, vecOffs2, vecIn2, __p); +- pDataDest[8] = pDataSrc[8]; +- return 0; +-} +- +-int +-foods64( int64_t * pDataSrc, int64_t * pDataDest) +-{ +- const uint64x2_t vecOffs1 = { 0, 1}; +- const uint64x2_t vecOffs2 = { 2, 3}; +- int32x4_t vecIn1 = vldrwq_z_s32 ((int32_t const *) pDataSrc, __p); +- int32x4_t vecIn2 = vldrwq_z_s32 ((int32_t const *) &pDataSrc[2], __p); +- +- vstrdq_scatter_shifted_offset_p_s64 (pDataDest, vecOffs1, (int64x2_t) vecIn1, __p); +- vstrdq_scatter_shifted_offset_p_s64 (pDataDest, vecOffs2, (int64x2_t) vecIn2, __p); +- +- pDataDest[2] = pDataSrc[2]; +- return 0; +-} +- +-/* { dg-final { scan-assembler-times "vstr\[a-z\]t" 20 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshr.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshr.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ - !$acc enter data attach(myvar%arr2, myptr) --! { dg-final { scan-tree-dump-times "(?n)#pragma acc enter data map\\(attach:myvar\\.arr2 \\\[bias: 0\\\]\\) map\\(to:myptr \\\[pointer set, len: \[0-9\]+\\\]\\) map\\(attach:\\(integer\\(kind=4\\)\\\[0:\\\] \\*\\) myptr\\.data \\\[bias: 0\\\]\\);$" 1 "original" } } --! { dg-final { scan-tree-dump-times "(?n)#pragma omp target oacc_enter_data map\\(attach:myvar\\.arr2 \\\[bias: 0\\\]\\) map\\(to:myptr \\\[pointer set, len: \[0-9\]+\\\]\\) map\\(attach:myptr\\.data \\\[bias: 0\\\]\\)$" 1 "gimple" } } -+! { dg-final { scan-tree-dump-times "(?n)#pragma acc enter data map\\(attach:\\(integer\\(kind=4\\)\\\[0:\\\] \\* restrict\\) myvar\\.arr2\\.data \\\[bias: 0\\\]\\) map\\(to:myptr \\\[pointer set, len: \[0-9\]+\\\]\\) map\\(attach:\\(integer\\(kind=4\\)\\\[0:\\\] \\*\\) myptr\\.data \\\[bias: 0\\\]\\);$" 1 "original" } } -+! { dg-final { scan-tree-dump-times "(?n)#pragma omp target oacc_enter_data map\\(attach:myvar\\.arr2\\.data \\\[bias: 0\\\]\\) map\\(to:myptr \\\[pointer set, len: \[0-9\]+\\\]\\) map\\(attach:myptr\\.data \\\[bias: 0\\\]\\)$" 1 "gimple" } } + #include "arm_mve.h" - !$acc exit data detach(myvar%arr2, myptr) --! { dg-final { scan-tree-dump-times "(?n)#pragma acc exit data map\\(detach:myvar\\.arr2 \\\[bias: 0\\\]\\) map\\(to:myptr \\\[pointer set, len: \[0-9\]+\\\]\\) map\\(detach:\\(integer\\(kind=4\\)\\\[0:\\\] \\*\\) myptr\\.data \\\[bias: 0\\\]\\);$" 1 "original" } } --! { dg-final { scan-tree-dump-times "(?n)#pragma omp target oacc_exit_data map\\(detach:myvar\\.arr2 \\\[bias: 0\\\]\\) map\\(to:myptr \\\[pointer set, len: \[0-9\]+\\\]\\) map\\(detach:myptr\\.data \\\[bias: 0\\\]\\)$" 1 "gimple" } } -+! { dg-final { scan-tree-dump-times "(?n)#pragma acc exit data map\\(detach:\\(integer\\(kind=4\\)\\\[0:\\\] \\* restrict\\) myvar\\.arr2\\.data \\\[bias: 0\\\]\\) map\\(to:myptr \\\[pointer set, len: \[0-9\]+\\\]\\) map\\(detach:\\(integer\\(kind=4\\)\\\[0:\\\] \\*\\) myptr\\.data \\\[bias: 0\\\]\\);$" 1 "original" } } -+! { dg-final { scan-tree-dump-times "(?n)#pragma omp target oacc_exit_data map\\(detach:myvar\\.arr2\\.data \\\[bias: 0\\\]\\) map\\(to:myptr \\\[pointer set, len: \[0-9\]+\\\]\\) map\\(detach:myptr\\.data \\\[bias: 0\\\]\\)$" 1 "gimple" } } ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** sqrshr (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32_t +-sqrshr_reg (int32_t longval3, int32_t x) ++foo (int32_t value, int32_t shift) + { +- return sqrshr (longval3, x); ++ return sqrshr (value, shift); ++} ++ ++#ifdef __cplusplus + } ++#endif - ! Test valid usage and processing of the finalize clause. - !$acc exit data detach(myvar%arr2, myptr) finalize --! { dg-final { scan-tree-dump-times "(?n)#pragma acc exit data map\\(detach:myvar\\.arr2 \\\[bias: 0\\\]\\) map\\(to:myptr \\\[pointer set, len: \[0-9\]+\\\]\\) map\\(detach:\\(integer\\(kind=4\\)\\\[0:\\\] \\*\\) myptr\\.data \\\[bias: 0\\\]\\) finalize;$" 1 "original" } } -+! { dg-final { scan-tree-dump-times "(?n)#pragma acc exit data map\\(detach:\\(integer\\(kind=4\\)\\\[0:\\\] \\* restrict\\) myvar\\.arr2\\.data \\\[bias: 0\\\]\\) map\\(to:myptr \\\[pointer set, len: \[0-9\]+\\\]\\) map\\(detach:\\(integer\\(kind=4\\)\\\[0:\\\] \\*\\) myptr\\.data \\\[bias: 0\\\]\\) finalize;$" 1 "original" } } - ! For array-descriptor detaches, we no longer generate a "release" mapping - ! for the pointed-to data for gimplify.c to turn into "delete". Make sure - ! the mapping still isn't there. --! { dg-final { scan-tree-dump-times "(?n)#pragma omp target oacc_exit_data map\\(force_detach:myvar\\.arr2 \\\[bias: 0\\\]\\) map\\(to:myptr \\\[pointer set, len: \[0-9\]+\\\]\\) map\\(force_detach:myptr\\.data \\\[bias: 0\\\]\\) finalize$" 1 "gimple" } } -+! { dg-final { scan-tree-dump-times "(?n)#pragma omp target oacc_exit_data map\\(force_detach:myvar\\.arr2\\.data \\\[bias: 0\\\]\\) map\\(to:myptr \\\[pointer set, len: \[0-9\]+\\\]\\) map\\(force_detach:myptr\\.data \\\[bias: 0\\\]\\) finalize$" 1 "gimple" } } +-/* { dg-final { scan-assembler "sqrshr\\tr\[0-9\]+, r\[0-9\]+" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ - end program att -new file mode 100644 ---- /dev/null -+++ b/src/gcc/testsuite/gfortran.dg/goacc/pr109622-5.f90 -@@ -0,0 +1,44 @@ -+! { dg-do compile } + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif + -+implicit none ++/* ++**foo: ++** ... ++** sqrshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #48, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int64_t +-sqrshrl_reg (int64_t longval3, int32_t x) ++foo (int64_t value, int32_t shift) + { +- return sqrshrl_sat48 (longval3, x); ++ return sqrshrl_sat48 (value, shift); ++} + -+type t -+integer :: foo -+character(len=8) :: bar -+integer :: qux(5) -+end type t ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "sqrshrl\\tr\[0-9\]+, r\[0-9\]+, #48, r\[0-9\]+" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif + -+type(t) :: var ++/* ++**foo: ++** ... ++** sqshl (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-sqshl_imm (int32_t longval3) ++foo (int32_t value) + { +- return sqshl (longval3, 25); ++ return sqshl (value, 1); ++} + -+var%foo = 3 -+var%bar = "HELLOOMP" -+var%qux = (/ 1, 2, 3, 4, 5 /) ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "sqshl\\tr\[0-9\]+, #25" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshll.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshll.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif + -+!$acc enter data copyin(var) ++/* ++**foo: ++** ... ++** sqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-sqshll_imm(int64_t value) ++foo (int64_t value) + { +- return sqshll (value, 21); ++ return sqshll (value, 1); ++} + -+!$acc enter data attach(var%foo) -+! { dg-error "'attach' clause argument must be ALLOCATABLE or a POINTER" "" { target *-*-* } .-1 } -+!$acc enter data attach(var%bar) -+! { dg-error "'attach' clause argument must be ALLOCATABLE or a POINTER" "" { target *-*-* } .-1 } -+!$acc enter data attach(var%qux) -+! { dg-error "'attach' clause argument must be ALLOCATABLE or a POINTER" "" { target *-*-* } .-1 } ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "sqshll\\tr\[0-9\]+, r\[0-9\]+, #21" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif + -+!$acc serial -+var%foo = 5 -+var%bar = "GOODBYE!" -+var%qux = (/ 6, 7, 8, 9, 10 /) -+!$acc end serial ++/* ++**foo: ++** ... ++** srshr (?:ip|fp|r[0-9]+), #1(?: @.*|) ++** ... ++*/ + int32_t +-srshr_imm (int32_t longval3) ++foo (int32_t value) + { +- return srshr (longval3, 25); ++ return srshr (value, 1); ++} + -+!$acc exit data detach(var%qux) -+! { dg-error "'detach' clause argument must be ALLOCATABLE or a POINTER" "" { target *-*-* } .-1 } -+!$acc exit data detach(var%bar) -+! { dg-error "'detach' clause argument must be ALLOCATABLE or a POINTER" "" { target *-*-* } .-1 } -+!$acc exit data detach(var%foo) -+! { dg-error "'detach' clause argument must be ALLOCATABLE or a POINTER" "" { target *-*-* } .-1 } ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "srshr\\tr\[0-9\]+, #25" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif + -+!$acc exit data copyout(var) ++/* ++**foo: ++** ... ++** srshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|) ++** ... ++*/ + int64_t +-srshrl_imm(int64_t value) ++foo (int64_t value) + { +- return srshrl (value, 21); ++ return srshrl (value, 1); ++} + -+if (var%foo.ne.5) stop 1 -+if (var%bar.ne."GOODBYE!") stop 2 ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "srshrl\\tr\[0-9\]+, r\[0-9\]+, #21" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshl.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshl.c +@@ -1,13 +1,40 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif + -+end -new file mode 100644 ---- /dev/null -+++ b/src/gcc/testsuite/gfortran.dg/goacc/pr109622-6.f90 -@@ -0,0 +1,8 @@ -+! { dg-do compile } ++/* ++**foo: ++** ... ++** uqrshl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32_t +-uqrshl_reg (uint32_t longval3, int32_t x) ++foo (uint32_t value, int32_t shift) + { +- return uqrshl (longval3, x); ++ return uqrshl (value, shift); ++} + -+implicit none -+integer :: x -+!$acc enter data attach(x) -+! { dg-error "'attach' clause argument must be ALLOCATABLE or a POINTER" "" { target *-*-* } .-1 } ++/* ++**foo1: ++** ... ++** uqrshl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32_t ++foo1 (int32_t shift) ++{ ++ return uqrshl (1, shift); ++} + -+end ---- a/src/gcc/testsuite/lib/target-supports.exp -+++ b/src/gcc/testsuite/lib/target-supports.exp -@@ -8555,7 +8555,8 @@ proc check_effective_target_vect_call_copysignf { } { - return [check_cached_effective_target_indexed vect_call_copysignf { - expr { [istarget i?86-*-*] || [istarget x86_64-*-*] - || [istarget powerpc*-*-*] -- || [istarget aarch64*-*-*] }}] -+ || [istarget aarch64*-*-*] -+ || [istarget amdgcn-*-*] }}] ++#ifdef __cplusplus } ++#endif - # Return 1 if the target supports hardware square root instructions. -@@ -8591,7 +8592,8 @@ proc check_effective_target_vect_call_sqrtf { } { +-/* { dg-final { scan-assembler "uqrshl\\tr\[0-9\]+, r\[0-9\]+" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c +@@ -1,13 +1,40 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** uqrshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #48, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint64_t +-uqrshll_reg (uint64_t longval3, int32_t x) ++foo (uint64_t value, int32_t shift) + { +- return uqrshll_sat48 (longval3, x); ++ return uqrshll_sat48 (value, shift); ++} ++ ++/* ++**foo1: ++** ... ++** uqrshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #48, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint64_t ++foo1 (int32_t shift) ++{ ++ return uqrshll_sat48 (1, shift); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "uqrshll\\tr\[0-9\]+, r\[0-9\]+, #48, r\[0-9\]+" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** uqshl (?:ip|fp|r[0-9]+), #1(?: @.*|) ++** ... ++*/ + uint32_t +-uqshl_imm (uint32_t longval3) ++foo (uint32_t value) + { +- return uqshl (longval3, 21); ++ return uqshl (value, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "uqshl\\tr\[0-9\]+, #21" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|) ++** ... ++*/ + uint64_t +-uqshll_imm(uint64_t value) ++foo (uint64_t value) + { +- return uqshll (value, 21); ++ return uqshll (value, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "uqshll\\tr\[0-9\]+, r\[0-9\]+, #21" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c +@@ -1,13 +1,40 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + +-uint64_t +-urshr_imm (uint32_t longval3) ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** urshr (?:ip|fp|r[0-9]+), #1(?: @.*|) ++** ... ++*/ ++uint32_t ++foo (uint32_t value) ++{ ++ return urshr (value, 1); ++} ++ ++/* ++**foo1: ++** ... ++** urshr (?:ip|fp|r[0-9]+), #1(?: @.*|) ++** ... ++*/ ++uint32_t ++foo1 () + { +- return urshr (longval3, 21); ++ return urshr (1, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "urshr\\tr\[0-9\]+, #21" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c +@@ -1,13 +1,40 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|) ++** ... ++*/ + uint64_t +-urshrl_imm(uint64_t value) ++foo (uint64_t value) + { +- return urshrl (value, 21); ++ return urshrl (value, 1); ++} ++ ++/* ++**foo1: ++** ... ++** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|) ++** ... ++*/ ++uint64_t ++foo1 () ++{ ++ return urshrl (1, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "urshrl\\tr\[0-9\]+, r\[0-9\]+, #21" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c +@@ -1,23 +1,57 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vadcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry_out, mve_pred16_t p) ++foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred16_t p) + { + return vadciq_m_s32 (inactive, a, b, carry_out, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vadcit.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vadcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry_out, mve_pred16_t p) ++foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred16_t p) + { + return vadciq_m (inactive, a, b, carry_out, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vadcit.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c +@@ -1,23 +1,57 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vadcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry_out, mve_pred16_t p) ++foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_pred16_t p) + { + return vadciq_m_u32 (inactive, a, b, carry_out, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vadcit.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vadcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry_out, mve_pred16_t p) ++foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_pred16_t p) + { + return vadciq_m (inactive, a, b, carry_out, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vadcit.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vadci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t a, int32x4_t b, unsigned * carry_out) ++foo (int32x4_t a, int32x4_t b, unsigned *carry_out) + { + return vadciq_s32 (a, b, carry_out); + } + +-/* { dg-final { scan-assembler "vadci.i32" } } */ + ++/* ++**foo1: ++** ... ++** vadci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t a, int32x4_t b, unsigned * carry_out) ++foo1 (int32x4_t a, int32x4_t b, unsigned *carry_out) + { + return vadciq (a, b, carry_out); + } + +-/* { dg-final { scan-assembler "vadci.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vadci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t a, uint32x4_t b, unsigned * carry_out) ++foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out) + { + return vadciq_u32 (a, b, carry_out); + } + +-/* { dg-final { scan-assembler "vadci.i32" } } */ + ++/* ++**foo1: ++** ... ++** vadci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32x4_t a, uint32x4_t b, unsigned * carry_out) ++foo1 (uint32x4_t a, uint32x4_t b, unsigned *carry_out) + { + return vadciq (a, b, carry_out); + } + +-/* { dg-final { scan-assembler "vadci.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c +@@ -1,23 +1,69 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vadct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry, mve_pred16_t p) ++foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t p) + { + return vadcq_m_s32 (inactive, a, b, carry, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vadct.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vadct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry, mve_pred16_t p) ++foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t p) + { + return vadcq_m (inactive, a, b, carry, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vadct.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c +@@ -1,23 +1,69 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vadct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry, mve_pred16_t p) ++foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred16_t p) + { + return vadcq_m_u32 (inactive, a, b, carry, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vadct.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vadct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry, mve_pred16_t p) ++foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred16_t p) + { + return vadcq_m (inactive, a, b, carry, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vadct.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c +@@ -1,21 +1,61 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vadc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t a, int32x4_t b, unsigned * carry) ++foo (int32x4_t a, int32x4_t b, unsigned *carry) + { + return vadcq_s32 (a, b, carry); + } + +-/* { dg-final { scan-assembler "vadc.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vadc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t a, int32x4_t b, unsigned * carry) ++foo1 (int32x4_t a, int32x4_t b, unsigned *carry) + { + return vadcq (a, b, carry); + } + +-/* { dg-final { scan-assembler "vadc.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c +@@ -1,21 +1,61 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vadc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t a, uint32x4_t b, unsigned * carry) ++foo (uint32x4_t a, uint32x4_t b, unsigned *carry) + { + return vadcq_u32 (a, b, carry); + } + +-/* { dg-final { scan-assembler "vadc.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vadc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32x4_t a, uint32x4_t b, unsigned * carry) ++foo1 (uint32x4_t a, uint32x4_t b, unsigned *carry) + { + return vadcq (a, b, carry); + } + +-/* { dg-final { scan-assembler "vadc.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p) +-{ +- return vaddq_m (inactive, a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p) +-{ +- return vaddq_m (inactive, a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo1 (float16x8_t a, float16_t b, mve_pred16_t p) +-{ +- return vaddq_x (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo1 (float32x4_t a, float32_t b, mve_pred16_t p) +-{ +- return vaddq_x (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b) + { + return vandq_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ + ++/* ++**foo1: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b) + { + return vandq (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b) + { + return vandq_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ + ++/* ++**foo1: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b) + { + return vandq (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vandq_m_f16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vandq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vandq_m_f32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vandq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vandq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vandq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vandq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vandq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vandq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vandq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vandq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vandq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vandq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vandq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vandq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vandq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vandq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ + ++/* ++**foo1: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vandq (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vandq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ + ++/* ++**foo1: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vandq (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vandq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ + ++/* ++**foo1: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vandq (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { + return vandq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ + ++/* ++**foo1: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vandq (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { + return vandq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ + ++/* ++**foo1: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vandq (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { + return vandq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ + ++/* ++**foo1: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vandq (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vandq_x_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vandq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vandq_x_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vandq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vandq_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vandq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vandq_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vandq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vandq_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vandq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vandq_x_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vandq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vandq_x_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vandq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vandq_x_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vandq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f16.c +@@ -1,22 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b) + { + return vbicq_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ + ++/* ++**foo1: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b) + { + return vbicq (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f32.c +@@ -1,22 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b) + { + return vbicq_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ + ++/* ++**foo1: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b) + { + return vbicq (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vbicq_m_f16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vbicq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vbicq_m_f32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vbicq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, mve_pred16_t p) + { +- return vbicq_m_n_s16 (a, 16, p); ++ return vbicq_m_n_s16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, mve_pred16_t p) + { +- return vbicq_m_n (a, 16, p); ++ return vbicq_m_n (a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, mve_pred16_t p) + { + return vbicq_m_n_s32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, mve_pred16_t p) + { + return vbicq_m_n (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, mve_pred16_t p) + { + return vbicq_m_n_u16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, mve_pred16_t p) + { + return vbicq_m_n (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, mve_pred16_t p) + { + return vbicq_m_n_u32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, mve_pred16_t p) + { + return vbicq_m_n (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vbicq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vbicq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vbicq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vbicq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vbicq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vbicq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vbicq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vbicq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vbicq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vbicq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vbicq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vbicq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s16.c +@@ -1,20 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbic.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a) + { + return vbicq_n_s16 (a, 1); + } + ++ ++/* ++**foo1: ++** ... ++** vbic.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a) + { + return vbicq (a, 1); + } + +-/* { dg-final { scan-assembler-times "vbic.i16" 2 } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s32.c +@@ -1,20 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbic.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a) + { + return vbicq_n_s32 (a, 1); + } + ++ ++/* ++**foo1: ++** ... ++** vbic.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a) + { + return vbicq (a, 1); + } + +-/* { dg-final { scan-assembler-times "vbic.i32" 2 } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u16.c +@@ -1,20 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbic.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a) + { + return vbicq_n_u16 (a, 1); + } + ++ ++/* ++**foo1: ++** ... ++** vbic.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a) + { + return vbicq (a, 1); + } + +-/* { dg-final { scan-assembler-times "vbic.i16" 2 } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u32.c +@@ -1,20 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbic.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a) + { + return vbicq_n_u32 (a, 1); + } + ++ ++/* ++**foo1: ++** ... ++** vbic.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a) + { + return vbicq (a, 1); + } + +-/* { dg-final { scan-assembler-times "vbic.i32" 2 } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s16.c +@@ -1,22 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vbicq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ + ++/* ++**foo1: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vbicq (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s32.c +@@ -1,22 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vbicq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ + ++/* ++**foo1: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vbicq (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s8.c +@@ -1,22 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vbicq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ + ++/* ++**foo1: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vbicq (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u16.c +@@ -1,22 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { + return vbicq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ + ++/* ++**foo1: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vbicq (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u32.c +@@ -1,22 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { + return vbicq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ + ++/* ++**foo1: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vbicq (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u8.c +@@ -1,22 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { + return vbicq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ + ++/* ++**foo1: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vbicq (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vbicq_x_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vbicq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vbicq_x_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vbicq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vbicq_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vbicq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vbicq_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vbicq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vbicq_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vbicq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vbicq_x_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vbicq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vbicq_x_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vbicq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vbicq_x_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vbicq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m_n_f16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m_n_f32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m_n_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m_n_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m_n_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m_n_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m_n_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m_n_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbrsr.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, int32_t b) + { + return vbrsrq_n_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.16" } } */ + ++/* ++**foo1: ++** ... ++** vbrsr.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, int32_t b) + { + return vbrsrq (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbrsr.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, int32_t b) + { + return vbrsrq_n_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.32" } } */ + ++/* ++**foo1: ++** ... ++** vbrsr.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, int32_t b) + { + return vbrsrq (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbrsr.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32_t b) + { + return vbrsrq_n_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.16" } } */ + ++/* ++**foo1: ++** ... ++** vbrsr.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32_t b) + { + return vbrsrq (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbrsr.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b) + { + return vbrsrq_n_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.32" } } */ + ++/* ++**foo1: ++** ... ++** vbrsr.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b) + { + return vbrsrq (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbrsr.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int32_t b) + { + return vbrsrq_n_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.8" } } */ + ++/* ++**foo1: ++** ... ++** vbrsr.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int32_t b) + { + return vbrsrq (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbrsr.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32_t b) + { + return vbrsrq_n_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.16" } } */ + ++/* ++**foo1: ++** ... ++** vbrsr.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32_t b) + { + return vbrsrq (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbrsr.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32_t b) + { + return vbrsrq_n_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.32" } } */ + ++/* ++**foo1: ++** ... ++** vbrsr.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, int32_t b) + { + return vbrsrq (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbrsr.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int32_t b) + { + return vbrsrq_n_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.8" } } */ + ++/* ++**foo1: ++** ... ++** vbrsr.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int32_t b) + { + return vbrsrq (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x_n_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x_n_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x_n_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x_n_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x_n_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x_n_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x_n_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x_n_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c +@@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b) + } + + /* +-**foo2: ++**foo2: { xfail *-*-* } + ** ... + ** vcmp.u16 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) + ** ... +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c +@@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b) + } + + /* +-**foo2: ++**foo2: { xfail *-*-* } + ** ... + ** vcmp.u32 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) + ** ... +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c +@@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b) + } + + /* +-**foo2: ++**foo2: { xfail *-*-* } + ** ... + ** vcmp.u8 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) + ** ... +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float16x8_t a, float16_t b, mve_pred16_t p) +-{ +- return vcmpeqq_m (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float32x4_t a, float32_t b, mve_pred16_t p) +-{ +- return vcmpeqq_m (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float16x8_t a, float16_t b) +-{ +- return vcmpeqq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c +@@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b) + } + + /* +-**foo2: ++**foo2: { xfail *-*-* } + ** ... + ** vcmp.f16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) + ** ... +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float32x4_t a, float32_t b) +-{ +- return vcmpeqq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c +@@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b) + } + + /* +-**foo2: ++**foo2: { xfail *-*-* } + ** ... + ** vcmp.f32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) + ** ... +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c +@@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b) + } + + /* +-**foo2: ++**foo2: { xfail *-*-* } + ** ... + ** vcmp.i16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) + ** ... +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c +@@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b) + } + + /* +-**foo2: ++**foo2: { xfail *-*-* } + ** ... + ** vcmp.i32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) + ** ... +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c +@@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b) + } + + /* +-**foo2: ++**foo2: { xfail *-*-* } + ** ... + ** vcmp.i8 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) + ** ... +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float16x8_t a, float16_t b, mve_pred16_t p) +-{ +- return vcmpgeq_m (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float32x4_t a, float32_t b, mve_pred16_t p) +-{ +- return vcmpgeq_m (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float16x8_t a, float16_t b) +-{ +- return vcmpgeq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c +@@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b) + } + + /* +-**foo2: ++**foo2: { xfail *-*-* } + ** ... + ** vcmp.f16 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) + ** ... +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float32x4_t a, float32_t b) +-{ +- return vcmpgeq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c +@@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b) + } + + /* +-**foo2: ++**foo2: { xfail *-*-* } + ** ... + ** vcmp.f32 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) + ** ... +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float16x8_t a, float16_t b, mve_pred16_t p) +-{ +- return vcmpgtq_m (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float32x4_t a, float32_t b, mve_pred16_t p) +-{ +- return vcmpgtq_m (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float16x8_t a, float16_t b) +-{ +- return vcmpgtq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c +@@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b) + } + + /* +-**foo2: ++**foo2: { xfail *-*-* } + ** ... + ** vcmp.f16 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) + ** ... +@@ -56,4 +56,4 @@ foo2 (float16x8_t a) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float32x4_t a, float32_t b) +-{ +- return vcmpgtq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c +@@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b) + } + + /* +-**foo2: ++**foo2: { xfail *-*-* } + ** ... + ** vcmp.f32 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) + ** ... +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c +@@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b) + } + + /* +-**foo2: ++**foo2: { xfail *-*-* } + ** ... + ** vcmp.u16 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) + ** ... +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c +@@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b) + } + + /* +-**foo2: ++**foo2: { xfail *-*-* } + ** ... + ** vcmp.u32 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) + ** ... +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c +@@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b) + } + + /* +-**foo2: ++**foo2: { xfail *-*-* } + ** ... + ** vcmp.u8 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) + ** ... +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float16x8_t a, float16_t b, mve_pred16_t p) +-{ +- return vcmpleq_m (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float32x4_t a, float32_t b, mve_pred16_t p) +-{ +- return vcmpleq_m (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float16x8_t a, float16_t b) +-{ +- return vcmpleq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c +@@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b) + } + + /* +-**foo2: ++**foo2: { xfail *-*-* } + ** ... + ** vcmp.f16 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) + ** ... +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float32x4_t a, float32_t b) +-{ +- return vcmpleq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c +@@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b) + } + + /* +-**foo2: ++**foo2: { xfail *-*-* } + ** ... + ** vcmp.f32 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) + ** ... +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float16x8_t a, float16_t b, mve_pred16_t p) +-{ +- return vcmpltq_m (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float32x4_t a, float32_t b, mve_pred16_t p) +-{ +- return vcmpltq_m (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float16x8_t a, float16_t b) +-{ +- return vcmpltq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c +@@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b) + } + + /* +-**foo2: ++**foo2: { xfail *-*-* } + ** ... + ** vcmp.f16 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) + ** ... +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float32x4_t a, float32_t b) +-{ +- return vcmpltq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c +@@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b) + } + + /* +-**foo2: ++**foo2: { xfail *-*-* } + ** ... + ** vcmp.f32 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) + ** ... +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float16x8_t a, float16_t b, mve_pred16_t p) +-{ +- return vcmpneq_m (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float32x4_t a, float32_t b, mve_pred16_t p) +-{ +- return vcmpneq_m (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float16x8_t a, float16_t b) +-{ +- return vcmpneq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c +@@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b) + } + + /* +-**foo2: ++**foo2: { xfail *-*-* } + ** ... + ** vcmp.f16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) + ** ... +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float32x4_t a, float32_t b) +-{ +- return vcmpneq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c +@@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b) + } + + /* +-**foo2: ++**foo2: { xfail *-*-* } + ** ... + ** vcmp.f32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) + ** ... +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c +@@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b) + } + + /* +-**foo2: ++**foo2: { xfail *-*-* } + ** ... + ** vcmp.i16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) + ** ... +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c +@@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b) + } + + /* +-**foo2: ++**foo2: { xfail *-*-* } + ** ... + ** vcmp.i32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) + ** ... +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c +@@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b) + } + + /* +-**foo2: ++**foo2: { xfail *-*-* } + ** ... + ** vcmp.i8 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) + ** ... +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c +@@ -1,21 +1,44 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vctp.16 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32_t a) + { + return vctp16q (a); + } + +-/* { dg-final { scan-assembler "vctp.16" } } */ +- ++/* ++**foo1: ++** ... ++** vctp.16 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t +-foo1 (uint32_t a) ++foo1 () + { +- return vctp16q (a); ++ return vctp16q (1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vctp.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c +@@ -1,22 +1,52 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vctpt.16 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32_t a, mve_pred16_t p) + { + return vctp16q_m (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vctpt.16" } } */ +- ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vctpt.16 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t +-foo1 (uint32_t a, mve_pred16_t p) ++foo1 (mve_pred16_t p) + { +- return vctp16q_m (a, p); ++ return vctp16q_m (1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c +@@ -1,21 +1,44 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vctp.32 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32_t a) + { + return vctp32q (a); + } + +-/* { dg-final { scan-assembler "vctp.32" } } */ +- ++/* ++**foo1: ++** ... ++** vctp.32 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t +-foo1 (uint32_t a) ++foo1 () + { +- return vctp32q (a); ++ return vctp32q (1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vctp.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c +@@ -1,22 +1,52 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vctpt.32 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32_t a, mve_pred16_t p) + { + return vctp32q_m (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vctpt.32" } } */ +- ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vctpt.32 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t +-foo1 (uint32_t a, mve_pred16_t p) ++foo1 (mve_pred16_t p) + { +- return vctp32q_m (a, p); ++ return vctp32q_m (1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c +@@ -1,21 +1,44 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vctp.64 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32_t a) + { + return vctp64q (a); + } + +-/* { dg-final { scan-assembler "vctp.64" } } */ +- ++/* ++**foo1: ++** ... ++** vctp.64 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t +-foo1 (uint32_t a) ++foo1 () + { +- return vctp64q (a); ++ return vctp64q (1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vctp.64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c +@@ -1,22 +1,52 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vctpt.64 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32_t a, mve_pred16_t p) + { + return vctp64q_m (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vctpt.64" } } */ +- ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vctpt.64 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t +-foo1 (uint32_t a, mve_pred16_t p) ++foo1 (mve_pred16_t p) + { +- return vctp64q_m (a, p); ++ return vctp64q_m (1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c +@@ -1,21 +1,44 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vctp.8 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32_t a) + { + return vctp8q (a); + } + +-/* { dg-final { scan-assembler "vctp.8" } } */ +- ++/* ++**foo1: ++** ... ++** vctp.8 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t +-foo1 (uint32_t a) ++foo1 () + { +- return vctp8q (a); ++ return vctp8q (1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vctp.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c +@@ -1,22 +1,52 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vctpt.8 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32_t a, mve_pred16_t p) + { + return vctp8q_m (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vctpt.8" } } */ +- ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vctpt.8 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t +-foo1 (uint32_t a, mve_pred16_t p) ++foo1 (mve_pred16_t p) + { +- return vctp8q_m (a, p); ++ return vctp8q_m (1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtat.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtaq_m_s16_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtat.s16.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtat.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtaq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtat.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtaq_m_s32_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtat.s32.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtat.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtaq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtat.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtaq_m_u16_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtat.u16.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtat.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtaq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtat.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtaq_m_u32_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtat.u32.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtat.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtaq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvta.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (float16x8_t a) + { + return vcvtaq_s16_f16 (a); + } + +-/* { dg-final { scan-assembler "vcvta.s16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvta.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (float32x4_t a) + { + return vcvtaq_s32_f32 (a); + } + +-/* { dg-final { scan-assembler "vcvta.s32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvta.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (float16x8_t a) + { +- return vcvtaq_u16_f16 (a); ++ return vcvtaq_u16_f16 (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vcvta.u16.f16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvta.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (float32x4_t a) + { +- return vcvtaq_u32_f32 (a); ++ return vcvtaq_u32_f32 (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vcvta.u32.f32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtat.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vcvtaq_x_s16_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtat.s16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtat.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vcvtaq_x_s32_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtat.s32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtat.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vcvtaq_x_u16_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtat.u16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtat.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vcvtaq_x_u32_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtat.u32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtb.f16.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float32x4_t b) + { + return vcvtbq_f16_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vcvtb.f16.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtb.f32.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float16x8_t a) + { + return vcvtbq_f32_f16 (a); + } + +-/* { dg-final { scan-assembler "vcvtb.f32.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c +@@ -1,22 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtbt.f16.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float32x4_t b, mve_pred16_t p) + { + return vcvtbq_m_f16_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtbt.f16.f32" } } */ +- +-float16x8_t +-foo1 (float16x8_t a, float32x4_t b, mve_pred16_t p) +-{ +- return vcvtbq_m (a, b, p); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c +@@ -1,22 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtbt.f32.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtbq_m_f32_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtbt.f32.f16" } } */ +- +-float32x4_t +-foo1 (float32x4_t inactive, float16x8_t a, mve_pred16_t p) +-{ +- return vcvtbq_m (inactive, a, p); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtbt.f32.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float16x8_t a, mve_pred16_t p) + { + return vcvtbq_x_f32_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtbt.f32.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtmt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtmq_m_s16_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtmt.s16.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtmt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtmq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtmt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtmq_m_s32_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtmt.s32.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtmt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtmq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtmt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtmq_m_u16_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtmt.u16.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtmt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtmq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtmt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtmq_m_u32_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtmt.u32.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtmt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtmq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtm.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (float16x8_t a) + { + return vcvtmq_s16_f16 (a); + } + +-/* { dg-final { scan-assembler "vcvtm.s16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtm.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (float32x4_t a) + { + return vcvtmq_s32_f32 (a); + } + +-/* { dg-final { scan-assembler "vcvtm.s32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtm.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (float16x8_t a) + { +- return vcvtmq_u16_f16 (a); ++ return vcvtmq_u16_f16 (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vcvtm.u16.f16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtm.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (float32x4_t a) + { +- return vcvtmq_u32_f32 (a); ++ return vcvtmq_u32_f32 (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vcvtm.u32.f32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtmt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vcvtmq_x_s16_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtmt.s16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtmt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vcvtmq_x_s32_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtmt.s32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtmt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vcvtmq_x_u16_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtmt.u16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtmt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vcvtmq_x_u32_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtmt.u32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtnt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtnq_m_s16_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtnt.s16.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtnt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtnq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtnt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtnq_m_s32_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtnt.s32.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtnt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtnq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtnt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtnq_m_u16_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtnt.u16.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtnt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtnq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtnt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtnq_m_u32_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtnt.u32.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtnt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtnq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtn.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (float16x8_t a) + { + return vcvtnq_s16_f16 (a); + } + +-/* { dg-final { scan-assembler "vcvtn.s16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtn.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (float32x4_t a) + { + return vcvtnq_s32_f32 (a); + } + +-/* { dg-final { scan-assembler "vcvtn.s32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtn.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (float16x8_t a) + { +- return vcvtnq_u16_f16 (a); ++ return vcvtnq_u16_f16 (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vcvtn.u16.f16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtn.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (float32x4_t a) + { + return vcvtnq_u32_f32 (a); + } + +-/* { dg-final { scan-assembler "vcvtn.u32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtnt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vcvtnq_x_s16_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtnt.s16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtnt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vcvtnq_x_s32_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtnt.s32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtnt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vcvtnq_x_u16_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtnt.u16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtnt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vcvtnq_x_u32_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtnt.u32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtpt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtpq_m_s16_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtpt.s16.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtpt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtpq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtpt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtpq_m_s32_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtpt.s32.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtpt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtpq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtpt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtpq_m_u16_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtpt.u16.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtpt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtpq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtpt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtpq_m_u32_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtpt.u32.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtpt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtpq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtp.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (float16x8_t a) + { + return vcvtpq_s16_f16 (a); + } + +-/* { dg-final { scan-assembler "vcvtp.s16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtp.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (float32x4_t a) + { + return vcvtpq_s32_f32 (a); + } + +-/* { dg-final { scan-assembler "vcvtp.s32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtp.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (float16x8_t a) + { +- return vcvtpq_u16_f16 (a); ++ return vcvtpq_u16_f16 (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vcvtp.u16.f16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtp.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (float32x4_t a) + { +- return vcvtpq_u32_f32 (a); ++ return vcvtpq_u32_f32 (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vcvtp.u32.f32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtpt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vcvtpq_x_s16_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtpt.s16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtpt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vcvtpq_x_s32_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtpt.s32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtpt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vcvtpq_x_u16_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtpt.u16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtpt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vcvtpq_x_u32_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtpt.u32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.f16.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (int16x8_t a) + { + return vcvtq_f16_s16 (a); + } + +-/* { dg-final { scan-assembler "vcvt.f16.s16" } } */ ++ ++/* ++**foo1: ++** ... ++** vcvt.f16.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo1 (int16x8_t a) ++{ ++ return vcvtq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.f16.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (uint16x8_t a) + { + return vcvtq_f16_u16 (a); + } + +-/* { dg-final { scan-assembler "vcvt.f16.u16" } } */ ++ ++/* ++**foo1: ++** ... ++** vcvt.f16.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo1 (uint16x8_t a) ++{ ++ return vcvtq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.f32.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (int32x4_t a) + { + return vcvtq_f32_s32 (a); + } + +-/* { dg-final { scan-assembler "vcvt.f32.s32" } } */ ++ ++/* ++**foo1: ++** ... ++** vcvt.f32.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo1 (int32x4_t a) ++{ ++ return vcvtq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.f32.u32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (uint32x4_t a) + { + return vcvtq_f32_u32 (a); + } + +-/* { dg-final { scan-assembler "vcvt.f32.u32" } } */ ++ ++/* ++**foo1: ++** ... ++** vcvt.f32.u32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo1 (uint32x4_t a) ++{ ++ return vcvtq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vcvtq_m_f16_s16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vcvtq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vcvtq_m_f16_u16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vcvtq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vcvtq_m_f32_s32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vcvtq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.u32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { + return vcvtq_m_f32_u32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.u32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { + return vcvtq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vcvtq_m_n_f16_s16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vcvtq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vcvtq_m_n_f16_u16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vcvtq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vcvtq_m_n_f32_s32 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vcvtq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { +- return vcvtq_m_n_f32_u32 (inactive, a, 16, p); ++ return vcvtq_m_n_f32_u32 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { +- return vcvtq_m_n (inactive, a, 16, p); ++ return vcvtq_m_n (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.s16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtq_m_n_s16_f16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.s16.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.s16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.s16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.s32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtq_m_n_s32_f32 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.s32.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.s32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.s32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.u16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtq_m_n_u16_f16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.u16.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.u16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.u16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.u32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtq_m_n_u32_f32 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.u32.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.u32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.u32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtq_m_s16_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.s16.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtq_m_s32_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.s32.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtq_m_u16_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.u16.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtq_m_u32_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.u32.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.f16.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (int16x8_t a) + { + return vcvtq_n_f16_s16 (a, 1); + } + +-/* { dg-final { scan-assembler "vcvt.f16.s16" } } */ + ++/* ++**foo1: ++** ... ++** vcvt.f16.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (int16x8_t a) + { + return vcvtq_n (a, 1); + } + +-/* { dg-final { scan-assembler "vcvt.f16.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.f16.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (uint16x8_t a) + { + return vcvtq_n_f16_u16 (a, 1); + } + +-/* { dg-final { scan-assembler "vcvt.f16.u16" } } */ + ++/* ++**foo1: ++** ... ++** vcvt.f16.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (uint16x8_t a) + { + return vcvtq_n (a, 1); + } + +-/* { dg-final { scan-assembler "vcvt.f16.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.f32.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (int32x4_t a) + { + return vcvtq_n_f32_s32 (a, 1); + } + +-/* { dg-final { scan-assembler "vcvt.f32.s32" } } */ + ++/* ++**foo1: ++** ... ++** vcvt.f32.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (int32x4_t a) + { + return vcvtq_n (a, 1); + } + +-/* { dg-final { scan-assembler "vcvt.f32.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.f32.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (uint32x4_t a) + { + return vcvtq_n_f32_u32 (a, 1); + } + +-/* { dg-final { scan-assembler "vcvt.f32.u32" } } */ + ++/* ++**foo1: ++** ... ++** vcvt.f32.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (uint32x4_t a) + { + return vcvtq_n (a, 1); + } + +-/* { dg-final { scan-assembler "vcvt.f32.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.s16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (float16x8_t a) + { + return vcvtq_n_s16_f16 (a, 1); + } + +-/* { dg-final { scan-assembler "vcvt.s16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.s32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (float32x4_t a) + { + return vcvtq_n_s32_f32 (a, 1); + } + +-/* { dg-final { scan-assembler "vcvt.s32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.u16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (float16x8_t a) + { + return vcvtq_n_u16_f16 (a, 1); + } + +-/* { dg-final { scan-assembler "vcvt.u16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.u32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (float32x4_t a) + { + return vcvtq_n_u32_f32 (a, 1); + } + +-/* { dg-final { scan-assembler "vcvt.u32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (float16x8_t a) + { + return vcvtq_s16_f16 (a); + } + +-/* { dg-final { scan-assembler "vcvt.s16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (float32x4_t a) + { + return vcvtq_s32_f32 (a); + } + +-/* { dg-final { scan-assembler "vcvt.s32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (float16x8_t a) + { +- return vcvtq_u16_f16 (a); ++ return vcvtq_u16_f16 (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vcvt.u16.f16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (float32x4_t a) + { +- return vcvtq_u32_f32 (a); ++ return vcvtq_u32_f32 (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vcvt.u32.f32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (int16x8_t a, mve_pred16_t p) + { + return vcvtq_x_f16_s16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (int16x8_t a, mve_pred16_t p) + { + return vcvtq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (uint16x8_t a, mve_pred16_t p) + { + return vcvtq_x_f16_u16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (uint16x8_t a, mve_pred16_t p) + { + return vcvtq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (int32x4_t a, mve_pred16_t p) + { + return vcvtq_x_f32_s32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (int32x4_t a, mve_pred16_t p) + { + return vcvtq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.u32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (uint32x4_t a, mve_pred16_t p) + { + return vcvtq_x_f32_u32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.u32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (uint32x4_t a, mve_pred16_t p) + { + return vcvtq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (int16x8_t a, mve_pred16_t p) + { + return vcvtq_x_n_f16_s16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (int16x8_t a, mve_pred16_t p) + { + return vcvtq_x_n (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (uint16x8_t a, mve_pred16_t p) + { + return vcvtq_x_n_f16_u16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (uint16x8_t a, mve_pred16_t p) + { + return vcvtq_x_n (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (int32x4_t a, mve_pred16_t p) + { + return vcvtq_x_n_f32_s32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (int32x4_t a, mve_pred16_t p) + { + return vcvtq_x_n (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (uint32x4_t a, mve_pred16_t p) + { +- return vcvtq_x_n_f32_u32 (a, 16, p); ++ return vcvtq_x_n_f32_u32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (uint32x4_t a, mve_pred16_t p) + { +- return vcvtq_x_n (a, 16, p); ++ return vcvtq_x_n (a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.s16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vcvtq_x_n_s16_f16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.s16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.s32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vcvtq_x_n_s32_f32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.s32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.u16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vcvtq_x_n_u16_f16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.u16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.u32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vcvtq_x_n_u32_f32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.u32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vcvtq_x_s16_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.s16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vcvtq_x_s32_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.s32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vcvtq_x_u16_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.u16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vcvtq_x_u32_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.u32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtt.f16.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float32x4_t b) + { + return vcvttq_f16_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vcvtt.f16.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtt.f32.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float16x8_t a) + { + return vcvttq_f32_f16 (a); + } + +-/* { dg-final { scan-assembler "vcvtt.f32.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c +@@ -1,22 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvttt.f16.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float32x4_t b, mve_pred16_t p) + { + return vcvttq_m_f16_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvttt.f16.f32" } } */ +- +-float16x8_t +-foo1 (float16x8_t a, float32x4_t b, mve_pred16_t p) +-{ +- return vcvttq_m (a, b, p); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c +@@ -1,22 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvttt.f32.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvttq_m_f32_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvttt.f32.f16" } } */ +- +-float32x4_t +-foo1 (float32x4_t inactive, float16x8_t a, mve_pred16_t p) +-{ +- return vcvttq_m (inactive, a, p); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvttt.f32.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float16x8_t a, mve_pred16_t p) + { + return vcvttq_x_f32_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvttt.f32.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b) + { + return veorq_f16 (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ + ++/* ++**foo1: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b) + { + return veorq (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b) + { + return veorq_f32 (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ + ++/* ++**foo1: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b) + { + return veorq (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return veorq_m_f16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return veorq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return veorq_m_f32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return veorq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return veorq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return veorq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return veorq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return veorq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return veorq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return veorq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return veorq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return veorq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return veorq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return veorq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return veorq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return veorq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return veorq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ + ++/* ++**foo1: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return veorq (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return veorq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ + ++/* ++**foo1: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return veorq (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return veorq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ + ++/* ++**foo1: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return veorq (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { + return veorq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ + ++/* ++**foo1: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return veorq (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { + return veorq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ + ++/* ++**foo1: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return veorq (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { + return veorq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ + ++/* ++**foo1: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return veorq (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return veorq_x_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return veorq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return veorq_x_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return veorq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return veorq_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return veorq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return veorq_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return veorq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return veorq_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return veorq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return veorq_x_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return veorq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return veorq_x_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return veorq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return veorq_x_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return veorq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vfma.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16x8_t a, float16x8_t b, float16x8_t c) ++foo (float16x8_t add, float16x8_t m1, float16x8_t m2) + { +- return vfmaq_f16 (a, b, c); ++ return vfmaq_f16 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vfma.f16" } } */ + ++/* ++**foo1: ++** ... ++** vfma.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t +-foo1 (float16x8_t a, float16x8_t b, float16x8_t c) ++foo1 (float16x8_t add, float16x8_t m1, float16x8_t m2) + { +- return vfmaq (a, b, c); ++ return vfmaq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vfma.f16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vfma.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32x4_t a, float32x4_t b, float32x4_t c) ++foo (float32x4_t add, float32x4_t m1, float32x4_t m2) + { +- return vfmaq_f32 (a, b, c); ++ return vfmaq_f32 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vfma.f32" } } */ + ++/* ++**foo1: ++** ... ++** vfma.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t +-foo1 (float32x4_t a, float32x4_t b, float32x4_t c) ++foo1 (float32x4_t add, float32x4_t m1, float32x4_t m2) + { +- return vfmaq (a, b, c); ++ return vfmaq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vfma.f32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmat.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p) ++foo (float16x8_t add, float16x8_t m1, float16x8_t m2, mve_pred16_t p) + { +- return vfmaq_m_f16 (a, b, c, p); ++ return vfmaq_m_f16 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vfmat.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmat.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t +-foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p) ++foo1 (float16x8_t add, float16x8_t m1, float16x8_t m2, mve_pred16_t p) + { +- return vfmaq_m (a, b, c, p); ++ return vfmaq_m (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vfmat.f16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmat.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p) ++foo (float32x4_t add, float32x4_t m1, float32x4_t m2, mve_pred16_t p) + { +- return vfmaq_m_f32 (a, b, c, p); ++ return vfmaq_m_f32 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vfmat.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmat.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t +-foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p) ++foo1 (float32x4_t add, float32x4_t m1, float32x4_t m2, mve_pred16_t p) + { +- return vfmaq_m (a, b, c, p); ++ return vfmaq_m (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vfmat.f32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo1 (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p) +-{ +- return vfmaq_m (a, b, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmat.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p) ++foo (float16x8_t add, float16x8_t m1, float16_t m2, mve_pred16_t p) + { +- return vfmaq_m_n_f16 (a, b, c, p); ++ return vfmaq_m_n_f16 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vfmat.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmat.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t +-foo1 (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p) ++foo1 (float16x8_t add, float16x8_t m1, float16_t m2, mve_pred16_t p) + { +- return vfmaq_m (a, b, c, p); ++ return vfmaq_m (add, m1, m2, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmat.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo2 (float16x8_t add, float16x8_t m1, mve_pred16_t p) ++{ ++ return vfmaq_m (add, m1, 1.1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vfmat.f16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo1 (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p) +-{ +- return vfmaq_m (a, b, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmat.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p) ++foo (float32x4_t add, float32x4_t m1, float32_t m2, mve_pred16_t p) + { +- return vfmaq_m_n_f32 (a, b, c, p); ++ return vfmaq_m_n_f32 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vfmat.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmat.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t +-foo1 (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p) ++foo1 (float32x4_t add, float32x4_t m1, float32_t m2, mve_pred16_t p) + { +- return vfmaq_m (a, b, c, p); ++ return vfmaq_m (add, m1, m2, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmat.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo2 (float32x4_t add, float32x4_t m1, mve_pred16_t p) ++{ ++ return vfmaq_m (add, m1, 1.1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vfmat.f32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo1 (float16x8_t a, float16x8_t b, float16_t c) +-{ +- return vfmaq (a, b, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vfma.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16x8_t a, float16x8_t b, float16_t c) ++foo (float16x8_t add, float16x8_t m1, float16_t m2) + { +- return vfmaq_n_f16 (a, b, c); ++ return vfmaq_n_f16 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vfma.f16" } } */ + ++/* ++**foo1: ++** ... ++** vfma.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t +-foo1 (float16x8_t a, float16x8_t b, float16_t c) ++foo1 (float16x8_t add, float16x8_t m1, float16_t m2) + { +- return vfmaq (a, b, c); ++ return vfmaq (add, m1, m2); ++} ++ ++/* ++**foo2: ++** ... ++** vfma.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo2 (float16x8_t add, float16x8_t m1) ++{ ++ return vfmaq (add, m1, 1.1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vfma.f16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo1 (float32x4_t a, float32x4_t b, float32_t c) +-{ +- return vfmaq (a, b, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vfma.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32x4_t a, float32x4_t b, float32_t c) ++foo (float32x4_t add, float32x4_t m1, float32_t m2) + { +- return vfmaq_n_f32 (a, b, c); ++ return vfmaq_n_f32 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vfma.f32" } } */ + ++/* ++**foo1: ++** ... ++** vfma.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t +-foo1 (float32x4_t a, float32x4_t b, float32_t c) ++foo1 (float32x4_t add, float32x4_t m1, float32_t m2) + { +- return vfmaq (a, b, c); ++ return vfmaq (add, m1, m2); ++} ++ ++/* ++**foo2: ++** ... ++** vfma.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo2 (float32x4_t add, float32x4_t m1) ++{ ++ return vfmaq (add, m1, 1.1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vfma.f32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo1 (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p) +-{ +- return vfmasq_m (a, b, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c +@@ -62,4 +62,4 @@ foo2 (float16x8_t m1, float16x8_t m2, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo1 (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p) +-{ +- return vfmasq_m (a, b, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c +@@ -62,4 +62,4 @@ foo2 (float32x4_t m1, float32x4_t m2, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo1 (float16x8_t a, float16x8_t b, float16_t c) +-{ +- return vfmasq (a, b, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vfmas.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16x8_t a, float16x8_t b, float16_t c) ++foo (float16x8_t m1, float16x8_t m2, float16_t add) + { +- return vfmasq_n_f16 (a, b, c); ++ return vfmasq_n_f16 (m1, m2, add); + } + +-/* { dg-final { scan-assembler "vfmas.f16" } } */ + ++/* ++**foo1: ++** ... ++** vfmas.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t +-foo1 (float16x8_t a, float16x8_t b, float16_t c) ++foo1 (float16x8_t m1, float16x8_t m2, float16_t add) + { +- return vfmasq (a, b, c); ++ return vfmasq (m1, m2, add); ++} ++ ++/* ++**foo2: ++** ... ++** vfmas.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo2 (float16x8_t m1, float16x8_t m2) ++{ ++ return vfmasq (m1, m2, 1.1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vfmas.f16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo1 (float32x4_t a, float32x4_t b, float32_t c) +-{ +- return vfmasq (a, b, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vfmas.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32x4_t a, float32x4_t b, float32_t c) ++foo (float32x4_t m1, float32x4_t m2, float32_t add) + { +- return vfmasq_n_f32 (a, b, c); ++ return vfmasq_n_f32 (m1, m2, add); + } + +-/* { dg-final { scan-assembler "vfmas.f32" } } */ + ++/* ++**foo1: ++** ... ++** vfmas.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t +-foo1 (float32x4_t a, float32x4_t b, float32_t c) ++foo1 (float32x4_t m1, float32x4_t m2, float32_t add) + { +- return vfmasq (a, b, c); ++ return vfmasq (m1, m2, add); ++} ++ ++/* ++**foo2: ++** ... ++** vfmas.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo2 (float32x4_t m1, float32x4_t m2) ++{ ++ return vfmasq (m1, m2, 1.1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vfmas.f32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vfms.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16x8_t a, float16x8_t b, float16x8_t c) ++foo (float16x8_t add, float16x8_t m1, float16x8_t m2) + { +- return vfmsq_f16 (a, b, c); ++ return vfmsq_f16 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vfms.f16" } } */ + ++/* ++**foo1: ++** ... ++** vfms.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t +-foo1 (float16x8_t a, float16x8_t b, float16x8_t c) ++foo1 (float16x8_t add, float16x8_t m1, float16x8_t m2) + { +- return vfmsq (a, b, c); ++ return vfmsq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vfms.f16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vfms.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32x4_t a, float32x4_t b, float32x4_t c) ++foo (float32x4_t add, float32x4_t m1, float32x4_t m2) + { +- return vfmsq_f32 (a, b, c); ++ return vfmsq_f32 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vfms.f32" } } */ + ++/* ++**foo1: ++** ... ++** vfms.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t +-foo1 (float32x4_t a, float32x4_t b, float32x4_t c) ++foo1 (float32x4_t add, float32x4_t m1, float32x4_t m2) + { +- return vfmsq (a, b, c); ++ return vfmsq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vfms.f32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmst.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p) ++foo (float16x8_t add, float16x8_t m1, float16x8_t m2, mve_pred16_t p) + { +- return vfmsq_m_f16 (a, b, c, p); ++ return vfmsq_m_f16 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vfmst.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmst.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t +-foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p) ++foo1 (float16x8_t add, float16x8_t m1, float16x8_t m2, mve_pred16_t p) + { +- return vfmsq_m (a, b, c, p); ++ return vfmsq_m (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vfmst.f16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmst.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p) ++foo (float32x4_t add, float32x4_t m1, float32x4_t m2, mve_pred16_t p) + { +- return vfmsq_m_f32 (a, b, c, p); ++ return vfmsq_m_f32 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vfmst.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmst.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t +-foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p) ++foo1 (float32x4_t add, float32x4_t m1, float32x4_t m2, mve_pred16_t p) + { +- return vfmsq_m (a, b, c, p); ++ return vfmsq_m (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vfmst.f32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vhcaddq_rot270_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vhcaddq_rot270_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vhcaddq_rot270_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vhcaddq_rot270_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vhcaddq_rot270_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vhcaddq_rot270_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhcadd.s16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vhcaddq_rot270_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vhcadd.s16" } } */ + ++/* ++**foo1: ++** ... ++** vhcadd.s16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vhcaddq_rot270 (a, b); + } + +-/* { dg-final { scan-assembler "vhcadd.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhcadd.s32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vhcaddq_rot270_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vhcadd.s32" } } */ + ++/* ++**foo1: ++** ... ++** vhcadd.s32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vhcaddq_rot270 (a, b); + } + +-/* { dg-final { scan-assembler "vhcadd.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhcadd.s8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vhcaddq_rot270_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vhcadd.s8" } } */ + ++/* ++**foo1: ++** ... ++** vhcadd.s8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vhcaddq_rot270 (a, b); + } + +-/* { dg-final { scan-assembler "vhcadd.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vhcaddq_rot270_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vhcaddq_rot270_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vhcaddq_rot270_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vhcaddq_rot270_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vhcaddq_rot270_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vhcaddq_rot270_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vhcaddq_rot90_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vhcaddq_rot90_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vhcaddq_rot90_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vhcaddq_rot90_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vhcaddq_rot90_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vhcaddq_rot90_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhcadd.s16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vhcaddq_rot90_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vhcadd.s16" } } */ + ++/* ++**foo1: ++** ... ++** vhcadd.s16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vhcaddq_rot90 (a, b); + } + +-/* { dg-final { scan-assembler "vhcadd.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhcadd.s32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vhcaddq_rot90_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vhcadd.s32" } } */ + ++/* ++**foo1: ++** ... ++** vhcadd.s32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vhcaddq_rot90 (a, b); + } + +-/* { dg-final { scan-assembler "vhcadd.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhcadd.s8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vhcaddq_rot90_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vhcadd.s8" } } */ + ++/* ++**foo1: ++** ... ++** vhcadd.s8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vhcaddq_rot90 (a, b); + } + +-/* { dg-final { scan-assembler "vhcadd.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vhcaddq_rot90_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vhcaddq_rot90_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vhcaddq_rot90_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vhcaddq_rot90_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vhcaddq_rot90_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vhcaddq_rot90_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c +@@ -1,20 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16_t const * base) ++foo (float16_t const *base) + { + return vld1q_f16 (base); + } + ++ ++/* ++**foo1: ++** ... ++** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + float16x8_t +-foo1 (float16_t const * base) ++foo1 (float16_t const *base) + { + return vld1q (base); + } + +-/* { dg-final { scan-assembler-times "vldrh.16" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c +@@ -1,20 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32_t const * base) ++foo (float32_t const *base) + { + return vld1q_f32 (base); + } + ++ ++/* ++**foo1: ++** ... ++** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + float32x4_t +-foo1 (float32_t const * base) ++foo1 (float32_t const *base) + { + return vld1q (base); + } + +-/* { dg-final { scan-assembler-times "vldrw.32" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c +@@ -1,20 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16_t const * base) ++foo (int16_t const *base) + { + return vld1q_s16 (base); + } + ++ ++/* ++**foo1: ++** ... ++** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int16_t const * base) ++foo1 (int16_t const *base) + { + return vld1q (base); + } + +-/* { dg-final { scan-assembler-times "vldrh.16" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c +@@ -1,20 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32_t const * base) ++foo (int32_t const *base) + { + return vld1q_s32 (base); + } + ++ ++/* ++**foo1: ++** ... ++** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32_t const * base) ++foo1 (int32_t const *base) + { + return vld1q (base); + } + +-/* { dg-final { scan-assembler-times "vldrw.32" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c +@@ -1,20 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int8x16_t +-foo (int8_t const * base) ++foo (int8_t const *base) + { + return vld1q_s8 (base); + } + ++ ++/* ++**foo1: ++** ... ++** vldrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int8x16_t +-foo1 (int8_t const * base) ++foo1 (int8_t const *base) + { + return vld1q (base); + } + +-/* { dg-final { scan-assembler-times "vldrb.8" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c +@@ -1,20 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint16_t const * base) ++foo (uint16_t const *base) + { + return vld1q_u16 (base); + } + ++ ++/* ++**foo1: ++** ... ++** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (uint16_t const * base) ++foo1 (uint16_t const *base) + { + return vld1q (base); + } + +-/* { dg-final { scan-assembler-times "vldrh.16" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c +@@ -1,20 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32_t const * base) ++foo (uint32_t const *base) + { + return vld1q_u32 (base); + } + ++ ++/* ++**foo1: ++** ... ++** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32_t const * base) ++foo1 (uint32_t const *base) + { + return vld1q (base); + } + +-/* { dg-final { scan-assembler-times "vldrw.32" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c +@@ -1,20 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint8x16_t +-foo (uint8_t const * base) ++foo (uint8_t const *base) + { + return vld1q_u8 (base); + } + ++ ++/* ++**foo1: ++** ... ++** vldrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint8x16_t +-foo1 (uint8_t const * base) ++foo1 (uint8_t const *base) + { + return vld1q (base); + } + +-/* { dg-final { scan-assembler-times "vldrb.8" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16_t const * base, mve_pred16_t p) ++foo (float16_t const *base, mve_pred16_t p) + { + return vld1q_z_f16 (base, p); + } + ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + float16x8_t +-foo1 (float16_t const * base, mve_pred16_t p) ++foo1 (float16_t const *base, mve_pred16_t p) + { + return vld1q_z (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 2 } } */ +-/* { dg-final { scan-assembler-times "vldrht.16" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32_t const * base, mve_pred16_t p) ++foo (float32_t const *base, mve_pred16_t p) + { + return vld1q_z_f32 (base, p); + } + ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + float32x4_t +-foo1 (float32_t const * base, mve_pred16_t p) ++foo1 (float32_t const *base, mve_pred16_t p) + { + return vld1q_z (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 2 } } */ +-/* { dg-final { scan-assembler-times "vldrwt.32" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16_t const * base, mve_pred16_t p) ++foo (int16_t const *base, mve_pred16_t p) + { + return vld1q_z_s16 (base, p); + } + ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int16_t const * base, mve_pred16_t p) ++foo1 (int16_t const *base, mve_pred16_t p) + { + return vld1q_z (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 2 } } */ +-/* { dg-final { scan-assembler-times "vldrht.16" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32_t const * base, mve_pred16_t p) ++foo (int32_t const *base, mve_pred16_t p) + { + return vld1q_z_s32 (base, p); + } + ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32_t const * base, mve_pred16_t p) ++foo1 (int32_t const *base, mve_pred16_t p) + { + return vld1q_z (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 2 } } */ +-/* { dg-final { scan-assembler-times "vldrwt.32" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int8x16_t +-foo (int8_t const * base, mve_pred16_t p) ++foo (int8_t const *base, mve_pred16_t p) + { + return vld1q_z_s8 (base, p); + } + ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int8x16_t +-foo1 (int8_t const * base, mve_pred16_t p) ++foo1 (int8_t const *base, mve_pred16_t p) + { + return vld1q_z (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 2 } } */ +-/* { dg-final { scan-assembler-times "vldrbt.8" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint16_t const * base, mve_pred16_t p) ++foo (uint16_t const *base, mve_pred16_t p) + { + return vld1q_z_u16 (base, p); + } + ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (uint16_t const * base, mve_pred16_t p) ++foo1 (uint16_t const *base, mve_pred16_t p) + { + return vld1q_z (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 2 } } */ +-/* { dg-final { scan-assembler-times "vldrht.16" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32_t const * base, mve_pred16_t p) ++foo (uint32_t const *base, mve_pred16_t p) + { + return vld1q_z_u32 (base, p); + } + ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32_t const * base, mve_pred16_t p) ++foo1 (uint32_t const *base, mve_pred16_t p) + { + return vld1q_z (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 2 } } */ +-/* { dg-final { scan-assembler-times "vldrwt.32" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint8x16_t +-foo (uint8_t const * base, mve_pred16_t p) ++foo (uint8_t const *base, mve_pred16_t p) + { + return vld1q_z_u8 (base, p); + } + ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint8x16_t +-foo1 (uint8_t const * base, mve_pred16_t p) ++foo1 (uint8_t const *base, mve_pred16_t p) + { + return vld1q_z (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 2 } } */ +-/* { dg-final { scan-assembler-times "vldrbt.8" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c +@@ -1,24 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vld40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + float16x8x4_t +-foo (float16_t const * addr) ++foo (float16_t const *addr) + { + return vld4q_f16 (addr); + } + +-/* { dg-final { scan-assembler "vld40.16" } } */ +-/* { dg-final { scan-assembler "vld41.16" } } */ +-/* { dg-final { scan-assembler "vld42.16" } } */ +-/* { dg-final { scan-assembler "vld43.16" } } */ + ++/* ++**foo1: ++** ... ++** vld40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + float16x8x4_t +-foo1 (float16_t const * addr) ++foo1 (float16_t const *addr) + { + return vld4q (addr); + } + +-/* { dg-final { scan-assembler "vld40.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c +@@ -1,24 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vld40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + float32x4x4_t +-foo (float32_t const * addr) ++foo (float32_t const *addr) + { + return vld4q_f32 (addr); + } + +-/* { dg-final { scan-assembler "vld40.32" } } */ +-/* { dg-final { scan-assembler "vld41.32" } } */ +-/* { dg-final { scan-assembler "vld42.32" } } */ +-/* { dg-final { scan-assembler "vld43.32" } } */ + ++/* ++**foo1: ++** ... ++** vld40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + float32x4x4_t +-foo1 (float32_t const * addr) ++foo1 (float32_t const *addr) + { + return vld4q (addr); + } + +-/* { dg-final { scan-assembler "vld40.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c +@@ -1,24 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vld40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + int16x8x4_t +-foo (int16_t const * addr) ++foo (int16_t const *addr) + { + return vld4q_s16 (addr); + } + +-/* { dg-final { scan-assembler "vld40.16" } } */ +-/* { dg-final { scan-assembler "vld41.16" } } */ +-/* { dg-final { scan-assembler "vld42.16" } } */ +-/* { dg-final { scan-assembler "vld43.16" } } */ + ++/* ++**foo1: ++** ... ++** vld40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + int16x8x4_t +-foo1 (int16_t const * addr) ++foo1 (int16_t const *addr) + { + return vld4q (addr); + } + +-/* { dg-final { scan-assembler "vld40.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c +@@ -1,24 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vld40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + int32x4x4_t +-foo (int32_t const * addr) ++foo (int32_t const *addr) + { + return vld4q_s32 (addr); + } + +-/* { dg-final { scan-assembler "vld40.32" } } */ +-/* { dg-final { scan-assembler "vld41.32" } } */ +-/* { dg-final { scan-assembler "vld42.32" } } */ +-/* { dg-final { scan-assembler "vld43.32" } } */ + ++/* ++**foo1: ++** ... ++** vld40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + int32x4x4_t +-foo1 (int32_t const * addr) ++foo1 (int32_t const *addr) + { + return vld4q (addr); + } + +-/* { dg-final { scan-assembler "vld40.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c +@@ -1,24 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vld40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + int8x16x4_t +-foo (int8_t const * addr) ++foo (int8_t const *addr) + { + return vld4q_s8 (addr); + } + +-/* { dg-final { scan-assembler "vld40.8" } } */ +-/* { dg-final { scan-assembler "vld41.8" } } */ +-/* { dg-final { scan-assembler "vld42.8" } } */ +-/* { dg-final { scan-assembler "vld43.8" } } */ + ++/* ++**foo1: ++** ... ++** vld40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + int8x16x4_t +-foo1 (int8_t const * addr) ++foo1 (int8_t const *addr) + { + return vld4q (addr); + } + +-/* { dg-final { scan-assembler "vld40.8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c +@@ -1,24 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vld40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + uint16x8x4_t +-foo (uint16_t const * addr) ++foo (uint16_t const *addr) + { + return vld4q_u16 (addr); + } + +-/* { dg-final { scan-assembler "vld40.16" } } */ +-/* { dg-final { scan-assembler "vld41.16" } } */ +-/* { dg-final { scan-assembler "vld42.16" } } */ +-/* { dg-final { scan-assembler "vld43.16" } } */ + ++/* ++**foo1: ++** ... ++** vld40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + uint16x8x4_t +-foo1 (uint16_t const * addr) ++foo1 (uint16_t const *addr) + { + return vld4q (addr); + } + +-/* { dg-final { scan-assembler "vld40.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c +@@ -1,24 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vld40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + uint32x4x4_t +-foo (uint32_t const * addr) ++foo (uint32_t const *addr) + { + return vld4q_u32 (addr); + } + +-/* { dg-final { scan-assembler "vld40.32" } } */ +-/* { dg-final { scan-assembler "vld41.32" } } */ +-/* { dg-final { scan-assembler "vld42.32" } } */ +-/* { dg-final { scan-assembler "vld43.32" } } */ + ++/* ++**foo1: ++** ... ++** vld40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + uint32x4x4_t +-foo1 (uint32_t const * addr) ++foo1 (uint32_t const *addr) + { + return vld4q (addr); + } + +-/* { dg-final { scan-assembler "vld40.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c +@@ -1,24 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vld40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + uint8x16x4_t +-foo (uint8_t const * addr) ++foo (uint8_t const *addr) + { + return vld4q_u8 (addr); + } + +-/* { dg-final { scan-assembler "vld40.8" } } */ +-/* { dg-final { scan-assembler "vld41.8" } } */ +-/* { dg-final { scan-assembler "vld42.8" } } */ +-/* { dg-final { scan-assembler "vld43.8" } } */ + ++/* ++**foo1: ++** ... ++** vld40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + uint8x16x4_t +-foo1 (uint8_t const * addr) ++foo1 (uint8_t const *addr) + { + return vld4q (addr); + } + +-/* { dg-final { scan-assembler "vld40.8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrb.s16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int8_t const * base, uint16x8_t offset) ++foo (int8_t const *base, uint16x8_t offset) + { + return vldrbq_gather_offset_s16 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrb.s16" } } */ + ++/* ++**foo1: ++** ... ++** vldrb.s16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int8_t const * base, uint16x8_t offset) ++foo1 (int8_t const *base, uint16x8_t offset) + { + return vldrbq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrb.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrb.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int8_t const * base, uint32x4_t offset) ++foo (int8_t const *base, uint32x4_t offset) + { + return vldrbq_gather_offset_s32 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrb.s32" } } */ + ++/* ++**foo1: ++** ... ++** vldrb.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int8_t const * base, uint32x4_t offset) ++foo1 (int8_t const *base, uint32x4_t offset) + { + return vldrbq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrb.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrb.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int8x16_t +-foo (int8_t const * base, uint8x16_t offset) ++foo (int8_t const *base, uint8x16_t offset) + { + return vldrbq_gather_offset_s8 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrb.u8" } } */ + ++/* ++**foo1: ++** ... ++** vldrb.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int8x16_t +-foo1 (int8_t const * base, uint8x16_t offset) ++foo1 (int8_t const *base, uint8x16_t offset) + { + return vldrbq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrb.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrb.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint8_t const * base, uint16x8_t offset) ++foo (uint8_t const *base, uint16x8_t offset) + { + return vldrbq_gather_offset_u16 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrb.u16" } } */ + ++/* ++**foo1: ++** ... ++** vldrb.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (uint8_t const * base, uint16x8_t offset) ++foo1 (uint8_t const *base, uint16x8_t offset) + { + return vldrbq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrb.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrb.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint8_t const * base, uint32x4_t offset) ++foo (uint8_t const *base, uint32x4_t offset) + { + return vldrbq_gather_offset_u32 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrb.u32" } } */ + ++/* ++**foo1: ++** ... ++** vldrb.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint8_t const * base, uint32x4_t offset) ++foo1 (uint8_t const *base, uint32x4_t offset) + { + return vldrbq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrb.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrb.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint8x16_t +-foo (uint8_t const * base, uint8x16_t offset) ++foo (uint8_t const *base, uint8x16_t offset) + { + return vldrbq_gather_offset_u8 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrb.u8" } } */ + ++/* ++**foo1: ++** ... ++** vldrb.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint8x16_t +-foo1 (uint8_t const * base, uint8x16_t offset) ++foo1 (uint8_t const *base, uint8x16_t offset) + { + return vldrbq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrb.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.s16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int8_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo (int8_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrbq_gather_offset_z_s16 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrbt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.s16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int8_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo1 (int8_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrbq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrbt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int8_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo (int8_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrbq_gather_offset_z_s32 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrbt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int8_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo1 (int8_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrbq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrbt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int8x16_t +-foo (int8_t const * base, uint8x16_t offset, mve_pred16_t p) ++foo (int8_t const *base, uint8x16_t offset, mve_pred16_t p) + { + return vldrbq_gather_offset_z_s8 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrbt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int8x16_t +-foo1 (int8_t const * base, uint8x16_t offset, mve_pred16_t p) ++foo1 (int8_t const *base, uint8x16_t offset, mve_pred16_t p) + { + return vldrbq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrbt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint8_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo (uint8_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrbq_gather_offset_z_u16 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrbt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (uint8_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo1 (uint8_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrbq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrbt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint8_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo (uint8_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrbq_gather_offset_z_u32 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrbt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint8_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo1 (uint8_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrbq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrbt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint8x16_t +-foo (uint8_t const * base, uint8x16_t offset, mve_pred16_t p) ++foo (uint8_t const *base, uint8x16_t offset, mve_pred16_t p) + { + return vldrbq_gather_offset_z_u8 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrbt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint8x16_t +-foo1 (uint8_t const * base, uint8x16_t offset, mve_pred16_t p) ++foo1 (uint8_t const *base, uint8x16_t offset, mve_pred16_t p) + { + return vldrbq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrbt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrb.s16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int8_t const * base) ++foo (int8_t const *base) + { + return vldrbq_s16 (base); + } + +-/* { dg-final { scan-assembler "vldrb.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrb.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int8_t const * base) ++foo (int8_t const *base) + { + return vldrbq_s32 (base); + } + +-/* { dg-final { scan-assembler "vldrb.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c +@@ -1,14 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int8x16_t +-foo (int8_t const * base) ++foo (int8_t const *base) + { + return vldrbq_s8 (base); + } + +-/* { dg-final { scan-assembler-times "vldrb.8" 1 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrb.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint8_t const * base) ++foo (uint8_t const *base) + { + return vldrbq_u16 (base); + } + +-/* { dg-final { scan-assembler "vldrb.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrb.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint8_t const * base) ++foo (uint8_t const *base) + { + return vldrbq_u32 (base); + } + +-/* { dg-final { scan-assembler "vldrb.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c +@@ -1,14 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint8x16_t +-foo (uint8_t const * base) ++foo (uint8_t const *base) + { + return vldrbq_u8 (base); + } + +-/* { dg-final { scan-assembler-times "vldrb.8" 1 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c +@@ -1,13 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.s16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int8_t const * base, mve_pred16_t p) ++foo (int8_t const *base, mve_pred16_t p) + { + return vldrbq_z_s16 (base, p); + } + +-/* { dg-final { scan-assembler "vldrbt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c +@@ -1,13 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int8_t const * base, mve_pred16_t p) ++foo (int8_t const *base, mve_pred16_t p) + { + return vldrbq_z_s32 (base, p); + } + +-/* { dg-final { scan-assembler "vldrbt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c +@@ -1,15 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int8x16_t +-foo (int8_t const * base, mve_pred16_t p) ++foo (int8_t const *base, mve_pred16_t p) + { + return vldrbq_z_s8 (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 1 } } */ +-/* { dg-final { scan-assembler-times "vldrbt.8" 1 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c +@@ -1,13 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint8_t const * base, mve_pred16_t p) ++foo (uint8_t const *base, mve_pred16_t p) + { + return vldrbq_z_u16 (base, p); + } + +-/* { dg-final { scan-assembler "vldrbt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c +@@ -1,13 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint8_t const * base, mve_pred16_t p) ++foo (uint8_t const *base, mve_pred16_t p) + { + return vldrbq_z_u32 (base, p); + } + +-/* { dg-final { scan-assembler "vldrbt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c +@@ -1,15 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint8x16_t +-foo (uint8_t const * base, mve_pred16_t p) ++foo (uint8_t const *base, mve_pred16_t p) + { + return vldrbq_z_u8 (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 1 } } */ +-/* { dg-final { scan-assembler-times "vldrbt.8" 1 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrd.64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + int64x2_t + foo (uint64x2_t addr) + { +- return vldrdq_gather_base_s64 (addr, 8); ++ return vldrdq_gather_base_s64 (addr, 0); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrd.64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrd.64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + uint64x2_t + foo (uint64x2_t addr) + { +- return vldrdq_gather_base_u64 (addr, 8); ++ return vldrdq_gather_base_u64 (addr, 0); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrd.64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c +@@ -1,16 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrd.64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + int64x2_t +-foo (uint64x2_t * addr) ++foo (uint64x2_t *addr) + { +- return vldrdq_gather_base_wb_s64 (addr, 8); ++ return vldrdq_gather_base_wb_s64 (addr, 0); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrd.64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ +-/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */ +-/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c +@@ -1,16 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrd.64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + uint64x2_t +-foo (uint64x2_t * addr) ++foo (uint64x2_t *addr) + { +- return vldrdq_gather_base_wb_u64 (addr, 8); ++ return vldrdq_gather_base_wb_u64 (addr, 0); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrd.64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ +-/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */ +-/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c +@@ -1,15 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ + #include "arm_mve.h" + +-int64x2_t foo (uint64x2_t * addr, mve_pred16_t p) ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ ++int64x2_t ++foo (uint64x2_t *addr, mve_pred16_t p) + { +- return vldrdq_gather_base_wb_z_s64 (addr, 1016, p); ++ return vldrdq_gather_base_wb_z_s64 (addr, 0, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vldrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ +-/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */ +-/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c +@@ -1,15 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ + #include "arm_mve.h" + +-uint64x2_t foo (uint64x2_t * addr, mve_pred16_t p) ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ ++uint64x2_t ++foo (uint64x2_t *addr, mve_pred16_t p) + { +- return vldrdq_gather_base_wb_z_u64 (addr, 8, p); ++ return vldrdq_gather_base_wb_z_u64 (addr, 0, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vldrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ +-/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */ +-/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c +@@ -1,13 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + int64x2_t + foo (uint64x2_t addr, mve_pred16_t p) + { +- return vldrdq_gather_base_z_s64 (addr, 8, p); ++ return vldrdq_gather_base_z_s64 (addr, 0, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrdt.u64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c +@@ -1,13 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + uint64x2_t + foo (uint64x2_t addr, mve_pred16_t p) + { +- return vldrdq_gather_base_z_u64 (addr, 8, p); ++ return vldrdq_gather_base_z_u64 (addr, 0, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrdt.u64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int64x2_t +-foo (int64_t const * base, uint64x2_t offset) ++foo (int64_t const *base, uint64x2_t offset) + { + return vldrdq_gather_offset_s64 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrd.u64" } } */ + ++/* ++**foo1: ++** ... ++** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int64x2_t +-foo1 (int64_t const * base, uint64x2_t offset) ++foo1 (int64_t const *base, uint64x2_t offset) + { + return vldrdq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrd.u64" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint64x2_t +-foo (uint64_t const * base, uint64x2_t offset) ++foo (uint64_t const *base, uint64x2_t offset) + { + return vldrdq_gather_offset_u64 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrd.u64" } } */ + ++/* ++**foo1: ++** ... ++** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint64x2_t +-foo1 (uint64_t const * base, uint64x2_t offset) ++foo1 (uint64_t const *base, uint64x2_t offset) + { + return vldrdq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrd.u64" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int64x2_t +-foo (int64_t const * base, uint64x2_t offset, mve_pred16_t p) ++foo (int64_t const *base, uint64x2_t offset, mve_pred16_t p) + { + return vldrdq_gather_offset_z_s64 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrdt.u64" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int64x2_t +-foo1 (int64_t const * base, uint64x2_t offset, mve_pred16_t p) ++foo1 (int64_t const *base, uint64x2_t offset, mve_pred16_t p) + { + return vldrdq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrdt.u64" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint64x2_t +-foo (uint64_t const * base, uint64x2_t offset, mve_pred16_t p) ++foo (uint64_t const *base, uint64x2_t offset, mve_pred16_t p) + { + return vldrdq_gather_offset_z_u64 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrdt.u64" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint64x2_t +-foo1 (uint64_t const * base, uint64x2_t offset, mve_pred16_t p) ++foo1 (uint64_t const *base, uint64x2_t offset, mve_pred16_t p) + { + return vldrdq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrdt.u64" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + int64x2_t +-foo (int64_t const * base, uint64x2_t offset) ++foo (int64_t const *base, uint64x2_t offset) + { + return vldrdq_gather_shifted_offset_s64 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrd.u64" } } */ + ++/* ++**foo1: ++** ... ++** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + int64x2_t +-foo1 (int64_t const * base, uint64x2_t offset) ++foo1 (int64_t const *base, uint64x2_t offset) + { + return vldrdq_gather_shifted_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrd.u64" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + uint64x2_t +-foo (uint64_t const * base, uint64x2_t offset) ++foo (uint64_t const *base, uint64x2_t offset) + { + return vldrdq_gather_shifted_offset_u64 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrd.u64" } } */ + ++/* ++**foo1: ++** ... ++** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + uint64x2_t +-foo1 (uint64_t const * base, uint64x2_t offset) ++foo1 (uint64_t const *base, uint64x2_t offset) + { + return vldrdq_gather_shifted_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrd.u64" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + int64x2_t +-foo (int64_t const * base, uint64x2_t offset, mve_pred16_t p) ++foo (int64_t const *base, uint64x2_t offset, mve_pred16_t p) + { + return vldrdq_gather_shifted_offset_z_s64 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrdt.u64" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + int64x2_t +-foo1 (int64_t const * base, uint64x2_t offset, mve_pred16_t p) ++foo1 (int64_t const *base, uint64x2_t offset, mve_pred16_t p) + { + return vldrdq_gather_shifted_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrdt.u64" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + uint64x2_t +-foo (uint64_t const * base, uint64x2_t offset, mve_pred16_t p) ++foo (uint64_t const *base, uint64x2_t offset, mve_pred16_t p) + { + return vldrdq_gather_shifted_offset_z_u64 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrdt.u64" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + uint64x2_t +-foo1 (uint64_t const * base, uint64x2_t offset, mve_pred16_t p) ++foo1 (uint64_t const *base, uint64x2_t offset, mve_pred16_t p) + { + return vldrdq_gather_shifted_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrdt.u64" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c +@@ -1,14 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16_t const * base) ++foo (float16_t const *base) + { + return vldrhq_f16 (base); + } + +-/* { dg-final { scan-assembler-times "vldrh.16" 1 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16_t const * base, uint16x8_t offset) ++foo (float16_t const *base, uint16x8_t offset) + { + return vldrhq_gather_offset_f16 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.f16" } } */ + ++/* ++**foo1: ++** ... ++** vldrh.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + float16x8_t +-foo1 (float16_t const * base, uint16x8_t offset) ++foo1 (float16_t const *base, uint16x8_t offset) + { + return vldrhq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16_t const * base, uint16x8_t offset) ++foo (int16_t const *base, uint16x8_t offset) + { + return vldrhq_gather_offset_s16 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.u16" } } */ + ++/* ++**foo1: ++** ... ++** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int16_t const * base, uint16x8_t offset) ++foo1 (int16_t const *base, uint16x8_t offset) + { + return vldrhq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int16_t const * base, uint32x4_t offset) ++foo (int16_t const *base, uint32x4_t offset) + { + return vldrhq_gather_offset_s32 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.s32" } } */ + ++/* ++**foo1: ++** ... ++** vldrh.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int16_t const * base, uint32x4_t offset) ++foo1 (int16_t const *base, uint32x4_t offset) + { + return vldrhq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint16_t const * base, uint16x8_t offset) ++foo (uint16_t const *base, uint16x8_t offset) + { + return vldrhq_gather_offset_u16 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.u16" } } */ + ++/* ++**foo1: ++** ... ++** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (uint16_t const * base, uint16x8_t offset) ++foo1 (uint16_t const *base, uint16x8_t offset) + { + return vldrhq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint16_t const * base, uint32x4_t offset) ++foo (uint16_t const *base, uint32x4_t offset) + { + return vldrhq_gather_offset_u32 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.u32" } } */ + ++/* ++**foo1: ++** ... ++** vldrh.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint16_t const * base, uint32x4_t offset) ++foo1 (uint16_t const *base, uint32x4_t offset) + { + return vldrhq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo (float16_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrhq_gather_offset_z_f16 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + float16x8_t +-foo1 (float16_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo1 (float16_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrhq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo (int16_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrhq_gather_offset_z_s16 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int16_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo1 (int16_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrhq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int16_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo (int16_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrhq_gather_offset_z_s32 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int16_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo1 (int16_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrhq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint16_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo (uint16_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrhq_gather_offset_z_u16 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (uint16_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo1 (uint16_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrhq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint16_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo (uint16_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrhq_gather_offset_z_u32 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint16_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo1 (uint16_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrhq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16_t const * base, uint16x8_t offset) ++foo (float16_t const *base, uint16x8_t offset) + { + return vldrhq_gather_shifted_offset_f16 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.f16" } } */ + ++/* ++**foo1: ++** ... ++** vldrh.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + float16x8_t +-foo1 (float16_t const * base, uint16x8_t offset) ++foo1 (float16_t const *base, uint16x8_t offset) + { + return vldrhq_gather_shifted_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16_t const * base, uint16x8_t offset) ++foo (int16_t const *base, uint16x8_t offset) + { + return vldrhq_gather_shifted_offset_s16 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.u16" } } */ + ++/* ++**foo1: ++** ... ++** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int16_t const * base, uint16x8_t offset) ++foo1 (int16_t const *base, uint16x8_t offset) + { + return vldrhq_gather_shifted_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int16_t const * base, uint32x4_t offset) ++foo (int16_t const *base, uint32x4_t offset) + { + return vldrhq_gather_shifted_offset_s32 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.s32" } } */ + ++/* ++**foo1: ++** ... ++** vldrh.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int16_t const * base, uint32x4_t offset) ++foo1 (int16_t const *base, uint32x4_t offset) + { + return vldrhq_gather_shifted_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint16_t const * base, uint16x8_t offset) ++foo (uint16_t const *base, uint16x8_t offset) + { + return vldrhq_gather_shifted_offset_u16 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.u16" } } */ + ++/* ++**foo1: ++** ... ++** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (uint16_t const * base, uint16x8_t offset) ++foo1 (uint16_t const *base, uint16x8_t offset) + { + return vldrhq_gather_shifted_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint16_t const * base, uint32x4_t offset) ++foo (uint16_t const *base, uint32x4_t offset) + { + return vldrhq_gather_shifted_offset_u32 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.u32" } } */ + ++/* ++**foo1: ++** ... ++** vldrh.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint16_t const * base, uint32x4_t offset) ++foo1 (uint16_t const *base, uint32x4_t offset) + { + return vldrhq_gather_shifted_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo (float16_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrhq_gather_shifted_offset_z_f16 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + float16x8_t +-foo1 (float16_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo1 (float16_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrhq_gather_shifted_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo (int16_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrhq_gather_shifted_offset_z_s16 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int16_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo1 (int16_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrhq_gather_shifted_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int16_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo (int16_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrhq_gather_shifted_offset_z_s32 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int16_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo1 (int16_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrhq_gather_shifted_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint16_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo (uint16_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrhq_gather_shifted_offset_z_u16 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (uint16_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo1 (uint16_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrhq_gather_shifted_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint16_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo (uint16_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrhq_gather_shifted_offset_z_u32 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint16_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo1 (uint16_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrhq_gather_shifted_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c +@@ -1,14 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16_t const * base) ++foo (int16_t const *base) + { + return vldrhq_s16 (base); + } + +-/* { dg-final { scan-assembler-times "vldrh.16" 1 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c +@@ -1,14 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int16_t const * base) ++foo (int16_t const *base) + { + return vldrhq_s32 (base); + } + +-/* { dg-final { scan-assembler-times "vldrh.s32" 1 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c +@@ -1,14 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint16_t const * base) ++foo (uint16_t const *base) + { + return vldrhq_u16 (base); + } + +-/* { dg-final { scan-assembler-times "vldrh.16" 1 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c +@@ -1,14 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint16_t const * base) ++foo (uint16_t const *base) + { + return vldrhq_u32 (base); + } + +-/* { dg-final { scan-assembler-times "vldrh.u32" 1 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c +@@ -1,15 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16_t const * base, mve_pred16_t p) ++foo (float16_t const *base, mve_pred16_t p) + { + return vldrhq_z_f16 (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 1 } } */ +-/* { dg-final { scan-assembler-times "vldrht.16" 1 } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c +@@ -1,15 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16_t const * base, mve_pred16_t p) ++foo (int16_t const *base, mve_pred16_t p) + { + return vldrhq_z_s16 (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 1 } } */ +-/* { dg-final { scan-assembler-times "vldrht.16" 1 } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c +@@ -1,15 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int16_t const * base, mve_pred16_t p) ++foo (int16_t const *base, mve_pred16_t p) + { + return vldrhq_z_s32 (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 1 } } */ +-/* { dg-final { scan-assembler-times "vldrht.s32" 1 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c +@@ -1,15 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint16_t const * base, mve_pred16_t p) ++foo (uint16_t const *base, mve_pred16_t p) + { + return vldrhq_z_u16 (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 1 } } */ +-/* { dg-final { scan-assembler-times "vldrht.16" 1 } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c +@@ -1,15 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint16_t const * base, mve_pred16_t p) ++foo (uint16_t const *base, mve_pred16_t p) + { + return vldrhq_z_u32 (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 1 } } */ +-/* { dg-final { scan-assembler-times "vldrht.u32" 1 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c +@@ -1,14 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32_t const * base) ++foo (float32_t const *base) + { + return vldrwq_f32 (base); + } + +-/* { dg-final { scan-assembler-times "vldrw.32" 1 } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + float32x4_t + foo (uint32x4_t addr) + { +- return vldrwq_gather_base_f32 (addr, 4); ++ return vldrwq_gather_base_f32 (addr, 0); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrw.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + int32x4_t + foo (uint32x4_t addr) + { +- return vldrwq_gather_base_s32 (addr, 4); ++ return vldrwq_gather_base_s32 (addr, 0); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrw.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t addr) + { +- return vldrwq_gather_base_u32 (addr, 4); ++ return vldrwq_gather_base_u32 (addr, 0); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrw.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c +@@ -1,16 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + float32x4_t +-foo (uint32x4_t * addr) ++foo (uint32x4_t *addr) + { +- return vldrwq_gather_base_wb_f32 (addr, 8); ++ return vldrwq_gather_base_wb_f32 (addr, 0); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ +-/* { dg-final { scan-assembler "vldrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ +-/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c +@@ -1,16 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (uint32x4_t * addr) ++foo (uint32x4_t *addr) + { +- return vldrwq_gather_base_wb_s32 (addr, 8); ++ return vldrwq_gather_base_wb_s32 (addr, 0); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ +-/* { dg-final { scan-assembler "vldrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ +-/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c +@@ -1,16 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t * addr) ++foo (uint32x4_t *addr) + { +- return vldrwq_gather_base_wb_u32 (addr, 8); ++ return vldrwq_gather_base_wb_u32 (addr, 0); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ +-/* { dg-final { scan-assembler "vldrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ +-/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c +@@ -1,18 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + float32x4_t +-foo (uint32x4_t * addr, mve_pred16_t p) ++foo (uint32x4_t *addr, mve_pred16_t p) + { +- return vldrwq_gather_base_wb_z_f32 (addr, 8, p); ++ return vldrwq_gather_base_wb_z_f32 (addr, 0, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ +-/* { dg-final { scan-assembler "vmsr\tp0, r\[0-9\]+.*" } } */ +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ +-/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c +@@ -1,18 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (uint32x4_t * addr, mve_pred16_t p) ++foo (uint32x4_t *addr, mve_pred16_t p) + { +- return vldrwq_gather_base_wb_z_s32 (addr, 8, p); ++ return vldrwq_gather_base_wb_z_s32 (addr, 0, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ +-/* { dg-final { scan-assembler "vmsr\tp0, r\[0-9\]+.*" } } */ +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ +-/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c +@@ -1,18 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t * addr, mve_pred16_t p) ++foo (uint32x4_t *addr, mve_pred16_t p) + { +- return vldrwq_gather_base_wb_z_u32 (addr, 8, p); ++ return vldrwq_gather_base_wb_z_u32 (addr, 0, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ +-/* { dg-final { scan-assembler "vmsr\tp0, r\[0-9\]+.*" } } */ +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ +-/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c +@@ -1,13 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + float32x4_t + foo (uint32x4_t addr, mve_pred16_t p) + { +- return vldrwq_gather_base_z_f32 (addr, 4, p); ++ return vldrwq_gather_base_z_f32 (addr, 0, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrwt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c +@@ -1,13 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + int32x4_t + foo (uint32x4_t addr, mve_pred16_t p) + { +- return vldrwq_gather_base_z_s32 (addr, 4, p); ++ return vldrwq_gather_base_z_s32 (addr, 0, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrwt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c +@@ -1,13 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t addr, mve_pred16_t p) + { +- return vldrwq_gather_base_z_u32 (addr, 4, p); ++ return vldrwq_gather_base_z_u32 (addr, 0, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrwt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32_t const * base, uint32x4_t offset) ++foo (float32_t const *base, uint32x4_t offset) + { + return vldrwq_gather_offset_f32 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrw.u32" } } */ + ++/* ++**foo1: ++** ... ++** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + float32x4_t +-foo1 (float32_t const * base, uint32x4_t offset) ++foo1 (float32_t const *base, uint32x4_t offset) + { + return vldrwq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrw.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32_t const * base, uint32x4_t offset) ++foo (int32_t const *base, uint32x4_t offset) + { + return vldrwq_gather_offset_s32 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrw.u32" } } */ + ++/* ++**foo1: ++** ... ++** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32_t const * base, uint32x4_t offset) ++foo1 (int32_t const *base, uint32x4_t offset) + { + return vldrwq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrw.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32_t const * base, uint32x4_t offset) ++foo (uint32_t const *base, uint32x4_t offset) + { + return vldrwq_gather_offset_u32 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrw.u32" } } */ + ++/* ++**foo1: ++** ... ++** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32_t const * base, uint32x4_t offset) ++foo1 (uint32_t const *base, uint32x4_t offset) + { + return vldrwq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrw.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo (float32_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrwq_gather_offset_z_f32 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrwt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + float32x4_t +-foo1 (float32_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo1 (float32_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrwq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrwt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo (int32_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrwq_gather_offset_z_s32 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrwt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo1 (int32_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrwq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrwt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo (uint32_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrwq_gather_offset_z_u32 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrwt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo1 (uint32_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrwq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrwt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32_t const * base, uint32x4_t offset) ++foo (float32_t const *base, uint32x4_t offset) + { + return vldrwq_gather_shifted_offset_f32 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrw.u32" } } */ + ++/* ++**foo1: ++** ... ++** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + float32x4_t +-foo1 (float32_t const * base, uint32x4_t offset) ++foo1 (float32_t const *base, uint32x4_t offset) + { + return vldrwq_gather_shifted_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrw.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32_t const * base, uint32x4_t offset) ++foo (int32_t const *base, uint32x4_t offset) + { + return vldrwq_gather_shifted_offset_s32 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrw.u32" } } */ + ++/* ++**foo1: ++** ... ++** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32_t const * base, uint32x4_t offset) ++foo1 (int32_t const *base, uint32x4_t offset) + { + return vldrwq_gather_shifted_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrw.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32_t const * base, uint32x4_t offset) ++foo (uint32_t const *base, uint32x4_t offset) + { + return vldrwq_gather_shifted_offset_u32 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrw.u32" } } */ + ++/* ++**foo1: ++** ... ++** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32_t const * base, uint32x4_t offset) ++foo1 (uint32_t const *base, uint32x4_t offset) + { + return vldrwq_gather_shifted_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrw.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo (float32_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrwq_gather_shifted_offset_z_f32 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrwt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + float32x4_t +-foo1 (float32_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo1 (float32_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrwq_gather_shifted_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrwt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo (int32_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrwq_gather_shifted_offset_z_s32 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrwt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo1 (int32_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrwq_gather_shifted_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrwt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo (uint32_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrwq_gather_shifted_offset_z_u32 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrwt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo1 (uint32_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrwq_gather_shifted_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrwt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c +@@ -1,14 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32_t const * base) ++foo (int32_t const *base) + { + return vldrwq_s32 (base); + } + +-/* { dg-final { scan-assembler-times "vldrw.32" 1 } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c +@@ -1,14 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32_t const * base) ++foo (uint32_t const *base) + { + return vldrwq_u32 (base); + } + +-/* { dg-final { scan-assembler-times "vldrw.32" 1 } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c +@@ -1,15 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32_t const * base, mve_pred16_t p) ++foo (float32_t const *base, mve_pred16_t p) + { + return vldrwq_z_f32 (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 1 } } */ +-/* { dg-final { scan-assembler-times "vldrwt.32" 1 } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c +@@ -1,15 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32_t const * base, mve_pred16_t p) ++foo (int32_t const *base, mve_pred16_t p) + { + return vldrwq_z_s32 (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 1 } } */ +-/* { dg-final { scan-assembler-times "vldrwt.32" 1 } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c +@@ -1,15 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32_t const * base, mve_pred16_t p) ++foo (uint32_t const *base, mve_pred16_t p) + { + return vldrwq_z_u32 (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 1 } } */ +-/* { dg-final { scan-assembler-times "vldrwt.32" 1 } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16_t +-foo1 (float16_t a, float16x8_t b) +-{ +- return vmaxnmavq (a, b); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32_t +-foo1 (float32_t a, float32x4_t b) +-{ +- return vmaxnmavq (a, b); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16_t +-foo1 (float16_t a, float16x8_t b, mve_pred16_t p) +-{ +- return vmaxnmavq_p (a, b, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32_t +-foo1 (float32_t a, float32x4_t b, mve_pred16_t p) +-{ +- return vmaxnmavq_p (a, b, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16_t +-foo1 (float16_t a, float16x8_t b) +-{ +- return vmaxnmvq (23.35, b); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32_t +-foo1 (float32_t a, float32x4_t b) +-{ +- return vmaxnmvq (34.56, b); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16_t +-foo1 (float16_t a, float16x8_t b, mve_pred16_t p) +-{ +- return vmaxnmvq_p (a, b, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32_t +-foo1 (float32_t a, float32x4_t b, mve_pred16_t p) +-{ +- return vmaxnmvq_p (a, b, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16_t +-foo1 (float16_t a, float16x8_t b) +-{ +- return vminnmavq (a, b); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32_t +-foo1 (float32_t a, float32x4_t b) +-{ +- return vminnmavq (a, b); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16_t +-foo1 (float16_t a, float16x8_t b, mve_pred16_t p) +-{ +- return vminnmavq_p (a, b, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32_t +-foo1 (float32_t a, float32x4_t b, mve_pred16_t p) +-{ +- return vminnmavq_p (a, b, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16_t +-foo1 (float16_t a, float16x8_t b) +-{ +- return vminnmvq (a, b); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32_t +-foo1 (float32_t a, float32x4_t b) +-{ +- return vminnmvq (a, b); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16_t +-foo1 (float16_t a, float16x8_t b, mve_pred16_t p) +-{ +- return vminnmvq_p (a, b, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32_t +-foo1 (float32_t a, float32x4_t b, mve_pred16_t p) +-{ +- return vminnmvq_p (a, b, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int16x8_t a, int16x8_t b, mve_pred16_t p) ++foo (int16x8_t m1, int16x8_t m2, mve_pred16_t p) + { +- return vmladavq_p_s16 (a, b, p); ++ return vmladavq_p_s16 (m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmladavt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) ++foo1 (int16x8_t m1, int16x8_t m2, mve_pred16_t p) + { +- return vmladavq_p (a, b, p); ++ return vmladavq_p (m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavt.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int32x4_t a, int32x4_t b, mve_pred16_t p) ++foo (int32x4_t m1, int32x4_t m2, mve_pred16_t p) + { +- return vmladavq_p_s32 (a, b, p); ++ return vmladavq_p_s32 (m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmladavt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) ++foo1 (int32x4_t m1, int32x4_t m2, mve_pred16_t p) + { +- return vmladavq_p (a, b, p); ++ return vmladavq_p (m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavt.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int8x16_t a, int8x16_t b, mve_pred16_t p) ++foo (int8x16_t m1, int8x16_t m2, mve_pred16_t p) + { +- return vmladavq_p_s8 (a, b, p); ++ return vmladavq_p_s8 (m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmladavt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) ++foo1 (int8x16_t m1, int8x16_t m2, mve_pred16_t p) + { +- return vmladavq_p (a, b, p); ++ return vmladavq_p (m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavt.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavt.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) ++foo (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p) + { +- return vmladavq_p_u16 (a, b, p); ++ return vmladavq_p_u16 (m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmladavt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavt.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) ++foo1 (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p) + { +- return vmladavq_p (a, b, p); ++ return vmladavq_p (m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavt.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavt.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) ++foo (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p) + { +- return vmladavq_p_u32 (a, b, p); ++ return vmladavq_p_u32 (m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmladavt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavt.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) ++foo1 (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p) + { +- return vmladavq_p (a, b, p); ++ return vmladavq_p (m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavt.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) ++foo (uint8x16_t m1, uint8x16_t m2, mve_pred16_t p) + { +- return vmladavq_p_u8 (a, b, p); ++ return vmladavq_p_u8 (m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmladavt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavt.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) ++foo1 (uint8x16_t m1, uint8x16_t m2, mve_pred16_t p) + { +- return vmladavq_p (a, b, p); ++ return vmladavq_p (m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavt.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmladav.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int16x8_t a, int16x8_t b) ++foo (int16x8_t m1, int16x8_t m2) + { +- return vmladavq_s16 (a, b); ++ return vmladavq_s16 (m1, m2); + } + +-/* { dg-final { scan-assembler "vmladav.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmladav.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int16x8_t a, int16x8_t b) ++foo1 (int16x8_t m1, int16x8_t m2) + { +- return vmladavq (a, b); ++ return vmladavq (m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladav.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmladav.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int32x4_t a, int32x4_t b) ++foo (int32x4_t m1, int32x4_t m2) + { +- return vmladavq_s32 (a, b); ++ return vmladavq_s32 (m1, m2); + } + +-/* { dg-final { scan-assembler "vmladav.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmladav.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int32x4_t a, int32x4_t b) ++foo1 (int32x4_t m1, int32x4_t m2) + { +- return vmladavq (a, b); ++ return vmladavq (m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladav.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmladav.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int8x16_t a, int8x16_t b) ++foo (int8x16_t m1, int8x16_t m2) + { +- return vmladavq_s8 (a, b); ++ return vmladavq_s8 (m1, m2); + } + +-/* { dg-final { scan-assembler "vmladav.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmladav.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int8x16_t a, int8x16_t b) ++foo1 (int8x16_t m1, int8x16_t m2) + { +- return vmladavq (a, b); ++ return vmladavq (m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladav.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmladav.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo (uint16x8_t a, uint16x8_t b) ++foo (uint16x8_t m1, uint16x8_t m2) + { +- return vmladavq_u16 (a, b); ++ return vmladavq_u16 (m1, m2); + } + +-/* { dg-final { scan-assembler "vmladav.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmladav.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo1 (uint16x8_t a, uint16x8_t b) ++foo1 (uint16x8_t m1, uint16x8_t m2) + { +- return vmladavq (a, b); ++ return vmladavq (m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladav.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmladav.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo (uint32x4_t a, uint32x4_t b) ++foo (uint32x4_t m1, uint32x4_t m2) + { +- return vmladavq_u32 (a, b); ++ return vmladavq_u32 (m1, m2); + } + +-/* { dg-final { scan-assembler "vmladav.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmladav.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo1 (uint32x4_t a, uint32x4_t b) ++foo1 (uint32x4_t m1, uint32x4_t m2) + { +- return vmladavq (a, b); ++ return vmladavq (m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladav.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmladav.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo (uint8x16_t a, uint8x16_t b) ++foo (uint8x16_t m1, uint8x16_t m2) + { +- return vmladavq_u8 (a, b); ++ return vmladavq_u8 (m1, m2); + } + +-/* { dg-final { scan-assembler "vmladav.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmladav.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo1 (uint8x16_t a, uint8x16_t b) ++foo1 (uint8x16_t m1, uint8x16_t m2) + { +- return vmladavq (a, b); ++ return vmladavq (m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladav.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavxt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int16x8_t a, int16x8_t b, mve_pred16_t p) ++foo (int16x8_t m1, int16x8_t m2, mve_pred16_t p) + { +- return vmladavxq_p_s16 (a, b, p); ++ return vmladavxq_p_s16 (m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmladavxt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavxt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) ++foo1 (int16x8_t m1, int16x8_t m2, mve_pred16_t p) + { +- return vmladavxq_p (a, b, p); ++ return vmladavxq_p (m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavxt.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavxt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int32x4_t a, int32x4_t b, mve_pred16_t p) ++foo (int32x4_t m1, int32x4_t m2, mve_pred16_t p) + { +- return vmladavxq_p_s32 (a, b, p); ++ return vmladavxq_p_s32 (m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmladavxt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavxt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) ++foo1 (int32x4_t m1, int32x4_t m2, mve_pred16_t p) + { +- return vmladavxq_p (a, b, p); ++ return vmladavxq_p (m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavxt.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavxt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int8x16_t a, int8x16_t b, mve_pred16_t p) ++foo (int8x16_t m1, int8x16_t m2, mve_pred16_t p) + { +- return vmladavxq_p_s8 (a, b, p); ++ return vmladavxq_p_s8 (m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmladavxt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavxt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) ++foo1 (int8x16_t m1, int8x16_t m2, mve_pred16_t p) + { +- return vmladavxq_p (a, b, p); ++ return vmladavxq_p (m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavxt.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmladavx.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int16x8_t a, int16x8_t b) ++foo (int16x8_t m1, int16x8_t m2) + { +- return vmladavxq_s16 (a, b); ++ return vmladavxq_s16 (m1, m2); + } + +-/* { dg-final { scan-assembler "vmladavx.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmladavx.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int16x8_t a, int16x8_t b) ++foo1 (int16x8_t m1, int16x8_t m2) + { +- return vmladavxq (a, b); ++ return vmladavxq (m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavx.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmladavx.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int32x4_t a, int32x4_t b) ++foo (int32x4_t m1, int32x4_t m2) + { +- return vmladavxq_s32 (a, b); ++ return vmladavxq_s32 (m1, m2); + } + +-/* { dg-final { scan-assembler "vmladavx.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmladavx.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int32x4_t a, int32x4_t b) ++foo1 (int32x4_t m1, int32x4_t m2) + { +- return vmladavxq (a, b); ++ return vmladavxq (m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavx.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmladavx.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int8x16_t a, int8x16_t b) ++foo (int8x16_t m1, int8x16_t m2) + { +- return vmladavxq_s8 (a, b); ++ return vmladavxq_s8 (m1, m2); + } + +-/* { dg-final { scan-assembler "vmladavx.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmladavx.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int8x16_t a, int8x16_t b) ++foo1 (int8x16_t m1, int8x16_t m2) + { +- return vmladavxq (a, b); ++ return vmladavxq (m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavx.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavat.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) ++foo (int64_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p) + { +- return vmlaldavaq_p_s16 (a, b, c, p); ++ return vmlaldavaq_p_s16 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmlaldavat.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavat.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo1 (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) ++foo1 (int64_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p) + { +- return vmlaldavaq_p (a, b, c, p); ++ return vmlaldavaq_p (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldavat.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavat.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) ++foo (int64_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p) + { +- return vmlaldavaq_p_s32 (a, b, c, p); ++ return vmlaldavaq_p_s32 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmlaldavat.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavat.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) ++foo1 (int64_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p) + { +- return vmlaldavaq_p (a, b, c, p); ++ return vmlaldavaq_p (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldavat.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c +@@ -1,21 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavat.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo (uint64_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p) ++foo (uint64_t add, uint16x8_t m1, uint16x8_t m2, mve_pred16_t p) + { +- return vmlaldavaq_p_u16 (a, b, c, p); ++ return vmlaldavaq_p_u16 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmlaldavat.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavat.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo1 (uint64_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p) ++foo1 (uint64_t add, uint16x8_t m1, uint16x8_t m2, mve_pred16_t p) + { +- return vmlaldavaq_p (a, b, c, p); ++ return vmlaldavaq_p (add, m1, m2, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavat.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint64_t ++foo2 (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p) ++{ ++ return vmlaldavaq_p (1, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldavat.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c +@@ -1,21 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavat.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p) ++foo (uint64_t add, uint32x4_t m1, uint32x4_t m2, mve_pred16_t p) + { +- return vmlaldavaq_p_u32 (a, b, c, p); ++ return vmlaldavaq_p_u32 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmlaldavat.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavat.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo1 (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p) ++foo1 (uint64_t add, uint32x4_t m1, uint32x4_t m2, mve_pred16_t p) + { +- return vmlaldavaq_p (a, b, c, p); ++ return vmlaldavaq_p (add, m1, m2, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavat.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint64_t ++foo2 (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p) ++{ ++ return vmlaldavaq_p (1, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldavat.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlaldava.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo (int64_t a, int16x8_t b, int16x8_t c) ++foo (int64_t add, int16x8_t m1, int16x8_t m2) + { +- return vmlaldavaq_s16 (a, b, c); ++ return vmlaldavaq_s16 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmlaldava.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmlaldava.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo1 (int64_t a, int16x8_t b, int16x8_t c) ++foo1 (int64_t add, int16x8_t m1, int16x8_t m2) + { +- return vmlaldavaq (a, b, c); ++ return vmlaldavaq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldava.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlaldava.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo (int64_t a, int32x4_t b, int32x4_t c) ++foo (int64_t add, int32x4_t m1, int32x4_t m2) + { +- return vmlaldavaq_s32 (a, b, c); ++ return vmlaldavaq_s32 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmlaldava.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmlaldava.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo1 (int64_t a, int32x4_t b, int32x4_t c) ++foo1 (int64_t add, int32x4_t m1, int32x4_t m2) + { +- return vmlaldavaq (a, b, c); ++ return vmlaldavaq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldava.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlaldava.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo (uint64_t a, uint16x8_t b, uint16x8_t c) ++foo (uint64_t add, uint16x8_t m1, uint16x8_t m2) + { +- return vmlaldavaq_u16 (a, b, c); ++ return vmlaldavaq_u16 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmlaldava.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmlaldava.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo1 (uint64_t a, uint16x8_t b, uint16x8_t c) ++foo1 (uint64_t add, uint16x8_t m1, uint16x8_t m2) + { +- return vmlaldavaq (a, b, c); ++ return vmlaldavaq (add, m1, m2); ++} ++ ++/* ++**foo2: ++** ... ++** vmlaldava.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint64_t ++foo2 (uint16x8_t m1, uint16x8_t m2) ++{ ++ return vmlaldavaq (1, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldava.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlaldava.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo (uint64_t a, uint32x4_t b, uint32x4_t c) ++foo (uint64_t add, uint32x4_t m1, uint32x4_t m2) + { +- return vmlaldavaq_u32 (a, b, c); ++ return vmlaldavaq_u32 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmlaldava.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmlaldava.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo1 (uint64_t a, uint32x4_t b, uint32x4_t c) ++foo1 (uint64_t add, uint32x4_t m1, uint32x4_t m2) + { +- return vmlaldavaq (a, b, c); ++ return vmlaldavaq (add, m1, m2); ++} ++ ++/* ++**foo2: ++** ... ++** vmlaldava.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint64_t ++foo2 (uint32x4_t m1, uint32x4_t m2) ++{ ++ return vmlaldavaq (1, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldava.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c +@@ -46,4 +46,4 @@ foo1 (int64_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c +@@ -46,4 +46,4 @@ foo1 (int64_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c +@@ -38,4 +38,4 @@ foo1 (int64_t add, int16x8_t m1, int16x8_t m2) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c +@@ -38,4 +38,4 @@ foo1 (int64_t add, int32x4_t m1, int32x4_t m2) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo (int16x8_t a, int16x8_t b, mve_pred16_t p) ++foo (int16x8_t m1, int16x8_t m2, mve_pred16_t p) + { +- return vmlaldavq_p_s16 (a, b, p); ++ return vmlaldavq_p_s16 (m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmlaldavt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) ++foo1 (int16x8_t m1, int16x8_t m2, mve_pred16_t p) + { +- return vmlaldavq_p (a, b, p); ++ return vmlaldavq_p (m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldavt.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo (int32x4_t a, int32x4_t b, mve_pred16_t p) ++foo (int32x4_t m1, int32x4_t m2, mve_pred16_t p) + { +- return vmlaldavq_p_s32 (a, b, p); ++ return vmlaldavq_p_s32 (m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmlaldavt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) ++foo1 (int32x4_t m1, int32x4_t m2, mve_pred16_t p) + { +- return vmlaldavq_p (a, b, p); ++ return vmlaldavq_p (m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldavt.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavt.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) ++foo (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p) + { +- return vmlaldavq_p_u16 (a, b, p); ++ return vmlaldavq_p_u16 (m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmlaldavt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavt.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) ++foo1 (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p) + { +- return vmlaldavq_p (a, b, p); ++ return vmlaldavq_p (m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldavt.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavt.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) ++foo (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p) + { +- return vmlaldavq_p_u32 (a, b, p); ++ return vmlaldavq_p_u32 (m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmlaldavt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavt.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) ++foo1 (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p) + { +- return vmlaldavq_p (a, b, p); ++ return vmlaldavq_p (m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldavt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlaldav.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo (int16x8_t a, int16x8_t b) ++foo (int16x8_t m1, int16x8_t m2) + { +- return vmlaldavq_s16 (a, b); ++ return vmlaldavq_s16 (m1, m2); + } + +-/* { dg-final { scan-assembler "vmlaldav.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmlaldav.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo1 (int16x8_t a, int16x8_t b) ++foo1 (int16x8_t m1, int16x8_t m2) + { +- return vmlaldavq (a, b); ++ return vmlaldavq (m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldav.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlaldav.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo (int32x4_t a, int32x4_t b) ++foo (int32x4_t m1, int32x4_t m2) + { +- return vmlaldavq_s32 (a, b); ++ return vmlaldavq_s32 (m1, m2); + } + +-/* { dg-final { scan-assembler "vmlaldav.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmlaldav.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo1 (int32x4_t a, int32x4_t b) ++foo1 (int32x4_t m1, int32x4_t m2) + { +- return vmlaldavq (a, b); ++ return vmlaldavq (m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldav.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlaldav.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo (uint16x8_t a, uint16x8_t b) ++foo (uint16x8_t m1, uint16x8_t m2) + { +- return vmlaldavq_u16 (a, b); ++ return vmlaldavq_u16 (m1, m2); + } + +-/* { dg-final { scan-assembler "vmlaldav.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmlaldav.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo1 (uint16x8_t a, uint16x8_t b) ++foo1 (uint16x8_t m1, uint16x8_t m2) + { +- return vmlaldavq (a, b); ++ return vmlaldavq (m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldav.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlaldav.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo (uint32x4_t a, uint32x4_t b) ++foo (uint32x4_t m1, uint32x4_t m2) + { +- return vmlaldavq_u32 (a, b); ++ return vmlaldavq_u32 (m1, m2); + } + +-/* { dg-final { scan-assembler "vmlaldav.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmlaldav.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo1 (uint32x4_t a, uint32x4_t b) ++foo1 (uint32x4_t m1, uint32x4_t m2) + { +- return vmlaldavq (a, b); ++ return vmlaldavq (m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldav.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavxt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo (int16x8_t a, int16x8_t b, mve_pred16_t p) ++foo (int16x8_t m1, int16x8_t m2, mve_pred16_t p) + { +- return vmlaldavxq_p_s16 (a, b, p); ++ return vmlaldavxq_p_s16 (m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmlaldavxt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavxt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) ++foo1 (int16x8_t m1, int16x8_t m2, mve_pred16_t p) + { +- return vmlaldavxq_p (a, b, p); ++ return vmlaldavxq_p (m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldavxt.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo (int32x4_t a, int32x4_t b, mve_pred16_t p) ++foo (int32x4_t m1, int32x4_t m2, mve_pred16_t p) + { +- return vmlaldavxq_p_s32 (a, b, p); ++ return vmlaldavxq_p_s32 (m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmlaldavxt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) ++foo1 (int32x4_t m1, int32x4_t m2, mve_pred16_t p) + { +- return vmlaldavxq_p (a, b, p); ++ return vmlaldavxq_p (m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldavxt.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlaldavx.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo (int16x8_t a, int16x8_t b) ++foo (int16x8_t m1, int16x8_t m2) + { +- return vmlaldavxq_s16 (a, b); ++ return vmlaldavxq_s16 (m1, m2); + } + +-/* { dg-final { scan-assembler "vmlaldavx.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmlaldavx.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo1 (int16x8_t a, int16x8_t b) ++foo1 (int16x8_t m1, int16x8_t m2) + { +- return vmlaldavxq (a, b); ++ return vmlaldavxq (m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldavx.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlaldavx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo (int32x4_t a, int32x4_t b) ++foo (int32x4_t m1, int32x4_t m2) + { +- return vmlaldavxq_s32 (a, b); ++ return vmlaldavxq_s32 (m1, m2); + } + +-/* { dg-final { scan-assembler "vmlaldavx.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmlaldavx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo1 (int32x4_t a, int32x4_t b) ++foo1 (int32x4_t m1, int32x4_t m2) + { +- return vmlaldavxq (a, b); ++ return vmlaldavxq (m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldavx.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlat.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) ++foo (int16x8_t add, int16x8_t m1, int16_t m2, mve_pred16_t p) + { +- return vmlaq_m_n_s16 (a, b, c, p); ++ return vmlaq_m_n_s16 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlat.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlat.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) ++foo1 (int16x8_t add, int16x8_t m1, int16_t m2, mve_pred16_t p) + { +- return vmlaq_m (a, b, c, p); ++ return vmlaq_m (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlat.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlat.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) ++foo (int32x4_t add, int32x4_t m1, int32_t m2, mve_pred16_t p) + { +- return vmlaq_m_n_s32 (a, b, c, p); ++ return vmlaq_m_n_s32 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlat.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlat.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) ++foo1 (int32x4_t add, int32x4_t m1, int32_t m2, mve_pred16_t p) + { +- return vmlaq_m (a, b, c, p); ++ return vmlaq_m (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlat.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlat.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t +-foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) ++foo (int8x16_t add, int8x16_t m1, int8_t m2, mve_pred16_t p) + { +- return vmlaq_m_n_s8 (a, b, c, p); ++ return vmlaq_m_n_s8 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlat.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlat.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t +-foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) ++foo1 (int8x16_t add, int8x16_t m1, int8_t m2, mve_pred16_t p) + { +- return vmlaq_m (a, b, c, p); ++ return vmlaq_m (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlat.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlat.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint16x8_t a, uint16x8_t b, uint16_t c, mve_pred16_t p) ++foo (uint16x8_t add, uint16x8_t m1, uint16_t m2, mve_pred16_t p) + { +- return vmlaq_m_n_u16 (a, b, c, p); ++ return vmlaq_m_n_u16 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlat.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlat.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (uint16x8_t a, uint16x8_t b, uint16_t c, mve_pred16_t p) ++foo1 (uint16x8_t add, uint16x8_t m1, uint16_t m2, mve_pred16_t p) + { +- return vmlaq_m (a, b, c, p); ++ return vmlaq_m (add, m1, m2, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlat.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t add, uint16x8_t m1, mve_pred16_t p) ++{ ++ return vmlaq_m (add, m1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlat.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlat.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t a, uint32x4_t b, uint32_t c, mve_pred16_t p) ++foo (uint32x4_t add, uint32x4_t m1, uint32_t m2, mve_pred16_t p) + { +- return vmlaq_m_n_u32 (a, b, c, p); ++ return vmlaq_m_n_u32 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlat.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlat.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32x4_t a, uint32x4_t b, uint32_t c, mve_pred16_t p) ++foo1 (uint32x4_t add, uint32x4_t m1, uint32_t m2, mve_pred16_t p) + { +- return vmlaq_m (a, b, c, p); ++ return vmlaq_m (add, m1, m2, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlat.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t add, uint32x4_t m1, mve_pred16_t p) ++{ ++ return vmlaq_m (add, m1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlat.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlat.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo (uint8x16_t a, uint8x16_t b, uint8_t c, mve_pred16_t p) ++foo (uint8x16_t add, uint8x16_t m1, uint8_t m2, mve_pred16_t p) + { +- return vmlaq_m_n_u8 (a, b, c, p); ++ return vmlaq_m_n_u8 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlat.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlat.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo1 (uint8x16_t a, uint8x16_t b, uint8_t c, mve_pred16_t p) ++foo1 (uint8x16_t add, uint8x16_t m1, uint8_t m2, mve_pred16_t p) + { +- return vmlaq_m (a, b, c, p); ++ return vmlaq_m (add, m1, m2, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlat.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t add, uint8x16_t m1, mve_pred16_t p) ++{ ++ return vmlaq_m (add, m1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlat.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmla.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16x8_t a, int16x8_t b, int16_t c) ++foo (int16x8_t add, int16x8_t m1, int16_t m2) + { +- return vmlaq_n_s16 (a, b, c); ++ return vmlaq_n_s16 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmla.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmla.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int16x8_t a, int16x8_t b, int16_t c) ++foo1 (int16x8_t add, int16x8_t m1, int16_t m2) + { +- return vmlaq (a, b, c); ++ return vmlaq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmla.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmla.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t a, int32x4_t b, int32_t c) ++foo (int32x4_t add, int32x4_t m1, int32_t m2) + { +- return vmlaq_n_s32 (a, b, c); ++ return vmlaq_n_s32 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmla.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmla.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t a, int32x4_t b, int32_t c) ++foo1 (int32x4_t add, int32x4_t m1, int32_t m2) + { +- return vmlaq (a, b, c); ++ return vmlaq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmla.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmla.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t +-foo (int8x16_t a, int8x16_t b, int8_t c) ++foo (int8x16_t add, int8x16_t m1, int8_t m2) + { +- return vmlaq_n_s8 (a, b, c); ++ return vmlaq_n_s8 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmla.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmla.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t +-foo1 (int8x16_t a, int8x16_t b, int8_t c) ++foo1 (int8x16_t add, int8x16_t m1, int8_t m2) + { +- return vmlaq (a, b, c); ++ return vmlaq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmla.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmla.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint16x8_t a, uint16x8_t b, uint16_t c) ++foo (uint16x8_t add, uint16x8_t m1, uint16_t m2) + { +- return vmlaq_n_u16 (a, b, c); ++ return vmlaq_n_u16 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmla.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmla.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (uint16x8_t a, uint16x8_t b, uint16_t c) ++foo1 (uint16x8_t add, uint16x8_t m1, uint16_t m2) + { +- return vmlaq (a, b, c); ++ return vmlaq (add, m1, m2); ++} ++ ++/* ++**foo2: ++** ... ++** vmla.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t add, uint16x8_t m1) ++{ ++ return vmlaq (add, m1, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmla.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmla.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t a, uint32x4_t b, uint32_t c) ++foo (uint32x4_t add, uint32x4_t m1, uint32_t m2) + { +- return vmlaq_n_u32 (a, b, c); ++ return vmlaq_n_u32 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmla.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmla.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32x4_t a, uint32x4_t b, uint32_t c) ++foo1 (uint32x4_t add, uint32x4_t m1, uint32_t m2) + { +- return vmlaq (a, b, c); ++ return vmlaq (add, m1, m2); ++} ++ ++/* ++**foo2: ++** ... ++** vmla.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t add, uint32x4_t m1) ++{ ++ return vmlaq (add, m1, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmla.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmla.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo (uint8x16_t a, uint8x16_t b, uint8_t c) ++foo (uint8x16_t add, uint8x16_t m1, uint8_t m2) + { +- return vmlaq_n_u8 (a, b, c); ++ return vmlaq_n_u8 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmla.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmla.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo1 (uint8x16_t a, uint8x16_t b, uint8_t c) ++foo1 (uint8x16_t add, uint8x16_t m1, uint8_t m2) + { +- return vmlaq (a, b, c); ++ return vmlaq (add, m1, m2); ++} ++ ++/* ++**foo2: ++** ... ++** vmla.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t add, uint8x16_t m1) ++{ ++ return vmlaq (add, m1, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmla.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavat.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) + { + return vmlsdavaq_p_s16 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsdavat.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavat.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) + { + return vmlsdavaq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsdavat.s16" } } */ +-/* { dg-final { scan-assembler "vmlsdavat.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavat.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vmlsdavaq_p_s32 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsdavat.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavat.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vmlsdavaq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsdavat.s32" } } */ +-/* { dg-final { scan-assembler "vmlsdavat.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavat.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p) + { + return vmlsdavaq_p_s8 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsdavat.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavat.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p) + { + return vmlsdavaq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsdavat.s8" } } */ +-/* { dg-final { scan-assembler "vmlsdavat.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsdava.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int16x8_t b, int16x8_t c) + { + return vmlsdavaq_s16 (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsdava.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmlsdava.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int16x8_t b, int16x8_t c) + { + return vmlsdavaq (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsdava.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsdava.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int32x4_t b, int32x4_t c) + { + return vmlsdavaq_s32 (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsdava.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmlsdava.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int32x4_t b, int32x4_t c) + { + return vmlsdavaq (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsdava.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsdava.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int8x16_t b, int8x16_t c) + { + return vmlsdavaq_s8 (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsdava.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmlsdava.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int8x16_t b, int8x16_t c) + { + return vmlsdavaq (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsdava.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavaxt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) + { + return vmlsdavaxq_p_s16 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsdavaxt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavaxt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) + { + return vmlsdavaxq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsdavaxt.s16" } } */ +-/* { dg-final { scan-assembler "vmlsdavaxt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavaxt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vmlsdavaxq_p_s32 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsdavaxt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavaxt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vmlsdavaxq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsdavaxt.s32" } } */ +-/* { dg-final { scan-assembler "vmlsdavaxt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavaxt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p) + { + return vmlsdavaxq_p_s8 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsdavaxt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavaxt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p) + { + return vmlsdavaxq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsdavaxt.s8" } } */ +-/* { dg-final { scan-assembler "vmlsdavaxt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsdavax.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int16x8_t b, int16x8_t c) + { + return vmlsdavaxq_s16 (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsdavax.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmlsdavax.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int16x8_t b, int16x8_t c) + { + return vmlsdavaxq (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsdavax.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsdavax.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int32x4_t b, int32x4_t c) + { + return vmlsdavaxq_s32 (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsdavax.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmlsdavax.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int32x4_t b, int32x4_t c) + { + return vmlsdavaxq (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsdavax.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsdavax.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int8x16_t b, int8x16_t c) + { + return vmlsdavaxq_s8 (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsdavax.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmlsdavax.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int8x16_t b, int8x16_t c) + { + return vmlsdavaxq (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsdavax.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmlsdavq_p_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsdavt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmlsdavq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsdavt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmlsdavq_p_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsdavt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmlsdavq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsdavt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vmlsdavq_p_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsdavt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vmlsdavq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsdavt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsdav.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int16x8_t a, int16x8_t b) + { + return vmlsdavq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vmlsdav.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmlsdav.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int16x8_t a, int16x8_t b) + { + return vmlsdavq (a, b); + } + +-/* { dg-final { scan-assembler "vmlsdav.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsdav.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32x4_t a, int32x4_t b) + { + return vmlsdavq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vmlsdav.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmlsdav.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32x4_t a, int32x4_t b) + { + return vmlsdavq (a, b); + } + +-/* { dg-final { scan-assembler "vmlsdav.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsdav.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int8x16_t a, int8x16_t b) + { + return vmlsdavq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vmlsdav.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmlsdav.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int8x16_t a, int8x16_t b) + { + return vmlsdavq (a, b); + } + +-/* { dg-final { scan-assembler "vmlsdav.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavxt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmlsdavxq_p_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsdavxt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavxt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmlsdavxq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsdavxt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavxt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmlsdavxq_p_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsdavxt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavxt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmlsdavxq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsdavxt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavxt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vmlsdavxq_p_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsdavxt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavxt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vmlsdavxq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsdavxt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsdavx.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int16x8_t a, int16x8_t b) + { + return vmlsdavxq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vmlsdavx.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmlsdavx.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int16x8_t a, int16x8_t b) + { + return vmlsdavxq (a, b); + } + +-/* { dg-final { scan-assembler "vmlsdavx.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsdavx.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32x4_t a, int32x4_t b) + { + return vmlsdavxq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vmlsdavx.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmlsdavx.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32x4_t a, int32x4_t b) + { + return vmlsdavxq (a, b); + } + +-/* { dg-final { scan-assembler "vmlsdavx.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsdavx.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int8x16_t a, int8x16_t b) + { + return vmlsdavxq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vmlsdavx.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmlsdavx.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int8x16_t a, int8x16_t b) + { + return vmlsdavxq (a, b); + } + +-/* { dg-final { scan-assembler "vmlsdavx.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavat.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) + { + return vmlsldavaq_p_s16 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsldavat.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavat.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) + { + return vmlsldavaq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsldavat.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavat.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vmlsldavaq_p_s32 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsldavat.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavat.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vmlsldavaq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsldavat.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsldava.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int16x8_t b, int16x8_t c) + { + return vmlsldavaq_s16 (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsldava.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmlsldava.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int16x8_t b, int16x8_t c) + { + return vmlsldavaq (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsldava.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsldava.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int32x4_t b, int32x4_t c) + { + return vmlsldavaq_s32 (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsldava.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmlsldava.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int32x4_t b, int32x4_t c) + { + return vmlsldavaq (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsldava.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavaxt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) + { + return vmlsldavaxq_p_s16 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsldavaxt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavaxt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) + { + return vmlsldavaxq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsldavaxt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavaxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vmlsldavaxq_p_s32 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsldavaxt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavaxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vmlsldavaxq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsldavaxt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsldavax.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int16x8_t b, int16x8_t c) + { + return vmlsldavaxq_s16 (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsldavax.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmlsldavax.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int16x8_t b, int16x8_t c) + { + return vmlsldavaxq (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsldavax.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsldavax.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int32x4_t b, int32x4_t c) + { + return vmlsldavaxq_s32 (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsldavax.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmlsldavax.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int32x4_t b, int32x4_t c) + { + return vmlsldavaxq (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsldavax.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmlsldavq_p_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsldavt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmlsldavq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsldavt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmlsldavq_p_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsldavt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmlsldavq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsldavt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsldav.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int16x8_t a, int16x8_t b) + { + return vmlsldavq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vmlsldav.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmlsldav.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int16x8_t a, int16x8_t b) + { + return vmlsldavq (a, b); + } + +-/* { dg-final { scan-assembler "vmlsldav.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsldav.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int32x4_t a, int32x4_t b) + { + return vmlsldavq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vmlsldav.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmlsldav.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int32x4_t a, int32x4_t b) + { + return vmlsldavq (a, b); + } + +-/* { dg-final { scan-assembler "vmlsldav.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavxt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmlsldavxq_p_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsldavxt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavxt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmlsldavxq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsldavxt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmlsldavxq_p_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsldavxt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmlsldavxq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsldavxt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsldavx.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int16x8_t a, int16x8_t b) + { + return vmlsldavxq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vmlsldavx.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmlsldavx.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int16x8_t a, int16x8_t b) + { + return vmlsldavxq (a, b); + } + +-/* { dg-final { scan-assembler "vmlsldavx.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsldavx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int32x4_t a, int32x4_t b) + { + return vmlsldavxq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vmlsldavx.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmlsldavx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int32x4_t a, int32x4_t b) + { + return vmlsldavxq (a, b); + } + +-/* { dg-final { scan-assembler "vmlsldavx.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int16x8_t a, mve_pred16_t p) + { + return vmovlbq_m_s16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovlbt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int16x8_t a, mve_pred16_t p) + { + return vmovlbq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int8x16_t a, mve_pred16_t p) + { + return vmovlbq_m_s8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovlbt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int8x16_t a, mve_pred16_t p) + { + return vmovlbq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vmovlbq_m_u16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovlbt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vmovlbq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.u8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vmovlbq_m_u8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovlbt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.u8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vmovlbq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c +@@ -1,21 +1,41 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovlb.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int16x8_t a) + { + return vmovlbq_s16 (a); + } + +-/* { dg-final { scan-assembler "vmovlb.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmovlb.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int16x8_t a) + { + return vmovlbq (a); + } + +-/* { dg-final { scan-assembler "vmovlb.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovlb.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int8x16_t a) + { + return vmovlbq_s8 (a); + } + +-/* { dg-final { scan-assembler "vmovlb.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmovlb.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int8x16_t a) + { + return vmovlbq (a); + } + +-/* { dg-final { scan-assembler "vmovlb.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovlb.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint16x8_t a) + { +- return vmovlbq_u16 (a); ++ return vmovlbq_u16 (a); + } + +-/* { dg-final { scan-assembler "vmovlb.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmovlb.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint16x8_t a) + { +- return vmovlbq (a); ++ return vmovlbq (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmovlb.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovlb.u8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint8x16_t a) + { +- return vmovlbq_u8 (a); ++ return vmovlbq_u8 (a); + } + +-/* { dg-final { scan-assembler "vmovlb.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmovlb.u8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint8x16_t a) + { +- return vmovlbq (a); ++ return vmovlbq (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmovlb.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int16x8_t a, mve_pred16_t p) + { + return vmovlbq_x_s16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovlbt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int16x8_t a, mve_pred16_t p) + { + return vmovlbq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int8x16_t a, mve_pred16_t p) + { + return vmovlbq_x_s8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovlbt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int8x16_t a, mve_pred16_t p) + { + return vmovlbq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint16x8_t a, mve_pred16_t p) + { + return vmovlbq_x_u16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovlbt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint16x8_t a, mve_pred16_t p) + { + return vmovlbq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.u8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint8x16_t a, mve_pred16_t p) + { + return vmovlbq_x_u8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovlbt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.u8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint8x16_t a, mve_pred16_t p) + { + return vmovlbq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int16x8_t a, mve_pred16_t p) + { + return vmovltq_m_s16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovltt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int16x8_t a, mve_pred16_t p) + { + return vmovltq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int8x16_t a, mve_pred16_t p) + { + return vmovltq_m_s8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovltt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int8x16_t a, mve_pred16_t p) + { + return vmovltq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vmovltq_m_u16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovltt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vmovltq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.u8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vmovltq_m_u8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovltt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.u8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vmovltq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c +@@ -1,21 +1,41 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovlt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int16x8_t a) + { + return vmovltq_s16 (a); + } + +-/* { dg-final { scan-assembler "vmovlt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmovlt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int16x8_t a) + { + return vmovltq (a); + } + +-/* { dg-final { scan-assembler "vmovlt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovlt.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int8x16_t a) + { + return vmovltq_s8 (a); + } + +-/* { dg-final { scan-assembler "vmovlt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmovlt.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int8x16_t a) + { + return vmovltq (a); + } + +-/* { dg-final { scan-assembler "vmovlt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovlt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint16x8_t a) + { +- return vmovltq_u16 (a); ++ return vmovltq_u16 (a); + } + +-/* { dg-final { scan-assembler "vmovlt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmovlt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint16x8_t a) + { +- return vmovltq (a); ++ return vmovltq (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmovlt.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovlt.u8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint8x16_t a) + { +- return vmovltq_u8 (a); ++ return vmovltq_u8 (a); + } + +-/* { dg-final { scan-assembler "vmovlt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmovlt.u8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint8x16_t a) + { +- return vmovltq (a); ++ return vmovltq (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmovlt.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int16x8_t a, mve_pred16_t p) + { + return vmovltq_x_s16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovltt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int16x8_t a, mve_pred16_t p) + { + return vmovltq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int8x16_t a, mve_pred16_t p) + { + return vmovltq_x_s8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovltt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int8x16_t a, mve_pred16_t p) + { + return vmovltq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint16x8_t a, mve_pred16_t p) + { + return vmovltq_x_u16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovltt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint16x8_t a, mve_pred16_t p) + { + return vmovltq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.u8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint8x16_t a, mve_pred16_t p) + { + return vmovltq_x_u8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovltt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.u8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint8x16_t a, mve_pred16_t p) + { + return vmovltq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovnbt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vmovnbq_m_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovnbt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovnbt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vmovnbq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovnbt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vmovnbq_m_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovnbt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovnbt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vmovnbq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovnbt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vmovnbq_m_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovnbt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovnbt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vmovnbq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovnbt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vmovnbq_m_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovnbt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovnbt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vmovnbq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovnb.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b) + { + return vmovnbq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vmovnb.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmovnb.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b) + { + return vmovnbq (a, b); + } + +-/* { dg-final { scan-assembler "vmovnb.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovnb.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b) + { + return vmovnbq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vmovnb.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmovnb.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b) + { + return vmovnbq (a, b); + } + +-/* { dg-final { scan-assembler "vmovnb.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovnb.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b) + { + return vmovnbq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vmovnb.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmovnb.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b) + { + return vmovnbq (a, b); + } + +-/* { dg-final { scan-assembler "vmovnb.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovnb.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b) + { + return vmovnbq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vmovnb.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmovnb.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b) + { + return vmovnbq (a, b); + } + +-/* { dg-final { scan-assembler "vmovnb.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovntt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vmovntq_m_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovntt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovntt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vmovntq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovntt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vmovntq_m_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovntt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovntt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vmovntq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovntt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vmovntq_m_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovntt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovntt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vmovntq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovntt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vmovntq_m_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovntt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovntt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vmovntq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovnt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b) + { + return vmovntq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vmovnt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmovnt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b) + { + return vmovntq (a, b); + } + +-/* { dg-final { scan-assembler "vmovnt.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovnt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b) + { + return vmovntq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vmovnt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmovnt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b) + { + return vmovntq (a, b); + } + +-/* { dg-final { scan-assembler "vmovnt.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovnt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b) + { + return vmovntq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vmovnt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmovnt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b) + { + return vmovntq (a, b); + } + +-/* { dg-final { scan-assembler "vmovnt.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovnt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b) + { + return vmovntq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vmovnt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmovnt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b) + { + return vmovntq (a, b); + } + +-/* { dg-final { scan-assembler "vmovnt.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p) +-{ +- return vmulq_m (inactive, a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p) +-{ +- return vmulq_m (inactive, a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo1 (float16x8_t a, float16_t b) +-{ +- return vmulq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo1 (float32x4_t a, float32_t b) +-{ +- return vmulq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo1 (float16x8_t a, float16_t b, mve_pred16_t p) +-{ +- return vmulq_x (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo1 (float32x4_t a, float32_t b, mve_pred16_t p) +-{ +- return vmulq_x (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, mve_pred16_t p) + { +- return vmvnq_m_n_s16 (inactive, 2, p); ++ return vmvnq_m_n_s16 (inactive, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, mve_pred16_t p) + { +- return vmvnq_m (inactive, 2, p); ++ return vmvnq_m (inactive, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, mve_pred16_t p) + { +- return vmvnq_m_n_s32 (inactive, 2, p); ++ return vmvnq_m_n_s32 (inactive, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, mve_pred16_t p) + { +- return vmvnq_m (inactive, 2, p); ++ return vmvnq_m (inactive, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, mve_pred16_t p) + { +- return vmvnq_m_n_u16 (inactive, 4, p); ++ return vmvnq_m_n_u16 (inactive, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, mve_pred16_t p) + { +- return vmvnq_m (inactive, 4, p); ++ return vmvnq_m (inactive, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, mve_pred16_t p) + { +- return vmvnq_m_n_u32 (inactive, 4, p); ++ return vmvnq_m_n_u32 (inactive, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, mve_pred16_t p) + { +- return vmvnq_m (inactive, 4, p); ++ return vmvnq_m (inactive, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vmvnq_m_s16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vmvnq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vmvnq_m_s32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vmvnq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vmvnq_m_s8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vmvnq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vmvnq_m_u16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vmvnq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { + return vmvnq_m_u32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { + return vmvnq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vmvnq_m_u8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vmvnq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmvn.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo () + { + return vmvnq_n_s16 (1); + } + +-/* { dg-final { scan-assembler "vmvn.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmvn.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo () + { +- return vmvnq_n_s32 (2); ++ return vmvnq_n_s32 (1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmvn.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmvn.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo () + { +- return vmvnq_n_u16 (1); ++ return vmvnq_n_u16 (1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmvn.i16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmvn.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo () + { +- return vmvnq_n_u32 (2); ++ return vmvnq_n_u32 (1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmvn.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c +@@ -1,21 +1,41 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmvn q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a) + { + return vmvnq_s16 (a); + } + +-/* { dg-final { scan-assembler "vmvn" } } */ + ++/* ++**foo1: ++** ... ++** vmvn q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a) + { + return vmvnq (a); + } + +-/* { dg-final { scan-assembler "vmvn" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c +@@ -1,21 +1,41 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmvn q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a) + { + return vmvnq_s32 (a); + } + +-/* { dg-final { scan-assembler "vmvn" } } */ + ++/* ++**foo1: ++** ... ++** vmvn q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a) + { + return vmvnq (a); + } + +-/* { dg-final { scan-assembler "vmvn" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmvn q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a) + { + return vmvnq_s8 (a); + } + +-/* { dg-final { scan-assembler "vmvn" } } */ + ++/* ++**foo1: ++** ... ++** vmvn q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a) + { + return vmvnq (a); + } + +-/* { dg-final { scan-assembler "vmvn" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmvn q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a) + { +- return vmvnq_u16 (a); ++ return vmvnq_u16 (a); + } + +-/* { dg-final { scan-assembler "vmvn" } } */ + ++/* ++**foo1: ++** ... ++** vmvn q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a) + { +- return vmvnq (a); ++ return vmvnq (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmvn" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmvn q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a) + { +- return vmvnq_u32 (a); ++ return vmvnq_u32 (a); + } + +-/* { dg-final { scan-assembler "vmvn" } } */ + ++/* ++**foo1: ++** ... ++** vmvn q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a) + { +- return vmvnq (a); ++ return vmvnq (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmvn" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmvn q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a) + { +- return vmvnq_u8 (a); ++ return vmvnq_u8 (a); + } + +-/* { dg-final { scan-assembler "vmvn" } } */ + ++/* ++**foo1: ++** ... ++** vmvn q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a) + { +- return vmvnq (a); ++ return vmvnq (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmvn" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (mve_pred16_t p) + { +- return vmvnq_x_n_s16 (2, p); ++ return vmvnq_x_n_s16 (1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt.i16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (mve_pred16_t p) + { +- return vmvnq_x_n_s32 (2, p); ++ return vmvnq_x_n_s32 (1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (mve_pred16_t p) + { +- return vmvnq_x_n_u16 (4, p); ++ return vmvnq_x_n_u16 (1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt.i16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (mve_pred16_t p) + { +- return vmvnq_x_n_u32 (4, p); ++ return vmvnq_x_n_u32 (1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, mve_pred16_t p) + { + return vmvnq_x_s16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, mve_pred16_t p) + { + return vmvnq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, mve_pred16_t p) + { + return vmvnq_x_s32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, mve_pred16_t p) + { + return vmvnq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, mve_pred16_t p) + { + return vmvnq_x_s8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, mve_pred16_t p) + { + return vmvnq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, mve_pred16_t p) + { + return vmvnq_x_u16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, mve_pred16_t p) + { + return vmvnq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, mve_pred16_t p) + { + return vmvnq_x_u32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, mve_pred16_t p) + { + return vmvnq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, mve_pred16_t p) + { + return vmvnq_x_u8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, mve_pred16_t p) + { + return vmvnq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b) + { + return vornq_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ + ++/* ++**foo1: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b) + { + return vornq (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b) + { + return vornq_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ + ++/* ++**foo1: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b) + { + return vornq (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vornq_m_f16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vornq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vornq_m_f32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vornq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vornq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vornq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vornq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vornq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vornq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vornq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vornq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vornq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vornq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vornq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vornq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vornq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vornq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ + ++/* ++**foo1: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vornq (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vornq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ + ++/* ++**foo1: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vornq (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vornq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ + ++/* ++**foo1: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vornq (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { + return vornq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ + ++/* ++**foo1: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vornq (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { + return vornq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ + ++/* ++**foo1: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vornq (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { + return vornq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ + ++/* ++**foo1: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vornq (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vornq_x_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vornq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vornq_x_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vornq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vornq_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vornq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vornq_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vornq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vornq_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vornq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vornq_x_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vornq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vornq_x_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vornq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vornq_x_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vornq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b) + { + return vorrq_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ + ++/* ++**foo1: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b) + { + return vorrq (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b) + { + return vorrq_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ + ++/* ++**foo1: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b) + { + return vorrq (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vorrq_m_f16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vorrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vorrq_m_f32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vorrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, mve_pred16_t p) + { +- return vorrq_m_n_s16 (a, 253, p); ++ return vorrq_m_n_s16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, mve_pred16_t p) + { +- return vorrq_m_n (a, 253, p); ++ return vorrq_m_n (a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, mve_pred16_t p) + { + return vorrq_m_n_s32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, mve_pred16_t p) + { + return vorrq_m_n (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, mve_pred16_t p) + { + return vorrq_m_n_u16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, mve_pred16_t p) + { + return vorrq_m_n (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, mve_pred16_t p) + { + return vorrq_m_n_u32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, mve_pred16_t p) + { + return vorrq_m_n (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vorrq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vorrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vorrq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vorrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vorrq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vorrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vorrq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vorrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vorrq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vorrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vorrq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vorrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s16.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorr.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a) + { + return vorrq_n_s16 (a, 1); + } + +-/* { dg-final { scan-assembler "vorr.i16" } } */ ++ ++/* ++**foo1: ++** ... ++** vorr.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++int16x8_t ++foo1 (int16x8_t a) ++{ ++ return vorrq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s32.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorr.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a) + { + return vorrq_n_s32 (a, 1); + } + +-/* { dg-final { scan-assembler "vorr.i32" } } */ ++ ++/* ++**foo1: ++** ... ++** vorr.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++int32x4_t ++foo1 (int32x4_t a) ++{ ++ return vorrq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u16.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorr.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a) + { + return vorrq_n_u16 (a, 1); + } + +-/* { dg-final { scan-assembler "vorr.i16" } } */ ++ ++/* ++**foo1: ++** ... ++** vorr.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo1 (uint16x8_t a) ++{ ++ return vorrq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u32.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorr.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a) + { +- return vorrq_n_u32 (a, 44); ++ return vorrq_n_u32 (a, 1); ++} ++ ++ ++/* ++**foo1: ++** ... ++** vorr.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo1 (uint32x4_t a) ++{ ++ return vorrq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vorr.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vorrq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ + ++/* ++**foo1: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vorrq (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vorrq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ + ++/* ++**foo1: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vorrq (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vorrq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ + ++/* ++**foo1: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vorrq (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { + return vorrq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ + ++/* ++**foo1: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vorrq (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { + return vorrq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ + ++/* ++**foo1: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vorrq (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { + return vorrq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ + ++/* ++**foo1: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vorrq (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vorrq_x_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vorrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vorrq_x_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vorrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vorrq_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vorrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vorrq_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vorrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vorrq_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vorrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vorrq_x_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vorrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vorrq_x_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vorrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vorrq_x_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vorrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c +@@ -1,21 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpnot(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (mve_pred16_t a) + { + return vpnot (a); + } + +-/* { dg-final { scan-assembler "vpnot" } } */ +- +-mve_pred16_t +-foo1 (mve_pred16_t a) +-{ +- return vpnot (a); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpnot" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f16.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vpselq_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vpselq (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f32.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vpselq_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vpselq (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vpselq_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vpselq (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vpselq_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vpselq (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64x2_t + foo (int64x2_t a, int64x2_t b, mve_pred16_t p) + { + return vpselq_s64 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64x2_t + foo1 (int64x2_t a, int64x2_t b, mve_pred16_t p) + { + return vpselq (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vpselq_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vpselq (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vpselq_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vpselq (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vpselq_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vpselq (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64x2_t + foo (uint64x2_t a, uint64x2_t b, mve_pred16_t p) + { + return vpselq_u64 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64x2_t + foo1 (uint64x2_t a, uint64x2_t b, mve_pred16_t p) + { + return vpselq (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vpselq_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vpselq (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovnbt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqmovnbq_m_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqmovnbt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovnbt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqmovnbq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovnbt.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqmovnbq_m_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqmovnbt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovnbt.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqmovnbq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovnbt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vqmovnbq_m_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqmovnbt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovnbt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vqmovnbq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovnbt.u32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vqmovnbq_m_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqmovnbt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovnbt.u32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vqmovnbq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqmovnb.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b) + { + return vqmovnbq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnb.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqmovnb.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b) + { + return vqmovnbq (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnb.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqmovnb.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b) + { + return vqmovnbq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnb.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqmovnb.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b) + { + return vqmovnbq (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnb.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqmovnb.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b) + { + return vqmovnbq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnb.u16" } } */ + ++/* ++**foo1: ++** ... ++** vqmovnb.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b) + { + return vqmovnbq (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnb.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqmovnb.u32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b) + { + return vqmovnbq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnb.u32" } } */ + ++/* ++**foo1: ++** ... ++** vqmovnb.u32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b) + { + return vqmovnbq (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnb.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovntt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqmovntq_m_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqmovntt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovntt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqmovntq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovntt.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqmovntq_m_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqmovntt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovntt.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqmovntq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovntt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vqmovntq_m_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqmovntt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovntt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vqmovntq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovntt.u32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vqmovntq_m_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqmovntt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovntt.u32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vqmovntq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqmovnt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b) + { + return vqmovntq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqmovnt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b) + { + return vqmovntq (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqmovnt.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b) + { + return vqmovntq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqmovnt.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b) + { + return vqmovntq (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqmovnt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b) + { + return vqmovntq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vqmovnt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b) + { + return vqmovntq (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqmovnt.u32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b) + { + return vqmovntq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vqmovnt.u32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b) + { + return vqmovntq (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovunbt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqmovunbq_m_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqmovunbt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovunbt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqmovunbq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovunbt.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqmovunbq_m_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqmovunbt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovunbt.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqmovunbq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqmovunb.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int16x8_t b) + { + return vqmovunbq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vqmovunb.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqmovunb.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int16x8_t b) + { + return vqmovunbq (a, b); + } + +-/* { dg-final { scan-assembler "vqmovunb.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqmovunb.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32x4_t b) + { + return vqmovunbq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vqmovunb.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqmovunb.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32x4_t b) + { + return vqmovunbq (a, b); + } + +-/* { dg-final { scan-assembler "vqmovunb.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovuntt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqmovuntq_m_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqmovuntt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovuntt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqmovuntq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovuntt.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqmovuntq_m_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqmovuntt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovuntt.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqmovuntq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqmovunt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int16x8_t b) + { + return vqmovuntq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vqmovunt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqmovunt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int16x8_t b) + { + return vqmovuntq (a, b); + } + +-/* { dg-final { scan-assembler "vqmovunt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqmovunt.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32x4_t b) + { + return vqmovuntq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vqmovunt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqmovunt.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32x4_t b) + { + return vqmovuntq (a, b); + } + +-/* { dg-final { scan-assembler "vqmovunt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c +@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c +@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c +@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c +@@ -38,4 +38,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c +@@ -38,4 +38,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c +@@ -38,4 +38,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c +@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c +@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c +@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c +@@ -38,4 +38,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c +@@ -38,4 +38,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c +@@ -38,4 +38,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c +@@ -46,4 +46,4 @@ foo1 (int16x8_t add, int16x8_t m1, int16_t m2, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c +@@ -46,4 +46,4 @@ foo1 (int32x4_t add, int32x4_t m1, int32_t m2, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c +@@ -46,4 +46,4 @@ foo1 (int8x16_t add, int8x16_t m1, int8_t m2, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c +@@ -38,4 +38,4 @@ foo1 (int16x8_t add, int16x8_t m1, int16_t m2) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c +@@ -38,4 +38,4 @@ foo1 (int32x4_t add, int32x4_t m1, int32_t m2) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c +@@ -38,4 +38,4 @@ foo1 (int8x16_t add, int8x16_t m1, int8_t m2) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c +@@ -46,4 +46,4 @@ foo1 (int16x8_t m1, int16x8_t m2, int16_t add, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c +@@ -46,4 +46,4 @@ foo1 (int32x4_t m1, int32x4_t m2, int32_t add, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c +@@ -46,4 +46,4 @@ foo1 (int8x16_t m1, int8x16_t m2, int8_t add, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c +@@ -38,4 +38,4 @@ foo1 (int16x8_t m1, int16x8_t m2, int16_t add) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c +@@ -38,4 +38,4 @@ foo1 (int32x4_t m1, int32x4_t m2, int32_t add) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c +@@ -38,4 +38,4 @@ foo1 (int8x16_t m1, int8x16_t m2, int8_t add) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c +@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c +@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c +@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c +@@ -38,4 +38,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c +@@ -38,4 +38,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c +@@ -38,4 +38,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c +@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c +@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c +@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c +@@ -38,4 +38,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c +@@ -38,4 +38,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c +@@ -38,4 +38,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c +@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c +@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c +@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c +@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c +@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c +@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c +@@ -38,4 +38,4 @@ foo1 (int16x8_t a, int16_t b) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c +@@ -38,4 +38,4 @@ foo1 (int32x4_t a, int32_t b) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c +@@ -38,4 +38,4 @@ foo1 (int8x16_t a, int8_t b) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c +@@ -38,4 +38,4 @@ foo1 (int16x8_t a, int16x8_t b) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c +@@ -38,4 +38,4 @@ foo1 (int32x4_t a, int32x4_t b) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c +@@ -38,4 +38,4 @@ foo1 (int8x16_t a, int8x16_t b) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32_t b, mve_pred16_t p) + { + return vqrshlq_m_n_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32_t b, mve_pred16_t p) + { + return vqrshlq_m_n (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vqrshlq_m_n_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vqrshlq_m_n (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int32_t b, mve_pred16_t p) + { + return vqrshlq_m_n_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int32_t b, mve_pred16_t p) + { + return vqrshlq_m_n (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32_t b, mve_pred16_t p) + { + return vqrshlq_m_n_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32_t b, mve_pred16_t p) + { + return vqrshlq_m_n (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32_t b, mve_pred16_t p) + { + return vqrshlq_m_n_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, int32_t b, mve_pred16_t p) + { + return vqrshlq_m_n (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int32_t b, mve_pred16_t p) + { + return vqrshlq_m_n_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int32_t b, mve_pred16_t p) + { + return vqrshlq_m_n (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqrshlq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqrshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqrshlq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqrshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqrshlq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqrshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqrshlq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqrshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqrshlq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqrshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqrshlq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqrshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshl.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32_t b) + { + return vqrshlq_n_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqrshl.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32_t b) + { + return vqrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshl.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b) + { + return vqrshlq_n_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqrshl.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b) + { + return vqrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshl.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int32_t b) + { + return vqrshlq_n_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqrshl.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int32_t b) + { + return vqrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshl.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32_t b) + { + return vqrshlq_n_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.u16" } } */ + ++/* ++**foo1: ++** ... ++** vqrshl.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32_t b) + { + return vqrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshl.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32_t b) + { + return vqrshlq_n_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.u32" } } */ + ++/* ++**foo1: ++** ... ++** vqrshl.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, int32_t b) + { + return vqrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshl.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int32_t b) + { + return vqrshlq_n_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.u8" } } */ + ++/* ++**foo1: ++** ... ++** vqrshl.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int32_t b) + { + return vqrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshl.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vqrshlq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqrshl.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vqrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshl.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vqrshlq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqrshl.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vqrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshl.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vqrshlq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqrshl.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vqrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshl.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int16x8_t b) + { + return vqrshlq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.u16" } } */ + ++/* ++**foo1: ++** ... ++** vqrshl.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int16x8_t b) + { + return vqrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshl.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32x4_t b) + { + return vqrshlq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.u32" } } */ + ++/* ++**foo1: ++** ... ++** vqrshl.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, int32x4_t b) + { + return vqrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshl.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int8x16_t b) + { + return vqrshlq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.u8" } } */ + ++/* ++**foo1: ++** ... ++** vqrshl.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int8x16_t b) + { + return vqrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrnbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqrshrnbq_m_n_s16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrnbt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrnbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqrshrnbq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrnbt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrnbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqrshrnbq_m_n_s32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrnbt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrnbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqrshrnbq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrnbt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrnbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vqrshrnbq_m_n_u16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrnbt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrnbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vqrshrnbq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrnbt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrnbt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vqrshrnbq_m_n_u32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrnbt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrnbt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vqrshrnbq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrnbt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshrnb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b) + { + return vqrshrnbq_n_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnb.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqrshrnb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b) + { + return vqrshrnbq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnb.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshrnb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b) + { + return vqrshrnbq_n_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnb.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqrshrnb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b) + { + return vqrshrnbq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnb.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshrnb.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b) + { + return vqrshrnbq_n_u16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnb.u16" } } */ + ++/* ++**foo1: ++** ... ++** vqrshrnb.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b) + { + return vqrshrnbq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnb.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshrnb.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b) + { + return vqrshrnbq_n_u32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnb.u32" } } */ + ++/* ++**foo1: ++** ... ++** vqrshrnb.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b) + { + return vqrshrnbq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnb.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqrshrntq_m_n_s16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrntt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqrshrntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrntt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqrshrntq_m_n_s32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrntt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqrshrntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrntt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrntt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vqrshrntq_m_n_u16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrntt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrntt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vqrshrntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrntt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrntt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vqrshrntq_m_n_u32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrntt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrntt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vqrshrntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrntt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshrnt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b) + { + return vqrshrntq_n_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqrshrnt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b) + { + return vqrshrntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshrnt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b) + { + return vqrshrntq_n_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqrshrnt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b) + { + return vqrshrntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshrnt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b) + { + return vqrshrntq_n_u16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vqrshrnt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b) + { + return vqrshrntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshrnt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b) + { + return vqrshrntq_n_u32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vqrshrnt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b) + { + return vqrshrntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrunbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqrshrunbq_m_n_s16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrunbt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrunbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqrshrunbq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrunbt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrunbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqrshrunbq_m_n_s32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrunbt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrunbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqrshrunbq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrunbt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshrunb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int16x8_t b) + { + return vqrshrunbq_n_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrunb.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqrshrunb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int16x8_t b) + { + return vqrshrunbq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrunb.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshrunb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32x4_t b) + { + return vqrshrunbq_n_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrunb.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqrshrunb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32x4_t b) + { + return vqrshrunbq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrunb.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshruntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqrshruntq_m_n_s16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshruntt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshruntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqrshruntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshruntt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshruntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqrshruntq_m_n_s32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshruntt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshruntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqrshruntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshruntt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshrunt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int16x8_t b) + { + return vqrshruntq_n_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrunt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqrshrunt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int16x8_t b) + { + return vqrshruntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrunt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshrunt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32x4_t b) + { + return vqrshruntq_n_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrunt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqrshrunt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32x4_t b) + { + return vqrshruntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrunt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vqshlq_m_n_s16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vqshlq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vqshlq_m_n_s32 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vqshlq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vqshlq_m_n_s8 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vqshlq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vqshlq_m_n_u16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vqshlq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { + return vqshlq_m_n_u32 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { + return vqshlq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vqshlq_m_n_u8 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vqshlq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32_t b, mve_pred16_t p) + { + return vqshlq_m_r_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32_t b, mve_pred16_t p) + { + return vqshlq_m_r (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vqshlq_m_r_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vqshlq_m_r (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int32_t b, mve_pred16_t p) + { + return vqshlq_m_r_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int32_t b, mve_pred16_t p) + { + return vqshlq_m_r (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32_t b, mve_pred16_t p) + { + return vqshlq_m_r_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32_t b, mve_pred16_t p) + { + return vqshlq_m_r (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32_t b, mve_pred16_t p) + { + return vqshlq_m_r_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, int32_t b, mve_pred16_t p) + { + return vqshlq_m_r (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int32_t b, mve_pred16_t p) + { + return vqshlq_m_r_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int32_t b, mve_pred16_t p) + { + return vqshlq_m_r (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqshlq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqshlq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqshlq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqshlq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqshlq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqshlq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a) + { + return vqshlq_n_s16 (a, 1); + } + +-/* { dg-final { scan-assembler "vqshl.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a) + { + return vqshlq_n (a, 1); + } + +-/* { dg-final { scan-assembler "vqshl.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a) + { + return vqshlq_n_s32 (a, 1); + } + +-/* { dg-final { scan-assembler "vqshl.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a) + { + return vqshlq_n (a, 1); + } + +-/* { dg-final { scan-assembler "vqshl.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a) + { + return vqshlq_n_s8 (a, 1); + } + +-/* { dg-final { scan-assembler "vqshl.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a) + { + return vqshlq_n (a, 1); + } + +-/* { dg-final { scan-assembler "vqshl.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a) + { + return vqshlq_n_u16 (a, 1); + } + +-/* { dg-final { scan-assembler "vqshl.u16" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a) + { + return vqshlq_n (a, 1); + } + +-/* { dg-final { scan-assembler "vqshl.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a) + { + return vqshlq_n_u32 (a, 1); + } + +-/* { dg-final { scan-assembler "vqshl.u32" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a) + { + return vqshlq_n (a, 1); + } + +-/* { dg-final { scan-assembler "vqshl.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a) + { + return vqshlq_n_u8 (a, 1); + } + +-/* { dg-final { scan-assembler "vqshl.u8" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a) + { + return vqshlq_n (a, 1); + } + +-/* { dg-final { scan-assembler "vqshl.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32_t b) + { + return vqshlq_r_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32_t b) + { + return vqshlq_r (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b) + { + return vqshlq_r_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b) + { + return vqshlq_r (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int32_t b) + { + return vqshlq_r_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int32_t b) + { + return vqshlq_r (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32_t b) + { + return vqshlq_r_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.u16" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32_t b) + { + return vqshlq_r (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32_t b) + { + return vqshlq_r_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.u32" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, int32_t b) + { + return vqshlq_r (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int32_t b) + { + return vqshlq_r_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.u8" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int32_t b) + { + return vqshlq_r (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vqshlq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vqshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vqshlq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vqshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vqshlq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vqshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int16x8_t b) + { + return vqshlq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.u16" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int16x8_t b) + { + return vqshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32x4_t b) + { + return vqshlq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.u32" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, int32x4_t b) + { + return vqshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int8x16_t b) + { + return vqshlq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.u8" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int8x16_t b) + { + return vqshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlut.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, int16x8_t a, mve_pred16_t p) + { +- return vqshluq_m_n_s16 (inactive, a, 7, p); ++ return vqshluq_m_n_s16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlut.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlut.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, int16x8_t a, mve_pred16_t p) + { +- return vqshluq_m (inactive, a, 7, p); ++ return vqshluq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlut.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, int32x4_t a, mve_pred16_t p) + { +- return vqshluq_m_n_s32 (inactive, a, 7, p); ++ return vqshluq_m_n_s32 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlut.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlut.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, int32x4_t a, mve_pred16_t p) + { +- return vqshluq_m (inactive, a, 7, p); ++ return vqshluq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlut.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, int8x16_t a, mve_pred16_t p) + { +- return vqshluq_m_n_s8 (inactive, a, 7, p); ++ return vqshluq_m_n_s8 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlut.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlut.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, int8x16_t a, mve_pred16_t p) + { +- return vqshluq_m (inactive, a, 7, p); ++ return vqshluq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshlu.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (int16x8_t a) + { +- return vqshluq_n_s16 (a, 7); ++ return vqshluq_n_s16 (a, 1); + } + +-/* { dg-final { scan-assembler "vqshlu.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqshlu.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (int16x8_t a) + { +- return vqshluq (a, 7); ++ return vqshluq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vqshlu.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshlu.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (int32x4_t a) + { +- return vqshluq_n_s32 (a, 7); ++ return vqshluq_n_s32 (a, 1); + } + +-/* { dg-final { scan-assembler "vqshlu.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqshlu.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (int32x4_t a) + { +- return vqshluq (a, 7); ++ return vqshluq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vqshlu.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshlu.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (int8x16_t a) + { +- return vqshluq_n_s8 (a, 7); ++ return vqshluq_n_s8 (a, 1); + } + +-/* { dg-final { scan-assembler "vqshlu.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqshlu.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (int8x16_t a) + { +- return vqshluq (a, 7); ++ return vqshluq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vqshlu.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrnbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b, mve_pred16_t p) + { +- return vqshrnbq_m_n_s16 (a, b, 7, p); ++ return vqshrnbq_m_n_s16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrnbt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrnbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) + { +- return vqshrnbq_m (a, b, 7, p); ++ return vqshrnbq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrnbt.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrnbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b, mve_pred16_t p) + { +- return vqshrnbq_m_n_s32 (a, b, 11, p); ++ return vqshrnbq_m_n_s32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrnbt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrnbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) + { +- return vqshrnbq_m (a, b, 11, p); ++ return vqshrnbq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrnbt.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrnbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vqshrnbq_m_n_u16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrnbt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrnbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vqshrnbq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrnbt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrnbt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vqshrnbq_m_n_u32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrnbt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrnbt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vqshrnbq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrnbt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshrnb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b) + { + return vqshrnbq_n_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrnb.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqshrnb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b) + { + return vqshrnbq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrnb.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshrnb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b) + { +- return vqshrnbq_n_s32 (a, b, 2); ++ return vqshrnbq_n_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrnb.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqshrnb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b) + { +- return vqshrnbq (a, b, 2); ++ return vqshrnbq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vqshrnb.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshrnb.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b) + { + return vqshrnbq_n_u16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrnb.u16" } } */ + ++/* ++**foo1: ++** ... ++** vqshrnb.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b) + { + return vqshrnbq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrnb.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshrnb.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b) + { +- return vqshrnbq_n_u32 (a, b, 15); ++ return vqshrnbq_n_u32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrnb.u32" } } */ + ++/* ++**foo1: ++** ... ++** vqshrnb.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b) + { +- return vqshrnbq (a, b, 15); ++ return vqshrnbq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vqshrnb.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqshrntq_m_n_s16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrntt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqshrntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrntt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqshrntq_m_n_s32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrntt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqshrntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrntt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrntt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vqshrntq_m_n_u16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrntt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrntt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vqshrntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrntt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrntt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vqshrntq_m_n_u32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrntt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrntt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vqshrntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrntt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshrnt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b) + { + return vqshrntq_n_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrnt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqshrnt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b) + { + return vqshrntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrnt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshrnt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b) + { + return vqshrntq_n_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrnt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqshrnt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b) + { + return vqshrntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrnt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshrnt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b) + { + return vqshrntq_n_u16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrnt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vqshrnt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b) + { + return vqshrntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrnt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshrnt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b) + { + return vqshrntq_n_u32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrnt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vqshrnt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b) + { + return vqshrntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrnt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrunbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqshrunbq_m_n_s16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrunbt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrunbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqshrunbq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrunbt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrunbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqshrunbq_m_n_s32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrunbt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrunbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqshrunbq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrunbt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshrunb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int16x8_t b) + { + return vqshrunbq_n_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrunb.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqshrunb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int16x8_t b) + { + return vqshrunbq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrunb.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshrunb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32x4_t b) + { + return vqshrunbq_n_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrunb.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqshrunb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32x4_t b) + { + return vqshrunbq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrunb.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshruntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqshruntq_m_n_s16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshruntt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshruntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqshruntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshruntt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshruntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqshruntq_m_n_s32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshruntt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshruntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqshruntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshruntt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshrunt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int16x8_t b) + { + return vqshruntq_n_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrunt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqshrunt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int16x8_t b) + { + return vqshruntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrunt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshrunt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32x4_t b) + { + return vqshruntq_n_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrunt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqshrunt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32x4_t b) + { + return vqshruntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrunt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c +@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c +@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c +@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c +@@ -62,4 +62,4 @@ foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c +@@ -62,4 +62,4 @@ foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c +@@ -62,4 +62,4 @@ foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c +@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c +@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c +@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c +@@ -46,4 +46,4 @@ foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c +@@ -46,4 +46,4 @@ foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c +@@ -46,4 +46,4 @@ foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c +@@ -38,4 +38,4 @@ foo1 (int16x8_t a, int16_t b) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c +@@ -38,4 +38,4 @@ foo1 (int32x4_t a, int32_t b) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c +@@ -38,4 +38,4 @@ foo1 (int8x16_t a, int8_t b) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c +@@ -50,4 +50,4 @@ foo2 (uint16x8_t a) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c +@@ -50,4 +50,4 @@ foo2 (uint32x4_t a) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c +@@ -50,4 +50,4 @@ foo2 (uint8x16_t a) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c +@@ -38,4 +38,4 @@ foo1 (int16x8_t a, int16x8_t b) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c +@@ -38,4 +38,4 @@ foo1 (int32x4_t a, int32x4_t b) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c +@@ -38,4 +38,4 @@ foo1 (int8x16_t a, int8x16_t b) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c +@@ -38,4 +38,4 @@ foo1 (uint16x8_t a, uint16x8_t b) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c +@@ -38,4 +38,4 @@ foo1 (uint32x4_t a, uint32x4_t b) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c +@@ -38,4 +38,4 @@ foo1 (uint8x16_t a, uint8x16_t b) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vrev16q_m_s8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev16t.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vrev16q_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vrev16q_m_u8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev16t.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vrev16q_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrev16.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a) + { + return vrev16q_s8 (a); + } + +-/* { dg-final { scan-assembler "vrev16.8" } } */ + ++/* ++**foo1: ++** ... ++** vrev16.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a) + { + return vrev16q (a); + } + +-/* { dg-final { scan-assembler "vrev16.8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrev16.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a) + { +- return vrev16q_u8 (a); ++ return vrev16q_u8 (a); + } + +-/* { dg-final { scan-assembler "vrev16.8" } } */ + ++/* ++**foo1: ++** ... ++** vrev16.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a) + { +- return vrev16q (a); ++ return vrev16q (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vrev16.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, mve_pred16_t p) + { + return vrev16q_x_s8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev16t.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, mve_pred16_t p) + { + return vrev16q_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, mve_pred16_t p) + { + return vrev16q_x_u8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev16t.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, mve_pred16_t p) + { + return vrev16q_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrev32.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a) + { + return vrev32q_f16 (a); + } + +-/* { dg-final { scan-assembler "vrev32.16" } } */ ++ ++/* ++**foo1: ++** ... ++** vrev32.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo1 (float16x8_t a) ++{ ++ return vrev32q (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrev32q_m_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev32t.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrev32q_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vrev32q_m_s16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev32t.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vrev32q_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vrev32q_m_s8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev32t.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vrev32q_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vrev32q_m_u16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev32t.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vrev32q_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vrev32q_m_u8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev32t.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vrev32q_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c +@@ -1,21 +1,41 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrev32.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a) + { + return vrev32q_s16 (a); + } + +-/* { dg-final { scan-assembler "vrev32.16" } } */ + ++/* ++**foo1: ++** ... ++** vrev32.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a) + { + return vrev32q (a); + } + +-/* { dg-final { scan-assembler "vrev32.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrev32.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a) + { + return vrev32q_s8 (a); + } + +-/* { dg-final { scan-assembler "vrev32.8" } } */ + ++/* ++**foo1: ++** ... ++** vrev32.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a) + { + return vrev32q (a); + } + +-/* { dg-final { scan-assembler "vrev32.8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrev32.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a) + { +- return vrev32q_u16 (a); ++ return vrev32q_u16 (a); + } + +-/* { dg-final { scan-assembler "vrev32.16" } } */ + ++/* ++**foo1: ++** ... ++** vrev32.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a) + { +- return vrev32q (a); ++ return vrev32q (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vrev32.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrev32.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a) + { +- return vrev32q_u8 (a); ++ return vrev32q_u8 (a); + } + +-/* { dg-final { scan-assembler "vrev32.8" } } */ + ++/* ++**foo1: ++** ... ++** vrev32.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a) + { +- return vrev32q (a); ++ return vrev32q (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vrev32.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vrev32q_x_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev32t.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, mve_pred16_t p) + { + return vrev32q_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, mve_pred16_t p) + { + return vrev32q_x_s16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev32t.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, mve_pred16_t p) + { + return vrev32q_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, mve_pred16_t p) + { + return vrev32q_x_s8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev32t.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, mve_pred16_t p) + { + return vrev32q_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, mve_pred16_t p) + { + return vrev32q_x_u16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev32t.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, mve_pred16_t p) + { + return vrev32q_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, mve_pred16_t p) + { + return vrev32q_x_u8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev32t.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, mve_pred16_t p) + { + return vrev32q_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrev64.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a) + { + return vrev64q_f16 (a); + } + +-/* { dg-final { scan-assembler "vrev64.16" } } */ ++ ++/* ++**foo1: ++** ... ++** vrev64.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo1 (float16x8_t a) ++{ ++ return vrev64q (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrev64.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a) + { + return vrev64q_f32 (a); + } + +-/* { dg-final { scan-assembler "vrev64.32" } } */ ++ ++/* ++**foo1: ++** ... ++** vrev64.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo1 (float32x4_t a) ++{ ++ return vrev64q (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrev64q_m_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrev64q_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vrev64q_m_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vrev64q_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vrev64q_m_s16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vrev64q_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vrev64q_m_s32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vrev64q_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vrev64q_m_s8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vrev64q_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vrev64q_m_u16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vrev64q_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { + return vrev64q_m_u32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { + return vrev64q_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vrev64q_m_u8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vrev64q_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrev64.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a) + { + return vrev64q_s16 (a); + } + +-/* { dg-final { scan-assembler "vrev64.16" } } */ + ++/* ++**foo1: ++** ... ++** vrev64.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a) + { + return vrev64q (a); + } + +-/* { dg-final { scan-assembler "vrev64.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrev64.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a) + { + return vrev64q_s32 (a); + } + +-/* { dg-final { scan-assembler "vrev64.32" } } */ + ++/* ++**foo1: ++** ... ++** vrev64.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a) + { + return vrev64q (a); + } + +-/* { dg-final { scan-assembler "vrev64.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrev64.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a) + { + return vrev64q_s8 (a); + } + +-/* { dg-final { scan-assembler "vrev64.8" } } */ + ++/* ++**foo1: ++** ... ++** vrev64.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a) + { + return vrev64q (a); + } + +-/* { dg-final { scan-assembler "vrev64.8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrev64.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a) + { +- return vrev64q_u16 (a); ++ return vrev64q_u16 (a); + } + +-/* { dg-final { scan-assembler "vrev64.16" } } */ + ++/* ++**foo1: ++** ... ++** vrev64.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a) + { +- return vrev64q (a); ++ return vrev64q (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vrev64.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrev64.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a) + { +- return vrev64q_u32 (a); ++ return vrev64q_u32 (a); + } + +-/* { dg-final { scan-assembler "vrev64.32" } } */ + ++/* ++**foo1: ++** ... ++** vrev64.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a) + { +- return vrev64q (a); ++ return vrev64q (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vrev64.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrev64.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a) + { +- return vrev64q_u8 (a); ++ return vrev64q_u8 (a); + } + +-/* { dg-final { scan-assembler "vrev64.8" } } */ + ++/* ++**foo1: ++** ... ++** vrev64.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a) + { +- return vrev64q (a); ++ return vrev64q (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vrev64.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vrev64q_x_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, mve_pred16_t p) + { + return vrev64q_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vrev64q_x_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, mve_pred16_t p) + { + return vrev64q_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, mve_pred16_t p) + { + return vrev64q_x_s16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, mve_pred16_t p) + { + return vrev64q_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, mve_pred16_t p) + { + return vrev64q_x_s32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, mve_pred16_t p) + { + return vrev64q_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, mve_pred16_t p) + { + return vrev64q_x_s8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, mve_pred16_t p) + { + return vrev64q_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, mve_pred16_t p) + { + return vrev64q_x_u16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, mve_pred16_t p) + { + return vrev64q_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, mve_pred16_t p) + { + return vrev64q_x_u32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, mve_pred16_t p) + { + return vrev64q_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, mve_pred16_t p) + { + return vrev64q_x_u8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, mve_pred16_t p) + { + return vrev64q_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vrhaddq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vrhaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrhaddq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrhaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vrhaddq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vrhaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vrhaddq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vrhaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vrhaddq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vrhaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vrhaddq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vrhaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrhadd.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vrhaddq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vrhadd.s16" } } */ + ++/* ++**foo1: ++** ... ++** vrhadd.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vrhaddq (a, b); + } + +-/* { dg-final { scan-assembler "vrhadd.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrhadd.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vrhaddq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vrhadd.s32" } } */ + ++/* ++**foo1: ++** ... ++** vrhadd.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vrhaddq (a, b); + } + +-/* { dg-final { scan-assembler "vrhadd.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrhadd.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vrhaddq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vrhadd.s8" } } */ + ++/* ++**foo1: ++** ... ++** vrhadd.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vrhaddq (a, b); + } + +-/* { dg-final { scan-assembler "vrhadd.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrhadd.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { + return vrhaddq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vrhadd.u16" } } */ + ++/* ++**foo1: ++** ... ++** vrhadd.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vrhaddq (a, b); + } + +-/* { dg-final { scan-assembler "vrhadd.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrhadd.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { + return vrhaddq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vrhadd.u32" } } */ + ++/* ++**foo1: ++** ... ++** vrhadd.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vrhaddq (a, b); + } + +-/* { dg-final { scan-assembler "vrhadd.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrhadd.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { + return vrhaddq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vrhadd.u8" } } */ + ++/* ++**foo1: ++** ... ++** vrhadd.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vrhaddq (a, b); + } + +-/* { dg-final { scan-assembler "vrhadd.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vrhaddq_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vrhaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrhaddq_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrhaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vrhaddq_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vrhaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vrhaddq_x_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vrhaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vrhaddq_x_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vrhaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vrhaddq_x_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vrhaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c +@@ -46,4 +46,4 @@ foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c +@@ -62,4 +62,4 @@ foo2 (uint32x4_t b, uint32x4_t c, mve_pred16_t p) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c +@@ -38,4 +38,4 @@ foo1 (int64_t a, int32x4_t b, int32x4_t c) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c +@@ -50,4 +50,4 @@ foo2 (uint32x4_t b, uint32x4_t c) + } + #endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlaldavhaxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vrmlaldavhaxq_p_s32 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vrmlaldavhaxt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlaldavhaxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vrmlaldavhaxq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vrmlaldavhaxt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrmlaldavhax.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int32x4_t b, int32x4_t c) + { + return vrmlaldavhaxq_s32 (a, b, c); + } + +-/* { dg-final { scan-assembler "vrmlaldavhax.s32" } } */ + ++/* ++**foo1: ++** ... ++** vrmlaldavhax.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int32x4_t b, int32x4_t c) + { + return vrmlaldavhaxq (a, b, c); + } + +-/* { dg-final { scan-assembler "vrmlaldavhax.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlaldavht.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrmlaldavhq_p_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vrmlaldavht.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlaldavht.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrmlaldavhq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vrmlaldavht.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlaldavht.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vrmlaldavhq_p_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vrmlaldavht.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlaldavht.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vrmlaldavhq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vrmlaldavht.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrmlaldavh.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int32x4_t a, int32x4_t b) + { + return vrmlaldavhq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vrmlaldavh.s32" } } */ + ++/* ++**foo1: ++** ... ++** vrmlaldavh.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int32x4_t a, int32x4_t b) + { + return vrmlaldavhq (a, b); + } + +-/* { dg-final { scan-assembler "vrmlaldavh.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrmlaldavh.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t + foo (uint32x4_t a, uint32x4_t b) + { + return vrmlaldavhq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vrmlaldavh.u32" } } */ + ++/* ++**foo1: ++** ... ++** vrmlaldavh.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vrmlaldavhq (a, b); + } + +-/* { dg-final { scan-assembler "vrmlaldavh.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlaldavhxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrmlaldavhxq_p_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vrmlaldavhxt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlaldavhxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrmlaldavhxq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vrmlaldavhxt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrmlaldavhx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int32x4_t a, int32x4_t b) + { + return vrmlaldavhxq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vrmlaldavhx.s32" } } */ + ++/* ++**foo1: ++** ... ++** vrmlaldavhx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int32x4_t a, int32x4_t b) + { + return vrmlaldavhxq (a, b); + } + +-/* { dg-final { scan-assembler "vrmlaldavhx.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlsldavhat.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vrmlsldavhaq_p_s32 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vrmlsldavhat.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlsldavhat.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vrmlsldavhaq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vrmlsldavhat.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrmlsldavha.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int32x4_t b, int32x4_t c) + { + return vrmlsldavhaq_s32 (a, b, c); + } + +-/* { dg-final { scan-assembler "vrmlsldavha.s32" } } */ + ++/* ++**foo1: ++** ... ++** vrmlsldavha.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int32x4_t b, int32x4_t c) + { + return vrmlsldavhaq (a, b, c); + } + +-/* { dg-final { scan-assembler "vrmlsldavha.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlsldavhaxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vrmlsldavhaxq_p_s32 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vrmlsldavhaxt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlsldavhaxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vrmlsldavhaxq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vrmlsldavhaxt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrmlsldavhax.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int32x4_t b, int32x4_t c) + { + return vrmlsldavhaxq_s32 (a, b, c); + } + +-/* { dg-final { scan-assembler "vrmlsldavhax.s32" } } */ + ++/* ++**foo1: ++** ... ++** vrmlsldavhax.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int32x4_t b, int32x4_t c) + { + return vrmlsldavhaxq (a, b, c); + } + +-/* { dg-final { scan-assembler "vrmlsldavhax.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlsldavht.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrmlsldavhq_p_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vrmlsldavht.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlsldavht.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrmlsldavhq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vrmlsldavht.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrmlsldavh.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int32x4_t a, int32x4_t b) + { + return vrmlsldavhq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vrmlsldavh.s32" } } */ + ++/* ++**foo1: ++** ... ++** vrmlsldavh.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int32x4_t a, int32x4_t b) + { + return vrmlsldavhq (a, b); + } + +-/* { dg-final { scan-assembler "vrmlsldavh.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlsldavhxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrmlsldavhxq_p_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vrmlsldavhxt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlsldavhxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrmlsldavhxq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vrmlsldavhxt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrmlsldavhx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int32x4_t a, int32x4_t b) + { + return vrmlsldavhxq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vrmlsldavhx.s32" } } */ + ++/* ++**foo1: ++** ... ++** vrmlsldavhx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int32x4_t a, int32x4_t b) + { + return vrmlsldavhxq (a, b); + } + +-/* { dg-final { scan-assembler "vrmlsldavhx.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vrmulhq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vrmulhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrmulhq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrmulhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vrmulhq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vrmulhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vrmulhq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vrmulhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vrmulhq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vrmulhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vrmulhq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vrmulhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrmulh.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vrmulhq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vrmulh.s16" } } */ + ++/* ++**foo1: ++** ... ++** vrmulh.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vrmulhq (a, b); + } + +-/* { dg-final { scan-assembler "vrmulh.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrmulh.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vrmulhq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vrmulh.s32" } } */ + ++/* ++**foo1: ++** ... ++** vrmulh.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vrmulhq (a, b); + } + +-/* { dg-final { scan-assembler "vrmulh.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrmulh.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vrmulhq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vrmulh.s8" } } */ + ++/* ++**foo1: ++** ... ++** vrmulh.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vrmulhq (a, b); + } + +-/* { dg-final { scan-assembler "vrmulh.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrmulh.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { + return vrmulhq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vrmulh.u16" } } */ + ++/* ++**foo1: ++** ... ++** vrmulh.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vrmulhq (a, b); + } + +-/* { dg-final { scan-assembler "vrmulh.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrmulh.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { + return vrmulhq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vrmulh.u32" } } */ + ++/* ++**foo1: ++** ... ++** vrmulh.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vrmulhq (a, b); + } + +-/* { dg-final { scan-assembler "vrmulh.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrmulh.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { + return vrmulhq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vrmulh.u8" } } */ + ++/* ++**foo1: ++** ... ++** vrmulh.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vrmulhq (a, b); + } + +-/* { dg-final { scan-assembler "vrmulh.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vrmulhq_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vrmulhq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrmulhq_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrmulhq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vrmulhq_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vrmulhq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vrmulhq_x_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vrmulhq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vrmulhq_x_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vrmulhq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vrmulhq_x_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vrmulhq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrinta.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a) + { + return vrndaq_f16 (a); + } + +-/* { dg-final { scan-assembler "vrinta.f16" } } */ ++ ++/* ++**foo1: ++** ... ++** vrinta.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo1 (float16x8_t a) ++{ ++ return vrndaq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrinta.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a) + { + return vrndaq_f32 (a); + } + +-/* { dg-final { scan-assembler "vrinta.f32" } } */ ++ ++/* ++**foo1: ++** ... ++** vrinta.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo1 (float32x4_t a) ++{ ++ return vrndaq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintat.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrndaq_m_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintat.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintat.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrndaq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintat.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vrndaq_m_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintat.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintat.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vrndaq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintat.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vrndaq_x_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintat.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintat.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, mve_pred16_t p) + { + return vrndaq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintat.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vrndaq_x_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintat.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintat.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, mve_pred16_t p) + { + return vrndaq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrintm.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a) + { + return vrndmq_f16 (a); + } + +-/* { dg-final { scan-assembler "vrintm.f16" } } */ ++ ++/* ++**foo1: ++** ... ++** vrintm.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo1 (float16x8_t a) ++{ ++ return vrndmq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrintm.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a) + { + return vrndmq_f32 (a); + } + +-/* { dg-final { scan-assembler "vrintm.f32" } } */ ++ ++/* ++**foo1: ++** ... ++** vrintm.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo1 (float32x4_t a) ++{ ++ return vrndmq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintmt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrndmq_m_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintmt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintmt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrndmq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintmt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vrndmq_m_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintmt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintmt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vrndmq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintmt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vrndmq_x_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintmt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintmt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, mve_pred16_t p) + { + return vrndmq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintmt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vrndmq_x_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintmt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintmt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, mve_pred16_t p) + { + return vrndmq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrintn.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a) + { + return vrndnq_f16 (a); + } + +-/* { dg-final { scan-assembler "vrintn.f16" } } */ ++ ++/* ++**foo1: ++** ... ++** vrintn.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo1 (float16x8_t a) ++{ ++ return vrndnq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrintn.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a) + { + return vrndnq_f32 (a); + } + +-/* { dg-final { scan-assembler "vrintn.f32" } } */ ++ ++/* ++**foo1: ++** ... ++** vrintn.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo1 (float32x4_t a) ++{ ++ return vrndnq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintnt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrndnq_m_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintnt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintnt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrndnq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintnt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vrndnq_m_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintnt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintnt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vrndnq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintnt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vrndnq_x_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintnt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintnt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, mve_pred16_t p) + { + return vrndnq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintnt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vrndnq_x_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintnt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintnt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, mve_pred16_t p) + { + return vrndnq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrintp.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a) + { + return vrndpq_f16 (a); + } + +-/* { dg-final { scan-assembler "vrintp.f16" } } */ ++ ++/* ++**foo1: ++** ... ++** vrintp.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo1 (float16x8_t a) ++{ ++ return vrndpq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrintp.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a) + { + return vrndpq_f32 (a); + } + +-/* { dg-final { scan-assembler "vrintp.f32" } } */ ++ ++/* ++**foo1: ++** ... ++** vrintp.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo1 (float32x4_t a) ++{ ++ return vrndpq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintpt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrndpq_m_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintpt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintpt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrndpq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintpt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vrndpq_m_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintpt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintpt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vrndpq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintpt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vrndpq_x_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintpt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintpt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, mve_pred16_t p) + { + return vrndpq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintpt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vrndpq_x_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintpt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintpt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, mve_pred16_t p) + { + return vrndpq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrintz.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a) + { + return vrndq_f16 (a); + } + +-/* { dg-final { scan-assembler "vrintz.f16" } } */ ++ ++/* ++**foo1: ++** ... ++** vrintz.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo1 (float16x8_t a) ++{ ++ return vrndq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrintz.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a) + { + return vrndq_f32 (a); + } + +-/* { dg-final { scan-assembler "vrintz.f32" } } */ ++ ++/* ++**foo1: ++** ... ++** vrintz.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo1 (float32x4_t a) ++{ ++ return vrndq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintzt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrndq_m_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintzt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintzt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrndq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintzt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vrndq_m_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintzt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintzt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vrndq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintzt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vrndq_x_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintzt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintzt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, mve_pred16_t p) + { + return vrndq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintzt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vrndq_x_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintzt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintzt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, mve_pred16_t p) + { + return vrndq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrintx.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a) + { + return vrndxq_f16 (a); + } + +-/* { dg-final { scan-assembler "vrintx.f16" } } */ ++ ++/* ++**foo1: ++** ... ++** vrintx.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo1 (float16x8_t a) ++{ ++ return vrndxq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrintx.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a) + { + return vrndxq_f32 (a); + } + +-/* { dg-final { scan-assembler "vrintx.f32" } } */ ++ ++/* ++**foo1: ++** ... ++** vrintx.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo1 (float32x4_t a) ++{ ++ return vrndxq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintxt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrndxq_m_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintxt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintxt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrndxq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintxt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vrndxq_m_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintxt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintxt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vrndxq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintxt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vrndxq_x_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintxt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintxt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, mve_pred16_t p) + { + return vrndxq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintxt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vrndxq_x_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintxt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintxt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, mve_pred16_t p) + { + return vrndxq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vrshrnbq_m_n_s16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrnbt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vrshrnbq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrnbt.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vrshrnbq_m_n_s32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrnbt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vrshrnbq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrnbt.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vrshrnbq_m_n_u16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrnbt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vrshrnbq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrnbt.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vrshrnbq_m_n_u32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrnbt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vrshrnbq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrnbt.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b) + { + return vrshrnbq_n_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnb.i16" } } */ + ++/* ++**foo1: ++** ... ++** vrshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b) + { + return vrshrnbq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnb.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b) + { + return vrshrnbq_n_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnb.i32" } } */ + ++/* ++**foo1: ++** ... ++** vrshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b) + { + return vrshrnbq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnb.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b) + { + return vrshrnbq_n_u16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnb.i16" } } */ + ++/* ++**foo1: ++** ... ++** vrshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b) + { + return vrshrnbq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnb.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b) + { + return vrshrnbq_n_u32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnb.i32" } } */ + ++/* ++**foo1: ++** ... ++** vrshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b) + { + return vrshrnbq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnb.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vrshrntq_m_n_s16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrntt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vrshrntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrntt.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vrshrntq_m_n_s32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrntt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vrshrntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrntt.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vrshrntq_m_n_u16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrntt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vrshrntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrntt.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vrshrntq_m_n_u32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrntt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vrshrntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrntt.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b) + { + return vrshrntq_n_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vrshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b) + { + return vrshrntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnt.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b) + { + return vrshrntq_n_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vrshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b) + { + return vrshrntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnt.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b) + { + return vrshrntq_n_u16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vrshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b) + { + return vrshrntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnt.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b) + { + return vrshrntq_n_u32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vrshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b) + { + return vrshrntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnt.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { +- return vrshrq_m_n_s16 (inactive, a, 16, p); ++ return vrshrq_m_n_s16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { +- return vrshrq_m (inactive, a, 16, p); ++ return vrshrq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { +- return vrshrq_m_n_s32 (inactive, a, 32, p); ++ return vrshrq_m_n_s32 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { +- return vrshrq_m (inactive, a, 32, p); ++ return vrshrq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { +- return vrshrq_m_n_s8 (inactive, a, 8, p); ++ return vrshrq_m_n_s8 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { +- return vrshrq_m (inactive, a, 8, p); ++ return vrshrq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { +- return vrshrq_m_n_u16 (inactive, a, 16, p); ++ return vrshrq_m_n_u16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { +- return vrshrq_m (inactive, a, 16, p); ++ return vrshrq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { +- return vrshrq_m_n_u32 (inactive, a, 32, p); ++ return vrshrq_m_n_u32 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { +- return vrshrq_m (inactive, a, 32, p); ++ return vrshrq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { +- return vrshrq_m_n_u8 (inactive, a, 8, p); ++ return vrshrq_m_n_u8 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { +- return vrshrq_m (inactive, a, 8, p); ++ return vrshrq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshr.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a) + { +- return vrshrq_n_s16 (a, 16); ++ return vrshrq_n_s16 (a, 1); + } + +-/* { dg-final { scan-assembler "vrshr.s16" } } */ + ++/* ++**foo1: ++** ... ++** vrshr.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a) + { +- return vrshrq (a, 16); ++ return vrshrq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vrshr.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshr.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a) + { +- return vrshrq_n_s32 (a, 32); ++ return vrshrq_n_s32 (a, 1); + } + +-/* { dg-final { scan-assembler "vrshr.s32" } } */ + ++/* ++**foo1: ++** ... ++** vrshr.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a) + { +- return vrshrq (a, 32); ++ return vrshrq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vrshr.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshr.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a) + { +- return vrshrq_n_s8 (a, 8); ++ return vrshrq_n_s8 (a, 1); + } + +-/* { dg-final { scan-assembler "vrshr.s8" } } */ + ++/* ++**foo1: ++** ... ++** vrshr.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a) + { +- return vrshrq (a, 8); ++ return vrshrq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vrshr.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshr.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a) + { +- return vrshrq_n_u16 (a, 16); ++ return vrshrq_n_u16 (a, 1); + } + +-/* { dg-final { scan-assembler "vrshr.u16" } } */ + ++/* ++**foo1: ++** ... ++** vrshr.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a) + { +- return vrshrq (a, 16); ++ return vrshrq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vrshr.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshr.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a) + { +- return vrshrq_n_u32 (a, 32); ++ return vrshrq_n_u32 (a, 1); + } + +-/* { dg-final { scan-assembler "vrshr.u32" } } */ + ++/* ++**foo1: ++** ... ++** vrshr.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a) + { +- return vrshrq (a, 32); ++ return vrshrq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vrshr.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshr.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a) + { +- return vrshrq_n_u8 (a, 8); ++ return vrshrq_n_u8 (a, 1); + } + +-/* { dg-final { scan-assembler "vrshr.u8" } } */ + ++/* ++**foo1: ++** ... ++** vrshr.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a) + { +- return vrshrq (a, 8); ++ return vrshrq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vrshr.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, mve_pred16_t p) + { +- return vrshrq_x_n_s16 (a, 16, p); ++ return vrshrq_x_n_s16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, mve_pred16_t p) + { +- return vrshrq_x (a, 16, p); ++ return vrshrq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, mve_pred16_t p) + { +- return vrshrq_x_n_s32 (a, 32, p); ++ return vrshrq_x_n_s32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, mve_pred16_t p) + { +- return vrshrq_x (a, 32, p); ++ return vrshrq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, mve_pred16_t p) + { +- return vrshrq_x_n_s8 (a, 8, p); ++ return vrshrq_x_n_s8 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, mve_pred16_t p) + { +- return vrshrq_x (a, 8, p); ++ return vrshrq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, mve_pred16_t p) + { +- return vrshrq_x_n_u16 (a, 16, p); ++ return vrshrq_x_n_u16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, mve_pred16_t p) + { +- return vrshrq_x (a, 16, p); ++ return vrshrq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, mve_pred16_t p) + { +- return vrshrq_x_n_u32 (a, 32, p); ++ return vrshrq_x_n_u32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, mve_pred16_t p) + { +- return vrshrq_x (a, 32, p); ++ return vrshrq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, mve_pred16_t p) + { +- return vrshrq_x_n_u8 (a, 8, p); ++ return vrshrq_x_n_u8 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, mve_pred16_t p) + { +- return vrshrq_x (a, 8, p); ++ return vrshrq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c +@@ -1,23 +1,57 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsbcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry_out, mve_pred16_t p) ++foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred16_t p) + { + return vsbciq_m_s32 (inactive, a, b, carry_out, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsbcit.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsbcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry_out, mve_pred16_t p) ++foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred16_t p) + { + return vsbciq_m (inactive, a, b, carry_out, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsbcit.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c +@@ -1,23 +1,57 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsbcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry_out, mve_pred16_t p) ++foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_pred16_t p) + { + return vsbciq_m_u32 (inactive, a, b, carry_out, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsbcit.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsbcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry_out, mve_pred16_t p) ++foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_pred16_t p) + { + return vsbciq_m (inactive, a, b, carry_out, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsbcit.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsbci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t a, int32x4_t b, unsigned * carry_out) ++foo (int32x4_t a, int32x4_t b, unsigned *carry_out) + { + return vsbciq_s32 (a, b, carry_out); + } + +-/* { dg-final { scan-assembler "vsbci.i32" } } */ + ++/* ++**foo1: ++** ... ++** vsbci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t a, int32x4_t b, unsigned * carry_out) ++foo1 (int32x4_t a, int32x4_t b, unsigned *carry_out) + { +- return vsbciq_s32 (a, b, carry_out); ++ return vsbciq (a, b, carry_out); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vsbci.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsbci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t a, uint32x4_t b, unsigned * carry_out) ++foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out) + { + return vsbciq_u32 (a, b, carry_out); + } + +-/* { dg-final { scan-assembler "vsbci.i32" } } */ + ++/* ++**foo1: ++** ... ++** vsbci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32x4_t a, uint32x4_t b, unsigned * carry_out) ++foo1 (uint32x4_t a, uint32x4_t b, unsigned *carry_out) + { +- return vsbciq_u32 (a, b, carry_out); ++ return vsbciq (a, b, carry_out); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vsbci.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c +@@ -1,23 +1,69 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsbct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry, mve_pred16_t p) ++foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t p) + { +- return vsbcq_m_s32 (inactive, a, b, carry, p); ++ return vsbcq_m_s32 (inactive, a, b, carry, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsbct.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsbct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1(int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry, mve_pred16_t p) ++foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t p) + { +- return vsbcq_m (inactive, a, b, carry, p); ++ return vsbcq_m (inactive, a, b, carry, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsbct.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c +@@ -1,22 +1,69 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsbct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry, mve_pred16_t p) ++foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred16_t p) + { +- return vsbcq_m_u32 (inactive, a, b, carry, p); ++ return vsbcq_m_u32 (inactive, a, b, carry, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsbct.i32" } } */ ++ ++/* ++**foo1: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsbct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry, mve_pred16_t p) ++foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred16_t p) + { +- return vsbcq_m (inactive, a, b, carry, p); ++ return vsbcq_m (inactive, a, b, carry, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsbct.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c +@@ -1,21 +1,61 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vsbc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t a, int32x4_t b, unsigned * carry) ++foo (int32x4_t a, int32x4_t b, unsigned *carry) + { + return vsbcq_s32 (a, b, carry); + } + +-/* { dg-final { scan-assembler "vsbc.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vsbc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t a, int32x4_t b, unsigned * carry) ++foo1 (int32x4_t a, int32x4_t b, unsigned *carry) + { + return vsbcq (a, b, carry); + } + +-/* { dg-final { scan-assembler "vsbc.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c +@@ -1,21 +1,61 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vsbc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t a, uint32x4_t b, unsigned * carry) ++foo (uint32x4_t a, uint32x4_t b, unsigned *carry) + { + return vsbcq_u32 (a, b, carry); + } + +-/* { dg-final { scan-assembler "vsbc.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vsbc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32x4_t a, uint32x4_t b, unsigned * carry) ++foo1 (uint32x4_t a, uint32x4_t b, unsigned *carry) + { + return vsbcq (a, b, carry); + } + +-/* { dg-final { scan-assembler "vsbc.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16-1.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo (float16_t a, float16x8_t b) +-{ +- return vsetq_lane (23.26, b, 0); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32-1.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo (float32_t a, float32x4_t b) +-{ +- return vsetq_lane (23.34, b, 0); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16x8_t a, uint32_t * b, mve_pred16_t p) ++foo (int16x8_t a, uint32_t *b, mve_pred16_t p) + { +- return vshlcq_m_s16 (a, b, 32, p); ++ return vshlcq_m_s16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlct" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int16x8_t a, uint32_t * b, mve_pred16_t p) ++foo1 (int16x8_t a, uint32_t *b, mve_pred16_t p) + { +- return vshlcq_m (a, b, 32, p); ++ return vshlcq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlct" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t a, uint32_t * b, mve_pred16_t p) ++foo (int32x4_t a, uint32_t *b, mve_pred16_t p) + { + return vshlcq_m_s32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlct" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t a, uint32_t * b, mve_pred16_t p) ++foo1 (int32x4_t a, uint32_t *b, mve_pred16_t p) + { + return vshlcq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlct" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t +-foo (int8x16_t a, uint32_t * b, mve_pred16_t p) ++foo (int8x16_t a, uint32_t *b, mve_pred16_t p) + { + return vshlcq_m_s8 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlct" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t +-foo1 (int8x16_t a, uint32_t * b, mve_pred16_t p) ++foo1 (int8x16_t a, uint32_t *b, mve_pred16_t p) + { + return vshlcq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlct" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint16x8_t a, uint32_t * b, mve_pred16_t p) ++foo (uint16x8_t a, uint32_t *b, mve_pred16_t p) + { + return vshlcq_m_u16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlct" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (uint16x8_t a, uint32_t * b, mve_pred16_t p) ++foo1 (uint16x8_t a, uint32_t *b, mve_pred16_t p) + { + return vshlcq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlct" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t a, uint32_t * b, mve_pred16_t p) ++foo (uint32x4_t a, uint32_t *b, mve_pred16_t p) + { + return vshlcq_m_u32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlct" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32x4_t a, uint32_t * b, mve_pred16_t p) ++foo1 (uint32x4_t a, uint32_t *b, mve_pred16_t p) + { + return vshlcq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlct" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo (uint8x16_t a, uint32_t * b, mve_pred16_t p) ++foo (uint8x16_t a, uint32_t *b, mve_pred16_t p) + { + return vshlcq_m_u8 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlct" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo1 (uint8x16_t a, uint32_t * b, mve_pred16_t p) ++foo1 (uint8x16_t a, uint32_t *b, mve_pred16_t p) + { + return vshlcq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlct" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16x8_t a, uint32_t * b) ++foo (int16x8_t a, uint32_t *b) + { + return vshlcq_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshlc" } } */ + ++/* ++**foo1: ++** ... ++** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int16x8_t a, uint32_t * b) ++foo1 (int16x8_t a, uint32_t *b) + { + return vshlcq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshlc" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t a, uint32_t * b) ++foo (int32x4_t a, uint32_t *b) + { + return vshlcq_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshlc" } } */ + ++/* ++**foo1: ++** ... ++** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t a, uint32_t * b) ++foo1 (int32x4_t a, uint32_t *b) + { + return vshlcq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshlc" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t +-foo (int8x16_t a, uint32_t * b) ++foo (int8x16_t a, uint32_t *b) + { + return vshlcq_s8 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshlc" } } */ + ++/* ++**foo1: ++** ... ++** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t +-foo1 (int8x16_t a, uint32_t * b) ++foo1 (int8x16_t a, uint32_t *b) + { + return vshlcq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshlc" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint16x8_t a, uint32_t * b) ++foo (uint16x8_t a, uint32_t *b) + { + return vshlcq_u16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshlc" } } */ + ++/* ++**foo1: ++** ... ++** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (uint16x8_t a, uint32_t * b) ++foo1 (uint16x8_t a, uint32_t *b) + { + return vshlcq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshlc" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t a, uint32_t * b) ++foo (uint32x4_t a, uint32_t *b) + { + return vshlcq_u32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshlc" } } */ + ++/* ++**foo1: ++** ... ++** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32x4_t a, uint32_t * b) ++foo1 (uint32x4_t a, uint32_t *b) + { + return vshlcq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshlc" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo (uint8x16_t a, uint32_t * b) ++foo (uint8x16_t a, uint32_t *b) + { + return vshlcq_u8 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshlc" } } */ + ++/* ++**foo1: ++** ... ++** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo1 (uint8x16_t a, uint32_t * b) ++foo1 (uint8x16_t a, uint32_t *b) + { + return vshlcq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshlc" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int16x8_t a, mve_pred16_t p) + { + return vshllbq_m_n_s16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshllbt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int16x8_t a, mve_pred16_t p) + { + return vshllbq_m (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshllbt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int8x16_t a, mve_pred16_t p) + { + return vshllbq_m_n_s8 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshllbt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int8x16_t a, mve_pred16_t p) + { + return vshllbq_m (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshllbt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vshllbq_m_n_u16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshllbt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vshllbq_m (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshllbt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vshllbq_m_n_u8 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshllbt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vshllbq_m (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshllbt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshllb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int16x8_t a) + { + return vshllbq_n_s16 (a, 1); + } + +-/* { dg-final { scan-assembler "vshllb.s16" } } */ + ++/* ++**foo1: ++** ... ++** vshllb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int16x8_t a) + { + return vshllbq (a, 1); + } + +-/* { dg-final { scan-assembler "vshllb.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshllb.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int8x16_t a) + { + return vshllbq_n_s8 (a, 1); + } + +-/* { dg-final { scan-assembler "vshllb.s8" } } */ + ++/* ++**foo1: ++** ... ++** vshllb.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int8x16_t a) + { + return vshllbq (a, 1); + } + +-/* { dg-final { scan-assembler "vshllb.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshllb.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint16x8_t a) + { + return vshllbq_n_u16 (a, 1); + } + +-/* { dg-final { scan-assembler "vshllb.u16" } } */ + ++/* ++**foo1: ++** ... ++** vshllb.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint16x8_t a) + { + return vshllbq (a, 1); + } + +-/* { dg-final { scan-assembler "vshllb.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshllb.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint8x16_t a) + { + return vshllbq_n_u8 (a, 1); + } + +-/* { dg-final { scan-assembler "vshllb.u8" } } */ + ++/* ++**foo1: ++** ... ++** vshllb.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint8x16_t a) + { + return vshllbq (a, 1); + } + +-/* { dg-final { scan-assembler "vshllb.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int16x8_t a, mve_pred16_t p) + { +- return vshllbq_x_n_s16 (a, 1, p); ++ return vshllbq_x_n_s16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshllbt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++int32x4_t ++foo1 (int16x8_t a, mve_pred16_t p) ++{ ++ return vshllbq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int8x16_t a, mve_pred16_t p) + { +- return vshllbq_x_n_s8 (a, 1, p); ++ return vshllbq_x_n_s8 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshllbt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++int16x8_t ++foo1 (int8x16_t a, mve_pred16_t p) ++{ ++ return vshllbq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint16x8_t a, mve_pred16_t p) + { +- return vshllbq_x_n_u16 (a, 1, p); ++ return vshllbq_x_n_u16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshllbt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo1 (uint16x8_t a, mve_pred16_t p) ++{ ++ return vshllbq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint8x16_t a, mve_pred16_t p) + { +- return vshllbq_x_n_u8 (a, 1, p); ++ return vshllbq_x_n_u8 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshllbt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo1 (uint8x16_t a, mve_pred16_t p) ++{ ++ return vshllbq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int16x8_t a, mve_pred16_t p) + { + return vshlltq_m_n_s16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlltt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int16x8_t a, mve_pred16_t p) + { + return vshlltq_m (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlltt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int8x16_t a, mve_pred16_t p) + { + return vshlltq_m_n_s8 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlltt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int8x16_t a, mve_pred16_t p) + { + return vshlltq_m (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlltt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vshlltq_m_n_u16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlltt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vshlltq_m (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlltt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vshlltq_m_n_u8 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlltt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vshlltq_m (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlltt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshllt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int16x8_t a) + { + return vshlltq_n_s16 (a, 1); + } + +-/* { dg-final { scan-assembler "vshllt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vshllt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int16x8_t a) + { + return vshlltq (a, 1); + } + +-/* { dg-final { scan-assembler "vshllt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshllt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int8x16_t a) + { + return vshlltq_n_s8 (a, 1); + } + +-/* { dg-final { scan-assembler "vshllt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vshllt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int8x16_t a) + { + return vshlltq (a, 1); + } + +-/* { dg-final { scan-assembler "vshllt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshllt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint16x8_t a) + { + return vshlltq_n_u16 (a, 1); + } + +-/* { dg-final { scan-assembler "vshllt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vshllt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint16x8_t a) + { + return vshlltq (a, 1); + } + +-/* { dg-final { scan-assembler "vshllt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshllt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint8x16_t a) + { + return vshlltq_n_u8 (a, 1); + } + +-/* { dg-final { scan-assembler "vshllt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vshllt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint8x16_t a) + { + return vshlltq (a, 1); + } + +-/* { dg-final { scan-assembler "vshllt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int16x8_t a, mve_pred16_t p) + { +- return vshlltq_x_n_s16 (a, 1, p); ++ return vshlltq_x_n_s16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlltt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++int32x4_t ++foo1 (int16x8_t a, mve_pred16_t p) ++{ ++ return vshlltq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int8x16_t a, mve_pred16_t p) + { +- return vshlltq_x_n_s8 (a, 1, p); ++ return vshlltq_x_n_s8 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlltt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++int16x8_t ++foo1 (int8x16_t a, mve_pred16_t p) ++{ ++ return vshlltq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint16x8_t a, mve_pred16_t p) + { +- return vshlltq_x_n_u16 (a, 1, p); ++ return vshlltq_x_n_u16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlltt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo1 (uint16x8_t a, mve_pred16_t p) ++{ ++ return vshlltq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint8x16_t a, mve_pred16_t p) + { +- return vshlltq_x_n_u8 (a, 1, p); ++ return vshlltq_x_n_u8 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlltt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo1 (uint8x16_t a, mve_pred16_t p) ++{ ++ return vshlltq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vshlq_m_n_s16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vshlq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vshlq_m_n_s32 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vshlq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vshlq_m_n_s8 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vshlq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vshlq_m_n_u16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vshlq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { + return vshlq_m_n_u32 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { + return vshlq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vshlq_m_n_u8 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vshlq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32_t b, mve_pred16_t p) + { + return vshlq_m_r_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32_t b, mve_pred16_t p) + { + return vshlq_m_r (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vshlq_m_r_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vshlq_m_r (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int32_t b, mve_pred16_t p) + { + return vshlq_m_r_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int32_t b, mve_pred16_t p) + { + return vshlq_m_r (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32_t b, mve_pred16_t p) + { + return vshlq_m_r_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32_t b, mve_pred16_t p) + { + return vshlq_m_r (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32_t b, mve_pred16_t p) + { + return vshlq_m_r_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, int32_t b, mve_pred16_t p) + { + return vshlq_m_r (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int32_t b, mve_pred16_t p) + { + return vshlq_m_r_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int32_t b, mve_pred16_t p) + { + return vshlq_m_r (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vshlq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vshlq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vshlq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vshlq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vshlq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vshlq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a) + { + return vshlq_n_s16 (a, 1); + } + +-/* { dg-final { scan-assembler "vshl.s16" } } */ + ++/* ++**foo1: ++** ... ++** vshl.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a) + { + return vshlq_n (a, 1); + } + +-/* { dg-final { scan-assembler "vshl.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a) + { +- return vshlq_n_s32 (a, 16); ++ return vshlq_n_s32 (a, 1); + } + +-/* { dg-final { scan-assembler "vshl.s32" } } */ + ++/* ++**foo1: ++** ... ++** vshl.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a) + { +- return vshlq_n (a, 16); ++ return vshlq_n (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshl.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a) + { + return vshlq_n_s8 (a, 1); + } + +-/* { dg-final { scan-assembler "vshl.s8" } } */ + ++/* ++**foo1: ++** ... ++** vshl.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a) + { + return vshlq_n (a, 1); + } + +-/* { dg-final { scan-assembler "vshl.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a) + { +- return vshlq_n_u16 (a, 11); ++ return vshlq_n_u16 (a, 1); + } + +-/* { dg-final { scan-assembler "vshl.u16" } } */ + ++/* ++**foo1: ++** ... ++** vshl.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a) + { +- return vshlq_n (a, 11); ++ return vshlq_n (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshl.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a) + { + return vshlq_n_u32 (a, 1); + } + +-/* { dg-final { scan-assembler "vshl.u32" } } */ + ++/* ++**foo1: ++** ... ++** vshl.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a) + { + return vshlq_n (a, 1); + } + +-/* { dg-final { scan-assembler "vshl.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a) + { + return vshlq_n_u8 (a, 1); + } + +-/* { dg-final { scan-assembler "vshl.u8" } } */ + ++/* ++**foo1: ++** ... ++** vshl.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a) + { + return vshlq_n (a, 1); + } + +-/* { dg-final { scan-assembler "vshl.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32_t b) + { + return vshlq_r_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vshl.s16" } } */ + ++/* ++**foo1: ++** ... ++** vshl.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32_t b) + { + return vshlq_r (a, b); + } + +-/* { dg-final { scan-assembler "vshl.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b) + { + return vshlq_r_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vshl.s32" } } */ + ++/* ++**foo1: ++** ... ++** vshl.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b) + { + return vshlq_r (a, b); + } + +-/* { dg-final { scan-assembler "vshl.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int32_t b) + { + return vshlq_r_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vshl.s8" } } */ + ++/* ++**foo1: ++** ... ++** vshl.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int32_t b) + { + return vshlq_r (a, b); + } + +-/* { dg-final { scan-assembler "vshl.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32_t b) + { + return vshlq_r_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vshl.u16" } } */ + ++/* ++**foo1: ++** ... ++** vshl.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32_t b) + { + return vshlq_r (a, b); + } + +-/* { dg-final { scan-assembler "vshl.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32_t b) + { + return vshlq_r_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vshl.u32" } } */ + ++/* ++**foo1: ++** ... ++** vshl.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, int32_t b) + { + return vshlq_r (a, b); + } + +-/* { dg-final { scan-assembler "vshl.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int32_t b) + { + return vshlq_r_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vshl.u8" } } */ + ++/* ++**foo1: ++** ... ++** vshl.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int32_t b) + { + return vshlq_r (a, b); + } + +-/* { dg-final { scan-assembler "vshl.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vshlq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vshl.s16" } } */ + ++/* ++**foo1: ++** ... ++** vshl.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vshlq (a, b); + } + +-/* { dg-final { scan-assembler "vshl.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vshlq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vshl.s32" } } */ + ++/* ++**foo1: ++** ... ++** vshl.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vshlq (a, b); + } + +-/* { dg-final { scan-assembler "vshl.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vshlq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vshl.s8" } } */ + ++/* ++**foo1: ++** ... ++** vshl.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vshlq (a, b); + } + +-/* { dg-final { scan-assembler "vshl.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int16x8_t b) + { + return vshlq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vshl.u16" } } */ + ++/* ++**foo1: ++** ... ++** vshl.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int16x8_t b) + { + return vshlq (a, b); + } + +-/* { dg-final { scan-assembler "vshl.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32x4_t b) + { + return vshlq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vshl.u32" } } */ + ++/* ++**foo1: ++** ... ++** vshl.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, int32x4_t b) + { + return vshlq (a, b); + } + +-/* { dg-final { scan-assembler "vshl.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int8x16_t b) + { + return vshlq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vshl.u8" } } */ + ++/* ++**foo1: ++** ... ++** vshl.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int8x16_t b) + { + return vshlq (a, b); + } + +-/* { dg-final { scan-assembler "vshl.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, mve_pred16_t p) + { +- return vshlq_x_n_s16 (a, 1, p); ++ return vshlq_x_n_s16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++int16x8_t ++foo1 (int16x8_t a, mve_pred16_t p) ++{ ++ return vshlq_x_n (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, mve_pred16_t p) + { +- return vshlq_x_n_s32 (a, 1, p); ++ return vshlq_x_n_s32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++int32x4_t ++foo1 (int32x4_t a, mve_pred16_t p) ++{ ++ return vshlq_x_n (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, mve_pred16_t p) + { +- return vshlq_x_n_s8 (a, 1, p); ++ return vshlq_x_n_s8 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++int8x16_t ++foo1 (int8x16_t a, mve_pred16_t p) ++{ ++ return vshlq_x_n (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, mve_pred16_t p) + { +- return vshlq_x_n_u16 (a, 1, p); ++ return vshlq_x_n_u16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo1 (uint16x8_t a, mve_pred16_t p) ++{ ++ return vshlq_x_n (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, mve_pred16_t p) + { +- return vshlq_x_n_u32 (a, 1, p); ++ return vshlq_x_n_u32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo1 (uint32x4_t a, mve_pred16_t p) ++{ ++ return vshlq_x_n (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, mve_pred16_t p) + { +- return vshlq_x_n_u8 (a, 1, p); ++ return vshlq_x_n_u8 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo1 (uint8x16_t a, mve_pred16_t p) ++{ ++ return vshlq_x_n (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { +- return vshlq_x_s16 (a, b, p); ++ return vshlq_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++int16x8_t ++foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) ++{ ++ return vshlq_x (a, b, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { +- return vshlq_x_s32 (a, b, p); ++ return vshlq_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++int32x4_t ++foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) ++{ ++ return vshlq_x (a, b, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { +- return vshlq_x_s8 (a, b, p); ++ return vshlq_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++int8x16_t ++foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) ++{ ++ return vshlq_x (a, b, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int16x8_t b, mve_pred16_t p) + { +- return vshlq_x_u16 (a, b, p); ++ return vshlq_x_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo1 (uint16x8_t a, int16x8_t b, mve_pred16_t p) ++{ ++ return vshlq_x (a, b, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32x4_t b, mve_pred16_t p) + { +- return vshlq_x_u32 (a, b, p); ++ return vshlq_x_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo1 (uint32x4_t a, int32x4_t b, mve_pred16_t p) ++{ ++ return vshlq_x (a, b, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int8x16_t b, mve_pred16_t p) + { +- return vshlq_x_u8 (a, b, p); ++ return vshlq_x_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo1 (uint8x16_t a, int8x16_t b, mve_pred16_t p) ++{ ++ return vshlq_x (a, b, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b, mve_pred16_t p) + { +- return vshrnbq_m_n_s16 (a, b, 8, p); ++ return vshrnbq_m_n_s16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrnbt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) + { +- return vshrnbq_m (a, b, 8, p); ++ return vshrnbq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrnbt.i16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b, mve_pred16_t p) + { +- return vshrnbq_m_n_s32 (a, b, 16, p); ++ return vshrnbq_m_n_s32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrnbt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) + { +- return vshrnbq_m (a, b, 16, p); ++ return vshrnbq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrnbt.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { +- return vshrnbq_m_n_u16 (a, b, 8, p); ++ return vshrnbq_m_n_u16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrnbt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { +- return vshrnbq_m (a, b, 8, p); ++ return vshrnbq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrnbt.i16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { +- return vshrnbq_m_n_u32 (a, b, 16, p); ++ return vshrnbq_m_n_u32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrnbt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { +- return vshrnbq_m (a, b, 16, p); ++ return vshrnbq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrnbt.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b) + { +- return vshrnbq_n_s16 (a, b, 8); ++ return vshrnbq_n_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshrnb.i16" } } */ + ++/* ++**foo1: ++** ... ++** vshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b) + { +- return vshrnbq (a, b, 8); ++ return vshrnbq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshrnb.i16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b) + { +- return vshrnbq_n_s32 (a, b, 16); ++ return vshrnbq_n_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshrnb.i32" } } */ + ++/* ++**foo1: ++** ... ++** vshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b) + { +- return vshrnbq (a, b, 16); ++ return vshrnbq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshrnb.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b) + { +- return vshrnbq_n_u16 (a, b, 8); ++ return vshrnbq_n_u16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshrnb.i16" } } */ + ++/* ++**foo1: ++** ... ++** vshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b) + { +- return vshrnbq (a, b, 8); ++ return vshrnbq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshrnb.i16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b) + { +- return vshrnbq_n_u32 (a, b, 16); ++ return vshrnbq_n_u32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshrnb.i32" } } */ + ++/* ++**foo1: ++** ... ++** vshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b) + { +- return vshrnbq (a, b, 16); ++ return vshrnbq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshrnb.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b, mve_pred16_t p) + { +- return vshrntq_m_n_s16 (a, b, 8, p); ++ return vshrntq_m_n_s16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrntt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) + { +- return vshrntq_m (a, b, 8, p); ++ return vshrntq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrntt.i16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b, mve_pred16_t p) + { +- return vshrntq_m_n_s32 (a, b, 16, p); ++ return vshrntq_m_n_s32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrntt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) + { +- return vshrntq_m (a, b, 16, p); ++ return vshrntq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrntt.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { +- return vshrntq_m_n_u16 (a, b, 8, p); ++ return vshrntq_m_n_u16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrntt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { +- return vshrntq_m (a, b, 8, p); ++ return vshrntq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrntt.i16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { +- return vshrntq_m_n_u32 (a, b, 16, p); ++ return vshrntq_m_n_u32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrntt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { +- return vshrntq_m (a, b, 16, p); ++ return vshrntq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrntt.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b) + { +- return vshrntq_n_s16 (a, b, 8); ++ return vshrntq_n_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshrnt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b) + { +- return vshrntq (a, b, 8); ++ return vshrntq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshrnt.i16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b) + { +- return vshrntq_n_s32 (a, b, 16); ++ return vshrntq_n_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshrnt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b) + { +- return vshrntq (a, b, 16); ++ return vshrntq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshrnt.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b) + { +- return vshrntq_n_u16 (a, b, 8); ++ return vshrntq_n_u16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshrnt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b) + { +- return vshrntq (a, b, 8); ++ return vshrntq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshrnt.i16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b) + { +- return vshrntq_n_u32 (a, b, 16); ++ return vshrntq_n_u32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshrnt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b) + { +- return vshrntq (a, b, 16); ++ return vshrntq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshrnt.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { +- return vshrq_m_n_s16 (inactive, a, 16, p); ++ return vshrq_m_n_s16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { +- return vshrq_m (inactive, a, 16, p); ++ return vshrq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { +- return vshrq_m_n_s32 (inactive, a, 32, p); ++ return vshrq_m_n_s32 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { +- return vshrq_m (inactive, a, 32, p); ++ return vshrq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { +- return vshrq_m_n_s8 (inactive, a, 8, p); ++ return vshrq_m_n_s8 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { +- return vshrq_m (inactive, a, 8, p); ++ return vshrq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { +- return vshrq_m_n_u16 (inactive, a, 16, p); ++ return vshrq_m_n_u16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { +- return vshrq_m (inactive, a, 16, p); ++ return vshrq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { +- return vshrq_m_n_u32 (inactive, a, 32, p); ++ return vshrq_m_n_u32 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { +- return vshrq_m (inactive, a, 32, p); ++ return vshrq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { +- return vshrq_m_n_u8 (inactive, a, 8, p); ++ return vshrq_m_n_u8 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { +- return vshrq_m (inactive, a, 8, p); ++ return vshrq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshr.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a) + { +- return vshrq_n_s16 (a, 16); ++ return vshrq_n_s16 (a, 1); + } + +-/* { dg-final { scan-assembler "vshr.s16" } } */ + ++/* ++**foo1: ++** ... ++** vshr.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a) + { +- return vshrq (a, 16); ++ return vshrq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshr.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshr.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a) + { +- return vshrq_n_s32 (a, 32); ++ return vshrq_n_s32 (a, 1); + } + +-/* { dg-final { scan-assembler "vshr.s32" } } */ + ++/* ++**foo1: ++** ... ++** vshr.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a) + { +- return vshrq (a, 32); ++ return vshrq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshr.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshr.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a) + { +- return vshrq_n_s8 (a, 8); ++ return vshrq_n_s8 (a, 1); + } + +-/* { dg-final { scan-assembler "vshr.s8" } } */ + ++/* ++**foo1: ++** ... ++** vshr.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a) + { +- return vshrq (a, 8); ++ return vshrq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshr.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshr.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a) + { +- return vshrq_n_u16 (a, 16); ++ return vshrq_n_u16 (a, 1); + } + +-/* { dg-final { scan-assembler "vshr.u16" } } */ + ++/* ++**foo1: ++** ... ++** vshr.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a) + { +- return vshrq (a, 16); ++ return vshrq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshr.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshr.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a) + { +- return vshrq_n_u32 (a, 32); ++ return vshrq_n_u32 (a, 1); + } + +-/* { dg-final { scan-assembler "vshr.u32" } } */ + ++/* ++**foo1: ++** ... ++** vshr.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a) + { +- return vshrq (a, 32); ++ return vshrq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshr.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshr.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a) + { +- return vshrq_n_u8 (a, 8); ++ return vshrq_n_u8 (a, 1); + } + +-/* { dg-final { scan-assembler "vshr.u8" } } */ + ++/* ++**foo1: ++** ... ++** vshr.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a) + { +- return vshrq (a, 8); ++ return vshrq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshr.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, mve_pred16_t p) + { +- return vshrq_x_n_s16 (a, 16, p); ++ return vshrq_x_n_s16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++int16x8_t ++foo1 (int16x8_t a, mve_pred16_t p) ++{ ++ return vshrq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, mve_pred16_t p) + { +- return vshrq_x_n_s32 (a, 32, p); ++ return vshrq_x_n_s32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++int32x4_t ++foo1 (int32x4_t a, mve_pred16_t p) ++{ ++ return vshrq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, mve_pred16_t p) + { +- return vshrq_x_n_s8 (a, 8, p); ++ return vshrq_x_n_s8 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++int8x16_t ++foo1 (int8x16_t a, mve_pred16_t p) ++{ ++ return vshrq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, mve_pred16_t p) + { +- return vshrq_x_n_u16 (a, 16, p); ++ return vshrq_x_n_u16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo1 (uint16x8_t a, mve_pred16_t p) ++{ ++ return vshrq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, mve_pred16_t p) + { +- return vshrq_x_n_u8 (a, 8, p); ++ return vshrq_x_n_u8 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo1 (uint8x16_t a, mve_pred16_t p) ++{ ++ return vshrq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vslit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { +- return vsliq_m_n_s16 (a, b, 15, p); ++ return vsliq_m_n_s16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vslit.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vslit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { +- return vsliq_m (a, b, 15, p); ++ return vsliq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vslit.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vslit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { +- return vsliq_m_n_s32 (a, b, 31, p); ++ return vsliq_m_n_s32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vslit.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vslit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { +- return vsliq_m (a, b, 31, p); ++ return vsliq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vslit.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vslit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { +- return vsliq_m_n_s8 (a, b, 7, p); ++ return vsliq_m_n_s8 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vslit.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vslit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { +- return vsliq_m (a, b, 7, p); ++ return vsliq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vslit.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vslit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { +- return vsliq_m_n_u16 (a, b, 15, p); ++ return vsliq_m_n_u16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vslit.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vslit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { +- return vsliq_m (a, b, 15, p); ++ return vsliq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vslit.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vslit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { +- return vsliq_m_n_u32 (a, b, 31, p); ++ return vsliq_m_n_u32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vslit.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vslit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { +- return vsliq_m (a, b, 31, p); ++ return vsliq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vslit.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vslit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { +- return vsliq_m_n_u8 (a, b, 7, p); ++ return vsliq_m_n_u8 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vslit.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vslit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { +- return vsliq_m (a, b, 7, p); ++ return vsliq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vslit.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsli.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { +- return vsliq_n_s16 (a, b, 15); ++ return vsliq_n_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vsli.16" } } */ + ++/* ++**foo1: ++** ... ++** vsli.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { +- return vsliq (a, b, 15); ++ return vsliq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vsli.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsli.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { +- return vsliq_n_s32 (a, b, 31); ++ return vsliq_n_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vsli.32" } } */ + ++/* ++**foo1: ++** ... ++** vsli.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { +- return vsliq (a, b, 31); ++ return vsliq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vsli.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsli.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { +- return vsliq_n_s8 (a, b, 7); ++ return vsliq_n_s8 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vsli.8" } } */ + ++/* ++**foo1: ++** ... ++** vsli.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { +- return vsliq (a, b, 7); ++ return vsliq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vsli.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsli.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { +- return vsliq_n_u16 (a, b, 15); ++ return vsliq_n_u16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vsli.16" } } */ + ++/* ++**foo1: ++** ... ++** vsli.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { +- return vsliq (a, b, 15); ++ return vsliq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vsli.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsli.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { +- return vsliq_n_u32 (a, b, 31); ++ return vsliq_n_u32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vsli.32" } } */ + ++/* ++**foo1: ++** ... ++** vsli.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { +- return vsliq (a, b, 31); ++ return vsliq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vsli.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsli.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { +- return vsliq_n_u8 (a, b, 7); ++ return vsliq_n_u8 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vsli.8" } } */ + ++/* ++**foo1: ++** ... ++** vsli.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { +- return vsliq (a, b, 7); ++ return vsliq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vsli.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsrit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { +- return vsriq_m_n_s16 (a, b, 4, p); ++ return vsriq_m_n_s16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsrit.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsrit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { +- return vsriq_m (a, b, 4, p); ++ return vsriq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsrit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { +- return vsriq_m_n_s32 (a, b, 2, p); ++ return vsriq_m_n_s32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsrit.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsrit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { +- return vsriq_m (a, b, 2, p); ++ return vsriq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsrit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { +- return vsriq_m_n_s8 (a, b, 4, p); ++ return vsriq_m_n_s8 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsrit.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsrit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { +- return vsriq_m (a, b, 4, p); ++ return vsriq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsrit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { +- return vsriq_m_n_u16 (a, b, 4, p); ++ return vsriq_m_n_u16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsrit.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsrit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { +- return vsriq_m (a, b, 4, p); ++ return vsriq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsrit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { +- return vsriq_m_n_u32 (a, b, 4, p); ++ return vsriq_m_n_u32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsrit.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsrit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { +- return vsriq_m (a, b, 4, p); ++ return vsriq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsrit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { +- return vsriq_m_n_u8 (a, b, 4, p); ++ return vsriq_m_n_u8 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsrit.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsrit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { +- return vsriq_m (a, b, 4, p); ++ return vsriq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsri.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { +- return vsriq_n_s16 (a, b, 4); ++ return vsriq_n_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vsri.16" } } */ + ++/* ++**foo1: ++** ... ++** vsri.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { +- return vsriq (a, b, 4); ++ return vsriq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vsri.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsri.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { +- return vsriq_n_s32 (a, b, 4); ++ return vsriq_n_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vsri.32" } } */ + ++/* ++**foo1: ++** ... ++** vsri.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { +- return vsriq (a, b, 4); ++ return vsriq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vsri.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsri.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { +- return vsriq_n_s8 (a, b, 4); ++ return vsriq_n_s8 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vsri.8" } } */ + ++/* ++**foo1: ++** ... ++** vsri.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { +- return vsriq (a, b, 4); ++ return vsriq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vsri.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsri.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { +- return vsriq_n_u16 (a, b, 4); ++ return vsriq_n_u16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vsri.16" } } */ + ++/* ++**foo1: ++** ... ++** vsri.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { +- return vsriq (a, b, 4); ++ return vsriq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vsri.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsri.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { +- return vsriq_n_u32 (a, b, 4); ++ return vsriq_n_u32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vsri.32" } } */ + ++/* ++**foo1: ++** ... ++** vsri.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { +- return vsriq (a, b, 4); ++ return vsriq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vsri.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsri.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { +- return vsriq_n_u8 (a, b, 4); ++ return vsriq_n_u8 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vsri.8" } } */ + ++/* ++**foo1: ++** ... ++** vsri.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { +- return vsriq (a, b, 4); ++ return vsriq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vsri.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c +@@ -1,25 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + +-void +-foo (float16_t * addr, float16x8_t value) +-{ +- vst1q_f16 (addr, value); +-} ++#ifdef __cplusplus ++extern "C" { ++#endif + ++/* ++**foo: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (float16_t * addr, float16x8_t value) ++foo (float16_t *base, float16x8_t value) + { +- vst1q (addr, value); ++ return vst1q_f16 (base, value); + } + +-/* { dg-final { scan-assembler-times "vstrh.16" 2 } } */ + ++/* ++**foo1: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo2 (float16_t a, float16x8_t x) ++foo1 (float16_t *base, float16x8_t value) + { +- vst1q (&a, x); ++ return vst1q (base, value); + } ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (float32_t * addr, float32x4_t value) ++foo (float32_t *base, float32x4_t value) + { +- vst1q_f32 (addr, value); ++ return vst1q_f32 (base, value); + } + +-/* { dg-final { scan-assembler "vstrw.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (float32_t * addr, float32x4_t value) ++foo1 (float32_t *base, float32x4_t value) + { +- vst1q (addr, value); ++ return vst1q (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrw.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (float16_t * addr, float16x8_t value, mve_pred16_t p) ++foo (float16_t *base, float16x8_t value, mve_pred16_t p) + { +- vst1q_p_f16 (addr, value, p); ++ return vst1q_p_f16 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (float16_t * addr, float16x8_t value, mve_pred16_t p) ++foo1 (float16_t *base, float16x8_t value, mve_pred16_t p) + { +- vst1q_p (addr, value, p); ++ return vst1q_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (float32_t * addr, float32x4_t value, mve_pred16_t p) ++foo (float32_t *base, float32x4_t value, mve_pred16_t p) + { +- vst1q_p_f32 (addr, value, p); ++ return vst1q_p_f32 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (float32_t * addr, float32x4_t value, mve_pred16_t p) ++foo1 (float32_t *base, float32x4_t value, mve_pred16_t p) + { +- vst1q_p (addr, value, p); ++ return vst1q_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int16_t * addr, int16x8_t value, mve_pred16_t p) ++foo (int16_t *base, int16x8_t value, mve_pred16_t p) + { +- vst1q_p_s16 (addr, value, p); ++ return vst1q_p_s16 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int16_t * addr, int16x8_t value, mve_pred16_t p) ++foo1 (int16_t *base, int16x8_t value, mve_pred16_t p) + { +- vst1q_p (addr, value, p); ++ return vst1q_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int32_t * addr, int32x4_t value, mve_pred16_t p) ++foo (int32_t *base, int32x4_t value, mve_pred16_t p) + { +- vst1q_p_s32 (addr, value, p); ++ return vst1q_p_s32 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int32_t * addr, int32x4_t value, mve_pred16_t p) ++foo1 (int32_t *base, int32x4_t value, mve_pred16_t p) + { +- vst1q_p (addr, value, p); ++ return vst1q_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int8_t * addr, int8x16_t value, mve_pred16_t p) ++foo (int8_t *base, int8x16_t value, mve_pred16_t p) + { +- vst1q_p_s8 (addr, value, p); ++ return vst1q_p_s8 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrbt.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int8_t * addr, int8x16_t value, mve_pred16_t p) ++foo1 (int8_t *base, int8x16_t value, mve_pred16_t p) + { +- vst1q_p (addr, value, p); ++ return vst1q_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrbt.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint16_t * addr, uint16x8_t value, mve_pred16_t p) ++foo (uint16_t *base, uint16x8_t value, mve_pred16_t p) + { +- vst1q_p_u16 (addr, value, p); ++ return vst1q_p_u16 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint16_t * addr, uint16x8_t value, mve_pred16_t p) ++foo1 (uint16_t *base, uint16x8_t value, mve_pred16_t p) + { +- vst1q_p (addr, value, p); ++ return vst1q_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint32_t * addr, uint32x4_t value, mve_pred16_t p) ++foo (uint32_t *base, uint32x4_t value, mve_pred16_t p) + { +- vst1q_p_u32 (addr, value, p); ++ return vst1q_p_u32 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint32_t * addr, uint32x4_t value, mve_pred16_t p) ++foo1 (uint32_t *base, uint32x4_t value, mve_pred16_t p) + { +- vst1q_p (addr, value, p); ++ return vst1q_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint8_t * addr, uint8x16_t value, mve_pred16_t p) ++foo (uint8_t *base, uint8x16_t value, mve_pred16_t p) + { +- vst1q_p_u8 (addr, value, p); ++ return vst1q_p_u8 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrbt.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint8_t * addr, uint8x16_t value, mve_pred16_t p) ++foo1 (uint8_t *base, uint8x16_t value, mve_pred16_t p) + { +- vst1q_p (addr, value, p); ++ return vst1q_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrbt.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c +@@ -1,25 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + +-void +-foo (int16_t * addr, int16x8_t value) +-{ +- vst1q_s16 (addr, value); +-} ++#ifdef __cplusplus ++extern "C" { ++#endif + ++/* ++**foo: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int16_t * addr, int16x8_t value) ++foo (int16_t *base, int16x8_t value) + { +- vst1q (addr, value); ++ return vst1q_s16 (base, value); + } + +-/* { dg-final { scan-assembler-times "vstrh.16" 2 } } */ + ++/* ++**foo1: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo2 (int16_t a, int16x8_t x) ++foo1 (int16_t *base, int16x8_t value) + { +- vst1q (&a, x); ++ return vst1q (base, value); + } ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int32_t * addr, int32x4_t value) ++foo (int32_t *base, int32x4_t value) + { +- vst1q_s32 (addr, value); ++ return vst1q_s32 (base, value); + } + +-/* { dg-final { scan-assembler "vstrw.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int32_t * addr, int32x4_t value) ++foo1 (int32_t *base, int32x4_t value) + { +- vst1q (addr, value); ++ return vst1q (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrw.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c +@@ -1,25 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + +-void +-foo (int8_t * addr, int8x16_t value) +-{ +- vst1q_s8 (addr, value); +-} ++#ifdef __cplusplus ++extern "C" { ++#endif + ++/* ++**foo: ++** ... ++** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int8_t * addr, int8x16_t value) ++foo (int8_t *base, int8x16_t value) + { +- vst1q (addr, value); ++ return vst1q_s8 (base, value); + } + +-/* { dg-final { scan-assembler-times "vstrb.8" 2 } } */ + ++/* ++**foo1: ++** ... ++** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo2 (int8_t a, int8x16_t x) ++foo1 (int8_t *base, int8x16_t value) + { +- vst1q (&a, x); ++ return vst1q (base, value); + } ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c +@@ -1,25 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + +-void +-foo (uint16_t * addr, uint16x8_t value) +-{ +- vst1q_u16 (addr, value); +-} ++#ifdef __cplusplus ++extern "C" { ++#endif + ++/* ++**foo: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint16_t * addr, uint16x8_t value) ++foo (uint16_t *base, uint16x8_t value) + { +- vst1q (addr, value); ++ return vst1q_u16 (base, value); + } + +-/* { dg-final { scan-assembler-times "vstrh.16" 2 } } */ + ++/* ++**foo1: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo2 (uint16_t a, uint16x8_t x) ++foo1 (uint16_t *base, uint16x8_t value) + { +- vst1q (&a, x); ++ return vst1q (base, value); + } ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint32_t * addr, uint32x4_t value) ++foo (uint32_t *base, uint32x4_t value) + { +- vst1q_u32 (addr, value); ++ return vst1q_u32 (base, value); + } + +-/* { dg-final { scan-assembler "vstrw.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint32_t * addr, uint32x4_t value) ++foo1 (uint32_t *base, uint32x4_t value) + { +- vst1q (addr, value); ++ return vst1q (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrw.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c +@@ -1,25 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + +-void +-foo (uint8_t * addr, uint8x16_t value) +-{ +- vst1q_u8 (addr, value); +-} ++#ifdef __cplusplus ++extern "C" { ++#endif + ++/* ++**foo: ++** ... ++** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint8_t * addr, uint8x16_t value) ++foo (uint8_t *base, uint8x16_t value) + { +- vst1q (addr, value); ++ return vst1q_u8 (base, value); + } + +-/* { dg-final { scan-assembler-times "vstrb.8" 2 } } */ + ++/* ++**foo1: ++** ... ++** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo2 (uint8_t a, uint8x16_t x) ++foo1 (uint8_t *base, uint8x16_t value) + { +- vst1q (&a, x); ++ return vst1q (base, value); + } ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c +@@ -1,22 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (float16_t * addr, float16x8x2_t value) ++foo (float16_t *addr, float16x8x2_t value) + { +- vst2q_f16 (addr, value); ++ return vst2q_f16 (addr, value); + } + +-/* { dg-final { scan-assembler "vst20.16" } } */ +-/* { dg-final { scan-assembler "vst21.16" } } */ + ++/* ++**foo1: ++** ... ++** vst20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (float16_t * addr, float16x8x2_t value) ++foo1 (float16_t *addr, float16x8x2_t value) + { +- vst2q (addr, value); ++ return vst2q (addr, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vst20.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c +@@ -1,22 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (float32_t * addr, float32x4x2_t value) ++foo (float32_t *addr, float32x4x2_t value) + { +- vst2q_f32 (addr, value); ++ return vst2q_f32 (addr, value); + } + +-/* { dg-final { scan-assembler "vst20.32" } } */ +-/* { dg-final { scan-assembler "vst21.32" } } */ + ++/* ++**foo1: ++** ... ++** vst20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (float32_t * addr, float32x4x2_t value) ++foo1 (float32_t *addr, float32x4x2_t value) + { +- vst2q (addr, value); ++ return vst2q (addr, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vst20.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c +@@ -1,22 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int16_t * addr, int16x8x2_t value) ++foo (int16_t *addr, int16x8x2_t value) + { +- vst2q_s16 (addr, value); ++ return vst2q_s16 (addr, value); + } + +-/* { dg-final { scan-assembler "vst20.16" } } */ +-/* { dg-final { scan-assembler "vst21.16" } } */ + ++/* ++**foo1: ++** ... ++** vst20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int16_t * addr, int16x8x2_t value) ++foo1 (int16_t *addr, int16x8x2_t value) + { +- vst2q (addr, value); ++ return vst2q (addr, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vst20.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c +@@ -1,22 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int32_t * addr, int32x4x2_t value) ++foo (int32_t *addr, int32x4x2_t value) + { +- vst2q_s32 (addr, value); ++ return vst2q_s32 (addr, value); + } + +-/* { dg-final { scan-assembler "vst20.32" } } */ +-/* { dg-final { scan-assembler "vst21.32" } } */ + ++/* ++**foo1: ++** ... ++** vst20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int32_t * addr, int32x4x2_t value) ++foo1 (int32_t *addr, int32x4x2_t value) + { +- vst2q (addr, value); ++ return vst2q (addr, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vst20.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c +@@ -1,22 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int8_t * addr, int8x16x2_t value) ++foo (int8_t *addr, int8x16x2_t value) + { +- vst2q_s8 (addr, value); ++ return vst2q_s8 (addr, value); + } + +-/* { dg-final { scan-assembler "vst20.8" } } */ +-/* { dg-final { scan-assembler "vst21.8" } } */ + ++/* ++**foo1: ++** ... ++** vst20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int8_t * addr, int8x16x2_t value) ++foo1 (int8_t *addr, int8x16x2_t value) + { +- vst2q (addr, value); ++ return vst2q (addr, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vst20.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c +@@ -1,22 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint16_t * addr, uint16x8x2_t value) ++foo (uint16_t *addr, uint16x8x2_t value) + { +- vst2q_u16 (addr, value); ++ return vst2q_u16 (addr, value); + } + +-/* { dg-final { scan-assembler "vst20.16" } } */ +-/* { dg-final { scan-assembler "vst21.16" } } */ + ++/* ++**foo1: ++** ... ++** vst20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint16_t * addr, uint16x8x2_t value) ++foo1 (uint16_t *addr, uint16x8x2_t value) + { +- vst2q (addr, value); ++ return vst2q (addr, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vst20.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c +@@ -1,22 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint32_t * addr, uint32x4x2_t value) ++foo (uint32_t *addr, uint32x4x2_t value) + { +- vst2q_u32 (addr, value); ++ return vst2q_u32 (addr, value); + } + +-/* { dg-final { scan-assembler "vst20.32" } } */ +-/* { dg-final { scan-assembler "vst21.32" } } */ + ++/* ++**foo1: ++** ... ++** vst20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint32_t * addr, uint32x4x2_t value) ++foo1 (uint32_t *addr, uint32x4x2_t value) + { +- vst2q (addr, value); ++ return vst2q (addr, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vst20.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c +@@ -1,22 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint8_t * addr, uint8x16x2_t value) ++foo (uint8_t *addr, uint8x16x2_t value) + { +- vst2q_u8 (addr, value); ++ return vst2q_u8 (addr, value); + } + +-/* { dg-final { scan-assembler "vst20.8" } } */ +-/* { dg-final { scan-assembler "vst21.8" } } */ + ++/* ++**foo1: ++** ... ++** vst20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint8_t * addr, uint8x16x2_t value) ++foo1 (uint8_t *addr, uint8x16x2_t value) + { +- vst2q (addr, value); ++ return vst2q (addr, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vst20.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c +@@ -1,37 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo (float16_t * addr, float16x8x4_t value) ++foo (float16_t *addr, float16x8x4_t value) + { +- vst4q_f16 (addr, value); ++ return vst4q_f16 (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.16" } } */ +-/* { dg-final { scan-assembler "vst41.16" } } */ +-/* { dg-final { scan-assembler "vst42.16" } } */ +-/* { dg-final { scan-assembler "vst43.16" } } */ + ++/* ++**foo1: ++** ... ++** vst40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo1 (float16_t * addr, float16x8x4_t value) ++foo1 (float16_t *addr, float16x8x4_t value) + { +- vst4q (addr, value); ++ return vst4q (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.16" } } */ +-/* { dg-final { scan-assembler "vst41.16" } } */ +-/* { dg-final { scan-assembler "vst42.16" } } */ +-/* { dg-final { scan-assembler "vst43.16" } } */ +- +-void +-foo2 (float16_t * addr, float16x8x4_t value) +-{ +- vst4q_f16 (addr, value); +- addr += 32; +- vst4q_f16 (addr, value); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler {vst43.16\s\{.*\}, \[.*\]!} } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c +@@ -1,37 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo (float32_t * addr, float32x4x4_t value) ++foo (float32_t *addr, float32x4x4_t value) + { +- vst4q_f32 (addr, value); ++ return vst4q_f32 (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.32" } } */ +-/* { dg-final { scan-assembler "vst41.32" } } */ +-/* { dg-final { scan-assembler "vst42.32" } } */ +-/* { dg-final { scan-assembler "vst43.32" } } */ + ++/* ++**foo1: ++** ... ++** vst40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo1 (float32_t * addr, float32x4x4_t value) ++foo1 (float32_t *addr, float32x4x4_t value) + { +- vst4q (addr, value); ++ return vst4q (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.32" } } */ +-/* { dg-final { scan-assembler "vst41.32" } } */ +-/* { dg-final { scan-assembler "vst42.32" } } */ +-/* { dg-final { scan-assembler "vst43.32" } } */ +- +-void +-foo2 (float32_t * addr, float32x4x4_t value) +-{ +- vst4q_f32 (addr, value); +- addr += 16; +- vst4q_f32 (addr, value); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler {vst43.32\s\{.*\}, \[.*\]!} } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c +@@ -1,37 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo (int16_t * addr, int16x8x4_t value) ++foo (int16_t *addr, int16x8x4_t value) + { +- vst4q_s16 (addr, value); ++ return vst4q_s16 (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.16" } } */ +-/* { dg-final { scan-assembler "vst41.16" } } */ +-/* { dg-final { scan-assembler "vst42.16" } } */ +-/* { dg-final { scan-assembler "vst43.16" } } */ + ++/* ++**foo1: ++** ... ++** vst40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo1 (int16_t * addr, int16x8x4_t value) ++foo1 (int16_t *addr, int16x8x4_t value) + { +- vst4q (addr, value); ++ return vst4q (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.16" } } */ +-/* { dg-final { scan-assembler "vst41.16" } } */ +-/* { dg-final { scan-assembler "vst42.16" } } */ +-/* { dg-final { scan-assembler "vst43.16" } } */ +- +-void +-foo2 (int16_t * addr, int16x8x4_t value) +-{ +- vst4q_s16 (addr, value); +- addr += 32; +- vst4q_s16 (addr, value); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler {vst43.16\s\{.*\}, \[.*\]!} } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c +@@ -1,37 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo (int32_t * addr, int32x4x4_t value) ++foo (int32_t *addr, int32x4x4_t value) + { +- vst4q_s32 (addr, value); ++ return vst4q_s32 (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.32" } } */ +-/* { dg-final { scan-assembler "vst41.32" } } */ +-/* { dg-final { scan-assembler "vst42.32" } } */ +-/* { dg-final { scan-assembler "vst43.32" } } */ + ++/* ++**foo1: ++** ... ++** vst40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo1 (int32_t * addr, int32x4x4_t value) ++foo1 (int32_t *addr, int32x4x4_t value) + { +- vst4q (addr, value); ++ return vst4q (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.32" } } */ +-/* { dg-final { scan-assembler "vst41.32" } } */ +-/* { dg-final { scan-assembler "vst42.32" } } */ +-/* { dg-final { scan-assembler "vst43.32" } } */ +- +-void +-foo2 (int32_t * addr, int32x4x4_t value) +-{ +- vst4q_s32 (addr, value); +- addr += 16; +- vst4q_s32 (addr, value); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler {vst43.32\s\{.*\}, \[.*\]!} } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c +@@ -1,37 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo (int8_t * addr, int8x16x4_t value) ++foo (int8_t *addr, int8x16x4_t value) + { +- vst4q_s8 (addr, value); ++ return vst4q_s8 (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.8" } } */ +-/* { dg-final { scan-assembler "vst41.8" } } */ +-/* { dg-final { scan-assembler "vst42.8" } } */ +-/* { dg-final { scan-assembler "vst43.8" } } */ + ++/* ++**foo1: ++** ... ++** vst40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo1 (int8_t * addr, int8x16x4_t value) ++foo1 (int8_t *addr, int8x16x4_t value) + { +- vst4q (addr, value); ++ return vst4q (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.8" } } */ +-/* { dg-final { scan-assembler "vst41.8" } } */ +-/* { dg-final { scan-assembler "vst42.8" } } */ +-/* { dg-final { scan-assembler "vst43.8" } } */ +- +-void +-foo2 (int8_t * addr, int8x16x4_t value) +-{ +- vst4q_s8 (addr, value); +- addr += 16*4; +- vst4q_s8 (addr, value); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler {vst43.8\s\{.*\}, \[.*\]!} } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c +@@ -1,37 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo (uint16_t * addr, uint16x8x4_t value) ++foo (uint16_t *addr, uint16x8x4_t value) + { +- vst4q_u16 (addr, value); ++ return vst4q_u16 (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.16" } } */ +-/* { dg-final { scan-assembler "vst41.16" } } */ +-/* { dg-final { scan-assembler "vst42.16" } } */ +-/* { dg-final { scan-assembler "vst43.16" } } */ + ++/* ++**foo1: ++** ... ++** vst40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo1 (uint16_t * addr, uint16x8x4_t value) ++foo1 (uint16_t *addr, uint16x8x4_t value) + { +- vst4q (addr, value); ++ return vst4q (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.16" } } */ +-/* { dg-final { scan-assembler "vst41.16" } } */ +-/* { dg-final { scan-assembler "vst42.16" } } */ +-/* { dg-final { scan-assembler "vst43.16" } } */ +- +-void +-foo2 (uint16_t * addr, uint16x8x4_t value) +-{ +- vst4q_u16 (addr, value); +- addr += 32; +- vst4q_u16 (addr, value); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler {vst43.16\s\{.*\}, \[.*\]!} } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c +@@ -1,37 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo (uint32_t * addr, uint32x4x4_t value) ++foo (uint32_t *addr, uint32x4x4_t value) + { +- vst4q_u32 (addr, value); ++ return vst4q_u32 (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.32" } } */ +-/* { dg-final { scan-assembler "vst41.32" } } */ +-/* { dg-final { scan-assembler "vst42.32" } } */ +-/* { dg-final { scan-assembler "vst43.32" } } */ + ++/* ++**foo1: ++** ... ++** vst40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo1 (uint32_t * addr, uint32x4x4_t value) ++foo1 (uint32_t *addr, uint32x4x4_t value) + { +- vst4q (addr, value); ++ return vst4q (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.32" } } */ +-/* { dg-final { scan-assembler "vst41.32" } } */ +-/* { dg-final { scan-assembler "vst42.32" } } */ +-/* { dg-final { scan-assembler "vst43.32" } } */ +- +-void +-foo2 (uint32_t * addr, uint32x4x4_t value) +-{ +- vst4q_u32 (addr, value); +- addr += 16; +- vst4q_u32 (addr, value); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler {vst43.32\s\{.*\}, \[.*\]!} } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c +@@ -1,37 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo (uint8_t * addr, uint8x16x4_t value) ++foo (uint8_t *addr, uint8x16x4_t value) + { +- vst4q_u8 (addr, value); ++ return vst4q_u8 (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.8" } } */ +-/* { dg-final { scan-assembler "vst41.8" } } */ +-/* { dg-final { scan-assembler "vst42.8" } } */ +-/* { dg-final { scan-assembler "vst43.8" } } */ + ++/* ++**foo1: ++** ... ++** vst40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo1 (uint8_t * addr, uint8x16x4_t value) ++foo1 (uint8_t *addr, uint8x16x4_t value) + { +- vst4q (addr, value); ++ return vst4q (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.8" } } */ +-/* { dg-final { scan-assembler "vst41.8" } } */ +-/* { dg-final { scan-assembler "vst42.8" } } */ +-/* { dg-final { scan-assembler "vst43.8" } } */ +- +-void +-foo2 (uint8_t * addr, uint8x16x4_t value) +-{ +- vst4q_u8 (addr, value); +- addr += 16*4; +- vst4q_u8 (addr, value); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler {vst43.8\s\{.*\}, \[.*\]!} } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int8_t * addr, int16x8_t value, mve_pred16_t p) ++foo (int8_t *base, int16x8_t value, mve_pred16_t p) + { +- vstrbq_p_s16 (addr, value, p); ++ return vstrbq_p_s16 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrbt.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int8_t * addr, int16x8_t value, mve_pred16_t p) ++foo1 (int8_t *base, int16x8_t value, mve_pred16_t p) + { +- vstrbq_p (addr, value, p); ++ return vstrbq_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrbt.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int8_t * addr, int32x4_t value, mve_pred16_t p) ++foo (int8_t *base, int32x4_t value, mve_pred16_t p) + { +- vstrbq_p_s32 (addr, value, p); ++ return vstrbq_p_s32 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrbt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int8_t * addr, int32x4_t value, mve_pred16_t p) ++foo1 (int8_t *base, int32x4_t value, mve_pred16_t p) + { +- vstrbq_p (addr, value, p); ++ return vstrbq_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrbt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int8_t * addr, int8x16_t value, mve_pred16_t p) ++foo (int8_t *base, int8x16_t value, mve_pred16_t p) + { +- vstrbq_p_s8 (addr, value, p); ++ return vstrbq_p_s8 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrbt.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int8_t * addr, int8x16_t value, mve_pred16_t p) ++foo1 (int8_t *base, int8x16_t value, mve_pred16_t p) + { +- vstrbq_p (addr, value, p); ++ return vstrbq_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrbt.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint8_t * addr, uint16x8_t value, mve_pred16_t p) ++foo (uint8_t *base, uint16x8_t value, mve_pred16_t p) + { +- vstrbq_p_u16 (addr, value, p); ++ return vstrbq_p_u16 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrbt.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint8_t * addr, uint16x8_t value, mve_pred16_t p) ++foo1 (uint8_t *base, uint16x8_t value, mve_pred16_t p) + { +- vstrbq_p (addr, value, p); ++ return vstrbq_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrbt.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint8_t * addr, uint32x4_t value, mve_pred16_t p) ++foo (uint8_t *base, uint32x4_t value, mve_pred16_t p) + { +- vstrbq_p_u32 (addr, value, p); ++ return vstrbq_p_u32 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrbt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint8_t * addr, uint32x4_t value, mve_pred16_t p) ++foo1 (uint8_t *base, uint32x4_t value, mve_pred16_t p) + { +- vstrbq_p (addr, value, p); ++ return vstrbq_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrbt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint8_t * addr, uint8x16_t value, mve_pred16_t p) ++foo (uint8_t *base, uint8x16_t value, mve_pred16_t p) + { +- vstrbq_p_u8 (addr, value, p); ++ return vstrbq_p_u8 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrbt.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint8_t * addr, uint8x16_t value, mve_pred16_t p) ++foo1 (uint8_t *base, uint8x16_t value, mve_pred16_t p) + { +- vstrbq_p (addr, value, p); ++ return vstrbq_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrbt.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int8_t * addr, int16x8_t value) ++foo (int8_t *base, int16x8_t value) + { +- vstrbq_s16 (addr, value); ++ return vstrbq_s16 (base, value); + } + +-/* { dg-final { scan-assembler "vstrb.16" } } */ + ++/* ++**foo1: ++** ... ++** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int8_t * addr, int16x8_t value) ++foo1 (int8_t *base, int16x8_t value) + { +- vstrbq (addr, value); ++ return vstrbq (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrb.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int8_t * addr, int32x4_t value) ++foo (int8_t *base, int32x4_t value) + { +- vstrbq_s32 (addr, value); ++ return vstrbq_s32 (base, value); + } + +-/* { dg-final { scan-assembler "vstrb.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int8_t * addr, int32x4_t value) ++foo1 (int8_t *base, int32x4_t value) + { +- vstrbq (addr, value); ++ return vstrbq (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrb.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int8_t * addr, int8x16_t value) ++foo (int8_t *base, int8x16_t value) + { +- vstrbq_s8 (addr, value); ++ return vstrbq_s8 (base, value); + } + +-/* { dg-final { scan-assembler "vstrb.8" } } */ + ++/* ++**foo1: ++** ... ++** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int8_t * addr, int8x16_t value) ++foo1 (int8_t *base, int8x16_t value) + { +- vstrbq (addr, value); ++ return vstrbq (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrb.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (int8_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) ++foo (int8_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) + { +- vstrbq_scatter_offset_p_s16 (base, offset, value, p); ++ return vstrbq_scatter_offset_p_s16 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrbt.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (int8_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) ++foo1 (int8_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) + { +- vstrbq_scatter_offset_p (base, offset, value, p); ++ return vstrbq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrbt.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (int8_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) ++foo (int8_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) + { +- vstrbq_scatter_offset_p_s32 (base, offset, value, p); ++ return vstrbq_scatter_offset_p_s32 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrbt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (int8_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) ++foo1 (int8_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) + { +- vstrbq_scatter_offset_p (base, offset, value, p); ++ return vstrbq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrbt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (int8_t * base, uint8x16_t offset, int8x16_t value, mve_pred16_t p) ++foo (int8_t *base, uint8x16_t offset, int8x16_t value, mve_pred16_t p) + { +- vstrbq_scatter_offset_p_s8 (base, offset, value, p); ++ return vstrbq_scatter_offset_p_s8 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrbt.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (int8_t * base, uint8x16_t offset, int8x16_t value, mve_pred16_t p) ++foo1 (int8_t *base, uint8x16_t offset, int8x16_t value, mve_pred16_t p) + { +- vstrbq_scatter_offset_p (base, offset, value, p); ++ return vstrbq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrbt.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint8_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) ++foo (uint8_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) + { +- vstrbq_scatter_offset_p_u16 (base, offset, value, p); ++ return vstrbq_scatter_offset_p_u16 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrbt.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint8_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) ++foo1 (uint8_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) + { +- vstrbq_scatter_offset_p (base, offset, value, p); ++ return vstrbq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrbt.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint8_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) ++foo (uint8_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) + { +- vstrbq_scatter_offset_p_u32 (base, offset, value, p); ++ return vstrbq_scatter_offset_p_u32 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrbt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint8_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) ++foo1 (uint8_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) + { +- vstrbq_scatter_offset_p (base, offset, value, p); ++ return vstrbq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrbt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint8_t * base, uint8x16_t offset, uint8x16_t value, mve_pred16_t p) ++foo (uint8_t *base, uint8x16_t offset, uint8x16_t value, mve_pred16_t p) + { +- vstrbq_scatter_offset_p_u8 (base, offset, value, p); ++ return vstrbq_scatter_offset_p_u8 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrbt.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint8_t * base, uint8x16_t offset, uint8x16_t value, mve_pred16_t p) ++foo1 (uint8_t *base, uint8x16_t offset, uint8x16_t value, mve_pred16_t p) + { +- vstrbq_scatter_offset_p (base, offset, value, p); ++ return vstrbq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrbt.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (int8_t * base, uint16x8_t offset, int16x8_t value) ++foo (int8_t *base, uint16x8_t offset, int16x8_t value) + { +- vstrbq_scatter_offset_s16 (base, offset, value); ++ return vstrbq_scatter_offset_s16 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrb.16" } } */ + ++/* ++**foo1: ++** ... ++** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (int8_t * base, uint16x8_t offset, int16x8_t value) ++foo1 (int8_t *base, uint16x8_t offset, int16x8_t value) + { +- vstrbq_scatter_offset (base, offset, value); ++ return vstrbq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrb.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (int8_t * base, uint32x4_t offset, int32x4_t value) ++foo (int8_t *base, uint32x4_t offset, int32x4_t value) + { +- vstrbq_scatter_offset_s32 (base, offset, value); ++ return vstrbq_scatter_offset_s32 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrb.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (int8_t * base, uint32x4_t offset, int32x4_t value) ++foo1 (int8_t *base, uint32x4_t offset, int32x4_t value) + { +- vstrbq_scatter_offset (base, offset, value); ++ return vstrbq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrb.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (int8_t * base, uint8x16_t offset, int8x16_t value) ++foo (int8_t *base, uint8x16_t offset, int8x16_t value) + { +- vstrbq_scatter_offset_s8 (base, offset, value); ++ return vstrbq_scatter_offset_s8 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrb.8" } } */ + ++/* ++**foo1: ++** ... ++** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (int8_t * base, uint8x16_t offset, int8x16_t value) ++foo1 (int8_t *base, uint8x16_t offset, int8x16_t value) + { +- vstrbq_scatter_offset (base, offset, value); ++ return vstrbq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrb.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint8_t * base, uint16x8_t offset, uint16x8_t value) ++foo (uint8_t *base, uint16x8_t offset, uint16x8_t value) + { +- vstrbq_scatter_offset_u16 (base, offset, value); ++ return vstrbq_scatter_offset_u16 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrb.16" } } */ + ++/* ++**foo1: ++** ... ++** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint8_t * base, uint16x8_t offset, uint16x8_t value) ++foo1 (uint8_t *base, uint16x8_t offset, uint16x8_t value) + { +- vstrbq_scatter_offset (base, offset, value); ++ return vstrbq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrb.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint8_t * base, uint32x4_t offset, uint32x4_t value) ++foo (uint8_t *base, uint32x4_t offset, uint32x4_t value) + { +- vstrbq_scatter_offset_u32 (base, offset, value); ++ return vstrbq_scatter_offset_u32 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrb.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint8_t * base, uint32x4_t offset, uint32x4_t value) ++foo1 (uint8_t *base, uint32x4_t offset, uint32x4_t value) + { +- vstrbq_scatter_offset (base, offset, value); ++ return vstrbq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrb.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint8_t * base, uint8x16_t offset, uint8x16_t value) ++foo (uint8_t *base, uint8x16_t offset, uint8x16_t value) + { +- vstrbq_scatter_offset_u8 (base, offset, value); ++ return vstrbq_scatter_offset_u8 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrb.8" } } */ + ++/* ++**foo1: ++** ... ++** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint8_t * base, uint8x16_t offset, uint8x16_t value) ++foo1 (uint8_t *base, uint8x16_t offset, uint8x16_t value) + { +- vstrbq_scatter_offset (base, offset, value); ++ return vstrbq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrb.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint8_t * addr, uint16x8_t value) ++foo (uint8_t *base, uint16x8_t value) + { +- vstrbq_u16 (addr, value); ++ return vstrbq_u16 (base, value); + } + +-/* { dg-final { scan-assembler "vstrb.16" } } */ + ++/* ++**foo1: ++** ... ++** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint8_t * addr, uint16x8_t value) ++foo1 (uint8_t *base, uint16x8_t value) + { +- vstrbq (addr, value); ++ return vstrbq (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrb.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint8_t * addr, uint32x4_t value) ++foo (uint8_t *base, uint32x4_t value) + { +- vstrbq_u32 (addr, value); ++ return vstrbq_u32 (base, value); + } + +-/* { dg-final { scan-assembler "vstrb.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint8_t * addr, uint32x4_t value) ++foo1 (uint8_t *base, uint32x4_t value) + { +- vstrbq (addr, value); ++ return vstrbq (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrb.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint8_t * addr, uint8x16_t value) ++foo (uint8_t *base, uint8x16_t value) + { +- vstrbq_u8 (addr, value); ++ return vstrbq_u8 (base, value); + } + +-/* { dg-final { scan-assembler "vstrb.8" } } */ + ++/* ++**foo1: ++** ... ++** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint8_t * addr, uint8x16_t value) ++foo1 (uint8_t *base, uint8x16_t value) + { +- vstrbq (addr, value); ++ return vstrbq (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrb.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint64x2_t addr, const int offset, int64x2_t value, mve_pred16_t p) ++foo (uint64x2_t addr, int64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_base_p_s64 (addr, 8, value, p); ++ return vstrdq_scatter_base_p_s64 (addr, 0, value, p); + } + +-/* { dg-final { scan-assembler "vstrdt.u64" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint64x2_t addr, const int offset, int64x2_t value, mve_pred16_t p) ++foo1 (uint64x2_t addr, int64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_base_p (addr, 8, value, p); ++ return vstrdq_scatter_base_p (addr, 0, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrdt.u64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint64x2_t addr, const int offset, uint64x2_t value, mve_pred16_t p) ++foo (uint64x2_t addr, uint64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_base_p_u64 (addr, 8, value, p); ++ return vstrdq_scatter_base_p_u64 (addr, 0, value, p); + } + +-/* { dg-final { scan-assembler "vstrdt.u64" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint64x2_t addr, const int offset, uint64x2_t value, mve_pred16_t p) ++foo1 (uint64x2_t addr, uint64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_base_p (addr, 8, value, p); ++ return vstrdq_scatter_base_p (addr, 0, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrdt.u64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint64x2_t addr, const int offset, int64x2_t value) ++foo (uint64x2_t addr, int64x2_t value) + { +- vstrdq_scatter_base_s64 (addr, 1016, value); ++ return vstrdq_scatter_base_s64 (addr, 0, value); + } + +-/* { dg-final { scan-assembler "vstrd.u64" } } */ + ++/* ++**foo1: ++** ... ++** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint64x2_t addr, const int offset, int64x2_t value) ++foo1 (uint64x2_t addr, int64x2_t value) + { +- vstrdq_scatter_base (addr, 1016, value); ++ return vstrdq_scatter_base (addr, 0, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrd.u64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint64x2_t addr, const int offset, uint64x2_t value) ++foo (uint64x2_t addr, uint64x2_t value) + { +- vstrdq_scatter_base_u64 (addr, 8, value); ++ return vstrdq_scatter_base_u64 (addr, 0, value); + } + +-/* { dg-final { scan-assembler "vstrd.u64" } } */ + ++/* ++**foo1: ++** ... ++** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint64x2_t addr, const int offset, uint64x2_t value) ++foo1 (uint64x2_t addr, uint64x2_t value) + { +- vstrdq_scatter_base (addr, 8, value); ++ return vstrdq_scatter_base (addr, 0, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrd.u64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c +@@ -1,19 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo (uint64x2_t * addr, const int offset, int64x2_t value, mve_pred16_t p) ++foo (uint64x2_t *addr, int64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_base_wb_p_s64 (addr, 8, value, p); ++ return vstrdq_scatter_base_wb_p_s64 (addr, 0, value, p); + } + ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo1 (uint64x2_t * addr, const int offset, int64x2_t value, mve_pred16_t p) ++foo1 (uint64x2_t *addr, int64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_base_wb_p (addr, 8, value, p); ++ return vstrdq_scatter_base_wb_p (addr, 0, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-times "vstrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c +@@ -1,19 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo (uint64x2_t * addr, const int offset, uint64x2_t value, mve_pred16_t p) ++foo (uint64x2_t *addr, uint64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_base_wb_p_u64 (addr, 8, value, p); ++ return vstrdq_scatter_base_wb_p_u64 (addr, 0, value, p); + } + ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo1 (uint64x2_t * addr, const int offset, uint64x2_t value, mve_pred16_t p) ++foo1 (uint64x2_t *addr, uint64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_base_wb_p (addr, 8, value, p); ++ return vstrdq_scatter_base_wb_p (addr, 0, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-times "vstrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c +@@ -1,19 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo (uint64x2_t * addr, const int offset, int64x2_t value) ++foo (uint64x2_t *addr, int64x2_t value) + { +- vstrdq_scatter_base_wb_s64 (addr, 8, value); ++ return vstrdq_scatter_base_wb_s64 (addr, 0, value); + } + ++ ++/* ++**foo1: ++** ... ++** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo1 (uint64x2_t * addr, const int offset, int64x2_t value) ++foo1 (uint64x2_t *addr, int64x2_t value) + { +- vstrdq_scatter_base_wb (addr, 8, value); ++ return vstrdq_scatter_base_wb (addr, 0, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-times "vstrd.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c +@@ -1,19 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo (uint64x2_t * addr, const int offset, uint64x2_t value) ++foo (uint64x2_t *addr, uint64x2_t value) + { +- vstrdq_scatter_base_wb_u64 (addr, 8, value); ++ return vstrdq_scatter_base_wb_u64 (addr, 0, value); + } + ++ ++/* ++**foo1: ++** ... ++** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo1 (uint64x2_t * addr, const int offset, uint64x2_t value) ++foo1 (uint64x2_t *addr, uint64x2_t value) + { +- vstrdq_scatter_base_wb (addr, 8, value); ++ return vstrdq_scatter_base_wb (addr, 0, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-times "vstrd.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p) ++foo (int64_t *base, uint64x2_t offset, int64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_offset_p_s64 (base, offset, value, p); ++ return vstrdq_scatter_offset_p_s64 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrdt.64" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p) ++foo1 (int64_t *base, uint64x2_t offset, int64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_offset_p (base, offset, value, p); ++ return vstrdq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrdt.64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p) ++foo (uint64_t *base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_offset_p_u64 (base, offset, value, p); ++ return vstrdq_scatter_offset_p_u64 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrdt.64" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p) ++foo1 (uint64_t *base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_offset_p (base, offset, value, p); ++ return vstrdq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrdt.64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (int64_t * base, uint64x2_t offset, int64x2_t value) ++foo (int64_t *base, uint64x2_t offset, int64x2_t value) + { +- vstrdq_scatter_offset_s64 (base, offset, value); ++ return vstrdq_scatter_offset_s64 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrd.64" } } */ + ++/* ++**foo1: ++** ... ++** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (int64_t * base, uint64x2_t offset, int64x2_t value) ++foo1 (int64_t *base, uint64x2_t offset, int64x2_t value) + { +- vstrdq_scatter_offset (base, offset, value); ++ return vstrdq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrd.64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint64_t * base, uint64x2_t offset, uint64x2_t value) ++foo (uint64_t *base, uint64x2_t offset, uint64x2_t value) + { +- vstrdq_scatter_offset_u64 (base, offset, value); ++ return vstrdq_scatter_offset_u64 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrd.64" } } */ + ++/* ++**foo1: ++** ... ++** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value) ++foo1 (uint64_t *base, uint64x2_t offset, uint64x2_t value) + { +- vstrdq_scatter_offset (base, offset, value); ++ return vstrdq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrd.64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + void +-foo (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p) ++foo (int64_t *base, uint64x2_t offset, int64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_shifted_offset_p_s64 (base, offset, value, p); ++ return vstrdq_scatter_shifted_offset_p_s64 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrdt.64" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + void +-foo1 (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p) ++foo1 (int64_t *base, uint64x2_t offset, int64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_shifted_offset_p (base, offset, value, p); ++ return vstrdq_scatter_shifted_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrdt.64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + void +-foo (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p) ++foo (uint64_t *base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_shifted_offset_p_u64 (base, offset, value, p); ++ return vstrdq_scatter_shifted_offset_p_u64 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrdt.64" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p) ++foo1 (uint64_t *base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_shifted_offset_p (base, offset, value, p); ++ return vstrdq_scatter_shifted_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrdt.64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + void +-foo (int64_t * base, uint64x2_t offset, int64x2_t value) ++foo (int64_t *base, uint64x2_t offset, int64x2_t value) + { +- vstrdq_scatter_shifted_offset_s64 (base, offset, value); ++ return vstrdq_scatter_shifted_offset_s64 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrd.64" } } */ + ++/* ++**foo1: ++** ... ++** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + void +-foo1 (int64_t * base, uint64x2_t offset, int64x2_t value) ++foo1 (int64_t *base, uint64x2_t offset, int64x2_t value) + { +- vstrdq_scatter_shifted_offset (base, offset, value); ++ return vstrdq_scatter_shifted_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrd.64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + void +-foo (uint64_t * base, uint64x2_t offset, uint64x2_t value) ++foo (uint64_t *base, uint64x2_t offset, uint64x2_t value) + { +- vstrdq_scatter_shifted_offset_u64 (base, offset, value); ++ return vstrdq_scatter_shifted_offset_u64 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrd.64" } } */ + ++/* ++**foo1: ++** ... ++** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value) ++foo1 (uint64_t *base, uint64x2_t offset, uint64x2_t value) + { +- vstrdq_scatter_shifted_offset (base, offset, value); ++ return vstrdq_scatter_shifted_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrd.64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (float16_t * addr, float16x8_t value) ++foo (float16_t *base, float16x8_t value) + { +- vstrhq_f16 (addr, value); ++ return vstrhq_f16 (base, value); + } + +-/* { dg-final { scan-assembler "vstrh.16" } } */ + ++/* ++**foo1: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (float16_t * addr, float16x8_t value) ++foo1 (float16_t *base, float16x8_t value) + { +- vstrhq (addr, value); ++ return vstrhq (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrh.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (float16_t * addr, float16x8_t value, mve_pred16_t p) ++foo (float16_t *base, float16x8_t value, mve_pred16_t p) + { +- vstrhq_p_f16 (addr, value, p); ++ return vstrhq_p_f16 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (float16_t * addr, float16x8_t value, mve_pred16_t p) ++foo1 (float16_t *base, float16x8_t value, mve_pred16_t p) + { +- vstrhq_p (addr, value, p); ++ return vstrhq_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int16_t * addr, int16x8_t value, mve_pred16_t p) ++foo (int16_t *base, int16x8_t value, mve_pred16_t p) + { +- vstrhq_p_s16 (addr, value, p); ++ return vstrhq_p_s16 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int16_t * addr, int16x8_t value, mve_pred16_t p) ++foo1 (int16_t *base, int16x8_t value, mve_pred16_t p) + { +- vstrhq_p (addr, value, p); ++ return vstrhq_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int16_t * addr, int32x4_t value, mve_pred16_t p) ++foo (int16_t *base, int32x4_t value, mve_pred16_t p) + { +- vstrhq_p_s32 (addr, value, p); ++ return vstrhq_p_s32 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int16_t * addr, int32x4_t value, mve_pred16_t p) ++foo1 (int16_t *base, int32x4_t value, mve_pred16_t p) + { +- vstrhq_p (addr, value, p); ++ return vstrhq_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint16_t * addr, uint16x8_t value, mve_pred16_t p) ++foo (uint16_t *base, uint16x8_t value, mve_pred16_t p) + { +- vstrhq_p_u16 (addr, value, p); ++ return vstrhq_p_u16 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint16_t * addr, uint16x8_t value, mve_pred16_t p) ++foo1 (uint16_t *base, uint16x8_t value, mve_pred16_t p) + { +- vstrhq_p (addr, value, p); ++ return vstrhq_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint16_t * addr, uint32x4_t value, mve_pred16_t p) ++foo (uint16_t *base, uint32x4_t value, mve_pred16_t p) + { +- vstrhq_p_u32 (addr, value, p); ++ return vstrhq_p_u32 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint16_t * addr, uint32x4_t value, mve_pred16_t p) ++foo1 (uint16_t *base, uint32x4_t value, mve_pred16_t p) + { +- vstrhq_p (addr, value, p); ++ return vstrhq_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int16_t * addr, int16x8_t value) ++foo (int16_t *base, int16x8_t value) + { +- vstrhq_s16 (addr, value); ++ return vstrhq_s16 (base, value); + } + +-/* { dg-final { scan-assembler "vstrh.16" } } */ + ++/* ++**foo1: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int16_t * addr, int16x8_t value) ++foo1 (int16_t *base, int16x8_t value) + { +- vstrhq (addr, value); ++ return vstrhq (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrh.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int16_t * addr, int32x4_t value) ++foo (int16_t *base, int32x4_t value) + { +- vstrhq_s32 (addr, value); ++ return vstrhq_s32 (base, value); + } + +-/* { dg-final { scan-assembler "vstrh.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int16_t * addr, int32x4_t value) ++foo1 (int16_t *base, int32x4_t value) + { +- vstrhq (addr, value); ++ return vstrhq (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrh.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (float16_t * base, uint16x8_t offset, float16x8_t value) ++foo (float16_t *base, uint16x8_t offset, float16x8_t value) + { +- vstrhq_scatter_offset_f16 (base, offset, value); ++ return vstrhq_scatter_offset_f16 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrh.16" } } */ + ++/* ++**foo1: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (float16_t * base, uint16x8_t offset, float16x8_t value) ++foo1 (float16_t *base, uint16x8_t offset, float16x8_t value) + { +- vstrhq_scatter_offset (base, offset, value); ++ return vstrhq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrh.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p) ++foo (float16_t *base, uint16x8_t offset, float16x8_t value, mve_pred16_t p) + { +- vstrhq_scatter_offset_p_f16 (base, offset, value, p); ++ return vstrhq_scatter_offset_p_f16 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p) ++foo1 (float16_t *base, uint16x8_t offset, float16x8_t value, mve_pred16_t p) + { +- vstrhq_scatter_offset_p (base, offset, value, p); ++ return vstrhq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) ++foo (int16_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) + { +- vstrhq_scatter_offset_p_s16 (base, offset, value, p); ++ return vstrhq_scatter_offset_p_s16 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) ++foo1 (int16_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) + { +- vstrhq_scatter_offset_p (base, offset, value, p); ++ return vstrhq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) ++foo (int16_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) + { +- vstrhq_scatter_offset_p_s32 (base, offset, value, p); ++ return vstrhq_scatter_offset_p_s32 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) ++foo1 (int16_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) + { +- vstrhq_scatter_offset_p (base, offset, value, p); ++ return vstrhq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) ++foo (uint16_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) + { +- vstrhq_scatter_offset_p_u16 (base, offset, value, p); ++ return vstrhq_scatter_offset_p_u16 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) ++foo1 (uint16_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) + { +- vstrhq_scatter_offset_p (base, offset, value, p); ++ return vstrhq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) ++foo (uint16_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) + { +- vstrhq_scatter_offset_p_u32 (base, offset, value, p); ++ return vstrhq_scatter_offset_p_u32 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) ++foo1 (uint16_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) + { +- vstrhq_scatter_offset_p (base, offset, value, p); ++ return vstrhq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (int16_t * base, uint16x8_t offset, int16x8_t value) ++foo (int16_t *base, uint16x8_t offset, int16x8_t value) + { +- vstrhq_scatter_offset_s16 (base, offset, value); ++ return vstrhq_scatter_offset_s16 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrh.16" } } */ + ++/* ++**foo1: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (int16_t * base, uint16x8_t offset, int16x8_t value) ++foo1 (int16_t *base, uint16x8_t offset, int16x8_t value) + { +- vstrhq_scatter_offset (base, offset, value); ++ return vstrhq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrh.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (int16_t * base, uint32x4_t offset, int32x4_t value) ++foo (int16_t *base, uint32x4_t offset, int32x4_t value) + { +- vstrhq_scatter_offset_s32 (base, offset, value); ++ return vstrhq_scatter_offset_s32 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrh.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (int16_t * base, uint32x4_t offset, int32x4_t value) ++foo1 (int16_t *base, uint32x4_t offset, int32x4_t value) + { +- vstrhq_scatter_offset (base, offset, value); ++ return vstrhq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrh.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint16_t * base, uint16x8_t offset, uint16x8_t value) ++foo (uint16_t *base, uint16x8_t offset, uint16x8_t value) + { +- vstrhq_scatter_offset_u16 (base, offset, value); ++ return vstrhq_scatter_offset_u16 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrh.16" } } */ + ++/* ++**foo1: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value) ++foo1 (uint16_t *base, uint16x8_t offset, uint16x8_t value) + { +- vstrhq_scatter_offset (base, offset, value); ++ return vstrhq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrh.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint16_t * base, uint32x4_t offset, uint32x4_t value) ++foo (uint16_t *base, uint32x4_t offset, uint32x4_t value) + { +- vstrhq_scatter_offset_u32 (base, offset, value); ++ return vstrhq_scatter_offset_u32 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrh.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value) ++foo1 (uint16_t *base, uint32x4_t offset, uint32x4_t value) + { +- vstrhq_scatter_offset (base, offset, value); ++ return vstrhq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrh.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo (float16_t * base, uint16x8_t offset, float16x8_t value) ++foo (float16_t *base, uint16x8_t offset, float16x8_t value) + { +- vstrhq_scatter_shifted_offset_f16 (base, offset, value); ++ return vstrhq_scatter_shifted_offset_f16 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrh.16" } } */ + ++/* ++**foo1: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo1 (float16_t * base, uint16x8_t offset, float16x8_t value) ++foo1 (float16_t *base, uint16x8_t offset, float16x8_t value) + { +- vstrhq_scatter_shifted_offset (base, offset, value); ++ return vstrhq_scatter_shifted_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrh.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p) ++foo (float16_t *base, uint16x8_t offset, float16x8_t value, mve_pred16_t p) + { +- vstrhq_scatter_shifted_offset_p_f16 (base, offset, value, p); ++ return vstrhq_scatter_shifted_offset_p_f16 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo1 (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p) ++foo1 (float16_t *base, uint16x8_t offset, float16x8_t value, mve_pred16_t p) + { +- vstrhq_scatter_shifted_offset_p (base, offset, value, p); ++ return vstrhq_scatter_shifted_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) ++foo (int16_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) + { +- vstrhq_scatter_shifted_offset_p_s16 (base, offset, value, p); ++ return vstrhq_scatter_shifted_offset_p_s16 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo1 (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) ++foo1 (int16_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) + { +- vstrhq_scatter_shifted_offset_p (base, offset, value, p); ++ return vstrhq_scatter_shifted_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) ++foo (int16_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) + { +- vstrhq_scatter_shifted_offset_p_s32 (base, offset, value, p); ++ return vstrhq_scatter_shifted_offset_p_s32 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo1 (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) ++foo1 (int16_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) + { +- vstrhq_scatter_shifted_offset_p (base, offset, value, p); ++ return vstrhq_scatter_shifted_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) ++foo (uint16_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) + { +- vstrhq_scatter_shifted_offset_p_u16 (base, offset, value, p); ++ return vstrhq_scatter_shifted_offset_p_u16 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) ++foo1 (uint16_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) + { +- vstrhq_scatter_shifted_offset_p (base, offset, value, p); ++ return vstrhq_scatter_shifted_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) ++foo (uint16_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) + { +- vstrhq_scatter_shifted_offset_p_u32 (base, offset, value, p); ++ return vstrhq_scatter_shifted_offset_p_u32 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) ++foo1 (uint16_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) + { +- vstrhq_scatter_shifted_offset_p (base, offset, value, p); ++ return vstrhq_scatter_shifted_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo (int16_t * base, uint16x8_t offset, int16x8_t value) ++foo (int16_t *base, uint16x8_t offset, int16x8_t value) + { +- vstrhq_scatter_shifted_offset_s16 (base, offset, value); ++ return vstrhq_scatter_shifted_offset_s16 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrh.16" } } */ + ++/* ++**foo1: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo1 (int16_t * base, uint16x8_t offset, int16x8_t value) ++foo1 (int16_t *base, uint16x8_t offset, int16x8_t value) + { +- vstrhq_scatter_shifted_offset (base, offset, value); ++ return vstrhq_scatter_shifted_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrh.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo (int16_t * base, uint32x4_t offset, int32x4_t value) ++foo (int16_t *base, uint32x4_t offset, int32x4_t value) + { +- vstrhq_scatter_shifted_offset_s32 (base, offset, value); ++ return vstrhq_scatter_shifted_offset_s32 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrh.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo1 (int16_t * base, uint32x4_t offset, int32x4_t value) ++foo1 (int16_t *base, uint32x4_t offset, int32x4_t value) + { +- vstrhq_scatter_shifted_offset (base, offset, value); ++ return vstrhq_scatter_shifted_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrh.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo (uint16_t * base, uint16x8_t offset, uint16x8_t value) ++foo (uint16_t *base, uint16x8_t offset, uint16x8_t value) + { +- vstrhq_scatter_shifted_offset_u16 (base, offset, value); ++ return vstrhq_scatter_shifted_offset_u16 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrh.16" } } */ + ++/* ++**foo1: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value) ++foo1 (uint16_t *base, uint16x8_t offset, uint16x8_t value) + { +- vstrhq_scatter_shifted_offset (base, offset, value); ++ return vstrhq_scatter_shifted_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrh.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo (uint16_t * base, uint32x4_t offset, uint32x4_t value) ++foo (uint16_t *base, uint32x4_t offset, uint32x4_t value) + { +- vstrhq_scatter_shifted_offset_u32 (base, offset, value); ++ return vstrhq_scatter_shifted_offset_u32 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrh.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value) ++foo1 (uint16_t *base, uint32x4_t offset, uint32x4_t value) + { +- vstrhq_scatter_shifted_offset (base, offset, value); ++ return vstrhq_scatter_shifted_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrh.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint16_t * addr, uint16x8_t value) ++foo (uint16_t *base, uint16x8_t value) + { +- vstrhq_u16 (addr, value); ++ return vstrhq_u16 (base, value); + } + +-/* { dg-final { scan-assembler "vstrh.16" } } */ + ++/* ++**foo1: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint16_t * addr, uint16x8_t value) ++foo1 (uint16_t *base, uint16x8_t value) + { +- vstrhq (addr, value); ++ return vstrhq (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrh.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint16_t * addr, uint32x4_t value) ++foo (uint16_t *base, uint32x4_t value) + { +- vstrhq_u32 (addr, value); ++ return vstrhq_u32 (base, value); + } + +-/* { dg-final { scan-assembler "vstrh.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint16_t * addr, uint32x4_t value) ++foo1 (uint16_t *base, uint32x4_t value) + { +- vstrhq (addr, value); ++ return vstrhq (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrh.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (float32_t * addr, float32x4_t value) ++foo (float32_t *base, float32x4_t value) + { +- vstrwq_f32 (addr, value); ++ return vstrwq_f32 (base, value); + } + +-/* { dg-final { scan-assembler "vstrw.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (float32_t * addr, float32x4_t value) ++foo1 (float32_t *base, float32x4_t value) + { +- vstrwq (addr, value); ++ return vstrwq (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrw.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (float32_t * addr, float32x4_t value, mve_pred16_t p) ++foo (float32_t *base, float32x4_t value, mve_pred16_t p) + { +- vstrwq_p_f32 (addr, value, p); ++ return vstrwq_p_f32 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (float32_t * addr, float32x4_t value, mve_pred16_t p) ++foo1 (float32_t *base, float32x4_t value, mve_pred16_t p) + { +- vstrwq_p (addr, value, p); ++ return vstrwq_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int32_t * addr, int32x4_t value, mve_pred16_t p) ++foo (int32_t *base, int32x4_t value, mve_pred16_t p) + { +- vstrwq_p_s32 (addr, value, p); ++ return vstrwq_p_s32 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int32_t * addr, int32x4_t value, mve_pred16_t p) ++foo1 (int32_t *base, int32x4_t value, mve_pred16_t p) + { +- vstrwq_p (addr, value, p); ++ return vstrwq_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint32_t * addr, uint32x4_t value, mve_pred16_t p) ++foo (uint32_t *base, uint32x4_t value, mve_pred16_t p) + { +- vstrwq_p_u32 (addr, value, p); ++ return vstrwq_p_u32 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint32_t * addr, uint32x4_t value, mve_pred16_t p) ++foo1 (uint32_t *base, uint32x4_t value, mve_pred16_t p) + { +- vstrwq_p (addr, value, p); ++ return vstrwq_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int32_t * addr, int32x4_t value) ++foo (int32_t *base, int32x4_t value) + { +- vstrwq_s32 (addr, value); ++ return vstrwq_s32 (base, value); + } + +-/* { dg-final { scan-assembler "vstrw.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int32_t * addr, int32x4_t value) ++foo1 (int32_t *base, int32x4_t value) + { +- vstrwq (addr, value); ++ return vstrwq (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrw.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void + foo (uint32x4_t addr, float32x4_t value) + { +- vstrwq_scatter_base_f32 (addr, 8, value); ++ return vstrwq_scatter_base_f32 (addr, 0, value); + } + +-/* { dg-final { scan-assembler "vstrw.u32" } } */ + ++/* ++**foo1: ++** ... ++** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void + foo1 (uint32x4_t addr, float32x4_t value) + { +- vstrwq_scatter_base (addr, 8, value); ++ return vstrwq_scatter_base (addr, 0, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrw.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void + foo (uint32x4_t addr, float32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_base_p_f32 (addr, 8, value, p); ++ return vstrwq_scatter_base_p_f32 (addr, 0, value, p); + } + +-/* { dg-final { scan-assembler "vstrwt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void + foo1 (uint32x4_t addr, float32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_base_p (addr, 8, value, p); ++ return vstrwq_scatter_base_p (addr, 0, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrwt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void + foo (uint32x4_t addr, int32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_base_p_s32 (addr, 8, value, p); ++ return vstrwq_scatter_base_p_s32 (addr, 0, value, p); + } + +-/* { dg-final { scan-assembler "vstrwt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void + foo1 (uint32x4_t addr, int32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_base_p (addr, 8, value, p); ++ return vstrwq_scatter_base_p (addr, 0, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrwt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void + foo (uint32x4_t addr, uint32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_base_p_u32 (addr, 8, value, p); ++ return vstrwq_scatter_base_p_u32 (addr, 0, value, p); + } + +-/* { dg-final { scan-assembler "vstrwt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void + foo1 (uint32x4_t addr, uint32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_base_p (addr, 8, value, p); ++ return vstrwq_scatter_base_p (addr, 0, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrwt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void + foo (uint32x4_t addr, int32x4_t value) + { +- vstrwq_scatter_base_s32 (addr, 8, value); ++ return vstrwq_scatter_base_s32 (addr, 0, value); + } + +-/* { dg-final { scan-assembler "vstrw.u32" } } */ + ++/* ++**foo1: ++** ... ++** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void + foo1 (uint32x4_t addr, int32x4_t value) + { +- vstrwq_scatter_base (addr, 8, value); ++ return vstrwq_scatter_base (addr, 0, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrw.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void + foo (uint32x4_t addr, uint32x4_t value) + { +- vstrwq_scatter_base_u32 (addr, 8, value); ++ return vstrwq_scatter_base_u32 (addr, 0, value); + } + +-/* { dg-final { scan-assembler "vstrw.u32" } } */ + ++/* ++**foo1: ++** ... ++** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void + foo1 (uint32x4_t addr, uint32x4_t value) + { +- vstrwq_scatter_base (addr, 8, value); ++ return vstrwq_scatter_base (addr, 0, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrw.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c +@@ -1,19 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo (uint32x4_t * addr, const int offset, float32x4_t value) ++foo (uint32x4_t *addr, float32x4_t value) + { +- vstrwq_scatter_base_wb_f32 (addr, 8, value); ++ return vstrwq_scatter_base_wb_f32 (addr, 0, value); + } + ++ ++/* ++**foo1: ++** ... ++** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo1 (uint32x4_t * addr, const int offset, float32x4_t value) ++foo1 (uint32x4_t *addr, float32x4_t value) + { +- vstrwq_scatter_base_wb (addr, 8, value); ++ return vstrwq_scatter_base_wb (addr, 0, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c +@@ -1,19 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo (uint32x4_t * addr, const int offset, float32x4_t value, mve_pred16_t p) ++foo (uint32x4_t *addr, float32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_base_wb_p_f32 (addr, 8, value, p); ++ return vstrwq_scatter_base_wb_p_f32 (addr, 0, value, p); + } + ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo1 (uint32x4_t * addr, const int offset, float32x4_t value, mve_pred16_t p) ++foo1 (uint32x4_t *addr, float32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_base_wb_p (addr, 8, value, p); ++ return vstrwq_scatter_base_wb_p (addr, 0, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c +@@ -1,19 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo (uint32x4_t * addr, const int offset, int32x4_t value, mve_pred16_t p) ++foo (uint32x4_t *addr, int32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_base_wb_p_s32 (addr, 8, value, p); ++ return vstrwq_scatter_base_wb_p_s32 (addr, 0, value, p); + } + ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo1 (uint32x4_t * addr, const int offset, int32x4_t value, mve_pred16_t p) ++foo1 (uint32x4_t *addr, int32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_base_wb_p (addr, 8, value, p); ++ return vstrwq_scatter_base_wb_p (addr, 0, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c +@@ -1,19 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo (uint32x4_t * addr, const int offset, uint32x4_t value, mve_pred16_t p) ++foo (uint32x4_t *addr, uint32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_base_wb_p_u32 (addr, 8, value, p); ++ return vstrwq_scatter_base_wb_p_u32 (addr, 0, value, p); + } + ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo1 (uint32x4_t * addr, const int offset, uint32x4_t value, mve_pred16_t p) ++foo1 (uint32x4_t *addr, uint32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_base_wb_p (addr, 8, value, p); ++ return vstrwq_scatter_base_wb_p (addr, 0, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c +@@ -1,19 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo (uint32x4_t * addr, const int offset, int32x4_t value) ++foo (uint32x4_t *addr, int32x4_t value) + { +- vstrwq_scatter_base_wb_s32 (addr, 8, value); ++ return vstrwq_scatter_base_wb_s32 (addr, 0, value); + } + ++ ++/* ++**foo1: ++** ... ++** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo1 (uint32x4_t * addr, const int offset, int32x4_t value) ++foo1 (uint32x4_t *addr, int32x4_t value) + { +- vstrwq_scatter_base_wb (addr, 8, value); ++ return vstrwq_scatter_base_wb (addr, 0, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c +@@ -1,19 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo (uint32x4_t * addr, uint32x4_t value) ++foo (uint32x4_t *addr, uint32x4_t value) + { +- vstrwq_scatter_base_wb_u32 (addr, 8, value); ++ return vstrwq_scatter_base_wb_u32 (addr, 0, value); + } + ++ ++/* ++**foo1: ++** ... ++** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo1 (uint32x4_t * addr, uint32x4_t value) ++foo1 (uint32x4_t *addr, uint32x4_t value) + { +- vstrwq_scatter_base_wb (addr, 8, value); ++ return vstrwq_scatter_base_wb (addr, 0, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (float32_t * base, uint32x4_t offset, float32x4_t value) ++foo (float32_t *base, uint32x4_t offset, float32x4_t value) + { +- vstrwq_scatter_offset_f32 (base, offset, value); ++ return vstrwq_scatter_offset_f32 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrw.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (float32_t * base, uint32x4_t offset, float32x4_t value) ++foo1 (float32_t *base, uint32x4_t offset, float32x4_t value) + { +- vstrwq_scatter_offset (base, offset, value); ++ return vstrwq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrw.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) ++foo (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_offset_p_f32 (base, offset, value, p); ++ return vstrwq_scatter_offset_p_f32 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) ++foo1 (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_offset_p (base, offset, value, p); ++ return vstrwq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) ++foo (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_offset_p_s32 (base, offset, value, p); ++ return vstrwq_scatter_offset_p_s32 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) ++foo1 (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_offset_p (base, offset, value, p); ++ return vstrwq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) ++foo (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_offset_p_u32 (base, offset, value, p); ++ return vstrwq_scatter_offset_p_u32 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) ++foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_offset_p (base, offset, value, p); ++ return vstrwq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (int32_t * base, uint32x4_t offset, int32x4_t value) ++foo (int32_t *base, uint32x4_t offset, int32x4_t value) + { +- vstrwq_scatter_offset_s32 (base, offset, value); ++ return vstrwq_scatter_offset_s32 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrw.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (int32_t * base, uint32x4_t offset, int32x4_t value) ++foo1 (int32_t *base, uint32x4_t offset, int32x4_t value) + { +- vstrwq_scatter_offset (base, offset, value); ++ return vstrwq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrw.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint32_t * base, uint32x4_t offset, uint32x4_t value) ++foo (uint32_t *base, uint32x4_t offset, uint32x4_t value) + { +- vstrwq_scatter_offset_u32 (base, offset, value); ++ return vstrwq_scatter_offset_u32 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrw.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value) ++foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value) + { +- vstrwq_scatter_offset (base, offset, value); ++ return vstrwq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrw.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + void +-foo (float32_t * base, uint32x4_t offset, float32x4_t value) ++foo (float32_t *base, uint32x4_t offset, float32x4_t value) + { +- vstrwq_scatter_shifted_offset_f32 (base, offset, value); ++ return vstrwq_scatter_shifted_offset_f32 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrw.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + void +-foo1 (float32_t * base, uint32x4_t offset, float32x4_t value) ++foo1 (float32_t *base, uint32x4_t offset, float32x4_t value) + { +- vstrwq_scatter_shifted_offset (base, offset, value); ++ return vstrwq_scatter_shifted_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrw.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + void +-foo (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) ++foo (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_shifted_offset_p_f32 (base, offset, value, p); ++ return vstrwq_scatter_shifted_offset_p_f32 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + void +-foo1 (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) ++foo1 (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_shifted_offset_p (base, offset, value, p); ++ return vstrwq_scatter_shifted_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + void +-foo (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) ++foo (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_shifted_offset_p_s32 (base, offset, value, p); ++ return vstrwq_scatter_shifted_offset_p_s32 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + void +-foo1 (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) ++foo1 (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_shifted_offset_p (base, offset, value, p); ++ return vstrwq_scatter_shifted_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + void +-foo (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) ++foo (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_shifted_offset_p_u32 (base, offset, value, p); ++ return vstrwq_scatter_shifted_offset_p_u32 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) ++foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_shifted_offset_p (base, offset, value, p); ++ return vstrwq_scatter_shifted_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + void +-foo (int32_t * base, uint32x4_t offset, int32x4_t value) ++foo (int32_t *base, uint32x4_t offset, int32x4_t value) + { +- vstrwq_scatter_shifted_offset_s32 (base, offset, value); ++ return vstrwq_scatter_shifted_offset_s32 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrw.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + void +-foo1 (int32_t * base, uint32x4_t offset, int32x4_t value) ++foo1 (int32_t *base, uint32x4_t offset, int32x4_t value) + { +- vstrwq_scatter_shifted_offset (base, offset, value); ++ return vstrwq_scatter_shifted_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrw.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + void +-foo (uint32_t * base, uint32x4_t offset, uint32x4_t value) ++foo (uint32_t *base, uint32x4_t offset, uint32x4_t value) + { +- vstrwq_scatter_shifted_offset_u32 (base, offset, value); ++ return vstrwq_scatter_shifted_offset_u32 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrw.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value) ++foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value) + { +- vstrwq_scatter_shifted_offset (base, offset, value); ++ return vstrwq_scatter_shifted_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrw.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint32_t * addr, uint32x4_t value) ++foo (uint32_t *base, uint32x4_t value) + { +- vstrwq_u32 (addr, value); ++ return vstrwq_u32 (base, value); + } + +-/* { dg-final { scan-assembler "vstrw.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint32_t * addr, uint32x4_t value) ++foo1 (uint32_t *base, uint32x4_t value) + { +- vstrwq (addr, value); ++ return vstrwq (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrw.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p) +-{ +- return vsubq_m (inactive, a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p) +-{ +- return vsubq_m (inactive, a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo1 (float16x8_t a, float16_t b) +-{ +- return vsubq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo1 (float32x4_t a, float32_t b) +-{ +- return vsubq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16-1.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo (float16x8_t a, float16_t b, mve_pred16_t p) +-{ +- return vsubq_x_n_f16 (a, 23.23, p); +-} +- +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +deleted file mode 100644 +--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32-1.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo (float32x4_t a, float32_t b, mve_pred16_t p) +-{ +- return vsubq_x_n_f32 (a, 23.23, p); +-} +- +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/arm/mve/mve_const_shifts.c +@@ -0,0 +1,41 @@ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ ++/* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++#include "arm_mve.h" ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo11: ++** ... ++** movs r0, #2 ++** ... ++*/ ++uint32_t ++foo11 () ++{ ++ return uqshl (1, 1); ++} ++ ++/* ++**foo12: ++** ... ++** movs r0, #2 ++** movs r1, #0 ++** ... ++*/ ++uint64_t ++foo12 () ++{ ++ return uqshll (1, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c +@@ -0,0 +1,67 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_mve_hw } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_1m_mve } */ ++ ++#include ++ ++volatile int32x4_t c1; ++volatile uint32x4_t c2; ++int *carry; ++ ++int ++main () ++{ ++ int32x4_t a1 = vcreateq_s32 (0, 0); ++ int32x4_t b1 = vcreateq_s32 (0, 0); ++ int32x4_t inactive1 = vcreateq_s32 (0, 0); ++ ++ uint32x4_t a2 = vcreateq_u32 (0, 0); ++ uint32x4_t b2 = vcreateq_u32 (0, 0); ++ uint32x4_t inactive2 = vcreateq_u32 (0, 0); ++ ++ mve_pred16_t p = 0xFFFF; ++ (*carry) = 0xFFFFFFFF; ++ ++ __builtin_arm_set_fpscr_nzcvqc (0); ++ c1 = vadcq (a1, b1, carry); ++ if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000) ++ __builtin_abort (); ++ (*carry) = 0xFFFFFFFF; ++ __builtin_arm_set_fpscr_nzcvqc (0); ++ c2 = vadcq (a2, b2, carry); ++ if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000) ++ __builtin_abort (); ++ (*carry) = 0xFFFFFFFF; ++ __builtin_arm_set_fpscr_nzcvqc (0); ++ c1 = vsbcq (a1, b1, carry); ++ if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000) ++ __builtin_abort (); ++ (*carry) = 0xFFFFFFFF; ++ __builtin_arm_set_fpscr_nzcvqc (0); ++ c2 = vsbcq (a2, b2, carry); ++ if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000) ++ __builtin_abort (); ++ (*carry) = 0xFFFFFFFF; ++ __builtin_arm_set_fpscr_nzcvqc (0); ++ c1 = vadcq_m (inactive1, a1, b1, carry, p); ++ if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000) ++ __builtin_abort (); ++ (*carry) = 0xFFFFFFFF; ++ __builtin_arm_set_fpscr_nzcvqc (0); ++ c2 = vadcq_m (inactive2, a2, b2, carry, p); ++ if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000) ++ __builtin_abort (); ++ (*carry) = 0xFFFFFFFF; ++ __builtin_arm_set_fpscr_nzcvqc (0); ++ c1 = vsbcq_m (inactive1, a1, b1, carry, p); ++ if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000) ++ __builtin_abort (); ++ (*carry) = 0xFFFFFFFF; ++ __builtin_arm_set_fpscr_nzcvqc (0); ++ c2 = vsbcq_m (inactive2, a2, b2, carry, p); ++ if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000) ++ __builtin_abort (); ++ ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c +@@ -7,9 +7,9 @@ + /* + ** test: + **... +-** vstrbt.8 q0, \[r0\] ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] + **... +-** vstrbt.8 q0, \[r0\] ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] + **... + */ + +--- a/src/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c +@@ -7,9 +7,9 @@ + /* + ** test: + **... +-** vstrht.32 q0, \[r0\] ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] + **... +-** vstrht.32 q0, \[r0\] ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] + **... + */ + +--- a/src/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c +@@ -7,9 +7,9 @@ + /* + ** test: + **... +-** vstrwt.32 q0, \[r0\] ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] + **... +-** vstrwt.32 q0, \[r0\] ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] + **... + */ + +--- a/src/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c +@@ -7,9 +7,9 @@ + /* + ** test: + **... +-** vstrwt.32 q0, \[r0\] ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] + **... +-** vstrwt.32 q0, \[r0\] ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] + **... + */ + +--- a/src/gcc/testsuite/gcc.target/arm/mve/pr108177-13-run.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-13-run.c +@@ -1,6 +1,6 @@ + /* { dg-do run } */ + /* { dg-require-effective-target arm_mve_hw } */ + /* { dg-options "-O2" } */ +-/* { dg-add-options arm_v8_1m_mve } */ ++/* { dg-add-options arm_v8_1m_mve_fp } */ + + #include "pr108177-13.c" +--- a/src/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c +@@ -7,9 +7,9 @@ + /* + ** test: + **... +-** vstrht.16 q0, \[r0\] ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] + **... +-** vstrht.16 q0, \[r0\] ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] + **... + */ + +--- a/src/gcc/testsuite/gcc.target/arm/mve/pr108177-14-run.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-14-run.c +@@ -1,6 +1,6 @@ + /* { dg-do run } */ + /* { dg-require-effective-target arm_mve_hw } */ + /* { dg-options "-O2" } */ +-/* { dg-add-options arm_v8_1m_mve } */ ++/* { dg-add-options arm_v8_1m_mve_fp } */ + + #include "pr108177-14.c" +--- a/src/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c +@@ -7,9 +7,9 @@ + /* + ** test: + **... +-** vstrwt.32 q0, \[r0\] ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] + **... +-** vstrwt.32 q0, \[r0\] ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] + **... + */ + +--- a/src/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c +@@ -7,9 +7,9 @@ + /* + ** test: + **... +-** vstrbt.8 q0, \[r0\] ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] + **... +-** vstrbt.8 q0, \[r0\] ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] + **... + */ + +--- a/src/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c +@@ -7,9 +7,9 @@ + /* + ** test: + **... +-** vstrbt.16 q0, \[r0\] ++** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] + **... +-** vstrbt.16 q0, \[r0\] ++** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] + **... + */ + +--- a/src/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c +@@ -7,9 +7,9 @@ + /* + ** test: + **... +-** vstrbt.16 q0, \[r0\] ++** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] + **... +-** vstrbt.16 q0, \[r0\] ++** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] + **... + */ + +--- a/src/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c +@@ -7,9 +7,9 @@ + /* + ** test: + **... +-** vstrbt.32 q0, \[r0\] ++** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] + **... +-** vstrbt.32 q0, \[r0\] ++** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] + **... + */ + +--- a/src/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c +@@ -7,9 +7,9 @@ + /* + ** test: + **... +-** vstrbt.32 q0, \[r0\] ++** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] + **... +-** vstrbt.32 q0, \[r0\] ++** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] + **... + */ + +--- a/src/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c +@@ -7,9 +7,9 @@ + /* + ** test: + **... +-** vstrht.16 q0, \[r0\] ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] + **... +-** vstrht.16 q0, \[r0\] ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] + **... + */ + +--- a/src/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c +@@ -7,9 +7,9 @@ + /* + ** test: + **... +-** vstrht.16 q0, \[r0\] ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] + **... +-** vstrht.16 q0, \[r0\] ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] + **... + */ + +--- a/src/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c ++++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c +@@ -7,9 +7,9 @@ + /* + ** test: + **... +-** vstrht.32 q0, \[r0\] ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] + **... +-** vstrht.32 q0, \[r0\] ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] + **... + */ + +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/arm/pr109939.c +@@ -0,0 +1,14 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_sat_ok } */ ++/* { dg-add-options arm_sat } */ ++/* { dg-additional-options "-O -Wall -Wconversion" } */ ++ ++#include ++ ++int dbg_ssat_out; ++int dbg_ssat_in; ++ ++void test_arm_ssat(void) ++{ ++ dbg_ssat_out = __ssat(dbg_ssat_in, 16); ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/arm/pure-code/pr109800.c +@@ -0,0 +1,4 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_hard_ok } */ ++/* { dg-options "-O2 -march=armv7-m -mfloat-abi=hard -mfpu=fpv4-sp-d16 -mbig-endian -mpure-code" } */ ++double f() { return 5.0; } +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/avr/pr82931.c +@@ -0,0 +1,29 @@ ++/* { dg-options "-Os" } */ ++/* { dg-final { scan-assembler-times "bst" 4 } } */ ++/* { dg-final { scan-assembler-times "bld" 4 } } */ ++ ++typedef __UINT8_TYPE__ uint8_t; ++typedef __UINT16_TYPE__ uint16_t; ++ ++#define BitMask (1u << 14) ++#define Bit8Mask ((uint8_t) (1u << 4)) ++ ++void merge1_8 (uint8_t *dst, const uint8_t *src) ++{ ++ *dst = (*src & Bit8Mask) | (*dst & ~ Bit8Mask); ++} ++ ++void merge2_8 (uint8_t *dst, const uint8_t *src) ++{ ++ *dst ^= (*dst ^ *src) & Bit8Mask; ++} ++ ++void merge1_16 (uint16_t *dst, const uint16_t *src) ++{ ++ *dst = (*src & BitMask) | (*dst & ~ BitMask); ++} ++ ++void merge2_16 (uint16_t *dst, const uint16_t *src) ++{ ++ *dst ^= (*dst ^ *src) & BitMask; ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/avr/torture/pr105753.c +@@ -0,0 +1,13 @@ ++int digit_sum (unsigned long n) ++{ ++ int sum = 0; ++ ++ do ++ { ++ int x = n % 10; ++ n /= 10; ++ sum += x; ++ } while(n); ++ ++ return sum; ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/avr/torture/pr109650-1.c +@@ -0,0 +1,63 @@ ++/* { dg-do run } */ ++/* { dg-options { -std=c99 } } */ ++ ++typedef _Bool bool; ++typedef __UINT8_TYPE__ uint8_t; ++ ++static inline __attribute__((__always_inline__)) ++bool func1a (bool p1, uint8_t p2) ++{ ++ if (p1) ++ return p2 <= 8; ++ return p2 <= 2; ++} ++ ++__attribute__((__noinline__, __noclone__)) ++bool func1b (bool p1, uint8_t p2) ++{ ++ return func1a (p1, p2); ++} ++ ++static inline __attribute__((__always_inline__)) ++bool func2a (bool p1, unsigned p2) ++{ ++ if (p1) ++ return p2 <= 8; ++ return p2 <= 2; ++} ++ ++__attribute__((__noinline__, __noclone__)) ++bool func2b (bool p1, unsigned p2) ++{ ++ return func2a (p1, p2); ++} ++ ++void test1 (void) ++{ ++ if (func1a (0, 1) != func1b (0, 1)) __builtin_abort(); ++ if (func1a (0, 2) != func1b (0, 2)) __builtin_abort(); ++ if (func1a (0, 3) != func1b (0, 3)) __builtin_abort(); ++ ++ if (func1a (1, 7) != func1b (1, 7)) __builtin_abort(); ++ if (func1a (1, 8) != func1b (1, 8)) __builtin_abort(); ++ if (func1a (1, 9) != func1b (1, 9)) __builtin_abort(); ++} ++ ++void test2 (void) ++{ ++ if (func2a (0, 1) != func2b (0, 1)) __builtin_abort(); ++ if (func2a (0, 2) != func2b (0, 2)) __builtin_abort(); ++ if (func2a (0, 3) != func2b (0, 3)) __builtin_abort(); ++ ++ if (func2a (1, 7) != func2b (1, 7)) __builtin_abort(); ++ if (func2a (1, 8) != func2b (1, 8)) __builtin_abort(); ++ if (func2a (1, 9) != func2b (1, 9)) __builtin_abort(); ++} ++ ++int main (void) ++{ ++ test1(); ++ test2(); ++ ++ __builtin_exit (0); ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/avr/torture/pr109650-2.c +@@ -0,0 +1,79 @@ ++/* { dg-do run } */ ++ ++typedef __UINT8_TYPE__ uint8_t; ++ ++#define AI static __inline__ __attribute__((__always_inline__)) ++#define NI __attribute__((__noinline__,__noclone__)) ++ ++AI uint8_t func1_eq (uint8_t c, unsigned x) ++{ ++ if (x == c) ++ return 1; ++ return 0; ++} ++ ++AI uint8_t func1_ne (uint8_t c, unsigned x) ++{ ++ if (x != c) ++ return 1; ++ return 0; ++} ++ ++AI uint8_t func1_ltu (uint8_t c, unsigned x) ++{ ++ if (x < c) ++ return 1; ++ return 0; ++} ++ ++AI uint8_t func1_leu (uint8_t c, unsigned x) ++{ ++ if (x <= c) ++ return 1; ++ return 0; ++} ++ ++AI uint8_t func1_gtu (uint8_t c, unsigned x) ++{ ++ if (x > c) ++ return 1; ++ return 0; ++} ++ ++AI uint8_t func1_geu (uint8_t c, unsigned x) ++{ ++ if (x >= c) ++ return 1; ++ return 0; ++} ++ ++NI uint8_t func2_eq (uint8_t c, unsigned x) { return func1_eq (c, x); } ++NI uint8_t func2_ne (uint8_t c, unsigned x) { return func1_ne (c, x); } ++NI uint8_t func2_ltu (uint8_t c, unsigned x) { return func1_ltu (c, x); } ++NI uint8_t func2_leu (uint8_t c, unsigned x) { return func1_leu (c, x); } ++NI uint8_t func2_gtu (uint8_t c, unsigned x) { return func1_gtu (c, x); } ++NI uint8_t func2_geu (uint8_t c, unsigned x) { return func1_geu (c, x); } ++ ++AI void test4 (uint8_t c, unsigned x) ++{ ++ if (func2_eq (c, x) != func1_eq (c, x)) __builtin_abort(); ++ if (func2_ne (c, x) != func1_ne (c, x)) __builtin_abort(); ++ if (func2_ltu (c, x) != func1_ltu (c, x)) __builtin_abort(); ++ if (func2_leu (c, x) != func1_leu (c, x)) __builtin_abort(); ++ if (func2_gtu (c, x) != func1_gtu (c, x)) __builtin_abort(); ++ if (func2_geu (c, x) != func1_geu (c, x)) __builtin_abort(); ++} ++ ++int main (void) ++{ ++ test4 (127, 127); ++ test4 (127, 128); ++ test4 (128, 127); ++ ++ test4 (0x42, 0x142); ++ test4 (0x0, 0x100); ++ test4 (0x0, 0x0); ++ test4 (0x0, 0x1); ++ ++ __builtin_exit (0); ++} +--- a/src/gcc/testsuite/gcc.target/gcn/fpdiv.c ++++ b/src/gcc/testsuite/gcc.target/gcn/fpdiv.c +@@ -1,5 +1,4 @@ + /* { dg-do run } */ +-/* { dg-options "-ffast-math" } */ + + #include + #include +--- a/src/gcc/testsuite/gcc.target/i386/avx-vzeroupper-12.c ++++ b/src/gcc/testsuite/gcc.target/i386/avx-vzeroupper-12.c +@@ -16,5 +16,6 @@ foo () + _mm256_zeroupper (); + } + +-/* { dg-final { scan-assembler-times "avx_vzeroupper" 4 } } */ ++/* { dg-final { scan-assembler-times "avx_vzeroupper" 4 { target ia32 } } } */ ++/* { dg-final { scan-assembler-times "avx_vzeroupper" 5 { target { ! ia32 } } } } */ + /* { dg-final { scan-assembler-times "\\*avx_vzeroall" 1 } } */ +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/i386/avx-vzeroupper-29.c +@@ -0,0 +1,14 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O0 -mavx -mtune=generic -mvzeroupper -dp" } */ ++ ++#include ++ ++extern __m256 x, y; ++ ++void ++foo () ++{ ++ x = y; ++} ++ ++/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/i386/avx-vzeroupper-7.c ++++ b/src/gcc/testsuite/gcc.target/i386/avx-vzeroupper-7.c +@@ -12,4 +12,5 @@ foo () + _mm256_zeroupper (); + } + +-/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 } } */ ++/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 { target ia32 } } } */ ++/* { dg-final { scan-assembler-times "avx_vzeroupper" 2 { target { ! ia32 } } } } */ +--- a/src/gcc/testsuite/gcc.target/i386/avx-vzeroupper-9.c ++++ b/src/gcc/testsuite/gcc.target/i386/avx-vzeroupper-9.c +@@ -15,4 +15,5 @@ foo () + _mm256_zeroupper (); + } + +-/* { dg-final { scan-assembler-times "avx_vzeroupper" 4 } } */ ++/* { dg-final { scan-assembler-times "avx_vzeroupper" 4 { target ia32 } } } */ ++/* { dg-final { scan-assembler-times "avx_vzeroupper" 5 { target { ! ia32 } } } } */ +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/i386/bf16_short_warn.c +@@ -0,0 +1,17 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ ++ ++#include ++typedef struct { ++short payload; ++} BFloat16; ++ ++__attribute__((target("avx512vl,avx512bf16"))) ++BFloat16 tobf16_avx512(float f) ++{ ++ BFloat16 r; ++ __m128bh m = _mm_cvtneps_pbh(_mm_set_ss(f)); ++ r.payload = m[0]; /* { dg-warning " be careful of implicit conversion between '__bf16' and 'short'" } */ ++ return r; ++} ++ +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/i386/mvc17.c +@@ -0,0 +1,11 @@ ++/* { dg-do compile } */ ++/* { dg-require-ifunc "" } */ ++/* { dg-options "-O2 -march=x86-64" } */ ++/* { dg-final { scan-assembler-times "rep mov" 1 } } */ ++ ++__attribute__((target_clones("default","arch=icelake-server"))) ++void ++foo (char *a, char *b, int size) ++{ ++ __builtin_memcpy (a, b, size & 0x7F); ++} +--- a/src/gcc/testsuite/gcc.target/i386/pr104610.c ++++ b/src/gcc/testsuite/gcc.target/i386/pr104610.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-O2 -mavx -mmove-max=256 -mstore-max=256" } */ ++/* { dg-options "-O2 -mavx -mmove-max=256 -mstore-max=256 -fno-stack-protector" } */ + /* { dg-final { scan-assembler-times {(?n)vptest.*ymm} 1 } } */ + /* { dg-final { scan-assembler-times {sete} 1 } } */ + /* { dg-final { scan-assembler-not {(?n)je.*L[0-9]} } } */ +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/i386/pr110108-2.c +@@ -0,0 +1,14 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mavx2 -O2 -funsigned-char" } */ ++/* { dg-final { scan-assembler-times "vpblendvb" 2 } } */ ++ ++#include ++__m128i do_stuff_128(__m128i X0, __m128i X1, __m128i X2) { ++ __m128i Result = _mm_blendv_epi8(X0, X1, X2); ++ return Result; ++} ++ ++__m256i do_stuff_256(__m256i X0, __m256i X1, __m256i X2) { ++ __m256i Result = _mm256_blendv_epi8(X0, X1, X2); ++ return Result; ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/i386/pr110227.c +@@ -0,0 +1,11 @@ ++/* { dg-do assemble { target { ! ia32 } } } */ ++/* { dg-options " -O2 -mavx512vl" } */ ++ ++#include ++ ++void f() ++{ ++ __m256i mask = _mm256_set_epi32(0, 0, 0, 0, -1, -1, -1, -1); ++ register __m256i reg asm("xmm16") = mask; ++ asm(""::"v"(reg)); ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/i386/pr110309.c +@@ -0,0 +1,10 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O3 --param vect-partial-vector-usage=1 -march=znver4 -mprefer-vector-width=256" } */ ++/* { dg-final { scan-assembler-not {(?n)vpblendd.*ymm} } } */ ++ ++ ++void foo (int * __restrict a, int *b) ++{ ++ for (int i = 0; i < 6; ++i) ++ a[i] = b[i] + 42; ++} +--- a/src/gcc/testsuite/gcc.target/i386/pr69482-1.c ++++ b/src/gcc/testsuite/gcc.target/i386/pr69482-1.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-O3" } */ ++/* { dg-options "-O3 -fno-stack-protector" } */ + + static inline void memset_s(void* s, int n) { + volatile unsigned char * p = s; +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/powerpc/darwin-abi-13-0.c +@@ -0,0 +1,23 @@ ++/* { dg-do compile { target powerpc*-*-darwin* } } */ ++/* { dg-require-effective-target ilp32 } */ ++/* { dg-options "-Wno-long-long" } */ ++ ++#include "darwin-structs-0.h" ++ ++int tcd[sizeof(cd) != 12 ? -1 : 1]; ++int acd[__alignof__(cd) != 4 ? -1 : 1]; ++ ++int sdc[sizeof(dc) != 16 ? -1 : 1]; ++int adc[__alignof__(dc) != 8 ? -1 : 1]; ++ ++int scL[sizeof(cL) != 12 ? -1 : 1]; ++int acL[__alignof__(cL) != 4 ? -1 : 1]; ++ ++int sLc[sizeof(Lc) != 16 ? -1 : 1]; ++int aLc[__alignof__(Lc) != 8 ? -1 : 1]; ++ ++int scD[sizeof(cD) != 32 ? -1 : 1]; ++int acD[__alignof__(cD) != 16 ? -1 : 1]; ++ ++int sDc[sizeof(Dc) != 32 ? -1 : 1]; ++int aDc[__alignof__(Dc) != 16 ? -1 : 1]; +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/powerpc/darwin-abi-13-1.c +@@ -0,0 +1,27 @@ ++/* { dg-do compile { target powerpc*-*-darwin* } } */ ++/* { dg-require-effective-target ilp32 } */ ++/* { dg-options "-Wno-long-long" } */ ++ ++#pragma pack(push, 1) ++ ++#include "darwin-structs-0.h" ++ ++int tcd[sizeof(cd) != 9 ? -1 : 1]; ++int acd[__alignof__(cd) != 1 ? -1 : 1]; ++ ++int sdc[sizeof(dc) != 9 ? -1 : 1]; ++int adc[__alignof__(dc) != 1 ? -1 : 1]; ++ ++int scL[sizeof(cL) != 9 ? -1 : 1]; ++int acL[__alignof__(cL) != 1 ? -1 : 1]; ++ ++int sLc[sizeof(Lc) != 9 ? -1 : 1]; ++int aLc[__alignof__(Lc) != 1 ? -1 : 1]; ++ ++int scD[sizeof(cD) != 17 ? -1 : 1]; ++int acD[__alignof__(cD) != 1 ? -1 : 1]; ++ ++int sDc[sizeof(Dc) != 17 ? -1 : 1]; ++int aDc[__alignof__(Dc) != 1 ? -1 : 1]; ++ ++#pragma pack(pop) +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/powerpc/darwin-abi-13-2.c +@@ -0,0 +1,27 @@ ++/* { dg-do compile { target powerpc*-*-darwin* } } */ ++/* { dg-require-effective-target ilp32 } */ ++/* { dg-options "-Wno-long-long" } */ ++ ++#pragma pack(push, 2) ++ ++#include "darwin-structs-0.h" ++ ++int tcd[sizeof(cd) != 10 ? -1 : 1]; ++int acd[__alignof__(cd) != 2 ? -1 : 1]; ++ ++int sdc[sizeof(dc) != 10 ? -1 : 1]; ++int adc[__alignof__(dc) != 2 ? -1 : 1]; ++ ++int scL[sizeof(cL) != 10 ? -1 : 1]; ++int acL[__alignof__(cL) != 2 ? -1 : 1]; ++ ++int sLc[sizeof(Lc) != 10 ? -1 : 1]; ++int aLc[__alignof__(Lc) != 2 ? -1 : 1]; ++ ++int scD[sizeof(cD) != 18 ? -1 : 1]; ++int acD[__alignof__(cD) != 2 ? -1 : 1]; ++ ++int sDc[sizeof(Dc) != 18 ? -1 : 1]; ++int aDc[__alignof__(Dc) != 2 ? -1 : 1]; ++ ++#pragma pack(pop) +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/powerpc/darwin-structs-0.h +@@ -0,0 +1,29 @@ ++typedef struct _cd { ++ char c; ++ double d; ++} cd; ++ ++typedef struct _dc { ++ double d; ++ char c; ++} dc; ++ ++typedef struct _cL { ++ char c; ++ long long L; ++} cL; ++ ++typedef struct _Lc { ++ long long L; ++ char c; ++} Lc; ++ ++typedef struct _cD { ++ char c; ++ long double D; ++} cD; ++ ++typedef struct _Dc { ++ long double D; ++ char c; ++} Dc; +--- a/src/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c +@@ -54,15 +54,17 @@ TEST(uint8_t) + TEST(int8_t) + + /* { dg-final { scan-assembler-times "lbz_cmpldi_cr0_QI_clobber_CCUNS_zero" 4 { target lp64 } } } */ +-/* { dg-final { scan-assembler-times "ld_cmpdi_cr0_DI_DI_CC_none" 4 { target lp64 } } } */ +-/* { dg-final { scan-assembler-times "ld_cmpdi_cr0_DI_clobber_CC_none" 4 { target lp64 } } } */ +-/* { dg-final { scan-assembler-times "ld_cmpldi_cr0_DI_DI_CCUNS_none" 1 { target lp64 } } } */ +-/* { dg-final { scan-assembler-times "ld_cmpldi_cr0_DI_clobber_CCUNS_none" 1 { target lp64 } } } */ ++/* { dg-final { scan-assembler-times "ld_cmpdi_cr0_DI_DI_CC_none" 24 { target lp64 } } } */ ++/* { dg-final { scan-assembler-times "ld_cmpdi_cr0_DI_clobber_CC_none" 8 { target lp64 } } } */ ++/* { dg-final { scan-assembler-times "ld_cmpldi_cr0_DI_DI_CCUNS_none" 2 { target lp64 } } } */ ++/* { dg-final { scan-assembler-times "ld_cmpldi_cr0_DI_clobber_CCUNS_none" 2 { target lp64 } } } */ + /* { dg-final { scan-assembler-times "lha_cmpdi_cr0_HI_clobber_CC_sign" 16 { target lp64 } } } */ + /* { dg-final { scan-assembler-times "lhz_cmpldi_cr0_HI_clobber_CCUNS_zero" 4 { target lp64 } } } */ + /* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_EXTSI_CC_sign" 0 { target lp64 } } } */ +-/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 4 { target lp64 } } } */ ++/* { dg-final { scan-assembler-times "lwz_cmpwi_cr0_SI_clobber_CC_none" 8 { target lp64 } } } */ ++/* { dg-final { scan-assembler-times "lwz_cmpwi_cr0_SI_SI_CC_none" 8 { target lp64 } } } */ + /* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero" 0 { target lp64 } } } */ ++/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_SI_CCUNS_none" 2 { target lp64 } } } */ + /* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_clobber_CCUNS_none" 2 { target lp64 } } } */ + + /* { dg-final { scan-assembler-times "lbz_cmpldi_cr0_QI_clobber_CCUNS_zero" 2 { target ilp32 } } } */ +@@ -73,6 +75,8 @@ TEST(int8_t) + /* { dg-final { scan-assembler-times "lha_cmpdi_cr0_HI_clobber_CC_sign" 8 { target ilp32 } } } */ + /* { dg-final { scan-assembler-times "lhz_cmpldi_cr0_HI_clobber_CCUNS_zero" 2 { target ilp32 } } } */ + /* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_EXTSI_CC_sign" 0 { target ilp32 } } } */ +-/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 9 { target ilp32 } } } */ ++/* { dg-final { scan-assembler-times "lwz_cmpwi_cr0_SI_SI_CC_none" 36 { target ilp32 } } } */ ++/* { dg-final { scan-assembler-times "lwz_cmpwi_cr0_SI_clobber_CC_none" 16 { target ilp32 } } } */ + /* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero" 0 { target ilp32 } } } */ + /* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_clobber_CCUNS_none" 6 { target ilp32 } } } */ ++/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_SI_CCUNS_none" 2 { target ilp32 } } } */ +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/powerpc/pr109069-1.c +@@ -0,0 +1,25 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target vmx_hw } */ ++/* { dg-options "-O2 -maltivec" } */ ++ ++/* Verify it run successfully. */ ++ ++#include ++ ++__attribute__ ((noipa)) ++vector signed int ++test () ++{ ++ vector signed int v = {-16, -16, -16, -16}; ++ vector signed int res = vec_sld (v, v, 3); ++ return res; ++} ++ ++int ++main () ++{ ++ vector signed int res = test (); ++ if (res[0] != 0xf0ffffff) ++ __builtin_abort (); ++ return 0; ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/powerpc/pr109069-2-run.c +@@ -0,0 +1,50 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target vsx_hw } */ ++/* { dg-options "-O2 -mvsx" } */ ++ ++/* Verify it doesn't generate wrong code. */ ++ ++#include "pr109069-2.h" ++ ++int ++main () ++{ ++ vector unsigned char res1 = test1 (); ++ for (int i = 0; i < 16; i++) ++ if (res1[i] != 0xd) ++ __builtin_abort (); ++ ++ vector signed short res2 = test2 (); ++ for (int i = 0; i < 8; i++) ++ if (res2[i] != 0x7777) ++ __builtin_abort (); ++ ++ vector signed int res3 = test3 (); ++ vector unsigned int res4 = test4 (); ++ vector float res6 = test6 (); ++ for (int i = 0; i < 4; i++) ++ { ++ if (res3[i] != 0xbbbbbbbb) ++ __builtin_abort (); ++ if (res4[i] != 0x7070707) ++ __builtin_abort (); ++ U32b u; ++ u.f = res6[i]; ++ if (u.i != 0x17171717) ++ __builtin_abort (); ++ } ++ ++ vector unsigned long long res5 = test5 (); ++ vector double res7 = test7 (); ++ for (int i = 0; i < 2; i++) ++ { ++ if (res5[i] != 0x4545454545454545ll) ++ __builtin_abort (); ++ U64b u; ++ u.f = res7[i]; ++ if (u.i != 0x5454545454545454ll) ++ __builtin_abort (); ++ } ++ return 0; ++} ++ +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/powerpc/pr109069-2.c +@@ -0,0 +1,12 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++/* Disable rs6000 optimize_swaps as it drops some REG_EQUAL ++ notes on const vector and affects test point here. */ ++/* { dg-options "-O2 -mvsx -mno-optimize-swaps" } */ ++ ++/* Verify we can optimize away vector shifting if every byte ++ of vector is the same. */ ++ ++#include "pr109069-2.h" ++ ++/* { dg-final { scan-assembler-not {\mvsldoi\M} } } */ +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/powerpc/pr109069-2.h +@@ -0,0 +1,83 @@ ++#include ++ ++typedef union ++{ ++ unsigned int i; ++ float f; ++} U32b; ++ ++typedef union ++{ ++ unsigned long long i; ++ double f; ++} U64b; ++ ++__attribute__ ((noipa)) ++vector unsigned char ++test1 () ++{ ++ vector unsigned char v = {0xd, 0xd, 0xd, 0xd, 0xd, 0xd, 0xd, 0xd, ++ 0xd, 0xd, 0xd, 0xd, 0xd, 0xd, 0xd, 0xd}; ++ vector unsigned char res = vec_sld (v, v, 3); ++ return res; ++} ++ ++__attribute__ ((noipa)) ++vector signed short ++test2 () ++{ ++ vector signed short v ++ = {0x7777, 0x7777, 0x7777, 0x7777, 0x7777, 0x7777, 0x7777, 0x7777}; ++ vector signed short res = vec_sld (v, v, 5); ++ return res; ++} ++ ++__attribute__ ((noipa)) ++vector signed int ++test3 () ++{ ++ vector signed int v = {0xbbbbbbbb, 0xbbbbbbbb, 0xbbbbbbbb, 0xbbbbbbbb}; ++ vector signed int res = vec_sld (v, v, 7); ++ return res; ++} ++ ++__attribute__ ((noipa)) ++vector unsigned int ++test4 () ++{ ++ vector unsigned int v = {0x07070707, 0x07070707, 0x07070707, 0x07070707}; ++ vector unsigned int res = vec_sld (v, v, 9); ++ return res; ++} ++ ++__attribute__ ((noipa)) ++vector unsigned long long ++test5 () ++{ ++ vector unsigned long long v = {0x4545454545454545ll, 0x4545454545454545ll}; ++ vector unsigned long long res = vec_sld (v, v, 10); ++ return res; ++} ++ ++__attribute__ ((noipa)) ++vector float ++test6 () ++{ ++ U32b u; ++ u.i = 0x17171717; ++ vector float vf = {u.f, u.f, u.f, u.f}; ++ vector float res = vec_sld (vf, vf, 11); ++ return res; ++} ++ ++__attribute__ ((noipa)) ++vector double ++test7 () ++{ ++ U64b u; ++ u.i = 0x5454545454545454ll; ++ vector double vf = {u.f, u.f}; ++ vector double res = vec_sld (vf, vf, 13); ++ return res; ++} ++ +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/powerpc/pr109932-1.c +@@ -0,0 +1,17 @@ ++/* { dg-require-effective-target int128 } */ ++/* { dg-require-effective-target powerpc_altivec_ok } */ ++/* { dg-options "-maltivec -mno-vsx" } */ ++ ++/* Verify there is no ICE but one expected error message instead. */ ++ ++#include ++ ++extern vector signed __int128 res_vslll; ++extern unsigned long long aull[2]; ++ ++void ++testVectorInt128Pack () ++{ ++ res_vslll = __builtin_pack_vector_int128 (aull[0], aull[1]); /* { dg-error "'__builtin_pack_vector_int128' requires the '-mvsx' option" } */ ++} ++ +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/powerpc/pr109932-2.c +@@ -0,0 +1,17 @@ ++/* { dg-require-effective-target int128 } */ ++/* { dg-require-effective-target powerpc_altivec_ok } */ ++/* { dg-options "-maltivec -mno-vsx" } */ ++ ++/* Verify there is no ICE but one expected error message instead. */ ++ ++#include ++ ++extern vector signed __int128 res_vslll; ++extern unsigned long long aull[2]; ++ ++void ++testVectorInt128Pack () ++{ ++ res_vslll = __builtin_pack_vector_int128 (aull[0], aull[1]); /* { dg-error "'__builtin_pack_vector_int128' requires the '-mvsx' option" } */ ++} ++ +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/powerpc/pr110011.c +@@ -0,0 +1,42 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target float128_runtime } */ ++/* Force long double to be with IBM format here, to verify ++ _Float128 constant still uses its own format (IEEE) for ++ encoding rather than IBM format. */ ++/* { dg-options "-mfp-in-toc -mabi=ibmlongdouble" } */ ++/* { dg-add-options float128 } */ ++ ++#define MPFR_FLOAT128_MAX 0x1.ffffffffffffffffffffffffffffp+16383f128 ++ ++__attribute__ ((noipa)) ++_Float128 f128_max () ++{ ++ return MPFR_FLOAT128_MAX; ++} ++ ++typedef union ++{ ++ int w[4]; ++ _Float128 f128; ++} U; ++ ++int main () ++{ ++ ++ U umax; ++ umax.f128 = f128_max (); ++ /* ieee float128 max: ++ 7ffeffff ffffffff ffffffff ffffffff. */ ++ if (umax.w[1] != 0xffffffff || umax.w[2] != 0xffffffff) ++ __builtin_abort (); ++#ifdef __LITTLE_ENDIAN__ ++ if (umax.w[0] != 0xffffffff || umax.w[3] != 0x7ffeffff) ++ __builtin_abort (); ++#else ++ if (umax.w[3] != 0xffffffff || umax.w[0] != 0x7ffeffff) ++ __builtin_abort (); ++#endif ++ ++ return 0; ++} ++ +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/riscv/inline-atomics-1.c +@@ -0,0 +1,18 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mno-inline-atomics" } */ ++/* { dg-message "note: '__sync_fetch_and_nand' changed semantics in GCC 4.4" "fetch_and_nand" { target *-*-* } 0 } */ ++/* { dg-final { scan-assembler "\tcall\t__sync_fetch_and_add_1" } } */ ++/* { dg-final { scan-assembler "\tcall\t__sync_fetch_and_nand_1" } } */ ++/* { dg-final { scan-assembler "\tcall\t__sync_bool_compare_and_swap_1" } } */ ++ ++char foo; ++char bar; ++char baz; ++ ++int ++main () ++{ ++ __sync_fetch_and_add(&foo, 1); ++ __sync_fetch_and_nand(&bar, 1); ++ __sync_bool_compare_and_swap (&baz, 1, 2); ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/riscv/inline-atomics-2.c +@@ -0,0 +1,9 @@ ++/* { dg-do compile } */ ++/* Verify that subword atomics do not generate calls. */ ++/* { dg-options "-minline-atomics" } */ ++/* { dg-message "note: '__sync_fetch_and_nand' changed semantics in GCC 4.4" "fetch_and_nand" { target *-*-* } 0 } */ ++/* { dg-final { scan-assembler-not "\tcall\t__sync_fetch_and_add_1" } } */ ++/* { dg-final { scan-assembler-not "\tcall\t__sync_fetch_and_nand_1" } } */ ++/* { dg-final { scan-assembler-not "\tcall\t__sync_bool_compare_and_swap_1" } } */ ++ ++#include "inline-atomics-1.c" +\ No newline at end of file +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/riscv/inline-atomics-3.c +@@ -0,0 +1,569 @@ ++/* Check all char alignments. */ ++/* Duplicate logic as libatomic/testsuite/libatomic.c/atomic-op-1.c */ ++/* Test __atomic routines for existence and proper execution on 1 byte ++ values with each valid memory model. */ ++/* { dg-do run } */ ++/* { dg-options "-minline-atomics -Wno-address-of-packed-member" } */ ++ ++/* Test the execution of the __atomic_*OP builtin routines for a char. */ ++ ++extern void abort(void); ++ ++char count, res; ++const char init = ~0; ++ ++struct A ++{ ++ char a; ++ char b; ++ char c; ++ char d; ++} __attribute__ ((packed)) A; ++ ++/* The fetch_op routines return the original value before the operation. */ ++ ++void ++test_fetch_add (char* v) ++{ ++ *v = 0; ++ count = 1; ++ ++ if (__atomic_fetch_add (v, count, __ATOMIC_RELAXED) != 0) ++ abort (); ++ ++ if (__atomic_fetch_add (v, 1, __ATOMIC_CONSUME) != 1) ++ abort (); ++ ++ if (__atomic_fetch_add (v, count, __ATOMIC_ACQUIRE) != 2) ++ abort (); ++ ++ if (__atomic_fetch_add (v, 1, __ATOMIC_RELEASE) != 3) ++ abort (); ++ ++ if (__atomic_fetch_add (v, count, __ATOMIC_ACQ_REL) != 4) ++ abort (); ++ ++ if (__atomic_fetch_add (v, 1, __ATOMIC_SEQ_CST) != 5) ++ abort (); ++} ++ ++ ++void ++test_fetch_sub (char* v) ++{ ++ *v = res = 20; ++ count = 0; ++ ++ if (__atomic_fetch_sub (v, count + 1, __ATOMIC_RELAXED) != res--) ++ abort (); ++ ++ if (__atomic_fetch_sub (v, 1, __ATOMIC_CONSUME) != res--) ++ abort (); ++ ++ if (__atomic_fetch_sub (v, count + 1, __ATOMIC_ACQUIRE) != res--) ++ abort (); ++ ++ if (__atomic_fetch_sub (v, 1, __ATOMIC_RELEASE) != res--) ++ abort (); ++ ++ if (__atomic_fetch_sub (v, count + 1, __ATOMIC_ACQ_REL) != res--) ++ abort (); ++ ++ if (__atomic_fetch_sub (v, 1, __ATOMIC_SEQ_CST) != res--) ++ abort (); ++} ++ ++void ++test_fetch_and (char* v) ++{ ++ *v = init; ++ ++ if (__atomic_fetch_and (v, 0, __ATOMIC_RELAXED) != init) ++ abort (); ++ ++ if (__atomic_fetch_and (v, init, __ATOMIC_CONSUME) != 0) ++ abort (); ++ ++ if (__atomic_fetch_and (v, 0, __ATOMIC_ACQUIRE) != 0) ++ abort (); ++ ++ *v = ~*v; ++ if (__atomic_fetch_and (v, init, __ATOMIC_RELEASE) != init) ++ abort (); ++ ++ if (__atomic_fetch_and (v, 0, __ATOMIC_ACQ_REL) != init) ++ abort (); ++ ++ if (__atomic_fetch_and (v, 0, __ATOMIC_SEQ_CST) != 0) ++ abort (); ++} ++ ++void ++test_fetch_nand (char* v) ++{ ++ *v = init; ++ ++ if (__atomic_fetch_nand (v, 0, __ATOMIC_RELAXED) != init) ++ abort (); ++ ++ if (__atomic_fetch_nand (v, init, __ATOMIC_CONSUME) != init) ++ abort (); ++ ++ if (__atomic_fetch_nand (v, 0, __ATOMIC_ACQUIRE) != 0 ) ++ abort (); ++ ++ if (__atomic_fetch_nand (v, init, __ATOMIC_RELEASE) != init) ++ abort (); ++ ++ if (__atomic_fetch_nand (v, init, __ATOMIC_ACQ_REL) != 0) ++ abort (); ++ ++ if (__atomic_fetch_nand (v, 0, __ATOMIC_SEQ_CST) != init) ++ abort (); ++} ++ ++void ++test_fetch_xor (char* v) ++{ ++ *v = init; ++ count = 0; ++ ++ if (__atomic_fetch_xor (v, count, __ATOMIC_RELAXED) != init) ++ abort (); ++ ++ if (__atomic_fetch_xor (v, ~count, __ATOMIC_CONSUME) != init) ++ abort (); ++ ++ if (__atomic_fetch_xor (v, 0, __ATOMIC_ACQUIRE) != 0) ++ abort (); ++ ++ if (__atomic_fetch_xor (v, ~count, __ATOMIC_RELEASE) != 0) ++ abort (); ++ ++ if (__atomic_fetch_xor (v, 0, __ATOMIC_ACQ_REL) != init) ++ abort (); ++ ++ if (__atomic_fetch_xor (v, ~count, __ATOMIC_SEQ_CST) != init) ++ abort (); ++} ++ ++void ++test_fetch_or (char* v) ++{ ++ *v = 0; ++ count = 1; ++ ++ if (__atomic_fetch_or (v, count, __ATOMIC_RELAXED) != 0) ++ abort (); ++ ++ count *= 2; ++ if (__atomic_fetch_or (v, 2, __ATOMIC_CONSUME) != 1) ++ abort (); ++ ++ count *= 2; ++ if (__atomic_fetch_or (v, count, __ATOMIC_ACQUIRE) != 3) ++ abort (); ++ ++ count *= 2; ++ if (__atomic_fetch_or (v, 8, __ATOMIC_RELEASE) != 7) ++ abort (); ++ ++ count *= 2; ++ if (__atomic_fetch_or (v, count, __ATOMIC_ACQ_REL) != 15) ++ abort (); ++ ++ count *= 2; ++ if (__atomic_fetch_or (v, count, __ATOMIC_SEQ_CST) != 31) ++ abort (); ++} ++ ++/* The OP_fetch routines return the new value after the operation. */ ++ ++void ++test_add_fetch (char* v) ++{ ++ *v = 0; ++ count = 1; ++ ++ if (__atomic_add_fetch (v, count, __ATOMIC_RELAXED) != 1) ++ abort (); ++ ++ if (__atomic_add_fetch (v, 1, __ATOMIC_CONSUME) != 2) ++ abort (); ++ ++ if (__atomic_add_fetch (v, count, __ATOMIC_ACQUIRE) != 3) ++ abort (); ++ ++ if (__atomic_add_fetch (v, 1, __ATOMIC_RELEASE) != 4) ++ abort (); ++ ++ if (__atomic_add_fetch (v, count, __ATOMIC_ACQ_REL) != 5) ++ abort (); ++ ++ if (__atomic_add_fetch (v, count, __ATOMIC_SEQ_CST) != 6) ++ abort (); ++} ++ ++ ++void ++test_sub_fetch (char* v) ++{ ++ *v = res = 20; ++ count = 0; ++ ++ if (__atomic_sub_fetch (v, count + 1, __ATOMIC_RELAXED) != --res) ++ abort (); ++ ++ if (__atomic_sub_fetch (v, 1, __ATOMIC_CONSUME) != --res) ++ abort (); ++ ++ if (__atomic_sub_fetch (v, count + 1, __ATOMIC_ACQUIRE) != --res) ++ abort (); ++ ++ if (__atomic_sub_fetch (v, 1, __ATOMIC_RELEASE) != --res) ++ abort (); ++ ++ if (__atomic_sub_fetch (v, count + 1, __ATOMIC_ACQ_REL) != --res) ++ abort (); ++ ++ if (__atomic_sub_fetch (v, count + 1, __ATOMIC_SEQ_CST) != --res) ++ abort (); ++} ++ ++void ++test_and_fetch (char* v) ++{ ++ *v = init; ++ ++ if (__atomic_and_fetch (v, 0, __ATOMIC_RELAXED) != 0) ++ abort (); ++ ++ *v = init; ++ if (__atomic_and_fetch (v, init, __ATOMIC_CONSUME) != init) ++ abort (); ++ ++ if (__atomic_and_fetch (v, 0, __ATOMIC_ACQUIRE) != 0) ++ abort (); ++ ++ *v = ~*v; ++ if (__atomic_and_fetch (v, init, __ATOMIC_RELEASE) != init) ++ abort (); ++ ++ if (__atomic_and_fetch (v, 0, __ATOMIC_ACQ_REL) != 0) ++ abort (); ++ ++ *v = ~*v; ++ if (__atomic_and_fetch (v, 0, __ATOMIC_SEQ_CST) != 0) ++ abort (); ++} ++ ++void ++test_nand_fetch (char* v) ++{ ++ *v = init; ++ ++ if (__atomic_nand_fetch (v, 0, __ATOMIC_RELAXED) != init) ++ abort (); ++ ++ if (__atomic_nand_fetch (v, init, __ATOMIC_CONSUME) != 0) ++ abort (); ++ ++ if (__atomic_nand_fetch (v, 0, __ATOMIC_ACQUIRE) != init) ++ abort (); ++ ++ if (__atomic_nand_fetch (v, init, __ATOMIC_RELEASE) != 0) ++ abort (); ++ ++ if (__atomic_nand_fetch (v, init, __ATOMIC_ACQ_REL) != init) ++ abort (); ++ ++ if (__atomic_nand_fetch (v, 0, __ATOMIC_SEQ_CST) != init) ++ abort (); ++} ++ ++ ++ ++void ++test_xor_fetch (char* v) ++{ ++ *v = init; ++ count = 0; ++ ++ if (__atomic_xor_fetch (v, count, __ATOMIC_RELAXED) != init) ++ abort (); ++ ++ if (__atomic_xor_fetch (v, ~count, __ATOMIC_CONSUME) != 0) ++ abort (); ++ ++ if (__atomic_xor_fetch (v, 0, __ATOMIC_ACQUIRE) != 0) ++ abort (); ++ ++ if (__atomic_xor_fetch (v, ~count, __ATOMIC_RELEASE) != init) ++ abort (); ++ ++ if (__atomic_xor_fetch (v, 0, __ATOMIC_ACQ_REL) != init) ++ abort (); ++ ++ if (__atomic_xor_fetch (v, ~count, __ATOMIC_SEQ_CST) != 0) ++ abort (); ++} ++ ++void ++test_or_fetch (char* v) ++{ ++ *v = 0; ++ count = 1; ++ ++ if (__atomic_or_fetch (v, count, __ATOMIC_RELAXED) != 1) ++ abort (); ++ ++ count *= 2; ++ if (__atomic_or_fetch (v, 2, __ATOMIC_CONSUME) != 3) ++ abort (); ++ ++ count *= 2; ++ if (__atomic_or_fetch (v, count, __ATOMIC_ACQUIRE) != 7) ++ abort (); ++ ++ count *= 2; ++ if (__atomic_or_fetch (v, 8, __ATOMIC_RELEASE) != 15) ++ abort (); ++ ++ count *= 2; ++ if (__atomic_or_fetch (v, count, __ATOMIC_ACQ_REL) != 31) ++ abort (); ++ ++ count *= 2; ++ if (__atomic_or_fetch (v, count, __ATOMIC_SEQ_CST) != 63) ++ abort (); ++} ++ ++ ++/* Test the OP routines with a result which isn't used. Use both variations ++ within each function. */ ++ ++void ++test_add (char* v) ++{ ++ *v = 0; ++ count = 1; ++ ++ __atomic_add_fetch (v, count, __ATOMIC_RELAXED); ++ if (*v != 1) ++ abort (); ++ ++ __atomic_fetch_add (v, count, __ATOMIC_CONSUME); ++ if (*v != 2) ++ abort (); ++ ++ __atomic_add_fetch (v, 1 , __ATOMIC_ACQUIRE); ++ if (*v != 3) ++ abort (); ++ ++ __atomic_fetch_add (v, 1, __ATOMIC_RELEASE); ++ if (*v != 4) ++ abort (); ++ ++ __atomic_add_fetch (v, count, __ATOMIC_ACQ_REL); ++ if (*v != 5) ++ abort (); ++ ++ __atomic_fetch_add (v, count, __ATOMIC_SEQ_CST); ++ if (*v != 6) ++ abort (); ++} ++ ++ ++void ++test_sub (char* v) ++{ ++ *v = res = 20; ++ count = 0; ++ ++ __atomic_sub_fetch (v, count + 1, __ATOMIC_RELAXED); ++ if (*v != --res) ++ abort (); ++ ++ __atomic_fetch_sub (v, count + 1, __ATOMIC_CONSUME); ++ if (*v != --res) ++ abort (); ++ ++ __atomic_sub_fetch (v, 1, __ATOMIC_ACQUIRE); ++ if (*v != --res) ++ abort (); ++ ++ __atomic_fetch_sub (v, 1, __ATOMIC_RELEASE); ++ if (*v != --res) ++ abort (); ++ ++ __atomic_sub_fetch (v, count + 1, __ATOMIC_ACQ_REL); ++ if (*v != --res) ++ abort (); ++ ++ __atomic_fetch_sub (v, count + 1, __ATOMIC_SEQ_CST); ++ if (*v != --res) ++ abort (); ++} ++ ++void ++test_and (char* v) ++{ ++ *v = init; ++ ++ __atomic_and_fetch (v, 0, __ATOMIC_RELAXED); ++ if (*v != 0) ++ abort (); ++ ++ *v = init; ++ __atomic_fetch_and (v, init, __ATOMIC_CONSUME); ++ if (*v != init) ++ abort (); ++ ++ __atomic_and_fetch (v, 0, __ATOMIC_ACQUIRE); ++ if (*v != 0) ++ abort (); ++ ++ *v = ~*v; ++ __atomic_fetch_and (v, init, __ATOMIC_RELEASE); ++ if (*v != init) ++ abort (); ++ ++ __atomic_and_fetch (v, 0, __ATOMIC_ACQ_REL); ++ if (*v != 0) ++ abort (); ++ ++ *v = ~*v; ++ __atomic_fetch_and (v, 0, __ATOMIC_SEQ_CST); ++ if (*v != 0) ++ abort (); ++} ++ ++void ++test_nand (char* v) ++{ ++ *v = init; ++ ++ __atomic_fetch_nand (v, 0, __ATOMIC_RELAXED); ++ if (*v != init) ++ abort (); ++ ++ __atomic_fetch_nand (v, init, __ATOMIC_CONSUME); ++ if (*v != 0) ++ abort (); ++ ++ __atomic_nand_fetch (v, 0, __ATOMIC_ACQUIRE); ++ if (*v != init) ++ abort (); ++ ++ __atomic_nand_fetch (v, init, __ATOMIC_RELEASE); ++ if (*v != 0) ++ abort (); ++ ++ __atomic_fetch_nand (v, init, __ATOMIC_ACQ_REL); ++ if (*v != init) ++ abort (); ++ ++ __atomic_nand_fetch (v, 0, __ATOMIC_SEQ_CST); ++ if (*v != init) ++ abort (); ++} ++ ++ ++ ++void ++test_xor (char* v) ++{ ++ *v = init; ++ count = 0; ++ ++ __atomic_xor_fetch (v, count, __ATOMIC_RELAXED); ++ if (*v != init) ++ abort (); ++ ++ __atomic_fetch_xor (v, ~count, __ATOMIC_CONSUME); ++ if (*v != 0) ++ abort (); ++ ++ __atomic_xor_fetch (v, 0, __ATOMIC_ACQUIRE); ++ if (*v != 0) ++ abort (); ++ ++ __atomic_fetch_xor (v, ~count, __ATOMIC_RELEASE); ++ if (*v != init) ++ abort (); ++ ++ __atomic_fetch_xor (v, 0, __ATOMIC_ACQ_REL); ++ if (*v != init) ++ abort (); ++ ++ __atomic_xor_fetch (v, ~count, __ATOMIC_SEQ_CST); ++ if (*v != 0) ++ abort (); ++} ++ ++void ++test_or (char* v) ++{ ++ *v = 0; ++ count = 1; ++ ++ __atomic_or_fetch (v, count, __ATOMIC_RELAXED); ++ if (*v != 1) ++ abort (); ++ ++ count *= 2; ++ __atomic_fetch_or (v, count, __ATOMIC_CONSUME); ++ if (*v != 3) ++ abort (); ++ ++ count *= 2; ++ __atomic_or_fetch (v, 4, __ATOMIC_ACQUIRE); ++ if (*v != 7) ++ abort (); ++ ++ count *= 2; ++ __atomic_fetch_or (v, 8, __ATOMIC_RELEASE); ++ if (*v != 15) ++ abort (); ++ ++ count *= 2; ++ __atomic_or_fetch (v, count, __ATOMIC_ACQ_REL); ++ if (*v != 31) ++ abort (); ++ ++ count *= 2; ++ __atomic_fetch_or (v, count, __ATOMIC_SEQ_CST); ++ if (*v != 63) ++ abort (); ++} ++ ++int ++main () ++{ ++ char* V[] = {&A.a, &A.b, &A.c, &A.d}; ++ ++ for (int i = 0; i < 4; i++) { ++ test_fetch_add (V[i]); ++ test_fetch_sub (V[i]); ++ test_fetch_and (V[i]); ++ test_fetch_nand (V[i]); ++ test_fetch_xor (V[i]); ++ test_fetch_or (V[i]); ++ ++ test_add_fetch (V[i]); ++ test_sub_fetch (V[i]); ++ test_and_fetch (V[i]); ++ test_nand_fetch (V[i]); ++ test_xor_fetch (V[i]); ++ test_or_fetch (V[i]); ++ ++ test_add (V[i]); ++ test_sub (V[i]); ++ test_and (V[i]); ++ test_nand (V[i]); ++ test_xor (V[i]); ++ test_or (V[i]); ++ } ++ ++ return 0; ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/riscv/inline-atomics-4.c +@@ -0,0 +1,566 @@ ++/* Check all short alignments. */ ++/* Duplicate logic as libatomic/testsuite/libatomic.c/atomic-op-2.c */ ++/* Test __atomic routines for existence and proper execution on 2 byte ++ values with each valid memory model. */ ++/* { dg-do run } */ ++/* { dg-options "-minline-atomics -Wno-address-of-packed-member" } */ ++ ++/* Test the execution of the __atomic_*OP builtin routines for a short. */ ++ ++extern void abort(void); ++ ++short count, res; ++const short init = ~0; ++ ++struct A ++{ ++ short a; ++ short b; ++} __attribute__ ((packed)) A; ++ ++/* The fetch_op routines return the original value before the operation. */ ++ ++void ++test_fetch_add (short* v) ++{ ++ *v = 0; ++ count = 1; ++ ++ if (__atomic_fetch_add (v, count, __ATOMIC_RELAXED) != 0) ++ abort (); ++ ++ if (__atomic_fetch_add (v, 1, __ATOMIC_CONSUME) != 1) ++ abort (); ++ ++ if (__atomic_fetch_add (v, count, __ATOMIC_ACQUIRE) != 2) ++ abort (); ++ ++ if (__atomic_fetch_add (v, 1, __ATOMIC_RELEASE) != 3) ++ abort (); ++ ++ if (__atomic_fetch_add (v, count, __ATOMIC_ACQ_REL) != 4) ++ abort (); ++ ++ if (__atomic_fetch_add (v, 1, __ATOMIC_SEQ_CST) != 5) ++ abort (); ++} ++ ++ ++void ++test_fetch_sub (short* v) ++{ ++ *v = res = 20; ++ count = 0; ++ ++ if (__atomic_fetch_sub (v, count + 1, __ATOMIC_RELAXED) != res--) ++ abort (); ++ ++ if (__atomic_fetch_sub (v, 1, __ATOMIC_CONSUME) != res--) ++ abort (); ++ ++ if (__atomic_fetch_sub (v, count + 1, __ATOMIC_ACQUIRE) != res--) ++ abort (); ++ ++ if (__atomic_fetch_sub (v, 1, __ATOMIC_RELEASE) != res--) ++ abort (); ++ ++ if (__atomic_fetch_sub (v, count + 1, __ATOMIC_ACQ_REL) != res--) ++ abort (); ++ ++ if (__atomic_fetch_sub (v, 1, __ATOMIC_SEQ_CST) != res--) ++ abort (); ++} ++ ++void ++test_fetch_and (short* v) ++{ ++ *v = init; ++ ++ if (__atomic_fetch_and (v, 0, __ATOMIC_RELAXED) != init) ++ abort (); ++ ++ if (__atomic_fetch_and (v, init, __ATOMIC_CONSUME) != 0) ++ abort (); ++ ++ if (__atomic_fetch_and (v, 0, __ATOMIC_ACQUIRE) != 0) ++ abort (); ++ ++ *v = ~*v; ++ if (__atomic_fetch_and (v, init, __ATOMIC_RELEASE) != init) ++ abort (); ++ ++ if (__atomic_fetch_and (v, 0, __ATOMIC_ACQ_REL) != init) ++ abort (); ++ ++ if (__atomic_fetch_and (v, 0, __ATOMIC_SEQ_CST) != 0) ++ abort (); ++} ++ ++void ++test_fetch_nand (short* v) ++{ ++ *v = init; ++ ++ if (__atomic_fetch_nand (v, 0, __ATOMIC_RELAXED) != init) ++ abort (); ++ ++ if (__atomic_fetch_nand (v, init, __ATOMIC_CONSUME) != init) ++ abort (); ++ ++ if (__atomic_fetch_nand (v, 0, __ATOMIC_ACQUIRE) != 0 ) ++ abort (); ++ ++ if (__atomic_fetch_nand (v, init, __ATOMIC_RELEASE) != init) ++ abort (); ++ ++ if (__atomic_fetch_nand (v, init, __ATOMIC_ACQ_REL) != 0) ++ abort (); ++ ++ if (__atomic_fetch_nand (v, 0, __ATOMIC_SEQ_CST) != init) ++ abort (); ++} ++ ++void ++test_fetch_xor (short* v) ++{ ++ *v = init; ++ count = 0; ++ ++ if (__atomic_fetch_xor (v, count, __ATOMIC_RELAXED) != init) ++ abort (); ++ ++ if (__atomic_fetch_xor (v, ~count, __ATOMIC_CONSUME) != init) ++ abort (); ++ ++ if (__atomic_fetch_xor (v, 0, __ATOMIC_ACQUIRE) != 0) ++ abort (); ++ ++ if (__atomic_fetch_xor (v, ~count, __ATOMIC_RELEASE) != 0) ++ abort (); ++ ++ if (__atomic_fetch_xor (v, 0, __ATOMIC_ACQ_REL) != init) ++ abort (); ++ ++ if (__atomic_fetch_xor (v, ~count, __ATOMIC_SEQ_CST) != init) ++ abort (); ++} ++ ++void ++test_fetch_or (short* v) ++{ ++ *v = 0; ++ count = 1; ++ ++ if (__atomic_fetch_or (v, count, __ATOMIC_RELAXED) != 0) ++ abort (); ++ ++ count *= 2; ++ if (__atomic_fetch_or (v, 2, __ATOMIC_CONSUME) != 1) ++ abort (); ++ ++ count *= 2; ++ if (__atomic_fetch_or (v, count, __ATOMIC_ACQUIRE) != 3) ++ abort (); ++ ++ count *= 2; ++ if (__atomic_fetch_or (v, 8, __ATOMIC_RELEASE) != 7) ++ abort (); ++ ++ count *= 2; ++ if (__atomic_fetch_or (v, count, __ATOMIC_ACQ_REL) != 15) ++ abort (); ++ ++ count *= 2; ++ if (__atomic_fetch_or (v, count, __ATOMIC_SEQ_CST) != 31) ++ abort (); ++} ++ ++/* The OP_fetch routines return the new value after the operation. */ ++ ++void ++test_add_fetch (short* v) ++{ ++ *v = 0; ++ count = 1; ++ ++ if (__atomic_add_fetch (v, count, __ATOMIC_RELAXED) != 1) ++ abort (); ++ ++ if (__atomic_add_fetch (v, 1, __ATOMIC_CONSUME) != 2) ++ abort (); ++ ++ if (__atomic_add_fetch (v, count, __ATOMIC_ACQUIRE) != 3) ++ abort (); ++ ++ if (__atomic_add_fetch (v, 1, __ATOMIC_RELEASE) != 4) ++ abort (); ++ ++ if (__atomic_add_fetch (v, count, __ATOMIC_ACQ_REL) != 5) ++ abort (); ++ ++ if (__atomic_add_fetch (v, count, __ATOMIC_SEQ_CST) != 6) ++ abort (); ++} ++ ++ ++void ++test_sub_fetch (short* v) ++{ ++ *v = res = 20; ++ count = 0; ++ ++ if (__atomic_sub_fetch (v, count + 1, __ATOMIC_RELAXED) != --res) ++ abort (); ++ ++ if (__atomic_sub_fetch (v, 1, __ATOMIC_CONSUME) != --res) ++ abort (); ++ ++ if (__atomic_sub_fetch (v, count + 1, __ATOMIC_ACQUIRE) != --res) ++ abort (); ++ ++ if (__atomic_sub_fetch (v, 1, __ATOMIC_RELEASE) != --res) ++ abort (); ++ ++ if (__atomic_sub_fetch (v, count + 1, __ATOMIC_ACQ_REL) != --res) ++ abort (); ++ ++ if (__atomic_sub_fetch (v, count + 1, __ATOMIC_SEQ_CST) != --res) ++ abort (); ++} ++ ++void ++test_and_fetch (short* v) ++{ ++ *v = init; ++ ++ if (__atomic_and_fetch (v, 0, __ATOMIC_RELAXED) != 0) ++ abort (); ++ ++ *v = init; ++ if (__atomic_and_fetch (v, init, __ATOMIC_CONSUME) != init) ++ abort (); ++ ++ if (__atomic_and_fetch (v, 0, __ATOMIC_ACQUIRE) != 0) ++ abort (); ++ ++ *v = ~*v; ++ if (__atomic_and_fetch (v, init, __ATOMIC_RELEASE) != init) ++ abort (); ++ ++ if (__atomic_and_fetch (v, 0, __ATOMIC_ACQ_REL) != 0) ++ abort (); ++ ++ *v = ~*v; ++ if (__atomic_and_fetch (v, 0, __ATOMIC_SEQ_CST) != 0) ++ abort (); ++} ++ ++void ++test_nand_fetch (short* v) ++{ ++ *v = init; ++ ++ if (__atomic_nand_fetch (v, 0, __ATOMIC_RELAXED) != init) ++ abort (); ++ ++ if (__atomic_nand_fetch (v, init, __ATOMIC_CONSUME) != 0) ++ abort (); ++ ++ if (__atomic_nand_fetch (v, 0, __ATOMIC_ACQUIRE) != init) ++ abort (); ++ ++ if (__atomic_nand_fetch (v, init, __ATOMIC_RELEASE) != 0) ++ abort (); ++ ++ if (__atomic_nand_fetch (v, init, __ATOMIC_ACQ_REL) != init) ++ abort (); ++ ++ if (__atomic_nand_fetch (v, 0, __ATOMIC_SEQ_CST) != init) ++ abort (); ++} ++ ++ ++ ++void ++test_xor_fetch (short* v) ++{ ++ *v = init; ++ count = 0; ++ ++ if (__atomic_xor_fetch (v, count, __ATOMIC_RELAXED) != init) ++ abort (); ++ ++ if (__atomic_xor_fetch (v, ~count, __ATOMIC_CONSUME) != 0) ++ abort (); ++ ++ if (__atomic_xor_fetch (v, 0, __ATOMIC_ACQUIRE) != 0) ++ abort (); ++ ++ if (__atomic_xor_fetch (v, ~count, __ATOMIC_RELEASE) != init) ++ abort (); ++ ++ if (__atomic_xor_fetch (v, 0, __ATOMIC_ACQ_REL) != init) ++ abort (); ++ ++ if (__atomic_xor_fetch (v, ~count, __ATOMIC_SEQ_CST) != 0) ++ abort (); ++} ++ ++void ++test_or_fetch (short* v) ++{ ++ *v = 0; ++ count = 1; ++ ++ if (__atomic_or_fetch (v, count, __ATOMIC_RELAXED) != 1) ++ abort (); ++ ++ count *= 2; ++ if (__atomic_or_fetch (v, 2, __ATOMIC_CONSUME) != 3) ++ abort (); ++ ++ count *= 2; ++ if (__atomic_or_fetch (v, count, __ATOMIC_ACQUIRE) != 7) ++ abort (); ++ ++ count *= 2; ++ if (__atomic_or_fetch (v, 8, __ATOMIC_RELEASE) != 15) ++ abort (); ++ ++ count *= 2; ++ if (__atomic_or_fetch (v, count, __ATOMIC_ACQ_REL) != 31) ++ abort (); ++ ++ count *= 2; ++ if (__atomic_or_fetch (v, count, __ATOMIC_SEQ_CST) != 63) ++ abort (); ++} ++ ++ ++/* Test the OP routines with a result which isn't used. Use both variations ++ within each function. */ ++ ++void ++test_add (short* v) ++{ ++ *v = 0; ++ count = 1; ++ ++ __atomic_add_fetch (v, count, __ATOMIC_RELAXED); ++ if (*v != 1) ++ abort (); ++ ++ __atomic_fetch_add (v, count, __ATOMIC_CONSUME); ++ if (*v != 2) ++ abort (); ++ ++ __atomic_add_fetch (v, 1 , __ATOMIC_ACQUIRE); ++ if (*v != 3) ++ abort (); ++ ++ __atomic_fetch_add (v, 1, __ATOMIC_RELEASE); ++ if (*v != 4) ++ abort (); ++ ++ __atomic_add_fetch (v, count, __ATOMIC_ACQ_REL); ++ if (*v != 5) ++ abort (); ++ ++ __atomic_fetch_add (v, count, __ATOMIC_SEQ_CST); ++ if (*v != 6) ++ abort (); ++} ++ ++ ++void ++test_sub (short* v) ++{ ++ *v = res = 20; ++ count = 0; ++ ++ __atomic_sub_fetch (v, count + 1, __ATOMIC_RELAXED); ++ if (*v != --res) ++ abort (); ++ ++ __atomic_fetch_sub (v, count + 1, __ATOMIC_CONSUME); ++ if (*v != --res) ++ abort (); ++ ++ __atomic_sub_fetch (v, 1, __ATOMIC_ACQUIRE); ++ if (*v != --res) ++ abort (); ++ ++ __atomic_fetch_sub (v, 1, __ATOMIC_RELEASE); ++ if (*v != --res) ++ abort (); ++ ++ __atomic_sub_fetch (v, count + 1, __ATOMIC_ACQ_REL); ++ if (*v != --res) ++ abort (); ++ ++ __atomic_fetch_sub (v, count + 1, __ATOMIC_SEQ_CST); ++ if (*v != --res) ++ abort (); ++} ++ ++void ++test_and (short* v) ++{ ++ *v = init; ++ ++ __atomic_and_fetch (v, 0, __ATOMIC_RELAXED); ++ if (*v != 0) ++ abort (); ++ ++ *v = init; ++ __atomic_fetch_and (v, init, __ATOMIC_CONSUME); ++ if (*v != init) ++ abort (); ++ ++ __atomic_and_fetch (v, 0, __ATOMIC_ACQUIRE); ++ if (*v != 0) ++ abort (); ++ ++ *v = ~*v; ++ __atomic_fetch_and (v, init, __ATOMIC_RELEASE); ++ if (*v != init) ++ abort (); ++ ++ __atomic_and_fetch (v, 0, __ATOMIC_ACQ_REL); ++ if (*v != 0) ++ abort (); ++ ++ *v = ~*v; ++ __atomic_fetch_and (v, 0, __ATOMIC_SEQ_CST); ++ if (*v != 0) ++ abort (); ++} ++ ++void ++test_nand (short* v) ++{ ++ *v = init; ++ ++ __atomic_fetch_nand (v, 0, __ATOMIC_RELAXED); ++ if (*v != init) ++ abort (); ++ ++ __atomic_fetch_nand (v, init, __ATOMIC_CONSUME); ++ if (*v != 0) ++ abort (); ++ ++ __atomic_nand_fetch (v, 0, __ATOMIC_ACQUIRE); ++ if (*v != init) ++ abort (); ++ ++ __atomic_nand_fetch (v, init, __ATOMIC_RELEASE); ++ if (*v != 0) ++ abort (); ++ ++ __atomic_fetch_nand (v, init, __ATOMIC_ACQ_REL); ++ if (*v != init) ++ abort (); ++ ++ __atomic_nand_fetch (v, 0, __ATOMIC_SEQ_CST); ++ if (*v != init) ++ abort (); ++} ++ ++ ++ ++void ++test_xor (short* v) ++{ ++ *v = init; ++ count = 0; ++ ++ __atomic_xor_fetch (v, count, __ATOMIC_RELAXED); ++ if (*v != init) ++ abort (); ++ ++ __atomic_fetch_xor (v, ~count, __ATOMIC_CONSUME); ++ if (*v != 0) ++ abort (); ++ ++ __atomic_xor_fetch (v, 0, __ATOMIC_ACQUIRE); ++ if (*v != 0) ++ abort (); ++ ++ __atomic_fetch_xor (v, ~count, __ATOMIC_RELEASE); ++ if (*v != init) ++ abort (); ++ ++ __atomic_fetch_xor (v, 0, __ATOMIC_ACQ_REL); ++ if (*v != init) ++ abort (); ++ ++ __atomic_xor_fetch (v, ~count, __ATOMIC_SEQ_CST); ++ if (*v != 0) ++ abort (); ++} ++ ++void ++test_or (short* v) ++{ ++ *v = 0; ++ count = 1; ++ ++ __atomic_or_fetch (v, count, __ATOMIC_RELAXED); ++ if (*v != 1) ++ abort (); ++ ++ count *= 2; ++ __atomic_fetch_or (v, count, __ATOMIC_CONSUME); ++ if (*v != 3) ++ abort (); ++ ++ count *= 2; ++ __atomic_or_fetch (v, 4, __ATOMIC_ACQUIRE); ++ if (*v != 7) ++ abort (); ++ ++ count *= 2; ++ __atomic_fetch_or (v, 8, __ATOMIC_RELEASE); ++ if (*v != 15) ++ abort (); ++ ++ count *= 2; ++ __atomic_or_fetch (v, count, __ATOMIC_ACQ_REL); ++ if (*v != 31) ++ abort (); ++ ++ count *= 2; ++ __atomic_fetch_or (v, count, __ATOMIC_SEQ_CST); ++ if (*v != 63) ++ abort (); ++} ++ ++int ++main () { ++ short* V[] = {&A.a, &A.b}; ++ ++ for (int i = 0; i < 2; i++) { ++ test_fetch_add (V[i]); ++ test_fetch_sub (V[i]); ++ test_fetch_and (V[i]); ++ test_fetch_nand (V[i]); ++ test_fetch_xor (V[i]); ++ test_fetch_or (V[i]); ++ ++ test_add_fetch (V[i]); ++ test_sub_fetch (V[i]); ++ test_and_fetch (V[i]); ++ test_nand_fetch (V[i]); ++ test_xor_fetch (V[i]); ++ test_or_fetch (V[i]); ++ ++ test_add (V[i]); ++ test_sub (V[i]); ++ test_and (V[i]); ++ test_nand (V[i]); ++ test_xor (V[i]); ++ test_or (V[i]); ++ } ++ ++ return 0; ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/riscv/inline-atomics-5.c +@@ -0,0 +1,87 @@ ++/* Test __atomic routines for existence and proper execution on 1 byte ++ values with each valid memory model. */ ++/* Duplicate logic as libatomic/testsuite/libatomic.c/atomic-compare-exchange-1.c */ ++/* { dg-do run } */ ++/* { dg-options "-minline-atomics" } */ ++ ++/* Test the execution of the __atomic_compare_exchange_n builtin for a char. */ ++ ++extern void abort(void); ++ ++char v = 0; ++char expected = 0; ++char max = ~0; ++char desired = ~0; ++char zero = 0; ++ ++#define STRONG 0 ++#define WEAK 1 ++ ++int ++main () ++{ ++ ++ if (!__atomic_compare_exchange_n (&v, &expected, max, STRONG , __ATOMIC_RELAXED, __ATOMIC_RELAXED)) ++ abort (); ++ if (expected != 0) ++ abort (); ++ ++ if (__atomic_compare_exchange_n (&v, &expected, 0, STRONG , __ATOMIC_ACQUIRE, __ATOMIC_RELAXED)) ++ abort (); ++ if (expected != max) ++ abort (); ++ ++ if (!__atomic_compare_exchange_n (&v, &expected, 0, STRONG , __ATOMIC_RELEASE, __ATOMIC_ACQUIRE)) ++ abort (); ++ if (expected != max) ++ abort (); ++ if (v != 0) ++ abort (); ++ ++ if (__atomic_compare_exchange_n (&v, &expected, desired, WEAK, __ATOMIC_ACQ_REL, __ATOMIC_ACQUIRE)) ++ abort (); ++ if (expected != 0) ++ abort (); ++ ++ if (!__atomic_compare_exchange_n (&v, &expected, desired, STRONG , __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST)) ++ abort (); ++ if (expected != 0) ++ abort (); ++ if (v != max) ++ abort (); ++ ++ /* Now test the generic version. */ ++ ++ v = 0; ++ ++ if (!__atomic_compare_exchange (&v, &expected, &max, STRONG, __ATOMIC_RELAXED, __ATOMIC_RELAXED)) ++ abort (); ++ if (expected != 0) ++ abort (); ++ ++ if (__atomic_compare_exchange (&v, &expected, &zero, STRONG , __ATOMIC_ACQUIRE, __ATOMIC_RELAXED)) ++ abort (); ++ if (expected != max) ++ abort (); ++ ++ if (!__atomic_compare_exchange (&v, &expected, &zero, STRONG , __ATOMIC_RELEASE, __ATOMIC_ACQUIRE)) ++ abort (); ++ if (expected != max) ++ abort (); ++ if (v != 0) ++ abort (); ++ ++ if (__atomic_compare_exchange (&v, &expected, &desired, WEAK, __ATOMIC_ACQ_REL, __ATOMIC_ACQUIRE)) ++ abort (); ++ if (expected != 0) ++ abort (); ++ ++ if (!__atomic_compare_exchange (&v, &expected, &desired, STRONG , __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST)) ++ abort (); ++ if (expected != 0) ++ abort (); ++ if (v != max) ++ abort (); ++ ++ return 0; ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/riscv/inline-atomics-6.c +@@ -0,0 +1,87 @@ ++/* Test __atomic routines for existence and proper execution on 2 byte ++ values with each valid memory model. */ ++/* Duplicate logic as libatomic/testsuite/libatomic.c/atomic-compare-exchange-2.c */ ++/* { dg-do run } */ ++/* { dg-options "-minline-atomics" } */ ++ ++/* Test the execution of the __atomic_compare_exchange_n builtin for a short. */ ++ ++extern void abort(void); ++ ++short v = 0; ++short expected = 0; ++short max = ~0; ++short desired = ~0; ++short zero = 0; ++ ++#define STRONG 0 ++#define WEAK 1 ++ ++int ++main () ++{ ++ ++ if (!__atomic_compare_exchange_n (&v, &expected, max, STRONG , __ATOMIC_RELAXED, __ATOMIC_RELAXED)) ++ abort (); ++ if (expected != 0) ++ abort (); ++ ++ if (__atomic_compare_exchange_n (&v, &expected, 0, STRONG , __ATOMIC_ACQUIRE, __ATOMIC_RELAXED)) ++ abort (); ++ if (expected != max) ++ abort (); ++ ++ if (!__atomic_compare_exchange_n (&v, &expected, 0, STRONG , __ATOMIC_RELEASE, __ATOMIC_ACQUIRE)) ++ abort (); ++ if (expected != max) ++ abort (); ++ if (v != 0) ++ abort (); ++ ++ if (__atomic_compare_exchange_n (&v, &expected, desired, WEAK, __ATOMIC_ACQ_REL, __ATOMIC_ACQUIRE)) ++ abort (); ++ if (expected != 0) ++ abort (); ++ ++ if (!__atomic_compare_exchange_n (&v, &expected, desired, STRONG , __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST)) ++ abort (); ++ if (expected != 0) ++ abort (); ++ if (v != max) ++ abort (); ++ ++ /* Now test the generic version. */ ++ ++ v = 0; ++ ++ if (!__atomic_compare_exchange (&v, &expected, &max, STRONG, __ATOMIC_RELAXED, __ATOMIC_RELAXED)) ++ abort (); ++ if (expected != 0) ++ abort (); ++ ++ if (__atomic_compare_exchange (&v, &expected, &zero, STRONG , __ATOMIC_ACQUIRE, __ATOMIC_RELAXED)) ++ abort (); ++ if (expected != max) ++ abort (); ++ ++ if (!__atomic_compare_exchange (&v, &expected, &zero, STRONG , __ATOMIC_RELEASE, __ATOMIC_ACQUIRE)) ++ abort (); ++ if (expected != max) ++ abort (); ++ if (v != 0) ++ abort (); ++ ++ if (__atomic_compare_exchange (&v, &expected, &desired, WEAK, __ATOMIC_ACQ_REL, __ATOMIC_ACQUIRE)) ++ abort (); ++ if (expected != 0) ++ abort (); ++ ++ if (!__atomic_compare_exchange (&v, &expected, &desired, STRONG , __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST)) ++ abort (); ++ if (expected != 0) ++ abort (); ++ if (v != max) ++ abort (); ++ ++ return 0; ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/riscv/inline-atomics-7.c +@@ -0,0 +1,69 @@ ++/* Test __atomic routines for existence and proper execution on 1 byte ++ values with each valid memory model. */ ++/* Duplicate logic as libatomic/testsuite/libatomic.c/atomic-exchange-1.c */ ++/* { dg-do run } */ ++/* { dg-options "-minline-atomics" } */ ++ ++/* Test the execution of the __atomic_exchange_n builtin for a char. */ ++ ++extern void abort(void); ++ ++char v, count, ret; ++ ++int ++main () ++{ ++ v = 0; ++ count = 0; ++ ++ if (__atomic_exchange_n (&v, count + 1, __ATOMIC_RELAXED) != count) ++ abort (); ++ count++; ++ ++ if (__atomic_exchange_n (&v, count + 1, __ATOMIC_ACQUIRE) != count) ++ abort (); ++ count++; ++ ++ if (__atomic_exchange_n (&v, count + 1, __ATOMIC_RELEASE) != count) ++ abort (); ++ count++; ++ ++ if (__atomic_exchange_n (&v, count + 1, __ATOMIC_ACQ_REL) != count) ++ abort (); ++ count++; ++ ++ if (__atomic_exchange_n (&v, count + 1, __ATOMIC_SEQ_CST) != count) ++ abort (); ++ count++; ++ ++ /* Now test the generic version. */ ++ ++ count++; ++ ++ __atomic_exchange (&v, &count, &ret, __ATOMIC_RELAXED); ++ if (ret != count - 1 || v != count) ++ abort (); ++ count++; ++ ++ __atomic_exchange (&v, &count, &ret, __ATOMIC_ACQUIRE); ++ if (ret != count - 1 || v != count) ++ abort (); ++ count++; ++ ++ __atomic_exchange (&v, &count, &ret, __ATOMIC_RELEASE); ++ if (ret != count - 1 || v != count) ++ abort (); ++ count++; ++ ++ __atomic_exchange (&v, &count, &ret, __ATOMIC_ACQ_REL); ++ if (ret != count - 1 || v != count) ++ abort (); ++ count++; ++ ++ __atomic_exchange (&v, &count, &ret, __ATOMIC_SEQ_CST); ++ if (ret != count - 1 || v != count) ++ abort (); ++ count++; ++ ++ return 0; ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/riscv/inline-atomics-8.c +@@ -0,0 +1,69 @@ ++/* Test __atomic routines for existence and proper execution on 2 byte ++ values with each valid memory model. */ ++/* Duplicate logic as libatomic/testsuite/libatomic.c/atomic-exchange-2.c */ ++/* { dg-do run } */ ++/* { dg-options "-minline-atomics" } */ ++ ++/* Test the execution of the __atomic_X builtin for a short. */ ++ ++extern void abort(void); ++ ++short v, count, ret; ++ ++int ++main () ++{ ++ v = 0; ++ count = 0; ++ ++ if (__atomic_exchange_n (&v, count + 1, __ATOMIC_RELAXED) != count) ++ abort (); ++ count++; ++ ++ if (__atomic_exchange_n (&v, count + 1, __ATOMIC_ACQUIRE) != count) ++ abort (); ++ count++; ++ ++ if (__atomic_exchange_n (&v, count + 1, __ATOMIC_RELEASE) != count) ++ abort (); ++ count++; ++ ++ if (__atomic_exchange_n (&v, count + 1, __ATOMIC_ACQ_REL) != count) ++ abort (); ++ count++; ++ ++ if (__atomic_exchange_n (&v, count + 1, __ATOMIC_SEQ_CST) != count) ++ abort (); ++ count++; ++ ++ /* Now test the generic version. */ ++ ++ count++; ++ ++ __atomic_exchange (&v, &count, &ret, __ATOMIC_RELAXED); ++ if (ret != count - 1 || v != count) ++ abort (); ++ count++; ++ ++ __atomic_exchange (&v, &count, &ret, __ATOMIC_ACQUIRE); ++ if (ret != count - 1 || v != count) ++ abort (); ++ count++; ++ ++ __atomic_exchange (&v, &count, &ret, __ATOMIC_RELEASE); ++ if (ret != count - 1 || v != count) ++ abort (); ++ count++; ++ ++ __atomic_exchange (&v, &count, &ret, __ATOMIC_ACQ_REL); ++ if (ret != count - 1 || v != count) ++ abort (); ++ count++; ++ ++ __atomic_exchange (&v, &count, &ret, __ATOMIC_SEQ_CST); ++ if (ret != count - 1 || v != count) ++ abort (); ++ count++; ++ ++ return 0; ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/riscv/rvv/base/pr109535.c +@@ -0,0 +1,11 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d" } */ ++ ++#include "riscv_vector.h" ++ ++void foo(void *in1, void *in2, void *in3, void *out, size_t vl) { ++ vint8m1_t a = __riscv_vle8_v_i8m1(in1, vl); ++ vint8m1_t b = __riscv_vadd_vx_i8m1 (a, vl, vl); ++ __riscv_vse8_v_i8m1(out, b, vl); ++} ++ +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109547.c +@@ -0,0 +1,14 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-schedule-insns -fno-schedule-insns2" } */ ++ ++#include "riscv_vector.h" ++ ++void func(unsigned char *out, unsigned char *in, unsigned long len) { ++ unsigned long i = 0; ++ while (i < len) { ++ unsigned long vl = __riscv_vsetvl_e8m1(len - i); ++ vuint8m1_t r = __riscv_vle8_v_u8m1(in + i, vl); ++ __riscv_vse8_v_u8m1(out + i, r, vl); ++ i += vl; ++ } ++/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */} +--- a/src/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c ++++ b/src/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c +@@ -11,4 +11,4 @@ void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, int c + __riscv_vse32_v_i32m1(out, c, __riscv_vsetvl_e8mf2 (vl)); + } + +-/* { dg-final { scan-assembler-times {vsetvli} 8 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/sparc/pr109541.c +@@ -0,0 +1,23 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O1 -mcpu=niagara4 -fpic -w" } */ ++ ++int rhash_sha512_process_block_A, rhash_sha512_process_block_i, ++rhash_sha512_process_block_block, rhash_sha512_process_block_W_0; ++ ++unsigned rhash_sha512_process_block_W_2; ++ ++void rhash_sha512_process_block (void) ++{ ++ unsigned C, E, F, G, H, W_0, W_4, W_9, W_5, W_3, T1; ++ ++ for (; rhash_sha512_process_block_i; rhash_sha512_process_block_i += 6) { ++ T1 = F + (rhash_sha512_process_block_W_2 += 6); ++ rhash_sha512_process_block_A += H & G + (W_5 += rhash_sha512_process_block_W_0); ++ H = C & T1 & E ^ F + (W_9 += rhash_sha512_process_block_W_0); ++ G = T1 ^ 6 + (W_0 += rhash_sha512_process_block_block); ++ F = (unsigned) &G; ++ T1 = (unsigned) (&T1 + (W_3 += rhash_sha512_process_block_block > 9 > W_4)); ++ C = (unsigned) (T1 + &E); ++ W_4 += W_5 += rhash_sha512_process_block_W_0; ++ } ++} +--- a/src/gcc/testsuite/gdc.dg/Wbuiltin_declaration_mismatch2.d ++++ b/src/gcc/testsuite/gdc.dg/Wbuiltin_declaration_mismatch2.d +@@ -77,32 +77,32 @@ void test_shuffle() + + void test_shufflevector() + { +- shufflevector!(int, int4, int)(0, 0, 0); // { dg-warning "mismatch in argument 1" } +- shufflevector!(double, int4, int)(0, 0, 0); // { dg-warning "mismatch in argument 1" } +- shufflevector!(fake4, int4, int)(f, 0, 0); // { dg-warning "mismatch in argument 1" } +- +- shufflevector!(int4, int, int)(0, 0, 0); // { dg-warning "mismatch in argument 2" } +- shufflevector!(int4, double, int)(0, 0, 0); // { dg-warning "mismatch in argument 2" } +- shufflevector!(int4, int4, int)(0, 0, 0); +- shufflevector!(int4, short8, int)(0, 0, 0); // { dg-error "mismatch in argument 2" } +- shufflevector!(int4, float4, int)(0, 0, 0); // { dg-error "mismatch in argument 2" } +- shufflevector!(int4, byte16, int)(0, 0, 0); // { dg-error "mismatch in argument 2" } +- shufflevector!(int4, fake4, int)(0, f, 0); // { dg-warning "mismatch in argument 2" } +- +- shufflevector!(int4, int4, double)(0, 0, 0); // { dg-warning "mismatch in argument 3" } +- shufflevector!(int4, int4, int4)(0, 0, 0); // { dg-warning "mismatch in argument 3" } +- shufflevector!(int4, int4, short8)(0, 0, 0); // { dg-warning "mismatch in argument 3" } +- shufflevector!(int4, int4, float4)(0, 0, 0); // { dg-warning "mismatch in argument 3" } +- shufflevector!(int4, int4, byte16)(0, 0, 0); // { dg-warning "mismatch in argument 3" } +- +- shufflevector!(int4, int4, int, double)(0, 0, 0, 0); // { dg-warning "mismatch in argument 4" } ++ shufflevector!(int, int4, int, int, int, int)(0, 0, 0, 0, 0, 0); // { dg-warning "mismatch in argument 1" } ++ shufflevector!(double, int4, int, int, int, int)(0, 0, 0, 0, 0, 0); // { dg-warning "mismatch in argument 1" } ++ shufflevector!(fake4, int4, int, int, int, int)(f, 0, 0, 0, 0, 0); // { dg-warning "mismatch in argument 1" } ++ ++ shufflevector!(int4, int, int, int, int, int)(0, 0, 0, 0, 0, 0); // { dg-warning "mismatch in argument 2" } ++ shufflevector!(int4, double, int, int, int, int)(0, 0, 0, 0, 0, 0); // { dg-warning "mismatch in argument 2" } ++ shufflevector!(int4, int4, int, int, int, int)(0, 0, 0, 0, 0, 0); ++ shufflevector!(int4, short8, int, int, int, int)(0, 0, 0, 0, 0, 0); // { dg-error "mismatch in argument 2" } ++ shufflevector!(int4, float4, int, int, int, int)(0, 0, 0, 0, 0, 0); // { dg-error "mismatch in argument 2" } ++ shufflevector!(int4, byte16, int, int, int, int)(0, 0, 0, 0, 0, 0); // { dg-error "mismatch in argument 2" } ++ shufflevector!(int4, fake4, int, int, int, int)(0, f, 0, 0, 0, 0); // { dg-warning "mismatch in argument 2" } ++ ++ shufflevector!(int4, int4, double, int, int, int)(0, 0, 0, 0, 0, 0); // { dg-warning "mismatch in argument 3" } ++ shufflevector!(int4, int4, int4, int, int, int)(0, 0, 0, 0, 0, 0); // { dg-warning "mismatch in argument 3" } ++ shufflevector!(int4, int4, short8, int, int, int)(0, 0, 0, 0, 0, 0); // { dg-warning "mismatch in argument 3" } ++ shufflevector!(int4, int4, float4, int, int, int)(0, 0, 0, 0, 0, 0); // { dg-warning "mismatch in argument 3" } ++ shufflevector!(int4, int4, byte16, int, int, int)(0, 0, 0, 0, 0, 0); // { dg-warning "mismatch in argument 3" } ++ ++ shufflevector!(int4, int4, int, double, int, int)(0, 0, 0, 0, 0, 0); // { dg-warning "mismatch in argument 4" } + shufflevector!(int4, int4, int, int, double, int)(0, 0, 0, 0, 0, 0); // { dg-warning "mismatch in argument 5" } + shufflevector!(int4, int4, int, int, int, double)(0, 0, 0, 0, 0, 0); // { dg-warning "mismatch in argument 6" } + + int i; +- shufflevector!(int4, int4, int)(0, 0, i); // { dg-error "argument .i. cannot be read at compile time" } +- shufflevector!(int4, int4, int)(0, 0, -1u); // { dg-error "element index .-1. is out of bounds" } +- shufflevector!(int4, int4, int)(0, 0, 8); // { dg-error "element index .8. is out of bounds" } ++ shufflevector!(int4, int4, int, int, int, int)(0, 0, i, 0, 0, 0); // { dg-error "argument .i. cannot be read at compile time" } ++ shufflevector!(int4, int4, int, int, int, int)(0, 0, -1u, 0, 0, 0); // { dg-error "element index .-1. is out of bounds" } ++ shufflevector!(int4, int4, int, int, int, int)(0, 0, 8, 0, 0, 0); // { dg-error "element index .8. is out of bounds" } + } + + void test_convertvector() +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gdc.dg/Wmismatched_enum.d +@@ -0,0 +1,4 @@ ++// { dg-do compile } ++// { dg-options "-Wmismatched-special-enum" } ++ ++enum __c_longlong : byte; // { dg-warning "differ from its declared size" } +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gdc.dg/pr108842.d +@@ -0,0 +1,4 @@ ++// { dg-do compile } ++// { dg-options "-fno-rtti" } ++module object; ++enum int[] x = [0, 1, 2]; +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gdc.dg/pr108962.d +@@ -0,0 +1,13 @@ ++// https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108962 ++// { dg-do compile } ++// { dg-options "-fno-exceptions -fdump-tree-original" } ++extern(C) void main() ++{ ++ final switch (0) ++ { ++ case 1: ++ return; ++ } ++} ++// { dg-final { scan-tree-dump-times "_d_assert_msg" 1 "original" } } ++// { dg-final { scan-tree-dump-not "_d_throw" "original" } } +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gdc.dg/pr110359.d +@@ -0,0 +1,22 @@ ++// https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110359 ++// { dg-do compile } ++// { dg-options "-fdump-tree-original" } ++double pow(in double x, in ulong p) ++{ ++ import gcc.builtins : __builtin_expect; ++ if (__builtin_expect(p == 0, false)) ++ return 1; ++ if (__builtin_expect(p == 1, false)) ++ return x; ++ ++ double s = x; ++ double v = 1; ++ for (ulong i = p; i > 1; i >>= 1) ++ { ++ v = (i & 0x1) ? s * v : v; ++ s = s * s; ++ } ++ return v * s; ++} ++// { dg-final { scan-tree-dump "if \\(__builtin_expect \\(p == 0, 0\\) != 0\\)" "original" } } ++// { dg-final { scan-tree-dump "if \\(__builtin_expect \\(p == 1, 0\\) != 0\\)" "original" } } +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gdc.dg/pr110471a.d +@@ -0,0 +1,5 @@ ++// https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110471 ++// { dg-do compile } ++// { dg-options "-fno-exceptions" } ++version (D_Exceptions) ++ static assert(0); +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gdc.dg/pr110471b.d +@@ -0,0 +1,5 @@ ++// https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110471 ++// { dg-do compile } ++// { dg-options "-fno-moduleinfo" } ++version (D_ModuleInfo) ++ static assert(0); +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gdc.dg/pr110471c.d +@@ -0,0 +1,5 @@ ++// https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110471 ++// { dg-do compile } ++// { dg-options "-fno-rtti" } ++version (D_TypeInfo) ++ static assert(0); +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gdc.dg/pr110514a.d +@@ -0,0 +1,9 @@ ++// { dg-do "compile" } ++// { dg-options "-O -fdump-tree-optimized" } ++immutable uint[] imm_arr = [1,2,3]; ++int test_imm(immutable uint[] ptr) ++{ ++ return imm_arr[2] == 3 ? 123 : 456; ++} ++// { dg-final { scan-assembler-not "_d_arraybounds_indexp" } } ++// { dg-final { scan-tree-dump "return 123;" optimized } } +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gdc.dg/pr110514b.d +@@ -0,0 +1,8 @@ ++// { dg-do "compile" } ++// { dg-options "-O" } ++immutable uint[] imm_ctor_arr; ++int test_imm_ctor(immutable uint[] ptr) ++{ ++ return imm_ctor_arr[2] == 3; ++} ++// { dg-final { scan-assembler "_d_arraybounds_indexp" } } +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gdc.dg/pr110514c.d +@@ -0,0 +1,8 @@ ++// { dg-do "compile" } ++// { dg-options "-O" } ++const uint[] cst_arr = [1,2,3]; ++int test_cst(const uint[] ptr) ++{ ++ return cst_arr[2] == 3; ++} ++// { dg-final { scan-assembler "_d_arraybounds_indexp" } } +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gdc.dg/pr110514d.d +@@ -0,0 +1,8 @@ ++// { dg-do "compile" } ++// { dg-options "-O" } ++const uint[] cst_ctor_arr; ++int test_cst_ctor(const uint[] ptr) ++{ ++ return cst_ctor_arr[2] == 3; ++} ++// { dg-final { scan-assembler "_d_arraybounds_indexp" } } +--- a/src/gcc/testsuite/gdc.dg/pr98277.d ++++ b/src/gcc/testsuite/gdc.dg/pr98277.d +@@ -11,3 +11,14 @@ ref int getSide(Side side, return ref int left, return ref int right) + { + return side == Side.left ? left : right; + } ++ ++enum SideA : int[] ++{ ++ left = [0], ++ right = [1], ++} ++ ++int getSideA(SideA side, ref int left, ref int right) ++{ ++ return side == SideA.left ? left : right; ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gdc.dg/torture/pr110406.d +@@ -0,0 +1,25 @@ ++// https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110406 ++// { dg-do compile { target i?86-*-* x86_64-*-* } } ++// { dg-options "-fdump-tree-optimized" } ++struct cpuid_abcd_t ++{ ++ uint eax; ++ uint ebx; ++ uint ecx; ++ uint edx; ++}; ++ ++cpuid_abcd_t cpuid_insn(const uint in_eax) ++{ ++ cpuid_abcd_t ret = void; ++ asm { "cpuid" ++ : "=a" (ret.eax), ++ "=b" (ret.ebx), ++ "=c" (ret.ecx), ++ "=d" (ret.edx) ++ : "a" (in_eax) ++ :; ++ } ++ return ret; ++} ++// { dg-final { scan-tree-dump-not "MEM " "optimized" } } +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gdc.dg/torture/pr110516a.d +@@ -0,0 +1,12 @@ ++// https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110516 ++// { dg-do compile } ++// { dg-options "-fno-moduleinfo -fdump-tree-optimized" } ++void fn110516(ubyte* ptr) ++{ ++ import core.volatile : volatileLoad; ++ volatileLoad(ptr); ++ volatileLoad(ptr); ++ volatileLoad(ptr); ++ volatileLoad(ptr); ++} ++// { dg-final { scan-tree-dump-times " ={v} " 4 "optimized" } } +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gdc.dg/torture/pr110516b.d +@@ -0,0 +1,12 @@ ++// https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110516 ++// { dg-do compile } ++// { dg-options "-fno-moduleinfo -fdump-tree-optimized" } ++void fn110516(ubyte* ptr) ++{ ++ import core.volatile : volatileStore; ++ volatileStore(ptr, 0); ++ volatileStore(ptr, 0); ++ volatileStore(ptr, 0); ++ volatileStore(ptr, 0); ++} ++// { dg-final { scan-tree-dump-times " ={v} " 4 "optimized" } } +--- a/src/gcc/testsuite/gdc.test/compilable/shared.d ++++ b/src/gcc/testsuite/gdc.test/compilable/shared.d +@@ -11,34 +11,48 @@ ref shared(int) f(return shared ref int y) + } + + // https://issues.dlang.org/show_bug.cgi?id=20908 ++struct S ++{ ++ int i = 2; ++} ++ ++union U ++{ ++ int i = 1; ++ bool b; ++} ++ + void test20908() + { +- // shared locals (or struct members) should be able to be initialised: +- shared int x; ++ // shared locals (or struct members) should be able to be initialised: ++ shared int x; + +- ref shared(int) fun() +- { +- static shared(int) val; ++ ref shared(int) fun() ++ { ++ static shared(int) val; + +- // return by reference +- return val; +- } ++ // return by reference ++ return val; ++ } + +- ref shared(int) fun2() +- { +- static shared(int)* val; ++ ref shared(int) fun2() ++ { ++ static shared(int)* val; + +- // transfer pointer to reference +- return *val; +- } ++ // transfer pointer to reference ++ return *val; ++ } + +- ref shared(int) fun3() +- { +- static shared(int)*** val; ++ ref shared(int) fun3() ++ { ++ static shared(int)*** val; ++ ++ // Multiple indirections ++ return ***val; ++ } + +- // Multiple indirections +- return ***val; +- } ++ shared S s; ++ shared U u; + } + + // Simple tests for `DotVarExp` +@@ -130,3 +144,15 @@ void main() + { + auto b = new shared Class(); + } ++ ++// https://issues.dlang.org/show_bug.cgi?id=23790 ++bool cas(shared bool*, bool, bool) { return true; } ++ ++struct Argh ++{ ++ bool locked; ++ void lock() shared ++ { ++ while(!cas(&locked, false, true)) {} ++ } ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gdc.test/compilable/test22739.d +@@ -0,0 +1,10 @@ ++// https://issues.dlang.org/show_bug.cgi?id=22739 ++ ++extern(C++) auto f(T)() ++{ ++ return T.init; ++} ++void main() ++{ ++ f!int; ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gdc.test/compilable/test23799.d +@@ -0,0 +1,37 @@ ++// https://issues.dlang.org/show_bug.cgi?id=23799 ++ ++// REQUIRED_ARGS: -betterC ++ ++struct Data ++{ ++ Data[] range; ++ string test; ++} ++ ++Data[] foo() ++{ ++ Data[] ret; ++ if (__ctfe) ++ { ++ Data tmp; ++ tmp.range ~= Data.init; ++ ret ~= tmp; ++ } ++ return ret; ++} ++ ++void func(Data dat)() ++{ ++} ++ ++void bar(Data dat)() ++{ ++ if (dat.test.length) ++ func!(dat.range[0])(); ++} ++ ++extern (C) void main() ++{ ++ static immutable data = foo(); ++ bar!(data[0])(); ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gdc.test/compilable/test23978.d +@@ -0,0 +1,30 @@ ++// REQUIRED_ARGS: -preview=dip1021 -lowmem ++// https://issues.dlang.org/show_bug.cgi?id=23978 ++ ++// Note: this is a memory corruption bug. ++// Memory returned by `GC.realloc` retains references to old memory in it, ++// mostly because of the smallarray optimization for `Array(T)`. ++// If this fails again, it might not be consistent, so try running it multiple times. ++ ++class LUBench { } ++void lup(ulong , ulong , int , int = 1) ++{ ++ new LUBench; ++} ++void lup_3200(ulong iters, ulong flops) ++{ ++ lup(iters, flops, 3200); ++} ++void raytrace() ++{ ++ struct V ++ { ++ float x, y, z; ++ auto normalize() { } ++ struct Tid { } ++ auto spawnLinked() { } ++ string[] namesByTid; ++ class MessageBox { } ++ auto cross() { } ++ } ++} +--- a/src/gcc/testsuite/gdc.test/fail_compilation/bug9631.d ++++ b/src/gcc/testsuite/gdc.test/fail_compilation/bug9631.d +@@ -4,7 +4,7 @@ TEST_OUTPUT: + fail_compilation/bug9631.d(20): Error: cannot implicitly convert expression `F()` of type `bug9631.T1!().F` to `bug9631.T2!().F` + --- + */ +- ++// DISABLED: win32 + template T1() + { + struct F { } +--- a/src/gcc/testsuite/gdc.test/fail_compilation/cerrors.d ++++ b/src/gcc/testsuite/gdc.test/fail_compilation/cerrors.d +@@ -1,10 +1,12 @@ + /* REQUIRED_ARGS: -wi + TEST_OUTPUT: + --- +-fail_compilation/cerrors.d(11): Error: C preprocessor directive `#if` is not supported, use `version` or `static if` +-fail_compilation/cerrors.d(11): Error: declaration expected, not `#` +-fail_compilation/cerrors.d(15): Warning: C preprocessor directive `#endif` is not supported +-fail_compilation/cerrors.d(15): Error: declaration expected, not `#` ++fail_compilation/cerrors.d(13): Error: C preprocessor directive `#if` is not supported, use `version` or `static if` ++fail_compilation/cerrors.d(13): Error: declaration expected, not `#` ++fail_compilation/cerrors.d(17): Error: C preprocessor directive `#endif` is not supported ++fail_compilation/cerrors.d(17): Error: declaration expected, not `#` ++fail_compilation/cerrors.d(21): Error: token string requires valid D tokens, not `#if` ++fail_compilation/cerrors.d(22): Deprecation: token string requires valid D tokens, not `#include` + --- + */ + +@@ -13,3 +15,9 @@ fail_compilation/cerrors.d(15): Error: declaration expected, not `#` + void test(wchar_t u); + + #endif ++ ++// https://issues.dlang.org/show_bug.cgi?id=23792 ++enum s1 = q{ ++#if 1 ++#include ++}; +--- a/src/gcc/testsuite/gdc.test/fail_compilation/fail17646.d ++++ b/src/gcc/testsuite/gdc.test/fail_compilation/fail17646.d +@@ -4,7 +4,7 @@ EXTRA_FILES: imports/fail17646.d + TEST_OUTPUT: + --- + fail_compilation/imports/fail17646.d(10): Error: found `}` instead of statement +-fail_compilation/fail17646.d(11): Error: function `fail17646.runTests!"".runTests` has no `return` statement, but is expected to return a value of type `int` ++fail_compilation/fail17646.d(15): Error: template instance `allTestData!Modules` template `allTestData` is not defined + fail_compilation/fail17646.d(18): Error: template instance `fail17646.runTests!""` error instantiating + --- + */ +--- a/src/gcc/testsuite/gdc.test/fail_compilation/fail19948.d ++++ b/src/gcc/testsuite/gdc.test/fail_compilation/fail19948.d +@@ -7,7 +7,7 @@ fail_compilation/fail19948.d(15): Error: function `fail19948.func(const(X))` is + fail_compilation/fail19948.d(15): cannot pass argument `X()` of type `fail19948.main.X` to parameter `const(fail19948.X)` + --- + */ +- ++// DISABLED: win32 + struct X {} + void main() + { +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gdc.test/fail_compilation/fail22857.d +@@ -0,0 +1,18 @@ ++// https://issues.dlang.org/show_bug.cgi?id=22857 ++// EXTRA_FILES: imports/import22857.d ++ ++/* ++TEST_OUTPUT: ++--- ++fail_compilation/imports/import22857.d(4): Error: (expression) expected following `static if` ++fail_compilation/imports/import22857.d(4): Error: declaration expected, not `}` ++fail_compilation/fail22857.d(17): Error: template instance `unaryFun!()` template `unaryFun` is not defined ++--- ++*/ ++ ++void isPrettyPropertyName() ++{ ++ import imports.import22857; ++ ++ unaryFun!(); ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gdc.test/fail_compilation/fail23816.d +@@ -0,0 +1,16 @@ ++// https://issues.dlang.org/show_bug.cgi?id=23816 ++ ++/* ++TEST_OUTPUT: ++--- ++fail_compilation/fail23816.d(14): Error: opcode expected, not `NOP` ++--- ++*/ ++ ++void main() ++{ ++ asm ++ { ++ NOP; ++ } ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gdc.test/fail_compilation/imports/import22857.d +@@ -0,0 +1,4 @@ ++template unaryFun() ++{ ++ static if ++} +--- a/src/gcc/testsuite/gdc.test/fail_compilation/shared.d ++++ b/src/gcc/testsuite/gdc.test/fail_compilation/shared.d +@@ -259,3 +259,22 @@ void test_casting_safe() @safe + auto x1 = cast(int*)s; + auto x2 = cast(const(shared(int*)))s; + } ++ ++#line 3100 ++ ++// https://issues.dlang.org/show_bug.cgi?id=23783 ++ ++/* ++TEST_OUTPUT: ++--- ++fail_compilation/shared.d(3114): Error: direct access to shared `x` is not allowed, see `core.atomic` ++fail_compilation/shared.d(3115): Error: direct access to shared `x` is not allowed, see `core.atomic` ++--- ++*/ ++ ++void test23783() ++{ ++ shared int x = 3; ++ assert(x == 3); ++ bool b = x == 3; ++} +--- a/src/gcc/testsuite/gdc.test/fail_compilation/test21164.d ++++ b/src/gcc/testsuite/gdc.test/fail_compilation/test21164.d +@@ -3,7 +3,8 @@ TEST_OUTPUT: + --- + fail_compilation/imports/test21164d.d(3): Error: (expression) expected following `static if` + fail_compilation/imports/test21164d.d(3): Error: found `}` instead of statement +-fail_compilation/test21164.d(11): Error: template instance `test21164a.D!(R!(O(), 1))` error instantiating ++fail_compilation/imports/test21164a.d(5): Error: undefined identifier `I` ++fail_compilation/test21164.d(12): Error: template instance `test21164a.D!(R!(O(), 1))` error instantiating + --- + */ + import imports.test21164a; +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gdc.test/runnable/complex3.d +@@ -0,0 +1,31 @@ ++// https://issues.dlang.org/show_bug.cgi?id=23778 ++ ++ ++enum __c_long_double : double; ++ ++alias __c_long_double c_long_double; ++ ++struct _Complex ++{ ++ c_long_double re; ++ c_long_double im; ++} ++ ++version (all) // bug to test ++{ ++ enum __c_complex_real : _Complex; ++ alias c_complex_real = __c_complex_real; ++} ++else // works ++ enum c_complex_real : _Complex; ++ ++c_complex_real toNative2(real re, real im) ++{ ++ return c_complex_real(re, im); ++} ++ ++void main() ++{ ++ c_complex_real n = toNative2(123, 456); ++ assert(123 == n.re && 456 == n.im); ++} +--- a/src/gcc/testsuite/gfortran.dg/allocatable_function_1.f90 ++++ b/src/gcc/testsuite/gfortran.dg/allocatable_function_1.f90 +@@ -107,4 +107,4 @@ contains + end function bar + + end program alloc_fun +-! { dg-final { scan-tree-dump-times "free" 10 "original" } } ++! { dg-final { scan-tree-dump-times "__builtin_free " 10 "original" } } +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gfortran.dg/findloc_9.f90 +@@ -0,0 +1,19 @@ ++! { dg-do compile } ++! { dg-options "-fdump-tree-original" } ++! PR fortran/110585 - simplification of FINDLOC for constant complex arguments ++ ++program mvce ++ implicit none ++ integer, parameter :: a(*) = findloc([(1.,0.),(2.,1.)], (2.,0.)) ++ integer, parameter :: b(*) = findloc([(1.,0.),(2.,1.)], (2.,0.), back=.true.) ++ integer, parameter :: c(*) = findloc([(1.,0.),(2.,1.)], (2.,1.)) ++ integer, parameter :: d(*) = findloc([(1.,0.),(2.,1.)], (2.,1.), back=.true.) ++ integer, parameter :: e = findloc([(1.,0.),(2.,1.)], (2.,1.), dim=1) ++ if (a(1) /= 0) stop 1 ++ if (b(1) /= 0) stop 2 ++ if (c(1) /= 2) stop 3 ++ if (d(1) /= 2) stop 4 ++ if (e /= 2) stop 5 ++end ++ ++! { dg-final { scan-tree-dump-not "_gfortran_stop_numeric" "original" } } +--- a/src/gcc/testsuite/gfortran.dg/goacc/attach-descriptor.f90 ++++ b/src/gcc/testsuite/gfortran.dg/goacc/attach-descriptor.f90 +@@ -11,19 +11,19 @@ program att + integer, pointer :: myptr(:) + + !$acc enter data attach(myvar%arr2, myptr) +-! { dg-final { scan-tree-dump-times "(?n)#pragma acc enter data map\\(attach:myvar\\.arr2 \\\[bias: 0\\\]\\) map\\(to:myptr \\\[pointer set, len: \[0-9\]+\\\]\\) map\\(attach:\\(integer\\(kind=4\\)\\\[0:\\\] \\*\\) myptr\\.data \\\[bias: 0\\\]\\);$" 1 "original" } } +-! { dg-final { scan-tree-dump-times "(?n)#pragma omp target oacc_enter_data map\\(attach:myvar\\.arr2 \\\[bias: 0\\\]\\) map\\(to:myptr \\\[pointer set, len: \[0-9\]+\\\]\\) map\\(attach:myptr\\.data \\\[bias: 0\\\]\\)$" 1 "gimple" } } ++! { dg-final { scan-tree-dump-times "(?n)#pragma acc enter data map\\(attach:\\(integer\\(kind=4\\)\\\[0:\\\] \\* restrict\\) myvar\\.arr2\\.data \\\[bias: 0\\\]\\) map\\(to:myptr \\\[pointer set, len: \[0-9\]+\\\]\\) map\\(attach:\\(integer\\(kind=4\\)\\\[0:\\\] \\*\\) myptr\\.data \\\[bias: 0\\\]\\);$" 1 "original" } } ++! { dg-final { scan-tree-dump-times "(?n)#pragma omp target oacc_enter_data map\\(attach:myvar\\.arr2\\.data \\\[bias: 0\\\]\\) map\\(to:myptr \\\[pointer set, len: \[0-9\]+\\\]\\) map\\(attach:myptr\\.data \\\[bias: 0\\\]\\)$" 1 "gimple" } } + + !$acc exit data detach(myvar%arr2, myptr) +-! { dg-final { scan-tree-dump-times "(?n)#pragma acc exit data map\\(detach:myvar\\.arr2 \\\[bias: 0\\\]\\) map\\(to:myptr \\\[pointer set, len: \[0-9\]+\\\]\\) map\\(detach:\\(integer\\(kind=4\\)\\\[0:\\\] \\*\\) myptr\\.data \\\[bias: 0\\\]\\);$" 1 "original" } } +-! { dg-final { scan-tree-dump-times "(?n)#pragma omp target oacc_exit_data map\\(detach:myvar\\.arr2 \\\[bias: 0\\\]\\) map\\(to:myptr \\\[pointer set, len: \[0-9\]+\\\]\\) map\\(detach:myptr\\.data \\\[bias: 0\\\]\\)$" 1 "gimple" } } ++! { dg-final { scan-tree-dump-times "(?n)#pragma acc exit data map\\(detach:\\(integer\\(kind=4\\)\\\[0:\\\] \\* restrict\\) myvar\\.arr2\\.data \\\[bias: 0\\\]\\) map\\(to:myptr \\\[pointer set, len: \[0-9\]+\\\]\\) map\\(detach:\\(integer\\(kind=4\\)\\\[0:\\\] \\*\\) myptr\\.data \\\[bias: 0\\\]\\);$" 1 "original" } } ++! { dg-final { scan-tree-dump-times "(?n)#pragma omp target oacc_exit_data map\\(detach:myvar\\.arr2\\.data \\\[bias: 0\\\]\\) map\\(to:myptr \\\[pointer set, len: \[0-9\]+\\\]\\) map\\(detach:myptr\\.data \\\[bias: 0\\\]\\)$" 1 "gimple" } } + + ! Test valid usage and processing of the finalize clause. + !$acc exit data detach(myvar%arr2, myptr) finalize +-! { dg-final { scan-tree-dump-times "(?n)#pragma acc exit data map\\(detach:myvar\\.arr2 \\\[bias: 0\\\]\\) map\\(to:myptr \\\[pointer set, len: \[0-9\]+\\\]\\) map\\(detach:\\(integer\\(kind=4\\)\\\[0:\\\] \\*\\) myptr\\.data \\\[bias: 0\\\]\\) finalize;$" 1 "original" } } ++! { dg-final { scan-tree-dump-times "(?n)#pragma acc exit data map\\(detach:\\(integer\\(kind=4\\)\\\[0:\\\] \\* restrict\\) myvar\\.arr2\\.data \\\[bias: 0\\\]\\) map\\(to:myptr \\\[pointer set, len: \[0-9\]+\\\]\\) map\\(detach:\\(integer\\(kind=4\\)\\\[0:\\\] \\*\\) myptr\\.data \\\[bias: 0\\\]\\) finalize;$" 1 "original" } } + ! For array-descriptor detaches, we no longer generate a "release" mapping + ! for the pointed-to data for gimplify.c to turn into "delete". Make sure + ! the mapping still isn't there. +-! { dg-final { scan-tree-dump-times "(?n)#pragma omp target oacc_exit_data map\\(force_detach:myvar\\.arr2 \\\[bias: 0\\\]\\) map\\(to:myptr \\\[pointer set, len: \[0-9\]+\\\]\\) map\\(force_detach:myptr\\.data \\\[bias: 0\\\]\\) finalize$" 1 "gimple" } } ++! { dg-final { scan-tree-dump-times "(?n)#pragma omp target oacc_exit_data map\\(force_detach:myvar\\.arr2\\.data \\\[bias: 0\\\]\\) map\\(to:myptr \\\[pointer set, len: \[0-9\]+\\\]\\) map\\(force_detach:myptr\\.data \\\[bias: 0\\\]\\) finalize$" 1 "gimple" } } + + end program att +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gfortran.dg/goacc/pr109622-5.f90 +@@ -0,0 +1,44 @@ ++! { dg-do compile } ++ ++implicit none ++ ++type t ++integer :: foo ++character(len=8) :: bar ++integer :: qux(5) ++end type t ++ ++type(t) :: var ++ ++var%foo = 3 ++var%bar = "HELLOOMP" ++var%qux = (/ 1, 2, 3, 4, 5 /) ++ ++!$acc enter data copyin(var) ++ ++!$acc enter data attach(var%foo) ++! { dg-error "'attach' clause argument must be ALLOCATABLE or a POINTER" "" { target *-*-* } .-1 } ++!$acc enter data attach(var%bar) ++! { dg-error "'attach' clause argument must be ALLOCATABLE or a POINTER" "" { target *-*-* } .-1 } ++!$acc enter data attach(var%qux) ++! { dg-error "'attach' clause argument must be ALLOCATABLE or a POINTER" "" { target *-*-* } .-1 } ++ ++!$acc serial ++var%foo = 5 ++var%bar = "GOODBYE!" ++var%qux = (/ 6, 7, 8, 9, 10 /) ++!$acc end serial ++ ++!$acc exit data detach(var%qux) ++! { dg-error "'detach' clause argument must be ALLOCATABLE or a POINTER" "" { target *-*-* } .-1 } ++!$acc exit data detach(var%bar) ++! { dg-error "'detach' clause argument must be ALLOCATABLE or a POINTER" "" { target *-*-* } .-1 } ++!$acc exit data detach(var%foo) ++! { dg-error "'detach' clause argument must be ALLOCATABLE or a POINTER" "" { target *-*-* } .-1 } ++ ++!$acc exit data copyout(var) ++ ++if (var%foo.ne.5) stop 1 ++if (var%bar.ne."GOODBYE!") stop 2 ++ ++end +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gfortran.dg/goacc/pr109622-6.f90 +@@ -0,0 +1,8 @@ ++! { dg-do compile } ++ ++implicit none ++integer :: x ++!$acc enter data attach(x) ++! { dg-error "'attach' clause argument must be ALLOCATABLE or a POINTER" "" { target *-*-* } .-1 } ++ ++end +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gfortran.dg/overload_5.f90 +@@ -0,0 +1,118 @@ ++! { dg-do run } ++! PR fortran/109641 ++! ++! Check overloading of intrinsic binary operators for numeric operands ++! Reported by Adelson Oliveira ++ ++MODULE TESTEOP ++ IMPLICIT NONE ++ INTERFACE OPERATOR(.MULT.) ++ MODULE PROCEDURE MULTr4 ++ MODULE PROCEDURE MULTc4 ++ END INTERFACE ++ INTERFACE OPERATOR(*) ++ MODULE PROCEDURE MULTr4 ++ MODULE PROCEDURE MULTc4 ++ END INTERFACE ++ INTERFACE OPERATOR(==) ++ MODULE PROCEDURE MULTr4 ++ MODULE PROCEDURE MULTc4 ++ MODULE PROCEDURE MULTr8 ++ END INTERFACE ++ INTERFACE OPERATOR(<) ++ MODULE PROCEDURE MULTc4 ++ MODULE PROCEDURE MULTi4 ++ END INTERFACE ++ INTERFACE OPERATOR(**) ++ MODULE PROCEDURE MULTc4 ++ MODULE PROCEDURE MULTi4 ++ END INTERFACE ++ interface copy ++ MODULE PROCEDURE copy ++ end interface copy ++CONTAINS ++ elemental function copy (z) ++ complex, intent(in) :: z ++ complex :: copy ++ copy = z ++ end function copy ++ FUNCTION MULTr4(v,m) ++ REAL, INTENT(IN) :: v(:) ++ REAL, INTENT(IN) :: m(:,:) ++ REAL :: MULTr4(SIZE(m,DIM=1),SIZE(m,DIM=2)) ++ INTEGER :: i ++ FORALL(i=1:SIZE(v)) MULTr4(:,i)=m(:,i)*v(i) ++ END FUNCTION MULTr4 ++ FUNCTION MULTr8(v,m) ++ REAL, INTENT(IN) :: v(:) ++ double precision, INTENT(IN) :: m(:,:) ++ double precision :: MULTr8(SIZE(m,DIM=1),SIZE(m,DIM=2)) ++ INTEGER :: i ++ FORALL(i=1:SIZE(v)) MULTr8(:,i)=m(:,i)*v(i) ++ END FUNCTION MULTr8 ++ FUNCTION MULTc4(v,m) ++ REAL, INTENT(IN) :: v(:) ++ COMPLEX, INTENT(IN) :: m(:,:) ++ COMPLEX :: MULTc4(SIZE(m,DIM=1),SIZE(m,DIM=2)) ++ INTEGER :: i ++ FORALL(i=1:SIZE(v)) MULTc4(:,i)=m(:,i)*v(i) ++ END FUNCTION MULTc4 ++ FUNCTION MULTi4(v,m) ++ REAL, INTENT(IN) :: v(:) ++ integer, INTENT(IN) :: m(:,:) ++ REAL :: MULTi4(SIZE(m,DIM=1),SIZE(m,DIM=2)) ++ INTEGER :: i ++ FORALL(i=1:SIZE(v)) MULTi4(:,i)=m(:,i)*v(i) ++ END FUNCTION MULTi4 ++END MODULE TESTEOP ++PROGRAM TESTE ++ USE TESTEOP ++ implicit none ++ type t ++ complex :: c(3,3) ++ end type t ++ real, parameter :: vv(3) = 42. ++ complex, parameter :: zz(3,3) = (1.0,0.0) ++ integer, parameter :: kk(3,3) = 2 ++ double precision :: dd(3,3) = 3.d0 ++ COMPLEX, ALLOCATABLE :: m(:,:),r(:,:), s(:,:) ++ REAL, ALLOCATABLE :: v(:) ++ type(t) :: z(1) = t(zz) ++ ALLOCATE(v(3),m(3,3),r(3,3),s(3,3)) ++ v = vv ++ m = zz ++ ! Original bug report ++ r=v.MULT.m ! Reference ++ s=v*m ++ if (any (r /= s)) stop 1 ++ if (.not. all (r == s)) stop 2 ++ ! Check other binary intrinsics ++ s=v==m ++ if (any (r /= s)) stop 3 ++ s=v==copy(m) ++ if (any (r /= s)) stop 4 ++ s=v==zz ++ if (any (r /= s)) stop 5 ++ s=v==copy(zz) ++ if (any (r /= s)) stop 6 ++ s=vv==m ++ if (any (r /= s)) stop 7 ++ s=vv==copy(m) ++ if (any (r /= s)) stop 8 ++ s=vv==zz ++ if (any (r /= s)) stop 9 ++ s=vv==copy(zz) ++ if (any (r /= s)) stop 10 ++ ! check if .eq. same operator as == etc. ++ s=v.eq.m ++ if (any (r /= s)) stop 11 ++ s=v.lt.z(1)%c ++ if (any (r /= s)) stop 12 ++ s=v<((z(1)%c)) ++ if (any (r /= s)) stop 13 ++ if (.not. all ( 1. < (vv**kk))) stop 14 ++ if (.not. all ( 1. < (vv< kk))) stop 15 ++ if (.not. all ((42.,0.) == (v < m ))) stop 16 ++ if (.not. all ((42.,0.) == (v** m ))) stop 17 ++ if (.not. all ( 126.d0 == (vv==dd))) stop 18 ++END PROGRAM TESTE +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gfortran.dg/ptr-func-5.f90 +@@ -0,0 +1,39 @@ ++! { dg-do compile } ++! PR fortran/109846 ++! CLASS pointer function result in variable definition context ++ ++module foo ++ implicit none ++ type :: parameter_list ++ contains ++ procedure :: sublist, sublist_nores ++ end type ++contains ++ function sublist (this) result (slist) ++ class(parameter_list), intent(inout) :: this ++ class(parameter_list), pointer :: slist ++ allocate (slist) ++ end function ++ function sublist_nores (this) ++ class(parameter_list), intent(inout) :: this ++ class(parameter_list), pointer :: sublist_nores ++ allocate (sublist_nores) ++ end function ++end module ++ ++program example ++ use foo ++ implicit none ++ type(parameter_list) :: plist ++ call sub1 (plist%sublist()) ++ call sub1 (plist%sublist_nores()) ++ call sub2 (plist%sublist()) ++ call sub2 (plist%sublist_nores()) ++contains ++ subroutine sub1 (plist) ++ type(parameter_list), intent(inout) :: plist ++ end subroutine ++ subroutine sub2 (plist) ++ type(parameter_list) :: plist ++ end subroutine ++end program +--- a/src/gcc/testsuite/gfortran.dg/reshape_8.f90 ++++ b/src/gcc/testsuite/gfortran.dg/reshape_8.f90 +@@ -11,4 +11,4 @@ program test + a = reshape([1,2,3,4], [2,0]) + print *, a + end +-! { dg-final { scan-tree-dump-times "data" 4 "original" } } ++! { dg-final { scan-tree-dump-not "data..0. =" "original" } } +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gfortran.dg/select_rank_6.f90 +@@ -0,0 +1,48 @@ ++! { dg-do compile } ++! PR fortran/100607 - fix diagnostics for SELECT RANK ++! Contributed by T.Burnus ++ ++program p ++ implicit none ++ integer, allocatable :: A(:,:,:) ++ ++ allocate(a(5:6,-2:2, 99:100)) ++ call foo(a) ++ call bar(a) ++ ++contains ++ ++ subroutine foo(x) ++ integer, allocatable :: x(..) ++ if (rank(x) /= 3) stop 1 ++ if (any (lbound(x) /= [5, -2, 99])) stop 2 ++ ++ select rank (x) ++ rank(3) ++ if (any (lbound(x) /= [5, -2, 99])) stop 3 ++ end select ++ ++ select rank (x) ! { dg-error "pointer or allocatable selector at .2." } ++ rank(*) ! { dg-error "pointer or allocatable selector at .2." } ++ if (rank(x) /= 1) stop 4 ++ if (lbound(x, 1) /= 1) stop 5 ++ end select ++ end ++ ++ subroutine bar(x) ++ integer :: x(..) ++ if (rank(x) /= 3) stop 6 ++ if (any (lbound(x) /= 1)) stop 7 ++ ++ select rank (x) ++ rank(3) ++ if (any (lbound(x) /= 1)) stop 8 ++ end select ++ ++ select rank (x) ++ rank(*) ++ if (rank(x) /= 1) stop 9 ++ if (lbound(x, 1) /= 1) stop 10 ++ end select ++ end ++end +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gfortran.dg/zero_sized_14.f90 +@@ -0,0 +1,181 @@ ++! { dg-do run } ++! PR fortran/86277 ++! ++! Check proper detection of presence of optional array dummy arguments ++! for zero-sized actual array arguments or array constructors: ++! tests for REAL (as non-character intrinsic type) and empty derived type ++ ++program test ++ implicit none ++ real, parameter :: m(0) = 42. ++ real, parameter :: n(1) = 23. ++ real :: x(0) = 1. ++ real :: z(1) = 2. ++ real :: w(0) ++ real, pointer :: p(:) ++ real, allocatable :: y(:) ++ integer :: k = 0, l = 0 ! Test/failure counter ++ type dt ++ ! Empty type ++ end type dt ++ type(dt), parameter :: t0(0) = dt() ++ type(dt), parameter :: t1(1) = dt() ++ type(dt) :: t2(0) = dt() ++ type(dt) :: t3(1) = dt() ++ type(dt) :: t4(0) ++ type(dt), allocatable :: tt(:) ++ ! ++ allocate (p(0)) ++ allocate (y(0)) ++ allocate (tt(0)) ++ call a0 () ++ call a1 () ++ call a2 () ++ call a3 () ++ call all_missing () ++ print *, "Total tests:", k, " failed:", l ++contains ++ subroutine a0 () ++ print *, "Variables as actual argument" ++ call i (m) ++ call i (n) ++ call i (x) ++ call i (w) ++ call i (y) ++ call i (p) ++ call j (t0) ++ call j (t1) ++ call j (t2) ++ call j (t3) ++ call j (t4) ++ call j (tt) ++ print *, "Array section as actual argument" ++ call i (m(1:0)) ++ call i (n(1:0)) ++ call i (x(1:0)) ++ call i (w(1:0)) ++ call i (z(1:0)) ++ call i (p(1:0)) ++ call j (t0(1:0)) ++ call j (t1(1:0)) ++ call j (t2(1:0)) ++ call j (t3(1:0)) ++ call j (t4(1:0)) ++ call j (tt(1:0)) ++ end subroutine a0 ++ ! ++ subroutine a1 () ++ print *, "Explicit temporary as actual argument" ++ call i ((m)) ++ call i ((n)) ++ call i ((n(1:0))) ++ call i ((x)) ++ call i ((w)) ++ call i ((z(1:0))) ++ call i ((y)) ++ call i ((p)) ++ call i ((p(1:0))) ++ call j ((t0)) ++ call j ((t1)) ++ call j ((tt)) ++ call j ((t1(1:0))) ++ call j ((tt(1:0))) ++ end subroutine a1 ++ ! ++ subroutine a2 () ++ print *, "Array constructor as actual argument" ++ call i ([m]) ++ call i ([n]) ++ call i ([x]) ++ call i ([w]) ++ call i ([z]) ++ call i ([m(1:0)]) ++ call i ([n(1:0)]) ++ call i ([m,n(1:0)]) ++ call i ([x(1:0)]) ++ call i ([w(1:0)]) ++ call i ([z(1:0)]) ++ call i ([y]) ++ call i ([p]) ++ call i ([y,y]) ++ call i ([p,p]) ++ call i ([y(1:0)]) ++ call i ([p(1:0)]) ++ call j ([t0]) ++ call j ([t0,t0]) ++ call j ([t1]) ++ call j ([tt]) ++ call j ([tt,tt]) ++ call j ([t1(1:0)]) ++ call j ([tt(1:0)]) ++ end subroutine a2 ++ ! ++ subroutine a3 () ++ print *, "Array constructor with type-spec as actual argument" ++ call i ([real:: ]) ++ call i ([real:: 7]) ++ call i ([real:: m]) ++ call i ([real:: n]) ++ call i ([real:: x]) ++ call i ([real:: w]) ++ call i ([real:: m(1:0)]) ++ call i ([real:: n(1:0)]) ++ call i ([real:: m,n(1:0)]) ++ call i ([real:: x(1:0)]) ++ call i ([real:: w(1:0)]) ++ call i ([real:: z(1:0)]) ++ call i ([real:: y]) ++ call i ([real:: p]) ++ call i ([real:: y,y]) ++ call i ([real:: p,p]) ++ call i ([real:: y(1:0)]) ++ call i ([real:: p(1:0)]) ++ call j ([ dt :: ]) ++ call j ([ dt :: t0]) ++ call j ([ dt :: t0,t0]) ++ call j ([ dt :: t1]) ++ call j ([ dt :: tt]) ++ call j ([ dt :: tt,tt]) ++ call j ([ dt :: t1(1:0)]) ++ call j ([ dt :: tt(1:0)]) ++ end subroutine a3 ++ ! ++ subroutine i (arg) ++ real, optional, intent(in) :: arg(:) ++ logical :: t ++ t = present (arg) ++ k = k + 1 ++ print *, 'test', k, merge (" ok", "FAIL", t) ++ if (.not. t) l = l + 1 ++ if (.not. t) stop k ++ end subroutine i ++ ! ++ subroutine j (arg) ++ type(dt), optional, intent(in) :: arg(:) ++ logical :: t ++ t = present (arg) ++ k = k + 1 ++ print *, 'test', k, merge (" ok", "FAIL", t) ++ if (.not. t) l = l + 1 ++ if (.not. t) stop k ++ end subroutine j ++ ! ++ subroutine all_missing (arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8) ++ real, optional, intent(in) :: arg1(:) ++ real, optional, allocatable :: arg2(:) ++ real, optional, pointer :: arg3(:) ++ character(*), optional, intent(in) :: arg4(:) ++ character(*), optional, allocatable :: arg5(:) ++ character(*), optional, pointer :: arg6(:) ++ character(:), optional, pointer :: arg7(:) ++ character(:), optional, allocatable :: arg8(:) ++ if (present (arg1)) stop 101 ++ if (present (arg2)) stop 102 ++ if (present (arg3)) stop 103 ++ if (present (arg4)) stop 104 ++ if (present (arg5)) stop 105 ++ if (present (arg6)) stop 106 ++ if (present (arg7)) stop 107 ++ if (present (arg8)) stop 108 ++ end subroutine all_missing ++end program +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gfortran.dg/zero_sized_15.f90 +@@ -0,0 +1,114 @@ ++! { dg-do run } ++! PR fortran/86277 ++! ++! Check proper detection of presence of optional array dummy arguments ++! for zero-sized actual array arguments or array constructors: ++! tests for CHARACTER ++ ++program test ++ implicit none ++ character(0), parameter :: c0(0) = "" ++ character(0), parameter :: c1(1) = "" ++ character(1), parameter :: d0(0) = "" ++ character(1), parameter :: d1(1) = "" ++ character(0) :: w0(0) ++ character(0) :: w1(1) ++ character(:), allocatable :: cc(:) ++ integer :: k = 0, l = 0 ! Test/failure counter ++ ! ++ allocate (character(0) :: cc(0)) ++ call a0 () ++ call a1 () ++ call a2 () ++ call a3 () ++ print *, "Total tests:", k, " failed:", l ++contains ++ subroutine a0 () ++ print *, "Variables as actual argument" ++ call i (c0) ++ call i (c1) ++ call i (d0) ++ call i (d1) ++ call i (w0) ++ call i (w1) ++ call i (cc) ++ print *, "Array section as actual argument" ++ call i (c1(1:0)) ++ call i (c1(1:0)(1:0)) ++ call i (w1(1:0)) ++ call i (w1(1:0)(1:0)) ++ call i (cc(1:0)) ++ call i (cc(1:0)(1:0)) ++ end subroutine a0 ++ ! ++ subroutine a1 () ++ print *, "Explicit temporary as actual argument" ++ call i ((c0)) ++ call i ((c1)) ++ call i ((d0)) ++ call i ((d1)) ++ call i ((w0)) ++ call i ((w1)) ++ call i ((cc)) ++ call i ((c1(1:0))) ++ call i ((c1(1:0)(1:0))) ++ call i ((w1(1:0))) ++ call i ((w1(1:0)(1:0))) ++ call i ((cc(1:0))) ++ call i ((cc(1:0)(1:0))) ++ end subroutine a1 ++ ! ++ subroutine a2 () ++ print *, "Array constructor as actual argument" ++ call i ([c0]) ++ call i ([c1]) ++ call i ([d0]) ++ call i ([d1]) ++ call i ([w0]) ++ call i ([w1]) ++ call i ([cc]) ++ call i ([c0,c0]) ++ call i ([c1,c1]) ++ call i ([d0,d0]) ++ call i ([cc,cc]) ++ call i ([c1(1:0)]) ++ call i ([c1(1:0)(1:0)]) ++ call i ([w1(1:0)]) ++ call i ([w1(1:0)(1:0)]) ++ call i ([cc(1:0)]) ++ call i ([cc(1:0)(1:0)]) ++ end subroutine a2 ++ ! ++ subroutine a3 () ++ print *, "Array constructor with type-spec as actual argument" ++ call i ([character(0) :: ]) ++ call i ([character(0) :: ""]) ++ call i ([character(0) :: c0]) ++ call i ([character(0) :: c1]) ++ call i ([character(0) :: d0]) ++ call i ([character(0) :: d1]) ++ call i ([character(0) :: w0]) ++ call i ([character(0) :: w1]) ++ call i ([character(0) :: cc]) ++ call i ([character(0) :: c0,c0]) ++ call i ([character(0) :: c1,c1]) ++ call i ([character(0) :: d0,d0]) ++ call i ([character(0) :: cc,cc]) ++ call i ([character(0) :: c1(1:0)]) ++ call i ([character(0) :: c1(1:0)(1:0)]) ++ call i ([character(0) :: w1(1:0)]) ++ call i ([character(0) :: w1(1:0)(1:0)]) ++ call i ([character(0) :: cc(1:0)]) ++ call i ([character(0) :: cc(1:0)(1:0)]) ++ end subroutine a3 ++ ! ++ subroutine i(arg) ++ character(*), optional, intent(in) :: arg(:) ++ logical :: t ++ t = present (arg) ++ k = k + 1 ++ print *, 'test', k, merge (" ok", "FAIL", t) ++ if (.not. t) l = l + 1 ++ if (.not. t) stop k ++ end subroutine i ++end program +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gnat.dg/opt101.adb +@@ -0,0 +1,23 @@ ++-- { dg-do run } ++-- { dg-options "-O" } ++ ++pragma Optimize_Alignment (Space); ++ ++with Opt101_Pkg; use Opt101_Pkg; ++ ++procedure Opt101 is ++ ++ C1 : Cont1; ++ C2 : Cont2; ++ ++begin ++ C1 := ((1234, 1, 2), 1, 2); ++ if C1.R.I1 /= 1 or C1.I2 /= 2 then ++ raise Program_Error; ++ end if; ++ ++ C2 := (1, (1234, 1, 2), 2); ++ if C2.R.I1 /= 1 or C2.I2 /= 2 then ++ raise Program_Error; ++ end if; ++end; +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gnat.dg/opt101_pkg.ads +@@ -0,0 +1,26 @@ ++package Opt101_Pkg is ++ ++ type Int is mod 16; ++ ++ type Rec is record ++ S : Short_Integer; ++ I1, I2 : Int; ++ end record; ++ pragma Pack (Rec); ++ for Rec'Alignment use 4; ++ ++ type Cont1 is record ++ R : Rec; ++ I1, I2 : Int; ++ end record; ++ pragma Pack (Cont1); ++ ++ type Cont2 is record ++ I1 : Int; ++ R : Rec; ++ I2 : Int; ++ end record; ++ pragma Pack (Cont2); ++ pragma No_Component_Reordering (Cont2); ++ ++end Opt101_Pkg; +--- a/src/gcc/testsuite/lib/target-supports.exp ++++ b/src/gcc/testsuite/lib/target-supports.exp +@@ -8555,7 +8555,8 @@ proc check_effective_target_vect_call_copysignf { } { + return [check_cached_effective_target_indexed vect_call_copysignf { + expr { [istarget i?86-*-*] || [istarget x86_64-*-*] + || [istarget powerpc*-*-*] +- || [istarget aarch64*-*-*] }}] ++ || [istarget aarch64*-*-*] ++ || [istarget amdgcn-*-*] }}] + } + + # Return 1 if the target supports hardware square root instructions. +@@ -8591,7 +8592,8 @@ proc check_effective_target_vect_call_sqrtf { } { || [istarget i?86-*-*] || [istarget x86_64-*-*] || ([istarget powerpc*-*-*] && [check_vsx_hw_available]) || ([istarget s390*-*-*] @@ -237079,6 +323220,15 @@ } # Return 1 if the target supports the fold_extract_last optab. +@@ -10948,7 +10953,7 @@ proc check_effective_target_aarch64_tiny { } { + # various architecture extensions via the .arch_extension pseudo-op. + + foreach { aarch64_ext } { "fp" "simd" "crypto" "crc" "lse" "dotprod" "sve" +- "i8mm" "f32mm" "f64mm" "bf16" "sb" "sve2" } { ++ "i8mm" "f32mm" "f64mm" "bf16" "sb" "sve2" "ls64" } { + eval [string map [list FUNC $aarch64_ext] { + proc check_effective_target_aarch64_asm_FUNC_ok { } { + if { [istarget aarch64*-*-*] } { --- a/src/gcc/tree-ssa-alias.cc +++ b/src/gcc/tree-ssa-alias.cc @@ -1330,7 +1330,7 @@ aliasing_component_refs_p (tree ref1, @@ -237115,6 +323265,26 @@ if (refs_may_alias_p_1 (&dref, ref, false)) return 1; } +@@ -2817,6 +2829,9 @@ ref_maybe_used_by_call_p_1 (gcall *call, ao_ref *ref, bool tbaa_p) + ao_ref_init_from_ptr_and_size (&rhs_ref, + gimple_call_arg (call, 0), + TYPE_SIZE_UNIT (TREE_TYPE (lhs))); ++ /* We cannot make this a known-size access since otherwise ++ we disambiguate against refs to decls that are smaller. */ ++ rhs_ref.size = -1; + rhs_ref.ref_alias_set = rhs_ref.base_alias_set + = tbaa_p ? get_deref_alias_set (TREE_TYPE + (gimple_call_arg (call, 1))) : 0; +@@ -3060,6 +3075,9 @@ call_may_clobber_ref_p_1 (gcall *call, ao_ref *ref, bool tbaa_p) + ao_ref lhs_ref; + ao_ref_init_from_ptr_and_size (&lhs_ref, gimple_call_arg (call, 0), + TYPE_SIZE_UNIT (TREE_TYPE (rhs))); ++ /* We cannot make this a known-size access since otherwise ++ we disambiguate against refs to decls that are smaller. */ ++ lhs_ref.size = -1; + lhs_ref.ref_alias_set = lhs_ref.base_alias_set + = tbaa_p ? get_deref_alias_set + (TREE_TYPE (gimple_call_arg (call, 1))) : 0; --- a/src/gcc/tree-ssa-ccp.cc +++ b/src/gcc/tree-ssa-ccp.cc @@ -1552,6 +1552,8 @@ bit_value_binop (enum tree_code code, signop sgn, int width, @@ -237137,8 +323307,277 @@ } break; +--- a/src/gcc/tree-ssa-ifcombine.cc ++++ b/src/gcc/tree-ssa-ifcombine.cc +@@ -128,7 +128,6 @@ bb_no_side_effects_p (basic_block bb) + gassign *ass; + enum tree_code rhs_code; + if (gimple_has_side_effects (stmt) +- || gimple_uses_undefined_value_p (stmt) + || gimple_could_trap_p (stmt) + || gimple_vuse (stmt) + /* We need to rewrite stmts with undefined overflow to use +@@ -153,6 +152,12 @@ bb_no_side_effects_p (basic_block bb) + should handle this. */ + || is_gimple_call (stmt)) + return false; ++ ++ ssa_op_iter it; ++ tree use; ++ FOR_EACH_SSA_TREE_OPERAND (use, stmt, it, SSA_OP_USE) ++ if (ssa_name_maybe_undef_p (use)) ++ return false; + } + + return true; +@@ -842,6 +847,7 @@ pass_tree_ifcombine::execute (function *fun) + + bbs = single_pred_before_succ_order (); + calculate_dominance_info (CDI_DOMINATORS); ++ mark_ssa_maybe_undefs (); + + /* Search every basic block for COND_EXPR we may be able to optimize. + +--- a/src/gcc/tree-ssa-loop-ivcanon.cc ++++ b/src/gcc/tree-ssa-loop-ivcanon.cc +@@ -1486,15 +1486,16 @@ tree_unroll_loops_completely (bool may_increase_size, bool unroll_outer) + } + BITMAP_FREE (fathers); + ++ /* Clean up the information about numbers of iterations, since ++ complete unrolling might have invalidated it. */ ++ scev_reset (); ++ + /* This will take care of removing completely unrolled loops + from the loop structures so we can continue unrolling now + innermost loops. */ + if (cleanup_tree_cfg ()) + update_ssa (TODO_update_ssa_only_virtuals); + +- /* Clean up the information about numbers of iterations, since +- complete unrolling might have invalidated it. */ +- scev_reset (); + if (flag_checking && loops_state_satisfies_p (LOOP_CLOSED_SSA)) + verify_loop_closed_ssa (true); + } +--- a/src/gcc/tree-ssa-pre.cc ++++ b/src/gcc/tree-ssa-pre.cc +@@ -4209,6 +4209,7 @@ compute_avail (function *fun) + else + { + ref->set = 0; ++ ref->base_set = 0; + if (ref1->opcode == MEM_REF) + ref1->op0 + = wide_int_to_tree (ptr_type_node, +--- a/src/gcc/tree-ssa-structalias.cc ++++ b/src/gcc/tree-ssa-structalias.cc +@@ -1581,64 +1581,6 @@ unify_nodes (constraint_graph_t graph, unsigned int to, unsigned int from, + bitmap_clear_bit (graph->succs[to], to); + } + +-/* Information needed to compute the topological ordering of a graph. */ +- +-struct topo_info +-{ +- /* sbitmap of visited nodes. */ +- sbitmap visited; +- /* Array that stores the topological order of the graph, *in +- reverse*. */ +- vec topo_order; +-}; +- +- +-/* Initialize and return a topological info structure. */ +- +-static struct topo_info * +-init_topo_info (void) +-{ +- size_t size = graph->size; +- struct topo_info *ti = XNEW (struct topo_info); +- ti->visited = sbitmap_alloc (size); +- bitmap_clear (ti->visited); +- ti->topo_order.create (1); +- return ti; +-} +- +- +-/* Free the topological sort info pointed to by TI. */ +- +-static void +-free_topo_info (struct topo_info *ti) +-{ +- sbitmap_free (ti->visited); +- ti->topo_order.release (); +- free (ti); +-} +- +-/* Visit the graph in topological order, and store the order in the +- topo_info structure. */ +- +-static void +-topo_visit (constraint_graph_t graph, struct topo_info *ti, +- unsigned int n) +-{ +- bitmap_iterator bi; +- unsigned int j; +- +- bitmap_set_bit (ti->visited, n); +- +- if (graph->succs[n]) +- EXECUTE_IF_SET_IN_BITMAP (graph->succs[n], 0, j, bi) +- { +- if (!bitmap_bit_p (ti->visited, j)) +- topo_visit (graph, ti, j); +- } +- +- ti->topo_order.safe_push (n); +-} +- + /* Process a constraint C that represents x = *(y + off), using DELTA as the + starting solution for y. */ + +@@ -1913,19 +1855,56 @@ find_indirect_cycles (constraint_graph_t graph) + scc_visit (graph, &si, i); + } + +-/* Compute a topological ordering for GRAPH, and store the result in the +- topo_info structure TI. */ ++/* Visit the graph in topological order starting at node N, and store the ++ order in TOPO_ORDER using VISITED to indicate visited nodes. */ + + static void +-compute_topo_order (constraint_graph_t graph, +- struct topo_info *ti) ++topo_visit (constraint_graph_t graph, vec &topo_order, ++ sbitmap visited, unsigned int n) ++{ ++ bitmap_iterator bi; ++ unsigned int j; ++ ++ bitmap_set_bit (visited, n); ++ ++ if (graph->succs[n]) ++ EXECUTE_IF_SET_IN_BITMAP (graph->succs[n], 0, j, bi) ++ { ++ unsigned k = find (j); ++ if (!bitmap_bit_p (visited, k)) ++ topo_visit (graph, topo_order, visited, k); ++ } ++ ++ topo_order.quick_push (n); ++} ++ ++/* Compute a topological ordering for GRAPH, and return the result. */ ++ ++static auto_vec ++compute_topo_order (constraint_graph_t graph) + { + unsigned int i; + unsigned int size = graph->size; + ++ auto_sbitmap visited (size); ++ bitmap_clear (visited); ++ ++ /* For the heuristic in add_graph_edge to work optimally make sure to ++ first visit the connected component of the graph containing ++ ESCAPED. Do this by extracting the connected component ++ with ESCAPED and append that to all other components as solve_graph ++ pops from the order. */ ++ auto_vec tail (size); ++ topo_visit (graph, tail, visited, find (escaped_id)); ++ ++ auto_vec topo_order (size); ++ + for (i = 0; i != size; ++i) +- if (!bitmap_bit_p (ti->visited, i) && find (i) == i) +- topo_visit (graph, ti, i); ++ if (!bitmap_bit_p (visited, i) && find (i) == i) ++ topo_visit (graph, topo_order, visited, i); ++ ++ topo_order.splice (tail); ++ return topo_order; + } + + /* Structure used to for hash value numbering of pointer equivalence +@@ -2753,17 +2732,14 @@ solve_graph (constraint_graph_t graph) + while (!bitmap_empty_p (changed)) + { + unsigned int i; +- struct topo_info *ti = init_topo_info (); + stats.iterations++; + + bitmap_obstack_initialize (&iteration_obstack); + +- compute_topo_order (graph, ti); +- +- while (ti->topo_order.length () != 0) ++ auto_vec topo_order = compute_topo_order (graph); ++ while (topo_order.length () != 0) + { +- +- i = ti->topo_order.pop (); ++ i = topo_order.pop (); + + /* If this variable is not a representative, skip it. */ + if (find (i) != i) +@@ -2895,7 +2871,6 @@ solve_graph (constraint_graph_t graph) + } + } + } +- free_topo_info (ti); + bitmap_obstack_release (&iteration_obstack); + } + +--- a/src/gcc/tree-ssa-tail-merge.cc ++++ b/src/gcc/tree-ssa-tail-merge.cc +@@ -1165,6 +1165,9 @@ gimple_equal_p (same_succ *same_succ, gimple *s1, gimple *s2) + return operand_equal_p (lhs1, lhs2, 0); + + case GIMPLE_ASSIGN: ++ if (gimple_assign_rhs_code (s1) != gimple_assign_rhs_code (s2)) ++ return false; ++ + lhs1 = gimple_get_lhs (s1); + lhs2 = gimple_get_lhs (s2); + if (TREE_CODE (lhs1) != SSA_NAME +@@ -1172,11 +1175,20 @@ gimple_equal_p (same_succ *same_succ, gimple *s1, gimple *s2) + return (operand_equal_p (lhs1, lhs2, 0) + && gimple_operand_equal_value_p (gimple_assign_rhs1 (s1), + gimple_assign_rhs1 (s2))); +- else if (TREE_CODE (lhs1) == SSA_NAME +- && TREE_CODE (lhs2) == SSA_NAME) +- return operand_equal_p (gimple_assign_rhs1 (s1), +- gimple_assign_rhs1 (s2), 0); +- return false; ++ ++ if (TREE_CODE (lhs1) != SSA_NAME ++ || TREE_CODE (lhs2) != SSA_NAME) ++ return false; ++ ++ gcc_checking_assert (gimple_num_args (s1) == gimple_num_args (s2)); ++ for (i = 0; i < gimple_num_args (s1); ++i) ++ { ++ t1 = gimple_arg (s1, i); ++ t2 = gimple_arg (s2, i); ++ if (!gimple_operand_equal_value_p (t1, t2)) ++ return false; ++ } ++ return true; + + case GIMPLE_COND: + t1 = gimple_cond_lhs (s1); --- a/src/gcc/tree-vect-loop.cc +++ b/src/gcc/tree-vect-loop.cc +@@ -3044,7 +3044,7 @@ vect_analyze_loop_1 (class loop *loop, vec_info_shared *shared, + res ? "succeeded" : " failed", + GET_MODE_NAME (loop_vinfo->vector_mode)); + +- if (!main_loop_vinfo && suggested_unroll_factor > 1) ++ if (res && !main_loop_vinfo && suggested_unroll_factor > 1) + { + if (dump_enabled_p ()) + dump_printf_loc (MSG_NOTE, vect_location, @@ -10114,9 +10114,10 @@ vectorizable_live_operation (vec_info *vinfo, use_stmt)) { @@ -237153,6 +323592,139 @@ if (dump_enabled_p ()) dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, "Using original scalar computation for " +--- a/src/gcc/tree-vect-patterns.cc ++++ b/src/gcc/tree-vect-patterns.cc +@@ -1885,7 +1885,7 @@ vect_recog_widen_sum_pattern (vec_info *vinfo, + Widening with mask first, shift later: + container = (type_out) container; + masked = container & (((1 << bitsize) - 1) << bitpos); +- result = patt2 >> masked; ++ result = masked >> bitpos; + + Widening with shift first, mask last: + container = (type_out) container; +@@ -1897,6 +1897,15 @@ vect_recog_widen_sum_pattern (vec_info *vinfo, + result = masked >> bitpos; + result = (type_out) result; + ++ If the bitfield is signed and it's wider than type_out, we need to ++ keep the result sign-extended: ++ container = (type) container; ++ masked = container << (prec - bitsize - bitpos); ++ result = (type_out) (masked >> (prec - bitsize)); ++ ++ Here type is the signed variant of the wider of type_out and the type ++ of container. ++ + The shifting is always optional depending on whether bitpos != 0. + + */ +@@ -1955,14 +1964,22 @@ vect_recog_bitfield_ref_pattern (vec_info *vinfo, stmt_vec_info stmt_info, + if (BYTES_BIG_ENDIAN) + shift_n = prec - shift_n - mask_width; + ++ bool ref_sext = (!TYPE_UNSIGNED (TREE_TYPE (bf_ref)) && ++ TYPE_PRECISION (ret_type) > mask_width); ++ bool load_widen = (TYPE_PRECISION (TREE_TYPE (container)) < ++ TYPE_PRECISION (ret_type)); ++ + /* We move the conversion earlier if the loaded type is smaller than the +- return type to enable the use of widening loads. */ +- if (TYPE_PRECISION (TREE_TYPE (container)) < TYPE_PRECISION (ret_type) +- && !useless_type_conversion_p (TREE_TYPE (container), ret_type)) ++ return type to enable the use of widening loads. And if we need a ++ sign extension, we need to convert the loaded value early to a signed ++ type as well. */ ++ if (ref_sext || load_widen) + { +- pattern_stmt +- = gimple_build_assign (vect_recog_temp_ssa_var (ret_type), +- NOP_EXPR, container); ++ tree type = load_widen ? ret_type : container_type; ++ if (ref_sext) ++ type = gimple_signed_type (type); ++ pattern_stmt = gimple_build_assign (vect_recog_temp_ssa_var (type), ++ NOP_EXPR, container); + container = gimple_get_lhs (pattern_stmt); + container_type = TREE_TYPE (container); + prec = tree_to_uhwi (TYPE_SIZE (container_type)); +@@ -1990,7 +2007,7 @@ vect_recog_bitfield_ref_pattern (vec_info *vinfo, stmt_vec_info stmt_info, + shift_first = true; + + tree result; +- if (shift_first) ++ if (shift_first && !ref_sext) + { + tree shifted = container; + if (shift_n) +@@ -2013,14 +2030,27 @@ vect_recog_bitfield_ref_pattern (vec_info *vinfo, stmt_vec_info stmt_info, + } + else + { +- tree mask = wide_int_to_tree (container_type, +- wi::shifted_mask (shift_n, mask_width, +- false, prec)); +- pattern_stmt +- = gimple_build_assign (vect_recog_temp_ssa_var (container_type), +- BIT_AND_EXPR, container, mask); +- tree masked = gimple_assign_lhs (pattern_stmt); ++ tree temp = vect_recog_temp_ssa_var (container_type); ++ if (!ref_sext) ++ { ++ tree mask = wide_int_to_tree (container_type, ++ wi::shifted_mask (shift_n, ++ mask_width, ++ false, prec)); ++ pattern_stmt = gimple_build_assign (temp, BIT_AND_EXPR, ++ container, mask); ++ } ++ else ++ { ++ HOST_WIDE_INT shl = prec - shift_n - mask_width; ++ shift_n += shl; ++ pattern_stmt = gimple_build_assign (temp, LSHIFT_EXPR, ++ container, ++ build_int_cst (sizetype, ++ shl)); ++ } + ++ tree masked = gimple_assign_lhs (pattern_stmt); + append_pattern_def_seq (vinfo, stmt_info, pattern_stmt, vectype); + pattern_stmt + = gimple_build_assign (vect_recog_temp_ssa_var (container_type), +--- a/src/gcc/tree-vect-slp.cc ++++ b/src/gcc/tree-vect-slp.cc +@@ -4670,14 +4670,28 @@ vect_optimize_slp_pass::start_choosing_layouts () + m_partition_layout_costs.safe_grow_cleared (m_partitions.length () + * m_perms.length ()); + +- /* We have to mark outgoing permutations facing non-reduction graph +- entries that are not represented as to be materialized. */ ++ /* We have to mark outgoing permutations facing non-associating-reduction ++ graph entries that are not represented as to be materialized. ++ slp_inst_kind_bb_reduc currently only covers associatable reductions. */ + for (slp_instance instance : m_vinfo->slp_instances) + if (SLP_INSTANCE_KIND (instance) == slp_inst_kind_ctor) + { + unsigned int node_i = SLP_INSTANCE_TREE (instance)->vertex; + m_partitions[m_vertices[node_i].partition].layout = 0; + } ++ else if (SLP_INSTANCE_KIND (instance) == slp_inst_kind_reduc_chain) ++ { ++ stmt_vec_info stmt_info ++ = SLP_TREE_REPRESENTATIVE (SLP_INSTANCE_TREE (instance)); ++ stmt_vec_info reduc_info = info_for_reduction (m_vinfo, stmt_info); ++ if (needs_fold_left_reduction_p (TREE_TYPE ++ (gimple_get_lhs (stmt_info->stmt)), ++ STMT_VINFO_REDUC_CODE (reduc_info))) ++ { ++ unsigned int node_i = SLP_INSTANCE_TREE (instance)->vertex; ++ m_partitions[m_vertices[node_i].partition].layout = 0; ++ } ++ } + + /* Check which layouts each node and partition can handle. Calculate the + weights associated with inserting layout changes on edges. */ --- a/src/gcc/wide-int.h +++ b/src/gcc/wide-int.h @@ -3185,9 +3185,11 @@ wi::lrotate (const T1 &x, const T2 &y, unsigned int width) @@ -237601,6 +324173,712 @@ else memcpy (next_arg.f128, arg.f128++, sizeof (float128)); if (++next_arg.f128 == gpr_end.f128) +--- a/src/libgcc/ChangeLog ++++ b/src/libgcc/ChangeLog +@@ -1,3 +1,42 @@ ++2023-06-03 Thomas Neumann ++ ++ PR libgcc/109670 ++ * unwind-dw2-fde.c: Fix radix sort buffer management. ++ ++2023-06-03 Thomas Neumann ++ ++ PR libgcc/109685 ++ * unwind-dw2-fde.c: Free sort array in atomic fast path. ++ ++2023-05-21 Iain Sandoe ++ ++ Backported from master: ++ 2023-05-19 Iain Sandoe ++ ++ * config.host: Arrange to set min Darwin OS versions from ++ the configured host version. ++ * config/darwin10-unwind-find-enc-func.c: Do not use current ++ headers, but declare the nexessary structures locally to the ++ versions in use for Mac OSX 10.6. ++ * config/t-darwin: Amend to handle configured min OS ++ versions. ++ * config/t-darwin-min-1: New. ++ * config/t-darwin-min-5: New. ++ * config/t-darwin-min-8: New. ++ ++2023-05-16 Patrick O'Neill ++ ++ PR target/104338 ++ * config/riscv/atomic.c: Add reference to duplicate logic. ++ ++2023-05-15 Thomas Neumann ++ ++ * unwind-dw2-fde.c: Fix assert in non-atomic path. ++ ++2023-05-15 Sören Tempel ++ ++ * unwind-dw2-fde.c: Accept empty ranges when deregistering frames. ++ + 2023-04-26 Release Manager + + * GCC 13.1.0 released. +--- a/src/libgcc/config.host ++++ b/src/libgcc/config.host +@@ -233,6 +233,24 @@ case ${host} in + ;; + esac + tmake_file="$tmake_file t-slibgcc-darwin" ++ # newer toolsets produce warnings when building for unsupported versions. ++ case ${host} in ++ *-*-darwin1[89]* | *-*-darwin2* ) ++ tmake_file="t-darwin-min-8 $tmake_file" ++ ;; ++ *-*-darwin9* | *-*-darwin1[0-7]*) ++ tmake_file="t-darwin-min-5 $tmake_file" ++ ;; ++ *-*-darwin[4-8]*) ++ tmake_file="t-darwin-min-1 $tmake_file" ++ ;; ++ *) ++ # Fall back to configuring for the oldest system known to work with ++ # all archs and the current sources. ++ tmake_file="t-darwin-min-5 $tmake_file" ++ echo "Warning: libgcc configured to support macOS 10.5" 1>&2 ++ ;; ++ esac + extra_parts="crt3.o libd10-uwfef.a crttms.o crttme.o libemutls_w.a" + ;; + *-*-dragonfly*) +--- a/src/libgcc/config/darwin10-unwind-find-enc-func.c ++++ b/src/libgcc/config/darwin10-unwind-find-enc-func.c +@@ -1,8 +1,34 @@ +-#include "tconfig.h" +-#include "tsystem.h" +-#include "unwind-dw2-fde.h" + #include "libgcc_tm.h" + ++/* This shim is special, it needs to be built for Mac OSX 10.6 ++ regardless of the current system version. ++ We must also build it to use the unwinder layout that was ++ present for 10.6 (and not update that). ++ So we copy the referenced structures from unwind-dw2-fde.h ++ to avoid pulling in newer system headers and/or changed ++ layouts. */ ++struct dwarf_eh_bases ++{ ++ void *tbase; ++ void *dbase; ++ void *func; ++}; ++ ++typedef int sword __attribute__ ((mode (SI))); ++typedef unsigned int uword __attribute__ ((mode (SI))); ++ ++/* The first few fields of an FDE. */ ++struct dwarf_fde ++{ ++ uword length; ++ sword CIE_delta; ++ unsigned char pc_begin[]; ++} __attribute__ ((packed, aligned (__alignof__ (void *)))); ++ ++typedef struct dwarf_fde fde; ++ ++extern const fde * _Unwind_Find_FDE (void *, struct dwarf_eh_bases *); ++ + void * + _darwin10_Unwind_FindEnclosingFunction (void *pc) + { +@@ -10,5 +36,5 @@ _darwin10_Unwind_FindEnclosingFunction (void *pc) + const struct dwarf_fde *fde = _Unwind_Find_FDE (pc-1, &bases); + if (fde) + return bases.func; +- return NULL; ++ return (void *) 0; + } +--- a/src/libgcc/config/riscv/atomic.c ++++ b/src/libgcc/config/riscv/atomic.c +@@ -30,6 +30,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + #define INVERT "not %[tmp1], %[tmp1]\n\t" + #define DONT_INVERT "" + ++/* Logic duplicated in gcc/gcc/config/riscv/sync.md for use when inlining is enabled */ ++ + #define GENERATE_FETCH_AND_OP(type, size, opname, insn, invert, cop) \ + type __sync_fetch_and_ ## opname ## _ ## size (type *p, type v) \ + { \ +--- a/src/libgcc/config/t-darwin ++++ b/src/libgcc/config/t-darwin +@@ -1,15 +1,15 @@ + # Set this as a minimum (unless overriden by arch t-files) since it's a + # reasonable lowest common denominator that works for all our archs. +-HOST_LIBGCC2_CFLAGS += -mmacosx-version-min=10.4 ++HOST_LIBGCC2_CFLAGS += $(DARWIN_MIN_LIB_VERSION) + + crt3.o: $(srcdir)/config/darwin-crt3.c +- $(crt_compile) -mmacosx-version-min=10.4 -c $< ++ $(crt_compile) $(DARWIN_MIN_CRT_VERSION) -c $< + + crttms.o: $(srcdir)/config/darwin-crt-tm.c +- $(crt_compile) -mmacosx-version-min=10.4 -DSTART -c $< ++ $(crt_compile) $(DARWIN_MIN_CRT_VERSION) -DSTART -c $< + + crttme.o: $(srcdir)/config/darwin-crt-tm.c +- $(crt_compile) -mmacosx-version-min=10.4 -DEND -c $< ++ $(crt_compile) $(DARWIN_MIN_CRT_VERSION) -DEND -c $< + + # Make emutls weak so that we can deal with -static-libgcc, override the + # hidden visibility when this is present in libgcc_eh. +@@ -25,6 +25,8 @@ libemutls_w.a: emutls_s.o + $(RANLIB_FOR_TARGET) $@ + + # Patch to __Unwind_Find_Enclosing_Function for Darwin10. ++# This needs to be built for darwin10, regardless of the current platform ++# version. + d10-uwfef.o: $(srcdir)/config/darwin10-unwind-find-enc-func.c libgcc_tm.h + $(crt_compile) -mmacosx-version-min=10.6 -c $< + +new file mode 100644 +--- /dev/null ++++ b/src/libgcc/config/t-darwin-min-1 +@@ -0,0 +1,3 @@ ++# Support building with -mmacosx-version-min back to 10.1. ++DARWIN_MIN_LIB_VERSION = -mmacosx-version-min=10.4 ++DARWIN_MIN_CRT_VERSION = -mmacosx-version-min=10.1 +new file mode 100644 +--- /dev/null ++++ b/src/libgcc/config/t-darwin-min-5 +@@ -0,0 +1,3 @@ ++# Support building with -mmacosx-version-min back to 10.5. ++DARWIN_MIN_LIB_VERSION = -mmacosx-version-min=10.5 ++DARWIN_MIN_CRT_VERSION = -mmacosx-version-min=10.5 +new file mode 100644 +--- /dev/null ++++ b/src/libgcc/config/t-darwin-min-8 +@@ -0,0 +1,3 @@ ++# Support building with -mmacosx-version-min back to 10.8. ++DARWIN_MIN_LIB_VERSION = -mmacosx-version-min=10.8 ++DARWIN_MIN_CRT_VERSION = -mmacosx-version-min=10.8 +--- a/src/libgcc/unwind-dw2-fde.c ++++ b/src/libgcc/unwind-dw2-fde.c +@@ -240,6 +240,13 @@ __deregister_frame_info_bases (const void *begin) + + // And remove + ob = btree_remove (®istered_frames, range[0]); ++ bool empty_table = (range[1] - range[0]) == 0; ++ ++ // Deallocate the sort array if any. ++ if (ob && ob->s.b.sorted) ++ { ++ free (ob->u.sort); ++ } + #else + init_object_mutex_once (); + __gthread_mutex_lock (&object_mutex); +@@ -276,9 +283,12 @@ __deregister_frame_info_bases (const void *begin) + + out: + __gthread_mutex_unlock (&object_mutex); ++ const int empty_table = 0; // The non-atomic path stores all tables. + #endif + +- gcc_assert (in_shutdown || ob); ++ // If we didn't find anything in the lookup data structures then they ++ // were either already destroyed or we tried to remove an empty range. ++ gcc_assert (in_shutdown || (empty_table || ob)); + return (void *) ob; + } + +@@ -624,8 +634,6 @@ fde_radixsort (struct object *ob, fde_extractor_t fde_extractor, + // Stop if we are already sorted. + if (!violations) + { +- // The sorted data is in a1 now. +- a2 = a1; + break; + } + +@@ -660,9 +668,9 @@ fde_radixsort (struct object *ob, fde_extractor_t fde_extractor, + #undef FANOUT + #undef FANOUTBITS + +- // The data is in a2 now, move in place if needed. +- if (a2 != v1->array) +- memcpy (v1->array, a2, sizeof (const fde *) * n); ++ // The data is in a1 now, move in place if needed. ++ if (a1 != v1->array) ++ memcpy (v1->array, a1, sizeof (const fde *) * n); + } + + static inline void +--- a/src/libgm2/ChangeLog ++++ b/src/libgm2/ChangeLog +@@ -1,3 +1,31 @@ ++2023-06-28 Thomas Schwinge ++ ++ Backported from master: ++ 2023-05-08 Thomas Schwinge ++ ++ * autogen.sh: Remove. ++ ++2023-06-28 Thomas Schwinge ++ ++ Backported from master: ++ 2023-05-08 Thomas Schwinge ++ ++ * autogen.sh: For 'aclocal', 'autoreconf', remove '-I .', ++ add '-I ..'. ++ * Makefile.am (ACLOCAL_AMFLAGS): Remove '-I .'. ++ * libm2cor/Makefile.am (ACLOCAL_AMFLAGS): Likewise. ++ * libm2iso/Makefile.am (ACLOCAL_AMFLAGS): Likewise. ++ * libm2log/Makefile.am (ACLOCAL_AMFLAGS): Likewise. ++ * libm2min/Makefile.am (ACLOCAL_AMFLAGS): Likewise. ++ * libm2pim/Makefile.am (ACLOCAL_AMFLAGS): Likewise. ++ * aclocal.m4: Regenerate. ++ * Makefile.in: Likewise. ++ * libm2cor/Makefile.in: Likewise. ++ * libm2iso/Makefile.in: Likewise. ++ * libm2log/Makefile.in: Likewise. ++ * libm2min/Makefile.in: Likewise. ++ * libm2pim/Makefile.in: Likewise. ++ + 2023-04-26 Release Manager + + * GCC 13.1.0 released. +--- a/src/libgm2/Makefile.am ++++ b/src/libgm2/Makefile.am +@@ -25,7 +25,7 @@ AUTOMAKE_OPTIONS = 1.8 foreign + + SUFFIXES = .c .mod .def .o .obj .lo .a + +-ACLOCAL_AMFLAGS = -I . -I .. -I ../config ++ACLOCAL_AMFLAGS = -I .. -I ../config + + # Multilib support. + MAKEOVERRIDES= +--- a/src/libgm2/Makefile.in ++++ b/src/libgm2/Makefile.in +@@ -90,15 +90,15 @@ host_triplet = @host@ + target_triplet = @target@ + subdir = . + ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 +-am__aclocal_m4_deps = $(top_srcdir)/../libtool.m4 \ +- $(top_srcdir)/../ltoptions.m4 $(top_srcdir)/../ltsugar.m4 \ +- $(top_srcdir)/../ltversion.m4 $(top_srcdir)/../lt~obsolete.m4 \ +- $(top_srcdir)/../config/acx.m4 \ ++am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \ + $(top_srcdir)/../config/depstand.m4 \ + $(top_srcdir)/../config/lead-dot.m4 \ + $(top_srcdir)/../config/multi.m4 \ + $(top_srcdir)/../config/no-executables.m4 \ +- $(top_srcdir)/../config/override.m4 $(top_srcdir)/configure.ac ++ $(top_srcdir)/../config/override.m4 \ ++ $(top_srcdir)/../libtool.m4 $(top_srcdir)/../ltoptions.m4 \ ++ $(top_srcdir)/../ltsugar.m4 $(top_srcdir)/../ltversion.m4 \ ++ $(top_srcdir)/../lt~obsolete.m4 $(top_srcdir)/configure.ac + am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ + $(ACLOCAL_M4) + DIST_COMMON = $(srcdir)/Makefile.am $(top_srcdir)/configure \ +@@ -332,7 +332,7 @@ top_srcdir = @top_srcdir@ + # Modula-2 support. + AUTOMAKE_OPTIONS = 1.8 foreign + SUFFIXES = .c .mod .def .o .obj .lo .a +-ACLOCAL_AMFLAGS = -I . -I .. -I ../config ++ACLOCAL_AMFLAGS = -I .. -I ../config + + # Multilib support. + MAKEOVERRIDES = +--- a/src/libgm2/aclocal.m4 ++++ b/src/libgm2/aclocal.m4 +@@ -1187,14 +1187,14 @@ AC_SUBST([am__tar]) + AC_SUBST([am__untar]) + ]) # _AM_PROG_TAR + +-m4_include([../libtool.m4]) +-m4_include([../ltoptions.m4]) +-m4_include([../ltsugar.m4]) +-m4_include([../ltversion.m4]) +-m4_include([../lt~obsolete.m4]) + m4_include([../config/acx.m4]) + m4_include([../config/depstand.m4]) + m4_include([../config/lead-dot.m4]) + m4_include([../config/multi.m4]) + m4_include([../config/no-executables.m4]) + m4_include([../config/override.m4]) ++m4_include([../libtool.m4]) ++m4_include([../ltoptions.m4]) ++m4_include([../ltsugar.m4]) ++m4_include([../ltversion.m4]) ++m4_include([../lt~obsolete.m4]) +deleted file mode 100755 +--- a/src/libgm2/autogen.sh ++++ /dev/null +@@ -1,31 +0,0 @@ +-#!/bin/sh +- +-# autogen.sh regenerate the autoconf files. +-# Copyright 2013-2022 Free Software Foundation, Inc. +-# +-# This file is free software; you can redistribute it and/or modify +-# it under the terms of the GNU General Public License as published by +-# the Free Software Foundation; either version 3 of the License, or +-# (at your option) any later version. +-# +-# This program is distributed in the hope that it will be useful, +-# but WITHOUT ANY WARRANTY; without even the implied warranty of +-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-# GNU General Public License for more details. +-# +-# You should have received a copy of the GNU General Public License +-# along with this program; see the file COPYING3. If not see +-# . +- +-rm -rf autom4te.cache +- +-# libtoolize +-rm -f aclocal.m4 +-# aclocal -I . -I config -I ../config +-aclocal -I . -I ../config +-autoreconf -I . -I ../config +-automake --include-deps +- +-rm -rf autom4te.cache +- +-exit 0 +--- a/src/libgm2/libm2cor/Makefile.am ++++ b/src/libgm2/libm2cor/Makefile.am +@@ -17,7 +17,7 @@ + + SUFFIXES = .c .cc .mod .def .o .obj .lo .a .la + +-ACLOCAL_AMFLAGS = -I . -I .. -I ../config ++ACLOCAL_AMFLAGS = -I .. -I ../config + + VPATH = . @srcdir@ @srcdir@/../../gcc/m2/gm2-libs-coroutines + +--- a/src/libgm2/libm2cor/Makefile.in ++++ b/src/libgm2/libm2cor/Makefile.in +@@ -107,15 +107,15 @@ host_triplet = @host@ + target_triplet = @target@ + subdir = libm2cor + ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 +-am__aclocal_m4_deps = $(top_srcdir)/../libtool.m4 \ +- $(top_srcdir)/../ltoptions.m4 $(top_srcdir)/../ltsugar.m4 \ +- $(top_srcdir)/../ltversion.m4 $(top_srcdir)/../lt~obsolete.m4 \ +- $(top_srcdir)/../config/acx.m4 \ ++am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \ + $(top_srcdir)/../config/depstand.m4 \ + $(top_srcdir)/../config/lead-dot.m4 \ + $(top_srcdir)/../config/multi.m4 \ + $(top_srcdir)/../config/no-executables.m4 \ +- $(top_srcdir)/../config/override.m4 $(top_srcdir)/configure.ac ++ $(top_srcdir)/../config/override.m4 \ ++ $(top_srcdir)/../libtool.m4 $(top_srcdir)/../ltoptions.m4 \ ++ $(top_srcdir)/../ltsugar.m4 $(top_srcdir)/../ltversion.m4 \ ++ $(top_srcdir)/../lt~obsolete.m4 $(top_srcdir)/configure.ac + am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ + $(ACLOCAL_M4) + DIST_COMMON = $(srcdir)/Makefile.am +@@ -384,7 +384,7 @@ top_build_prefix = @top_build_prefix@ + top_builddir = @top_builddir@ + top_srcdir = @top_srcdir@ + SUFFIXES = .c .cc .mod .def .o .obj .lo .a .la +-ACLOCAL_AMFLAGS = -I . -I .. -I ../config ++ACLOCAL_AMFLAGS = -I .. -I ../config + + # Multilib support. + MAKEOVERRIDES = +--- a/src/libgm2/libm2iso/Makefile.am ++++ b/src/libgm2/libm2iso/Makefile.am +@@ -17,7 +17,7 @@ + + SUFFIXES = .c .cc .mod .def .o .obj .lo .a .la + +-ACLOCAL_AMFLAGS = -I . -I .. -I ../config ++ACLOCAL_AMFLAGS = -I .. -I ../config + + VPATH = . @srcdir@ @srcdir@/../../gcc/m2/gm2-libs-iso + +--- a/src/libgm2/libm2iso/Makefile.in ++++ b/src/libgm2/libm2iso/Makefile.in +@@ -107,15 +107,15 @@ host_triplet = @host@ + target_triplet = @target@ + subdir = libm2iso + ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 +-am__aclocal_m4_deps = $(top_srcdir)/../libtool.m4 \ +- $(top_srcdir)/../ltoptions.m4 $(top_srcdir)/../ltsugar.m4 \ +- $(top_srcdir)/../ltversion.m4 $(top_srcdir)/../lt~obsolete.m4 \ +- $(top_srcdir)/../config/acx.m4 \ ++am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \ + $(top_srcdir)/../config/depstand.m4 \ + $(top_srcdir)/../config/lead-dot.m4 \ + $(top_srcdir)/../config/multi.m4 \ + $(top_srcdir)/../config/no-executables.m4 \ +- $(top_srcdir)/../config/override.m4 $(top_srcdir)/configure.ac ++ $(top_srcdir)/../config/override.m4 \ ++ $(top_srcdir)/../libtool.m4 $(top_srcdir)/../ltoptions.m4 \ ++ $(top_srcdir)/../ltsugar.m4 $(top_srcdir)/../ltversion.m4 \ ++ $(top_srcdir)/../lt~obsolete.m4 $(top_srcdir)/configure.ac + am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ + $(ACLOCAL_M4) + DIST_COMMON = $(srcdir)/Makefile.am +@@ -409,7 +409,7 @@ top_build_prefix = @top_build_prefix@ + top_builddir = @top_builddir@ + top_srcdir = @top_srcdir@ + SUFFIXES = .c .cc .mod .def .o .obj .lo .a .la +-ACLOCAL_AMFLAGS = -I . -I .. -I ../config ++ACLOCAL_AMFLAGS = -I .. -I ../config + + # Multilib support. + MAKEOVERRIDES = +--- a/src/libgm2/libm2log/Makefile.am ++++ b/src/libgm2/libm2log/Makefile.am +@@ -17,7 +17,7 @@ + + SUFFIXES = .c .mod .def .o .obj .lo .a .la + +-ACLOCAL_AMFLAGS = -I . -I .. -I ../config ++ACLOCAL_AMFLAGS = -I .. -I ../config + + VPATH = . @srcdir@ @srcdir@/../../gcc/m2/gm2-libs-log + +--- a/src/libgm2/libm2log/Makefile.in ++++ b/src/libgm2/libm2log/Makefile.in +@@ -107,15 +107,15 @@ host_triplet = @host@ + target_triplet = @target@ + subdir = libm2log + ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 +-am__aclocal_m4_deps = $(top_srcdir)/../libtool.m4 \ +- $(top_srcdir)/../ltoptions.m4 $(top_srcdir)/../ltsugar.m4 \ +- $(top_srcdir)/../ltversion.m4 $(top_srcdir)/../lt~obsolete.m4 \ +- $(top_srcdir)/../config/acx.m4 \ ++am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \ + $(top_srcdir)/../config/depstand.m4 \ + $(top_srcdir)/../config/lead-dot.m4 \ + $(top_srcdir)/../config/multi.m4 \ + $(top_srcdir)/../config/no-executables.m4 \ +- $(top_srcdir)/../config/override.m4 $(top_srcdir)/configure.ac ++ $(top_srcdir)/../config/override.m4 \ ++ $(top_srcdir)/../libtool.m4 $(top_srcdir)/../ltoptions.m4 \ ++ $(top_srcdir)/../ltsugar.m4 $(top_srcdir)/../ltversion.m4 \ ++ $(top_srcdir)/../lt~obsolete.m4 $(top_srcdir)/configure.ac + am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ + $(ACLOCAL_M4) + DIST_COMMON = $(srcdir)/Makefile.am +@@ -373,7 +373,7 @@ top_build_prefix = @top_build_prefix@ + top_builddir = @top_builddir@ + top_srcdir = @top_srcdir@ + SUFFIXES = .c .mod .def .o .obj .lo .a .la +-ACLOCAL_AMFLAGS = -I . -I .. -I ../config ++ACLOCAL_AMFLAGS = -I .. -I ../config + + # Multilib support. + MAKEOVERRIDES = +--- a/src/libgm2/libm2min/Makefile.am ++++ b/src/libgm2/libm2min/Makefile.am +@@ -17,7 +17,7 @@ + + SUFFIXES = .c .mod .def .o .obj .lo .a .la + +-ACLOCAL_AMFLAGS = -I . -I .. -I ../config ++ACLOCAL_AMFLAGS = -I .. -I ../config + + VPATH = . @srcdir@/../../gcc/m2/gm2-libs-min + +--- a/src/libgm2/libm2min/Makefile.in ++++ b/src/libgm2/libm2min/Makefile.in +@@ -107,15 +107,15 @@ host_triplet = @host@ + target_triplet = @target@ + subdir = libm2min + ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 +-am__aclocal_m4_deps = $(top_srcdir)/../libtool.m4 \ +- $(top_srcdir)/../ltoptions.m4 $(top_srcdir)/../ltsugar.m4 \ +- $(top_srcdir)/../ltversion.m4 $(top_srcdir)/../lt~obsolete.m4 \ +- $(top_srcdir)/../config/acx.m4 \ ++am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \ + $(top_srcdir)/../config/depstand.m4 \ + $(top_srcdir)/../config/lead-dot.m4 \ + $(top_srcdir)/../config/multi.m4 \ + $(top_srcdir)/../config/no-executables.m4 \ +- $(top_srcdir)/../config/override.m4 $(top_srcdir)/configure.ac ++ $(top_srcdir)/../config/override.m4 \ ++ $(top_srcdir)/../libtool.m4 $(top_srcdir)/../ltoptions.m4 \ ++ $(top_srcdir)/../ltsugar.m4 $(top_srcdir)/../ltversion.m4 \ ++ $(top_srcdir)/../lt~obsolete.m4 $(top_srcdir)/configure.ac + am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ + $(ACLOCAL_M4) + DIST_COMMON = $(srcdir)/Makefile.am +@@ -363,7 +363,7 @@ top_build_prefix = @top_build_prefix@ + top_builddir = @top_builddir@ + top_srcdir = @top_srcdir@ + SUFFIXES = .c .mod .def .o .obj .lo .a .la +-ACLOCAL_AMFLAGS = -I . -I .. -I ../config ++ACLOCAL_AMFLAGS = -I .. -I ../config + + # Multilib support. + MAKEOVERRIDES = +--- a/src/libgm2/libm2pim/Makefile.am ++++ b/src/libgm2/libm2pim/Makefile.am +@@ -17,7 +17,7 @@ + + SUFFIXES = .c .mod .def .o .obj .lo .a .la + +-ACLOCAL_AMFLAGS = -I . -I .. -I ../config ++ACLOCAL_AMFLAGS = -I .. -I ../config + + VPATH = . @srcdir@ @srcdir@/../../gcc/m2/gm2-libs + +--- a/src/libgm2/libm2pim/Makefile.in ++++ b/src/libgm2/libm2pim/Makefile.in +@@ -107,15 +107,15 @@ host_triplet = @host@ + target_triplet = @target@ + subdir = libm2pim + ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 +-am__aclocal_m4_deps = $(top_srcdir)/../libtool.m4 \ +- $(top_srcdir)/../ltoptions.m4 $(top_srcdir)/../ltsugar.m4 \ +- $(top_srcdir)/../ltversion.m4 $(top_srcdir)/../lt~obsolete.m4 \ +- $(top_srcdir)/../config/acx.m4 \ ++am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \ + $(top_srcdir)/../config/depstand.m4 \ + $(top_srcdir)/../config/lead-dot.m4 \ + $(top_srcdir)/../config/multi.m4 \ + $(top_srcdir)/../config/no-executables.m4 \ +- $(top_srcdir)/../config/override.m4 $(top_srcdir)/configure.ac ++ $(top_srcdir)/../config/override.m4 \ ++ $(top_srcdir)/../libtool.m4 $(top_srcdir)/../ltoptions.m4 \ ++ $(top_srcdir)/../ltsugar.m4 $(top_srcdir)/../ltversion.m4 \ ++ $(top_srcdir)/../lt~obsolete.m4 $(top_srcdir)/configure.ac + am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ + $(ACLOCAL_M4) + DIST_COMMON = $(srcdir)/Makefile.am +@@ -398,7 +398,7 @@ top_build_prefix = @top_build_prefix@ + top_builddir = @top_builddir@ + top_srcdir = @top_srcdir@ + SUFFIXES = .c .mod .def .o .obj .lo .a .la +-ACLOCAL_AMFLAGS = -I . -I .. -I ../config ++ACLOCAL_AMFLAGS = -I .. -I ../config + + # Multilib support. + MAKEOVERRIDES = +--- a/src/libgo/Makefile.am ++++ b/src/libgo/Makefile.am +@@ -417,6 +417,7 @@ toolexeclibgounicode_DATA = \ + # Some internal packages are needed to bootstrap the gc toolchain. + toolexeclibgointernaldir = $(toolexeclibgodir)/internal + toolexeclibgointernal_DATA = \ ++ internal/lazyregexp.gox \ + internal/reflectlite.gox \ + internal/unsafeheader.gox + +@@ -462,6 +463,7 @@ runtime_files = \ + runtime/go-memclr.c \ + runtime/go-memmove.c \ + runtime/go-memequal.c \ ++ runtime/go-mmap.c \ + runtime/go-nanotime.c \ + runtime/go-now.c \ + runtime/go-nosys.c \ +--- a/src/libgo/Makefile.in ++++ b/src/libgo/Makefile.in +@@ -246,15 +246,15 @@ am__objects_4 = runtime/aeshash.lo runtime/go-assert.lo \ + runtime/go-construct-map.lo runtime/go-ffi.lo \ + runtime/go-fieldtrack.lo runtime/go-matherr.lo \ + runtime/go-memclr.lo runtime/go-memmove.lo \ +- runtime/go-memequal.lo runtime/go-nanotime.lo \ +- runtime/go-now.lo runtime/go-nosys.lo runtime/go-strerror.lo \ +- runtime/go-reflect-call.lo runtime/go-setenv.lo \ +- runtime/go-signal.lo runtime/go-unsafe-pointer.lo \ +- runtime/go-unsetenv.lo runtime/go-unwind.lo \ +- runtime/go-varargs.lo runtime/env_posix.lo runtime/panic.lo \ +- runtime/print.lo runtime/proc.lo runtime/runtime_c.lo \ +- runtime/stack.lo runtime/yield.lo $(am__objects_2) \ +- $(am__objects_3) ++ runtime/go-memequal.lo runtime/go-mmap.lo \ ++ runtime/go-nanotime.lo runtime/go-now.lo runtime/go-nosys.lo \ ++ runtime/go-strerror.lo runtime/go-reflect-call.lo \ ++ runtime/go-setenv.lo runtime/go-signal.lo \ ++ runtime/go-unsafe-pointer.lo runtime/go-unsetenv.lo \ ++ runtime/go-unwind.lo runtime/go-varargs.lo \ ++ runtime/env_posix.lo runtime/panic.lo runtime/print.lo \ ++ runtime/proc.lo runtime/runtime_c.lo runtime/stack.lo \ ++ runtime/yield.lo $(am__objects_2) $(am__objects_3) + am_libgo_llgo_la_OBJECTS = $(am__objects_4) + libgo_llgo_la_OBJECTS = $(am_libgo_llgo_la_OBJECTS) + AM_V_lt = $(am__v_lt_@AM_V@) +@@ -885,6 +885,7 @@ toolexeclibgounicode_DATA = \ + # Some internal packages are needed to bootstrap the gc toolchain. + toolexeclibgointernaldir = $(toolexeclibgodir)/internal + toolexeclibgointernal_DATA = \ ++ internal/lazyregexp.gox \ + internal/reflectlite.gox \ + internal/unsafeheader.gox + +@@ -914,6 +915,7 @@ runtime_files = \ + runtime/go-memclr.c \ + runtime/go-memmove.c \ + runtime/go-memequal.c \ ++ runtime/go-mmap.c \ + runtime/go-nanotime.c \ + runtime/go-now.c \ + runtime/go-nosys.c \ +@@ -1385,6 +1387,8 @@ runtime/go-memmove.lo: runtime/$(am__dirstamp) \ + runtime/$(DEPDIR)/$(am__dirstamp) + runtime/go-memequal.lo: runtime/$(am__dirstamp) \ + runtime/$(DEPDIR)/$(am__dirstamp) ++runtime/go-mmap.lo: runtime/$(am__dirstamp) \ ++ runtime/$(DEPDIR)/$(am__dirstamp) + runtime/go-nanotime.lo: runtime/$(am__dirstamp) \ + runtime/$(DEPDIR)/$(am__dirstamp) + runtime/go-now.lo: runtime/$(am__dirstamp) \ +@@ -1454,6 +1458,7 @@ distclean-compile: + @AMDEP_TRUE@@am__include@ @am__quote@runtime/$(DEPDIR)/go-memclr.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@runtime/$(DEPDIR)/go-memequal.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@runtime/$(DEPDIR)/go-memmove.Plo@am__quote@ ++@AMDEP_TRUE@@am__include@ @am__quote@runtime/$(DEPDIR)/go-mmap.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@runtime/$(DEPDIR)/go-nanotime.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@runtime/$(DEPDIR)/go-nosys.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@runtime/$(DEPDIR)/go-now.Plo@am__quote@ +--- a/src/libgo/go/internal/abi/abi.go ++++ b/src/libgo/go/internal/abi/abi.go +@@ -17,10 +17,7 @@ package abi + // compile-time error. + // + // Implemented as a compile intrinsic. +-func FuncPCABI0(f any) uintptr { +- // The compiler should remove all calls. +- panic("FuncPCABI0") +-} ++func FuncPCABI0(f any) uintptr + + // FuncPCABIInternal returns the entry PC of the function f. If f is a + // direct reference of a function, it must be defined as ABIInternal. +@@ -29,7 +26,4 @@ func FuncPCABI0(f any) uintptr { + // the behavior is undefined. + // + // Implemented as a compile intrinsic. +-func FuncPCABIInternal(f any) uintptr { +- // The compiler should remove all calls. +- panic("FuncPCABIInternal") +-} ++func FuncPCABIInternal(f any) uintptr +--- a/src/libgo/go/runtime/mem_gccgo.go ++++ b/src/libgo/go/runtime/mem_gccgo.go +@@ -14,8 +14,8 @@ import ( + //go:linkname sysAlloc + //go:linkname sysFree + +-//extern mmap +-func sysMmap(addr unsafe.Pointer, n uintptr, prot, flags, fd int32, off _libgo_off_t_type) unsafe.Pointer ++//extern __go_mmap ++func sysMmap(addr unsafe.Pointer, n uintptr, prot, flags, fd int32, off uintptr) unsafe.Pointer + + //extern munmap + func munmap(addr unsafe.Pointer, length uintptr) int32 +@@ -38,7 +38,7 @@ func init() { + } + + func mmap(addr unsafe.Pointer, n uintptr, prot, flags, fd int32, off uintptr) (unsafe.Pointer, int) { +- p := sysMmap(addr, n, prot, flags, fd, _libgo_off_t_type(off)) ++ p := sysMmap(addr, n, prot, flags, fd, off) + if uintptr(p) == _MAP_FAILED { + return nil, errno() + } --- a/src/libgo/go/syscall/libcall_linux.go +++ b/src/libgo/go/syscall/libcall_linux.go @@ -189,6 +189,14 @@ func Gettid() (tid int) { @@ -237618,9 +324896,113 @@ //sys Removexattr(path string, attr string) (err error) //removexattr(path *byte, name *byte) _C_int +new file mode 100644 +--- /dev/null ++++ b/src/libgo/runtime/go-mmap.c +@@ -0,0 +1,21 @@ ++/* go-mmap.c -- functions for calling C mmap functions. ++ ++ Copyright 2023 The Go Authors. All rights reserved. ++ Use of this source code is governed by a BSD-style ++ license that can be found in the LICENSE file. */ ++ ++#include "config.h" ++ ++#include ++#include ++ ++/* The exact C function to call varies between mmap and mmap64, and ++ the size of the off_t argument also varies. Here we provide a ++ function that Go code can call with consistent types. */ ++ ++void * ++__go_mmap(void *addr, uintptr_t length, int32_t prot, int32_t flags, ++ int32_t fd, uintptr_t offset) ++{ ++ return mmap(addr, length, prot, flags, fd, offset); ++} +--- a/src/libgo/runtime/runtime.h ++++ b/src/libgo/runtime/runtime.h +@@ -355,9 +355,6 @@ bool runtime_notetsleepg(Note*, int64) // false - timeout + /* + * low level C-called + */ +-#define runtime_mmap mmap +-#define runtime_munmap munmap +-#define runtime_madvise madvise + #define runtime_memclr(buf, size) __builtin_memset((buf), 0, (size)) + #define runtime_getcallerpc() __builtin_return_address(0) + --- a/src/libgomp/ChangeLog +++ b/src/libgomp/ChangeLog -@@ -1,3 +1,30 @@ +@@ -1,3 +1,97 @@ ++2023-06-28 Thomas Schwinge ++ ++ Backported from master: ++ 2023-06-02 Thomas Schwinge ++ ++ PR testsuite/66005 ++ * testsuite/lib/libgomp.exp: 'flock' through stdout. ++ * testsuite/flock: New. ++ * configure.ac (FLOCK): Point to that if no 'flock' available, but ++ 'perl' is. ++ * configure: Regenerate. ++ ++2023-06-28 Thomas Schwinge ++ ++ Backported from master: ++ 2023-05-15 Thomas Schwinge ++ ++ PR testsuite/66005 ++ * configure.ac: Look for 'flock'. ++ * testsuite/Makefile.am (gcc_test_parallel_slots): Enable parallel testing. ++ * testsuite/config/default.exp: Don't 'load_lib "standard.exp"' here... ++ * testsuite/lib/libgomp.exp: ... but here, instead. ++ (libgomp_load): Override for parallel testing. ++ * testsuite/libgomp-site-extra.exp.in (FLOCK): Set. ++ * configure: Regenerate. ++ * Makefile.in: Regenerate. ++ * testsuite/Makefile.in: Regenerate. ++ ++2023-06-28 Rainer Orth ++ ++ Backported from master: ++ 2023-05-15 Rainer Orth ++ Thomas Schwinge ++ ++ PR testsuite/66005 ++ * testsuite/Makefile.am (PWD_COMMAND): New variable. ++ (%/site.exp): New target. ++ (check_p_numbers0, check_p_numbers1, check_p_numbers2) ++ (check_p_numbers3, check_p_numbers4, check_p_numbers5) ++ (check_p_numbers6, check_p_numbers, gcc_test_parallel_slots) ++ (check_p_subdirs) ++ (check_DEJAGNU_libgomp_targets): New variables. ++ ($(check_DEJAGNU_libgomp_targets)): New target. ++ ($(check_DEJAGNU_libgomp_targets)): New dependency. ++ (check-DEJAGNU $(check_DEJAGNU_libgomp_targets)): New targets. ++ * testsuite/Makefile.in: Regenerate. ++ * testsuite/lib/libgomp.exp: For parallel testing, ++ 'load_file ../libgomp-test-support.exp'. ++ ++2023-06-28 Thomas Schwinge ++ ++ Backported from master: ++ 2023-05-08 Thomas Schwinge ++ ++ * testsuite/libgomp.c++/c++.exp: Use 'lang_include_flags' instead ++ of 'libstdcxx_includes'. ++ * testsuite/libgomp.oacc-c++/c++.exp: Likewise. ++ ++2023-05-16 Tobias Burnus ++ ++ Backported from master: ++ 2023-05-12 Tobias Burnus ++ ++ PR libstdc++/109816 ++ * testsuite/libgomp.c++/target-map-class-1.C: New test. ++ * testsuite/libgomp.c++/target-map-class-2.C: New test. ++ +2023-05-05 Julian Brown + + Backported from master: @@ -237651,6 +325033,612 @@ 2023-04-26 Release Manager * GCC 13.1.0 released. +--- a/src/libgomp/Makefile.in ++++ b/src/libgomp/Makefile.in +@@ -382,6 +382,7 @@ EXEEXT = @EXEEXT@ + FC = @FC@ + FCFLAGS = @FCFLAGS@ + FGREP = @FGREP@ ++FLOCK = @FLOCK@ + GREP = @GREP@ + INSTALL = @INSTALL@ + INSTALL_DATA = @INSTALL_DATA@ +--- a/src/libgomp/configure ++++ b/src/libgomp/configure +@@ -656,6 +656,7 @@ tmake_file + XLDFLAGS + XCFLAGS + config_path ++FLOCK + CPU_COUNT + LIBGOMP_BUILD_VERSIONED_SHLIB_SUN_FALSE + LIBGOMP_BUILD_VERSIONED_SHLIB_SUN_TRUE +@@ -11418,7 +11419,7 @@ else + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 11421 "configure" ++#line 11422 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +@@ -11524,7 +11525,7 @@ else + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 11527 "configure" ++#line 11528 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +@@ -16486,6 +16487,91 @@ $as_echo "unable to detect (assuming 1)" >&6; } + fi + + ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for flock implementation" >&5 ++$as_echo "$as_me: checking for flock implementation" >&6;} ++for ac_prog in flock ++do ++ # Extract the first word of "$ac_prog", so it can be a program name with args. ++set dummy $ac_prog; ac_word=$2 ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 ++$as_echo_n "checking for $ac_word... " >&6; } ++if ${ac_cv_prog_FLOCK+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ if test -n "$FLOCK"; then ++ ac_cv_prog_FLOCK="$FLOCK" # Let the user override the test. ++else ++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR ++for as_dir in $PATH ++do ++ IFS=$as_save_IFS ++ test -z "$as_dir" && as_dir=. ++ for ac_exec_ext in '' $ac_executable_extensions; do ++ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then ++ ac_cv_prog_FLOCK="$ac_prog" ++ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 ++ break 2 ++ fi ++done ++ done ++IFS=$as_save_IFS ++ ++fi ++fi ++FLOCK=$ac_cv_prog_FLOCK ++if test -n "$FLOCK"; then ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $FLOCK" >&5 ++$as_echo "$FLOCK" >&6; } ++else ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 ++$as_echo "no" >&6; } ++fi ++ ++ ++ test -n "$FLOCK" && break ++done ++ ++# Fallback if 'perl' is available. ++if test -z "$FLOCK"; then ++ # Extract the first word of "perl", so it can be a program name with args. ++set dummy perl; ac_word=$2 ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 ++$as_echo_n "checking for $ac_word... " >&6; } ++if ${ac_cv_prog_FLOCK+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ if test -n "$FLOCK"; then ++ ac_cv_prog_FLOCK="$FLOCK" # Let the user override the test. ++else ++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR ++for as_dir in $PATH ++do ++ IFS=$as_save_IFS ++ test -z "$as_dir" && as_dir=. ++ for ac_exec_ext in '' $ac_executable_extensions; do ++ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then ++ ac_cv_prog_FLOCK="$srcdir/testsuite/flock" ++ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 ++ break 2 ++ fi ++done ++ done ++IFS=$as_save_IFS ++ ++fi ++fi ++FLOCK=$ac_cv_prog_FLOCK ++if test -n "$FLOCK"; then ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $FLOCK" >&5 ++$as_echo "$FLOCK" >&6; } ++else ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 ++$as_echo "no" >&6; } ++fi ++ ++ ++fi ++ + # Get target configury. + . ${srcdir}/configure.tgt + CFLAGS="$save_CFLAGS $XCFLAGS" +--- a/src/libgomp/configure.ac ++++ b/src/libgomp/configure.ac +@@ -339,6 +339,13 @@ fi + AX_COUNT_CPUS + AC_SUBST(CPU_COUNT) + ++AC_MSG_NOTICE([checking for flock implementation]) ++AC_CHECK_PROGS(FLOCK, flock) ++# Fallback if 'perl' is available. ++if test -z "$FLOCK"; then ++ AC_CHECK_PROG(FLOCK, perl, $srcdir/testsuite/flock) ++fi ++ + # Get target configury. + . ${srcdir}/configure.tgt + CFLAGS="$save_CFLAGS $XCFLAGS" +--- a/src/libgomp/testsuite/Makefile.am ++++ b/src/libgomp/testsuite/Makefile.am +@@ -12,6 +12,8 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + RUNTESTDEFAULTFLAGS = --tool $$tool --srcdir $$srcdir + ++PWD_COMMAND = $${PWDCMD-pwd} ++ + EXTRA_DEJAGNU_SITE_CONFIG = libgomp-site-extra.exp + + # Instead of directly in ../testsuite/libgomp-test-support.exp.in, the +@@ -25,17 +27,6 @@ libgomp-test-support.exp: libgomp-test-support.pt.exp Makefile + 'set offload_additional_lib_paths "$(offload_additional_lib_paths)"' + mv $@.tmp $@ + +-check-DEJAGNU: site.exp +- srcdir='$(srcdir)'; export srcdir; \ +- EXPECT=$(EXPECT); export EXPECT; \ +- if $(SHELL) -c "$(_RUNTEST) --version" > /dev/null 2>&1; then \ +- exit_status=0; l='$(PACKAGE)'; for tool in $$l; do \ +- if $(_RUNTEST) $(AM_RUNTESTFLAGS) $(RUNTESTDEFAULTFLAGS) $(RUNTESTFLAGS); \ +- then :; else exit_status=1; fi; \ +- done; \ +- else echo "WARNING: could not find '$(_RUNTEST)'" 1>&2; :;\ +- fi; \ +- exit $$exit_status + site.exp: Makefile $(EXTRA_DEJAGNU_SITE_CONFIG) + @echo 'Making a new site.exp file ...' + @echo '## these variables are automatically generated by make ##' >site.tmp +@@ -63,6 +54,72 @@ site.exp: Makefile $(EXTRA_DEJAGNU_SITE_CONFIG) + @test ! -f site.exp || mv site.exp site.bak + @mv site.tmp site.exp + ++%/site.exp: site.exp ++ -@test -d $* || mkdir $* ++ @srcdir=`cd $(srcdir); ${PWD_COMMAND}`; ++ @objdir=`${PWD_COMMAND}`/$*; \ ++ sed -e "s|^set srcdir .*$$|set srcdir $$srcdir|" \ ++ -e "s|^set objdir .*$$|set objdir $$objdir|" \ ++ site.exp > $*/site.exp.tmp ++ @-rm -f $*/site.bak ++ @test ! -f $*/site.exp || mv $*/site.exp $*/site.bak ++ @mv $*/site.exp.tmp $*/site.exp ++ ++check_p_numbers0:=1 2 3 4 5 6 7 8 9 ++check_p_numbers1:=0 $(check_p_numbers0) ++check_p_numbers2:=$(foreach i,$(check_p_numbers0),$(addprefix $(i),$(check_p_numbers1))) ++check_p_numbers3:=$(addprefix 0,$(check_p_numbers1)) $(check_p_numbers2) ++check_p_numbers4:=$(foreach i,$(check_p_numbers0),$(addprefix $(i),$(check_p_numbers3))) ++check_p_numbers5:=$(addprefix 0,$(check_p_numbers3)) $(check_p_numbers4) ++check_p_numbers6:=$(foreach i,$(check_p_numbers0),$(addprefix $(i),$(check_p_numbers5))) ++check_p_numbers:=$(check_p_numbers0) $(check_p_numbers2) $(check_p_numbers4) $(check_p_numbers6) ++# If unable to serialize execution testing, use just one parallel slot. ++gcc_test_parallel_slots:=$(if $(FLOCK),$(if $(GCC_TEST_PARALLEL_SLOTS),$(GCC_TEST_PARALLEL_SLOTS),19),1) ++check_p_subdirs=$(wordlist 1,$(gcc_test_parallel_slots),$(check_p_numbers)) ++check_DEJAGNU_libgomp_targets = $(addprefix check-DEJAGNUlibgomp,$(check_p_subdirs)) ++$(check_DEJAGNU_libgomp_targets): check-DEJAGNUlibgomp%: libgomp%/site.exp ++ ++check-DEJAGNU $(check_DEJAGNU_libgomp_targets): check-DEJAGNU%: site.exp ++ $(if $*,@)AR="$(AR)"; export AR; \ ++ RANLIB="$(RANLIB)"; export RANLIB; \ ++ if [ -z "$*" ] && [ -n "$(filter -j%, $(MFLAGS))" ]; then \ ++ rm -rf libgomp-parallel || true; \ ++ mkdir libgomp-parallel; \ ++ $(MAKE) $(AM_MAKEFLAGS) $(check_DEJAGNU_libgomp_targets); \ ++ rm -rf libgomp-parallel || true; \ ++ for idx in $(check_p_subdirs); do \ ++ if [ -d libgomp$$idx ]; then \ ++ mv -f libgomp$$idx/libgomp.sum libgomp$$idx/libgomp.sum.sep; \ ++ mv -f libgomp$$idx/libgomp.log libgomp$$idx/libgomp.log.sep; \ ++ fi; \ ++ done; \ ++ $(SHELL) $(srcdir)/../../contrib/dg-extract-results.sh \ ++ libgomp[0-9]*/libgomp.sum.sep > libgomp.sum; \ ++ $(SHELL) $(srcdir)/../../contrib/dg-extract-results.sh -L \ ++ libgomp[0-9]*/libgomp.log.sep > libgomp.log; \ ++ exit 0; \ ++ fi; \ ++ srcdir=`$(am__cd) $(srcdir) && pwd`; export srcdir; \ ++ EXPECT=$(EXPECT); export EXPECT; \ ++ runtest=$(_RUNTEST); \ ++ if [ -z "$$runtest" ]; then runtest=runtest; fi; \ ++ tool=libgomp; \ ++ if [ -n "$*" ]; then \ ++ if [ -f libgomp-parallel/finished ]; then rm -rf "$*"; exit 0; fi; \ ++ GCC_RUNTEST_PARALLELIZE_DIR=`${PWD_COMMAND}`/libgomp-parallel; \ ++ export GCC_RUNTEST_PARALLELIZE_DIR; \ ++ cd "$*"; \ ++ fi; \ ++ if $(SHELL) -c "$$runtest --version" > /dev/null 2>&1; then \ ++ $$runtest $(AM_RUNTESTFLAGS) $(RUNTESTDEFAULTFLAGS) \ ++ $(RUNTESTFLAGS); \ ++ if [ -n "$*" ]; then \ ++ touch $$GCC_RUNTEST_PARALLELIZE_DIR/finished; \ ++ fi; \ ++ else \ ++ echo "WARNING: could not find \`runtest'" 1>&2; :;\ ++ fi ++ + distclean-DEJAGNU: + -rm -f site.exp site.bak + -l='$(PACKAGE)'; for tool in $$l; do \ +--- a/src/libgomp/testsuite/Makefile.in ++++ b/src/libgomp/testsuite/Makefile.in +@@ -161,6 +161,7 @@ EXEEXT = @EXEEXT@ + FC = @FC@ + FCFLAGS = @FCFLAGS@ + FGREP = @FGREP@ ++FLOCK = @FLOCK@ + GREP = @GREP@ + INSTALL = @INSTALL@ + INSTALL_DATA = @INSTALL_DATA@ +@@ -299,7 +300,20 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + + RUNTESTDEFAULTFLAGS = --tool $$tool --srcdir $$srcdir ++PWD_COMMAND = $${PWDCMD-pwd} + EXTRA_DEJAGNU_SITE_CONFIG = libgomp-site-extra.exp ++check_p_numbers0 := 1 2 3 4 5 6 7 8 9 ++check_p_numbers1 := 0 $(check_p_numbers0) ++check_p_numbers2 := $(foreach i,$(check_p_numbers0),$(addprefix $(i),$(check_p_numbers1))) ++check_p_numbers3 := $(addprefix 0,$(check_p_numbers1)) $(check_p_numbers2) ++check_p_numbers4 := $(foreach i,$(check_p_numbers0),$(addprefix $(i),$(check_p_numbers3))) ++check_p_numbers5 := $(addprefix 0,$(check_p_numbers3)) $(check_p_numbers4) ++check_p_numbers6 := $(foreach i,$(check_p_numbers0),$(addprefix $(i),$(check_p_numbers5))) ++check_p_numbers := $(check_p_numbers0) $(check_p_numbers2) $(check_p_numbers4) $(check_p_numbers6) ++# If unable to serialize execution testing, use just one parallel slot. ++gcc_test_parallel_slots := $(if $(FLOCK),$(if $(GCC_TEST_PARALLEL_SLOTS),$(GCC_TEST_PARALLEL_SLOTS),19),1) ++check_p_subdirs = $(wordlist 1,$(gcc_test_parallel_slots),$(check_p_numbers)) ++check_DEJAGNU_libgomp_targets = $(addprefix check-DEJAGNUlibgomp,$(check_p_subdirs)) + all: all-am + + .SUFFIXES: +@@ -474,17 +488,6 @@ libgomp-test-support.exp: libgomp-test-support.pt.exp Makefile + 'set offload_additional_lib_paths "$(offload_additional_lib_paths)"' + mv $@.tmp $@ + +-check-DEJAGNU: site.exp +- srcdir='$(srcdir)'; export srcdir; \ +- EXPECT=$(EXPECT); export EXPECT; \ +- if $(SHELL) -c "$(_RUNTEST) --version" > /dev/null 2>&1; then \ +- exit_status=0; l='$(PACKAGE)'; for tool in $$l; do \ +- if $(_RUNTEST) $(AM_RUNTESTFLAGS) $(RUNTESTDEFAULTFLAGS) $(RUNTESTFLAGS); \ +- then :; else exit_status=1; fi; \ +- done; \ +- else echo "WARNING: could not find '$(_RUNTEST)'" 1>&2; :;\ +- fi; \ +- exit $$exit_status + site.exp: Makefile $(EXTRA_DEJAGNU_SITE_CONFIG) + @echo 'Making a new site.exp file ...' + @echo '## these variables are automatically generated by make ##' >site.tmp +@@ -512,6 +515,59 @@ site.exp: Makefile $(EXTRA_DEJAGNU_SITE_CONFIG) + @test ! -f site.exp || mv site.exp site.bak + @mv site.tmp site.exp + ++%/site.exp: site.exp ++ -@test -d $* || mkdir $* ++ @srcdir=`cd $(srcdir); ${PWD_COMMAND}`; ++ @objdir=`${PWD_COMMAND}`/$*; \ ++ sed -e "s|^set srcdir .*$$|set srcdir $$srcdir|" \ ++ -e "s|^set objdir .*$$|set objdir $$objdir|" \ ++ site.exp > $*/site.exp.tmp ++ @-rm -f $*/site.bak ++ @test ! -f $*/site.exp || mv $*/site.exp $*/site.bak ++ @mv $*/site.exp.tmp $*/site.exp ++$(check_DEJAGNU_libgomp_targets): check-DEJAGNUlibgomp%: libgomp%/site.exp ++ ++check-DEJAGNU $(check_DEJAGNU_libgomp_targets): check-DEJAGNU%: site.exp ++ $(if $*,@)AR="$(AR)"; export AR; \ ++ RANLIB="$(RANLIB)"; export RANLIB; \ ++ if [ -z "$*" ] && [ -n "$(filter -j%, $(MFLAGS))" ]; then \ ++ rm -rf libgomp-parallel || true; \ ++ mkdir libgomp-parallel; \ ++ $(MAKE) $(AM_MAKEFLAGS) $(check_DEJAGNU_libgomp_targets); \ ++ rm -rf libgomp-parallel || true; \ ++ for idx in $(check_p_subdirs); do \ ++ if [ -d libgomp$$idx ]; then \ ++ mv -f libgomp$$idx/libgomp.sum libgomp$$idx/libgomp.sum.sep; \ ++ mv -f libgomp$$idx/libgomp.log libgomp$$idx/libgomp.log.sep; \ ++ fi; \ ++ done; \ ++ $(SHELL) $(srcdir)/../../contrib/dg-extract-results.sh \ ++ libgomp[0-9]*/libgomp.sum.sep > libgomp.sum; \ ++ $(SHELL) $(srcdir)/../../contrib/dg-extract-results.sh -L \ ++ libgomp[0-9]*/libgomp.log.sep > libgomp.log; \ ++ exit 0; \ ++ fi; \ ++ srcdir=`$(am__cd) $(srcdir) && pwd`; export srcdir; \ ++ EXPECT=$(EXPECT); export EXPECT; \ ++ runtest=$(_RUNTEST); \ ++ if [ -z "$$runtest" ]; then runtest=runtest; fi; \ ++ tool=libgomp; \ ++ if [ -n "$*" ]; then \ ++ if [ -f libgomp-parallel/finished ]; then rm -rf "$*"; exit 0; fi; \ ++ GCC_RUNTEST_PARALLELIZE_DIR=`${PWD_COMMAND}`/libgomp-parallel; \ ++ export GCC_RUNTEST_PARALLELIZE_DIR; \ ++ cd "$*"; \ ++ fi; \ ++ if $(SHELL) -c "$$runtest --version" > /dev/null 2>&1; then \ ++ $$runtest $(AM_RUNTESTFLAGS) $(RUNTESTDEFAULTFLAGS) \ ++ $(RUNTESTFLAGS); \ ++ if [ -n "$*" ]; then \ ++ touch $$GCC_RUNTEST_PARALLELIZE_DIR/finished; \ ++ fi; \ ++ else \ ++ echo "WARNING: could not find \`runtest'" 1>&2; :;\ ++ fi ++ + distclean-DEJAGNU: + -rm -f site.exp site.bak + -l='$(PACKAGE)'; for tool in $$l; do \ +--- a/src/libgomp/testsuite/config/default.exp ++++ b/src/libgomp/testsuite/config/default.exp +@@ -13,5 +13,3 @@ + # You should have received a copy of the GNU General Public License + # along with this program; see the file COPYING3. If not see + # . +- +-load_lib "standard.exp" +new file mode 100755 +--- /dev/null ++++ b/src/libgomp/testsuite/flock +@@ -0,0 +1,17 @@ ++#!/usr/bin/env perl ++ ++use strict; ++use warnings; ++ ++# Only arguments '--exclusive 1' exactly are supported. ++(@ARGV == 2) or die; ++my $mode = shift; ++($mode eq "--exclusive") or die; ++my $fd = shift; ++($fd eq "1") or die; ++ ++use Fcntl ':flock'; ++ ++open(my $fh, '>&=', 1) or die "open: $!"; ++ ++flock($fh, LOCK_EX) or die "flock: $!"; +--- a/src/libgomp/testsuite/lib/libgomp.exp ++++ b/src/libgomp/testsuite/lib/libgomp.exp +@@ -9,6 +9,7 @@ proc load_gcc_lib { filename } { + } + + load_lib dg.exp ++load_lib standard.exp + + # Required to use gcc-dg.exp - however, the latter should NOT be + # loaded until ${tool}_target_compile is defined since it uses that +@@ -42,7 +43,12 @@ load_gcc_lib torture-options.exp + load_gcc_lib fortran-modules.exp + + # Try to load a test support file, built during libgomp configuration. +-load_file libgomp-test-support.exp ++# Search in '..' vs. '.' to support parallel vs. sequential testing. ++if [info exists ::env(GCC_RUNTEST_PARALLELIZE_DIR)] { ++ load_file ../libgomp-test-support.exp ++} else { ++ load_file libgomp-test-support.exp ++} + + set dg-do-what-default run + +@@ -292,6 +298,36 @@ proc libgomp_option_proc { option } { + } + } + ++if ![info exists ::env(GCC_RUNTEST_PARALLELIZE_DIR)] { ++ # No parallel testing. ++} elseif { $FLOCK == "" } { ++ # Using just one parallel slot. ++} else { ++ # Using several parallel slots. Override DejaGnu ++ # 'standard.exp:${tool}_load'... ++ rename libgomp_load standard_libgomp_load ++ proc libgomp_load { program args } { ++ # ... in order to serialize execution testing via an exclusive lock. ++ # We use stdout, as per ++ # "[...] FILEHANDLE [...] be open with write intent to use LOCK_EX". ++ set lock_file ../lock ++ set lock_kind --exclusive ++ set lock_fd [open $lock_file a+] ++ set lock_clock_begin [clock seconds] ++ global FLOCK ++ exec $FLOCK $lock_kind 1 >@ $lock_fd ++ set lock_clock_end [clock seconds] ++ verbose -log "Got ${FLOCK}('$lock_file', '$lock_kind') at [clock format $lock_clock_end] after [expr $lock_clock_end - $lock_clock_begin] s" 2 ++ ++ set result [standard_libgomp_load $program $args] ++ ++ # Unlock (implicit with 'close'). ++ close $lock_fd ++ ++ return $result ++ } ++} ++ + # Translate offload target to OpenACC device type. Return the empty string if + # not supported, and 'host' for offload target 'disable'. + proc offload_target_to_openacc_device_type { offload_target } { +--- a/src/libgomp/testsuite/libgomp-site-extra.exp.in ++++ b/src/libgomp/testsuite/libgomp-site-extra.exp.in +@@ -1 +1,2 @@ ++set FLOCK {@FLOCK@} + set GCC_UNDER_TEST {@CC@} +--- a/src/libgomp/testsuite/libgomp.c++/c++.exp ++++ b/src/libgomp/testsuite/libgomp.c++/c++.exp +@@ -66,13 +66,12 @@ if { $lang_test_file_found } { + + set flags_file "${blddir}/../libstdc++-v3/scripts/testsuite_flags" + if { [file exists $flags_file] } { +- set libstdcxx_includes [exec sh $flags_file --build-includes] +- } else { +- set libstdcxx_includes "" ++ set lang_source_re {^.*\.[cC]$} ++ set lang_include_flags [exec sh $flags_file --build-includes] + } + + # Main loop. +- dg-runtest $tests "" "$libstdcxx_includes $DEFAULT_CFLAGS" ++ dg-runtest $tests "" $DEFAULT_CFLAGS + } + + # See above. +new file mode 100644 +--- /dev/null ++++ b/src/libgomp/testsuite/libgomp.c++/target-map-class-1.C +@@ -0,0 +1,98 @@ ++/* PR middle-end/109816 */ ++ ++/* This variant: without -flto, see target-map-class-2.C for -flto. */ ++ ++/* iostream.h adds 'globl _ZSt21ios_base_library_initv' with _GLIBCXX_SYMVER_GNU, ++ but it shouldn't end up in the offload assembly but only in the host assembly. */ ++ ++/* Example based on sollve_vv's test_target_data_map_classes.cpp; however, ++ relevant is only the 'include' and not the actual executable code. */ ++ ++#include ++#include ++ ++using namespace std; ++ ++#define N 1000 ++ ++struct A ++{ ++ int *h_array; ++ int size, sum; ++ ++ A (int *array, const int s) : h_array(array), size(s), sum(0) { } ++ ~A() { h_array = NULL; } ++}; ++ ++void ++test_map_tofrom_class_heap () ++{ ++ int *array = new int[N]; ++ A *obj = new A (array, N); ++ ++ #pragma omp target map(from: array[:N]) map(tofrom: obj[:1]) ++ { ++ int *tmp_h_array = obj->h_array; ++ obj->h_array = array; ++ int tmp = 0; ++ for (int i = 0; i < N; ++i) ++ { ++ obj->h_array[i] = 4*i; ++ tmp += 3; ++ } ++ obj->h_array = tmp_h_array; ++ obj->sum = tmp; ++ } ++ ++ for (int i = 0; i < N; ++i) ++ if (obj->h_array[i] != 4*i) ++ __builtin_abort (); ++ ++ if (3*N != obj->sum) ++ { ++ std::cout << "sum: " << obj->sum << std::endl; ++ __builtin_abort (); ++ } ++ ++ delete obj; ++ delete[] array; ++} ++ ++void ++test_map_tofrom_class_stack () ++{ ++ int array[N]; ++ A obj(array, N); ++ ++ #pragma omp target map(from: array[:N]) map(tofrom: obj) ++ { ++ int *tmp_h_array = obj.h_array; ++ obj.h_array = array; ++ int tmp = 0; ++ for (int i = 0; i < N; ++i) ++ { ++ obj.h_array[i] = 7*i; ++ tmp += 5; ++ } ++ obj.h_array = tmp_h_array; ++ obj.sum = tmp; ++ } ++ ++ for (int i = 0; i < N; ++i) ++ if (obj.h_array[i] != 7*i) ++ __builtin_abort (); ++ ++ if (5*N != obj.sum) ++ { ++ std::cout << "sum: " << obj.sum << std::endl; ++ __builtin_abort (); ++ } ++} ++ ++int ++main() ++{ ++ test_map_tofrom_class_heap(); ++ test_map_tofrom_class_stack(); ++ return 0; ++} +new file mode 100644 +--- /dev/null ++++ b/src/libgomp/testsuite/libgomp.c++/target-map-class-2.C +@@ -0,0 +1,6 @@ ++/* { dg-additional-options "-flto" } */ ++/* PR middle-end/109816 */ ++ ++/* This variant: with -flto, see target-map-class-1.C for without -flto. */ ++ ++#include "target-map-class-1.C" +--- a/src/libgomp/testsuite/libgomp.oacc-c++/c++.exp ++++ b/src/libgomp/testsuite/libgomp.oacc-c++/c++.exp +@@ -72,9 +72,8 @@ if { $lang_test_file_found } { + + set flags_file "${blddir}/../libstdc++-v3/scripts/testsuite_flags" + if { [file exists $flags_file] } { +- set libstdcxx_includes [exec sh $flags_file --build-includes] +- } else { +- set libstdcxx_includes "" ++ set lang_source_re {^.*\.[cC]$} ++ set lang_include_flags [exec sh $flags_file --build-includes] + } + + # Test with all available offload targets, and with offloading disabled. +@@ -147,7 +146,7 @@ if { $lang_test_file_found } { + } + } + +- gcc-dg-runtest $tests "$tagopt" "$libstdcxx_includes" ++ gcc-dg-runtest $tests "$tagopt" "" + } + unset offload_target + } else { new file mode 100644 --- /dev/null +++ b/src/libgomp/testsuite/libgomp.oacc-fortran/pr109622-2.f90 @@ -237708,120 +325696,752 @@ + +var%bar => tgt + -+var%foo = 99 -+tgt = 199 ++var%foo = 99 ++tgt = 199 ++ ++!$acc enter data copyin(var, tgt) ++ ++!$acc enter data attach(var%bar) ++ ++!$acc serial ++! { dg-warning "using .vector_length \\(32\\)., ignoring 1" "" { target openacc_nvidia_accel_selected } .-1 } ++var%foo = 5 ++var%bar = 7 ++!$acc end serial ++ ++!$acc exit data detach(var%bar) ++ ++!$acc exit data copyout(var, tgt) ++ ++if (var%foo.ne.5) stop 1 ++if (any(tgt.ne.7)) stop 2 ++ ++end +new file mode 100644 +--- /dev/null ++++ b/src/libgomp/testsuite/libgomp.oacc-fortran/pr109622-4.f90 +@@ -0,0 +1,47 @@ ++! { dg-do run } ++ ++use openacc ++implicit none ++ ++type t ++integer :: foo ++character(len=8), pointer :: bar ++character(len=4), allocatable :: qux ++end type t ++ ++type(t) :: var ++character(len=8), target :: tgt ++ ++allocate(var%qux) ++ ++var%bar => tgt ++ ++var%foo = 99 ++tgt = "Octopus!" ++var%qux = "Fish" ++ ++!$acc enter data copyin(var, tgt) ++ ++! Avoid automatic attach (i.e. with "enter data") ++call acc_copyin (var%qux) ++ ++!$acc enter data attach(var%bar, var%qux) ++ ++!$acc serial ++! { dg-warning "using .vector_length \\(32\\)., ignoring 1" "" { target openacc_nvidia_accel_selected } .-1 } ++var%foo = 5 ++var%bar = "Plankton" ++var%qux = "Pond" ++!$acc end serial ++ ++!$acc exit data detach(var%bar, var%qux) ++ ++call acc_copyout (var%qux) ++ ++!$acc exit data copyout(var, tgt) ++ ++if (var%foo.ne.5) stop 1 ++if (tgt.ne."Plankton") stop 2 ++if (var%qux.ne."Pond") stop 3 ++ ++end +new file mode 100644 +--- /dev/null ++++ b/src/libgomp/testsuite/libgomp.oacc-fortran/pr109622.f90 +@@ -0,0 +1,35 @@ ++! { dg-do run } ++ ++implicit none ++ ++type t ++integer :: value ++type(t), pointer :: chain ++end type t ++ ++type(t), target :: var, var2 ++ ++var%value = 99 ++var2%value = 199 ++ ++var%chain => var2 ++nullify(var2%chain) ++ ++!$acc enter data copyin(var, var2) ++ ++!$acc enter data attach(var%chain) ++ ++!$acc serial ++! { dg-warning "using .vector_length \\(32\\)., ignoring 1" "" { target openacc_nvidia_accel_selected } .-1 } ++var%value = 5 ++var%chain%value = 7 ++!$acc end serial ++ ++!$acc exit data detach(var%chain) ++ ++!$acc exit data copyout(var, var2) ++ ++if (var%value.ne.5) stop 1 ++if (var2%value.ne.7) stop 2 ++ ++end +--- a/src/libphobos/ChangeLog ++++ b/src/libphobos/ChangeLog +@@ -1,3 +1,30 @@ ++2023-07-03 Iain Sandoe ++ ++ Backported from master: ++ 2023-07-02 Iain Sandoe ++ ++ * libdruntime/config/aarch64/switchcontext.S: Exclude ELF- ++ specific constructs for Darwin. ++ * libdruntime/config/arm/switchcontext.S: Likewise. ++ * libdruntime/core/thread/fiber.d: Disable switching fibres ++ between threads. ++ ++2023-07-03 Iain Sandoe ++ ++ Backported from master: ++ 2023-07-01 Iain Sandoe ++ ++ PR d/103944 ++ * testsuite/libphobos.gc/forkgc2.d: Skip for Darwin. ++ ++2023-06-26 Iain Buclaw ++ ++ Backported from master: ++ 2023-06-25 Iain Buclaw ++ ++ * libdruntime/MERGE: Merge upstream druntime a45f4e9f43. ++ * src/MERGE: Merge upstream phobos 106038f2e. ++ + 2023-04-26 Release Manager + + * GCC 13.1.0 released. +--- a/src/libphobos/libdruntime/MERGE ++++ b/src/libphobos/libdruntime/MERGE +@@ -1,4 +1,4 @@ +-5f7552bb2829b75d5e36cc767a476e1ab35147b7 ++a45f4e9f43e9fdbf0b666175e5e66b1ce4f561f6 + + The first line of this file holds the git revision number of the last + merge done from the dlang/dmd repository. +--- a/src/libphobos/libdruntime/config/aarch64/switchcontext.S ++++ b/src/libphobos/libdruntime/config/aarch64/switchcontext.S +@@ -44,7 +44,9 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + */ + .text + .global CSYM(fiber_switchContext) ++#ifndef __APPLE__ + .type CSYM(fiber_switchContext), %function ++#endif + .align 4 + CSYM(fiber_switchContext): + .cfi_startproc +@@ -77,8 +79,9 @@ CSYM(fiber_switchContext): + ldp d15, d14, [sp], #20*8 + ret + .cfi_endproc ++#ifndef __APPLE__ + .size CSYM(fiber_switchContext),.-CSYM(fiber_switchContext) +- ++#endif + /** + * When generating any kind of backtrace (gdb, exception handling) for + * a function called in a Fiber, we need to tell the unwinder to stop +@@ -93,11 +96,15 @@ CSYM(fiber_switchContext): + .text + .global CSYM(fiber_trampoline) + .p2align 2 ++#ifndef __APPLE__ + .type CSYM(fiber_trampoline), %function ++#endif + CSYM(fiber_trampoline): + .cfi_startproc + .cfi_undefined x30 + // fiber_entryPoint never returns + bl CSYM(fiber_entryPoint) + .cfi_endproc ++#ifndef __APPLE__ + .size CSYM(fiber_trampoline),.-CSYM(fiber_trampoline) ++#endif +--- a/src/libphobos/libdruntime/config/arm/switchcontext.S ++++ b/src/libphobos/libdruntime/config/arm/switchcontext.S +@@ -60,11 +60,15 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + */ + + .text ++#ifndef __APPLE__ + #if defined(__ARM_PCS_VFP) || (defined(__ARM_PCS) && !defined(__SOFTFP__)) + .fpu vfp + #endif + .global CSYM(fiber_switchContext) + .type CSYM(fiber_switchContext), %function ++#else ++ .global CSYM(fiber_switchContext) ++#endif + .align 4 + CSYM(fiber_switchContext): + .cfi_sections .debug_frame +@@ -111,8 +115,12 @@ CSYM(fiber_switchContext): + mov lr, #0 + // return by writing lr into pc + mov pc, r1 ++#ifndef __APPLE__ + .fnend + .cfi_endproc + .size CSYM(fiber_switchContext),.-CSYM(fiber_switchContext) ++#else ++ .cfi_endproc ++#endif + + #endif +--- a/src/libphobos/libdruntime/core/sys/windows/stacktrace.d ++++ b/src/libphobos/libdruntime/core/sys/windows/stacktrace.d +@@ -239,6 +239,8 @@ private: + if (frameNum >= skip) + { + buffer[nframes++] = stackframe.AddrPC.Offset; ++ if (nframes >= buffer.length) ++ break; + } + frameNum++; + } +--- a/src/libphobos/libdruntime/core/thread/fiber.d ++++ b/src/libphobos/libdruntime/core/thread/fiber.d +@@ -1785,6 +1785,7 @@ version (OSX) + { + version (X86) version = UnsafeFiberMigration; + version (X86_64) version = UnsafeFiberMigration; ++ version (AArch64) version = UnsafeFiberMigration; + } + + version (UnsafeFiberMigration) +--- a/src/libphobos/src/MERGE ++++ b/src/libphobos/src/MERGE +@@ -1,4 +1,4 @@ +-67a47cf39d52b3cb3ae4117c0237415e03737f8a ++106038f2eaa70045bf25b29bb1c789304a6065f7 + + The first line of this file holds the git revision number of the last + merge done from the dlang/phobos repository. +--- a/src/libphobos/src/std/functional.d ++++ b/src/libphobos/src/std/functional.d +@@ -48,6 +48,9 @@ $(TR $(TH Function Name) $(TH Description) + $(TD Create a unary or binary function from a string. Most often + used when defining algorithms on ranges. + )) ++ $(TR $(TD $(LREF bind)) ++ $(TD Passes the fields of a struct as arguments to a function. ++ )) + )) + + Copyright: Copyright Andrei Alexandrescu 2008 - 2009. +--- a/src/libphobos/testsuite/libphobos.gc/forkgc2.d ++++ b/src/libphobos/testsuite/libphobos.gc/forkgc2.d +@@ -1,3 +1,4 @@ ++// { dg-skip-if "test hangs the testsuite PR103944" { *-*-darwin* } } + import core.stdc.stdlib : exit; + import core.sys.posix.sys.wait : waitpid; + import core.sys.posix.unistd : fork; +--- a/src/libstdc++-v3/ChangeLog ++++ b/src/libstdc++-v3/ChangeLog +@@ -1,3 +1,708 @@ ++2023-07-06 Jonathan Wakely ++ ++ Backported from master: ++ 2023-07-06 Jonathan Wakely ++ ++ PR libstdc++/104299 ++ * doc/xml/manual/configure.xml: Describe stdio_pure argument to ++ --enable-cstdio. ++ * doc/html/manual/configure.html: Regenerate. ++ ++2023-06-29 Jonathan Wakely ++ ++ Backported from master: ++ 2023-05-31 Jonathan Wakely ++ ++ * acinclude.m4 (GLIBCXX_ZONEINFO_DIR): Fix for 32-bit pointers ++ to check __INT_PTR_WIDTH__ instead of sizeof(void*). ++ * configure: Regenerate. ++ ++2023-06-29 Jonathan Wakely ++ ++ Backported from master: ++ 2023-05-31 Jonathan Wakely ++ ++ * acinclude.m4 (GLIBCXX_ZONEINFO_DIR): Extend logic for avr and ++ msp430 to all 16-bit targets. ++ * configure: Regenerate. ++ ++2023-06-29 Jonathan Wakely ++ ++ Backported from master: ++ 2023-06-26 Jonathan Wakely ++ ++ PR libstdc++/110239 ++ * include/std/format (__format::__parse_integer): Fix buffer ++ overflow for wide chars. ++ (formatter::format): Cast to uintptr_t instead ++ of uint64_t. ++ * testsuite/std/format/string.cc: Test too-large widths. ++ ++2023-06-29 Jonathan Wakely ++ ++ Backported from master: ++ 2023-06-09 Jonathan Wakely ++ ++ PR libstdc++/110149 ++ * include/std/format (formatter::parse): ++ Only alow 0 and P for C++26 and non-strict modes. ++ (formatter::format): Use toupper for P ++ type, and insert zero-fill characters for 0 option. ++ * testsuite/std/format/functions/format.cc: Check pointer ++ formatting. Only check P2510R3 extensions conditionally. ++ * testsuite/std/format/parse_ctx.cc: Only check P2510R3 ++ extensions conditionally. ++ ++2023-06-29 Jonathan Wakely ++ ++ Backported from master: ++ 2023-05-16 Jonathan Wakely ++ ++ PR libstdc++/109741 ++ * acinclude.m4 (GLIBCXX_CHECK_ALIGNAS_CACHELINE): Define. ++ * config.h.in: Regenerate. ++ * configure: Regenerate. ++ * configure.ac: Use GLIBCXX_CHECK_ALIGNAS_CACHELINE. ++ * src/c++11/shared_ptr.cc (__gnu_internal::get_mutex): Do not ++ align lock table if not supported. use __GCC_DESTRUCTIVE_SIZE ++ instead of hardcoded 64. ++ ++2023-06-29 Jonathan Wakely ++ ++ Backported from master: ++ 2023-06-09 Jonathan Wakely ++ ++ PR libstdc++/100285 ++ * include/experimental/internet [IPPROTO_TCP || IPPROTO_UDP] ++ (basic_endpoint, basic_resolver_entry, resolver_base) ++ (basic_resolver_results, basic_resolver): Only define if the tcp ++ or udp protocols will be defined. ++ ++2023-06-29 Jonathan Wakely ++ ++ Backported from master: ++ 2023-06-07 Jonathan Wakely ++ ++ * testsuite/20_util/duration/cons/2.cc: Use values that aren't ++ affected by rounding. ++ * testsuite/20_util/from_chars/5.cc: Cast arithmetic result to ++ double before comparing for equality. ++ * testsuite/20_util/from_chars/6.cc: Likewise. ++ * testsuite/20_util/variant/86874.cc: Use values that aren't ++ affected by rounding. ++ * testsuite/25_algorithms/lower_bound/partitioned.cc: Compare to ++ original value instead of to floating-point-literal. ++ * testsuite/26_numerics/random/discrete_distribution/cons/range.cc: ++ Cast arithmetic result to double before comparing for equality. ++ * testsuite/26_numerics/random/piecewise_constant_distribution/cons/range.cc: ++ Likewise. ++ * testsuite/26_numerics/random/piecewise_linear_distribution/cons/range.cc: ++ Likewise. ++ * testsuite/26_numerics/valarray/transcend.cc (eq): Check that ++ the absolute difference is less than 0.01 instead of comparing ++ to two decimal places. ++ * testsuite/27_io/basic_istream/extractors_arithmetic/char/01.cc: ++ Cast arithmetic result to double before comparing for equality. ++ * testsuite/27_io/basic_istream/extractors_arithmetic/char/09.cc: ++ Likewise. ++ * testsuite/27_io/basic_istream/extractors_arithmetic/char/10.cc: ++ Likewise. ++ * testsuite/27_io/basic_istream/extractors_arithmetic/wchar_t/01.cc: ++ Likewise. ++ * testsuite/27_io/basic_istream/extractors_arithmetic/wchar_t/09.cc: ++ Likewise. ++ * testsuite/27_io/basic_istream/extractors_arithmetic/wchar_t/10.cc: ++ Likewise. ++ * testsuite/ext/random/hoyt_distribution/cons/parms.cc: Likewise. ++ ++2023-06-29 Jonathan Wakely ++ ++ Backported from master: ++ 2023-05-31 Jonathan Wakely ++ ++ * include/std/scoped_allocator (scoped_allocator_adaptor): Add ++ noexcept to all constructors except the default constructor. ++ (scoped_allocator_adaptor::inner_allocator): Add noexcept. ++ (scoped_allocator_adaptor::outer_allocator): Likewise. ++ * testsuite/20_util/scoped_allocator/noexcept.cc: New test. ++ ++2023-06-29 Jonathan Wakely ++ ++ Backported from master: ++ 2023-06-09 Jonathan Wakely ++ ++ * testsuite/23_containers/deque/modifiers/emplace/52799.cc: ++ Removed. ++ * testsuite/23_containers/deque/modifiers/emplace/const_iterator.cc: ++ Removed. ++ * testsuite/23_containers/list/modifiers/emplace/52799.cc: ++ Removed. ++ * testsuite/23_containers/list/modifiers/emplace/const_iterator.cc: ++ Removed. ++ * testsuite/23_containers/vector/modifiers/emplace/52799.cc: ++ Removed. ++ * testsuite/23_containers/vector/modifiers/emplace/const_iterator.cc: ++ Removed. ++ * testsuite/23_containers/deque/modifiers/emplace/1.cc: New ++ test. ++ * testsuite/23_containers/list/modifiers/emplace/1.cc: New ++ test. ++ * testsuite/23_containers/vector/modifiers/emplace/1.cc: New ++ test. ++ ++2023-06-06 Jonathan Wakely ++ ++ Backported from master: ++ 2023-06-01 Jonathan Wakely ++ ++ * include/std/expected (expected::and_then, expected::or_else) ++ (expected::transform_error): Use _M_val and _M_unex instead of ++ calling value() and error(), as per LWG 3938. ++ (expected::transform): Likewise. Remove incorrect std::move ++ calls from lvalue overloads. ++ (expected::and_then, expected::or_else) ++ (expected::transform): Use _M_unex instead of calling ++ error(). ++ * testsuite/20_util/expected/lwg3877.cc: Add checks for and_then ++ and transform, and for std::expected. ++ * testsuite/20_util/expected/lwg3938.cc: New test. ++ ++2023-06-06 Jonathan Wakely ++ ++ Backported from master: ++ 2023-05-17 Jonathan Wakely ++ ++ * include/std/expected (expected::and_then, expected::or_else) ++ (expected::transform, expected::transform_error): Fix exception ++ specifications as per LWG 3877. ++ (expected::and_then, expected::transform): ++ Likewise. ++ * testsuite/20_util/expected/lwg3877.cc: New test. ++ ++2023-06-06 Jonathan Wakely ++ ++ Backported from master: ++ 2023-06-06 Jonathan Wakely ++ ++ PR libstdc++/108178 ++ * src/filesystem/ops-common.h (do_copy_file): Check for empty ++ files by trying to read a character. ++ * testsuite/27_io/filesystem/operations/copy_file_108178.cc: ++ New test. ++ ++2023-06-06 Jonathan Wakely ++ ++ Backported from master: ++ 2023-06-06 Jonathan Wakely ++ ++ * src/filesystem/ops-common.h (do_copy_file) [O_CLOEXEC]: Set ++ close-on-exec flag on file descriptors. ++ ++2023-06-06 Jonathan Wakely ++ ++ Backported from master: ++ 2023-06-06 Jonathan Wakely ++ ++ PR libstdc++/110139 ++ * include/std/array (__array_traits::operator T*()): Make ++ conversion operator explicit. ++ (array::front): Use size_type as subscript operand. ++ (array::data): Use static_cast to make conversion explicit. ++ * testsuite/23_containers/array/element_access/110139.cc: New ++ test. ++ ++2023-06-06 Joseph Faulls ++ ++ Backported from master: ++ 2023-06-06 Joseph Faulls ++ ++ * include/bits/locale_classes.tcc: Remove check for ++ codecvt facet. ++ ++2023-06-01 Jonathan Wakely ++ ++ Backported from master: ++ 2023-05-11 Jonathan Wakely ++ ++ PR libstdc++/109758 ++ * include/bits/std_abs.h (abs(__float128)): Handle negative NaN ++ and negative zero correctly. ++ * testsuite/26_numerics/headers/cmath/109758.cc: New test. ++ ++2023-06-01 Jonathan Wakely ++ ++ Backported from master: ++ 2023-05-12 Jonathan Wakely ++ ++ * testsuite/experimental/feat-cxx14.cc: Remove dependency on ++ _GLIBCXX_USE_C99_STDINT_TR1. ++ ++2023-06-01 Jonathan Wakely ++ ++ Backported from master: ++ 2023-05-12 Jonathan Wakely ++ ++ * testsuite/21_strings/basic_string_view/typedefs.cc: Remove ++ dependency on _GLIBCXX_USE_C99_STDINT_TR1. ++ * testsuite/experimental/string_view/typedefs.cc: Likewise. ++ ++2023-06-01 Jonathan Wakely ++ ++ Backported from master: ++ 2023-06-01 Jonathan Wakely ++ ++ * testsuite/26_numerics/pstl/numeric_ops/transform_reduce.cc: ++ Add const to equality operator. ++ ++2023-06-01 Jonathan Wakely ++ ++ Backported from master: ++ 2023-06-01 Jonathan Wakely ++ ++ * doc/xml/manual/evolution.xml: Document removal of implicit ++ allocator rebinding extensions in strict mode and for C++20. ++ * doc/html/*: Regenerate. ++ ++2023-06-01 Jonathan Wakely ++ ++ Backported from master: ++ 2023-05-12 Jonathan Wakely ++ ++ * acinclude.m4 (GLIBCXX_CHECK_C99_TR1): Use a non-null pointer ++ to check for nan, nanf, and nanl. ++ * configure: Regenerate. ++ ++2023-06-01 Jonathan Wakely ++ ++ Backported from master: ++ 2023-05-16 Jonathan Wakely ++ ++ * testsuite/libstdc++-prettyprinters/chrono.cc: Only test ++ printer for chrono::zoned_time for cx11 ABI and tzdb effective ++ target. ++ ++2023-06-01 Jonathan Wakely ++ ++ Backported from master: ++ 2023-05-09 Jonathan Wakely ++ ++ * python/libstdcxx/v6/printers.py (StdChronoDurationPrinter): ++ Print floating-point durations correctly. ++ (StdChronoTimePointPrinter): Support printing only the value, ++ not the type name. Uncomment handling for known clocks. ++ (StdChronoZonedTimePrinter): Remove type names from output. ++ (StdChronoCalendarPrinter): Fix hh_mm_ss member access. ++ (StdChronoTimeZonePrinter): Add equals sign to output. ++ * testsuite/libstdc++-prettyprinters/chrono.cc: New test. ++ ++2023-05-30 Alexandre Oliva ++ ++ Backported from master: ++ 2023-05-30 Alexandre Oliva ++ ++ * testsuite/20_util/from_chars/4.cc: Skip long double test06 ++ on x86_64-vxworks. ++ * testsuite/20_util/to_chars/long_double.cc: Xfail run on ++ x86_64-vxworks. ++ ++2023-05-30 Matthias Kretz ++ ++ Backported from master: ++ 2023-05-30 Matthias Kretz ++ ++ PR libstdc++/109822 ++ * include/experimental/bits/simd.h (to_native): Use int NTTP ++ as specified in PTS2. ++ (to_compatible): Likewise. Add missing tag to call mask ++ generator ctor. ++ * testsuite/experimental/simd/pr109822_cast_functions.cc: New ++ test. + -+!$acc enter data copyin(var, tgt) ++2023-05-30 Matthias Kretz + -+!$acc enter data attach(var%bar) ++ Backported from master: ++ 2023-05-30 Matthias Kretz + -+!$acc serial -+! { dg-warning "using .vector_length \\(32\\)., ignoring 1" "" { target openacc_nvidia_accel_selected } .-1 } -+var%foo = 5 -+var%bar = 7 -+!$acc end serial ++ * testsuite/experimental/simd/tests/integer_operators.cc: ++ Compute expected value differently to avoid getting turned into ++ a vector shift. + -+!$acc exit data detach(var%bar) ++2023-05-30 Matthias Kretz + -+!$acc exit data copyout(var, tgt) ++ Backported from master: ++ 2023-05-30 Matthias Kretz + -+if (var%foo.ne.5) stop 1 -+if (any(tgt.ne.7)) stop 2 ++ * testsuite/experimental/simd/tests/operator_cvt.cc: Make long ++ double <-> (u)long conversion tests conditional on sizeof(long ++ double) and sizeof(long). + -+end -new file mode 100644 ---- /dev/null -+++ b/src/libgomp/testsuite/libgomp.oacc-fortran/pr109622-4.f90 -@@ -0,0 +1,47 @@ -+! { dg-do run } ++2023-05-30 Matthias Kretz + -+use openacc -+implicit none ++ Backported from master: ++ 2023-05-26 Matthias Kretz + -+type t -+integer :: foo -+character(len=8), pointer :: bar -+character(len=4), allocatable :: qux -+end type t ++ * include/experimental/bits/simd_ppc.h (_S_bit_shift_left): ++ Negative __y is UB, so prefer signed compare. + -+type(t) :: var -+character(len=8), target :: tgt ++2023-05-25 Alexandre Oliva + -+allocate(var%qux) ++ Backported from master: ++ 2023-05-25 Alexandre Oliva + -+var%bar => tgt ++ * testsuite/20_util/to_chars/long_double.cc: Expect execution ++ fail on x86-vxworks. + -+var%foo = 99 -+tgt = "Octopus!" -+var%qux = "Fish" ++2023-05-25 Matthias Kretz + -+!$acc enter data copyin(var, tgt) ++ Backported from master: ++ 2023-05-23 Matthias Kretz + -+! Avoid automatic attach (i.e. with "enter data") -+call acc_copyin (var%qux) ++ PR libstdc++/109261 ++ * include/experimental/bits/simd.h (_SimdWrapper::_M_set): ++ Avoid vector builtin subscripting in constant expressions. ++ (resizing_simd_cast): Avoid memcpy if constant_evaluated. ++ (const_where_expression, where_expression, where) ++ (__extract_part, simd_mask, _SimdIntOperators, simd): Add either ++ _GLIBCXX_SIMD_CONSTEXPR (on public APIs), or constexpr (on ++ internal APIs). ++ * include/experimental/bits/simd_builtin.h (__vector_permute) ++ (__vector_shuffle, __extract_part, _GnuTraits::_SimdCastType1) ++ (_GnuTraits::_SimdCastType2, _SimdImplBuiltin) ++ (_MaskImplBuiltin::_S_store): Add constexpr. ++ (_CommonImplBuiltin::_S_store_bool_array) ++ (_SimdImplBuiltin::_S_load, _SimdImplBuiltin::_S_store) ++ (_SimdImplBuiltin::_S_reduce, _MaskImplBuiltin::_S_load): Add ++ constant_evaluated case. ++ * include/experimental/bits/simd_fixed_size.h ++ (_S_masked_load): Reword comment. ++ (__tuple_element_meta, __make_meta, _SimdTuple::_M_apply_r) ++ (_SimdTuple::_M_subscript_read, _SimdTuple::_M_subscript_write) ++ (__make_simd_tuple, __optimize_simd_tuple, __extract_part) ++ (__autocvt_to_simd, _Fixed::__traits::_SimdBase) ++ (_Fixed::__traits::_SimdCastType, _SimdImplFixedSize): Add ++ constexpr. ++ (_SimdTuple::operator[], _M_set): Add constexpr and add ++ constant_evaluated case. ++ (_MaskImplFixedSize::_S_load): Add constant_evaluated case. ++ * include/experimental/bits/simd_scalar.h: Add constexpr. ++ * include/experimental/bits/simd_x86.h (_CommonImplX86): Add ++ constexpr and add constant_evaluated case. ++ (_SimdImplX86::_S_equal_to, _S_not_equal_to, _S_less) ++ (_S_less_equal): Value-initialize to satisfy constexpr ++ evaluation. ++ (_MaskImplX86::_S_load): Add constant_evaluated case. ++ (_MaskImplX86::_S_store): Add constexpr and constant_evaluated ++ case. Value-initialize local variables. ++ (_MaskImplX86::_S_logical_and, _S_logical_or, _S_bit_not) ++ (_S_bit_and, _S_bit_or, _S_bit_xor): Add constant_evaluated ++ case. ++ * testsuite/experimental/simd/pr109261_constexpr_simd.cc: New ++ test. + -+!$acc enter data attach(var%bar, var%qux) ++2023-05-25 Matthias Kretz + -+!$acc serial -+! { dg-warning "using .vector_length \\(32\\)., ignoring 1" "" { target openacc_nvidia_accel_selected } .-1 } -+var%foo = 5 -+var%bar = "Plankton" -+var%qux = "Pond" -+!$acc end serial ++ Backported from master: ++ 2023-05-24 Matthias Kretz + -+!$acc exit data detach(var%bar, var%qux) ++ PR libstdc++/109949 ++ * include/experimental/bits/simd.h (__intrinsic_type): If ++ __ALTIVEC__ is defined, map gnu::vector_size types to their ++ corresponding __vector T types without losing unsignedness of ++ integer types. Also prefer long long over long. ++ * include/experimental/bits/simd_ppc.h (_S_popcount): Cast mask ++ object to the expected unsigned vector type. + -+call acc_copyout (var%qux) ++2023-05-25 Matthias Kretz + -+!$acc exit data copyout(var, tgt) ++ Backported from master: ++ 2023-05-24 Matthias Kretz + -+if (var%foo.ne.5) stop 1 -+if (tgt.ne."Plankton") stop 2 -+if (var%qux.ne."Pond") stop 3 ++ PR libstdc++/109261 ++ * include/experimental/bits/simd_neon.h (_S_reduce): Add ++ constexpr and make NEON implementation conditional on ++ not __builtin_is_constant_evaluated. + -+end -new file mode 100644 ---- /dev/null -+++ b/src/libgomp/testsuite/libgomp.oacc-fortran/pr109622.f90 -@@ -0,0 +1,35 @@ -+! { dg-do run } ++2023-05-25 Matthias Kretz + -+implicit none ++ Backported from master: ++ 2023-05-24 Matthias Kretz + -+type t -+integer :: value -+type(t), pointer :: chain -+end type t ++ PR libstdc++/109261 ++ * include/experimental/bits/simd.h (__intrinsic_type): ++ Specialize __intrinsic_type and ++ __intrinsic_type in any case, but provide the member ++ type only with __aarch64__. + -+type(t), target :: var, var2 ++2023-05-25 Matthias Kretz + -+var%value = 99 -+var2%value = 199 ++ Backported from master: ++ 2023-05-22 Matthias Kretz + -+var%chain => var2 -+nullify(var2%chain) ++ * include/experimental/bits/simd_builtin.h (_S_fpclassify): Move ++ __infn into #ifdef'ed block. ++ * testsuite/experimental/simd/tests/fpclassify.cc: Declare ++ constants only when used. ++ * testsuite/experimental/simd/tests/frexp.cc: Likewise. ++ * testsuite/experimental/simd/tests/logarithm.cc: Likewise. ++ * testsuite/experimental/simd/tests/trunc_ceil_floor.cc: ++ Likewise. ++ * testsuite/experimental/simd/tests/ldexp_scalbn_scalbln_modf.cc: ++ Move totest and expect1 into #ifdef'ed block. + -+!$acc enter data copyin(var, var2) ++2023-05-17 Jakub Jelinek + -+!$acc enter data attach(var%chain) ++ Backported from master: ++ 2023-05-17 Jakub Jelinek + -+!$acc serial -+! { dg-warning "using .vector_length \\(32\\)., ignoring 1" "" { target openacc_nvidia_accel_selected } .-1 } -+var%value = 5 -+var%chain%value = 7 -+!$acc end serial ++ PR libstdc++/109883 ++ * testsuite/26_numerics/headers/cmath/constexpr_std_c++23.cc: New test. + -+!$acc exit data detach(var%chain) ++2023-05-17 Jakub Jelinek + -+!$acc exit data copyout(var, var2) ++ Backported from master: ++ 2023-05-17 Jakub Jelinek + -+if (var%value.ne.5) stop 1 -+if (var2%value.ne.7) stop 2 ++ PR libstdc++/109883 ++ * include/c_global/cmath (atan2, fmod, pow): Move ++ __gnu_cxx::__promote_2 using templates after _Float{16,32,64,128} and ++ __gnu_cxx::__bfloat16_t overloads. ++ (copysign, fdim, fmax, fmin, hypot, nextafter, remainder, remquo): ++ Likewise. ++ (fma): Move __gnu_cxx::__promote_3 using template after ++ _Float{16,32,64,128} and __gnu_cxx::__bfloat16_t overloads. + -+end ---- a/src/libstdc++-v3/ChangeLog -+++ b/src/libstdc++-v3/ChangeLog -@@ -1,3 +1,235 @@ +2023-05-11 Jonathan Wakely + + Backported from master: @@ -238059,6 +326679,28 @@ * GCC 13.1.0 released. --- a/src/libstdc++-v3/acinclude.m4 +++ b/src/libstdc++-v3/acinclude.m4 +@@ -1620,7 +1620,7 @@ AC_DEFUN([GLIBCXX_CHECK_C99_TR1], [ + AC_LANG_SAVE + AC_LANG_CPLUSPLUS + +- # Use -std=c++98 because the default (-std=gnu++98) leaves __STRICT_ANSI__ ++ # Use -std=c++98 because -std=gnu++98 leaves __STRICT_ANSI__ + # undefined and fake C99 facilities may be spuriously enabled. + ac_save_CXXFLAGS="$CXXFLAGS" + CXXFLAGS="$CXXFLAGS -std=c++98" +@@ -1885,9 +1885,9 @@ AC_DEFUN([GLIBCXX_CHECK_C99_TR1], [ + lround(0.0); + lroundf(0.0f); + lroundl(0.0l); +- nan(0); +- nanf(0); +- nanl(0); ++ nan(""); ++ nanf(""); ++ nanl(""); + nearbyint(0.0); + nearbyintf(0.0f); + nearbyintl(0.0l); @@ -3841,7 +3841,7 @@ changequote([,])dnl fi @@ -238068,6 +326710,73 @@ # Everything parsed; figure out what files and settings to use. case $enable_symvers in +@@ -5201,12 +5201,15 @@ AC_DEFUN([GLIBCXX_ZONEINFO_DIR], [ + zoneinfo_dir=none + ;; + esac +- case "$host" in +- avr-*-* | msp430-*-* ) embed_zoneinfo=no ;; +- *) +- # Also embed a copy of the tzdata.zi file as a static string. +- embed_zoneinfo=yes ;; +- esac ++ ++ AC_COMPUTE_INT(glibcxx_cv_at_least_32bit, [__INTPTR_WIDTH__ >= 32]) ++ if test "$glibcxx_cv_at_least_32bit" -ne 0; then ++ # Also embed a copy of the tzdata.zi file as a static string. ++ embed_zoneinfo=yes ++ else ++ # The embedded data is too large for 16-bit targets. ++ embed_zoneinfo=no ++ fi + elif test "x${with_libstdcxx_zoneinfo}" = xno; then + # Disable tzdb support completely. + zoneinfo_dir=none +@@ -5246,6 +5249,31 @@ AC_DEFUN([GLIBCXX_ZONEINFO_DIR], [ + fi + ]) + ++dnl ++dnl Check whether lock tables can be aligned to avoid false sharing. ++dnl ++dnl Defines: ++dnl _GLIBCXX_CAN_ALIGNAS_DESTRUCTIVE_SIZE if objects with static storage ++dnl duration can be aligned to std::hardware_destructive_interference_size. ++dnl ++AC_DEFUN([GLIBCXX_CHECK_ALIGNAS_CACHELINE], [ ++ AC_LANG_SAVE ++ AC_LANG_CPLUSPLUS ++ ++ AC_MSG_CHECKING([whether static objects can be aligned to the cacheline size]) ++ AC_TRY_COMPILE(, [struct alignas(__GCC_DESTRUCTIVE_SIZE) Aligned { }; ++ alignas(Aligned) static char buf[sizeof(Aligned) * 16]; ++ ], [ac_alignas_cacheline=yes], [ac_alignas_cacheline=no]) ++ if test "$ac_alignas_cacheline" = yes; then ++ AC_DEFINE_UNQUOTED(_GLIBCXX_CAN_ALIGNAS_DESTRUCTIVE_SIZE, 1, ++ [Define if global objects can be aligned to ++ std::hardware_destructive_interference_size.]) ++ fi ++ AC_MSG_RESULT($ac_alignas_cacheline) ++ ++ AC_LANG_RESTORE ++]) ++ + # Macros from the top-level gcc directory. + m4_include([../config/gc++filt.m4]) + m4_include([../config/tls.m4]) +--- a/src/libstdc++-v3/config.h.in ++++ b/src/libstdc++-v3/config.h.in +@@ -819,6 +819,10 @@ + /* Define if the compiler supports C++11 atomics. */ + #undef _GLIBCXX_ATOMIC_BUILTINS + ++/* Define if global objects can be aligned to ++ std::hardware_destructive_interference_size. */ ++#undef _GLIBCXX_CAN_ALIGNAS_DESTRUCTIVE_SIZE ++ + /* Define to use concept checking code from the boost libraries. */ + #undef _GLIBCXX_CONCEPT_CHECKS + --- a/src/libstdc++-v3/config/abi/post/aarch64-linux-gnu/baseline_symbols.txt +++ b/src/libstdc++-v3/config/abi/post/aarch64-linux-gnu/baseline_symbols.txt @@ -4232,6 +4232,7 @@ FUNC:_ZSt21__glibcxx_assert_failPKciS0_S0_@@GLIBCXX_3.4.30 @@ -245475,6 +334184,28 @@ --- a/src/libstdc++-v3/configure +++ b/src/libstdc++-v3/configure +@@ -19731,7 +19731,7 @@ ac_link='$CXX -o conftest$ac_exeext $CXXFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ex + ac_compiler_gnu=$ac_cv_cxx_compiler_gnu + + +- # Use -std=c++98 because the default (-std=gnu++98) leaves __STRICT_ANSI__ ++ # Use -std=c++98 because -std=gnu++98 leaves __STRICT_ANSI__ + # undefined and fake C99 facilities may be spuriously enabled. + ac_save_CXXFLAGS="$CXXFLAGS" + CXXFLAGS="$CXXFLAGS -std=c++98" +@@ -20106,9 +20106,9 @@ typedef double_t my_double_t; + lround(0.0); + lroundf(0.0f); + lroundl(0.0l); +- nan(0); +- nanf(0); +- nanl(0); ++ nan(""); ++ nanf(""); ++ nanl(""); + nearbyint(0.0); + nearbyintf(0.0f); + nearbyintl(0.0l); @@ -68652,7 +68652,7 @@ $as_echo "$as_me: WARNING: === Symbol versioning will be disabled." >&2;} fi @@ -245484,6 +334215,99 @@ # Everything parsed; figure out what files and settings to use. case $enable_symvers in +@@ -71557,12 +71557,18 @@ fi + zoneinfo_dir=none + ;; + esac +- case "$host" in +- avr-*-* | msp430-*-* ) embed_zoneinfo=no ;; +- *) +- # Also embed a copy of the tzdata.zi file as a static string. +- embed_zoneinfo=yes ;; +- esac ++ ++ if ac_fn_c_compute_int "$LINENO" "__INTPTR_WIDTH__ >= 32" "glibcxx_cv_at_least_32bit" ""; then : ++ ++fi ++ ++ if test "$glibcxx_cv_at_least_32bit" -ne 0; then ++ # Also embed a copy of the tzdata.zi file as a static string. ++ embed_zoneinfo=yes ++ else ++ # The embedded data is too large for 16-bit targets. ++ embed_zoneinfo=no ++ fi + elif test "x${with_libstdcxx_zoneinfo}" = xno; then + # Disable tzdb support completely. + zoneinfo_dir=none +@@ -71611,6 +71617,55 @@ _ACEOF + fi + + ++# For src/c++11/shared_ptr.cc alignment. ++ ++ ++ ac_ext=cpp ++ac_cpp='$CXXCPP $CPPFLAGS' ++ac_compile='$CXX -c $CXXFLAGS $CPPFLAGS conftest.$ac_ext >&5' ++ac_link='$CXX -o conftest$ac_exeext $CXXFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' ++ac_compiler_gnu=$ac_cv_cxx_compiler_gnu ++ ++ ++ { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether static objects can be aligned to the cacheline size" >&5 ++$as_echo_n "checking whether static objects can be aligned to the cacheline size... " >&6; } ++ cat confdefs.h - <<_ACEOF >conftest.$ac_ext ++/* end confdefs.h. */ ++ ++int ++main () ++{ ++struct alignas(__GCC_DESTRUCTIVE_SIZE) Aligned { }; ++ alignas(Aligned) static char buf[sizeof(Aligned) * 16]; ++ ++ ; ++ return 0; ++} ++_ACEOF ++if ac_fn_cxx_try_compile "$LINENO"; then : ++ ac_alignas_cacheline=yes ++else ++ ac_alignas_cacheline=no ++fi ++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext ++ if test "$ac_alignas_cacheline" = yes; then ++ ++cat >>confdefs.h <<_ACEOF ++#define _GLIBCXX_CAN_ALIGNAS_DESTRUCTIVE_SIZE 1 ++_ACEOF ++ ++ fi ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_alignas_cacheline" >&5 ++$as_echo "$ac_alignas_cacheline" >&6; } ++ ++ ac_ext=c ++ac_cpp='$CPP $CPPFLAGS' ++ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' ++ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' ++ac_compiler_gnu=$ac_cv_c_compiler_gnu ++ ++ ++ + # Define documentation rules conditionally. + + # See if makeinfo has been installed and is modern enough +--- a/src/libstdc++-v3/configure.ac ++++ b/src/libstdc++-v3/configure.ac +@@ -538,6 +538,9 @@ GLIBCXX_EMERGENCY_EH_ALLOC + # For src/c++20/tzdb.cc defaults. + GLIBCXX_ZONEINFO_DIR + ++# For src/c++11/shared_ptr.cc alignment. ++GLIBCXX_CHECK_ALIGNAS_CACHELINE ++ + # Define documentation rules conditionally. + + # See if makeinfo has been installed and is modern enough --- a/src/libstdc++-v3/configure.host +++ b/src/libstdc++-v3/configure.host @@ -323,6 +323,9 @@ case "${host}" in @@ -245553,6 +334377,51 @@ __GXX_ABI_VERSION. This macro is defined as the version of the compiler v3 ABI, with g++ 3.0 being version 100. This macro will be automatically defined whenever g++ is used (the curious can +--- a/src/libstdc++-v3/doc/html/manual/api.html ++++ b/src/libstdc++-v3/doc/html/manual/api.html +@@ -370,6 +370,11 @@ Calling a std::bind result as volatile was deprecated + For the non-default --enable-symvers=gnu-versioned-namespace + configuration, the shared library SONAME has been changed to + libstdc++.so.8. ++

++ The extension allowing containers to be instantiated with an allocator ++ that doesn't match the container's value type is no longer allowed in ++ strict (-std=c++NN) modes, only in ++ -std=gnu++NN modes. +

11

+ The --enable-cheaders=c_std configuration + was deprecated. +--- a/src/libstdc++-v3/doc/html/manual/configure.html ++++ b/src/libstdc++-v3/doc/html/manual/configure.html +@@ -38,9 +38,14 @@ + 

+    --with-gxx-include-dir=/foo/H-x86-gcc-3-c-gxx-inc/include/4.4-20090404
--enable-cstdio

This is an abbreviated form of '--enable-cstdio=stdio' + (described next). +-

--enable-cstdio=OPTION

Select a target-specific I/O package. At the moment, the only +- choice is to use 'stdio', a generic "C" abstraction. +- The default is 'stdio'. This option can change the library ABI. ++

--enable-cstdio=OPTION

Select a target-specific I/O package. The choices are 'stdio' ++ which is a generic abstraction using POSIX file I/O APIs ++ (read, write, ++ lseek, etc.), and 'stdio_pure' which is similar ++ but only uses standard C file I/O APIs (fread, ++ fwrite, fseek, etc.). ++ The 'stdio_posix' choice is a synonym for 'stdio'. ++ The default is 'stdio'. This option can change the library ABI. +

--enable-clocale

This is an abbreviated form of '--enable-clocale=generic' + (described next). +

--enable-clocale=OPTION

Select a target-specific underlying locale package. The --- a/src/libstdc++-v3/doc/xml/manual/abi.xml +++ b/src/libstdc++-v3/doc/xml/manual/abi.xml @@ -203,6 +203,11 @@ compatible. @@ -245583,6 +334452,55 @@ +--- a/src/libstdc++-v3/doc/xml/manual/configure.xml ++++ b/src/libstdc++-v3/doc/xml/manual/configure.xml +@@ -74,9 +74,14 @@ + + + --enable-cstdio=OPTION +- Select a target-specific I/O package. At the moment, the only +- choice is to use 'stdio', a generic "C" abstraction. +- The default is 'stdio'. This option can change the library ABI. ++ Select a target-specific I/O package. The choices are 'stdio' ++ which is a generic abstraction using POSIX file I/O APIs ++ (read, write, ++ lseek, etc.), and 'stdio_pure' which is similar ++ but only uses standard C file I/O APIs (fread, ++ fwrite, fseek, etc.). ++ The 'stdio_posix' choice is a synonym for 'stdio'. ++ The default is 'stdio'. This option can change the library ABI. + + + +--- a/src/libstdc++-v3/doc/xml/manual/evolution.xml ++++ b/src/libstdc++-v3/doc/xml/manual/evolution.xml +@@ -915,6 +915,13 @@ Calling a std::bind result as volatile was deprecated for C++17. + libstdc++.so.8. + + ++ ++ The extension allowing containers to be instantiated with an allocator ++ that doesn't match the container's value type is no longer allowed in ++ strict () modes, only in ++ modes. ++ ++ + + +

<constant>9</constant> +@@ -998,6 +1005,12 @@ Calling a std::bind result as volatile was deprecated for C++17. + added. + + ++ ++ The extension allowing containers to be instantiated with an allocator ++ that doesn't match the container's value type is no longer allowed in ++ C++20 mode, even in non-strict mode. ++ ++ +
+ +
<constant>11</constant> --- a/src/libstdc++-v3/include/bits/basic_string.h +++ b/src/libstdc++-v3/include/bits/basic_string.h @@ -69,6 +69,8 @@ _GLIBCXX_BEGIN_NAMESPACE_CXX11 @@ -245905,6 +334823,18 @@ /// @} group numeric_arrays +--- a/src/libstdc++-v3/include/bits/locale_classes.tcc ++++ b/src/libstdc++-v3/include/bits/locale_classes.tcc +@@ -129,9 +129,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION + _GLIBCXX_STD_FACET(time_put); + _GLIBCXX_STD_FACET(messages); + #endif +-#ifdef _GLIBCXX_USE_CHAR8_T +- _GLIBCXX_STD_FACET(codecvt); +-#endif + #if __cplusplus >= 201103L + _GLIBCXX_STD_FACET(codecvt); + _GLIBCXX_STD_FACET(codecvt); --- a/src/libstdc++-v3/include/bits/mask_array.h +++ b/src/libstdc++-v3/include/bits/mask_array.h @@ -181,6 +181,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION @@ -246438,6 +335368,31 @@ /// @} group numeric_arrays +--- a/src/libstdc++-v3/include/bits/std_abs.h ++++ b/src/libstdc++-v3/include/bits/std_abs.h +@@ -135,11 +135,20 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION + __extension__ inline _GLIBCXX_CONSTEXPR + __float128 + abs(__float128 __x) +- { return __x < 0 ? -__x : __x; } ++ { ++#if defined(_GLIBCXX_LDOUBLE_IS_IEEE_BINARY128) ++ return __builtin_fabsl(__x); ++#elif defined(_GLIBCXX_HAVE_FLOAT128_MATH) ++ return __builtin_fabsf128(__x); ++#else ++ // Assume that __builtin_signbit works for __float128. ++ return __builtin_signbit(__x) ? -__x : __x; ++#endif ++ } + #endif + + _GLIBCXX_END_NAMESPACE_VERSION + } // namespace +-} // extern "C"++" ++} // extern "C++" + + #endif // _GLIBCXX_BITS_STD_ABS_H --- a/src/libstdc++-v3/include/bits/stl_bvector.h +++ b/src/libstdc++-v3/include/bits/stl_bvector.h @@ -684,6 +684,8 @@ _GLIBCXX_BEGIN_NAMESPACE_CONTAINER @@ -246598,6 +335553,2371 @@ #ifndef _USES_ALLOCATOR_H #define _USES_ALLOCATOR_H 1 +--- a/src/libstdc++-v3/include/c_global/cmath ++++ b/src/libstdc++-v3/include/c_global/cmath +@@ -151,15 +151,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION + { return __builtin_atan2l(__y, __x); } + #endif + +- template +- inline _GLIBCXX_CONSTEXPR +- typename __gnu_cxx::__promote_2<_Tp, _Up>::__type +- atan2(_Tp __y, _Up __x) +- { +- typedef typename __gnu_cxx::__promote_2<_Tp, _Up>::__type __type; +- return atan2(__type(__y), __type(__x)); +- } +- + using ::ceil; + + #ifndef __CORRECT_ISO_CPP_MATH_H_PROTO +@@ -286,15 +277,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION + { return __builtin_fmodl(__x, __y); } + #endif + +- template +- inline _GLIBCXX_CONSTEXPR +- typename __gnu_cxx::__promote_2<_Tp, _Up>::__type +- fmod(_Tp __x, _Up __y) +- { +- typedef typename __gnu_cxx::__promote_2<_Tp, _Up>::__type __type; +- return fmod(__type(__x), __type(__y)); +- } +- + using ::frexp; + + #ifndef __CORRECT_ISO_CPP_MATH_H_PROTO +@@ -411,15 +393,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION + #endif + #endif + +- template +- inline _GLIBCXX_CONSTEXPR +- typename __gnu_cxx::__promote_2<_Tp, _Up>::__type +- pow(_Tp __x, _Up __y) +- { +- typedef typename __gnu_cxx::__promote_2<_Tp, _Up>::__type __type; +- return pow(__type(__x), __type(__y)); +- } +- + using ::sin; + + #ifndef __CORRECT_ISO_CPP_MATH_H_PROTO +@@ -1073,6 +1046,33 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION + { return __gnu_cxx::__bfloat16_t(__builtin_tanhf(__x)); } + #endif + ++ template ++ inline _GLIBCXX_CONSTEXPR ++ typename __gnu_cxx::__promote_2<_Tp, _Up>::__type ++ atan2(_Tp __y, _Up __x) ++ { ++ typedef typename __gnu_cxx::__promote_2<_Tp, _Up>::__type __type; ++ return atan2(__type(__y), __type(__x)); ++ } ++ ++ template ++ inline _GLIBCXX_CONSTEXPR ++ typename __gnu_cxx::__promote_2<_Tp, _Up>::__type ++ fmod(_Tp __x, _Up __y) ++ { ++ typedef typename __gnu_cxx::__promote_2<_Tp, _Up>::__type __type; ++ return fmod(__type(__x), __type(__y)); ++ } ++ ++ template ++ inline _GLIBCXX_CONSTEXPR ++ typename __gnu_cxx::__promote_2<_Tp, _Up>::__type ++ pow(_Tp __x, _Up __y) ++ { ++ typedef typename __gnu_cxx::__promote_2<_Tp, _Up>::__type __type; ++ return pow(__type(__x), __type(__y)); ++ } ++ + #if _GLIBCXX_USE_C99_MATH + #if !_GLIBCXX_USE_C99_FP_MACROS_DYNAMIC + +@@ -2107,16 +2107,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION + { return __builtin_copysignl(__x, __y); } + #endif + +-#ifndef __CORRECT_ISO_CPP11_MATH_H_PROTO_INT +- template +- constexpr typename __gnu_cxx::__promote_2<_Tp, _Up>::__type +- copysign(_Tp __x, _Up __y) +- { +- typedef typename __gnu_cxx::__promote_2<_Tp, _Up>::__type __type; +- return copysign(__type(__x), __type(__y)); +- } +-#endif +- + #ifndef __CORRECT_ISO_CPP11_MATH_H_PROTO_FP + constexpr float + erf(float __x) +@@ -2199,16 +2189,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION + { return __builtin_fdiml(__x, __y); } + #endif + +-#ifndef __CORRECT_ISO_CPP11_MATH_H_PROTO_INT +- template +- constexpr typename __gnu_cxx::__promote_2<_Tp, _Up>::__type +- fdim(_Tp __x, _Up __y) +- { +- typedef typename __gnu_cxx::__promote_2<_Tp, _Up>::__type __type; +- return fdim(__type(__x), __type(__y)); +- } +-#endif +- + #ifndef __CORRECT_ISO_CPP11_MATH_H_PROTO_FP + constexpr float + fma(float __x, float __y, float __z) +@@ -2219,16 +2199,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION + { return __builtin_fmal(__x, __y, __z); } + #endif + +-#ifndef __CORRECT_ISO_CPP11_MATH_H_PROTO_INT +- template +- constexpr typename __gnu_cxx::__promote_3<_Tp, _Up, _Vp>::__type +- fma(_Tp __x, _Up __y, _Vp __z) +- { +- typedef typename __gnu_cxx::__promote_3<_Tp, _Up, _Vp>::__type __type; +- return fma(__type(__x), __type(__y), __type(__z)); +- } +-#endif +- + #ifndef __CORRECT_ISO_CPP11_MATH_H_PROTO_FP + constexpr float + fmax(float __x, float __y) +@@ -2239,16 +2209,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION + { return __builtin_fmaxl(__x, __y); } + #endif + +-#ifndef __CORRECT_ISO_CPP11_MATH_H_PROTO_INT +- template +- constexpr typename __gnu_cxx::__promote_2<_Tp, _Up>::__type +- fmax(_Tp __x, _Up __y) +- { +- typedef typename __gnu_cxx::__promote_2<_Tp, _Up>::__type __type; +- return fmax(__type(__x), __type(__y)); +- } +-#endif +- + #ifndef __CORRECT_ISO_CPP11_MATH_H_PROTO_FP + constexpr float + fmin(float __x, float __y) +@@ -2259,16 +2219,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION + { return __builtin_fminl(__x, __y); } + #endif + +-#ifndef __CORRECT_ISO_CPP11_MATH_H_PROTO_INT +- template +- constexpr typename __gnu_cxx::__promote_2<_Tp, _Up>::__type +- fmin(_Tp __x, _Up __y) +- { +- typedef typename __gnu_cxx::__promote_2<_Tp, _Up>::__type __type; +- return fmin(__type(__x), __type(__y)); +- } +-#endif +- + #ifndef __CORRECT_ISO_CPP11_MATH_H_PROTO_FP + constexpr float + hypot(float __x, float __y) +@@ -2279,16 +2229,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION + { return __builtin_hypotl(__x, __y); } + #endif + +-#ifndef __CORRECT_ISO_CPP11_MATH_H_PROTO_INT +- template +- constexpr typename __gnu_cxx::__promote_2<_Tp, _Up>::__type +- hypot(_Tp __x, _Up __y) +- { +- typedef typename __gnu_cxx::__promote_2<_Tp, _Up>::__type __type; +- return hypot(__type(__x), __type(__y)); +- } +-#endif +- + #ifndef __CORRECT_ISO_CPP11_MATH_H_PROTO_FP + constexpr int + ilogb(float __x) +@@ -2481,16 +2421,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION + { return __builtin_nextafterl(__x, __y); } + #endif + +-#ifndef __CORRECT_ISO_CPP11_MATH_H_PROTO_INT +- template +- constexpr typename __gnu_cxx::__promote_2<_Tp, _Up>::__type +- nextafter(_Tp __x, _Up __y) +- { +- typedef typename __gnu_cxx::__promote_2<_Tp, _Up>::__type __type; +- return nextafter(__type(__x), __type(__y)); +- } +-#endif +- + #ifndef __CORRECT_ISO_CPP11_MATH_H_PROTO_FP + constexpr float + nexttoward(float __x, long double __y) +@@ -2519,16 +2449,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION + { return __builtin_remainderl(__x, __y); } + #endif + +-#ifndef __CORRECT_ISO_CPP11_MATH_H_PROTO_INT +- template +- constexpr typename __gnu_cxx::__promote_2<_Tp, _Up>::__type +- remainder(_Tp __x, _Up __y) +- { +- typedef typename __gnu_cxx::__promote_2<_Tp, _Up>::__type __type; +- return remainder(__type(__x), __type(__y)); +- } +-#endif +- + #ifndef __CORRECT_ISO_CPP11_MATH_H_PROTO_FP + inline float + remquo(float __x, float __y, int* __pquo) +@@ -2539,16 +2459,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION + { return __builtin_remquol(__x, __y, __pquo); } + #endif + +-#ifndef __CORRECT_ISO_CPP11_MATH_H_PROTO_INT +- template +- inline typename __gnu_cxx::__promote_2<_Tp, _Up>::__type +- remquo(_Tp __x, _Up __y, int* __pquo) +- { +- typedef typename __gnu_cxx::__promote_2<_Tp, _Up>::__type __type; +- return remquo(__type(__x), __type(__y), __pquo); +- } +-#endif +- + #ifndef __CORRECT_ISO_CPP11_MATH_H_PROTO_FP + constexpr float + rint(float __x) +@@ -3555,6 +3465,79 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION + { return __gnu_cxx::__bfloat16_t(__builtin_truncf(__x)); } + #endif + ++#ifndef __CORRECT_ISO_CPP11_MATH_H_PROTO_INT ++ template ++ constexpr typename __gnu_cxx::__promote_2<_Tp, _Up>::__type ++ copysign(_Tp __x, _Up __y) ++ { ++ typedef typename __gnu_cxx::__promote_2<_Tp, _Up>::__type __type; ++ return copysign(__type(__x), __type(__y)); ++ } ++ ++ template ++ constexpr typename __gnu_cxx::__promote_2<_Tp, _Up>::__type ++ fdim(_Tp __x, _Up __y) ++ { ++ typedef typename __gnu_cxx::__promote_2<_Tp, _Up>::__type __type; ++ return fdim(__type(__x), __type(__y)); ++ } ++ ++ template ++ constexpr typename __gnu_cxx::__promote_2<_Tp, _Up>::__type ++ fmax(_Tp __x, _Up __y) ++ { ++ typedef typename __gnu_cxx::__promote_2<_Tp, _Up>::__type __type; ++ return fmax(__type(__x), __type(__y)); ++ } ++ ++ template ++ constexpr typename __gnu_cxx::__promote_2<_Tp, _Up>::__type ++ fmin(_Tp __x, _Up __y) ++ { ++ typedef typename __gnu_cxx::__promote_2<_Tp, _Up>::__type __type; ++ return fmin(__type(__x), __type(__y)); ++ } ++ ++ template ++ constexpr typename __gnu_cxx::__promote_2<_Tp, _Up>::__type ++ hypot(_Tp __x, _Up __y) ++ { ++ typedef typename __gnu_cxx::__promote_2<_Tp, _Up>::__type __type; ++ return hypot(__type(__x), __type(__y)); ++ } ++ ++ template ++ constexpr typename __gnu_cxx::__promote_2<_Tp, _Up>::__type ++ nextafter(_Tp __x, _Up __y) ++ { ++ typedef typename __gnu_cxx::__promote_2<_Tp, _Up>::__type __type; ++ return nextafter(__type(__x), __type(__y)); ++ } ++ ++ template ++ constexpr typename __gnu_cxx::__promote_2<_Tp, _Up>::__type ++ remainder(_Tp __x, _Up __y) ++ { ++ typedef typename __gnu_cxx::__promote_2<_Tp, _Up>::__type __type; ++ return remainder(__type(__x), __type(__y)); ++ } ++ ++ template ++ inline typename __gnu_cxx::__promote_2<_Tp, _Up>::__type ++ remquo(_Tp __x, _Up __y, int* __pquo) ++ { ++ typedef typename __gnu_cxx::__promote_2<_Tp, _Up>::__type __type; ++ return remquo(__type(__x), __type(__y), __pquo); ++ } ++ ++ template ++ constexpr typename __gnu_cxx::__promote_3<_Tp, _Up, _Vp>::__type ++ fma(_Tp __x, _Up __y, _Vp __z) ++ { ++ typedef typename __gnu_cxx::__promote_3<_Tp, _Up, _Vp>::__type __type; ++ return fma(__type(__x), __type(__y), __type(__z)); ++ } ++#endif + + #endif // _GLIBCXX_USE_C99_MATH_TR1 + #endif // C++11 +--- a/src/libstdc++-v3/include/experimental/bits/simd.h ++++ b/src/libstdc++-v3/include/experimental/bits/simd.h +@@ -2369,15 +2369,21 @@ template <> + struct __intrinsic_type + { using type = float32x4_t; }; + +-#if _GLIBCXX_SIMD_HAVE_NEON_A64 + template <> + struct __intrinsic_type +- { using type = float64x1_t; }; ++ { ++#if _GLIBCXX_SIMD_HAVE_NEON_A64 ++ using type = float64x1_t; ++#endif ++ }; + + template <> + struct __intrinsic_type +- { using type = float64x2_t; }; ++ { ++#if _GLIBCXX_SIMD_HAVE_NEON_A64 ++ using type = float64x2_t; + #endif ++ }; + + #define _GLIBCXX_SIMD_ARM_INTRIN(_Bits, _Np) \ + template <> \ +@@ -2460,11 +2466,40 @@ template + "no __intrinsic_type support for 64-bit floating point on PowerPC w/o VSX"); + #endif + +- using type = +- typename __intrinsic_type_impl< +- conditional_t, +- conditional_t<_S_is_ldouble, double, _Tp>, +- __int_for_sizeof_t<_Tp>>>::type; ++ static constexpr auto __element_type() ++ { ++ if constexpr (is_floating_point_v<_Tp>) ++ { ++ if constexpr (_S_is_ldouble) ++ return double {}; ++ else ++ return _Tp {}; ++ } ++ else if constexpr (is_signed_v<_Tp>) ++ { ++ if constexpr (sizeof(_Tp) == sizeof(_SChar)) ++ return _SChar {}; ++ else if constexpr (sizeof(_Tp) == sizeof(short)) ++ return short {}; ++ else if constexpr (sizeof(_Tp) == sizeof(int)) ++ return int {}; ++ else if constexpr (sizeof(_Tp) == sizeof(_LLong)) ++ return _LLong {}; ++ } ++ else ++ { ++ if constexpr (sizeof(_Tp) == sizeof(_UChar)) ++ return _UChar {}; ++ else if constexpr (sizeof(_Tp) == sizeof(_UShort)) ++ return _UShort {}; ++ else if constexpr (sizeof(_Tp) == sizeof(_UInt)) ++ return _UInt {}; ++ else if constexpr (sizeof(_Tp) == sizeof(_ULLong)) ++ return _ULLong {}; ++ } ++ } ++ ++ using type = typename __intrinsic_type_impl::type; + }; + #endif // __ALTIVEC__ + +@@ -2675,7 +2710,14 @@ template + + _GLIBCXX_SIMD_INTRINSIC constexpr void + _M_set(size_t __i, _Tp __x) +- { _M_data[__i] = __x; } ++ { ++ if (__builtin_is_constant_evaluated()) ++ _M_data = __generate_from_n_evaluations<_Width, _BuiltinType>([&](auto __j) { ++ return __j == __i ? __x : _M_data[__j()]; ++ }); ++ else ++ _M_data[__i] = __x; ++ } + + _GLIBCXX_SIMD_INTRINSIC + constexpr bool +@@ -3186,6 +3228,10 @@ template + { + if constexpr (is_same_v) + return __x; ++ else if (__builtin_is_constant_evaluated()) ++ return _Tp([&](auto __i) constexpr { ++ return __i < simd_size_v<_Up, _Ap> ? __x[__i] : _Up(); ++ }); + else if constexpr (simd_size_v<_Up, _Ap> == 1) + { + _Tp __r{}; +@@ -3258,7 +3304,7 @@ template + return {__mem, vector_aligned}; + } + +-template ++template + _GLIBCXX_SIMD_INTRINSIC + enable_if_t<(_Np == native_simd_mask<_Tp>::size()), native_simd_mask<_Tp>> + to_native(const fixed_size_simd_mask<_Tp, _Np>& __x) +@@ -3269,7 +3315,7 @@ template + } + + // to_compatible {{{2 +-template ++template + _GLIBCXX_SIMD_INTRINSIC enable_if_t<(_Np == simd<_Tp>::size()), simd<_Tp>> + to_compatible(const simd<_Tp, simd_abi::fixed_size<_Np>>& __x) + { +@@ -3278,12 +3324,13 @@ template + return {__mem, vector_aligned}; + } + +-template ++template + _GLIBCXX_SIMD_INTRINSIC + enable_if_t<(_Np == simd_mask<_Tp>::size()), simd_mask<_Tp>> + to_compatible(const simd_mask<_Tp, simd_abi::fixed_size<_Np>>& __x) + { + return simd_mask<_Tp>( ++ __private_init, + [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { return __x[__i]; }); + } + +@@ -3321,10 +3368,11 @@ template + + const_where_expression& operator=(const const_where_expression&) = delete; + +- _GLIBCXX_SIMD_INTRINSIC const_where_expression(const _M& __kk, const _Tp& dd) +- : _M_k(__kk), _M_value(const_cast<_Tp&>(dd)) {} ++ _GLIBCXX_SIMD_INTRINSIC constexpr ++ const_where_expression(const _M& __kk, const _Tp& dd) ++ : _M_k(__kk), _M_value(const_cast<_Tp&>(dd)) {} + +- _GLIBCXX_SIMD_INTRINSIC _V ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR _V + operator-() const&& + { + return {__private_init, +@@ -3333,7 +3381,7 @@ template + } + + template +- [[nodiscard]] _GLIBCXX_SIMD_INTRINSIC _V ++ [[nodiscard]] _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR _V + copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _IsSimdFlagType<_Flags>) const&& + { + return {__private_init, +@@ -3342,7 +3390,7 @@ template + } + + template +- _GLIBCXX_SIMD_INTRINSIC void ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void + copy_to(_LoadStorePtr<_Up, value_type>* __mem, _IsSimdFlagType<_Flags>) const&& + { + _Impl::_S_masked_store(__data(_M_value), +@@ -3381,19 +3429,21 @@ template + const_where_expression(const const_where_expression&) = delete; + const_where_expression& operator=(const const_where_expression&) = delete; + +- _GLIBCXX_SIMD_INTRINSIC const_where_expression(const bool __kk, const _Tp& dd) +- : _M_k(__kk), _M_value(const_cast<_Tp&>(dd)) {} ++ _GLIBCXX_SIMD_INTRINSIC constexpr ++ const_where_expression(const bool __kk, const _Tp& dd) ++ : _M_k(__kk), _M_value(const_cast<_Tp&>(dd)) {} + +- _GLIBCXX_SIMD_INTRINSIC _V operator-() const&& ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR _V ++ operator-() const&& + { return _M_k ? -_M_value : _M_value; } + + template +- [[nodiscard]] _GLIBCXX_SIMD_INTRINSIC _V ++ [[nodiscard]] _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR _V + copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _IsSimdFlagType<_Flags>) const&& + { return _M_k ? static_cast<_V>(__mem[0]) : _M_value; } + + template +- _GLIBCXX_SIMD_INTRINSIC void ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void + copy_to(_LoadStorePtr<_Up, value_type>* __mem, _IsSimdFlagType<_Flags>) const&& + { + if (_M_k) +@@ -3419,18 +3469,21 @@ template + is_same::value, ""); + static_assert(_M::size() == _Tp::size(), ""); + +- _GLIBCXX_SIMD_INTRINSIC friend _Tp& __get_lvalue(where_expression& __x) ++ _GLIBCXX_SIMD_INTRINSIC friend constexpr _Tp& ++ __get_lvalue(where_expression& __x) + { return __x._M_value; } + + public: + where_expression(const where_expression&) = delete; + where_expression& operator=(const where_expression&) = delete; + +- _GLIBCXX_SIMD_INTRINSIC where_expression(const _M& __kk, _Tp& dd) +- : const_where_expression<_M, _Tp>(__kk, dd) {} ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR ++ where_expression(const _M& __kk, _Tp& dd) ++ : const_where_expression<_M, _Tp>(__kk, dd) {} + + template +- _GLIBCXX_SIMD_INTRINSIC void operator=(_Up&& __x) && ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void ++ operator=(_Up&& __x) && + { + _Impl::_S_masked_assign(__data(_M_k), __data(_M_value), + __to_value_type_or_member_type<_Tp>( +@@ -3439,7 +3492,8 @@ template + + #define _GLIBCXX_SIMD_OP_(__op, __name) \ + template \ +- _GLIBCXX_SIMD_INTRINSIC void operator __op##=(_Up&& __x)&& \ ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void \ ++ operator __op##=(_Up&& __x)&& \ + { \ + _Impl::template _S_masked_cassign( \ + __data(_M_k), __data(_M_value), \ +@@ -3461,28 +3515,28 @@ template + _GLIBCXX_SIMD_OP_(>>, _S_shift_right); + #undef _GLIBCXX_SIMD_OP_ + +- _GLIBCXX_SIMD_INTRINSIC void ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void + operator++() && + { + __data(_M_value) + = _Impl::template _S_masked_unary<__increment>(__data(_M_k), __data(_M_value)); + } + +- _GLIBCXX_SIMD_INTRINSIC void ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void + operator++(int) && + { + __data(_M_value) + = _Impl::template _S_masked_unary<__increment>(__data(_M_k), __data(_M_value)); + } + +- _GLIBCXX_SIMD_INTRINSIC void ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void + operator--() && + { + __data(_M_value) + = _Impl::template _S_masked_unary<__decrement>(__data(_M_k), __data(_M_value)); + } + +- _GLIBCXX_SIMD_INTRINSIC void ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void + operator--(int) && + { + __data(_M_value) +@@ -3491,7 +3545,7 @@ template + + // intentionally hides const_where_expression::copy_from + template +- _GLIBCXX_SIMD_INTRINSIC void ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void + copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _IsSimdFlagType<_Flags>) && + { + __data(_M_value) = _Impl::_S_masked_load(__data(_M_value), __data(_M_k), +@@ -3513,13 +3567,13 @@ template + where_expression(const where_expression&) = delete; + where_expression& operator=(const where_expression&) = delete; + +- _GLIBCXX_SIMD_INTRINSIC ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR + where_expression(const _M& __kk, _Tp& dd) + : const_where_expression<_M, _Tp>(__kk, dd) {} + + #define _GLIBCXX_SIMD_OP_(__op) \ + template \ +- _GLIBCXX_SIMD_INTRINSIC void \ ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void \ + operator __op(_Up&& __x)&& \ + { if (_M_k) _M_value __op static_cast<_Up&&>(__x); } + +@@ -3536,68 +3590,71 @@ template + _GLIBCXX_SIMD_OP_(>>=) + #undef _GLIBCXX_SIMD_OP_ + +- _GLIBCXX_SIMD_INTRINSIC void ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void + operator++() && + { if (_M_k) ++_M_value; } + +- _GLIBCXX_SIMD_INTRINSIC void ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void + operator++(int) && + { if (_M_k) ++_M_value; } + +- _GLIBCXX_SIMD_INTRINSIC void ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void + operator--() && + { if (_M_k) --_M_value; } + +- _GLIBCXX_SIMD_INTRINSIC void ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void + operator--(int) && + { if (_M_k) --_M_value; } + + // intentionally hides const_where_expression::copy_from + template +- _GLIBCXX_SIMD_INTRINSIC void ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void + copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _IsSimdFlagType<_Flags>) && + { if (_M_k) _M_value = __mem[0]; } + }; + + // where {{{1 + template +- _GLIBCXX_SIMD_INTRINSIC where_expression, simd<_Tp, _Ap>> ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR ++ where_expression, simd<_Tp, _Ap>> + where(const typename simd<_Tp, _Ap>::mask_type& __k, simd<_Tp, _Ap>& __value) + { return {__k, __value}; } + + template +- _GLIBCXX_SIMD_INTRINSIC ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR + const_where_expression, simd<_Tp, _Ap>> + where(const typename simd<_Tp, _Ap>::mask_type& __k, const simd<_Tp, _Ap>& __value) + { return {__k, __value}; } + + template +- _GLIBCXX_SIMD_INTRINSIC ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR + where_expression, simd_mask<_Tp, _Ap>> + where(const remove_const_t>& __k, simd_mask<_Tp, _Ap>& __value) + { return {__k, __value}; } + + template +- _GLIBCXX_SIMD_INTRINSIC ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR + const_where_expression, simd_mask<_Tp, _Ap>> + where(const remove_const_t>& __k, const simd_mask<_Tp, _Ap>& __value) + { return {__k, __value}; } + + template +- _GLIBCXX_SIMD_INTRINSIC where_expression ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR where_expression + where(_ExactBool __k, _Tp& __value) + { return {__k, __value}; } + + template +- _GLIBCXX_SIMD_INTRINSIC const_where_expression ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR const_where_expression + where(_ExactBool __k, const _Tp& __value) + { return {__k, __value}; } + + template +- void where(bool __k, simd<_Tp, _Ap>& __value) = delete; ++ _GLIBCXX_SIMD_CONSTEXPR void ++ where(bool __k, simd<_Tp, _Ap>& __value) = delete; + + template +- void where(bool __k, const simd<_Tp, _Ap>& __value) = delete; ++ _GLIBCXX_SIMD_CONSTEXPR void ++ where(bool __k, const simd<_Tp, _Ap>& __value) = delete; + + // proposed mask iterations {{{1 + namespace __proposed { +@@ -3820,12 +3877,12 @@ template +- _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_CONST ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_CONST constexpr + _SimdWrapper<_Tp, _Np / _Total * _Combine> + __extract_part(const _SimdWrapper<_Tp, _Np> __x); + + template +- _GLIBCXX_SIMD_INTRINSIC auto ++ _GLIBCXX_SIMD_INTRINSIC constexpr auto + __extract_part(const _SimdTuple<_Tp, _A0, _As...>& __x); + + // }}} +@@ -4551,7 +4608,7 @@ template + + // }}} + // access to internal representation (optional feature) {{{ +- _GLIBCXX_SIMD_ALWAYS_INLINE explicit ++ _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR explicit + simd_mask(typename _Traits::_MaskCastType __init) + : _M_data{__init} {} + // conversions to internal type is done in _MaskBase +@@ -4562,11 +4619,11 @@ template + // Conversion of simd_mask to and from bitset makes it much easier to + // interface with other facilities. I suggest adding `static + // simd_mask::from_bitset` and `simd_mask::to_bitset`. +- _GLIBCXX_SIMD_ALWAYS_INLINE static simd_mask ++ _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR static simd_mask + __from_bitset(bitset bs) + { return {__bitset_init, bs}; } + +- _GLIBCXX_SIMD_ALWAYS_INLINE bitset ++ _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR bitset + __to_bitset() const + { return _Impl::_S_to_bits(_M_data)._M_to_bitset(); } + +@@ -4591,7 +4648,7 @@ template + template >, + is_same<_Up, _Up>>::value>> +- _GLIBCXX_SIMD_ALWAYS_INLINE ++ _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR + simd_mask(const simd_mask<_Up, simd_abi::fixed_size>& __x) + : _M_data(_Impl::_S_from_bitmask(__data(__x), _S_type_tag)) {} + #endif +@@ -4599,12 +4656,12 @@ template + // }}} + // load constructor {{{ + template +- _GLIBCXX_SIMD_ALWAYS_INLINE ++ _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR + simd_mask(const value_type* __mem, _IsSimdFlagType<_Flags>) + : _M_data(_Impl::template _S_load<_Ip>(_Flags::template _S_apply(__mem))) {} + + template +- _GLIBCXX_SIMD_ALWAYS_INLINE ++ _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR + simd_mask(const value_type* __mem, simd_mask __k, _IsSimdFlagType<_Flags>) + : _M_data{} + { +@@ -4615,20 +4672,20 @@ template + // }}} + // loads [simd_mask.load] {{{ + template +- _GLIBCXX_SIMD_ALWAYS_INLINE void ++ _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR void + copy_from(const value_type* __mem, _IsSimdFlagType<_Flags>) + { _M_data = _Impl::template _S_load<_Ip>(_Flags::template _S_apply(__mem)); } + + // }}} + // stores [simd_mask.store] {{{ + template +- _GLIBCXX_SIMD_ALWAYS_INLINE void ++ _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR void + copy_to(value_type* __mem, _IsSimdFlagType<_Flags>) const + { _Impl::_S_store(_M_data, _Flags::template _S_apply(__mem)); } + + // }}} + // scalar access {{{ +- _GLIBCXX_SIMD_ALWAYS_INLINE reference ++ _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR reference + operator[](size_t __i) + { + if (__i >= size()) +@@ -4636,7 +4693,7 @@ template + return {_M_data, int(__i)}; + } + +- _GLIBCXX_SIMD_ALWAYS_INLINE value_type ++ _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR value_type + operator[](size_t __i) const + { + if (__i >= size()) +@@ -4649,7 +4706,7 @@ template + + // }}} + // negation {{{ +- _GLIBCXX_SIMD_ALWAYS_INLINE simd_mask ++ _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR simd_mask + operator!() const + { return {__private_init, _Impl::_S_bit_not(_M_data)}; } + +@@ -4659,7 +4716,7 @@ template + // simd_mask && simd_mask needs disambiguation + template , simd_mask>>> +- _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask ++ _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR friend simd_mask + operator&&(const simd_mask& __x, const simd_mask<_Up, _A2>& __y) + { + return {__private_init, +@@ -4668,7 +4725,7 @@ template + + template , simd_mask>>> +- _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask ++ _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR friend simd_mask + operator||(const simd_mask& __x, const simd_mask<_Up, _A2>& __y) + { + return {__private_init, +@@ -4676,41 +4733,41 @@ template + } + #endif // _GLIBCXX_SIMD_ENABLE_IMPLICIT_MASK_CAST + +- _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask ++ _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR friend simd_mask + operator&&(const simd_mask& __x, const simd_mask& __y) + { return {__private_init, _Impl::_S_logical_and(__x._M_data, __y._M_data)}; } + +- _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask ++ _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR friend simd_mask + operator||(const simd_mask& __x, const simd_mask& __y) + { return {__private_init, _Impl::_S_logical_or(__x._M_data, __y._M_data)}; } + +- _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask ++ _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR friend simd_mask + operator&(const simd_mask& __x, const simd_mask& __y) + { return {__private_init, _Impl::_S_bit_and(__x._M_data, __y._M_data)}; } + +- _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask ++ _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR friend simd_mask + operator|(const simd_mask& __x, const simd_mask& __y) + { return {__private_init, _Impl::_S_bit_or(__x._M_data, __y._M_data)}; } + +- _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask ++ _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR friend simd_mask + operator^(const simd_mask& __x, const simd_mask& __y) + { return {__private_init, _Impl::_S_bit_xor(__x._M_data, __y._M_data)}; } + +- _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask& ++ _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR friend simd_mask& + operator&=(simd_mask& __x, const simd_mask& __y) + { + __x._M_data = _Impl::_S_bit_and(__x._M_data, __y._M_data); + return __x; + } + +- _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask& ++ _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR friend simd_mask& + operator|=(simd_mask& __x, const simd_mask& __y) + { + __x._M_data = _Impl::_S_bit_or(__x._M_data, __y._M_data); + return __x; + } + +- _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask& ++ _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR friend simd_mask& + operator^=(simd_mask& __x, const simd_mask& __y) + { + __x._M_data = _Impl::_S_bit_xor(__x._M_data, __y._M_data); +@@ -4747,7 +4804,8 @@ template + + // }}} + // bitset_init ctor {{{ +- _GLIBCXX_SIMD_INTRINSIC simd_mask(_BitsetInit, bitset __init) ++ _GLIBCXX_SIMD_INTRINSIC constexpr ++ simd_mask(_BitsetInit, bitset __init) + : _M_data(_Impl::_S_from_bitmask(_SanitizedBitMask(__init), _S_type_tag)) + {} + +@@ -5015,7 +5073,8 @@ template + { + using _Impl = typename _SimdTraits<_Tp, _Abi>::_SimdImpl; + +- _GLIBCXX_SIMD_INTRINSIC const _V& __derived() const ++ _GLIBCXX_SIMD_INTRINSIC constexpr const _V& ++ __derived() const + { return *static_cast(this); } + + template +@@ -5235,7 +5294,7 @@ template + + // load constructor + template +- _GLIBCXX_SIMD_ALWAYS_INLINE ++ _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR + simd(const _Up* __mem, _IsSimdFlagType<_Flags>) + : _M_data( + _Impl::_S_load(_Flags::template _S_apply(__mem), _S_type_tag)) +@@ -5243,7 +5302,7 @@ template + + // loads [simd.load] + template +- _GLIBCXX_SIMD_ALWAYS_INLINE void ++ _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR void + copy_from(const _Vectorizable<_Up>* __mem, _IsSimdFlagType<_Flags>) + { + _M_data = static_cast( +@@ -5252,7 +5311,7 @@ template + + // stores [simd.store] + template +- _GLIBCXX_SIMD_ALWAYS_INLINE void ++ _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR void + copy_to(_Vectorizable<_Up>* __mem, _IsSimdFlagType<_Flags>) const + { + _Impl::_S_store(_M_data, _Flags::template _S_apply(__mem), +@@ -5424,7 +5483,7 @@ template + } + + private: +- _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR static mask_type ++ _GLIBCXX_SIMD_INTRINSIC static constexpr mask_type + _S_make_mask(typename mask_type::_MemberType __k) + { return {__private_init, __k}; } + +--- a/src/libstdc++-v3/include/experimental/bits/simd_builtin.h ++++ b/src/libstdc++-v3/include/experimental/bits/simd_builtin.h +@@ -52,7 +52,7 @@ template > + // Index == -1 requests zeroing of the output element + template , + typename = __detail::__odr_helper> +- _Tp ++ constexpr _Tp + __vector_permute(_Tp __x) + { + static_assert(sizeof...(_Indices) == _TVT::_S_full_size); +@@ -65,7 +65,7 @@ template , + // Index == -1 requests zeroing of the output element + template , + typename = __detail::__odr_helper> +- _Tp ++ constexpr _Tp + __vector_shuffle(_Tp __x, _Tp __y) + { + return _Tp{(_Indices == -1 ? 0 +@@ -205,7 +205,7 @@ template > + // }}} + // __extract_part(_SimdWrapper<_Tp, _Np>) {{{ + template +- _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_CONST ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_CONST constexpr + _SimdWrapper<_Tp, _Np / _Total * _Combine> + __extract_part(const _SimdWrapper<_Tp, _Np> __x) + { +@@ -905,10 +905,10 @@ template + _SimdMember _M_data; + + public: +- _GLIBCXX_SIMD_ALWAYS_INLINE ++ _GLIBCXX_SIMD_ALWAYS_INLINE constexpr + _SimdCastType1(_Ap __a) : _M_data(__vector_bitcast<_Tp>(__a)) {} + +- _GLIBCXX_SIMD_ALWAYS_INLINE ++ _GLIBCXX_SIMD_ALWAYS_INLINE constexpr + operator _SimdMember() const { return _M_data; } + }; + +@@ -919,13 +919,13 @@ template + _SimdMember _M_data; + + public: +- _GLIBCXX_SIMD_ALWAYS_INLINE ++ _GLIBCXX_SIMD_ALWAYS_INLINE constexpr + _SimdCastType2(_Ap __a) : _M_data(__vector_bitcast<_Tp>(__a)) {} + +- _GLIBCXX_SIMD_ALWAYS_INLINE ++ _GLIBCXX_SIMD_ALWAYS_INLINE constexpr + _SimdCastType2(_Bp __b) : _M_data(__b) {} + +- _GLIBCXX_SIMD_ALWAYS_INLINE ++ _GLIBCXX_SIMD_ALWAYS_INLINE constexpr + operator _SimdMember() const { return _M_data; } + }; + +@@ -1345,6 +1345,11 @@ struct _CommonImplBuiltin + { + if constexpr (_Np == 1) + __mem[0] = __x[0]; ++ else if (__builtin_is_constant_evaluated()) ++ { ++ for (size_t __i = 0; __i < _Np; ++__i) ++ __mem[__i] = __x[__i]; ++ } + else if constexpr (_Np == 2) + { + short __bool2 = (__x._M_to_bits() * 0x81) & 0x0101; +@@ -1424,12 +1429,12 @@ template + + // _M_make_simd(_SimdWrapper/__intrinsic_type_t) {{{2 + template +- _GLIBCXX_SIMD_INTRINSIC static simd<_Tp, _Abi> ++ _GLIBCXX_SIMD_INTRINSIC static constexpr simd<_Tp, _Abi> + _M_make_simd(_SimdWrapper<_Tp, _Np> __x) + { return {__private_init, __x}; } + + template +- _GLIBCXX_SIMD_INTRINSIC static simd<_Tp, _Abi> ++ _GLIBCXX_SIMD_INTRINSIC static constexpr simd<_Tp, _Abi> + _M_make_simd(__intrinsic_type_t<_Tp, _Np> __x) + { return {__private_init, __vector_bitcast<_Tp>(__x)}; } + +@@ -1455,7 +1460,7 @@ template + + // _S_load {{{2 + template +- _GLIBCXX_SIMD_INTRINSIC static _SimdMember<_Tp> ++ _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdMember<_Tp> + _S_load(const _Up* __mem, _TypeTag<_Tp>) noexcept + { + constexpr size_t _Np = _S_size<_Tp>; +@@ -1464,7 +1469,12 @@ template + : (is_floating_point_v<_Up> && __have_avx) || __have_avx2 ? 32 + : 16; + constexpr size_t __bytes_to_load = sizeof(_Up) * _Np; +- if constexpr (sizeof(_Up) > 8) ++ if (__builtin_is_constant_evaluated()) ++ return __generate_vector<_Tp, _S_full_size<_Tp>>( ++ [&](auto __i) constexpr { ++ return static_cast<_Tp>(__i < _Np ? __mem[__i] : 0); ++ }); ++ else if constexpr (sizeof(_Up) > 8) + return __generate_vector<_Tp, _SimdMember<_Tp>::_S_full_size>( + [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { + return static_cast<_Tp>(__i < _Np ? __mem[__i] : 0); +@@ -1511,7 +1521,7 @@ template + + // _S_masked_load {{{2 + template +- static inline _SimdWrapper<_Tp, _Np> ++ static constexpr inline _SimdWrapper<_Tp, _Np> + _S_masked_load(_SimdWrapper<_Tp, _Np> __merge, _MaskMember<_Tp> __k, + const _Up* __mem) noexcept + { +@@ -1524,14 +1534,19 @@ template + + // _S_store {{{2 + template +- _GLIBCXX_SIMD_INTRINSIC static void ++ _GLIBCXX_SIMD_INTRINSIC static constexpr void + _S_store(_SimdMember<_Tp> __v, _Up* __mem, _TypeTag<_Tp>) noexcept + { + // TODO: converting int -> "smaller int" can be optimized with AVX512 + constexpr size_t _Np = _S_size<_Tp>; + constexpr size_t __max_store_size + = _SuperImpl::template _S_max_store_size<_Up>; +- if constexpr (sizeof(_Up) > 8) ++ if (__builtin_is_constant_evaluated()) ++ { ++ for (size_t __i = 0; __i < _Np; ++__i) ++ __mem[__i] = __v[__i]; ++ } ++ else if constexpr (sizeof(_Up) > 8) + __execute_n_times<_Np>([&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { + __mem[__i] = __v[__i]; + }); +@@ -1562,7 +1577,7 @@ template + + // _S_masked_store_nocvt {{{2 + template +- _GLIBCXX_SIMD_INTRINSIC static void ++ _GLIBCXX_SIMD_INTRINSIC static constexpr void + _S_masked_store_nocvt(_SimdWrapper<_Tp, _Np> __v, _Tp* __mem, _MaskMember<_Tp> __k) + { + _BitOps::_S_bit_iteration( +@@ -1575,7 +1590,7 @@ template + // _S_masked_store {{{2 + template , + typename _Tp = typename _TVT::value_type, typename _Up> +- static inline void ++ static constexpr inline void + _S_masked_store(const _TW __v, _Up* __mem, const _MaskMember<_Tp> __k) noexcept + { + constexpr size_t _TV_size = _S_size<_Tp>; +@@ -1803,7 +1818,7 @@ template + // reductions {{{2 + template +- _GLIBCXX_SIMD_INTRINSIC static _Tp ++ _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp + _S_reduce_partial(index_sequence<_Is...>, index_sequence<_Zeros...>, + simd<_Tp, _Abi> __x, _BinaryOperation&& __binary_op) + { +@@ -1833,6 +1848,13 @@ template + else if constexpr (_Np == 2) + return __binary_op(simd<_Tp, simd_abi::scalar>(__x[0]), + simd<_Tp, simd_abi::scalar>(__x[1]))[0]; ++ else if (__builtin_is_constant_evaluated()) ++ { ++ simd<_Tp, simd_abi::scalar> __acc = __x[0]; ++ for (size_t __i = 1; __i < _Np; ++__i) ++ __acc = __binary_op(__acc, simd<_Tp, simd_abi::scalar>(__x[__i])); ++ return __acc[0]; ++ } + else if constexpr (_Abi::template _S_is_partial<_Tp>) //{{{ + { + [[maybe_unused]] constexpr auto __full_size +@@ -2370,12 +2392,12 @@ template + constexpr size_t _NI = sizeof(__xn) / sizeof(_I); + _GLIBCXX_SIMD_USE_CONSTEXPR auto __minn + = __vector_bitcast<_I>(__vector_broadcast<_NI>(__norm_min_v<_Tp>)); +- _GLIBCXX_SIMD_USE_CONSTEXPR auto __infn +- = __vector_bitcast<_I>(__vector_broadcast<_NI>(__infinity_v<_Tp>)); + + _GLIBCXX_SIMD_USE_CONSTEXPR auto __fp_normal + = __vector_broadcast<_NI, _I>(FP_NORMAL); + #if !__FINITE_MATH_ONLY__ ++ _GLIBCXX_SIMD_USE_CONSTEXPR auto __infn ++ = __vector_bitcast<_I>(__vector_broadcast<_NI>(__infinity_v<_Tp>)); + _GLIBCXX_SIMD_USE_CONSTEXPR auto __fp_nan + = __vector_broadcast<_NI, _I>(FP_NAN); + _GLIBCXX_SIMD_USE_CONSTEXPR auto __fp_infinite +@@ -2445,24 +2467,24 @@ template + + // _S_increment & _S_decrement{{{2 + template +- _GLIBCXX_SIMD_INTRINSIC static void ++ _GLIBCXX_SIMD_INTRINSIC static constexpr void + _S_increment(_SimdWrapper<_Tp, _Np>& __x) + { __x = __x._M_data + 1; } + + template +- _GLIBCXX_SIMD_INTRINSIC static void ++ _GLIBCXX_SIMD_INTRINSIC static constexpr void + _S_decrement(_SimdWrapper<_Tp, _Np>& __x) + { __x = __x._M_data - 1; } + + // smart_reference access {{{2 + template +- _GLIBCXX_SIMD_INTRINSIC constexpr static void ++ _GLIBCXX_SIMD_INTRINSIC static constexpr void + _S_set(_SimdWrapper<_Tp, _Np>& __v, int __i, _Up&& __x) noexcept + { __v._M_set(__i, static_cast<_Up&&>(__x)); } + + // _S_masked_assign{{{2 + template +- _GLIBCXX_SIMD_INTRINSIC static void ++ _GLIBCXX_SIMD_INTRINSIC static constexpr void + _S_masked_assign(_SimdWrapper<_K, _Np> __k, _SimdWrapper<_Tp, _Np>& __lhs, + __type_identity_t<_SimdWrapper<_Tp, _Np>> __rhs) + { +@@ -2475,7 +2497,7 @@ template + } + + template +- _GLIBCXX_SIMD_INTRINSIC static void ++ _GLIBCXX_SIMD_INTRINSIC static constexpr void + _S_masked_assign(_SimdWrapper<_K, _Np> __k, _SimdWrapper<_Tp, _Np>& __lhs, + __type_identity_t<_Tp> __rhs) + { +@@ -2503,7 +2525,7 @@ template + + // _S_masked_cassign {{{2 + template +- _GLIBCXX_SIMD_INTRINSIC static void ++ _GLIBCXX_SIMD_INTRINSIC static constexpr void + _S_masked_cassign(const _SimdWrapper<_K, _Np> __k, + _SimdWrapper<_Tp, _Np>& __lhs, + const __type_identity_t<_SimdWrapper<_Tp, _Np>> __rhs, +@@ -2519,7 +2541,7 @@ template + } + + template +- _GLIBCXX_SIMD_INTRINSIC static void ++ _GLIBCXX_SIMD_INTRINSIC static constexpr void + _S_masked_cassign(const _SimdWrapper<_K, _Np> __k, + _SimdWrapper<_Tp, _Np>& __lhs, + const __type_identity_t<_Tp> __rhs, _Op __op) +@@ -2528,7 +2550,7 @@ template + // _S_masked_unary {{{2 + template

9

+ C++17 header + <memory_resource> +@@ -425,6 +430,10 @@ Calling a std::bind result as volatile was deprecated + and + <stop_token> + added. ++

++ The extension allowing containers to be instantiated with an allocator ++ that doesn't match the container's value type is no longer allowed in ++ C++20 mode, even in non-strict -std=gnu++20 mode. +