diff -Nru gcc-4.7-4.7.2/debian/changelog gcc-4.7-4.7.3/debian/changelog --- gcc-4.7-4.7.2/debian/changelog 2013-06-25 15:26:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/changelog 2013-06-25 15:26:04.000000000 +0000 @@ -1,8 +1,517 @@ -gcc-4.7 (4.7.2-11precise2) precise; urgency=low +gcc-4.7 (4.7.3-2ubuntu1~12.04) precise; urgency=low - * Build for lucid. + * PPA upload. - -- Matthias Klose Mon, 26 Nov 2012 04:55:31 +0100 + -- Matthias Klose Sun, 21 Apr 2013 19:53:11 +0200 + +gcc-4.7 (4.7.3-2ubuntu1) raring; urgency=low + + * Merge with Debian; remaining changes: + - Build from upstream source. + * Re-enable Linaro changes which were reverted in 4.7.3-1ubuntu1. + + -- Matthias Klose Sun, 21 Apr 2013 19:24:42 +0200 + +gcc-4.7 (4.7.3-2) experimental; urgency=low + + * Update to SVN 20130421 (r198115) from the gcc-4_7-branch. + - Fix PR libstdc++/54847, PR debug/53453, PR target/56890 (sparc), + PR target/55487 (parisc), PR c++/56388, PR fortran/56994, + PR middle-end/56848, PR middle-end/56077, PR tree-optimization/48189. + * Use target specific names for libstdc++ baseline files. LP: #1168267. + * Fix control file for builds without the x32 multilibs + * Ignore the return value for dh_shlibdeps for builds on precise/ARM. + * In gnatlink, pass the options and libraries after objects to the + linker to avoid link failures with --as-needed. Addresses: #680292. + + -- Matthias Klose Sun, 21 Apr 2013 14:54:57 +0200 + +gcc-4.7 (4.7.3-1ubuntu1) raring; urgency=low + + * Merge with Debian; remaining changes: + - Build from upstream source. + * Revert Linaro changes for this upload: + - Revert the partial backport Vectorizer Cost Model for ARM. + * Use target specific names for libstdc++ baseline files. LP: #1168267. + + -- Matthias Klose Fri, 12 Apr 2013 13:17:16 +0200 + +gcc-4.7 (4.7.3-1) experimental; urgency=low + + * GCC 4.7.3 release. + - Fix PR middle-end/56848, reverting the fix for PR middle-end/56077. + * Refresh patches. + * Update the Linaro support to the 4.7-2013.04 release. + - Merges from the arm/aarch64-4.7-branch branch. + - Partial backport Vectorizer Cost Model for ARM. + - Backport "Turn off 64bits ops in Neon" from mainline. + + -- Matthias Klose Thu, 11 Apr 2013 12:19:03 +0200 + +gcc-4.7 (4.7.2-24) experimental; urgency=low + + * Fix PR middle-end/56848, reverting the fix for PR middle-end/56077. + + -- Matthias Klose Fri, 05 Apr 2013 19:56:11 +0200 + +gcc-4.7 (4.7.2-23ubuntu2) raring; urgency=low + + * Fix PR middle-end/56848, reverting the fix for PR middle-end/56077. + LP: #1164886. + + -- Matthias Klose Fri, 05 Apr 2013 12:13:56 +0200 + +gcc-4.7 (4.7.2-23ubuntu2~r197382) raring; urgency=low + + * Merge with Debian; remaining changes: + - Build from upstream source. + + -- Matthias Klose Thu, 04 Apr 2013 13:23:14 +0200 + +gcc-4.7 (4.7.2-23) experimental; urgency=low + + * Update to SVN 20130404 (r197476) from the gcc-4_7-branch (4.7.3 release + candidate 1). + - Fix PR libstdc++/56012, PR libstdc++/56011, PR target/56529 (SH), + PR tree-optimization/55481, PR middle-end/52888, PR target/56351 (ARM), + PR tree-optimization/56443, PR c++/56543, PR lto/50293, PR c++/56614, + PR c++/56403, PR c++/56534, PR ada/52123, PR fortran/56575, + PR fortran/55362, PR libstdc++/56468, PR libstdc++/56002, + PR target/49880 (SH), PR tree-optimization/56608, PR target/56470 (ARM), + PR tree-optimization/56270, PR target/56560 (x86), PR bootstrap/56258, + PR c++/54277, PR c++/56646, PR fortran/56615, PR tree-optimization/56501, + PR tree-optimization/56539, PR debug/56510, PR middle-end/56768, + PR middle-end/45472, PR middle-end/56461, PR middle-end/55889, + PR middle-end/56077, PR debug/56819, PR c++/56794, PR c++/56774, + PR c++/35722, PR fortran/56737, PR fortran/56737, PR fortran/56735, + PR target/56771. + * Fix PR rtl-optimization/56484 (Venkataramanan Kumar, Linaro only). + LP: #1135633. + * Update the Linaro support to the 4.7-2013.03 release. + + -- Matthias Klose Thu, 04 Apr 2013 13:06:02 +0200 + +gcc-4.7 (4.7.2-22ubuntu5) raring; urgency=low + + * Update to SVN 20130328 (r197184) from the gcc-4_7-branch. + - Fix PR libstdc++/56468, PR libstdc++/56002, + PR target/49880 (SH), PR tree-optimization/56608, PR target/56470 (ARM), + PR tree-optimization/56270, PR target/56560 (x86), PR bootstrap/56258, + PR c++/54277, PR c++/56646, PR fortran/56615. + + -- Matthias Klose Thu, 28 Mar 2013 03:30:49 +0100 + +gcc-4.7 (4.7.2-22ubuntu4) raring; urgency=low + + * Update the Linaro support to the 4.7-2013.03 release. + - Aarch64 updates. + + -- Matthias Klose Thu, 14 Mar 2013 20:52:50 -0700 + +gcc-4.7 (4.7.2-22ubuntu3) raring; urgency=low + + * Update to SVN 20130307 (r196523) from the gcc-4_7-branch. + - Fix PR libstdc++/56012, PR libstdc++/56011, PR target/56529 (SH), + PR tree-optimization/55481, PR middle-end/52888, PR target/56351 (ARM), + PR tree-optimization/56443, PR c++/56543, PR lto/50293, PR c++/56614, + PR c++/56403, PR c++/56534, PR ada/52123, PR fortran/56575, + PR fortran/55362. + * Fix PR rtl-optimization/56484 (Venkataramanan Kumar, Linaro only). + LP: #1135633. + + -- Matthias Klose Fri, 08 Mar 2013 00:40:18 +0800 + +gcc-4.7 (4.7.2-22ubuntu2) raring; urgency=low + + * Build arm64 from the Linaro branch again. + + -- Matthias Klose Tue, 26 Feb 2013 07:55:17 +0100 + +gcc-4.7 (4.7.2-22ubuntu1) raring; urgency=low + + * Merge with Debian; remaining changes: + - Build from upstream source. + + -- Matthias Klose Sat, 23 Feb 2013 06:43:05 +0100 + +gcc-4.7 (4.7.2-22) experimental; urgency=low + + * Update to SVN 20130222 (r196236) from the gcc-4_7-branch. + - Fix PR rtl-optimization/56275, PR target/56043, PR c++/56268, + PR c++/56247, PR target/52122, PR c++/56291, PR target/52123, + PR target/52122, PR c++/54276, PR c++/52026, PR c++/55710, PR c++/56135, + PR fortran/53537, PR middle-end/56217, PR libstdc++/55043, + PR other/56245, PR bootstrap/56258, PR tree-optimization/56350, + PR tree-optimization/56381, PR tree-optimization/56250, + PR middle-end/56217, PR tree-optimization/55110, PR c++/40405, + PR c++/56395, PR c++/56241, PR c++/56239, PR c++/56237, PR ada/56271, + PR fortran/56385, PR libfortran/30162. + * Revert the fix for PR optimization/53844. LP: #1123588. + * Update the Linaro support to the 4.7-2013.02 release. + + -- Matthias Klose Sat, 23 Feb 2013 06:28:17 +0100 + +gcc-4.7 (4.7.2-21ubuntu3) raring; urgency=low + + * Update to SVN 20130214 (r196053) from the gcc-4_7-branch. + - Fix PR c++/56291, PR target/52123, PR target/52122. + * Update the Linaro support to the 4.7-2013.02 release. + + -- Matthias Klose Thu, 14 Feb 2013 19:11:22 +0100 + +gcc-4.7 (4.7.2-21ubuntu2) raring; urgency=low + + * Update to SVN 20130212 (r195985) from the gcc-4_7-branch. + - Fix PR rtl-optimization/56275, PR target/56043, PR c++/56268, + PR c++/56247, PR target/52122. + * Revert the fix for PR optimization/53844. LP: #1123588. + + -- Matthias Klose Wed, 13 Feb 2013 01:16:12 +0100 + +gcc-4.7 (4.7.2-21ubuntu1) raring; urgency=low + + * Merge with Debian; remaining changes: + - Build from upstream source. + + -- Matthias Klose Fri, 08 Feb 2013 23:59:10 +0100 + +gcc-4.7 (4.7.2-21) experimental; urgency=low + + * Update to SVN 20130208 (r195898) from the gcc-4_7-branch. + - Fix PR libgomp/51376, PR libgomp/56073, PR libquadmath/56072, + PR other/54620, PR target/39064, PR other/53413, PR other/53285, + PR bootstrap/56227, PR target/53040, PR tree-optimization/55107, + PR tree-optimization/54767, PR tree-optimization/44061, PR lto/55660, + PR middle-end/55890, PR tree-optimization/53844, PR middle-end/55890, + PR tree-optimization/56125, PR tree-optimization/56098, PR target/49069, + PR tree-optimization/56051, PR middle-end/56015, PR target/55940, + PR tree-optimization/55921, PR rtl-optimization/55838, PR c++/54046, + PR middle-end/55094, PR tree-optimization/55236, + PR rtl-optimization/54127, PR c++/54122, PR c++/55652, PR c++/54207, + PR c++/55542, PR c++/54046, PR target/50678, PR fortran/50627, + PR fortran/56054, PR fortran/56052, PR bootstrap/56227, + PR tree-optimization/56051, PR middle-end/56015, PR target/55940, + PR tree-optimization/55921, PR rtl-optimization/55838, PR c++/54046, + PR middle-end/55094, PR tree-optimization/55236, + PR rtl-optimization/54127, PR c++/54122, PR c++/55652, PR c++/54207, + PR c++/55542, PR c++/54046, PR target/50678, PR fortran/50627, + PR fortran/56054, PR fortran/56052, PR bootstrap/56227. + + [ Thibaut Girka ] + * Fix dh_shlibdeps and dh_gencontrol cross-build mangling for + libgfortran-dev packages. + + [ Matthias Klose ] + * Fix dh_shlibdeps calls for the libgo packages. + * Use the CLooG PPL 1.0 backend for graphite. + + -- Matthias Klose Fri, 08 Feb 2013 21:04:54 +0100 + +gcc-4.7 (4.7.2-20ubuntu1) raring; urgency=low + + * Merge with Debian; remaining changes: + - Build from upstream source. + + -- Matthias Klose Wed, 30 Jan 2013 02:46:31 +0100 + +gcc-4.7 (4.7.2-20) experimental; urgency=low + + * Update to SVN 20130130 (r195565) from the gcc-4_7-branch. + - Fix PR libstdc++/56085, PR target/56114, PR target/56028, + PR tree-optimization/55755, PR rtl-optimization/56023, + PR tree-optimization/55264, PR target/55981, PR c++/56104, PR c++/53650, + PR c++/56071, PR c++/56059, PR fortran/56081, PR tree-optimization/56113, + PR target/35294 (ARM). + + [ Matthias Klose ] + * Fix MULTILIB_OS_DIRNAME for the default multilib on x32. + * Bump dependencies on cloog/ppl. + * Add a Build-Using attribute for each binary package, which can be + built from the gcc-4.7-source package (patch derived from a proposal by + Ansgar Burchardt). + - Use it for cross-compiler packages. + - Not yet used when building gcj, gdc or gnat using the gcc-source package. + These packages don't require an exact version of the gcc-source package, + but just a versions which is specifed by the build dependencies. + + [ Thibaut Girka ] + * Fix regexp used to list patched autotools files. + + -- Matthias Klose Wed, 30 Jan 2013 01:04:15 +0100 + +gcc-4.7 (4.7.2-19ubuntu1) raring; urgency=low + + * Merge with Debian; remaining changes: + - Build from upstream source. + + -- Matthias Klose Thu, 17 Jan 2013 21:47:02 +0100 + +gcc-4.7 (4.7.2-19) experimental; urgency=low + + * Update to SVN 20130117 (r195280) from the gcc-4_7-branch. + - Fix PR target/55974 (AVR), PR fortran/55072, PR fortran/55618, + PR libstdc++/52887, PR fortran/55983. + - Backport multiarch patches. + * Update the Linaro support to the 4.7-2013.01 release. + + * Don't call dh_shlibdeps for staged cross builds. These packages + are never shipped, and the information is irrelevant. + * Don't ship libiberty.a in gcc-4.7-hppa64. Closes: #659556. + * Fix dependency on the non-default multilib libc-dev. LP: #1100894. + + -- Matthias Klose Thu, 17 Jan 2013 21:48:29 +0100 + +gcc-4.7 (4.7.2-18ubuntu1) raring; urgency=low + + * Merge with Debian; remaining changes: + - Build from upstream source. + + -- Matthias Klose Fri, 11 Jan 2013 18:31:24 +0100 + +gcc-4.7 (4.7.2-18) experimental; urgency=low + + * Update to SVN 20130111 (r195107) from the gcc-4_7-branch. + - Fix PR c++/55877, PR target/55897, PR target/54461, PR other/55243, + PR target/55712, PR fortran/42769, PR fortran/45836, PR fortran/45900, + PR fortran/55852, PR fortran/55827, PR c++/55893. + * Explicitly search multiarch and multilib system directories when + calling dh_shlibdeps. + * Let gjdoc accept -source 1.5|1.6|1.7. Addresses: #678945. + * Fix build configured with --enable-java-maintainer-mode. + * Don't ship .md5 files in the libstdc++-doc package. + * Always configure --with-system-zlib. + * Search library dependencies in the build-sysroot too. + * Don't complain about missing .substvars files when trying to mangle + these files. + * Add ARM multilib packages to the control file for staged cross builds. + * Fix ARM multilib shlibs dependency generation for cross builds. + + -- Matthias Klose Fri, 11 Jan 2013 17:18:23 +0100 + +gcc-4.7 (4.7.2-17ubuntu2) raring; urgency=low + + * Update to SVN 20130105 (r194933) from the gcc-4_7-branch. + - Fix PR c++/55877. + * Explicitly search multiarch and multilib system directories when + calling dh_shlibdeps. + * Let gjdoc accept -source 1.5|1.6|1.7. Addresses: #678945. + * Fix build configured with --enable-java-maintainer-mode. + * Don't ship .md5 files in the libstdc++-doc package. + * Always configure --with-system-zlib. + + -- Matthias Klose Sat, 05 Jan 2013 20:28:47 +0100 + +gcc-4.7 (4.7.2-17ubuntu1) raring; urgency=low + + * Merge with Debian; remaining changes: + - Build from upstream source. + + -- Matthias Klose Fri, 04 Jan 2013 16:42:31 +0100 + +gcc-4.7 (4.7.2-17) experimental; urgency=low + + * Update to SVN 20130104 (r194901) from the gcc-4_7-branch. + - Fix PR target/53789 (hppa), PR bootstrap/55707, PR c++/55804, + PR tree-optimization/55355, PR c++/55419, PR c++/55753, PR c++/55842, + PR c++/55856, PR c++/54325, PR c++/55032, PR c++/55245, PR c++/55724, + PR ada/53737, PR fortran/54818, PR libfortran/30162. + + [ Matthias Klose ] + * Move .jar symlinks from the -jre-lib into the -jre-headless package. + * Keep the debug link for libstdc++6. Closes: #696854. + * Fix libstdc++ symbols files for sparc 128bit symbols. + * Keep the rt.jar symlink in the gcj-jre-headless package. + + [ Thibaut Girka ] + * Prepare for optional dependencies on the packages built on the + target architecture. + * When using the above, + - use the same settings for gcc_lib_dir, sysroot, header and C++ header + locations as for the native build. + - install libraries into the multiarch directories. + - use cpp-4.x- instead of gcc-4.x-base to collect doc files. + + -- Matthias Klose Fri, 04 Jan 2013 16:24:21 +0100 + +gcc-4.7 (4.7.2-16ubuntu1) raring; urgency=low + + * Fix libc6 multilib dependencies on armhf. + + -- Matthias Klose Tue, 18 Dec 2012 14:10:51 +0100 + +gcc-4.7 (4.7.2-16) experimental; urgency=low + + * Allow building a gcj cross compiler. + * Fix libobjc-dbg dependencies on libgcc-dbg packages. + + -- Matthias Klose Mon, 17 Dec 2012 15:58:31 +0100 + +gcc-4.7 (4.7.2-15ubuntu1) raring; urgency=low + + * Merge with Debian; remaining changes: + - Build from upstream source. + + -- Matthias Klose Mon, 17 Dec 2012 14:57:14 +0100 + +gcc-4.7 (4.7.2-15) experimental; urgency=low + + * Update to SVN 20121217 (r194553) from the gcc-4_7-branch. + - Fix PR libstdc++/55631, PR middle-end/55492, PR target/54121, + PR c++/54883, PR c++/55643, PR target/55673, PR ada/54614, PR ada/53766. + + [ Matthias Klose ] + * Drop build-dependency on libelf. + * Drop the g++-multilib build dependency, use the built compiler to + check which multilib variants can be run. Provide an asm symlink for + the build. + * Stop configuring cross compilers --with-headers --with-libs. + * Always call dh_shlibdeps with -l, pointing to the correct dependency + packages. + * Fix cross build stage1 package installation, only including the target + files in the gcc package. + * Explicitly configure with --enable-multiarch when doing builds + supporting the multiarch layout. + * Only configure --with-sysroot, --with-build-sysroot when values are set. + * Revert: For stage1 builds, include gcc_lib_dir files in the gcc package. + * Allow multilib enabled stage1 and stage2 cross builds. + * libgcc backports from the trunk: + - Always define USE_PT_GNU_EH_FRAME in crtstuff.c for glibc. + - Build static libgcc with hidden visibility even with --disable-shared. + * Don't check glibc version to configure --with-long-double-128. + * Don't auto-detect multilib osdirnames. + * Don't set a LD_LIBRARY_PATH when calling dh_shlibdeps in cross builds. + * Pretend that wheezy has x32 support (sid is now known as wheezy :-/). + + [ Thibaut Girka ] + * Call $(cross_gencontrol) dh_gencontrol bulding libgfortran-dev. + * Set MULTIARCH_DIRNAME for builds configured with --disable-multilib + on mips and s390. + + -- Matthias Klose Mon, 17 Dec 2012 14:12:49 +0100 + +gcc-4.7 (4.7.2-14ubuntu2) raring; urgency=low + + * Update to SVN 20121214 (r194398) from the gcc-4_7-branch. + - Fix PR libstdc++/55631, PR middle-end/55492, PR target/54121, + PR c++/54883, PR c++/55643. + + [ Matthias Klose ] + * Drop build-dependency on libelf. + * Drop the g++-multilib build dependency, use the built compiler to + check which multilib variants can be run. Provide an asm symlink for + the build. + * Stop configuring cross compilers --with-headers --with-libs. + * Always call dh_shlibdeps with -l, pointing to the correct dependency + packages. + * Fix cross build stage1 package installation, only including the target + files in the gcc package. + + [ Thibaut Girka ] + * Call $(cross_gencontrol) dh_gencontrol bulding libgfortran-dev. + * Set MULTIARCH_DIRNAME for builds configured with --disable-multilib + on mips and s390. + + -- Matthias Klose Fri, 14 Dec 2012 14:50:51 +0100 + +gcc-4.7 (4.7.2-14ubuntu1) raring; urgency=low + + * Merge with Debian; remaining changes: + - Build from upstream source. + + -- Matthias Klose Tue, 11 Dec 2012 09:03:32 +0100 + +gcc-4.7 (4.7.2-14) experimental; urgency=low + + * Update to SVN 20121211 (r194382) from the gcc-4_7-branch. + - Fix PR target/55344, PR target/53912. + * Update the Linaro support to a 4.7-2012.12 pre-release. + * Fix spu cross build on powerpc/ppc64. + * Make libgcj packages Multi-Arch: same, append the Debian architecture + name to the gcj java home. + * Don't encode versioned build dependencies on binutils and dpkg-dev in + the control file (makes the package cross-buildable). + * Drop the versioned build dependency on make (>= 3.81). + * Only include gengtype for native builds. Needs upstream changes. + See #645018. + * Build fixes for libstdc++ and libgo, when cross building the native + compiler. + * When cross building the native compiler, configure --with-sysroot=/ + and without --without-ppl. + * Fix package builds with the common libraries provided by a newer + gcc-X.Y package. + * Stop building packages now built from gcc-4.8 in experimental. + + -- Matthias Klose Tue, 11 Dec 2012 08:49:17 +0100 + +gcc-4.7 (4.7.2-13) experimental; urgency=low + + * Update to SVN 20121208 (r194323) from the gcc-4_7-branch. + - Fix PR libstdc++/55503, PR libgcc/48076, PR c/55570, + PR tree-optimization/53663, PR target/53912, PR target/55195, + PR target/55171, PR lto/54795, PR lto/55474, PR rtl-optimization/55489, + PR c++/53137, PR c++/53862, PR c++/53039, PR c++/50852, PR c++/53039, + PR c++/55032, PR c++/54325, PR c++/55058, PR c++/55249, PR c++/54744, + PR c++/54947, PR c++/55015, PR c++/53821, PR c++/55419, PR ada/52110, + bootstrap/55571, PR target/55597. + * Point to gcc's README.Bugs when building gcj packages. Closes: #623987. + * Re-enable the patch to add options -fuse-ld=gold and -fuse-ld=bfd. Keep + -fuse-ld=ld.bfd as an alias. + * For cross builds, don't use the multiarch location for the C++ headers. + * For cross builds, fix multilib inter package dependencies. + * For cross builds, fix libc6 dependencies for non-default multilib packages. + * Aarch64 updates, taken from the Linaro branch. + * Only run the libgo testsuite for flags configured in RUNTESTFLAGS. + * Remove the cross-includes patch, not needed anymore with --with-sysroot=/. + * For cross builds, install into /usr/lib/gcc-cross to avoid file conflicts + with the native compiler for the target architecture. + * For cross builds, don't add /usr/local/include to the standard include + path, however /usr/local/include/ is still on the path. + * For cross builds, provide symbols files based on the symbols files for + the native build. Not picked up by dh_makeshlibs yet. + + -- Matthias Klose Sat, 08 Dec 2012 14:52:45 +0100 + +gcc-4.7 (4.7.2-12ubuntu2) raring; urgency=low + + * Update to SVN 20121205 (r194220) from the gcc-4_7-branch. + - Fix PR libstdc++/55503, PR libgcc/48076, PR c/55570, + PR tree-optimization/53663, PR target/53912, PR target/55195, + PR target/55171, PR lto/54795, PR lto/55474, PR rtl-optimization/55489, + PR c++/53137, PR c++/53862, PR c++/53039, PR c++/50852, PR c++/53039, + PR ada/52110, bootstrap/55571. + * Point to gcc's README.Bugs when building gcj packages. Closes: #623987. + * Re-enable the patch to add options -fuse-ld=gold and -fuse-ld=bfd. Keep + -fuse-ld=ld.bfd as an alias. + * For cross builds, don't use the multiarch location for the C++ headers. + * Split out a gccgo-4.7-doc package. + + -- Matthias Klose Wed, 05 Dec 2012 13:31:27 +0100 + +gcc-4.7 (4.7.2-12ubuntu1) raring; urgency=low + + * Merge with Debian; remaining changes: + - Build from upstream source. + + -- Matthias Klose Tue, 27 Nov 2012 13:38:44 +0100 + +gcc-4.7 (4.7.2-12) experimental; urgency=low + + * Update to SVN 20121127 (r193840) from the gcc-4_7-branch. + - Fix PR middle-end/55331 (ice on valid), PR tree-optimization/54976 (ice + on valid), PR tree-optimization/54894 (ice on valid), + PR middle-end/54735 (ice on valid), PR c++/55446 (wrong code), + PR fortran/55314 (rejects valid). + + [ Matthias Klose ] + * Fix x32 multiarch name (x86_64-linux-gnux32). + * gcc-4.7-base: Add break to gcc-4.4-base (<< 4.4.7). Closes: #690172. + * Add weak __aeabi symbols to the libgcc1 ARM symbol files. Closes: #677139. + * For stage1 builds, include gcc_lib_dir files in the gcc package. + + [ Thibaut Girka ] + * Fix libstdc++ multiarch include path for cross builds. + + -- Matthias Klose Tue, 27 Nov 2012 11:02:10 +0100 gcc-4.7 (4.7.2-11ubuntu1) raring; urgency=low diff -Nru gcc-4.7-4.7.2/debian/control gcc-4.7-4.7.3/debian/control --- gcc-4.7-4.7.2/debian/control 2013-06-25 15:26:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/control 2013-06-25 15:26:04.000000000 +0000 @@ -5,7 +5,17 @@ XSBC-Original-Maintainer: Debian GCC Maintainers Uploaders: Matthias Klose Standards-Version: 3.9.3 -Build-Depends: dpkg-dev (>= 1.16.0~ubuntu4), debhelper (>= 5.0.62), g++-multilib [amd64 armel armhf i386 kfreebsd-amd64 mips mipsel powerpc ppc64 s390 s390x sparc x32], libc6.1-dev (>= 2.13-0ubuntu6) [alpha ia64] | libc0.3-dev (>= 2.13-0ubuntu6) [hurd-i386] | libc0.1-dev (>= 2.13-0ubuntu6) [kfreebsd-i386 kfreebsd-amd64] | libc6-dev (>= 2.13-0ubuntu6), libc6-dev (>= 2.13-31) [armel armhf], libc6-dev-amd64 [i386 x32], libc6-dev-sparc64 [sparc], libc6-dev-s390 [s390x], libc6-dev-s390x [s390], libc6-dev-i386 [amd64 x32], libc6-dev-powerpc [ppc64], libc6-dev-ppc64 [powerpc], libc0.1-dev-i386 [kfreebsd-amd64], lib32gcc1 [amd64 ppc64 kfreebsd-amd64 s390x x32], lib64gcc1 [i386 powerpc sparc s390 x32], libc6-dev-mips64 [mips mipsel], libc6-dev-mipsn32 [mips mipsel], libc6-dev-armhf [armel], libc6-dev-armel [armhf], m4, libtool, autoconf2.64, libunwind7-dev (>= 0.98.5-6) [ia64], libatomic-ops-dev [ia64], zlib1g-dev, gawk, lzma, xz-utils, patchutils, binutils (>= 2.22) | binutils-multiarch (>= 2.22), binutils-hppa64 (>= 2.22) [hppa], gperf (>= 3.0.1), bison (>= 1:2.3), flex, gettext, texinfo (>= 4.3), locales, procps, sharutils, netbase, binutils-spu (>= 2.22) [powerpc ppc64], newlib-spu (>= 1.16.0) [powerpc ppc64], libcloog-ppl-dev (>= 0.15.9-2~), libmpc-dev, libmpfr-dev (>= 3.0.0-9~), libgmp-dev (>= 2:5.0.1~), libelf-dev | libelfg0-dev (>= 0.8.12), dejagnu [!m68k !hurd-i386 !hurd-alpha], autogen, realpath (>= 1.9.12), chrpath, lsb-release, make (>= 3.81), quilt +Build-Depends: debhelper (>= 5.0.62), + libc6.1-dev (>= 2.13-0ubuntu6) [alpha ia64] | libc0.3-dev (>= 2.13-0ubuntu6) [hurd-i386] | libc0.1-dev (>= 2.13-0ubuntu6) [kfreebsd-i386 kfreebsd-amd64] | libc6-dev (>= 2.13-0ubuntu6) , libc6-dev (>= 2.13-31) [armel armhf], libc6-dev-amd64 [i386 x32], libc6-dev-sparc64 [sparc], libc6-dev-s390 [s390x], libc6-dev-s390x [s390], libc6-dev-i386 [amd64 x32], libc6-dev-powerpc [ppc64], libc6-dev-ppc64 [powerpc], libc0.1-dev-i386 [kfreebsd-amd64], lib32gcc1 [amd64 ppc64 kfreebsd-amd64 s390x x32], lib64gcc1 [i386 powerpc sparc s390 x32], libc6-dev-mips64 [mips mipsel], libc6-dev-mipsn32 [mips mipsel], libc6-dev-armhf [armel], libc6-dev-armel [armhf], + m4, libtool, autoconf2.64, automake (>= 1:1.11), automake (<< 1:1.12), + libunwind7-dev (>= 0.98.5-6) [ia64], libatomic-ops-dev [ia64], + zlib1g-dev, gawk, lzma, xz-utils, patchutils, + binutils-hppa64 (>= 2.22) [hppa], + gperf (>= 3.0.1), bison (>= 1:2.3), flex, gettext, + texinfo (>= 4.3), locales, sharutils, + procps, netbase, binutils-spu (>= 2.22) [powerpc ppc64], newlib-spu (>= 1.16.0) [powerpc ppc64], + libcloog-ppl-dev (>= 0.15.11), libmpc-dev, libmpfr-dev (>= 3.0.0-9~), libgmp-dev (>= 2:5.0.1~), + dejagnu [!m68k !arm !armel !armhf !hurd-i386 !hurd-alpha], autogen, realpath (>= 1.9.12), chrpath, lsb-release, quilt Build-Depends-Indep: doxygen (>= 1.7.2), graphviz (>= 2.2), ghostscript, texlive-latex-base, xsltproc, libxml2-utils, docbook-xsl-ns, Build-Conflicts: binutils-gold Homepage: http://gcc.gnu.org/ @@ -19,25 +29,11 @@ Priority: required Depends: ${misc:Depends} Replaces: ${base:Replaces} -Breaks: gcj-4.4-base (<< 4.4.6-9~), gnat-4.4-base (<< 4.4.6-3~), gcj-4.6-base (<< 4.6.1-4~), gnat-4.6 (<< 4.6.1-5~), dehydra (<= 0.9.hg20110609-2) +Breaks: gcc-4.4-base (<< 4.4.7), gcj-4.4-base (<< 4.4.6-9~), gnat-4.4-base (<< 4.4.6-3~), gcj-4.6-base (<< 4.6.1-4~), gnat-4.6 (<< 4.6.1-5~), dehydra (<= 0.9.hg20110609-2) Description: GCC, the GNU Compiler Collection (base package) This package contains files common to all languages and libraries contained in the GNU Compiler Collection (GCC). -Package: libgcc1 -Architecture: any -Section: libs -Priority: required -Depends: gcc-4.7-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Multi-Arch: same -Pre-Depends: multiarch-support -Breaks: ${multiarch:breaks} -Provides: libgcc1-armel [armel], libgcc1-armhf [armhf] -Description: GCC support library - Shared version of the support library, a library of internal subroutines - that GCC uses to overcome shortcomings of particular machines, or - special needs for some languages. - Package: libgcc-4.7-dev Architecture: any Section: libdevel @@ -50,71 +46,6 @@ This package contains the headers and static library files necessary for building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. -Package: libgcc1-dbg -Architecture: any -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libgcc1 (= ${gcc:EpochVersion}), ${misc:Depends} -Multi-Arch: same -Provides: libgcc1-dbg-armel [armel], libgcc1-dbg-armhf [armhf] -Description: GCC support library (debug symbols) - Debug symbols for the GCC support library. - -Package: libgcc2 -Architecture: m68k -Section: libs -Priority: required -Depends: gcc-4.7-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Multi-Arch: same -Pre-Depends: multiarch-support -Breaks: ${multiarch:breaks} -Description: GCC support library - Shared version of the support library, a library of internal subroutines - that GCC uses to overcome shortcomings of particular machines, or - special needs for some languages. - -Package: libgcc2-dbg -Architecture: m68k -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libgcc2 (= ${gcc:Version}), ${misc:Depends} -Multi-Arch: same -Description: GCC support library (debug symbols) - Debug symbols for the GCC support library. - -Package: libgcc4 -Architecture: hppa -Multi-Arch: same -Pre-Depends: multiarch-support -Breaks: ${multiarch:breaks} -Section: libs -Priority: required -Depends: gcc-4.7-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Description: GCC support library - Shared version of the support library, a library of internal subroutines - that GCC uses to overcome shortcomings of particular machines, or - special needs for some languages. - -Package: libgcc4-dbg -Architecture: hppa -Multi-Arch: same -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libgcc4 (= ${gcc:Version}), ${misc:Depends} -Description: GCC support library (debug symbols) - Debug symbols for the GCC support library. - -Package: lib64gcc1 -Architecture: i386 powerpc sparc s390 mips mipsel x32 -Section: libs -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${misc:Depends} -Conflicts: libgcc1 (<= 1:3.3-0pre9) -Description: GCC support library (64bit) - Shared version of the support library, a library of internal subroutines - that GCC uses to overcome shortcomings of particular machines, or - special needs for some languages. - Package: lib64gcc-4.7-dev Architecture: i386 powerpc sparc s390 mips mipsel x32 Section: libdevel @@ -126,25 +57,6 @@ This package contains the headers and static library files necessary for building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. -Package: lib64gcc1-dbg -Architecture: i386 powerpc sparc s390 mips mipsel x32 -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib64gcc1 (= ${gcc:EpochVersion}), ${misc:Depends} -Description: GCC support library (debug symbols) - Debug symbols for the GCC support library. - -Package: lib32gcc1 -Architecture: amd64 ppc64 kfreebsd-amd64 s390x x32 -Section: libs -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${misc:Depends} -Conflicts: ${confl:lib32} -Description: GCC support library (32 bit Version) - Shared version of the support library, a library of internal subroutines - that GCC uses to overcome shortcomings of particular machines, or - special needs for some languages. - Package: lib32gcc-4.7-dev Architecture: amd64 ppc64 kfreebsd-amd64 s390x x32 Section: libdevel @@ -156,25 +68,6 @@ This package contains the headers and static library files necessary for building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. -Package: lib32gcc1-dbg -Architecture: amd64 ppc64 kfreebsd-amd64 s390x x32 -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib32gcc1 (= ${gcc:EpochVersion}), ${misc:Depends} -Description: GCC support library (debug symbols) - Debug symbols for the GCC support library. - -Package: libhfgcc1 -Architecture: armel -Section: libs -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${misc:Depends} -Conflicts: libgcc1-armhf [armel] -Description: GCC support library (hard float ABI) - Shared version of the support library, a library of internal subroutines - that GCC uses to overcome shortcomings of particular machines, or - special needs for some languages. - Package: libhfgcc-4.7-dev Architecture: armel Section: libdevel @@ -186,26 +79,6 @@ This package contains the headers and static library files necessary for building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. -Package: libhfgcc1-dbg -Architecture: armel -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libhfgcc1 (= ${gcc:EpochVersion}), ${misc:Depends} -Conflicts: libgcc1-dbg-armhf [armel] -Description: GCC support library (debug symbols) - Debug symbols for the GCC support library. - -Package: libsfgcc1 -Architecture: armhf -Section: libs -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${misc:Depends} -Conflicts: libgcc1-armel [armhf] -Description: GCC support library (soft float ABI) - Shared version of the support library, a library of internal subroutines - that GCC uses to overcome shortcomings of particular machines, or - special needs for some languages. - Package: libsfgcc-4.7-dev Architecture: armhf Section: libdevel @@ -217,26 +90,6 @@ This package contains the headers and static library files necessary for building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. -Package: libsfgcc1-dbg -Architecture: armhf -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libsfgcc1 (= ${gcc:EpochVersion}), ${misc:Depends} -Conflicts: libgcc1-dbg-armel [armhf] -Description: GCC support library (debug symbols) - Debug symbols for the GCC support library. - -Package: libn32gcc1 -Architecture: mips mipsel -Section: libs -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${misc:Depends} -Conflicts: libgcc1 (<= 1:3.3-0pre9) -Description: GCC support library (n32) - Shared version of the support library, a library of internal subroutines - that GCC uses to overcome shortcomings of particular machines, or - special needs for some languages. - Package: libn32gcc-4.7-dev Architecture: mips mipsel Section: libdevel @@ -248,21 +101,13 @@ This package contains the headers and static library files necessary for building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. -Package: libn32gcc1-dbg -Architecture: mips mipsel -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libn32gcc1 (= ${gcc:EpochVersion}), ${misc:Depends} -Description: GCC support library (debug symbols) - Debug symbols for the GCC support library. - Package: gcc-4.7 Architecture: any Section: devel Priority: optional Depends: gcc-4.7-base (= ${gcc:Version}), cpp-4.7 (= ${gcc:Version}), binutils (>= ${binutils:Version}), libgcc-4.7-dev (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} Recommends: ${dep:libcdev} -Suggests: ${gcc:multilib}, libmudflap0-4.7-dev (>= ${gcc:Version}), gcc-4.7-doc (>= ${gcc:SoftVersion}), gcc-4.7-locales (>= ${gcc:SoftVersion}), libgcc1-dbg, libgomp1-dbg, libitm1-dbg, libquadmath0-dbg, libmudflap0-dbg, ${dep:libcloog}, ${dep:gold} +Suggests: ${gcc:multilib}, libmudflap0-4.7-dev (>= ${gcc:Version}), gcc-4.7-doc (>= ${gcc:SoftVersion}), gcc-4.7-locales (>= ${gcc:SoftVersion}), libgcc1-dbg (>= ${gcc:EpochVersion}), libgomp1-dbg (>= ${gcc:Version}), libitm1-dbg (>= ${gcc:Version}), libquadmath0-dbg (>= ${gcc:Version}), libmudflap0-dbg (>= ${gcc:Version}), ${dep:libcloog}, ${dep:gold} Provides: c-compiler Description: GNU C compiler This is the GNU C compiler, a fairly portable optimizing compiler for C. @@ -367,7 +212,7 @@ Priority: optional Depends: gcc-4.7-base (= ${gcc:Version}), gcc-4.7 (= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} Provides: c++-compiler, c++abi2-dev -Suggests: ${gxx:multilib}, gcc-4.7-doc (>= ${gcc:SoftVersion}), libstdc++6-4.7-dbg +Suggests: ${gxx:multilib}, gcc-4.7-doc (>= ${gcc:SoftVersion}), libstdc++6-4.7-dbg (>= ${gcc:Version}) Description: GNU C++ compiler This is the GNU C++ compiler, a fairly portable optimizing compiler for C++. @@ -383,128 +228,6 @@ On architectures with multilib support, the package contains files and dependencies for the non-default multilib architecture(s). -Package: libmudflap0 -Architecture: any -Multi-Arch: same -Pre-Depends: multiarch-support -Breaks: ${multiarch:breaks} -Provides: libmudflap0-armel [armel], libmudflap0-armhf [armhf] -Section: libs -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Description: GCC mudflap shared support libraries - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libmudflap0-dbg -Architecture: any -Multi-Arch: same -Provides: libmudflap0-dbg-armel [armel], libmudflap0-dbg-armhf [armhf] -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libmudflap0 (= ${gcc:Version}), ${misc:Depends} -Description: GCC mudflap shared support libraries (debug symbols) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: lib32mudflap0 -Architecture: amd64 ppc64 kfreebsd-amd64 s390x x32 -Section: libs -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Replaces: libmudflap0 (<< 4.1) -Conflicts: ${confl:lib32} -Description: GCC mudflap shared support libraries (32bit) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: lib32mudflap0-dbg -Architecture: amd64 ppc64 kfreebsd-amd64 s390x x32 -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib32mudflap0 (= ${gcc:Version}), ${misc:Depends} -Description: GCC mudflap shared support libraries (32 bit debug symbols) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: lib64mudflap0 -Architecture: i386 powerpc sparc s390 mips mipsel x32 -Section: libs -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Replaces: libmudflap0 (<< 4.1) -Description: GCC mudflap shared support libraries (64bit) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: lib64mudflap0-dbg -Architecture: i386 powerpc sparc s390 mips mipsel x32 -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib64mudflap0 (= ${gcc:Version}), ${misc:Depends} -Description: GCC mudflap shared support libraries (64 bit debug symbols) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libn32mudflap0 -Architecture: mips mipsel -Section: libs -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Replaces: libmudflap0 (<< 4.1) -Description: GCC mudflap shared support libraries (n32) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libn32mudflap0-dbg -Architecture: mips mipsel -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libn32mudflap0 (= ${gcc:Version}), ${misc:Depends} -Description: GCC mudflap shared support libraries (n32 debug symbols) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libhfmudflap0 -Architecture: armel -Section: libs -Priority: optional -Conflicts: libmudflap0-armhf [armel] -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Description: GCC mudflap shared support libraries (hard float) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libhfmudflap0-dbg -Architecture: armel -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libhfmudflap0 (= ${gcc:Version}), ${misc:Depends} -Conflicts: libmudflap0-dbg-armhf [armel] -Description: GCC mudflap shared support libraries (hard float debug symbols) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libsfmudflap0 -Architecture: armhf -Section: libs -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: libmudflap0-armel [armhf] -Description: GCC mudflap shared support libraries (soft float) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libsfmudflap0-dbg -Architecture: armhf -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libsfmudflap0 (= ${gcc:Version}), ${misc:Depends} -Conflicts: libmudflap0-dbg-armel [armhf] -Description: GCC mudflap shared support libraries (soft float debug symbols) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - Package: libmudflap0-4.7-dev Architecture: any Section: libdevel @@ -518,368 +241,6 @@ . This package contains the headers and the static libraries. -Package: libgomp1 -Section: libs -Architecture: any -Multi-Arch: same -Pre-Depends: multiarch-support -Breaks: ${multiarch:breaks} -Provides: libgomp1-armel [armel], libgomp1-armhf [armhf] -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Description: GCC OpenMP (GOMP) support library - GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers - in the GNU Compiler Collection. - -Package: libgomp1-dbg -Architecture: any -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libgomp1 (= ${gcc:Version}), ${misc:Depends} -Multi-Arch: same -Provides: libgomp1-dbg-armel [armel], libgomp1-dbg-armhf [armhf] -Description: GCC OpenMP (GOMP) support library (debug symbols) - GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers - in the GNU Compiler Collection. - -Package: lib32gomp1 -Section: libs -Architecture: amd64 ppc64 kfreebsd-amd64 s390x x32 -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: ${confl:lib32} -Description: GCC OpenMP (GOMP) support library (32bit) - GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers - in the GNU Compiler Collection. - -Package: lib32gomp1-dbg -Architecture: amd64 ppc64 kfreebsd-amd64 s390x x32 -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib32gomp1 (= ${gcc:Version}), ${misc:Depends} -Description: GCC OpenMP (GOMP) support library (32 bit debug symbols) - GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers - in the GNU Compiler Collection. - -Package: lib64gomp1 -Section: libs -Architecture: i386 powerpc sparc s390 mips mipsel x32 -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Description: GCC OpenMP (GOMP) support library (64bit) - GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers - in the GNU Compiler Collection. - -Package: lib64gomp1-dbg -Architecture: i386 powerpc sparc s390 mips mipsel x32 -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib64gomp1 (= ${gcc:Version}), ${misc:Depends} -Description: GCC OpenMP (GOMP) support library (64bit debug symbols) - GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers - in the GNU Compiler Collection. - -Package: libn32gomp1 -Section: libs -Architecture: mips mipsel -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Description: GCC OpenMP (GOMP) support library (n32) - GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers - in the GNU Compiler Collection. - -Package: libn32gomp1-dbg -Architecture: mips mipsel -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libn32gomp1 (= ${gcc:Version}), ${misc:Depends} -Description: GCC OpenMP (GOMP) support library (n32 debug symbols) - GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers - -Package: libhfgomp1 -Section: libs -Architecture: armel -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: libgomp1-armhf [armel] -Description: GCC OpenMP (GOMP) support library (hard float ABI) - GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers - in the GNU Compiler Collection. - -Package: libhfgomp1-dbg -Architecture: armel -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libhfgomp1 (= ${gcc:Version}), ${misc:Depends} -Conflicts: libgomp1-dbg-armhf [armel] -Description: GCC OpenMP (GOMP) support library (hard float ABI debug symbols) - GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers - -Package: libsfgomp1 -Section: libs -Architecture: armhf -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: libgomp1-armel [armhf] -Description: GCC OpenMP (GOMP) support library (soft float ABI) - GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers - in the GNU Compiler Collection. - -Package: libsfgomp1-dbg -Architecture: armhf -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libsfgomp1 (= ${gcc:Version}), ${misc:Depends} -Conflicts: libgomp1-dbg-armel [armhf] -Description: GCC OpenMP (GOMP) support library (soft float ABI debug symbols) - GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers - -Package: libitm1 -Section: libs -Architecture: any -Multi-Arch: same -Pre-Depends: multiarch-support -Provides: libitm1-armel [armel], libitm1-armhf [armhf] -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Description: GNU Transactional Memory Library - GNU Transactional Memory Library (libitm) provides transaction support for - accesses to the memory of a process, enabling easy-to-use synchronization of - accesses to shared memory by several threads. - -Package: libitm1-dbg -Architecture: any -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libitm1 (= ${gcc:Version}), ${misc:Depends} -Multi-Arch: same -Provides: libitm1-dbg-armel [armel], libitm1-dbg-armhf [armhf] -Description: GNU Transactional Memory Library (debug symbols) - GNU Transactional Memory Library (libitm) provides transaction support for - accesses to the memory of a process, enabling easy-to-use synchronization of - accesses to shared memory by several threads. - -Package: lib32itm1 -Section: libs -Architecture: amd64 ppc64 kfreebsd-amd64 s390x x32 -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: ${confl:lib32} -Description: GNU Transactional Memory Library (32bit) - GNU Transactional Memory Library (libitm) provides transaction support for - accesses to the memory of a process, enabling easy-to-use synchronization of - accesses to shared memory by several threads. - -Package: lib32itm1-dbg -Architecture: amd64 ppc64 kfreebsd-amd64 s390x x32 -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib32itm1 (= ${gcc:Version}), ${misc:Depends} -Description: GNU Transactional Memory Library (32 bit debug symbols) - GNU Transactional Memory Library (libitm) provides transaction support for - accesses to the memory of a process, enabling easy-to-use synchronization of - accesses to shared memory by several threads. - -Package: lib64itm1 -Section: libs -Architecture: i386 powerpc sparc s390 mips mipsel x32 -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Description: GNU Transactional Memory Library (64bit) - GNU Transactional Memory Library (libitm) provides transaction support for - accesses to the memory of a process, enabling easy-to-use synchronization of - accesses to shared memory by several threads. - -Package: lib64itm1-dbg -Architecture: i386 powerpc sparc s390 mips mipsel x32 -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib64itm1 (= ${gcc:Version}), ${misc:Depends} -Description: GNU Transactional Memory Library (64bit debug symbols) - GNU Transactional Memory Library (libitm) provides transaction support for - accesses to the memory of a process, enabling easy-to-use synchronization of - accesses to shared memory by several threads. - -Package: libn32itm1 -Section: libs -Architecture: mips mipsel -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Description: GNU Transactional Memory Library (n32) - GNU Transactional Memory Library (libitm) provides transaction support for - accesses to the memory of a process, enabling easy-to-use synchronization of - accesses to shared memory by several threads. - -Package: libn32itm1-dbg -Architecture: mips mipsel -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libn32itm1 (= ${gcc:Version}), ${misc:Depends} -Description: GNU Transactional Memory Library (n32 debug symbols) - GNU Transactional Memory Library (libitm) provides transaction support for - accesses to the memory of a process, enabling easy-to-use synchronization of - accesses to shared memory by several threads. - -Package: libhfitm1 -Section: libs -Architecture: armel -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: libitm1-armhf [armel] -Description: GNU Transactional Memory Library (hard float ABI) - GNU Transactional Memory Library (libitm) provides transaction support for - accesses to the memory of a process, enabling easy-to-use synchronization of - accesses to shared memory by several threads. - -Package: libhfitm1-dbg -Architecture: armel -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libhfitm1 (= ${gcc:Version}), ${misc:Depends} -Conflicts: libitm1-armel [armhf] -Description: GNU Transactional Memory Library (hard float ABI debug symbols) - GNU Transactional Memory Library (libitm) provides transaction support for - accesses to the memory of a process, enabling easy-to-use synchronization of - accesses to shared memory by several threads. - -Package: libsfitm1 -Section: libs -Architecture: armhf -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Description: GNU Transactional Memory Library (soft float ABI) - GNU Transactional Memory Library (libitm) provides transaction support for - accesses to the memory of a process, enabling easy-to-use synchronization of - accesses to shared memory by several threads. - -Package: libsfitm1-dbg -Architecture: armhf -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libsfitm1 (= ${gcc:Version}), ${misc:Depends} -Description: GNU Transactional Memory Library (soft float ABI debug symbols) - GNU Transactional Memory Library (libitm) provides transaction support for - accesses to the memory of a process, enabling easy-to-use synchronization of - accesses to shared memory by several threads. - -Package: libquadmath0 -Section: libs -Architecture: any -Multi-Arch: same -Pre-Depends: multiarch-support -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Description: GCC Quad-Precision Math Library - A library, which provides quad-precision mathematical functions on targets - supporting the __float128 datatype. The library is used to provide on such - targets the REAL(16) type in the GNU Fortran compiler. - -Package: libquadmath0-dbg -Architecture: any -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libquadmath0 (= ${gcc:Version}), ${misc:Depends} -Multi-Arch: same -Description: GCC Quad-Precision Math Library (debug symbols) - A library, which provides quad-precision mathematical functions on targets - supporting the __float128 datatype. - -Package: lib32quadmath0 -Section: libs -Architecture: amd64 ppc64 kfreebsd-amd64 s390x x32 -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: ${confl:lib32} -Description: GCC Quad-Precision Math Library (32bit) - A library, which provides quad-precision mathematical functions on targets - supporting the __float128 datatype. The library is used to provide on such - targets the REAL(16) type in the GNU Fortran compiler. - -Package: lib32quadmath0-dbg -Architecture: amd64 ppc64 kfreebsd-amd64 s390x x32 -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib32quadmath0 (= ${gcc:Version}), ${misc:Depends} -Description: GCC Quad-Precision Math Library (32 bit debug symbols) - A library, which provides quad-precision mathematical functions on targets - supporting the __float128 datatype. - -Package: lib64quadmath0 -Section: libs -Architecture: i386 powerpc sparc s390 mips mipsel x32 -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Description: GCC Quad-Precision Math Library (64bit) - A library, which provides quad-precision mathematical functions on targets - supporting the __float128 datatype. The library is used to provide on such - targets the REAL(16) type in the GNU Fortran compiler. - -Package: lib64quadmath0-dbg -Architecture: i386 powerpc sparc s390 mips mipsel x32 -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib64quadmath0 (= ${gcc:Version}), ${misc:Depends} -Description: GCC Quad-Precision Math Library (64bit debug symbols) - A library, which provides quad-precision mathematical functions on targets - supporting the __float128 datatype. - -Package: libn32quadmath0 -Section: libs -Architecture: mips mipsel -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Description: GCC Quad-Precision Math Library (n32) - A library, which provides quad-precision mathematical functions on targets - supporting the __float128 datatype. The library is used to provide on such - targets the REAL(16) type in the GNU Fortran compiler. - -Package: libn32quadmath0-dbg -Architecture: mips mipsel -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libn32quadmath0 (= ${gcc:Version}), ${misc:Depends} -Description: GCC Quad-Precision Math Library (n32 debug symbols) - A library, which provides quad-precision mathematical functions on targets - supporting the __float128 datatype. - -Package: libhfquadmath0 -Section: libs -Architecture: armel -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Description: GCC Quad-Precision Math Library (hard float ABI) - A library, which provides quad-precision mathematical functions on targets - supporting the __float128 datatype. The library is used to provide on such - targets the REAL(16) type in the GNU Fortran compiler. - -Package: libhfquadmath0-dbg -Architecture: armel -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libhfquadmath0 (= ${gcc:Version}), ${misc:Depends} -Description: GCC Quad-Precision Math Library (hard float ABI debug symbols) - A library, which provides quad-precision mathematical functions on targets - supporting the __float128 datatype. - -Package: libsfquadmath0 -Section: libs -Architecture: armhf -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Description: GCC Quad-Precision Math Library (soft float ABI) - A library, which provides quad-precision mathematical functions on targets - supporting the __float128 datatype. The library is used to provide on such - targets the REAL(16) type in the GNU Fortran compiler. - -Package: libsfquadmath0-dbg -Architecture: armhf -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libsfquadmath0 (= ${gcc:Version}), ${misc:Depends} -Description: GCC Quad-Precision Math Library (hard float ABI debug symbols) - A library, which provides quad-precision mathematical functions on targets - supporting the __float128 datatype. - Package: gobjc++-4.7 Architecture: any Priority: optional @@ -907,7 +268,7 @@ Architecture: any Priority: optional Depends: gcc-4.7-base (= ${gcc:Version}), gcc-4.7 (= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, libobjc-4.7-dev (= ${gcc:Version}), ${misc:Depends} -Suggests: ${gobjc:multilib}, gcc-4.7-doc (>= ${gcc:SoftVersion}), libobjc4-dbg +Suggests: ${gobjc:multilib}, gcc-4.7-doc (>= ${gcc:SoftVersion}), libobjc4-dbg (>= ${gcc:Version}) Provides: objc-compiler Description: GNU Objective-C compiler This is the GNU Objective-C compiler, which compiles @@ -926,17 +287,6 @@ On architectures with multilib support, the package contains files and dependencies for the non-default multilib architecture(s). -Package: libobjc4 -Section: libs -Architecture: any -Multi-Arch: same -Pre-Depends: multiarch-support -Provides: libobjc4-armel [armel], libobjc4-armhf [armhf] -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Description: Runtime library for GNU Objective-C applications - Library needed for GNU ObjC applications linked against the shared library. - Package: libobjc-4.7-dev Architecture: any Section: libdevel @@ -948,24 +298,6 @@ This package contains the headers and static library files needed to build GNU ObjC applications. -Package: libobjc4-dbg -Section: debug -Architecture: any -Multi-Arch: same -Provides: libobjc4-dbg-armel [armel], libobjc4-dbg-armhf [armhf] -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libobjc4 (= ${gcc:Version}), libgcc1-dbg, ${misc:Depends} -Description: Runtime library for GNU Objective-C applications (debug symbols) - Library needed for GNU ObjC applications linked against the shared library. - -Package: lib64objc4 -Section: libs -Architecture: i386 powerpc sparc s390 mips mipsel x32 -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Description: Runtime library for GNU Objective-C applications (64bit) - Library needed for GNU ObjC applications linked against the shared library. - Package: lib64objc-4.7-dev Architecture: i386 powerpc sparc s390 mips mipsel x32 Section: libdevel @@ -976,23 +308,6 @@ This package contains the headers and static library files needed to build GNU ObjC applications. -Package: lib64objc4-dbg -Section: debug -Architecture: i386 powerpc sparc s390 mips mipsel x32 -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib64objc4 (= ${gcc:Version}), lib64gcc1-dbg, ${misc:Depends} -Description: Runtime library for GNU Objective-C applications (64 bit debug symbols) - Library needed for GNU ObjC applications linked against the shared library. - -Package: lib32objc4 -Section: libs -Architecture: amd64 ppc64 kfreebsd-amd64 s390x x32 -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: ${confl:lib32} -Description: Runtime library for GNU Objective-C applications (32bit) - Library needed for GNU ObjC applications linked against the shared library. - Package: lib32objc-4.7-dev Architecture: amd64 ppc64 kfreebsd-amd64 s390x x32 Section: libdevel @@ -1003,22 +318,6 @@ This package contains the headers and static library files needed to build GNU ObjC applications. -Package: lib32objc4-dbg -Section: debug -Architecture: amd64 ppc64 kfreebsd-amd64 s390x x32 -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib32objc4 (= ${gcc:Version}), lib32gcc1-dbg, ${misc:Depends} -Description: Runtime library for GNU Objective-C applications (32 bit debug symbols) - Library needed for GNU ObjC applications linked against the shared library. - -Package: libn32objc4 -Section: libs -Architecture: mips mipsel -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Description: Runtime library for GNU Objective-C applications (n32) - Library needed for GNU ObjC applications linked against the shared library. - Package: libn32objc-4.7-dev Architecture: mips mipsel Section: libdevel @@ -1029,23 +328,6 @@ This package contains the headers and static library files needed to build GNU ObjC applications. -Package: libn32objc4-dbg -Section: debug -Architecture: mips mipsel -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libn32objc4 (= ${gcc:Version}), libn32gcc1-dbg, ${misc:Depends} -Description: Runtime library for GNU Objective-C applications (n32 debug symbols) - Library needed for GNU ObjC applications linked against the shared library. - -Package: libhfobjc4 -Section: libs -Architecture: armel -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: libobjc4-armhf [armel] -Description: Runtime library for GNU Objective-C applications (hard float ABI) - Library needed for GNU ObjC applications linked against the shared library. - Package: libhfobjc-4.7-dev Architecture: armel Section: libdevel @@ -1056,24 +338,6 @@ This package contains the headers and static library files needed to build GNU ObjC applications. -Package: libhfobjc4-dbg -Section: debug -Architecture: armel -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libhfobjc4 (= ${gcc:Version}), libhfgcc1-dbg, ${misc:Depends} -Conflicts: libobjc4-dbg-armhf [armel] -Description: Runtime library for GNU Objective-C applications (hard float ABI debug symbols) - Library needed for GNU ObjC applications linked against the shared library. - -Package: libsfobjc4 -Section: libs -Architecture: armhf -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: libobjc4-armel [armhf] -Description: Runtime library for GNU Objective-C applications (soft float ABI) - Library needed for GNU ObjC applications linked against the shared library. - Package: libsfobjc-4.7-dev Architecture: armhf Section: libdevel @@ -1084,21 +348,12 @@ This package contains the headers and static library files needed to build GNU ObjC applications. -Package: libsfobjc4-dbg -Section: debug -Architecture: armhf -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libsfobjc4 (= ${gcc:Version}), libsfgcc1-dbg, ${misc:Depends} -Conflicts: libobjc4-dbg-armel [armhf] -Description: Runtime library for GNU Objective-C applications (soft float ABI debug symbols) - Library needed for GNU ObjC applications linked against the shared library. - Package: gfortran-4.7 Architecture: any Priority: optional Depends: gcc-4.7-base (= ${gcc:Version}), gcc-4.7 (= ${gcc:Version}), libgfortran-4.7-dev (= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends} Provides: fortran95-compiler -Suggests: ${gfortran:multilib}, gfortran-4.7-doc, libgfortran3-dbg +Suggests: ${gfortran:multilib}, gfortran-4.7-doc, libgfortran3-dbg (>= ${gcc:Version}) Description: GNU Fortran compiler This is the GNU Fortran compiler, which compiles Fortran on platforms supported by the gcc compiler. It uses the @@ -1124,24 +379,11 @@ Description: Documentation for the GNU Fortran compiler (gfortran) Documentation for the GNU Fortran compiler in info format. -Package: libgfortran3 -Section: libs -Architecture: any -Multi-Arch: same -Pre-Depends: multiarch-support -Breaks: ${multiarch:breaks} -Provides: libgfortran3-armel [armel], libgfortran3-armhf [armhf] -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Description: Runtime library for GNU Fortran applications - Library needed for GNU Fortran applications linked against the - shared library. - Package: libgfortran-4.7-dev Architecture: any Section: libdevel Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), libgfortran3, ${shlibs:Depends}, ${misc:Depends} +Depends: gcc-4.7-base (= ${gcc:Version}), libgfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} Replaces: gfortran-4.7 (<< ${gcc:SplitVersion}) Breaks: gfortran-4.7 (<< ${gcc:SplitVersion}) Multi-Arch: same @@ -1149,26 +391,6 @@ This package contains the headers and static library files needed to build GNU Fortran applications. -Package: libgfortran3-dbg -Section: debug -Architecture: any -Multi-Arch: same -Provides: libgfortran3-dbg-armel [armel], libgfortran3-dbg-armhf [armhf] -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libgfortran3 (= ${gcc:Version}), ${misc:Depends} -Description: Runtime library for GNU Fortran applications (debug symbols) - Library needed for GNU Fortran applications linked against the - shared library. - -Package: lib64gfortran3 -Section: libs -Architecture: i386 powerpc sparc s390 mips mipsel x32 -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Description: Runtime library for GNU Fortran applications (64bit) - Library needed for GNU Fortran applications linked against the - shared library. - Package: lib64gfortran-4.7-dev Architecture: i386 powerpc sparc s390 mips mipsel x32 Section: libdevel @@ -1180,25 +402,6 @@ This package contains the headers and static library files needed to build GNU Fortran applications. -Package: lib64gfortran3-dbg -Section: debug -Architecture: i386 powerpc sparc s390 mips mipsel x32 -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib64gfortran3 (= ${gcc:Version}), ${misc:Depends} -Description: Runtime library for GNU Fortran applications (64bit debug symbols) - Library needed for GNU Fortran applications linked against the - shared library. - -Package: lib32gfortran3 -Section: libs -Architecture: amd64 ppc64 kfreebsd-amd64 s390x x32 -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: ${confl:lib32} -Description: Runtime library for GNU Fortran applications (32bit) - Library needed for GNU Fortran applications linked against the - shared library. - Package: lib32gfortran-4.7-dev Architecture: amd64 ppc64 kfreebsd-amd64 s390x x32 Section: libdevel @@ -1210,24 +413,6 @@ This package contains the headers and static library files needed to build GNU Fortran applications. -Package: lib32gfortran3-dbg -Section: debug -Architecture: amd64 ppc64 kfreebsd-amd64 s390x x32 -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib32gfortran3 (= ${gcc:Version}), ${misc:Depends} -Description: Runtime library for GNU Fortran applications (32 bit debug symbols) - Library needed for GNU Fortran applications linked against the - shared library. - -Package: libn32gfortran3 -Section: libs -Architecture: mips mipsel -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Description: Runtime library for GNU Fortran applications (n32) - Library needed for GNU Fortran applications linked against the - shared library. - Package: libn32gfortran-4.7-dev Architecture: mips mipsel Section: libdevel @@ -1239,25 +424,6 @@ This package contains the headers and static library files needed to build GNU Fortran applications. -Package: libn32gfortran3-dbg -Section: debug -Architecture: mips mipsel -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libn32gfortran3 (= ${gcc:Version}), ${misc:Depends} -Description: Runtime library for GNU Fortran applications (n32 debug symbols) - Library needed for GNU Fortran applications linked against the - shared library. - -Package: libhfgfortran3 -Section: libs -Architecture: armel -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: libgfortran3-armhf [armel] -Description: Runtime library for GNU Fortran applications (hard float ABI) - Library needed for GNU Fortran applications linked against the - shared library. - Package: libhfgfortran-4.7-dev Architecture: armel Section: libdevel @@ -1269,26 +435,6 @@ This package contains the headers and static library files needed to build GNU Fortran applications. -Package: libhfgfortran3-dbg -Section: debug -Architecture: armel -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libhfgfortran3 (= ${gcc:Version}), ${misc:Depends} -Conflicts: libgfortran3-dbg-armhf [armel] -Description: Runtime library for GNU Fortran applications (hard float ABI debug symbols) - Library needed for GNU Fortran applications linked against the - shared library. - -Package: libsfgfortran3 -Section: libs -Architecture: armhf -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: libgfortran3-armel [armhf] -Description: Runtime library for GNU Fortran applications (soft float ABI) - Library needed for GNU Fortran applications linked against the - shared library. - Package: libsfgfortran-4.7-dev Architecture: armhf Section: libdevel @@ -1300,22 +446,12 @@ This package contains the headers and static library files needed to build GNU Fortran applications. -Package: libsfgfortran3-dbg -Section: debug -Architecture: armhf -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libsfgfortran3 (= ${gcc:Version}), ${misc:Depends} -Conflicts: libgfortran3-dbg-armel [armhf] -Description: Runtime library for GNU Fortran applications (hard float ABI debug symbols) - Library needed for GNU Fortran applications linked against the - shared library. - Package: gccgo-4.7 Architecture: any Priority: optional Depends: gcc-4.7-base (= ${gcc:Version}), gcc-4.7 (= ${gcc:Version}), libgo0 (>= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends} Provides: go-compiler -Suggests: ${go:multilib}, gccgo-4.7-doc, libgo0-dbg +Suggests: ${go:multilib}, gccgo-4.7-doc, libgo0-dbg (>= ${gcc:Version}) Replaces: gcc-4.7-doc (<< 4.7.2-11) Description: GNU Go compiler This is the GNU Go compiler, which compiles Go on platforms supported @@ -1420,88 +556,6 @@ Library needed for GNU Go applications linked against the shared library. -Package: libstdc++6 -Architecture: any -Section: libs -Priority: important -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libc}, ${shlibs:Depends}, ${misc:Depends} -Multi-Arch: same -Pre-Depends: multiarch-support -Breaks: ${multiarch:breaks} -Provides: libstdc++6-armel [armel], libstdc++6-armhf [armhf] -Conflicts: scim (<< 1.4.2-1) -Description: GNU Standard C++ Library v3 - This package contains an additional runtime library for C++ programs - built with the GNU compiler. - . - libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which - was included up to g++-2.95. The first version of libstdc++-v3 appeared - in g++-3.0. - -Package: lib32stdc++6 -Architecture: amd64 ppc64 kfreebsd-amd64 s390x x32 -Section: libs -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib32gcc1, ${shlibs:Depends}, ${misc:Depends} -Conflicts: ${confl:lib32} -Description: GNU Standard C++ Library v3 (32 bit Version) - This package contains an additional runtime library for C++ programs - built with the GNU compiler. - -Package: lib64stdc++6 -Architecture: i386 powerpc sparc s390 mips mipsel x32 -Section: libs -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${shlibs:Depends}, lib64gcc1, ${misc:Depends} -Description: GNU Standard C++ Library v3 (64bit) - This package contains an additional runtime library for C++ programs - built with the GNU compiler. - . - libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which - was included up to g++-2.95. The first version of libstdc++-v3 appeared - in g++-3.0. - -Package: libn32stdc++6 -Architecture: mips mipsel -Section: libs -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${shlibs:Depends}, libn32gcc1, ${misc:Depends} -Description: GNU Standard C++ Library v3 (n32) - This package contains an additional runtime library for C++ programs - built with the GNU compiler. - . - libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which - was included up to g++-2.95. The first version of libstdc++-v3 appeared - in g++-3.0. - -Package: libhfstdc++6 -Architecture: armel -Section: libs -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${shlibs:Depends}, libhfgcc1, ${misc:Depends} -Conflicts: libstdc++6-armhf [armel] -Description: GNU Standard C++ Library v3 (hard float ABI) - This package contains an additional runtime library for C++ programs - built with the GNU compiler. - . - libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which - was included up to g++-2.95. The first version of libstdc++-v3 appeared - in g++-3.0. - -Package: libsfstdc++6 -Architecture: armhf -Section: libs -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${shlibs:Depends}, libsfgcc1, ${misc:Depends} -Conflicts: libstdc++6-armel [armhf] -Description: GNU Standard C++ Library v3 (soft float ABI) - This package contains an additional runtime library for C++ programs - built with the GNU compiler. - . - libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which - was included up to g++-2.95. The first version of libstdc++-v3 appeared - in g++-3.0. - Package: libstdc++6-4.7-dev Architecture: any Multi-Arch: same @@ -1536,7 +590,7 @@ Architecture: any Section: debug Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libstdc++6 (>= ${gcc:Version}), libgcc1-dbg, ${shlibs:Depends}, ${misc:Depends} +Depends: gcc-4.7-base (= ${gcc:Version}), libstdc++6 (>= ${gcc:Version}), libgcc1-dbg (>= ${gcc:EpochVersion}), ${shlibs:Depends}, ${misc:Depends} Multi-Arch: same Provides: libstdc++6-4.7-dbg-armel [armel], libstdc++6-4.7-dbg-armhf [armhf] Recommends: libstdc++6-4.7-dev (= ${gcc:Version}) @@ -1564,7 +618,7 @@ Architecture: amd64 ppc64 kfreebsd-amd64 s390x x32 Section: debug Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib32stdc++6 (>= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), lib32gcc1-dbg, ${shlibs:Depends}, ${misc:Depends} +Depends: gcc-4.7-base (= ${gcc:Version}), lib32stdc++6 (>= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), lib32gcc1-dbg (>= ${gcc:EpochVersion}), ${shlibs:Depends}, ${misc:Depends} Conflicts: lib32stdc++6-dbg, lib32stdc++6-4.0-dbg, lib32stdc++6-4.1-dbg, lib32stdc++6-4.2-dbg, lib32stdc++6-4.3-dbg, lib32stdc++6-4.4-dbg, lib32stdc++6-4.5-dbg, lib32stdc++6-4.6-dbg Description: GNU Standard C++ Library v3 (debugging files) This package contains the shared library of libstdc++ compiled with @@ -1589,7 +643,7 @@ Architecture: i386 powerpc sparc s390 mips mipsel x32 Section: debug Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib64stdc++6 (>= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), lib64gcc1-dbg, ${shlibs:Depends}, ${misc:Depends} +Depends: gcc-4.7-base (= ${gcc:Version}), lib64stdc++6 (>= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), lib64gcc1-dbg (>= ${gcc:EpochVersion}), ${shlibs:Depends}, ${misc:Depends} Conflicts: lib64stdc++6-dbg, lib64stdc++6-4.0-dbg, lib64stdc++6-4.1-dbg, lib64stdc++6-4.2-dbg, lib64stdc++6-4.3-dbg, lib64stdc++6-4.4-dbg, lib64stdc++6-4.5-dbg, lib64stdc++6-4.6-dbg Description: GNU Standard C++ Library v3 (debugging files) This package contains the shared library of libstdc++ compiled with @@ -1614,7 +668,7 @@ Architecture: mips mipsel Section: debug Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libn32stdc++6 (>= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), libn32gcc1-dbg, ${shlibs:Depends}, ${misc:Depends} +Depends: gcc-4.7-base (= ${gcc:Version}), libn32stdc++6 (>= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), libn32gcc1-dbg (>= ${gcc:EpochVersion}), ${shlibs:Depends}, ${misc:Depends} Conflicts: libn32stdc++6-dbg, libn32stdc++6-4.0-dbg, libn32stdc++6-4.1-dbg, libn32stdc++6-4.2-dbg, libn32stdc++6-4.3-dbg, libn32stdc++6-4.4-dbg, libn32stdc++6-4.5-dbg, libn32stdc++6-4.6-dbg Description: GNU Standard C++ Library v3 (debugging files) This package contains the shared library of libstdc++ compiled with @@ -1624,7 +678,7 @@ Architecture: armel Section: libdevel Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), libhfgcc-4.7-dev (= ${gcc:Version}), libhfstdc++6 (>= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), ${misc:Depends} +Depends: gcc-4.7-base (= ${gcc:Version}), libhfgcc-4.7-dev (= ${gcc:Version}), libstdc++6 (>= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), ${misc:Depends} Replaces: libstdc++6-4.7-dev (<< ${gcc:SplitVersion}), g++-4.7-multilib (<< ${gcc:SplitVersion}) Breaks: libstdc++6-4.7-dev (<< ${gcc:SplitVersion}), g++-4.7-multilib (<< ${gcc:SplitVersion}) Description: GNU Standard C++ Library v3 (development files) @@ -1639,7 +693,7 @@ Architecture: armel Section: debug Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libhfstdc++6 (>= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), libhfgcc1-dbg, ${shlibs:Depends}, ${misc:Depends} +Depends: gcc-4.7-base (= ${gcc:Version}), libhfstdc++6 (>= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), libhfgcc1-dbg (>= ${gcc:EpochVersion}), ${shlibs:Depends}, ${misc:Depends} Conflicts: libhfstdc++6-dbg, libhfstdc++6-4.3-dbg, libhfstdc++6-4.4-dbg, libhfstdc++6-4.5-dbg, libhfstdc++6-4.6-dbg, libstdc++6-armhf [armel] Description: GNU Standard C++ Library v3 (debugging files) This package contains the shared library of libstdc++ compiled with @@ -1664,7 +718,7 @@ Architecture: armhf Section: debug Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libsfstdc++6 (>= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), libsfgcc1-dbg, ${shlibs:Depends}, ${misc:Depends} +Depends: gcc-4.7-base (= ${gcc:Version}), libsfstdc++6 (>= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), libsfgcc1-dbg (>= ${gcc:EpochVersion}), ${shlibs:Depends}, ${misc:Depends} Conflicts: libsfstdc++6-dbg, libsfstdc++6-4.3-dbg, libsfstdc++6-4.4-dbg, libsfstdc++6-4.5-dbg, libsfstdc++6-4.6-dbg, libstdc++6-armel [armhf] Description: GNU Standard C++ Library v3 (debugging files) This package contains the shared library of libstdc++ compiled with @@ -1693,20 +747,6 @@ These are versions of basic static libraries such as libgcc.a compiled with the -msoft-float option, for CPUs without a floating-point unit. -Package: fixincludes -Architecture: any -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), gcc-4.7 (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Description: Fix non-ANSI header files - FixIncludes was created to fix non-ANSI system header files. Many - system manufacturers supply proprietary headers that are not ANSI compliant. - The GNU compilers cannot compile non-ANSI headers. Consequently, the - FixIncludes shell script was written to fix the header files. - . - Not all packages with header files are installed on the system, when the - package is built, so we make fixincludes available at build time of other - packages, such that checking tools like lintian can make use of it. - Package: gcc-4.7-doc Architecture: all Section: doc diff -Nru gcc-4.7-4.7.2/debian/control.m4 gcc-4.7-4.7.3/debian/control.m4 --- gcc-4.7-4.7.2/debian/control.m4 2013-06-25 15:26:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/control.m4 2013-06-25 15:26:04.000000000 +0000 @@ -20,6 +20,14 @@ define(`ifenabled', `ifelse(index(enabled_languages, `$1'), -1, `dnl', `$2')') +define(`CROSS_ARCH', ifdef(`CROSS_ARCH', CROSS_ARCH, `all')) +define(`libdep', `lib$2$1`'LS`'AQ (ifelse(`$3',`',`>=',`$3') ifelse(`$4',`',`${gcc:Version}',`$4'))') +define(`libdevdep', `lib$2$1`'LS`'AQ (ifelse(`$3',`',`=',`$3') ifelse(`$4',`',`${gcc:Version}',`$4'))') +define(`libdbgdep', `lib$2$1`'LS`'AQ (ifelse(`$3',`',`>=',`$3') ifelse(`$4',`',`${gcc:Version}',`$4'))') + +define(`BUILT_USING', ifelse(add_built_using,yes,`Built-Using: ${Built-Using} +')) + divert`'dnl dnl -------------------------------------------------------------------------- Source: SRCNAME @@ -44,9 +52,26 @@ ')dnl SRCNAME Standards-Version: 3.9.3 ifdef(`TARGET',`dnl cross -Build-Depends: DPKG_BUILD_DEP debhelper (>= 5.0.62), LIBC_BUILD_DEP, LIBC_BIARCH_BUILD_DEP LIBUNWIND_BUILD_DEP LIBATOMIC_OPS_BUILD_DEP AUTOGEN_BUILD_DEP AUTO_BUILD_DEP SOURCE_BUILD_DEP CROSS_BUILD_DEP CLOOG_BUILD_DEP MPC_BUILD_DEP MPFR_BUILD_DEP GMP_BUILD_DEP ELF_BUILD_DEP, zlib1g-dev, gawk, lzma, xz-utils, patchutils, BINUTILS_BUILD_DEP, bison (>= 1:2.3), flex, realpath (>= 1.9.12), lsb-release, make (>= 3.81), quilt +Build-Depends: DPKG_BUILD_DEP debhelper (>= 5.0.62), + LIBC_BUILD_DEP, LIBC_BIARCH_BUILD_DEP + LIBUNWIND_BUILD_DEP LIBATOMIC_OPS_BUILD_DEP AUTOGEN_BUILD_DEP AUTO_BUILD_DEP + SOURCE_BUILD_DEP CROSS_BUILD_DEP + CLOOG_BUILD_DEP MPC_BUILD_DEP MPFR_BUILD_DEP GMP_BUILD_DEP, + zlib1g-dev, gawk, lzma, xz-utils, patchutils, + BINUTILS_BUILD_DEP, + bison (>= 1:2.3), flex, realpath (>= 1.9.12), lsb-release, quilt ',`dnl native -Build-Depends: DPKG_BUILD_DEP debhelper (>= 5.0.62), GCC_MULTILIB_BUILD_DEP LIBC_BUILD_DEP, LIBC_BIARCH_BUILD_DEP AUTO_BUILD_DEP AUTOGEN_BUILD_DEP libunwind7-dev (>= 0.98.5-6) [ia64], libatomic-ops-dev [ia64], zlib1g-dev, gawk, lzma, xz-utils, patchutils, BINUTILS_BUILD_DEP, binutils-hppa64 (>= BINUTILSV) [hppa], gperf (>= 3.0.1), bison (>= 1:2.3), flex, gettext, texinfo (>= 4.3), FORTRAN_BUILD_DEP locales, procps, sharutils, JAVA_BUILD_DEP GNAT_BUILD_DEP GO_BUILD_DEP GDC_BUILD_DEP SPU_BUILD_DEP CLOOG_BUILD_DEP MPC_BUILD_DEP MPFR_BUILD_DEP GMP_BUILD_DEP ELF_BUILD_DEP CHECK_BUILD_DEP realpath (>= 1.9.12), chrpath, lsb-release, make (>= 3.81), quilt +Build-Depends: debhelper (>= 5.0.62), + LIBC_BUILD_DEP, LIBC_BIARCH_BUILD_DEP + AUTO_BUILD_DEP AUTOGEN_BUILD_DEP + libunwind7-dev (>= 0.98.5-6) [ia64], libatomic-ops-dev [ia64], + zlib1g-dev, gawk, lzma, xz-utils, patchutils, + binutils-hppa64 (>= BINUTILSV) [hppa], + gperf (>= 3.0.1), bison (>= 1:2.3), flex, gettext, + texinfo (>= 4.3), locales, sharutils, + procps, FORTRAN_BUILD_DEP JAVA_BUILD_DEP GNAT_BUILD_DEP GO_BUILD_DEP GDC_BUILD_DEP SPU_BUILD_DEP + CLOOG_BUILD_DEP MPC_BUILD_DEP MPFR_BUILD_DEP GMP_BUILD_DEP + CHECK_BUILD_DEP realpath (>= 1.9.12), chrpath, lsb-release, quilt Build-Depends-Indep: LIBSTDCXX_BUILD_INDEP JAVA_BUILD_INDEP ')dnl Build-Conflicts: binutils-gold @@ -105,7 +130,7 @@ Priority: PRI(required) Depends: ${misc:Depends} Replaces: ${base:Replaces} -Breaks: gcj-4.4-base (<< 4.4.6-9~), gnat-4.4-base (<< 4.4.6-3~), gcj-4.6-base (<< 4.6.1-4~), gnat-4.6 (<< 4.6.1-5~), dehydra (<= 0.9.hg20110609-2) +Breaks: gcc-4.4-base (<< 4.4.7), gcj-4.4-base (<< 4.4.6-9~), gnat-4.4-base (<< 4.4.6-3~), gcj-4.6-base (<< 4.6.1-4~), gnat-4.6 (<< 4.6.1-5~), dehydra (<= 0.9.hg20110609-2) Description: GCC, the GNU Compiler Collection (base package) This package contains files common to all languages and libraries contained in the GNU Compiler Collection (GCC). @@ -129,20 +154,46 @@ Section: devel Priority: PRI(extra) Depends: ${misc:Depends} +BUILT_USING`'dnl Description: GCC, the GNU Compiler Collection (base package) This package contains files common to all languages and libraries contained in the GNU Compiler Collection (GCC). ')`'dnl ifenabled(`java',` +ifdef(`TARGET', `', ` +ifenabled(`gcjbase',` Package: gcj`'PV-base Architecture: any +ifdef(`MULTIARCH', `Multi-Arch: same +')`'dnl Section: libs Priority: PRI(optional) Depends: ${misc:Depends} +BUILT_USING`'dnl +Description: GCC, the GNU Compiler Collection (gcj base package) + This package contains files common to all java related packages + built from the GNU Compiler Collection (GCC). +')`'dnl gccbase +')`'dnl native + +ifenabled(`gcjxbase',` +dnl override default base package dependencies to cross version +dnl This creates a toolchain that doesnt depend on the system -base packages +define(`BASETARGET', `PV`'TS') +define(`BASEDEP', `gcj`'BASETARGET-base (= ${gcc:Version})') +define(`SOFTBASEDEP', `gcj`'BASETARGET-base (>= ${gcc:SoftVersion})') + +Package: gcj`'BASETARGET-base +Architecture: any +Section: devel +Priority: PRI(extra) +Depends: ${misc:Depends} +BUILT_USING`'dnl Description: GCC, the GNU Compiler Collection (gcj base package) This package contains files common to all java related packages built from the GNU Compiler Collection (GCC). +')`'dnl ')`'dnl java ifenabled(`ada',` @@ -152,6 +203,7 @@ Priority: PRI(optional) Depends: ${misc:Depends} Breaks: gcc-4.6 (<< 4.6.1-8~) +BUILT_USING`'dnl Description: GNU Ada compiler (common files) GNAT is a compiler for the Ada programming language. It produces optimized code on platforms supported by the GNU Compiler Collection (GCC). @@ -161,7 +213,7 @@ ifenabled(`libgcc',` Package: libgcc1`'LS -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',required) Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} @@ -170,6 +222,7 @@ Pre-Depends: multiarch-support Breaks: ${multiarch:breaks} ')`Provides: libgcc1-armel [armel], libgcc1-armhf [armhf]') +BUILT_USING`'dnl Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') Shared version of the support library, a library of internal subroutines that GCC uses to overcome shortcomings of particular machines, or @@ -180,29 +233,17 @@ environment. ')`'dnl -Package: libgcc`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`any') -Section: libdevel -Priority: optional -Recommends: ${dep:libcdev} -Depends: BASEDEP, ${dep:libgcc}, ${dep:libssp}, ${dep:libgomp}, ${dep:libitm}, ${dep:libqmath}, ${dep:libunwinddev}, ${shlibs:Depends}, ${misc:Depends} -Replaces: gcc`'PV (<< ${gcc:SplitVersion}) -ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same -'))`'dnl -Description: GCC support library (development files) - This package contains the headers and static library files necessary for - building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. - Package: libgcc1-dbg`'LS -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') Section: debug Priority: extra -Depends: BASEDEP, libgcc1`'LS (= ${gcc:EpochVersion}), ${misc:Depends} +Depends: BASEDEP, libdep(gcc1,,=,${gcc:EpochVersion}), ${misc:Depends} ifdef(`TARGET',`',`dnl ifdef(`MULTIARCH',`Multi-Arch: same ')dnl Provides: libgcc1-dbg-armel [armel], libgcc1-dbg-armhf [armhf] ')dnl +BUILT_USING`'dnl Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `') Debug symbols for the GCC support library. ifdef(`TARGET', `dnl @@ -212,7 +253,7 @@ ')`'dnl Package: libgcc2`'LS -Architecture: ifdef(`TARGET',`all',`m68k') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`m68k') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',required) Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} @@ -221,6 +262,7 @@ Pre-Depends: multiarch-support Breaks: ${multiarch:breaks} '))`'dnl +BUILT_USING`'dnl Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') Shared version of the support library, a library of internal subroutines that GCC uses to overcome shortcomings of particular machines, or @@ -232,12 +274,13 @@ ')`'dnl Package: libgcc2-dbg`'LS -Architecture: ifdef(`TARGET',`all',`m68k') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`m68k') Section: debug Priority: extra -Depends: BASEDEP, libgcc2`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(gcc2,,=,${gcc:EpochVersion}), ${misc:Depends} ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same '))`'dnl +BUILT_USING`'dnl Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `') Debug symbols for the GCC support library. ifdef(`TARGET', `dnl @@ -247,9 +290,25 @@ ')`'dnl ')`'dnl libgcc +ifenabled(`cdev',` +Package: libgcc`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') +Section: libdevel +Priority: optional +Recommends: ${dep:libcdev} +Depends: BASEDEP, ${dep:libgcc}, ${dep:libssp}, ${dep:libgomp}, ${dep:libitm}, ${dep:libqmath}, ${dep:libunwinddev}, ${shlibs:Depends}, ${misc:Depends} +Replaces: gcc`'PV (<< ${gcc:SplitVersion}) +ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same +'))`'dnl +BUILT_USING`'dnl +Description: GCC support library (development files) + This package contains the headers and static library files necessary for + building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. +')`'dnl cdev + ifenabled(`lib4gcc',` Package: libgcc4`'LS -Architecture: ifdef(`TARGET',`all',`hppa') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`hppa') ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same Pre-Depends: multiarch-support Breaks: ${multiarch:breaks} @@ -257,6 +316,7 @@ Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',required) Depends: ifdef(`STANDALONEJAVA',`gcj`'PV-base (>= ${gcj:Version})',`BASEDEP'), ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') Shared version of the support library, a library of internal subroutines that GCC uses to overcome shortcomings of particular machines, or @@ -268,12 +328,13 @@ ')`'dnl Package: libgcc4-dbg`'LS -Architecture: ifdef(`TARGET',`all',`hppa') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`hppa') ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same '))`'dnl Section: debug Priority: extra -Depends: BASEDEP, libgcc4`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(gcc4,,=,${gcc:EpochVersion}), ${misc:Depends} +BUILT_USING`'dnl Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `') Debug symbols for the GCC support library. ifdef(`TARGET', `dnl @@ -285,13 +346,14 @@ ifenabled(`lib64gcc',` Package: lib64gcc1`'LS -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${dep:libcbiarch}, ${misc:Depends} ifdef(`TARGET',`Provides: lib64gcc1-TARGET-dcv1 ',`')`'dnl Conflicts: libgcc`'GCC_SO`'LS (<= 1:3.3-0pre9) +BUILT_USING`'dnl Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') (64bit) Shared version of the support library, a library of internal subroutines that GCC uses to overcome shortcomings of particular machines, or @@ -302,22 +364,12 @@ environment. ')`'dnl -Package: lib64gcc`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`biarch64_archs') -Section: libdevel -Priority: optional -Recommends: ${dep:libcdev} -Depends: BASEDEP, ${dep:libgccbiarch}, ${dep:libsspbiarch}, ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends} -Replaces: gcc`'PV-multilib (<< ${gcc:SplitVersion}) -Description: GCC support library (64bit development files) - This package contains the headers and static library files necessary for - building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. - Package: lib64gcc1-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Section: debug Priority: extra -Depends: BASEDEP, lib64gcc1`'LS (= ${gcc:EpochVersion}), ${misc:Depends} +Depends: BASEDEP, libdep(gcc1,64,=,${gcc:EpochVersion}), ${misc:Depends} +BUILT_USING`'dnl Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `') Debug symbols for the GCC support library. ifdef(`TARGET', `dnl @@ -327,15 +379,30 @@ ')`'dnl ')`'dnl lib64gcc +ifenabled(`cdev',` +Package: lib64gcc`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') +Section: libdevel +Priority: optional +Recommends: ${dep:libcdev} +Depends: BASEDEP, ${dep:libgccbiarch}, ${dep:libsspbiarch}, ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends} +Replaces: gcc`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: GCC support library (64bit development files) + This package contains the headers and static library files necessary for + building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. +')`'dnl cdev + ifenabled(`lib32gcc',` Package: lib32gcc1`'LS -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: extra Depends: BASEDEP, ${dep:libcbiarch}, ${misc:Depends} Conflicts: ${confl:lib32} ifdef(`TARGET',`Provides: lib32gcc1-TARGET-dcv1 ',`')`'dnl +BUILT_USING`'dnl Description: GCC support library (32 bit Version) Shared version of the support library, a library of internal subroutines that GCC uses to overcome shortcomings of particular machines, or @@ -346,22 +413,12 @@ environment. ')`'dnl -Package: lib32gcc`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`biarch32_archs') -Section: libdevel -Priority: optional -Recommends: ${dep:libcdev} -Depends: BASEDEP, ${dep:libgccbiarch}, ${dep:libsspbiarch}, ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends} -Replaces: gcc`'PV-multilib (<< ${gcc:SplitVersion}) -Description: GCC support library (32 bit development files) - This package contains the headers and static library files necessary for - building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. - Package: lib32gcc1-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Section: debug Priority: extra -Depends: BASEDEP, lib32gcc1`'LS (= ${gcc:EpochVersion}), ${misc:Depends} +Depends: BASEDEP, libdep(gcc1,32,=,${gcc:EpochVersion}), ${misc:Depends} +BUILT_USING`'dnl Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `') Debug symbols for the GCC support library. ifdef(`TARGET', `dnl @@ -371,12 +428,27 @@ ')`'dnl ')`'dnl lib32gcc1 +ifenabled(`cdev',` +Package: lib32gcc`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') +Section: libdevel +Priority: optional +Recommends: ${dep:libcdev} +Depends: BASEDEP, ${dep:libgccbiarch}, ${dep:libsspbiarch}, ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends} +Replaces: gcc`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: GCC support library (32 bit development files) + This package contains the headers and static library files necessary for + building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. +')`'dnl cdev + ifenabled(`libneongcc',` Package: libgcc1-neon`'LS Architecture: NEON_ARCHS Section: libs Priority: extra Depends: BASEDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC support library [neon optimized] Shared version of the support library, a library of internal subroutines that GCC uses to overcome shortcomings of particular machines, or @@ -388,13 +460,14 @@ ifenabled(`libhfgcc',` Package: libhfgcc1`'LS -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${dep:libcbiarch}, ${misc:Depends} ifdef(`TARGET',`Provides: libhfgcc1-TARGET-dcv1 ',`Conflicts: libgcc1-armhf [biarchhf_archs] ')`'dnl +BUILT_USING`'dnl Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') (hard float ABI) Shared version of the support library, a library of internal subroutines that GCC uses to overcome shortcomings of particular machines, or @@ -405,23 +478,13 @@ environment. ')`'dnl -Package: libhfgcc`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') -Section: libdevel -Priority: optional -Recommends: ${dep:libcdev} -Depends: BASEDEP, ${dep:libgccbiarch}, ${dep:libsspbiarch}, ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends} -Replaces: gcc`'PV-multilib (<< ${gcc:SplitVersion}) -Description: GCC support library (hard float ABI development files) - This package contains the headers and static library files necessary for - building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. - Package: libhfgcc1-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Section: debug Priority: extra -Depends: BASEDEP, libhfgcc1`'LS (= ${gcc:EpochVersion}), ${misc:Depends} +Depends: BASEDEP, libdep(gcc1,hf,=,${gcc:EpochVersion}), ${misc:Depends} ifdef(`TARGET',`dnl',`Conflicts: libgcc1-dbg-armhf [biarchhf_archs]') +BUILT_USING`'dnl Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `') Debug symbols for the GCC support library. ifdef(`TARGET', `dnl @@ -431,15 +494,32 @@ ')`'dnl ')`'dnl libhfgcc +ifenabled(`cdev',` +ifenabled(`armml',` +Package: libhfgcc`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') +Section: libdevel +Priority: optional +Recommends: ${dep:libcdev} +Depends: BASEDEP, ${dep:libgccbiarch}, ${dep:libsspbiarch}, ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends} +Replaces: gcc`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: GCC support library (hard float ABI development files) + This package contains the headers and static library files necessary for + building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. +')`'dnl armml +')`'dnl cdev + ifenabled(`libsfgcc',` Package: libsfgcc1`'LS -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${dep:libcbiarch}, ${misc:Depends} ifdef(`TARGET',`Provides: libsfgcc1-TARGET-dcv1 ',`Conflicts: libgcc1-armel [biarchsf_archs] ')`'dnl +BUILT_USING`'dnl Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') (soft float ABI) Shared version of the support library, a library of internal subroutines that GCC uses to overcome shortcomings of particular machines, or @@ -450,23 +530,13 @@ environment. ')`'dnl -Package: libsfgcc`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') -Section: libdevel -Priority: optional -Recommends: ${dep:libcdev} -Depends: BASEDEP, ${dep:libgccbiarch}, ${dep:libsspbiarch}, ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends} -Replaces: gcc`'PV-multilib (<< ${gcc:SplitVersion}) -Description: GCC support library (soft float ABI development files) - This package contains the headers and static library files necessary for - building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. - Package: libsfgcc1-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Section: debug Priority: extra -Depends: BASEDEP, libsfgcc1`'LS (= ${gcc:EpochVersion}), ${misc:Depends} +Depends: BASEDEP, libdep(gcc1,sf,=,${gcc:EpochVersion}), ${misc:Depends} ifdef(`TARGET',`dnl',`Conflicts: libgcc1-dbg-armel [biarchsf_archs]') +BUILT_USING`'dnl Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `') Debug symbols for the GCC support library. ifdef(`TARGET', `dnl @@ -476,15 +546,32 @@ ')`'dnl ')`'dnl libsfgcc +ifenabled(`cdev',` +ifenabled(`armml',` +Package: libsfgcc`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') +Section: libdevel +Priority: optional +Recommends: ${dep:libcdev} +Depends: BASEDEP, ${dep:libgccbiarch}, ${dep:libsspbiarch}, ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends} +Replaces: gcc`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: GCC support library (soft float ABI development files) + This package contains the headers and static library files necessary for + building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. +')`'dnl armml +')`'dnl cdev + ifenabled(`libn32gcc',` Package: libn32gcc1`'LS -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${dep:libcbiarch}, ${misc:Depends} ifdef(`TARGET',`Provides: libn32gcc1-TARGET-dcv1 ',`')`'dnl Conflicts: libgcc`'GCC_SO`'LS (<= 1:3.3-0pre9) +BUILT_USING`'dnl Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') (n32) Shared version of the support library, a library of internal subroutines that GCC uses to overcome shortcomings of particular machines, or @@ -495,22 +582,12 @@ environment. ')`'dnl -Package: libn32gcc`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') -Section: libdevel -Priority: optional -Recommends: ${dep:libcdev} -Depends: BASEDEP, ${dep:libgccbiarch}, ${dep:libsspbiarch}, ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends} -Replaces: gcc`'PV-multilib (<< ${gcc:SplitVersion}) -Description: GCC support library (n32 development files) - This package contains the headers and static library files necessary for - building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. - Package: libn32gcc1-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Section: debug Priority: extra -Depends: BASEDEP, libn32gcc1`'LS (= ${gcc:EpochVersion}), ${misc:Depends} +Depends: BASEDEP, libdep(gcc1,n32,=,${gcc:EpochVersion}), ${misc:Depends} +BUILT_USING`'dnl Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `') Debug symbols for the GCC support library. ifdef(`TARGET', `dnl @@ -520,14 +597,29 @@ ')`'dnl ')`'dnl libn32gcc +ifenabled(`cdev',` +Package: libn32gcc`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') +Section: libdevel +Priority: optional +Recommends: ${dep:libcdev} +Depends: BASEDEP, ${dep:libgccbiarch}, ${dep:libsspbiarch}, ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends} +Replaces: gcc`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: GCC support library (n32 development files) + This package contains the headers and static library files necessary for + building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. +')`'dnl cdev + ifenabled(`libx32gcc',` Package: libx32gcc1`'LS -Architecture: ifdef(`TARGET',`all',`biarchx32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${dep:libcbiarch}, ${misc:Depends} ifdef(`TARGET',`Provides: libx32gcc1-TARGET-dcv1 ',`')`'dnl +BUILT_USING`'dnl Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') (x32) Shared version of the support library, a library of internal subroutines that GCC uses to overcome shortcomings of particular machines, or @@ -538,22 +630,12 @@ environment. ')`'dnl -Package: libx32gcc`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`biarchx32_archs') -Section: libdevel -Priority: optional -Recommends: ${dep:libcdev} -Depends: BASEDEP, ${dep:libgccbiarch}, ${dep:libsspbiarch}, ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends} -Replaces: gcc`'PV-multilib (<< ${gcc:SplitVersion}) -Description: GCC support library (x32 development files) - This package contains the headers and static library files necessary for - building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. - Package: libx32gcc1-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchx32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') Section: debug Priority: extra -Depends: BASEDEP, libx32gcc1`'LS (= ${gcc:EpochVersion}), ${misc:Depends} +Depends: BASEDEP, libdep(gcc1,x32,=,${gcc:EpochVersion}), ${misc:Depends} +BUILT_USING`'dnl Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `') Debug symbols for the GCC support library. ifdef(`TARGET', `dnl @@ -561,6 +643,20 @@ This package contains files for TARGET architecture, for use in cross-compile environment. ')`'dnl + +ifenabled(`cdev',` +Package: libx32gcc`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') +Section: libdevel +Priority: optional +Recommends: ${dep:libcdev} +Depends: BASEDEP, ${dep:libgccbiarch}, ${dep:libsspbiarch}, ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends} +Replaces: gcc`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: GCC support library (x32 development files) + This package contains the headers and static library files necessary for + building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. +')`'dnl cdev ')`'dnl libx32gcc ifdef(`TARGET', `', ` @@ -573,6 +669,7 @@ Section: libs Priority: PRI(optional) Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC math support library Support library for GCC. @@ -581,6 +678,7 @@ Section: libs Priority: PRI(optional) Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC math support library (32bit) Support library for GCC. @@ -589,6 +687,7 @@ Section: libs Priority: PRI(optional) Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC math support library (64bit) Support library for GCC. ')`'dnl @@ -599,10 +698,11 @@ Architecture: any Section: devel Priority: ifdef(`TARGET',`extra',`PRI(optional)') -Depends: BASEDEP, cpp`'PV`'TS (= ${gcc:Version}), binutils`'TS (>= ${binutils:Version}), libgcc`'PV-dev`'LS (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, cpp`'PV`'TS (= ${gcc:Version}), binutils`'TS (>= ${binutils:Version}), libdevdep(gcc`'PV-dev,,=), ${shlibs:Depends}, ${misc:Depends} Recommends: ${dep:libcdev} -Suggests: ${gcc:multilib}, libmudflap`'MF_SO`'PV-dev`'LS (>= ${gcc:Version}), gcc`'PV-doc (>= ${gcc:SoftVersion}), gcc`'PV-locales (>= ${gcc:SoftVersion}), libgcc`'GCC_SO-dbg`'LS, libgomp`'GOMP_SO-dbg`'LS, libitm`'ITM_SO-dbg`'LS, libquadmath`'QMATH_SO-dbg`'LS, libmudflap`'MF_SO-dbg`'LS, ${dep:libcloog}, ${dep:gold} +Suggests: ${gcc:multilib}, libdevdep(mudflap`'MF_SO`'PV-dev,,>=,${gcc:Version}), gcc`'PV-doc (>= ${gcc:SoftVersion}), gcc`'PV-locales (>= ${gcc:SoftVersion}), libdbgdep(gcc`'GCC_SO-dbg,,>=,${gcc:EpochVersion}), libdbgdep(gomp`'GOMP_SO-dbg), libdbgdep(itm`'ITM_SO-dbg), libdbgdep(quadmath`'QMATH_SO-dbg,), libdbgdep(mudflap`'MF_SO-dbg,), ${dep:libcloog}, ${dep:gold} Provides: c-compiler`'TS +BUILT_USING`'dnl Description: GNU C compiler`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `') This is the GNU C compiler, a fairly portable optimizing compiler for C. ifdef(`TARGET', `dnl @@ -617,6 +717,7 @@ Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), ${dep:libcbiarchdev}, ${dep:libgccbiarchdev}, ${shlibs:Depends}, ${misc:Depends} Suggests: ${dep:libmudflapbiarch} +BUILT_USING`'dnl Description: GNU C compiler (multilib files)`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `') This is the GNU C compiler, a fairly portable optimizing compiler for C. . @@ -630,6 +731,7 @@ Section: devel Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), GMP_BUILD_DEP ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: Files for GNU GCC plugin development. This package contains (header) files for GNU GCC plugin development. It is only used for the development of GCC plugins, but not needed to run @@ -644,6 +746,7 @@ Priority: PRI(optional) Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} Conflicts: gcc-3.3-hppa64 (<= 1:3.3.4-5), gcc-3.4-hppa64 (<= 3.4.1-3) +BUILT_USING`'dnl Description: GNU C compiler (cross compiler for hppa64) This is the GNU C compiler, a fairly portable optimizing compiler for C. @@ -654,6 +757,7 @@ Priority: PRI(optional) Depends: BASEDEP, binutils-spu (>= 2.18.1~cvs20080103-3), newlib-spu, ${shlibs:Depends}, ${misc:Depends} Provides: spu-gcc +BUILT_USING`'dnl Description: SPU cross-compiler (preprocessor and C compiler) GNU Compiler Collection for the Cell Broadband Engine SPU (preprocessor and C compiler). @@ -664,6 +768,7 @@ Priority: PRI(optional) Depends: BASEDEP, gcc`'PV-spu (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} Provides: spu-g++ +BUILT_USING`'dnl Description: SPU cross-compiler (C++ compiler) GNU Compiler Collection for the Cell Broadband Engine SPU (C++ compiler). @@ -673,6 +778,7 @@ Priority: PRI(optional) Depends: BASEDEP, gcc`'PV-spu (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} Provides: spu-gfortran +BUILT_USING`'dnl Description: SPU cross-compiler (Fortran compiler) GNU Compiler Collection for the Cell Broadband Engine SPU (Fortran compiler). @@ -687,6 +793,7 @@ Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} Suggests: gcc`'PV-locales (>= ${gcc:SoftVersion}) Replaces: gcc-4.6 (<< 4.6.1-9) +BUILT_USING`'dnl Description: GNU C preprocessor A macro processor that is used automatically by the GNU C compiler to transform programs before actual compilation. @@ -732,9 +839,10 @@ Architecture: any Section: devel Priority: ifdef(`TARGET',`extra',`PRI(optional)') -Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), libstdc++CXX_SO`'PV-dev`'LS (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), libdevdep(stdc++CXX_SO`'PV-dev,,=,${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} Provides: c++-compiler`'TS`'ifdef(`TARGET)',`',`, c++abi2-dev') -Suggests: ${gxx:multilib}, gcc`'PV-doc (>= ${gcc:SoftVersion}), libstdc++CXX_SO`'PV-dbg`'LS +Suggests: ${gxx:multilib}, gcc`'PV-doc (>= ${gcc:SoftVersion}), libdbgdep(stdc++CXX_SO`'PV-dbg,) +BUILT_USING`'dnl Description: GNU C++ compiler`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `') This is the GNU C++ compiler, a fairly portable optimizing compiler for C++. ifdef(`TARGET', `dnl @@ -749,6 +857,7 @@ Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, g++`'PV`'TS (= ${gcc:Version}), gcc`'PV-multilib`'TS (= ${gcc:Version}), ${dep:libcxxbiarchdev}, ${shlibs:Depends}, ${misc:Depends} Suggests: ${dep:libcxxbiarchdbg} +BUILT_USING`'dnl Description: GNU C++ compiler (multilib files)`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `') This is the GNU C++ compiler, a fairly portable optimizing compiler for C++. . @@ -761,7 +870,7 @@ ifenabled(`mudflap',` ifenabled(`libmudf',` Package: libmudflap`'MF_SO`'LS -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') ifdef(`TARGET',`dnl',ifdef(`MULTIARCH', `Multi-Arch: same Pre-Depends: multiarch-support Breaks: ${multiarch:breaks} @@ -769,95 +878,105 @@ Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC mudflap shared support libraries The libmudflap libraries are used by GCC for instrumenting pointer and array dereferencing operations. Package: libmudflap`'MF_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') ifdef(`TARGET',`dnl',ifdef(`MULTIARCH', `Multi-Arch: same ')`Provides: libmudflap'MF_SO`-dbg-armel [armel], libmudflap'MF_SO`-dbg-armhf [armhf]') Section: debug Priority: extra -Depends: BASEDEP, libmudflap`'MF_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(mudflap`'MF_SO,,=), ${misc:Depends} +BUILT_USING`'dnl Description: GCC mudflap shared support libraries (debug symbols) The libmudflap libraries are used by GCC for instrumenting pointer and array dereferencing operations. Package: lib32mudflap`'MF_SO`'LS -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Replaces: libmudflap0 (<< 4.1) Conflicts: ${confl:lib32} +BUILT_USING`'dnl Description: GCC mudflap shared support libraries (32bit) The libmudflap libraries are used by GCC for instrumenting pointer and array dereferencing operations. Package: lib32mudflap`'MF_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Section: debug Priority: extra -Depends: BASEDEP, lib32mudflap`'MF_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(mudflap`'MF_SO,32,=), ${misc:Depends} +BUILT_USING`'dnl Description: GCC mudflap shared support libraries (32 bit debug symbols) The libmudflap libraries are used by GCC for instrumenting pointer and array dereferencing operations. Package: lib64mudflap`'MF_SO`'LS -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Replaces: libmudflap0 (<< 4.1) +BUILT_USING`'dnl Description: GCC mudflap shared support libraries (64bit) The libmudflap libraries are used by GCC for instrumenting pointer and array dereferencing operations. Package: lib64mudflap`'MF_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Section: debug Priority: extra -Depends: BASEDEP, lib64mudflap`'MF_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(mudflap`'MF_SO,64,=), ${misc:Depends} +BUILT_USING`'dnl Description: GCC mudflap shared support libraries (64 bit debug symbols) The libmudflap libraries are used by GCC for instrumenting pointer and array dereferencing operations. Package: libn32mudflap`'MF_SO`'LS -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Replaces: libmudflap0 (<< 4.1) +BUILT_USING`'dnl Description: GCC mudflap shared support libraries (n32) The libmudflap libraries are used by GCC for instrumenting pointer and array dereferencing operations. Package: libn32mudflap`'MF_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Section: debug Priority: extra -Depends: BASEDEP, libn32mudflap`'MF_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(mudflap`'MF_SO,n32,=), ${misc:Depends} +BUILT_USING`'dnl Description: GCC mudflap shared support libraries (n32 debug symbols) The libmudflap libraries are used by GCC for instrumenting pointer and array dereferencing operations. ifenabled(`libx32mudflap',` Package: libx32mudflap`'MF_SO`'LS -Architecture: ifdef(`TARGET',`all',`biarchx32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Replaces: libmudflap0 (<< 4.1) +BUILT_USING`'dnl Description: GCC mudflap shared support libraries (x32) The libmudflap libraries are used by GCC for instrumenting pointer and array dereferencing operations. Package: libx32mudflap`'MF_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchx32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') Section: debug Priority: extra -Depends: BASEDEP, libx32mudflap`'MF_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(mudflap`'MF_SO,x32,=), ${misc:Depends} +BUILT_USING`'dnl Description: GCC mudflap shared support libraries (x32 debug symbols) The libmudflap libraries are used by GCC for instrumenting pointer and array dereferencing operations. @@ -865,21 +984,23 @@ ifenabled(`libhfmudflap',` Package: libhfmudflap`'MF_SO`'LS -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') ifdef(`TARGET',`dnl',`Conflicts: libmudflap`'MF_SO`'-armhf [biarchhf_archs]') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC mudflap shared support libraries (hard float) The libmudflap libraries are used by GCC for instrumenting pointer and array dereferencing operations. Package: libhfmudflap`'MF_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Section: debug Priority: extra -Depends: BASEDEP, libhfmudflap`'MF_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(mudflap`'MF_SO,hf,=), ${misc:Depends} ifdef(`TARGET',`dnl',`Conflicts: libmudflap`'MF_SO`'-dbg-armhf [biarchhf_archs]') +BUILT_USING`'dnl Description: GCC mudflap shared support libraries (hard float debug symbols) The libmudflap libraries are used by GCC for instrumenting pointer and array dereferencing operations. @@ -887,21 +1008,23 @@ ifenabled(`libsfmudflap',` Package: libsfmudflap`'MF_SO`'LS -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} ifdef(`TARGET',`dnl',`Conflicts: libmudflap`'MF_SO`'-armel [biarchsf_archs]') +BUILT_USING`'dnl Description: GCC mudflap shared support libraries (soft float) The libmudflap libraries are used by GCC for instrumenting pointer and array dereferencing operations. Package: libsfmudflap`'MF_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Section: debug Priority: extra -Depends: BASEDEP, libsfmudflap`'MF_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(mudflap`'MF_SO,sf,=), ${misc:Depends} ifdef(`TARGET',`dnl',`Conflicts: libmudflap`'MF_SO`'-dbg-armel [biarchsf_archs]') +BUILT_USING`'dnl Description: GCC mudflap shared support libraries (soft float debug symbols) The libmudflap libraries are used by GCC for instrumenting pointer and array dereferencing operations. @@ -909,12 +1032,13 @@ ')`'dnl libmudf Package: libmudflap`'MF_SO`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') Section: ifdef(`TARGET',`devel',`libdevel') Priority: ifdef(`TARGET',`extra',`PRI(optional)') -Depends: BASEDEP, libmudflap`'MF_SO`'LS (>= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, libdevdep(mudflap`'MF_SO,,>=,${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends} Suggests: ${sug:libmudflapdev} Conflicts: libmudflap0-dev +BUILT_USING`'dnl Description: GCC mudflap support libraries (development files) The libmudflap libraries are used by GCC for instrumenting pointer and array dereferencing operations. @@ -932,6 +1056,7 @@ Section: libs Priority: PRI(optional) Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC stack smashing protection library GCC can now emit code for protecting applications from stack-smashing attacks. The protection is realized by buffer overflow detection and reordering of @@ -944,6 +1069,7 @@ Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Replaces: libssp0 (<< 4.1) Conflicts: ${confl:lib32} +BUILT_USING`'dnl Description: GCC stack smashing protection library (32bit) GCC can now emit code for protecting applications from stack-smashing attacks. The protection is realized by buffer overflow detection and reordering of @@ -955,6 +1081,7 @@ Priority: PRI(optional) Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Replaces: libssp0 (<< 4.1) +BUILT_USING`'dnl Description: GCC stack smashing protection library (64bit) GCC can now emit code for protecting applications from stack-smashing attacks. The protection is realized by buffer overflow detection and reordering of @@ -966,6 +1093,7 @@ Priority: PRI(optional) Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Replaces: libssp0 (<< 4.1) +BUILT_USING`'dnl Description: GCC stack smashing protection library (n32) GCC can now emit code for protecting applications from stack-smashing attacks. The protection is realized by buffer overflow detection and reordering of @@ -977,6 +1105,7 @@ Priority: PRI(optional) Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Replaces: libssp0 (<< 4.1) +BUILT_USING`'dnl Description: GCC stack smashing protection library (x32) GCC can now emit code for protecting applications from stack-smashing attacks. The protection is realized by buffer overflow detection and reordering of @@ -987,6 +1116,7 @@ Section: libs Priority: PRI(optional) Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC stack smashing protection library (hard float ABI) GCC can now emit code for protecting applications from stack-smashing attacks. The protection is realized by buffer overflow detection and reordering of @@ -997,6 +1127,7 @@ Section: libs Priority: PRI(optional) Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC stack smashing protection library (soft float ABI) GCC can now emit code for protecting applications from stack-smashing attacks. The protection is realized by buffer overflow detection and reordering of @@ -1007,97 +1138,107 @@ ifenabled(`libgomp',` Package: libgomp`'GOMP_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') ifdef(`TARGET',`dnl',ifdef(`MULTIARCH', `Multi-Arch: same Pre-Depends: multiarch-support Breaks: ${multiarch:breaks} ')`Provides: libgomp'GOMP_SO`-armel [armel], libgomp'GOMP_SO`-armhf [armhf]') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC OpenMP (GOMP) support library GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers in the GNU Compiler Collection. Package: libgomp`'GOMP_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') Section: debug Priority: extra -Depends: BASEDEP, libgomp`'GOMP_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(gomp`'GOMP_SO,,=), ${misc:Depends} ifdef(`TARGET',`dnl',ifdef(`MULTIARCH', `Multi-Arch: same ')`Provides: libgomp'GOMP_SO`-dbg-armel [armel], libgomp'GOMP_SO`-dbg-armhf [armhf]') +BUILT_USING`'dnl Description: GCC OpenMP (GOMP) support library (debug symbols) GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers in the GNU Compiler Collection. Package: lib32gomp`'GOMP_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Conflicts: ${confl:lib32} +BUILT_USING`'dnl Description: GCC OpenMP (GOMP) support library (32bit) GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers in the GNU Compiler Collection. Package: lib32gomp`'GOMP_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Section: debug Priority: extra -Depends: BASEDEP, lib32gomp`'GOMP_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(gomp`'GOMP_SO,32,=), ${misc:Depends} +BUILT_USING`'dnl Description: GCC OpenMP (GOMP) support library (32 bit debug symbols) GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers in the GNU Compiler Collection. Package: lib64gomp`'GOMP_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC OpenMP (GOMP) support library (64bit) GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers in the GNU Compiler Collection. Package: lib64gomp`'GOMP_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Section: debug Priority: extra -Depends: BASEDEP, lib64gomp`'GOMP_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(gomp`'GOMP_SO,64,=), ${misc:Depends} +BUILT_USING`'dnl Description: GCC OpenMP (GOMP) support library (64bit debug symbols) GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers in the GNU Compiler Collection. Package: libn32gomp`'GOMP_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC OpenMP (GOMP) support library (n32) GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers in the GNU Compiler Collection. Package: libn32gomp`'GOMP_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Section: debug Priority: extra -Depends: BASEDEP, libn32gomp`'GOMP_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(gomp`'GOMP_SO,n32,=), ${misc:Depends} +BUILT_USING`'dnl Description: GCC OpenMP (GOMP) support library (n32 debug symbols) GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers ifenabled(`libx32gomp',` Package: libx32gomp`'GOMP_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchx32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC OpenMP (GOMP) support library (x32) GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers in the GNU Compiler Collection. Package: libx32gomp`'GOMP_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchx32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') Section: debug Priority: extra -Depends: BASEDEP, libx32gomp`'GOMP_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(gomp`'GOMP_SO,x32,=), ${misc:Depends} +BUILT_USING`'dnl Description: GCC OpenMP (GOMP) support library (x32 debug symbols) GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers ')`'dnl libx32gomp @@ -1105,20 +1246,22 @@ ifenabled(`libhfgomp',` Package: libhfgomp`'GOMP_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} ifdef(`TARGET',`dnl',`Conflicts: libgomp'GOMP_SO`-armhf [biarchhf_archs]') +BUILT_USING`'dnl Description: GCC OpenMP (GOMP) support library (hard float ABI) GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers in the GNU Compiler Collection. Package: libhfgomp`'GOMP_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Section: debug Priority: extra -Depends: BASEDEP, libhfgomp`'GOMP_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(gomp`'GOMP_SO,hf,=), ${misc:Depends} ifdef(`TARGET',`dnl',`Conflicts: libgomp'GOMP_SO`-dbg-armhf [biarchhf_archs]') +BUILT_USING`'dnl Description: GCC OpenMP (GOMP) support library (hard float ABI debug symbols) GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers ')`'dnl libhfgomp @@ -1126,20 +1269,22 @@ ifenabled(`libsfgomp',` Package: libsfgomp`'GOMP_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} ifdef(`TARGET',`dnl',`Conflicts: libgomp'GOMP_SO`-armel [biarchsf_archs]') +BUILT_USING`'dnl Description: GCC OpenMP (GOMP) support library (soft float ABI) GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers in the GNU Compiler Collection. Package: libsfgomp`'GOMP_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Section: debug Priority: extra -Depends: BASEDEP, libsfgomp`'GOMP_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(gomp`'GOMP_SO,sf,=), ${misc:Depends} ifdef(`TARGET',`dnl',`Conflicts: libgomp'GOMP_SO`-dbg-armel [biarchsf_archs]') +BUILT_USING`'dnl Description: GCC OpenMP (GOMP) support library (soft float ABI debug symbols) GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers ')`'dnl libsfgomp @@ -1150,6 +1295,7 @@ Section: libs Priority: extra Depends: BASEDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC OpenMP (GOMP) support library [neon optimized] GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers in the GNU Compiler Collection. @@ -1162,24 +1308,26 @@ ifenabled(`libitm',` Package: libitm`'ITM_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') ifdef(`TARGET',`dnl',ifdef(`MULTIARCH', `Multi-Arch: same Pre-Depends: multiarch-support ')`Provides: libitm'ITM_SO`-armel [armel], libitm'ITM_SO`-armhf [armhf]') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GNU Transactional Memory Library GNU Transactional Memory Library (libitm) provides transaction support for accesses to the memory of a process, enabling easy-to-use synchronization of accesses to shared memory by several threads. Package: libitm`'ITM_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') Section: debug Priority: extra -Depends: BASEDEP, libitm`'ITM_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(itm`'ITM_SO,,=), ${misc:Depends} ifdef(`TARGET',`dnl',ifdef(`MULTIARCH', `Multi-Arch: same ')`Provides: libitm'ITM_SO`-dbg-armel [armel], libitm'ITM_SO`-dbg-armhf [armhf]') +BUILT_USING`'dnl Description: GNU Transactional Memory Library (debug symbols) GNU Transactional Memory Library (libitm) provides transaction support for accesses to the memory of a process, enabling easy-to-use synchronization of @@ -1187,20 +1335,22 @@ Package: lib32itm`'ITM_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Conflicts: ${confl:lib32} +BUILT_USING`'dnl Description: GNU Transactional Memory Library (32bit) GNU Transactional Memory Library (libitm) provides transaction support for accesses to the memory of a process, enabling easy-to-use synchronization of accesses to shared memory by several threads. Package: lib32itm`'ITM_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Section: debug Priority: extra -Depends: BASEDEP, lib32itm`'ITM_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(itm`'ITM_SO,32,=), ${misc:Depends} +BUILT_USING`'dnl Description: GNU Transactional Memory Library (32 bit debug symbols) GNU Transactional Memory Library (libitm) provides transaction support for accesses to the memory of a process, enabling easy-to-use synchronization of @@ -1208,19 +1358,21 @@ Package: lib64itm`'ITM_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GNU Transactional Memory Library (64bit) GNU Transactional Memory Library (libitm) provides transaction support for accesses to the memory of a process, enabling easy-to-use synchronization of accesses to shared memory by several threads. Package: lib64itm`'ITM_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Section: debug Priority: extra -Depends: BASEDEP, lib64itm`'ITM_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(itm`'ITM_SO,64,=), ${misc:Depends} +BUILT_USING`'dnl Description: GNU Transactional Memory Library (64bit debug symbols) GNU Transactional Memory Library (libitm) provides transaction support for accesses to the memory of a process, enabling easy-to-use synchronization of @@ -1228,19 +1380,21 @@ Package: libn32itm`'ITM_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GNU Transactional Memory Library (n32) GNU Transactional Memory Library (libitm) provides transaction support for accesses to the memory of a process, enabling easy-to-use synchronization of accesses to shared memory by several threads. Package: libn32itm`'ITM_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Section: debug Priority: extra -Depends: BASEDEP, libn32itm`'ITM_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(itm`'ITM_SO,n32,=), ${misc:Depends} +BUILT_USING`'dnl Description: GNU Transactional Memory Library (n32 debug symbols) GNU Transactional Memory Library (libitm) provides transaction support for accesses to the memory of a process, enabling easy-to-use synchronization of @@ -1249,19 +1403,21 @@ ifenabled(`libx32itm',` Package: libx32itm`'ITM_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchx32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GNU Transactional Memory Library (x32) This manual documents the usage and internals of libitm. It provides transaction support for accesses to the memory of a process, enabling easy-to-use synchronization of accesses to shared memory by several threads. Package: libx32itm`'ITM_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchx32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') Section: debug Priority: extra -Depends: BASEDEP, libx32itm`'ITM_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(itm`'ITM_SO,x32,=), ${misc:Depends} +BUILT_USING`'dnl Description: GNU Transactional Memory Library (x32 debug symbols) This manual documents the usage and internals of libitm. It provides transaction support for accesses to the memory of a process, enabling @@ -1271,21 +1427,23 @@ ifenabled(`libhfitm',` Package: libhfitm`'ITM_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} ifdef(`TARGET',`dnl',`Conflicts: libitm'ITM_SO`-armhf [biarchhf_archs]') +BUILT_USING`'dnl Description: GNU Transactional Memory Library (hard float ABI) GNU Transactional Memory Library (libitm) provides transaction support for accesses to the memory of a process, enabling easy-to-use synchronization of accesses to shared memory by several threads. Package: libhfitm`'ITM_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Section: debug Priority: extra -Depends: BASEDEP, libhfitm`'ITM_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(itm`'ITM_SO,hf,=), ${misc:Depends} ifdef(`TARGET',`dnl',`Conflicts: libitm'ITM_SO`-armel [biarchsf_archs]') +BUILT_USING`'dnl Description: GNU Transactional Memory Library (hard float ABI debug symbols) GNU Transactional Memory Library (libitm) provides transaction support for accesses to the memory of a process, enabling easy-to-use synchronization of @@ -1295,19 +1453,21 @@ ifenabled(`libsfitm',` Package: libsfitm`'ITM_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GNU Transactional Memory Library (soft float ABI) GNU Transactional Memory Library (libitm) provides transaction support for accesses to the memory of a process, enabling easy-to-use synchronization of accesses to shared memory by several threads. Package: libsfitm`'ITM_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Section: debug Priority: extra -Depends: BASEDEP, libsfitm`'ITM_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(itm`'ITM_SO,sf,=), ${misc:Depends} +BUILT_USING`'dnl Description: GNU Transactional Memory Library (soft float ABI debug symbols) GNU Transactional Memory Library (libitm) provides transaction support for accesses to the memory of a process, enabling easy-to-use synchronization of @@ -1320,6 +1480,7 @@ Section: libs Priority: extra Depends: BASEDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GNU Transactional Memory Library [neon optimized] GNU Transactional Memory Library (libitm) provides transaction support for accesses to the memory of a process, enabling easy-to-use synchronization of @@ -1333,82 +1494,90 @@ ifenabled(`libqmath',` Package: libquadmath`'QMATH_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') ifdef(`TARGET',`dnl',ifdef(`MULTIARCH', `Multi-Arch: same Pre-Depends: multiarch-support '))`'dnl Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC Quad-Precision Math Library A library, which provides quad-precision mathematical functions on targets supporting the __float128 datatype. The library is used to provide on such targets the REAL(16) type in the GNU Fortran compiler. Package: libquadmath`'QMATH_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') Section: debug Priority: extra -Depends: BASEDEP, libquadmath`'QMATH_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(quadmath`'QMATH_SO,,=), ${misc:Depends} ifdef(`TARGET',`dnl',ifdef(`MULTIARCH', `Multi-Arch: same '))`'dnl +BUILT_USING`'dnl Description: GCC Quad-Precision Math Library (debug symbols) A library, which provides quad-precision mathematical functions on targets supporting the __float128 datatype. Package: lib32quadmath`'QMATH_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Conflicts: ${confl:lib32} +BUILT_USING`'dnl Description: GCC Quad-Precision Math Library (32bit) A library, which provides quad-precision mathematical functions on targets supporting the __float128 datatype. The library is used to provide on such targets the REAL(16) type in the GNU Fortran compiler. Package: lib32quadmath`'QMATH_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Section: debug Priority: extra -Depends: BASEDEP, lib32quadmath`'QMATH_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(quadmath`'QMATH_SO,32,=), ${misc:Depends} +BUILT_USING`'dnl Description: GCC Quad-Precision Math Library (32 bit debug symbols) A library, which provides quad-precision mathematical functions on targets supporting the __float128 datatype. Package: lib64quadmath`'QMATH_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC Quad-Precision Math Library (64bit) A library, which provides quad-precision mathematical functions on targets supporting the __float128 datatype. The library is used to provide on such targets the REAL(16) type in the GNU Fortran compiler. Package: lib64quadmath`'QMATH_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Section: debug Priority: extra -Depends: BASEDEP, lib64quadmath`'QMATH_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(quadmath`'QMATH_SO,64,=), ${misc:Depends} +BUILT_USING`'dnl Description: GCC Quad-Precision Math Library (64bit debug symbols) A library, which provides quad-precision mathematical functions on targets supporting the __float128 datatype. Package: libn32quadmath`'QMATH_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC Quad-Precision Math Library (n32) A library, which provides quad-precision mathematical functions on targets supporting the __float128 datatype. The library is used to provide on such targets the REAL(16) type in the GNU Fortran compiler. Package: libn32quadmath`'QMATH_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Section: debug Priority: extra -Depends: BASEDEP, libn32quadmath`'QMATH_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(quadmath`'QMATH_SO,n32,=), ${misc:Depends} +BUILT_USING`'dnl Description: GCC Quad-Precision Math Library (n32 debug symbols) A library, which provides quad-precision mathematical functions on targets supporting the __float128 datatype. @@ -1416,19 +1585,21 @@ ifenabled(`libx32qmath',` Package: libx32quadmath`'QMATH_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchx32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC Quad-Precision Math Library (x32) A library, which provides quad-precision mathematical functions on targets supporting the __float128 datatype. The library is used to provide on such targets the REAL(16) type in the GNU Fortran compiler. Package: libx32quadmath`'QMATH_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchx32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') Section: debug Priority: extra -Depends: BASEDEP, libx32quadmath`'QMATH_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(quadmath`'QMATH_SO,x32,=), ${misc:Depends} +BUILT_USING`'dnl Description: GCC Quad-Precision Math Library (x32 debug symbols) A library, which provides quad-precision mathematical functions on targets supporting the __float128 datatype. @@ -1437,19 +1608,21 @@ ifenabled(`libhfqmath',` Package: libhfquadmath`'QMATH_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC Quad-Precision Math Library (hard float ABI) A library, which provides quad-precision mathematical functions on targets supporting the __float128 datatype. The library is used to provide on such targets the REAL(16) type in the GNU Fortran compiler. Package: libhfquadmath`'QMATH_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Section: debug Priority: extra -Depends: BASEDEP, libhfquadmath`'QMATH_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(quadmath`'QMATH_SO,hf,=), ${misc:Depends} +BUILT_USING`'dnl Description: GCC Quad-Precision Math Library (hard float ABI debug symbols) A library, which provides quad-precision mathematical functions on targets supporting the __float128 datatype. @@ -1458,19 +1631,21 @@ ifenabled(`libsfqmath',` Package: libsfquadmath`'QMATH_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC Quad-Precision Math Library (soft float ABI) A library, which provides quad-precision mathematical functions on targets supporting the __float128 datatype. The library is used to provide on such targets the REAL(16) type in the GNU Fortran compiler. Package: libsfquadmath`'QMATH_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Section: debug Priority: extra -Depends: BASEDEP, libsfquadmath`'QMATH_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(quadmath`'QMATH_SO,sf,=), ${misc:Depends} +BUILT_USING`'dnl Description: GCC Quad-Precision Math Library (hard float ABI debug symbols) A library, which provides quad-precision mathematical functions on targets supporting the __float128 datatype. @@ -1482,9 +1657,10 @@ Package: gobjc++`'PV`'TS Architecture: any Priority: ifdef(`TARGET',`extra',`PRI(optional)') -Depends: BASEDEP, gobjc`'PV`'TS (= ${gcc:Version}), g++`'PV`'TS (= ${gcc:Version}), ${shlibs:Depends}, libobjc`'PV-dev`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, gobjc`'PV`'TS (= ${gcc:Version}), g++`'PV`'TS (= ${gcc:Version}), ${shlibs:Depends}, libdevdep(objc`'PV-dev,,=), ${misc:Depends} Suggests: ${gobjcxx:multilib}, gcc`'PV-doc (>= ${gcc:SoftVersion}) Provides: objc++-compiler`'TS +BUILT_USING`'dnl Description: GNU Objective-C++ compiler This is the GNU Objective-C++ compiler, which compiles Objective-C++ on platforms supported by the gcc compiler. It uses the @@ -1497,6 +1673,7 @@ Section: devel Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, gobjc++`'PV`'TS (= ${gcc:Version}), g++`'PV-multilib`'TS (= ${gcc:Version}), gobjc`'PV-multilib`'TS (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GNU Objective-C++ compiler (multilib files) This is the GNU Objective-C++ compiler, which compiles Objective-C++ on platforms supported by the gcc compiler. @@ -1511,10 +1688,11 @@ Package: gobjc`'PV`'TS Architecture: any Priority: ifdef(`TARGET',`extra',`PRI(optional)') -Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, libobjc`'PV-dev`'LS (= ${gcc:Version}), ${misc:Depends} -Suggests: ${gobjc:multilib}, gcc`'PV-doc (>= ${gcc:SoftVersion}), libobjc`'OBJC_SO-dbg`'LS +Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, libdevdep(objc`'PV-dev,,=), ${misc:Depends} +Suggests: ${gobjc:multilib}, gcc`'PV-doc (>= ${gcc:SoftVersion}), libdbgdep(objc`'OBJC_SO-dbg,) Provides: objc-compiler`'TS ifdef(`__sparc__',`Conflicts: gcc`'PV-sparc64', `dnl') +BUILT_USING`'dnl Description: GNU Objective-C compiler This is the GNU Objective-C compiler, which compiles Objective-C on platforms supported by the gcc compiler. It uses the @@ -1526,6 +1704,7 @@ Section: devel Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, gobjc`'PV`'TS (= ${gcc:Version}), gcc`'PV-multilib`'TS (= ${gcc:Version}), ${dep:libobjcbiarchdev}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GNU Objective-C compiler (multilib files)`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `') This is the GNU Objective-C compiler, which compiles Objective-C on platforms supported by the gcc compiler. @@ -1533,40 +1712,114 @@ On architectures with multilib support, the package contains files and dependencies for the non-default multilib architecture(s). ')`'dnl multilib + +Package: libobjc`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') +Section: libdevel +Priority: optional +Depends: BASEDEP, libdevdep(gcc`'PV-dev,,=), libdep(objc`'OBJC_SO,,>=), ${shlibs:Depends}, ${misc:Depends} +Replaces: gobjc`'PV (<< ${gcc:SplitVersion}) +ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same +'))`'dnl +BUILT_USING`'dnl +Description: Runtime library for GNU Objective-C applications (development files) + This package contains the headers and static library files needed to build + GNU ObjC applications. + +Package: lib64objc`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') +Section: libdevel +Priority: optional +Depends: BASEDEP, libdevdep(gcc`'PV-dev,64,=), libdep(objc`'OBJC_SO,64,>=), ${shlibs:Depends}, ${misc:Depends} +Replaces: gobjc`'PV-multilib (<< ${gcc:SplitVersion}) +Description: Runtime library for GNU Objective-C applications (64bit development files) + This package contains the headers and static library files needed to build + GNU ObjC applications. + +Package: lib32objc`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') +Section: libdevel +Priority: optional +Depends: BASEDEP, libdevdep(gcc`'PV-dev,32,=), libdep(objc`'OBJC_SO,32,>=), ${shlibs:Depends}, ${misc:Depends} +Replaces: gobjc`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: Runtime library for GNU Objective-C applications (32bit development files) + This package contains the headers and static library files needed to build + GNU ObjC applications. + +Package: libn32objc`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') +Section: libdevel +Priority: optional +Depends: BASEDEP, libdevdep(gcc`'PV-dev,n32,=), libdep(objc`'OBJC_SO,n32,>=), ${shlibs:Depends}, ${misc:Depends} +Replaces: gobjc`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: Runtime library for GNU Objective-C applications (n32 development files) + This package contains the headers and static library files needed to build + GNU ObjC applications. + +ifenabled(`libx32objc',` +Package: libx32objc`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') +Section: libdevel +Priority: optional +Depends: BASEDEP, libdevdep(gcc`'PV-dev,x32,=), libdep(objc`'OBJC_SO,x32,>=), ${shlibs:Depends}, ${misc:Depends} +Replaces: gobjc`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: Runtime library for GNU Objective-C applications (x32 development files) + This package contains the headers and static library files needed to build + GNU ObjC applications. +')`'dnl libx32objc + +ifenabled(`armml',` +Package: libhfobjc`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') +Section: libdevel +Priority: optional +Depends: BASEDEP, libdevdep(gcc`'PV-dev,hf,=), libdep(objc`'OBJC_SO,hf,>=), ${shlibs:Depends}, ${misc:Depends} +Replaces: gobjc`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: Runtime library for GNU Objective-C applications (hard float ABI development files) + This package contains the headers and static library files needed to build + GNU ObjC applications. +')`'dnl armml + +ifenabled(`armml',` +Package: libsfobjc`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') +Section: libdevel +Priority: optional +Depends: BASEDEP, libdevdep(gcc`'PV-dev,sf,=), libdep(objc`'OBJC_SO,sf,>=), ${shlibs:Depends}, ${misc:Depends} +Replaces: gobjc`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: Runtime library for GNU Objective-C applications (soft float development files) + This package contains the headers and static library files needed to build + GNU ObjC applications. +')`'dnl armml ')`'dnl objcdev ifenabled(`libobjc',` Package: libobjc`'OBJC_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') ifdef(`TARGET',`dnl',ifdef(`MULTIARCH', `Multi-Arch: same Pre-Depends: multiarch-support ifelse(OBJC_SO,`2',`Breaks: ${multiarch:breaks} ',`')')`Provides: libobjc'OBJC_SO`-armel [armel], libobjc'OBJC_SO`-armhf [armhf]') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Objective-C applications Library needed for GNU ObjC applications linked against the shared library. -Package: libobjc`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`any') -Section: libdevel -Priority: optional -Depends: BASEDEP, libgcc`'PV-dev`'LS (= ${gcc:Version}), libobjc`'OBJC_SO`'LS (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Replaces: gobjc`'PV (<< ${gcc:SplitVersion}) -ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same -'))`'dnl -Description: Runtime library for GNU Objective-C applications (development files) - This package contains the headers and static library files needed to build - GNU ObjC applications. - Package: libobjc`'OBJC_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') ifdef(`TARGET',`dnl',ifdef(`MULTIARCH', `Multi-Arch: same ')`Provides: libobjc'OBJC_SO`-dbg-armel [armel], libobjc'OBJC_SO`-dbg-armhf [armhf]') Priority: extra -Depends: BASEDEP, libobjc`'OBJC_SO`'LS (= ${gcc:Version}), libgcc`'GCC_SO-dbg`'LS, ${misc:Depends} +Depends: BASEDEP, libdep(objc`'OBJC_SO,,=), libdbgdep(gcc`'GCC_SO-dbg,,>=,${gcc:EpochVersion}), ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Objective-C applications (debug symbols) Library needed for GNU ObjC applications linked against the shared library. ')`'dnl libobjc @@ -1574,27 +1827,19 @@ ifenabled(`lib64objc',` Package: lib64objc`'OBJC_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Objective-C applications (64bit) Library needed for GNU ObjC applications linked against the shared library. -Package: lib64objc`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`biarch64_archs') -Section: libdevel -Priority: optional -Depends: BASEDEP, lib64gcc`'PV-dev`'LS (= ${gcc:Version}), lib64objc`'OBJC_SO`'LS (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Replaces: gobjc`'PV-multilib (<< ${gcc:SplitVersion}) -Description: Runtime library for GNU Objective-C applications (64bit development files) - This package contains the headers and static library files needed to build - GNU ObjC applications. - Package: lib64objc`'OBJC_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Priority: extra -Depends: BASEDEP, lib64objc`'OBJC_SO`'LS (= ${gcc:Version}), lib64gcc`'GCC_SO-dbg`'LS, ${misc:Depends} +Depends: BASEDEP, libdep(objc`'OBJC_SO,64,=), libdbgdep(gcc`'GCC_SO-dbg,64,>=,${gcc:EpochVersion}), ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Objective-C applications (64 bit debug symbols) Library needed for GNU ObjC applications linked against the shared library. ')`'dnl lib64objc @@ -1602,28 +1847,20 @@ ifenabled(`lib32objc',` Package: lib32objc`'OBJC_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Conflicts: ${confl:lib32} +BUILT_USING`'dnl Description: Runtime library for GNU Objective-C applications (32bit) Library needed for GNU ObjC applications linked against the shared library. -Package: lib32objc`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`biarch32_archs') -Section: libdevel -Priority: optional -Depends: BASEDEP, lib32gcc`'PV-dev`'LS (= ${gcc:Version}), lib32objc`'OBJC_SO`'LS (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Replaces: gobjc`'PV-multilib (<< ${gcc:SplitVersion}) -Description: Runtime library for GNU Objective-C applications (32bit development files) - This package contains the headers and static library files needed to build - GNU ObjC applications. - Package: lib32objc`'OBJC_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Priority: extra -Depends: BASEDEP, lib32objc`'OBJC_SO`'LS (= ${gcc:Version}), lib32gcc`'GCC_SO-dbg`'LS, ${misc:Depends} +Depends: BASEDEP, libdep(objc`'OBJC_SO,32,=), libdbgdep(gcc`'GCC_SO-dbg,32,>=,${gcc:EpochVersion}), ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Objective-C applications (32 bit debug symbols) Library needed for GNU ObjC applications linked against the shared library. ')`'dnl lib32objc @@ -1631,27 +1868,19 @@ ifenabled(`libn32objc',` Package: libn32objc`'OBJC_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Objective-C applications (n32) Library needed for GNU ObjC applications linked against the shared library. -Package: libn32objc`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') -Section: libdevel -Priority: optional -Depends: BASEDEP, libn32gcc`'PV-dev`'LS (= ${gcc:Version}), libn32objc`'OBJC_SO`'LS (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Replaces: gobjc`'PV-multilib (<< ${gcc:SplitVersion}) -Description: Runtime library for GNU Objective-C applications (n32 development files) - This package contains the headers and static library files needed to build - GNU ObjC applications. - Package: libn32objc`'OBJC_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Priority: extra -Depends: BASEDEP, libn32objc`'OBJC_SO`'LS (= ${gcc:Version}), libn32gcc`'GCC_SO-dbg`'LS, ${misc:Depends} +Depends: BASEDEP, libdep(objc`'OBJC_SO,n32,=), libdbgdep(gcc`'GCC_SO-dbg,n32,>=,${gcc:EpochVersion}), ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Objective-C applications (n32 debug symbols) Library needed for GNU ObjC applications linked against the shared library. ')`'dnl libn32objc @@ -1659,27 +1888,19 @@ ifenabled(`libx32objc',` Package: libx32objc`'OBJC_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchx32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Objective-C applications (x32) Library needed for GNU ObjC applications linked against the shared library. -Package: libx32objc`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`biarchx32_archs') -Section: libdevel -Priority: optional -Depends: BASEDEP, libx32gcc`'PV-dev`'LS (= ${gcc:Version}), libx32objc`'OBJC_SO`'LS (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Replaces: gobjc`'PV-multilib (<< ${gcc:SplitVersion}) -Description: Runtime library for GNU Objective-C applications (x32 development files) - This package contains the headers and static library files needed to build - GNU ObjC applications. - Package: libx32objc`'OBJC_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`biarchx32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') Priority: extra -Depends: BASEDEP, libx32objc`'OBJC_SO`'LS (= ${gcc:Version}), libx32gcc`'GCC_SO-dbg`'LS, ${misc:Depends} +Depends: BASEDEP, libdep(objc`'OBJC_SO,x32,=), libdbgdep(gcc`'GCC_SO-dbg,x32,>=,${gcc:EpochVersion}), ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Objective-C applications (x32 debug symbols) Library needed for GNU ObjC applications linked against the shared library. ')`'dnl libx32objc @@ -1687,29 +1908,21 @@ ifenabled(`libhfobjc',` Package: libhfobjc`'OBJC_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} ifdef(`TARGET',`dnl',`Conflicts: libobjc'OBJC_SO`-armhf [biarchhf_archs]') +BUILT_USING`'dnl Description: Runtime library for GNU Objective-C applications (hard float ABI) Library needed for GNU ObjC applications linked against the shared library. -Package: libhfobjc`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') -Section: libdevel -Priority: optional -Depends: BASEDEP, libhfgcc`'PV-dev`'LS (= ${gcc:Version}), libhfobjc`'OBJC_SO`'LS (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Replaces: gobjc`'PV-multilib (<< ${gcc:SplitVersion}) -Description: Runtime library for GNU Objective-C applications (hard float ABI development files) - This package contains the headers and static library files needed to build - GNU ObjC applications. - Package: libhfobjc`'OBJC_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Priority: extra -Depends: BASEDEP, libhfobjc`'OBJC_SO`'LS (= ${gcc:Version}), libhfgcc`'GCC_SO-dbg`'LS, ${misc:Depends} +Depends: BASEDEP, libdep(objc`'OBJC_SO,hf,=), libdbgdep(gcc`'GCC_SO-dbg,hf,>=,${gcc:EpochVersion}), ${misc:Depends} ifdef(`TARGET',`dnl',`Conflicts: libobjc'OBJC_SO`-dbg-armhf [biarchhf_archs]') +BUILT_USING`'dnl Description: Runtime library for GNU Objective-C applications (hard float ABI debug symbols) Library needed for GNU ObjC applications linked against the shared library. ')`'dnl libhfobjc @@ -1717,29 +1930,21 @@ ifenabled(`libsfobjc',` Package: libsfobjc`'OBJC_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} ifdef(`TARGET',`dnl',`Conflicts: libobjc'OBJC_SO`-armel [biarchsf_archs]') +BUILT_USING`'dnl Description: Runtime library for GNU Objective-C applications (soft float ABI) Library needed for GNU ObjC applications linked against the shared library. -Package: libsfobjc`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') -Section: libdevel -Priority: optional -Depends: BASEDEP, libsfgcc`'PV-dev`'LS (= ${gcc:Version}), libsfobjc`'OBJC_SO`'LS (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Replaces: gobjc`'PV-multilib (<< ${gcc:SplitVersion}) -Description: Runtime library for GNU Objective-C applications (soft float development files) - This package contains the headers and static library files needed to build - GNU ObjC applications. - Package: libsfobjc`'OBJC_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Priority: extra -Depends: BASEDEP, libsfobjc`'OBJC_SO`'LS (= ${gcc:Version}), libsfgcc`'GCC_SO-dbg`'LS, ${misc:Depends} +Depends: BASEDEP, libdep(objc`'OBJC_SO,sf,=), libdbgdep(gcc`'GCC_SO-dbg,sf,>=,${gcc:EpochVersion}), ${misc:Depends} ifdef(`TARGET',`dnl',`Conflicts: libobjc'OBJC_SO`-dbg-armel [biarchsf_archs]') +BUILT_USING`'dnl Description: Runtime library for GNU Objective-C applications (soft float ABI debug symbols) Library needed for GNU ObjC applications linked against the shared library. ')`'dnl libsfobjc @@ -1750,6 +1955,7 @@ Architecture: NEON_ARCHS Priority: PRI(optional) Depends: BASEDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Objective-C applications [NEON version] Library needed for GNU ObjC applications linked against the shared library. . @@ -1763,9 +1969,10 @@ Package: gfortran`'PV`'TS Architecture: any Priority: ifdef(`TARGET',`extra',`PRI(optional)') -Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), libgfortran`'PV-dev`'LS (= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), libdevdep(gfortran`'PV-dev,,=), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends} Provides: fortran95-compiler -Suggests: ${gfortran:multilib}, gfortran`'PV-doc, libgfortran`'FORTRAN_SO-dbg`'LS +Suggests: ${gfortran:multilib}, gfortran`'PV-doc, libdbgdep(gfortran`'FORTRAN_SO-dbg,) +BUILT_USING`'dnl Description: GNU Fortran compiler This is the GNU Fortran compiler, which compiles Fortran on platforms supported by the gcc compiler. It uses the @@ -1777,6 +1984,7 @@ Section: devel Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, gfortran`'PV`'TS (= ${gcc:Version}), gcc`'PV-multilib`'TS (= ${gcc:Version}), ${dep:libgfortranbiarchdev}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GNU Fortran compiler (multilib files)`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `') This is the GNU Fortran compiler, which compiles Fortran on platforms supported by the gcc compiler. @@ -1794,42 +2002,123 @@ Description: Documentation for the GNU Fortran compiler (gfortran) Documentation for the GNU Fortran compiler in info `format'. ')`'dnl gfdldoc + +Package: libgfortran`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') +Section: ifdef(`TARGET',`devel',`libdevel') +Priority: optional +Depends: BASEDEP, libdep(gfortran`'FORTRAN_SO,), ${shlibs:Depends}, ${misc:Depends} +Replaces: gfortran`'PV (<< ${gcc:SplitVersion}) +Breaks: gfortran`'PV (<< ${gcc:SplitVersion}) +ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same +'))`'dnl +BUILT_USING`'dnl +Description: Runtime library for GNU Fortran applications (development files) + This package contains the headers and static library files needed to build + GNU Fortran applications. + +Package: lib64gfortran`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') +Section: libdevel +Priority: optional +Depends: BASEDEP, libdep(gfortran`'FORTRAN_SO,64,>=), ${shlibs:Depends}, ${misc:Depends} +Replaces: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) +Breaks: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: Runtime library for GNU Fortran applications (64bit development files) + This package contains the headers and static library files needed to build + GNU Fortran applications. + +Package: lib32gfortran`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') +Section: libdevel +Priority: optional +Depends: BASEDEP, libdep(gfortran`'FORTRAN_SO,32,>=), ${shlibs:Depends}, ${misc:Depends} +Replaces: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) +Breaks: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: Runtime library for GNU Fortran applications (32bit development files) + This package contains the headers and static library files needed to build + GNU Fortran applications. + +Package: libn32gfortran`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') +Section: libdevel +Priority: optional +Depends: BASEDEP, libdep(gfortran`'FORTRAN_SO,n32,>=), ${shlibs:Depends}, ${misc:Depends} +Replaces: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) +Breaks: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: Runtime library for GNU Fortran applications (n32 development files) + This package contains the headers and static library files needed to build + GNU Fortran applications. + +ifenabled(`libx32gfortran',` +Package: libx32gfortran`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') +Section: libdevel +Priority: optional +Depends: BASEDEP, libdep(gfortran`'FORTRAN_SO,x32,>=), ${shlibs:Depends}, ${misc:Depends} +Replaces: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) +Breaks: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: Runtime library for GNU Fortran applications (x32 development files) + This package contains the headers and static library files needed to build + GNU Fortran applications. +')`'dnl libx32gfortran + +ifenabled(`armml',` +Package: libhfgfortran`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') +Section: libdevel +Priority: optional +Depends: BASEDEP, libdep(gfortran`'FORTRAN_SO,hf,>=), ${shlibs:Depends}, ${misc:Depends} +Replaces: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) +Breaks: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: Runtime library for GNU Fortran applications (hard float ABI development files) + This package contains the headers and static library files needed to build + GNU Fortran applications. +')`'dnl armml + +ifenabled(`armml',` +Package: libsfgfortran`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') +Section: libdevel +Priority: optional +Depends: BASEDEP, libdep(gfortran`'FORTRAN_SO,sf,>=), ${shlibs:Depends}, ${misc:Depends} +Replaces: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) +Breaks: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: Runtime library for GNU Fortran applications (soft float ABI development files) + This package contains the headers and static library files needed to build + GNU Fortran applications. +')`'dnl armml ')`'dnl fdev ifenabled(`libgfortran',` Package: libgfortran`'FORTRAN_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') ifdef(`TARGET',`dnl',ifdef(`MULTIARCH', `Multi-Arch: same Pre-Depends: multiarch-support Breaks: ${multiarch:breaks} ')`Provides: libgfortran'FORTRAN_SO`-armel [armel], libgfortran'FORTRAN_SO`-armhf [armhf]') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Fortran applications Library needed for GNU Fortran applications linked against the shared library. -Package: libgfortran`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`any') -Section: libdevel -Priority: optional -Depends: BASEDEP, libgfortran`'FORTRAN_SO`'LS, ${shlibs:Depends}, ${misc:Depends} -Replaces: gfortran`'PV (<< ${gcc:SplitVersion}) -Breaks: gfortran`'PV (<< ${gcc:SplitVersion}) -ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same -'))`'dnl -Description: Runtime library for GNU Fortran applications (development files) - This package contains the headers and static library files needed to build - GNU Fortran applications. - Package: libgfortran`'FORTRAN_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') ifdef(`TARGET',`dnl',ifdef(`MULTIARCH', `Multi-Arch: same ')`Provides: libgfortran'FORTRAN_SO`-dbg-armel [armel], libgfortran'FORTRAN_SO`-dbg-armhf [armhf]') Priority: extra -Depends: BASEDEP, libgfortran`'FORTRAN_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(gfortran`'FORTRAN_SO,,=), ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Fortran applications (debug symbols) Library needed for GNU Fortran applications linked against the shared library. @@ -1838,29 +2127,20 @@ ifenabled(`lib64gfortran',` Package: lib64gfortran`'FORTRAN_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Fortran applications (64bit) Library needed for GNU Fortran applications linked against the shared library. -Package: lib64gfortran`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`biarch64_archs') -Section: libdevel -Priority: optional -Depends: BASEDEP, lib64gfortran`'FORTRAN_SO`'LS (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Replaces: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) -Breaks: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) -Description: Runtime library for GNU Fortran applications (64bit development files) - This package contains the headers and static library files needed to build - GNU Fortran applications. - Package: lib64gfortran`'FORTRAN_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Priority: extra -Depends: BASEDEP, lib64gfortran`'FORTRAN_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(gfortran`'FORTRAN_SO,64,=), ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Fortran applications (64bit debug symbols) Library needed for GNU Fortran applications linked against the shared library. @@ -1869,30 +2149,21 @@ ifenabled(`lib32gfortran',` Package: lib32gfortran`'FORTRAN_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Conflicts: ${confl:lib32} +BUILT_USING`'dnl Description: Runtime library for GNU Fortran applications (32bit) Library needed for GNU Fortran applications linked against the shared library. -Package: lib32gfortran`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`biarch32_archs') -Section: libdevel -Priority: optional -Depends: BASEDEP, lib32gfortran`'FORTRAN_SO`'LS (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Replaces: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) -Breaks: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) -Description: Runtime library for GNU Fortran applications (32bit development files) - This package contains the headers and static library files needed to build - GNU Fortran applications. - Package: lib32gfortran`'FORTRAN_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Priority: extra -Depends: BASEDEP, lib32gfortran`'FORTRAN_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(gfortran`'FORTRAN_SO,32,=), ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Fortran applications (32 bit debug symbols) Library needed for GNU Fortran applications linked against the shared library. @@ -1901,29 +2172,20 @@ ifenabled(`libn32gfortran',` Package: libn32gfortran`'FORTRAN_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Fortran applications (n32) Library needed for GNU Fortran applications linked against the shared library. -Package: libn32gfortran`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') -Section: libdevel -Priority: optional -Depends: BASEDEP, libn32gfortran`'FORTRAN_SO`'LS (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Replaces: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) -Breaks: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) -Description: Runtime library for GNU Fortran applications (n32 development files) - This package contains the headers and static library files needed to build - GNU Fortran applications. - Package: libn32gfortran`'FORTRAN_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Priority: extra -Depends: BASEDEP, libn32gfortran`'FORTRAN_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(gfortran`'FORTRAN_SO,n32,=), ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Fortran applications (n32 debug symbols) Library needed for GNU Fortran applications linked against the shared library. @@ -1932,29 +2194,20 @@ ifenabled(`libx32gfortran',` Package: libx32gfortran`'FORTRAN_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchx32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Fortran applications (x32) Library needed for GNU Fortran applications linked against the shared library. -Package: libx32gfortran`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`biarchx32_archs') -Section: libdevel -Priority: optional -Depends: BASEDEP, libx32gfortran`'FORTRAN_SO`'LS (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Replaces: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) -Breaks: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) -Description: Runtime library for GNU Fortran applications (x32 development files) - This package contains the headers and static library files needed to build - GNU Fortran applications. - Package: libx32gfortran`'FORTRAN_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`biarchx32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') Priority: extra -Depends: BASEDEP, libx32gfortran`'FORTRAN_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(gfortran`'FORTRAN_SO,x32,=), ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Fortran applications (x32 debug symbols) Library needed for GNU Fortran applications linked against the shared library. @@ -1963,31 +2216,22 @@ ifenabled(`libhfgfortran',` Package: libhfgfortran`'FORTRAN_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} ifdef(`TARGET',`dnl',`Conflicts: libgfortran'FORTRAN_SO`-armhf [biarchhf_archs]') +BUILT_USING`'dnl Description: Runtime library for GNU Fortran applications (hard float ABI) Library needed for GNU Fortran applications linked against the shared library. -Package: libhfgfortran`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') -Section: libdevel -Priority: optional -Depends: BASEDEP, libhfgfortran`'FORTRAN_SO`'LS (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Replaces: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) -Breaks: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) -Description: Runtime library for GNU Fortran applications (hard float ABI development files) - This package contains the headers and static library files needed to build - GNU Fortran applications. - Package: libhfgfortran`'FORTRAN_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Priority: extra -Depends: BASEDEP, libhfgfortran`'FORTRAN_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(gfortran`'FORTRAN_SO,hf,=), ${misc:Depends} ifdef(`TARGET',`dnl',`Conflicts: libgfortran'FORTRAN_SO`-dbg-armhf [biarchhf_archs]') +BUILT_USING`'dnl Description: Runtime library for GNU Fortran applications (hard float ABI debug symbols) Library needed for GNU Fortran applications linked against the shared library. @@ -1996,31 +2240,22 @@ ifenabled(`libsfgfortran',` Package: libsfgfortran`'FORTRAN_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} ifdef(`TARGET',`dnl',`Conflicts: libgfortran'FORTRAN_SO`-armel [biarchsf_archs]') +BUILT_USING`'dnl Description: Runtime library for GNU Fortran applications (soft float ABI) Library needed for GNU Fortran applications linked against the shared library. -Package: libsfgfortran`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') -Section: libdevel -Priority: optional -Depends: BASEDEP, libsfgfortran`'FORTRAN_SO`'LS (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Replaces: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) -Breaks: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) -Description: Runtime library for GNU Fortran applications (soft float ABI development files) - This package contains the headers and static library files needed to build - GNU Fortran applications. - Package: libsfgfortran`'FORTRAN_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Priority: extra -Depends: BASEDEP, libsfgfortran`'FORTRAN_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(gfortran`'FORTRAN_SO,sf,=), ${misc:Depends} ifdef(`TARGET',`dnl',`Conflicts: libgfortran'FORTRAN_SO`-dbg-armel [biarchsf_archs]') +BUILT_USING`'dnl Description: Runtime library for GNU Fortran applications (hard float ABI debug symbols) Library needed for GNU Fortran applications linked against the shared library. @@ -2036,6 +2271,7 @@ ')`'dnl Priority: extra Depends: BASEDEP, libgcc1-neon`'LS, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Fortran applications [NEON version] Library needed for GNU Fortran applications linked against the shared library. @@ -2050,10 +2286,11 @@ Package: gccgo`'PV`'TS Architecture: any Priority: ifdef(`TARGET',`extra',`PRI(optional)') -Depends: BASEDEP, ifdef(`STANDALONEGO',,`gcc`'PV`'TS (= ${gcc:Version}), ')libgo`'GO_SO`'LS (>= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, ifdef(`STANDALONEGO',,`gcc`'PV`'TS (= ${gcc:Version}), ')libdep(go`'GO_SO`',,>=), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends} Provides: go-compiler -Suggests: ${go:multilib}, gccgo`'PV-doc, libgo`'GO_SO-dbg`'LS +Suggests: ${go:multilib}, gccgo`'PV-doc, libdbgdep(go`'GO_SO-dbg,) Replaces: gcc-4.7-doc (<< 4.7.2-11) +BUILT_USING`'dnl Description: GNU Go compiler This is the GNU Go compiler, which compiles Go on platforms supported by the gcc compiler. It uses the gcc backend to generate optimized code. @@ -2065,6 +2302,7 @@ Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, gccgo`'PV`'TS (= ${gcc:Version}), ifdef(`STANDALONEGO',,`gcc`'PV-multilib`'TS (= ${gcc:Version}), ')${dep:libgobiarch}, ${shlibs:Depends}, ${misc:Depends} Suggests: ${dep:libgobiarchdbg} +BUILT_USING`'dnl Description: GNU Go compiler (multilib files)`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `') This is the GNU Go compiler, which compiles Go on platforms supported by the gcc compiler. @@ -2079,6 +2317,7 @@ Section: doc Priority: PRI(optional) Depends: gcc`'PV-base (>= ${gcc:SoftVersion}), dpkg (>= 1.15.4) | install-info, ${misc:Depends} +BUILT_USING`'dnl Description: Documentation for the GNU Go compiler (gccgo) Documentation for the GNU Go compiler in info `format'. ')`'dnl gfdldoc @@ -2087,23 +2326,25 @@ ifenabled(`libggo',` Package: libgo`'GO_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') ifdef(`TARGET',`dnl',ifdef(`MULTIARCH', `Multi-Arch: same Pre-Depends: multiarch-support ')`Provides: libgo'GO_SO`-armel [armel], libgo'GO_SO`-armhf [armhf]') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Go applications Library needed for GNU Go applications linked against the shared library. Package: libgo`'GO_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') ifdef(`TARGET',`dnl',ifdef(`MULTIARCH', `Multi-Arch: same ')`Provides: libgo'GO_SO`-dbg-armel [armel], libgo'GO_SO`-dbg-armhf [armhf]') Priority: extra -Depends: BASEDEP, libgo`'GO_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(go`'GO_SO,,=), ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Go applications (debug symbols) Library needed for GNU Go applications linked against the shared library. @@ -2112,18 +2353,20 @@ ifenabled(`lib64ggo',` Package: lib64go`'GO_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Go applications (64bit) Library needed for GNU Go applications linked against the shared library. Package: lib64go`'GO_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Priority: extra -Depends: BASEDEP, lib64go`'GO_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(go`'GO_SO,64,=), ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Go applications (64bit debug symbols) Library needed for GNU Go applications linked against the shared library. @@ -2132,19 +2375,21 @@ ifenabled(`lib32ggo',` Package: lib32go`'GO_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Conflicts: ${confl:lib32} +BUILT_USING`'dnl Description: Runtime library for GNU Go applications (32bit) Library needed for GNU Go applications linked against the shared library. Package: lib32go`'GO_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Priority: extra -Depends: BASEDEP, lib32go`'GO_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(go`'GO_SO,32,=), ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Go applications (32 bit debug symbols) Library needed for GNU Go applications linked against the shared library. @@ -2153,18 +2398,20 @@ ifenabled(`libn32ggo',` Package: libn32go`'GO_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Go applications (n32) Library needed for GNU Go applications linked against the shared library. Package: libn32go`'GO_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Priority: extra -Depends: BASEDEP, libn32go`'GO_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(go`'GO_SO,n32,=), ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Go applications (n32 debug symbols) Library needed for GNU Go applications linked against the shared library. @@ -2173,18 +2420,20 @@ ifenabled(`libx32ggo',` Package: libx32go`'GO_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchx32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Go applications (x32) Library needed for GNU Go applications linked against the shared library. Package: libx32go`'GO_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`biarchx32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') Priority: extra -Depends: BASEDEP, libx32go`'GO_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(go`'GO_SO,x32,=), ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Go applications (x32 debug symbols) Library needed for GNU Go applications linked against the shared library. @@ -2193,16 +2442,17 @@ ifenabled(`java',` ifenabled(`gcj',` -Package: gcj`'PV-jdk +Package: gcj`'PV-jdk`'TS Section: java Architecture: any -Priority: PRI(optional) -Depends: gcj`'PV-base (= ${gcj:Version}), ${dep:gcj}, ${dep:libcdev}, gcj`'PV-jre (= ${gcj:Version}), libgcj`'GCJ_SO-dev (= ${gcj:Version}), gcj`'PV-jre-lib (>= ${gcj:SoftVersion}), ${dep:ecj}, fastjar, libgcj-bc, java-common, libantlr-java, ${shlibs:Depends}, dpkg (>= 1.15.4) | install-info, ${misc:Depends} +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, ${dep:gcj}, ${dep:libcdev}, gcj`'PV-jre`'TS (= ${gcj:Version}), libdevdep(gcj`'GCJ_SO-dev,,=,${gcj:Version}), ${dep:ecj}, fastjar, libgcj-bc`'LS, java-common, libantlr-java, ${shlibs:Depends}, dpkg (>= 1.15.4) | install-info, ${misc:Depends} Recommends: libecj-java-gcj -Suggests: gcj`'PV-source (>= ${gcj:SoftVersion}), libgcj`'GCJ_SO-dbg +Suggests: gcj`'PV-source (>= ${gcj:SoftVersion}), libdbgdep(gcj`'GCJ_SO-dbg,) Provides: java-compiler, java-sdk, java2-sdk, java5-sdk Conflicts: gcj-4.4, cpp-4.1 (<< 4.1.1), gcc-4.1 (<< 4.1.1) Replaces: libgcj11 (<< 4.5-20100101-1) +BUILT_USING`'dnl Description: gcj and classpath development tools for Java(TM) GCJ is a front end to the GCC compiler which can natively compile both Java(tm) source and bytecode files. The compiler can also generate class @@ -2219,21 +2469,24 @@ Section: java Architecture: all Priority: PRI(optional) -Depends: gcj`'PV-base (>= ${gcj:SoftVersion}), ${misc:Depends} +Depends: BASEDEP, ${misc:Depends} Conflicts: classpath (<= 0.04-4) Replaces: java-gcj-compat (<< 1.0.65-3), java-gcj-compat-dev (<< 1.0.65-3) +BUILT_USING`'dnl Description: Java runtime library (common files) This package contains files shared by classpath and libgcj libraries. ')`'dnl libgcjcommon -Package: gcj`'PV-jre-headless -Priority: optional +Package: gcj`'PV-jre-headless`'TS +Priority: ifdef(`TARGET',`extra',`PRI(optional)') Section: java Architecture: any -Depends: gcj`'PV-base (= ${gcj:Version}), libgcj`'LIBGCJ_EXT (= ${gcj:Version}), ${dep:prctl}, ${shlibs:Depends}, ${misc:Depends} -Suggests: fastjar, gcj`'PV-jdk (= ${gcj:Version}), libgcj`'LIBGCJ_EXT-awt (= ${gcj:Version}) +Depends: BASEDEP, gcj`'PV-jre-lib`'TS (>= ${gcj:SoftVersion}), libdep(gcj`'LIBGCJ_EXT,,=,${gcj:Version}), ${dep:prctl}, ${shlibs:Depends}, ${misc:Depends} +Suggests: fastjar, gcj`'PV-jdk`'TS (= ${gcj:Version}), libdep(gcj`'LIBGCJ_EXT-awt,,=,${gcj:Version}) Conflicts: gij-4.4, java-gcj-compat (<< 1.0.76-4) +Replaces: gcj-4.7-jre-lib`'TS (<< 4.7.2-10) Provides: java5-runtime-headless, java2-runtime-headless, java1-runtime-headless, java-runtime-headless +BUILT_USING`'dnl Description: Java runtime environment using GIJ/classpath (headless version) GIJ is a Java bytecode interpreter, not limited to interpreting bytecode. It includes a class loader which can dynamically load shared objects, so @@ -2244,12 +2497,13 @@ It is meant to provide a Java-RTE-like interface to the GIJ/GCJ tool set, limited to the headless tools and libraries. -Package: gcj`'PV-jre +Package: gcj`'PV-jre`'TS Section: java Architecture: any -Priority: PRI(optional) -Depends: gcj`'PV-base (= ${gcj:Version}), gcj`'PV-jre-headless (= ${gcj:Version}), libgcj`'LIBGCJ_EXT-awt (= ${gcj:Version}), ${shlibs:Depends}, ${misc:Depends} +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, gcj`'PV-jre-headless`'TS (= ${gcj:Version}), libdep(gcj`'LIBGCJ_EXT-awt,,=,${gcj:Version}), ${shlibs:Depends}, ${misc:Depends} Provides: java5-runtime, java2-runtime, java1-runtime, java-runtime +BUILT_USING`'dnl Description: Java runtime environment using GIJ/classpath GIJ is a Java bytecode interpreter, not limited to interpreting bytecode. It includes a class loader which can dynamically load shared objects, so @@ -2259,16 +2513,18 @@ The package contains as well a collection of wrapper scripts and symlinks. It is meant to provide a Java-RTE-like interface to the GIJ/GCJ tool set. -Package: libgcj`'LIBGCJ_EXT +Package: libgcj`'LIBGCJ_EXT`'LS Section: libs Architecture: any Priority: PRI(optional) ifdef(`MULTIARCH', `Pre-Depends: multiarch-support +Multi-Arch: same ')`'dnl -Depends: gcj`'PV-base (>= ${gcj:Version}), libgcj-common (>= 1:4.1.1-21), ${shlibs:Depends}, ${misc:Depends} -Recommends: gcj`'PV-jre-lib (>= ${gcj:SoftVersion}) -Suggests: libgcj`'GCJ_SO-dbg, libgcj`'LIBGCJ_EXT-awt (= ${gcj:Version}) +Depends: SOFTBASEDEP, libgcj-common (>= 1:4.1.1-21), ${shlibs:Depends}, ${misc:Depends} +Recommends: gcj`'PV-jre-lib`'TS (>= ${gcj:SoftVersion}) +Suggests: libdbgdep(gcj`'GCJ_SO-dbg,), libdep(gcj`'LIBGCJ_EXT-awt,,=,${gcj:Version}) Replaces: gij-4.4 (<< 4.4.0-1) +BUILT_USING`'dnl Description: Java runtime library for use with gcj This is the runtime that goes along with the gcj front end to gcc. libgcj includes parts of the Java Class Libraries, plus glue to @@ -2277,11 +2533,12 @@ To show file names and line numbers in stack traces, the packages libgcj`'GCJ_SO-dbg and binutils are required. -Package: gcj`'PV-jre-lib +Package: gcj`'PV-jre-lib`'TS Section: java Architecture: all Priority: PRI(optional) -Depends: gcj`'PV-base (>= ${gcj:SoftVersion}), libgcj`'LIBGCJ_EXT (>= ${gcj:SoftVersion}), ${misc:Depends} +Depends: SOFTBASEDEP, libdep(gcj`'LIBGCJ_EXT,,>=,${gcj:SoftVersion}), ${misc:Depends} +BUILT_USING`'dnl Description: Java runtime library for use with gcj (jar files) This is the jar file that goes along with the gcj front end to gcc. @@ -2291,8 +2548,10 @@ Architecture: any Priority: PRI(optional) ifdef(`MULTIARCH', `Pre-Depends: multiarch-support +Multi-Arch: same ')`'dnl -Depends: gcj`'PV-base (>= ${gcj:Version}), libgcj`'LIBGCJ_EXT (>= ${gcj:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(gcj`'LIBGCJ_EXT,,>=,${gcj:Version}), ${misc:Depends} +BUILT_USING`'dnl Description: Link time only library for use with gcj A fake library that is used at link time only. It ensures that binaries built with the BC-ABI link against a constant SONAME. @@ -2300,40 +2559,46 @@ libgcj.so changes. ')`'dnl gcjbc -Package: libgcj`'LIBGCJ_EXT-awt +Package: libgcj`'LIBGCJ_EXT-awt`'LS Section: libs Architecture: any Priority: PRI(optional) ifdef(`MULTIARCH', `Pre-Depends: multiarch-support +Multi-Arch: same ')`'dnl -Depends: gcj`'PV-base (>= ${gcj:Version}), libgcj`'LIBGCJ_EXT (= ${gcj:Version}), ${shlibs:Depends}, ${misc:Depends} +Depends: SOFTBASEDEP, libdep(gcj`'LIBGCJ_EXT,,=,${gcj:Version}), ${shlibs:Depends}, ${misc:Depends} Suggests: ${pkg:gcjqt} +BUILT_USING`'dnl Description: AWT peer runtime libraries for use with gcj These are runtime libraries holding the AWT peer implementations for libgcj (currently the GTK+ based peer library is required, the QT bases library is not built). ifenabled(`gtkpeer',` -Package: libgcj`'GCJ_SO-awt-gtk +Package: libgcj`'GCJ_SO-awt-gtk`'LS Section: libs Architecture: any Priority: PRI(optional) ifdef(`MULTIARCH', `Pre-Depends: multiarch-support +Multi-Arch: same ')`'dnl -Depends: gcj`'PV-base (= ${gcj:Version}), libgcj`'LIBGCJ_EXT-awt (= ${gcj:Version}), ${shlibs:Depends}, ${misc:Depends} +Depends: SOFTBASEDEP, libgcj`'LIBGCJ_EXT-awt`'LS (= ${gcj:Version}), ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: AWT GTK+ peer runtime library for use with libgcj This is the runtime library holding the GTK+ based AWT peer implementation for libgcj. ')`'dnl gtkpeer ifenabled(`qtpeer',` -Package: libgcj`'GCJ_SO-awt-qt +Package: libgcj`'GCJ_SO-awt-qt`'LS Section: libs Architecture: any Priority: PRI(optional) ifdef(`MULTIARCH', `Pre-Depends: multiarch-support +Multi-Arch: same ')`'dnl -Depends: gcj`'PV-base (= ${gcj:Version}), libgcj`'LIBGCJ_EXT-awt (= ${gcj:Version}), ${shlibs:Depends}, ${misc:Depends} +Depends: SOFTBASEDEP, libdep(gcj`'LIBGCJ_EXT-awt,,=,${gcj:Version}), ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: AWT QT peer runtime library for use with libgcj This is the runtime library holding the QT based AWT peer implementation for libgcj. @@ -2341,39 +2606,47 @@ ')`'dnl libgcj ifenabled(`libgcjdev',` -Package: libgcj`'GCJ_SO-dev +Package: libgcj`'GCJ_SO-dev`'LS Section: libdevel Architecture: any +ifdef(`MULTIARCH', `Multi-Arch: same +')`'dnl Priority: PRI(optional) -Depends: gcj`'PV-base (= ${gcj:Version}), gcj`'PV-jdk (= ${gcj:Version}), gcj`'PV-jre-lib (>= ${gcj:SoftVersion}), libgcj`'LIBGCJ_EXT-awt (= ${gcj:Version}), libgcj-bc, ${pkg:gcjgtk}, ${pkg:gcjqt}, zlib1g-dev, ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, gcj`'PV-jdk`'TS (= ${gcj:Version}), gcj`'PV-jre-lib`'TS (>= ${gcj:SoftVersion}), libdep(gcj`'LIBGCJ_EXT-awt,,=,${gcj:Version}), libgcj-bc`'LS, ${pkg:gcjgtk}, ${pkg:gcjqt}, zlib1g-dev, ${shlibs:Depends}, ${misc:Depends} Suggests: libgcj-doc +BUILT_USING`'dnl Description: Java development headers for use with gcj These are the development headers that go along with the gcj front end to gcc. libgcj includes parts of the Java Class Libraries, plus glue to connect the libraries to the compiler and the underlying OS. -Package: libgcj`'GCJ_SO-dbg +Package: libgcj`'GCJ_SO-dbg`'LS Section: debug Architecture: any Priority: extra ifdef(`MULTIARCH', `Pre-Depends: multiarch-support +Multi-Arch: same ')`'dnl -Depends: gcj`'PV-base (= ${gcj:Version}), libgcj`'LIBGCJ_EXT (= ${gcj:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(gcj`'LIBGCJ_EXT,,=,${gcj:Version}), ${misc:Depends} Recommends: binutils, libc6-dbg | libc-dbg +BUILT_USING`'dnl Description: Debugging symbols for libraries provided in libgcj`'GCJ_SO-dev The package provides debugging symbols for the libraries provided in libgcj`'GCJ_SO-dev. . binutils is required to show file names and line numbers in stack traces. +ifenabled(`gcjsrc',` Package: gcj`'PV-source Section: java Architecture: all Priority: PRI(optional) Depends: gcj`'PV-base (>= ${gcj:SoftVersion}), gcj`'PV-jdk (>= ${gcj:SoftVersion}), ${misc:Depends} +BUILT_USING`'dnl Description: GCJ java sources for use in IDEs like eclipse and netbeans These are the java source files packaged as a zip file for use in development environments like eclipse and netbeans. +')`'dnl ifenabled(`gcjdoc',` Package: libgcj-doc @@ -2383,6 +2656,7 @@ Depends: gcj`'PV-base (>= ${gcj:SoftVersion}), ${misc:Depends} Enhances: libgcj`'GCJ_SO-dev Provides: classpath-doc +BUILT_USING`'dnl Description: libgcj API documentation and example programs Autogenerated documentation describing the API of the libgcj library. Sources and precompiled example programs from the classpath library. @@ -2393,7 +2667,7 @@ ifenabled(`c++',` ifenabled(`libcxx',` Package: libstdc++CXX_SO`'LS -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',PRI(important)) Depends: BASEDEP, ${dep:libc}, ${shlibs:Depends}, ${misc:Depends} @@ -2403,6 +2677,7 @@ Breaks: ${multiarch:breaks} ')`Provides: libstdc++'CXX_SO`-armel [armel], libstdc++'CXX_SO`-armhf [armhf]') Conflicts: scim (<< 1.4.2-1) +BUILT_USING`'dnl Description: GNU Standard C++ Library v3`'ifdef(`TARGET)',` (TARGET)', `') This package contains an additional runtime library for C++ programs built with the GNU compiler. @@ -2419,13 +2694,14 @@ ifenabled(`lib32cxx',` Package: lib32stdc++CXX_SO`'LS -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: extra -Depends: BASEDEP, lib32gcc1`'LS, ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, libdep(gcc1,32), ${shlibs:Depends}, ${misc:Depends} Conflicts: ${confl:lib32} ifdef(`TARGET',`Provides: lib32stdc++CXX_SO-TARGET-dcv1 ',`')`'dnl +BUILT_USING`'dnl Description: GNU Standard C++ Library v3 (32 bit Version) This package contains an additional runtime library for C++ programs built with the GNU compiler. @@ -2438,12 +2714,13 @@ ifenabled(`lib64cxx',` Package: lib64stdc++CXX_SO`'LS -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',PRI(optional)) -Depends: BASEDEP, ${shlibs:Depends}, lib64gcc1`'LS, ${misc:Depends} +Depends: BASEDEP, libdep(gcc1,64), ${shlibs:Depends}, ${misc:Depends} ifdef(`TARGET',`Provides: lib64stdc++CXX_SO-TARGET-dcv1 ',`')`'dnl +BUILT_USING`'dnl Description: GNU Standard C++ Library v3`'ifdef(`TARGET)',` (TARGET)', `') (64bit) This package contains an additional runtime library for C++ programs built with the GNU compiler. @@ -2460,12 +2737,13 @@ ifenabled(`libn32cxx',` Package: libn32stdc++CXX_SO`'LS -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',PRI(optional)) -Depends: BASEDEP, ${shlibs:Depends}, libn32gcc1`'LS, ${misc:Depends} +Depends: BASEDEP, libdep(gcc1,n32), ${shlibs:Depends}, ${misc:Depends} ifdef(`TARGET',`Provides: libn32stdc++CXX_SO-TARGET-dcv1 ',`')`'dnl +BUILT_USING`'dnl Description: GNU Standard C++ Library v3`'ifdef(`TARGET)',` (TARGET)', `') (n32) This package contains an additional runtime library for C++ programs built with the GNU compiler. @@ -2482,12 +2760,13 @@ ifenabled(`libx32cxx',` Package: libx32stdc++CXX_SO`'LS -Architecture: ifdef(`TARGET',`all',`biarchx32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',PRI(optional)) -Depends: BASEDEP, ${shlibs:Depends}, libx32gcc1`'LS, ${misc:Depends} +Depends: BASEDEP, libdep(gcc1,x32), ${shlibs:Depends}, ${misc:Depends} ifdef(`TARGET',`Provides: libx32stdc++CXX_SO-TARGET-dcv1 ',`')`'dnl +BUILT_USING`'dnl Description: GNU Standard C++ Library v3`'ifdef(`TARGET)',` (TARGET)', `') (x32) This package contains an additional runtime library for C++ programs built with the GNU compiler. @@ -2504,13 +2783,14 @@ ifenabled(`libhfcxx',` Package: libhfstdc++CXX_SO`'LS -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',PRI(optional)) -Depends: BASEDEP, ${shlibs:Depends}, libhfgcc1`'LS, ${misc:Depends} +Depends: BASEDEP, libdep(gcc1,hf), ${shlibs:Depends}, ${misc:Depends} ifdef(`TARGET',`Provides: libhfstdc++CXX_SO-TARGET-dcv1 ',`')`'dnl ifdef(`TARGET',`dnl',`Conflicts: libstdc++'CXX_SO`-armhf [biarchhf_archs]') +BUILT_USING`'dnl Description: GNU Standard C++ Library v3`'ifdef(`TARGET)',` (TARGET)', `') (hard float ABI) This package contains an additional runtime library for C++ programs built with the GNU compiler. @@ -2527,13 +2807,14 @@ ifenabled(`libsfcxx',` Package: libsfstdc++CXX_SO`'LS -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',PRI(optional)) -Depends: BASEDEP, ${shlibs:Depends}, libsfgcc1`'LS, ${misc:Depends} +Depends: BASEDEP, libdep(gcc1,sf), ${shlibs:Depends}, ${misc:Depends} ifdef(`TARGET',`Provides: libsfstdc++CXX_SO-TARGET-dcv1 ',`')`'dnl ifdef(`TARGET',`dnl',`Conflicts: libstdc++'CXX_SO`-armel [biarchsf_archs]') +BUILT_USING`'dnl Description: GNU Standard C++ Library v3`'ifdef(`TARGET)',` (TARGET)', `') (soft float ABI) This package contains an additional runtime library for C++ programs built with the GNU compiler. @@ -2554,6 +2835,7 @@ Section: libs Priority: extra Depends: BASEDEP, libc6-neon`'LS, libgcc1-neon`'LS, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GNU Standard C++ Library v3 [NEON version] This package contains an additional runtime library for C++ programs built with the GNU compiler. @@ -2564,18 +2846,19 @@ ifenabled(`c++dev',` Package: libstdc++CXX_SO`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same '))`'dnl Section: ifdef(`TARGET',`devel',`libdevel') Priority: ifdef(`TARGET',`extra',PRI(optional)) -Depends: BASEDEP, libgcc`'PV-dev`'LS (= ${gcc:Version}), libstdc++CXX_SO`'LS (>= ${gcc:Version}), ${dep:libcdev}, ${misc:Depends} +Depends: BASEDEP, libdevdep(gcc`'PV-dev,,=), libdep(stdc++CXX_SO,,>=), ${dep:libcdev}, ${misc:Depends} ifdef(`TARGET',`',`dnl native Conflicts: libg++27-dev, libg++272-dev (<< 2.7.2.8-1), libstdc++2.8-dev, libg++2.8-dev, libstdc++2.9-dev, libstdc++2.9-glibc2.1-dev, libstdc++2.10-dev (<< 1:2.95.3-2), libstdc++3.0-dev Replaces: g++`'PV (<< ${gcc:SplitVersion}) Suggests: libstdc++CXX_SO`'PV-doc ')`'dnl native Provides: libstdc++-dev`'LS`'ifdef(`TARGET',`, libstdc++-dev-TARGET-dcv1, libstdc++CXX_SO-dev-TARGET-dcv1') +BUILT_USING`'dnl Description: GNU Standard C++ Library v3 (development files)`'ifdef(`TARGET)',` (TARGET)', `') This package contains the headers and static library files necessary for building C++ programs which use libstdc++. @@ -2590,14 +2873,15 @@ ')`'dnl Package: libstdc++CXX_SO`'PV-pic`'LS -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same '))`'dnl Section: ifdef(`TARGET',`devel',`libdevel') Priority: extra -Depends: BASEDEP, libstdc++CXX_SO`'LS (>= ${gcc:Version}), libstdc++CXX_SO`'PV-dev`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(stdc++CXX_SO,,>=), libdevdep(stdc++CXX_SO`'PV-dev,,=), ${misc:Depends} ifdef(`TARGET',`Provides: libstdc++CXX_SO-pic-TARGET-dcv1 ',`')`'dnl +BUILT_USING`'dnl Description: GNU Standard C++ Library v3 (shared library subset kit)`'ifdef(`TARGET)',` (TARGET)', `') This is used to develop subsets of the libstdc++ shared libraries for use on custom installation floppies and in embedded systems. @@ -2610,16 +2894,17 @@ ')`'dnl Package: libstdc++CXX_SO`'PV-dbg`'LS -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') Section: debug Priority: extra -Depends: BASEDEP, libstdc++CXX_SO`'LS (>= ${gcc:Version}), libgcc`'GCC_SO-dbg`'LS, ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, libdep(stdc++CXX_SO,,>=), libdbgdep(gcc`'GCC_SO-dbg,,>=,${gcc:EpochVersion}), ${shlibs:Depends}, ${misc:Depends} ifdef(`TARGET',`Provides: libstdc++CXX_SO-dbg-TARGET-dcv1',`dnl ifdef(`MULTIARCH', `Multi-Arch: same',`dnl') Provides: libstdc++'CXX_SO`'PV`-dbg-armel [armel], libstdc++'CXX_SO`'PV`-dbg-armhf [armhf]dnl ') -Recommends: libstdc++CXX_SO`'PV-dev`'LS (= ${gcc:Version}) +Recommends: libdevdep(stdc++CXX_SO`'PV-dev,,=) Conflicts: libstdc++5-dbg`'LS, libstdc++5-3.3-dbg`'LS, libstdc++6-dbg`'LS, libstdc++6-4.0-dbg`'LS, libstdc++6-4.1-dbg`'LS, libstdc++6-4.2-dbg`'LS, libstdc++6-4.3-dbg`'LS, libstdc++6-4.4-dbg`'LS, libstdc++6-4.5-dbg`'LS, libstdc++6-4.6-dbg`'LS +BUILT_USING`'dnl Description: GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `') This package contains the shared library of libstdc++ compiled with debugging symbols. @@ -2630,14 +2915,15 @@ ')`'dnl Package: lib32stdc++CXX_SO`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Section: ifdef(`TARGET',`devel',`libdevel') Priority: ifdef(`TARGET',`extra',PRI(optional)) -Depends: BASEDEP, lib32gcc`'PV-dev`'LS (= ${gcc:Version}), lib32stdc++CXX_SO`'LS (>= ${gcc:Version}), libstdc++CXX_SO`'PV-dev (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdevdep(gcc`'PV-dev,32,=), libdep(stdc++CXX_SO,32,>=), libdevdep(stdc++CXX_SO`'PV-dev,,=), ${misc:Depends} ifdef(`TARGET',`',`dnl native Replaces: libstdc++CXX_SO`'PV-dev (<< ${gcc:SplitVersion}), g++`'PV-multilib (<< ${gcc:SplitVersion}) Breaks: libstdc++CXX_SO`'PV-dev (<< ${gcc:SplitVersion}), g++`'PV-multilib (<< ${gcc:SplitVersion}) ')`'dnl native +BUILT_USING`'dnl Description: GNU Standard C++ Library v3 (development files)`'ifdef(`TARGET',` (TARGET)', `') This package contains the headers and static library files necessary for building C++ programs which use libstdc++. @@ -2652,13 +2938,14 @@ ')`'dnl Package: lib32stdc++CXX_SO`'PV-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Section: debug Priority: extra -Depends: BASEDEP, lib32stdc++CXX_SO`'LS (>= ${gcc:Version}), libstdc++CXX_SO`'PV-dev`'LS (= ${gcc:Version}), lib32gcc`'GCC_SO-dbg`'LS, ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, libdep(stdc++CXX_SO,32,>=), libdevdep(stdc++CXX_SO`'PV-dev,,=), libdbgdep(gcc`'GCC_SO-dbg,32,>=,${gcc:EpochVersion}), ${shlibs:Depends}, ${misc:Depends} ifdef(`TARGET',`Provides: lib32stdc++CXX_SO-dbg-TARGET-dcv1 ',`')`'dnl Conflicts: lib32stdc++6-dbg`'LS, lib32stdc++6-4.0-dbg`'LS, lib32stdc++6-4.1-dbg`'LS, lib32stdc++6-4.2-dbg`'LS, lib32stdc++6-4.3-dbg`'LS, lib32stdc++6-4.4-dbg`'LS, lib32stdc++6-4.5-dbg`'LS, lib32stdc++6-4.6-dbg`'LS +BUILT_USING`'dnl Description: GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `') This package contains the shared library of libstdc++ compiled with debugging symbols. @@ -2669,14 +2956,15 @@ ')`'dnl Package: lib64stdc++CXX_SO`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Section: ifdef(`TARGET',`devel',`libdevel') Priority: ifdef(`TARGET',`extra',PRI(optional)) -Depends: BASEDEP, lib64gcc`'PV-dev`'LS (= ${gcc:Version}), lib64stdc++CXX_SO`'LS (>= ${gcc:Version}), libstdc++CXX_SO`'PV-dev (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdevdep(gcc`'PV-dev,64,=), libdep(stdc++CXX_SO,64,>=), libdevdep(stdc++CXX_SO`'PV-dev,,=), ${misc:Depends} ifdef(`TARGET',`',`dnl native Replaces: libstdc++CXX_SO`'PV-dev (<< ${gcc:SplitVersion}), g++`'PV-multilib (<< ${gcc:SplitVersion}) Breaks: libstdc++CXX_SO`'PV-dev (<< ${gcc:SplitVersion}), g++`'PV-multilib (<< ${gcc:SplitVersion}) ')`'dnl native +BUILT_USING`'dnl Description: GNU Standard C++ Library v3 (development files)`'ifdef(`TARGET',` (TARGET)', `') This package contains the headers and static library files necessary for building C++ programs which use libstdc++. @@ -2691,13 +2979,14 @@ ')`'dnl Package: lib64stdc++CXX_SO`'PV-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Section: debug Priority: extra -Depends: BASEDEP, lib64stdc++CXX_SO`'LS (>= ${gcc:Version}), libstdc++CXX_SO`'PV-dev`'LS (= ${gcc:Version}), lib64gcc`'GCC_SO-dbg`'LS, ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, libdep(stdc++CXX_SO,64,>=), libdevdep(stdc++CXX_SO`'PV-dev,,=), libdbgdep(gcc`'GCC_SO-dbg,64,>=,${gcc:EpochVersion}), ${shlibs:Depends}, ${misc:Depends} ifdef(`TARGET',`Provides: lib64stdc++CXX_SO-dbg-TARGET-dcv1 ',`')`'dnl Conflicts: lib64stdc++6-dbg`'LS, lib64stdc++6-4.0-dbg`'LS, lib64stdc++6-4.1-dbg`'LS, lib64stdc++6-4.2-dbg`'LS, lib64stdc++6-4.3-dbg`'LS, lib64stdc++6-4.4-dbg`'LS, lib64stdc++6-4.5-dbg`'LS, lib64stdc++6-4.6-dbg`'LS +BUILT_USING`'dnl Description: GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `') This package contains the shared library of libstdc++ compiled with debugging symbols. @@ -2708,14 +2997,15 @@ ')`'dnl Package: libn32stdc++CXX_SO`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Section: ifdef(`TARGET',`devel',`libdevel') Priority: ifdef(`TARGET',`extra',PRI(optional)) -Depends: BASEDEP, libn32gcc`'PV-dev`'LS (= ${gcc:Version}), libn32stdc++CXX_SO`'LS (>= ${gcc:Version}), libstdc++CXX_SO`'PV-dev (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdevdep(gcc`'PV-dev,n32,=), libdep(stdc++CXX_SO,n32,>=), libdevdep(stdc++CXX_SO`'PV-dev,,=), ${misc:Depends} ifdef(`TARGET',`',`dnl native Replaces: libstdc++CXX_SO`'PV-dev (<< ${gcc:SplitVersion}), g++`'PV-multilib (<< ${gcc:SplitVersion}) Breaks: libstdc++CXX_SO`'PV-dev (<< ${gcc:SplitVersion}), g++`'PV-multilib (<< ${gcc:SplitVersion}) ')`'dnl native +BUILT_USING`'dnl Description: GNU Standard C++ Library v3 (development files)`'ifdef(`TARGET',` (TARGET)', `') This package contains the headers and static library files necessary for building C++ programs which use libstdc++. @@ -2730,13 +3020,14 @@ ')`'dnl Package: libn32stdc++CXX_SO`'PV-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Section: debug Priority: extra -Depends: BASEDEP, libn32stdc++CXX_SO`'LS (>= ${gcc:Version}), libstdc++CXX_SO`'PV-dev`'LS (= ${gcc:Version}), libn32gcc`'GCC_SO-dbg`'LS, ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, libdep(stdc++CXX_SO,n32,>=), libdevdep(stdc++CXX_SO`'PV-dev,,=), libdbgdep(gcc`'GCC_SO-dbg,n32,>=,${gcc:EpochVersion}), ${shlibs:Depends}, ${misc:Depends} ifdef(`TARGET',`Provides: libn32stdc++CXX_SO-dbg-TARGET-dcv1 ',`')`'dnl Conflicts: libn32stdc++6-dbg`'LS, libn32stdc++6-4.0-dbg`'LS, libn32stdc++6-4.1-dbg`'LS, libn32stdc++6-4.2-dbg`'LS, libn32stdc++6-4.3-dbg`'LS, libn32stdc++6-4.4-dbg`'LS, libn32stdc++6-4.5-dbg`'LS, libn32stdc++6-4.6-dbg`'LS +BUILT_USING`'dnl Description: GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `') This package contains the shared library of libstdc++ compiled with debugging symbols. @@ -2746,16 +3037,17 @@ environment. ')`'dnl -ifenabled(`libx32cxx',` +ifenabled(`libx32dbgcxx',` Package: libx32stdc++CXX_SO`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`biarchx32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') Section: ifdef(`TARGET',`devel',`libdevel') Priority: ifdef(`TARGET',`extra',PRI(optional)) -Depends: BASEDEP, libx32gcc`'PV-dev`'LS (= ${gcc:Version}), libx32stdc++CXX_SO`'LS (>= ${gcc:Version}), libstdc++CXX_SO`'PV-dev (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdevdep(gcc`'PV-dev,x32,=), libdep(stdc++CXX_SO,x32,>=), libdevdep(stdc++CXX_SO`'PV-dev,,=), ${misc:Depends} ifdef(`TARGET',`',`dnl native Replaces: libstdc++CXX_SO`'PV-dev (<< ${gcc:SplitVersion}), g++`'PV-multilib (<< ${gcc:SplitVersion}) Breaks: libstdc++CXX_SO`'PV-dev (<< ${gcc:SplitVersion}), g++`'PV-multilib (<< ${gcc:SplitVersion}) ')`'dnl native +BUILT_USING`'dnl Description: GNU Standard C++ Library v3 (development files)`'ifdef(`TARGET',` (TARGET)', `') This package contains the headers and static library files necessary for building C++ programs which use libstdc++. @@ -2770,13 +3062,14 @@ ')`'dnl Package: libx32stdc++CXX_SO`'PV-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchx32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') Section: debug Priority: extra -Depends: BASEDEP, libx32stdc++CXX_SO`'LS (>= ${gcc:Version}), libstdc++CXX_SO`'PV-dev`'LS (= ${gcc:Version}), libx32gcc`'GCC_SO-dbg`'LS, ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, libdep(stdc++CXX_SO,x32,>=), libdevdep(stdc++CXX_SO`'PV-dev,,=), libdbgdep(gcc`'GCC_SO-dbg,x32,>=,${gcc:EpochVersion}), ${shlibs:Depends}, ${misc:Depends} ifdef(`TARGET',`Provides: libx32stdc++CXX_SO-dbg-TARGET-dcv1 ',`')`'dnl Conflicts: libx32stdc++6-dbg`'LS, libx32stdc++6-4.0-dbg`'LS, libx32stdc++6-4.1-dbg`'LS, libx32stdc++6-4.2-dbg`'LS, libx32stdc++6-4.3-dbg`'LS, libx32stdc++6-4.4-dbg`'LS, libx32stdc++6-4.5-dbg`'LS, libx32stdc++6-4.6-dbg`'LS +BUILT_USING`'dnl Description: GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `') This package contains the shared library of libstdc++ compiled with debugging symbols. @@ -2789,14 +3082,15 @@ ifenabled(`libhfdbgcxx',` Package: libhfstdc++CXX_SO`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Section: ifdef(`TARGET',`devel',`libdevel') Priority: ifdef(`TARGET',`extra',PRI(optional)) -Depends: BASEDEP, libhfgcc`'PV-dev`'LS (= ${gcc:Version}), libhfstdc++CXX_SO`'LS (>= ${gcc:Version}), libstdc++CXX_SO`'PV-dev (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdevdep(gcc`'PV-dev,hf,=), libdep(stdc++CXX_SO,,>=), libdevdep(stdc++CXX_SO`'PV-dev,,=), ${misc:Depends} ifdef(`TARGET',`',`dnl native Replaces: libstdc++CXX_SO`'PV-dev (<< ${gcc:SplitVersion}), g++`'PV-multilib (<< ${gcc:SplitVersion}) Breaks: libstdc++CXX_SO`'PV-dev (<< ${gcc:SplitVersion}), g++`'PV-multilib (<< ${gcc:SplitVersion}) ')`'dnl native +BUILT_USING`'dnl Description: GNU Standard C++ Library v3 (development files)`'ifdef(`TARGET',` (TARGET)', `') This package contains the headers and static library files necessary for building C++ programs which use libstdc++. @@ -2811,13 +3105,14 @@ ')`'dnl Package: libhfstdc++CXX_SO`'PV-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Section: debug Priority: extra -Depends: BASEDEP, libhfstdc++CXX_SO`'LS (>= ${gcc:Version}), libstdc++CXX_SO`'PV-dev`'LS (= ${gcc:Version}), libhfgcc`'GCC_SO-dbg`'LS, ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, libdep(stdc++CXX_SO,hf,>=), libdevdep(stdc++CXX_SO`'PV-dev,,=), libdbgdep(gcc`'GCC_SO-dbg,hf,>=,${gcc:EpochVersion}), ${shlibs:Depends}, ${misc:Depends} ifdef(`TARGET',`Provides: libhfstdc++CXX_SO-dbg-TARGET-dcv1 ',`')`'dnl ifdef(`TARGET',`dnl',`Conflicts: libhfstdc++6-dbg`'LS, libhfstdc++6-4.3-dbg`'LS, libhfstdc++6-4.4-dbg`'LS, libhfstdc++6-4.5-dbg`'LS, libhfstdc++6-4.6-dbg`'LS, libstdc++'CXX_SO`-armhf [biarchhf_archs]') +BUILT_USING`'dnl Description: GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `') This package contains the shared library of libstdc++ compiled with debugging symbols. @@ -2830,14 +3125,15 @@ ifenabled(`libsfdbgcxx',` Package: libsfstdc++CXX_SO`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Section: ifdef(`TARGET',`devel',`libdevel') Priority: ifdef(`TARGET',`extra',PRI(optional)) -Depends: BASEDEP, libsfgcc`'PV-dev`'LS (= ${gcc:Version}), libsfstdc++CXX_SO`'LS (>= ${gcc:Version}), libstdc++CXX_SO`'PV-dev (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdevdep(gcc`'PV-dev,sf,=), libdep(stdc++CXX_SO,sf,>=), libdevdep(stdc++CXX_SO`'PV-dev,,=), ${misc:Depends} ifdef(`TARGET',`',`dnl native Replaces: libstdc++CXX_SO`'PV-dev (<< ${gcc:SplitVersion}), g++`'PV-multilib (<< ${gcc:SplitVersion}) Breaks: libstdc++CXX_SO`'PV-dev (<< ${gcc:SplitVersion}), g++`'PV-multilib (<< ${gcc:SplitVersion}) ')`'dnl native +BUILT_USING`'dnl Description: GNU Standard C++ Library v3 (development files)`'ifdef(`TARGET',` (TARGET)', `') This package contains the headers and static library files necessary for building C++ programs which use libstdc++. @@ -2852,13 +3148,14 @@ ')`'dnl Package: libsfstdc++CXX_SO`'PV-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Section: debug Priority: extra -Depends: BASEDEP, libsfstdc++CXX_SO`'LS (>= ${gcc:Version}), libstdc++CXX_SO`'PV-dev`'LS (= ${gcc:Version}), libsfgcc`'GCC_SO-dbg`'LS, ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, libdep(stdc++CXX_SO,sf,>=), libdevdep(stdc++CXX_SO`'PV-dev,,=), libdbgdep(gcc`'GCC_SO-dbg,sf,>=,${gcc:EpochVersion}), ${shlibs:Depends}, ${misc:Depends} ifdef(`TARGET',`Provides: libsfstdc++CXX_SO-dbg-TARGET-dcv1 ',`')`'dnl ifdef(`TARGET',`dnl',`Conflicts: libsfstdc++6-dbg`'LS, libsfstdc++6-4.3-dbg`'LS, libsfstdc++6-4.4-dbg`'LS, libsfstdc++6-4.5-dbg`'LS, libsfstdc++6-4.6-dbg`'LS, libstdc++'CXX_SO`-armel [biarchsf_archs]') +BUILT_USING`'dnl Description: GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `') This package contains the shared library of libstdc++ compiled with debugging symbols. @@ -2897,6 +3194,7 @@ Suggests: gnat`'PV-doc, ada-reference-manual-html, ada-reference-manual-info, ada-reference-manual-pdf, ada-reference-manual-text, gnat`'-GNAT_V-sjlj Provides: ada-compiler Conflicts: gnat (<< 4.1), gnat-3.1, gnat-3.2, gnat-3.3, gnat-3.4, gnat-3.5, gnat-4.0, gnat-4.1, gnat-4.2, gnat-4.3, gnat-4.4, gnat-4.6 +BUILT_USING`'dnl Description: GNU Ada compiler GNAT is a compiler for the Ada programming language. It produces optimized code on platforms supported by the GNU Compiler Collection (GCC). @@ -2910,6 +3208,7 @@ ifdef(`MULTIARCH', `Pre-Depends: multiarch-support ')`'dnl Depends: gnat`'PV-base (= ${gnat:Version}), gnat`'-GNAT_V (= ${gnat:Version}), ${misc:Depends} +BUILT_USING`'dnl Description: GNU Ada compiler (setjump/longjump runtime library) GNAT is a compiler for the Ada programming language. It produces optimized code on platforms supported by the GNU Compiler Collection (GCC). @@ -2927,6 +3226,7 @@ '))`'dnl Priority: PRI(optional) Depends: gnat`'PV-base (= ${gnat:Version}), ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: runtime for applications compiled with GNAT (shared library) GNAT is a compiler for the Ada programming language. It produces optimized code on platforms supported by the GNU Compiler Collection (GCC). @@ -2944,6 +3244,7 @@ '))`'dnl Priority: extra Depends: gnat`'PV-base (= ${gnat:Version}), libgnat`'-GNAT_V (= ${gnat:Version}), ${misc:Depends} +BUILT_USING`'dnl Description: runtime for applications compiled with GNAT (debugging symbols) GNAT is a compiler for the Ada programming language. It produces optimized code on platforms supported by the GNU Compiler Collection (GCC). @@ -2960,6 +3261,7 @@ Depends: gnat`'PV-base (= ${gnat:Version}), gnat`'PV (= ${gnat:Version}), ada-compiler, libgnatvsn`'GNAT_V (= ${gnat:Version}), ${misc:Depends} Conflicts: libgnatvsn-dev (<< `'GNAT_V), libgnatvsn4.1-dev, libgnatvsn4.3-dev, libgnatvsn4.4-dev, libgnatvsn4.5-dev, libgnatvsn4.6-dev +BUILT_USING`'dnl Description: GNU Ada compiler selected components (development files) GNAT is a compiler for the Ada programming language. It produces optimized code on platforms supported by the GNU Compiler Collection (GCC). @@ -2978,6 +3280,7 @@ Priority: PRI(optional) Section: libs Depends: gnat`'PV-base (= ${gnat:Version}), libgnat`'-GNAT_V (= ${gnat:Version}), ${misc:Depends} +BUILT_USING`'dnl Description: GNU Ada compiler selected components (shared library) GNAT is a compiler for the Ada programming language. It produces optimized code on platforms supported by the GNU Compiler Collection (GCC). @@ -2997,6 +3300,7 @@ Section: debug Depends: gnat`'PV-base (= ${gnat:Version}), libgnatvsn`'GNAT_V (= ${gnat:Version}), ${misc:Depends} Suggests: gnat, ada-compiler +BUILT_USING`'dnl Description: GNU Ada compiler selected components (debugging symbols) GNAT is a compiler for the Ada programming language. It produces optimized code on platforms supported by the GNU Compiler Collection (GCC). @@ -3014,6 +3318,7 @@ Depends: gnat`'PV-base (= ${gnat:Version}), gnat`'PV (= ${gnat:Version}), ada-compiler, libgnatprj`'GNAT_V (= ${gnat:Version}), libgnatvsn`'GNAT_V-dev (= ${gnat:Version}), ${misc:Depends} Conflicts: libgnatprj-dev (<< `'GNAT_V), libgnatprj4.1-dev, libgnatprj4.3-dev, libgnatprj4.4-dev, libgnatprj4.5-dev, libgnatprj4.6-dev +BUILT_USING`'dnl Description: GNU Ada compiler Project Manager (development files) GNAT is a compiler for the Ada programming language. It produces optimized code on platforms supported by the GNU Compiler Collection (GCC). @@ -3035,6 +3340,7 @@ Priority: PRI(optional) Section: libs Depends: gnat`'PV-base (= ${gnat:Version}), libgnat`'-GNAT_V (= ${gnat:Version}), libgnatvsn`'GNAT_V (= ${gnat:Version}), ${misc:Depends} +BUILT_USING`'dnl Description: GNU Ada compiler Project Manager (shared library) GNAT is a compiler for the Ada programming language. It produces optimized code on platforms supported by the GNU Compiler Collection (GCC). @@ -3057,6 +3363,7 @@ Section: debug Depends: gnat`'PV-base (= ${gnat:Version}), libgnatprj`'GNAT_V (= ${gnat:Version}), ${misc:Depends} Suggests: gnat, ada-compiler +BUILT_USING`'dnl Description: GNU Ada compiler Project Manager (debugging symbols) GNAT is a compiler for the Ada programming language. It produces optimized code on platforms supported by the GNU Compiler Collection (GCC). @@ -3077,6 +3384,7 @@ Architecture: biarch64_archs Priority: PRI(optional) Depends: gnat`'PV-base (= ${gnat:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: runtime for applications compiled with GNAT (64 bits shared library) GNAT is a compiler for the Ada programming language. It produces optimized code on platforms supported by the GNU Compiler Collection (GCC). @@ -3095,6 +3403,7 @@ Depends: dpkg (>= 1.15.4) | install-info, ${misc:Depends} Suggests: gnat`'PV Conflicts: gnat-4.1-doc, gnat-4.2-doc, gnat-4.3-doc, gnat-4.4-doc, gnat-4.6-doc +BUILT_USING`'dnl Description: GNU Ada compiler (documentation) GNAT is a compiler for the Ada programming language. It produces optimized code on platforms supported by the GNU Compiler Collection (GCC). @@ -3113,6 +3422,7 @@ Depends: SOFTBASEDEP, g++`'PV (>= ${gcc:SoftVersion}), libphobos`'PHOBOS_V`'PV-dev (= ${gdc:Version}) [libphobos_no_archs], ${shlibs:Depends}, ${misc:Depends} Provides: gdc, d-compiler, d-v2-compiler Replaces: gdc (<< 4.4.6-5) +BUILT_USING`'dnl Description: GNU D compiler (version 2), based on the GCC backend This is the GNU D compiler, which compiles D on platforms supported by gcc. It uses the gcc backend to generate optimised code. @@ -3126,6 +3436,7 @@ Priority: PRI(optional) Depends: gdc`'PV`'TS (= ${gdc:Version}), zlib1g-dev, ${shlibs:Depends}, ${misc:Depends} Provides: libphobos`'PHOBOS_V`'TS-dev +BUILT_USING`'dnl Description: Phobos D standard library This is the Phobos standard library that comes with the D2 compiler. . @@ -3133,10 +3444,11 @@ Package: libphobos`'PHOBOS_V`'PV`'TS-dbg Section: debug -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') Priority: extra Depends: gdc`'PV`'TS (= ${gdc:Version}), libphobos`'PHOBOS_V`'PV-dev (= ${gdc:Version}), ${misc:Depends} Provides: libphobos`'PHOBOS_V`'TS-dbg +BUILT_USING`'dnl Description: The Phobos D standard library (debug symbols) This is the Phobos standard library that comes with the D2 compiler. . @@ -3151,6 +3463,7 @@ Priority: PRI(optional) Depends: BASEDEP, ifenabled(`cdev',`gcc`'PV (= ${gcc:Version}),') ${shlibs:Depends}, ${misc:Depends} Conflicts: gcc-4.4-soft-float, gcc-4.5-soft-float, gcc-4.6-soft-float +BUILT_USING`'dnl Description: GCC soft-floating-point gcc libraries (ARM) These are versions of basic static libraries such as libgcc.a compiled with the -msoft-float option, for CPUs without a floating-point unit. @@ -3162,6 +3475,7 @@ Architecture: any Priority: PRI(optional) Depends: BASEDEP, gcc`'PV (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: Fix non-ANSI header files FixIncludes was created to fix non-ANSI system header files. Many system manufacturers supply proprietary headers that are not ANSI compliant. @@ -3196,6 +3510,7 @@ Priority: PRI(optional) Depends: BASEDEP, ${shlibs:Depends}ifenabled(`cdev',`, gcc`'PV (= ${gcc:Version})'), ${misc:Depends} Conflicts: gcc-3.2-nof +BUILT_USING`'dnl Description: GCC no-floating-point gcc libraries (powerpc) These are versions of basic static libraries such as libgcc.a compiled with the -msoft-float option, for CPUs without a floating-point unit. diff -Nru gcc-4.7-4.7.2/debian/gccgo-BV-doc.doc-base gcc-4.7-4.7.3/debian/gccgo-BV-doc.doc-base --- gcc-4.7-4.7.2/debian/gccgo-BV-doc.doc-base 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/gccgo-BV-doc.doc-base 2013-06-25 15:26:04.000000000 +0000 @@ -0,0 +1,17 @@ +Document: gccgo-@BV@ +Title: The GNU Go compiler (version @BV@) +Author: Various +Abstract: This manual describes how to use gccgo, the GNU compiler for + the Go programming language. This manual is specifically about + gccgo. For more information about the Go programming + language in general, including language specifications and standard + package documentation, see http://golang.org/. +Section: Programming + +Format: html +Index: /usr/share/doc/gcc-@BV@-base/gccgo.html +Files: /usr/share/doc/gcc-@BV@-base/gccgo.html + +Format: info +Index: /usr/share/info/gccgo-@BV@.info.gz +Files: /usr/share/info/gccgo-@BV@* diff -Nru gcc-4.7-4.7.2/debian/gccgo-BV.doc-base gcc-4.7-4.7.3/debian/gccgo-BV.doc-base --- gcc-4.7-4.7.2/debian/gccgo-BV.doc-base 2013-06-25 15:26:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/gccgo-BV.doc-base 1970-01-01 00:00:00.000000000 +0000 @@ -1,17 +0,0 @@ -Document: gccgo-@BV@ -Title: The GNU Go compiler (version @BV@) -Author: Various -Abstract: This manual describes how to use gccgo, the GNU compiler for - the Go programming language. This manual is specifically about - gccgo. For more information about the Go programming - language in general, including language specifications and standard - package documentation, see http://golang.org/. -Section: Programming - -Format: html -Index: /usr/share/doc/gcc-@BV@-base/gccgo.html -Files: /usr/share/doc/gcc-@BV@-base/gccgo.html - -Format: info -Index: /usr/share/info/gccgo-@BV@.info.gz -Files: /usr/share/info/gccgo-@BV@* diff -Nru gcc-4.7-4.7.2/debian/gcj-BV-jre-headless.overrides gcc-4.7-4.7.3/debian/gcj-BV-jre-headless.overrides --- gcc-4.7-4.7.2/debian/gcj-BV-jre-headless.overrides 2013-06-25 15:26:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/gcj-BV-jre-headless.overrides 2013-06-25 15:26:04.000000000 +0000 @@ -1,2 +1,5 @@ # pick up the exact version, in case another gcj version is installed gcj-@BV@-jre-headless binary: binary-or-shlib-defines-rpath + +# don't strip the binaries, keep the libgcj13-dbg package Multi-Arch: same +gcj-@BV@-jre-headless binary: unstripped-binary-or-object diff -Nru gcc-4.7-4.7.2/debian/lib64stdc++6.symbols.sparc gcc-4.7-4.7.3/debian/lib64stdc++6.symbols.sparc --- gcc-4.7-4.7.2/debian/lib64stdc++6.symbols.sparc 2013-06-25 15:26:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/lib64stdc++6.symbols.sparc 2013-06-25 15:26:04.000000000 +0000 @@ -1,5 +1,6 @@ libstdc++.so.6 lib64stdc++6 #MINVER# #include "libstdc++6.symbols.64bit" +#include "libstdc++6.symbols.128bit" #include "libstdc++6.symbols.excprop" _ZN9__gnu_cxx12__atomic_addEPVli@GLIBCXX_3.4 4.1.1 _ZN9__gnu_cxx18__exchange_and_addEPVli@GLIBCXX_3.4 4.1.1 diff -Nru gcc-4.7-4.7.2/debian/libgcc1.symbols.aeabi gcc-4.7-4.7.3/debian/libgcc1.symbols.aeabi --- gcc-4.7-4.7.2/debian/libgcc1.symbols.aeabi 2013-06-25 15:26:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/libgcc1.symbols.aeabi 2013-06-25 15:26:04.000000000 +0000 @@ -61,6 +61,8 @@ __aeabi_ulcmp@GCC_3.5 1:4.4.0 __aeabi_uldivmod@GCC_3.5 1:4.4.0 __aeabi_unwind_cpp_pr0@GCC_3.5 1:4.4.0 + __aeabi_unwind_cpp_pr1@GCC_3.5 1:4.4.0 + __aeabi_unwind_cpp_pr2@GCC_3.5 1:4.4.0 __aeabi_uread4@GCC_3.5 1:4.4.0 __aeabi_uread8@GCC_3.5 1:4.4.0 __aeabi_uwrite4@GCC_3.5 1:4.4.0 diff -Nru gcc-4.7-4.7.2/debian/libstdc++6.symbols.sparc gcc-4.7-4.7.3/debian/libstdc++6.symbols.sparc --- gcc-4.7-4.7.2/debian/libstdc++6.symbols.sparc 2013-06-25 15:26:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/libstdc++6.symbols.sparc 2013-06-25 15:26:04.000000000 +0000 @@ -4,6 +4,5 @@ __gxx_personality_v0@CXXABI_1.3 4.1.1 #include "libstdc++6.symbols.glibcxxmath" #include "libstdc++6.symbols.ldbl.32bit" -#include "libstdc++6.symbols.128bit" _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2 _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2 diff -Nru gcc-4.7-4.7.2/debian/libstdc++6.symbols.sparc64 gcc-4.7-4.7.3/debian/libstdc++6.symbols.sparc64 --- gcc-4.7-4.7.2/debian/libstdc++6.symbols.sparc64 2013-06-25 15:26:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/libstdc++6.symbols.sparc64 2013-06-25 15:26:04.000000000 +0000 @@ -1,6 +1,7 @@ libstdc++.so.6 libstdc++6 #MINVER# #include "libstdc++6.symbols.64bit" #include "libstdc++6.symbols.excprop" +#include "libstdc++6.symbols.128bit" _ZN9__gnu_cxx12__atomic_addEPVli@GLIBCXX_3.4 4.1.1 _ZN9__gnu_cxx18__exchange_and_addEPVli@GLIBCXX_3.4 4.1.1 # FIXME: Currently no ldbl symbols in the 64bit libstdc++ on sparc. diff -Nru gcc-4.7-4.7.2/debian/patches/ada-link-shlib.diff gcc-4.7-4.7.3/debian/patches/ada-link-shlib.diff --- gcc-4.7-4.7.2/debian/patches/ada-link-shlib.diff 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/ada-link-shlib.diff 2013-06-25 15:26:04.000000000 +0000 @@ -0,0 +1,85 @@ +# DP: In gnatlink, pass the options and libraries after objects to the +# DP: linker to avoid link failures with --as-needed. Closes: #680292. + +--- a/src/gcc/ada/mlib-tgt-specific-linux.adb ++++ b/src/gcc/ada/mlib-tgt-specific-linux.adb +@@ -81,19 +81,54 @@ + Version_Arg : String_Access; + Symbolic_Link_Needed : Boolean := False; + ++ N_Options : Argument_List := Options; ++ Options_Last : Natural := N_Options'Last; ++ -- After moving -lxxx to Options_2, N_Options up to index Options_Last ++ -- will contain the Options to pass to MLib.Utl.Gcc. ++ ++ Real_Options_2 : Argument_List (1 .. Options'Length); ++ Real_Options_2_Last : Natural := 0; ++ -- Real_Options_2 up to index Real_Options_2_Last will contain the ++ -- Options_2 to pass to MLib.Utl.Gcc. ++ + begin + if Opt.Verbose_Mode then + Write_Str ("building relocatable shared library "); + Write_Line (Lib_Path); + end if; + ++ -- Move all -lxxx to Options_2 ++ ++ declare ++ Index : Natural := N_Options'First; ++ Arg : String_Access; ++ ++ begin ++ while Index <= Options_Last loop ++ Arg := N_Options (Index); ++ ++ if Arg'Length > 2 ++ and then Arg (Arg'First .. Arg'First + 1) = "-l" ++ then ++ Real_Options_2_Last := Real_Options_2_Last + 1; ++ Real_Options_2 (Real_Options_2_Last) := Arg; ++ N_Options (Index .. Options_Last - 1) := ++ N_Options (Index + 1 .. Options_Last); ++ Options_Last := Options_Last - 1; ++ ++ else ++ Index := Index + 1; ++ end if; ++ end loop; ++ end; ++ + if Lib_Version = "" then + Utl.Gcc + (Output_File => Lib_Path, + Objects => Ofiles, +- Options => Options, ++ Options => N_Options (N_Options'First .. Options_Last), + Driver_Name => Driver_Name, +- Options_2 => No_Argument_List); ++ Options_2 => Real_Options_2 (1 .. Real_Options_2_Last)); + + else + declare +@@ -111,18 +146,18 @@ + Utl.Gcc + (Output_File => Lib_Version, + Objects => Ofiles, +- Options => Options & Version_Arg, ++ Options => N_Options (N_Options'First .. Options_Last) & Version_Arg, + Driver_Name => Driver_Name, +- Options_2 => No_Argument_List); ++ Options_2 => Real_Options_2 (1 .. Real_Options_2_Last)); + Symbolic_Link_Needed := Lib_Version /= Lib_Path; + + else + Utl.Gcc + (Output_File => Lib_Dir & Directory_Separator & Lib_Version, + Objects => Ofiles, +- Options => Options & Version_Arg, ++ Options => N_Options (N_Options'First .. Options_Last) & Version_Arg, + Driver_Name => Driver_Name, +- Options_2 => No_Argument_List); ++ Options_2 => Real_Options_2 (1 .. Real_Options_2_Last)); + Symbolic_Link_Needed := + Lib_Dir & Directory_Separator & Lib_Version /= Lib_Path; + end if; diff -Nru gcc-4.7-4.7.2/debian/patches/arm-multilib-defaults.diff gcc-4.7-4.7.3/debian/patches/arm-multilib-defaults.diff --- gcc-4.7-4.7.2/debian/patches/arm-multilib-defaults.diff 2013-06-25 15:26:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/arm-multilib-defaults.diff 2013-06-25 15:26:04.000000000 +0000 @@ -4,7 +4,7 @@ =================================================================== --- a/src/gcc/config.gcc +++ b/src/gcc/config.gcc -@@ -3238,10 +3238,18 @@ +@@ -3129,10 +3129,18 @@ esac case "$with_float" in @@ -25,7 +25,7 @@ *) echo "Unknown floating point type used in --with-float=$with_float" 1>&2 exit 1 -@@ -3285,6 +3293,9 @@ +@@ -3176,6 +3184,9 @@ "" \ | arm | thumb ) #OK diff -Nru gcc-4.7-4.7.2/debian/patches/arm-no-va_list-warn.diff gcc-4.7-4.7.3/debian/patches/arm-no-va_list-warn.diff --- gcc-4.7-4.7.2/debian/patches/arm-no-va_list-warn.diff 2013-06-25 15:26:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/arm-no-va_list-warn.diff 2013-06-25 15:26:04.000000000 +0000 @@ -11,7 +11,7 @@ =================================================================== --- a/src/gcc/config/arm/arm.c +++ b/src/gcc/config/arm/arm.c -@@ -24432,16 +24432,7 @@ +@@ -24495,16 +24495,7 @@ has to be managled as if it is in the "std" namespace. */ if (TARGET_AAPCS_BASED && lang_hooks.types_compatible_p (CONST_CAST_TREE (type), va_list_type)) diff -Nru gcc-4.7-4.7.2/debian/patches/cell-branch-doc.diff gcc-4.7-4.7.3/debian/patches/cell-branch-doc.diff --- gcc-4.7-4.7.2/debian/patches/cell-branch-doc.diff 2013-06-25 15:26:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/cell-branch-doc.diff 1970-01-01 00:00:00.000000000 +0000 @@ -1,2 +0,0 @@ -# DP: Updates from the cell-4_5-branch (documentation) up to 2010xxxx - diff -Nru gcc-4.7-4.7.2/debian/patches/cell-branch.diff gcc-4.7-4.7.3/debian/patches/cell-branch.diff --- gcc-4.7-4.7.2/debian/patches/cell-branch.diff 2013-06-25 15:26:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/cell-branch.diff 1970-01-01 00:00:00.000000000 +0000 @@ -1,4 +0,0 @@ -# DP: Updates from the cell-4_5-branch up to 2010xxxx - -svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_5-branch@xxxx svn://gcc.gnu.org/svn/gcc/branches/cell-4_5-branch - diff -Nru gcc-4.7-4.7.2/debian/patches/config-ml.diff gcc-4.7-4.7.3/debian/patches/config-ml.diff --- gcc-4.7-4.7.2/debian/patches/config-ml.diff 2013-06-25 15:26:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/config-ml.diff 2013-06-25 15:26:04.000000000 +0000 @@ -93,7 +93,7 @@ =================================================================== --- a/src/libstdc++-v3/include/Makefile.am +++ b/src/libstdc++-v3/include/Makefile.am -@@ -829,8 +829,9 @@ +@@ -821,8 +821,9 @@ endif host_srcdir = ${glibcxx_srcdir}/$(OS_INC_SRCDIR) @@ -105,7 +105,7 @@ host_headers = \ ${host_srcdir}/ctype_base.h \ ${host_srcdir}/ctype_inline.h \ -@@ -1050,6 +1051,7 @@ +@@ -1042,6 +1043,7 @@ stamp-${host_alias}: @-mkdir -p ${host_builddir} @@ -117,7 +117,7 @@ =================================================================== --- a/src/libstdc++-v3/include/Makefile.in +++ b/src/libstdc++-v3/include/Makefile.in -@@ -1082,8 +1082,9 @@ +@@ -1066,8 +1066,9 @@ # For --enable-cheaders=c_std @GLIBCXX_C_HEADERS_COMPATIBILITY_TRUE@c_compatibility_headers_extra = ${c_compatibility_headers} host_srcdir = ${glibcxx_srcdir}/$(OS_INC_SRCDIR) @@ -129,7 +129,7 @@ host_headers = \ ${host_srcdir}/ctype_base.h \ ${host_srcdir}/ctype_inline.h \ -@@ -1461,6 +1462,7 @@ +@@ -1445,6 +1446,7 @@ stamp-${host_alias}: @-mkdir -p ${host_builddir} @@ -141,7 +141,7 @@ =================================================================== --- a/src/libstdc++-v3/configure.ac +++ b/src/libstdc++-v3/configure.ac -@@ -458,6 +458,16 @@ +@@ -447,6 +447,16 @@ multilib_arg= fi diff -Nru gcc-4.7-4.7.2/debian/patches/cross-fixes.diff gcc-4.7-4.7.3/debian/patches/cross-fixes.diff --- gcc-4.7-4.7.2/debian/patches/cross-fixes.diff 2013-06-25 15:26:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/cross-fixes.diff 2013-06-25 15:26:04.000000000 +0000 @@ -1,32 +1,17 @@ # DP: Fix the linker error when creating an xcc for ia64 --- - gcc/config/alpha/linux-unwind.h | 3 +++ gcc/config/ia64/fde-glibc.c | 3 +++ gcc/config/ia64/unwind-ia64.c | 3 ++- gcc/unwind-compat.c | 2 ++ gcc/unwind-generic.h | 2 ++ 6 files changed, 14 insertions(+), 1 deletions(-) ---- a/src/libgcc/config/alpha/linux-unwind.h -+++ b/src/libgcc/config/alpha/linux-unwind.h -@@ -29,6 +29,7 @@ Boston, MA 02110-1301, USA. */ - /* Do code reading to identify a signal frame, and set the frame - state data appropriately. See unwind-dw2.c for the structs. */ - -+#ifndef inhibit_libc - #include - #include - -@@ -80,3 +81,5 @@ alpha_fallback_frame_state (struct _Unwind_Context *context, - fs->retaddr_column = 64; - return _URC_NO_REASON; - } -+ -+#endif +Index: b/src/libgcc/config/ia64/fde-glibc.c +=================================================================== --- a/src/libgcc/config/ia64/fde-glibc.c +++ b/src/libgcc/config/ia64/fde-glibc.c -@@ -31,6 +31,7 @@ +@@ -28,6 +28,7 @@ #ifndef _GNU_SOURCE #define _GNU_SOURCE 1 #endif @@ -34,54 +19,60 @@ #include "config.h" #include #include -@@ -162,3 +163,5 @@ _Unwind_FindTableEntry (void *pc, unsigned long *segment_base, - +@@ -160,3 +161,5 @@ + return data.ret; } + +#endif +Index: b/src/libgcc/config/ia64/unwind-ia64.c +=================================================================== --- a/src/libgcc/config/ia64/unwind-ia64.c +++ b/src/libgcc/config/ia64/unwind-ia64.c @@ -27,6 +27,7 @@ - This exception does not however invalidate any other reasons why - the executable file might be covered by the GNU General Public License. */ - + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +#ifndef inhibit_libc #include "tconfig.h" #include "tsystem.h" #include "coretypes.h" -@@ -2417,3 +2417,4 @@ alias (_Unwind_SetIP); +@@ -2469,3 +2470,4 @@ #endif - + #endif +#endif +Index: b/src/libgcc/unwind-compat.c +=================================================================== --- a/src/libgcc/unwind-compat.c +++ b/src/libgcc/unwind-compat.c -@@ -29,6 +29,7 @@ - 02110-1301, USA. */ - +@@ -24,6 +24,7 @@ + . */ + #if defined (USE_GAS_SYMVER) && defined (USE_LIBUNWIND_EXCEPTIONS) +#ifndef inhibit_libc #include "tconfig.h" #include "tsystem.h" #include "unwind.h" -@@ -213,3 +214,4 @@ _Unwind_SetIP (struct _Unwind_Context *context, _Unwind_Ptr val) +@@ -208,3 +209,4 @@ } symver (_Unwind_SetIP, GCC_3.0); #endif +#endif +Index: b/src/libgcc/unwind-generic.h +=================================================================== --- a/src/libgcc/unwind-generic.h +++ b/src/libgcc/unwind-generic.h -@@ -214,6 +214,7 @@ _Unwind_SjLj_Resume_or_Rethrow (struct _Unwind_Exception *); +@@ -211,6 +211,7 @@ compatible with the standard ABI for IA-64, we inline these. */ - + #ifdef __ia64__ +#ifndef inhibit_libc #include - + static inline _Unwind_Ptr -@@ -232,6 +233,7 @@ _Unwind_GetTextRelBase (struct _Unwind_Context *_C __attribute__ ((__unused__))) - +@@ -229,6 +230,7 @@ + /* @@@ Retrieve the Backing Store Pointer of the given context. */ extern _Unwind_Word _Unwind_GetBSP (struct _Unwind_Context *); +#endif diff -Nru gcc-4.7-4.7.2/debian/patches/cross-include.diff gcc-4.7-4.7.3/debian/patches/cross-include.diff --- gcc-4.7-4.7.2/debian/patches/cross-include.diff 2013-06-25 15:26:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/cross-include.diff 1970-01-01 00:00:00.000000000 +0000 @@ -1,18 +0,0 @@ -# DP: Set cross include path to .../include, not .../sys-include -# DP: This should be a fix for famous limits.h issue - ---- - gcc/configure.ac | 2 +- - 1 files changed, 1 insertions(+), 1 deletions(-) - ---- a/src/gcc/configure.ac -+++ b/src/gcc/configure.ac -@@ -764,7 +764,7 @@ AC_ARG_WITH(sysroot, - ], [ - TARGET_SYSTEM_ROOT= - TARGET_SYSTEM_ROOT_DEFINE= -- CROSS_SYSTEM_HEADER_DIR='$(gcc_tooldir)/sys-include' -+ CROSS_SYSTEM_HEADER_DIR='/usr/$(target_noncanonical)/include' - ]) - AC_SUBST(TARGET_SYSTEM_ROOT) - AC_SUBST(TARGET_SYSTEM_ROOT_DEFINE) diff -Nru gcc-4.7-4.7.2/debian/patches/cross-install-location.diff gcc-4.7-4.7.3/debian/patches/cross-install-location.diff --- gcc-4.7-4.7.2/debian/patches/cross-install-location.diff 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/cross-install-location.diff 2013-06-25 15:26:04.000000000 +0000 @@ -0,0 +1,335 @@ +--- a/src/libmudflap/Makefile.in 2012-12-08 08:32:41.301881153 +0100 ++++ b/src/libmudflap/Makefile.in 2012-12-08 08:58:29.281874520 +0100 +@@ -269,7 +269,7 @@ + @LIBMUDFLAPTH_FALSE@libmudflapth = + @LIBMUDFLAPTH_TRUE@libmudflapth = libmudflapth.la + toolexeclib_LTLIBRARIES = libmudflap.la $(libmudflapth) +-libsubincludedir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version)/include ++libsubincludedir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version)/include + nobase_libsubinclude_HEADERS = mf-runtime.h + libmudflap_la_SOURCES = \ + mf-runtime.c \ +--- a/src/libmudflap/Makefile.am 2012-12-08 08:32:41.301881153 +0100 ++++ b/src/libmudflap/Makefile.am 2012-12-08 08:58:04.633876182 +0100 +@@ -23,7 +23,7 @@ + + toolexeclib_LTLIBRARIES = libmudflap.la $(libmudflapth) + target_noncanonical = @target_noncanonical@ +-libsubincludedir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version)/include ++libsubincludedir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version)/include + nobase_libsubinclude_HEADERS = mf-runtime.h + + +--- a/src/fixincludes/Makefile.in 2011-01-03 21:52:22.000000000 +0100 ++++ b/src/fixincludes/Makefile.in 2012-12-08 08:53:27.029874709 +0100 +@@ -52,9 +52,9 @@ + gcc_version := $(shell cat $(srcdir)/../gcc/BASE-VER) + + # Directory in which the compiler finds libraries etc. +-libsubdir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version) ++libsubdir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version) + # Directory in which the compiler finds executables +-libexecsubdir = $(libexecdir)/gcc/$(target_noncanonical)/$(gcc_version) ++libexecsubdir = $(libexecdir)/gcc-cross/$(target_noncanonical)/$(gcc_version) + # Where our executable files go + itoolsdir = $(libexecsubdir)/install-tools + # Where our data files go +--- a/src/libgfortran/Makefile.in 2012-09-20 09:23:55.000000000 +0200 ++++ b/src/libgfortran/Makefile.in 2012-12-08 08:50:26.369874316 +0100 +@@ -499,12 +499,12 @@ + + libgfortran_la_DEPENDENCIES = $(version_dep) libgfortran.spec $(LIBQUADLIB_DEP) + myexeclib_LTLIBRARIES = libgfortranbegin.la +-myexeclibdir = $(libdir)/gcc/$(target_alias)/$(gcc_version)$(MULTISUBDIR) ++myexeclibdir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)$(MULTISUBDIR) + libgfortranbegin_la_SOURCES = fmain.c + libgfortranbegin_la_LDFLAGS = -static + libgfortranbegin_la_LINK = $(LINK) $(libgfortranbegin_la_LDFLAGS) + cafexeclib_LTLIBRARIES = libcaf_single.la +-cafexeclibdir = $(libdir)/gcc/$(target_alias)/$(gcc_version)$(MULTISUBDIR) ++cafexeclibdir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)$(MULTISUBDIR) + libcaf_single_la_SOURCES = caf/single.c + libcaf_single_la_LDFLAGS = -static + libcaf_single_la_DEPENDENCIES = caf/libcaf.h +--- a/src/libgfortran/Makefile.am 2012-01-09 17:02:36.000000000 +0100 ++++ b/src/libgfortran/Makefile.am 2012-12-08 08:49:41.957876998 +0100 +@@ -42,13 +42,13 @@ + libgfortran_la_DEPENDENCIES = $(version_dep) libgfortran.spec $(LIBQUADLIB_DEP) + + myexeclib_LTLIBRARIES = libgfortranbegin.la +-myexeclibdir = $(libdir)/gcc/$(target_alias)/$(gcc_version)$(MULTISUBDIR) ++myexeclibdir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)$(MULTISUBDIR) + libgfortranbegin_la_SOURCES = fmain.c + libgfortranbegin_la_LDFLAGS = -static + libgfortranbegin_la_LINK = $(LINK) $(libgfortranbegin_la_LDFLAGS) + + cafexeclib_LTLIBRARIES = libcaf_single.la +-cafexeclibdir = $(libdir)/gcc/$(target_alias)/$(gcc_version)$(MULTISUBDIR) ++cafexeclibdir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)$(MULTISUBDIR) + libcaf_single_la_SOURCES = caf/single.c + libcaf_single_la_LDFLAGS = -static + libcaf_single_la_DEPENDENCIES = caf/libcaf.h +--- a/src/lto-plugin/Makefile.in 2011-08-10 10:48:37.000000000 +0200 ++++ b/src/lto-plugin/Makefile.in 2012-12-08 09:00:17.861873944 +0100 +@@ -227,7 +227,7 @@ + ACLOCAL_AMFLAGS = -I .. -I ../config + AUTOMAKE_OPTIONS = no-dependencies + gcc_version := $(shell cat $(top_srcdir)/../gcc/BASE-VER) +-libexecsubdir := $(libexecdir)/gcc/$(target_noncanonical)/$(gcc_version) ++libexecsubdir := $(libexecdir)/gcc-cross/$(target_noncanonical)/$(gcc_version) + AM_CPPFLAGS = -I$(top_srcdir)/../include $(DEFS) + AM_CFLAGS = @ac_lto_plugin_warn_cflags@ + AM_LIBTOOLFLAGS = --tag=disable-static +--- a/src/lto-plugin/Makefile.am 2011-08-10 10:48:37.000000000 +0200 ++++ b/src/lto-plugin/Makefile.am 2012-12-08 08:59:54.621875067 +0100 +@@ -5,7 +5,7 @@ + + gcc_version := $(shell cat $(top_srcdir)/../gcc/BASE-VER) + target_noncanonical := @target_noncanonical@ +-libexecsubdir := $(libexecdir)/gcc/$(target_noncanonical)/$(gcc_version) ++libexecsubdir := $(libexecdir)/gcc-cross/$(target_noncanonical)/$(gcc_version) + + AM_CPPFLAGS = -I$(top_srcdir)/../include $(DEFS) + AM_CFLAGS = @ac_lto_plugin_warn_cflags@ +--- a/src/libitm/Makefile.in 2012-12-08 08:32:40.093881158 +0100 ++++ b/src/libitm/Makefile.in 2012-12-08 08:54:51.929875619 +0100 +@@ -306,8 +306,8 @@ + gcc_version := $(shell cat $(top_srcdir)/../gcc/BASE-VER) + abi_version = -fabi-version=4 + search_path = $(addprefix $(top_srcdir)/config/, $(config_path)) $(top_srcdir) +-fincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/finclude +-libsubincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/include ++fincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/finclude ++libsubincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include + AM_CPPFLAGS = $(addprefix -I, $(search_path)) + AM_CFLAGS = $(XCFLAGS) + AM_CXXFLAGS = $(XCFLAGS) -std=gnu++0x -funwind-tables -fno-exceptions \ +--- a/src/libitm/Makefile.am 2012-02-14 14:14:27.000000000 +0100 ++++ b/src/libitm/Makefile.am 2012-12-08 08:53:58.341873782 +0100 +@@ -11,8 +11,8 @@ + config_path = @config_path@ + search_path = $(addprefix $(top_srcdir)/config/, $(config_path)) $(top_srcdir) + +-fincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/finclude +-libsubincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/include ++fincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/finclude ++libsubincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include + + vpath % $(strip $(search_path)) + +--- a/src/gcc/gcc.c 2012-08-06 16:34:27.000000000 +0200 ++++ b/src/gcc/gcc.c 2012-12-08 08:42:06.353877392 +0100 +@@ -3621,7 +3621,7 @@ + GCC_EXEC_PREFIX is typically a directory name with a trailing + / (which is ignored by make_relative_prefix), so append a + program name. */ +- char *tmp_prefix = concat (gcc_exec_prefix, "gcc", NULL); ++ char *tmp_prefix = concat (gcc_exec_prefix, "gcc-cross", NULL); + gcc_libexec_prefix = get_relative_prefix (tmp_prefix, + standard_exec_prefix, + standard_libexec_prefix); +@@ -3647,15 +3647,15 @@ + { + int len = strlen (gcc_exec_prefix); + +- if (len > (int) sizeof ("/lib/gcc/") - 1 ++ if (len > (int) sizeof ("/lib/gcc-cross/") - 1 + && (IS_DIR_SEPARATOR (gcc_exec_prefix[len-1]))) + { +- temp = gcc_exec_prefix + len - sizeof ("/lib/gcc/") + 1; ++ temp = gcc_exec_prefix + len - sizeof ("/lib/gcc-cross/") + 1; + if (IS_DIR_SEPARATOR (*temp) + && filename_ncmp (temp + 1, "lib", 3) == 0 + && IS_DIR_SEPARATOR (temp[4]) +- && filename_ncmp (temp + 5, "gcc", 3) == 0) +- len -= sizeof ("/lib/gcc/") - 1; ++ && filename_ncmp (temp + 5, "gcc-cross", 3) == 0) ++ len -= sizeof ("/lib/gcc-cross/") - 1; + } + + set_std_prefix (gcc_exec_prefix, len); +--- a/src/gcc/Makefile.in 2012-12-08 08:32:41.337881153 +0100 ++++ b/src/gcc/Makefile.in 2012-12-08 08:36:18.493883559 +0100 +@@ -566,9 +566,9 @@ + # -------- + + # Directory in which the compiler finds libraries etc. +-libsubdir = $(libdir)/gcc/$(target_noncanonical)/$(version) ++libsubdir = $(libdir)/gcc-cross/$(target_noncanonical)/$(version) + # Directory in which the compiler finds executables +-libexecsubdir = $(libexecdir)/gcc/$(target_noncanonical)/$(version) ++libexecsubdir = $(libexecdir)/gcc-cross/$(target_noncanonical)/$(version) + # Directory in which all plugin resources are installed + plugin_resourcesdir = $(libsubdir)/plugin + # Directory in which plugin headers are installed +@@ -2079,8 +2079,8 @@ + + DRIVER_DEFINES = \ + -DSTANDARD_STARTFILE_PREFIX=\"$(unlibsubdir)/\" \ +- -DSTANDARD_EXEC_PREFIX=\"$(libdir)/gcc/\" \ +- -DSTANDARD_LIBEXEC_PREFIX=\"$(libexecdir)/gcc/\" \ ++ -DSTANDARD_EXEC_PREFIX=\"$(libdir)/gcc-cross/\" \ ++ -DSTANDARD_LIBEXEC_PREFIX=\"$(libexecdir)/gcc-cross/\" \ + -DDEFAULT_TARGET_VERSION=\"$(version)\" \ + -DDEFAULT_TARGET_MACHINE=\"$(target_noncanonical)\" \ + -DSTANDARD_BINDIR_PREFIX=\"$(bindir)/\" \ +@@ -3980,7 +3980,7 @@ + -DTOOL_INCLUDE_DIR=\"$(gcc_tooldir)/include\" \ + -DNATIVE_SYSTEM_HEADER_DIR=\"$(NATIVE_SYSTEM_HEADER_DIR)\" \ + -DPREFIX=\"$(prefix)/\" \ +- -DSTANDARD_EXEC_PREFIX=\"$(libdir)/gcc/\" \ ++ -DSTANDARD_EXEC_PREFIX=\"$(libdir)/gcc-cross/\" \ + @TARGET_SYSTEM_ROOT_DEFINE@ + + CFLAGS-cppbuiltin.o += $(PREPROCESSOR_DEFINES) -DBASEVER=$(FULLVER_s) +--- a/src/libssp/Makefile.in 2011-02-13 12:45:53.000000000 +0100 ++++ b/src/libssp/Makefile.in 2012-12-08 08:59:07.469875025 +0100 +@@ -259,7 +259,7 @@ + @LIBSSP_USE_SYMVER_SUN_TRUE@@LIBSSP_USE_SYMVER_TRUE@version_dep = ssp.map-sun + AM_CFLAGS = -Wall + toolexeclib_LTLIBRARIES = libssp.la libssp_nonshared.la +-libsubincludedir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version)/include ++libsubincludedir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version)/include + nobase_libsubinclude_HEADERS = ssp/ssp.h ssp/string.h ssp/stdio.h ssp/unistd.h + libssp_la_SOURCES = \ + ssp.c gets-chk.c memcpy-chk.c memmove-chk.c mempcpy-chk.c \ +--- a/src/libssp/Makefile.am 2010-12-06 01:50:04.000000000 +0100 ++++ b/src/libssp/Makefile.am 2012-12-08 08:58:51.241873553 +0100 +@@ -39,7 +39,7 @@ + toolexeclib_LTLIBRARIES = libssp.la libssp_nonshared.la + + target_noncanonical = @target_noncanonical@ +-libsubincludedir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version)/include ++libsubincludedir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version)/include + nobase_libsubinclude_HEADERS = ssp/ssp.h ssp/string.h ssp/stdio.h ssp/unistd.h + + libssp_la_SOURCES = \ +--- a/src/libquadmath/Makefile.in 2011-09-21 16:36:03.000000000 +0200 ++++ b/src/libquadmath/Makefile.in 2012-12-08 08:49:10.557875680 +0100 +@@ -319,7 +319,7 @@ + + @BUILD_LIBQUADMATH_TRUE@libquadmath_la_DEPENDENCIES = $(version_dep) $(libquadmath_la_LIBADD) + @BUILD_LIBQUADMATH_TRUE@nodist_libsubinclude_HEADERS = quadmath.h quadmath_weak.h +-@BUILD_LIBQUADMATH_TRUE@libsubincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/include ++@BUILD_LIBQUADMATH_TRUE@libsubincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include + @BUILD_LIBQUADMATH_TRUE@libquadmath_la_SOURCES = \ + @BUILD_LIBQUADMATH_TRUE@ math/acoshq.c math/fmodq.c math/acosq.c math/frexpq.c \ + @BUILD_LIBQUADMATH_TRUE@ math/rem_pio2q.c math/asinhq.c math/hypotq.c math/remainderq.c \ +--- a/src/libquadmath/Makefile.am 2011-09-21 16:36:03.000000000 +0200 ++++ b/src/libquadmath/Makefile.am 2012-12-08 08:48:25.553878276 +0100 +@@ -40,7 +40,7 @@ + libquadmath_la_DEPENDENCIES = $(version_dep) $(libquadmath_la_LIBADD) + + nodist_libsubinclude_HEADERS = quadmath.h quadmath_weak.h +-libsubincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/include ++libsubincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include + + libquadmath_la_SOURCES = \ + math/acoshq.c math/fmodq.c math/acosq.c math/frexpq.c \ +--- a/src/libobjc/Makefile.in 2011-11-02 16:28:43.000000000 +0100 ++++ b/src/libobjc/Makefile.in 2012-12-08 08:50:47.241873110 +0100 +@@ -51,7 +51,7 @@ + -include ../boehm-gc/threads.mk + + libdir = $(exec_prefix)/lib +-libsubdir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version) ++libsubdir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version) + + # Multilib support variables. + MULTISRCTOP = +--- a/src/libada/Makefile.in 2012-08-06 16:34:27.000000000 +0200 ++++ b/src/libada/Makefile.in 2012-12-08 08:53:01.321876031 +0100 +@@ -62,7 +62,7 @@ + + target_noncanonical:=@target_noncanonical@ + version := $(shell cat $(srcdir)/../gcc/BASE-VER) +-libsubdir := $(libdir)/gcc/$(target_noncanonical)/$(version)$(MULTISUBDIR) ++libsubdir := $(libdir)/gcc-cross/$(target_noncanonical)/$(version)$(MULTISUBDIR) + ADA_RTS_DIR=$(GCC_DIR)/ada/rts$(subst /,_,$(MULTISUBDIR)) + ADA_RTS_SUBDIR=./rts$(subst /,_,$(MULTISUBDIR)) + +--- a/src/libgomp/Makefile.in 2012-09-20 09:23:55.000000000 +0200 ++++ b/src/libgomp/Makefile.in 2012-12-08 08:45:32.157878288 +0100 +@@ -291,8 +291,8 @@ + SUBDIRS = testsuite + gcc_version := $(shell cat $(top_srcdir)/../gcc/BASE-VER) + search_path = $(addprefix $(top_srcdir)/config/, $(config_path)) $(top_srcdir) +-fincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/finclude +-libsubincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/include ++fincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/finclude ++libsubincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include + AM_CPPFLAGS = $(addprefix -I, $(search_path)) + AM_CFLAGS = $(XCFLAGS) + AM_LDFLAGS = $(XLDFLAGS) $(SECTION_LDFLAGS) $(OPT_LDFLAGS) +--- a/src/libgomp/Makefile.am 2012-02-27 14:51:50.000000000 +0100 ++++ b/src/libgomp/Makefile.am 2012-12-08 08:44:48.913867574 +0100 +@@ -9,8 +9,8 @@ + config_path = @config_path@ + search_path = $(addprefix $(top_srcdir)/config/, $(config_path)) $(top_srcdir) + +-fincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/finclude +-libsubincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/include ++fincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/finclude ++libsubincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include + + vpath % $(strip $(search_path)) + +--- a/src/libgcc/Makefile.in 2012-12-08 08:32:41.249881153 +0100 ++++ b/src/libgcc/Makefile.in 2012-12-08 08:43:50.201879083 +0100 +@@ -178,7 +178,7 @@ + STRIP_FOR_TARGET = $(STRIP) + + # Directory in which the compiler finds libraries etc. +-libsubdir = $(libdir)/gcc/$(host_noncanonical)/$(version) ++libsubdir = $(libdir)/gcc-cross/$(host_noncanonical)/$(version) + # Used to install the shared libgcc. + slibdir = @slibdir@ + # Maybe used for DLLs on Windows targets. +--- a/src/libjava/Makefile.in 2012-12-08 08:32:41.249881153 +0100 ++++ b/src/libjava/Makefile.in 2012-12-08 08:51:43.365881984 +0100 +@@ -785,8 +785,8 @@ + + + # This is required by TL_AC_GXX_INCLUDE_DIR. +-libsubdir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version) +-libexecsubdir = $(libexecdir)/gcc/$(target_noncanonical)/$(gcc_version) ++libsubdir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version) ++libexecsubdir = $(libexecdir)/gcc-cross/$(target_noncanonical)/$(gcc_version) + toolexeclib_LTLIBRARIES = libgcj.la libgij.la libgcj-tools.la \ + $(am__append_2) $(am__append_3) $(am__append_4) + toolexecmainlib_DATA = libgcj.spec +--- a/src/libjava/Makefile.am 2012-12-08 08:32:41.241881153 +0100 ++++ b/src/libjava/Makefile.am 2012-12-08 08:51:13.481876463 +0100 +@@ -34,9 +34,9 @@ + target_noncanonical = @target_noncanonical@ + + # This is required by TL_AC_GXX_INCLUDE_DIR. +-libsubdir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version) ++libsubdir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version) + +-libexecsubdir = $(libexecdir)/gcc/$(target_noncanonical)/$(gcc_version) ++libexecsubdir = $(libexecdir)/gcc-cross/$(target_noncanonical)/$(gcc_version) + + ## + ## What gets installed, and where. +--- a/src/libffi/include/Makefile.am 2006-09-12 18:51:43.000000000 +0200 ++++ b/src/libffi/include/Makefile.am 2012-12-08 09:42:12.313863513 +0100 +@@ -7,6 +7,6 @@ + + # Where generated headers like ffitarget.h get installed. + gcc_version := $(shell cat $(top_srcdir)/../gcc/BASE-VER) +-toollibffidir := $(libdir)/gcc/$(target_alias)/$(gcc_version)/include ++toollibffidir := $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include + + toollibffi_HEADERS = ffi.h ffitarget.h +--- a/src/libffi/include/Makefile.in 2012-12-08 09:12:36.913870891 +0100 ++++ b/src/libffi/include/Makefile.in 2012-12-08 09:42:24.901862621 +0100 +@@ -213,7 +213,7 @@ + + # Where generated headers like ffitarget.h get installed. + gcc_version := $(shell cat $(top_srcdir)/../gcc/BASE-VER) +-toollibffidir := $(libdir)/gcc/$(target_alias)/$(gcc_version)/include ++toollibffidir := $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include + toollibffi_HEADERS = ffi.h ffitarget.h + all: all-am + diff -Nru gcc-4.7-4.7.2/debian/patches/cross-ma-install-location.diff gcc-4.7-4.7.3/debian/patches/cross-ma-install-location.diff --- gcc-4.7-4.7.2/debian/patches/cross-ma-install-location.diff 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/cross-ma-install-location.diff 2013-06-25 15:26:04.000000000 +0000 @@ -0,0 +1,306 @@ +--- a/src/boehm-gc/configure.ac ++++ b/src/boehm-gc/configure.ac +@@ -493,14 +493,8 @@ + AC_DEFINE(USE_MMAP, 1, [use MMAP instead of sbrk to get new memory]) + fi + +-if test -n "$with_cross_host" && +- test x"$with_cross_host" != x"no"; then +- toolexecdir='$(exec_prefix)/$(target_noncanonical)' +- toolexeclibdir='$(toolexecdir)/lib' +-else +- toolexecdir='$(libdir)/gcc-lib/$(target_noncanonical)' +- toolexeclibdir='$(libdir)' +-fi ++toolexecdir='$(libdir)/gcc-lib/$(target_noncanonical)' ++toolexeclibdir='$(libdir)' + multi_os_directory=`$CC -print-multi-os-directory` + case $multi_os_directory in + .) ;; # Avoid trailing /. +--- a/src/libada/configure.ac ++++ b/src/libada/configure.ac +@@ -65,15 +65,8 @@ + toolexeclibdir='$(toolexecdir)/$(gcc_version)$(MULTISUBDIR)' + ;; + no) +- if test -n "$with_cross_host" && +- test x"$with_cross_host" != x"no"; then +- # Install a library built with a cross compiler in tooldir, not libdir. +- toolexecdir='$(exec_prefix)/$(target_alias)' +- toolexeclibdir='$(toolexecdir)/lib' +- else +- toolexecdir='$(libdir)/gcc-lib/$(target_alias)' +- toolexeclibdir='$(libdir)' +- fi ++ toolexecdir='$(libdir)/gcc-lib/$(target_alias)' ++ toolexeclibdir='$(libdir)' + multi_os_directory=`$CC -print-multi-os-directory` + case $multi_os_directory in + .) ;; # Avoid trailing /. +--- a/src/libffi/configure.ac ++++ b/src/libffi/configure.ac +@@ -421,14 +421,9 @@ + AC_DEFINE(USING_PURIFY, 1, [Define this if you are using Purify and want to suppress spurious messages.]) + fi) + +-if test -n "$with_cross_host" && +- test x"$with_cross_host" != x"no"; then +- toolexecdir='$(exec_prefix)/$(target_alias)' +- toolexeclibdir='$(toolexecdir)/lib' +-else +- toolexecdir='$(libdir)/gcc-lib/$(target_alias)' +- toolexeclibdir='$(libdir)' +-fi ++toolexecdir='$(libdir)/gcc-lib/$(target_alias)' ++toolexeclibdir='$(libdir)' ++ + multi_os_directory=`$CC -print-multi-os-directory` + case $multi_os_directory in + .) ;; # Avoid trailing /. +--- a/src/libgcc/configure.ac ++++ b/src/libgcc/configure.ac +@@ -83,8 +83,6 @@ + slibdir="$with_slibdir", + if test "${version_specific_libs}" = yes; then + slibdir='$(libsubdir)' +-elif test -n "$with_cross_host" && test x"$with_cross_host" != x"no"; then +- slibdir='$(exec_prefix)/$(host_noncanonical)/lib' + else + slibdir='$(libdir)' + fi) +@@ -129,15 +127,8 @@ + toolexeclibdir='$(toolexecdir)/$(gcc_version)$(MULTISUBDIR)' + ;; + no) +- if test -n "$with_cross_host" && +- test x"$with_cross_host" != x"no"; then +- # Install a library built with a cross compiler in tooldir, not libdir. +- toolexecdir='$(exec_prefix)/$(target_noncanonical)' +- toolexeclibdir='$(toolexecdir)/lib' +- else +- toolexecdir='$(libdir)/gcc-lib/$(target_noncanonical)' +- toolexeclibdir='$(libdir)' +- fi ++ toolexecdir='$(libdir)/gcc-lib/$(target_noncanonical)' ++ toolexeclibdir='$(libdir)' + multi_os_directory=`$CC -print-multi-os-directory` + case $multi_os_directory in + .) ;; # Avoid trailing /. +--- a/src/libgfortran/configure.ac ++++ b/src/libgfortran/configure.ac +@@ -98,15 +98,8 @@ + toolexeclibdir='$(toolexecdir)/$(gcc_version)$(MULTISUBDIR)' + ;; + no) +- if test -n "$with_cross_host" && +- test x"$with_cross_host" != x"no"; then +- # Install a library built with a cross compiler in tooldir, not libdir. +- toolexecdir='$(exec_prefix)/$(target_alias)' +- toolexeclibdir='$(toolexecdir)/lib' +- else +- toolexecdir='$(libdir)/gcc-lib/$(target_alias)' +- toolexeclibdir='$(libdir)' +- fi ++ toolexecdir='$(libdir)/gcc-lib/$(target_alias)' ++ toolexeclibdir='$(libdir)' + multi_os_directory=`$CC -print-multi-os-directory` + case $multi_os_directory in + .) ;; # Avoid trailing /. +--- a/src/libgo/configure.ac ++++ b/src/libgo/configure.ac +@@ -77,14 +77,8 @@ + + # Calculate glibgo_toolexecdir, glibgo_toolexeclibdir + # Install a library built with a cross compiler in tooldir, not libdir. +-if test -n "$with_cross_host" && +- test x"$with_cross_host" != x"no"; then +- nover_glibgo_toolexecdir='${exec_prefix}/${host_alias}' +- nover_glibgo_toolexeclibdir='${toolexecdir}/lib' +-else +- nover_glibgo_toolexecdir='${libdir}/gcc/${host_alias}' +- nover_glibgo_toolexeclibdir='${libdir}' +-fi ++nover_glibgo_toolexecdir='${libdir}/gcc/${host_alias}' ++nover_glibgo_toolexeclibdir='${libdir}' + multi_os_directory=`$CC -print-multi-os-directory` + case $multi_os_directory in + .) ;; # Avoid trailing /. +--- a/src/libgomp/configure.ac ++++ b/src/libgomp/configure.ac +@@ -76,15 +76,8 @@ + toolexeclibdir='$(toolexecdir)/$(gcc_version)$(MULTISUBDIR)' + ;; + no) +- if test -n "$with_cross_host" && +- test x"$with_cross_host" != x"no"; then +- # Install a library built with a cross compiler in tooldir, not libdir. +- toolexecdir='$(exec_prefix)/$(target_alias)' +- toolexeclibdir='$(toolexecdir)/lib' +- else +- toolexecdir='$(libdir)/gcc-lib/$(target_alias)' +- toolexeclibdir='$(libdir)' +- fi ++ toolexecdir='$(libdir)/gcc-lib/$(target_alias)' ++ toolexeclibdir='$(libdir)' + multi_os_directory=`$CC -print-multi-os-directory` + case $multi_os_directory in + .) ;; # Avoid trailing /. +--- a/src/libitm/configure.ac ++++ b/src/libitm/configure.ac +@@ -89,15 +89,8 @@ + toolexeclibdir='$(toolexecdir)/$(gcc_version)$(MULTISUBDIR)' + ;; + no) +- if test -n "$with_cross_host" && +- test x"$with_cross_host" != x"no"; then +- # Install a library built with a cross compiler in tooldir, not libdir. +- toolexecdir='$(exec_prefix)/$(target_alias)' +- toolexeclibdir='$(toolexecdir)/lib' +- else +- toolexecdir='$(libdir)/gcc-lib/$(target_alias)' +- toolexeclibdir='$(libdir)' +- fi ++ toolexecdir='$(libdir)/gcc-lib/$(target_alias)' ++ toolexeclibdir='$(libdir)' + multi_os_directory=`$CC -print-multi-os-directory` + case $multi_os_directory in + .) ;; # Avoid trailing /. +--- a/src/libjava/configure.ac ++++ b/src/libjava/configure.ac +@@ -1589,15 +1589,8 @@ + toolexeclibdir=$toolexecmainlibdir + ;; + no) +- if test -n "$with_cross_host" && +- test x"$with_cross_host" != x"no"; then +- # Install a library built with a cross compiler in tooldir, not libdir. +- toolexecdir='$(exec_prefix)/$(target_noncanonical)' +- toolexecmainlibdir='$(toolexecdir)/lib' +- else +- toolexecdir='$(libdir)/gcc-lib/$(target_noncanonical)' +- toolexecmainlibdir='$(libdir)' +- fi ++ toolexecdir='$(libdir)/gcc-lib/$(target_noncanonical)' ++ toolexecmainlibdir='$(libdir)' + multi_os_directory=`$CC -print-multi-os-directory` + case $multi_os_directory in + .) toolexeclibdir=$toolexecmainlibdir ;; # Avoid trailing /. +--- a/src/libmudflap/configure.ac ++++ b/src/libmudflap/configure.ac +@@ -157,15 +157,8 @@ + toolexeclibdir='$(toolexecdir)/$(gcc_version)$(MULTISUBDIR)' + ;; + no) +- if test -n "$with_cross_host" && +- test x"$with_cross_host" != x"no"; then +- # Install a library built with a cross compiler in tooldir, not libdir. +- toolexecdir='$(exec_prefix)/$(target_alias)' +- toolexeclibdir='$(toolexecdir)/lib' +- else +- toolexecdir='$(libdir)/gcc-lib/$(target_alias)' +- toolexeclibdir='$(libdir)' +- fi ++ toolexecdir='$(libdir)/gcc-lib/$(target_alias)' ++ toolexeclibdir='$(libdir)' + multi_os_directory=`$CC -print-multi-os-directory` + case $multi_os_directory in + .) ;; # Avoid trailing /. +--- a/src/libobjc/configure.ac ++++ b/src/libobjc/configure.ac +@@ -116,15 +116,8 @@ + toolexeclibdir='$(toolexecdir)/$(gcc_version)$(MULTISUBDIR)' + ;; + no) +- if test -n "$with_cross_host" && +- test x"$with_cross_host" != x"no"; then +- # Install a library built with a cross compiler in tooldir, not libdir. +- toolexecdir='$(exec_prefix)/$(target_noncanonical)' +- toolexeclibdir='$(toolexecdir)/lib' +- else +- toolexecdir='$(libdir)/gcc-lib/$(target_noncanonical)' +- toolexeclibdir='$(libdir)' +- fi ++ toolexecdir='$(libdir)/gcc-lib/$(target_noncanonical)' ++ toolexeclibdir='$(libdir)' + multi_os_directory=`$CC -print-multi-os-directory` + case $multi_os_directory in + .) ;; # Avoid trailing /. +--- a/src/libquadmath/configure.ac ++++ b/src/libquadmath/configure.ac +@@ -93,15 +93,8 @@ + toolexeclibdir='$(toolexecdir)/$(gcc_version)$(MULTISUBDIR)' + ;; + no) +- if test -n "$with_cross_host" && +- test x"$with_cross_host" != x"no"; then +- # Install a library built with a cross compiler in tooldir, not libdir. +- toolexecdir='$(exec_prefix)/$(target_alias)' +- toolexeclibdir='$(toolexecdir)/lib' +- else +- toolexecdir='$(libdir)/gcc-lib/$(target_alias)' +- toolexeclibdir='$(libdir)' +- fi ++ toolexecdir='$(libdir)/gcc-lib/$(target_alias)' ++ toolexeclibdir='$(libdir)' + multi_os_directory=`$CC -print-multi-os-directory` + case $multi_os_directory in + .) ;; # Avoid trailing /. +--- a/src/libssp/configure.ac ++++ b/src/libssp/configure.ac +@@ -170,15 +170,8 @@ + toolexeclibdir='$(toolexecdir)/$(gcc_version)$(MULTISUBDIR)' + ;; + no) +- if test -n "$with_cross_host" && +- test x"$with_cross_host" != x"no"; then +- # Install a library built with a cross compiler in tooldir, not libdir. +- toolexecdir='$(exec_prefix)/$(target_alias)' +- toolexeclibdir='$(toolexecdir)/lib' +- else +- toolexecdir='$(libdir)/gcc-lib/$(target_alias)' +- toolexeclibdir='$(libdir)' +- fi ++ toolexecdir='$(libdir)/gcc-lib/$(target_alias)' ++ toolexeclibdir='$(libdir)' + multi_os_directory=`$CC -print-multi-os-directory` + case $multi_os_directory in + .) ;; # Avoid trailing /. +--- a/src/libstdc++-v3/acinclude.m4 ++++ b/src/libstdc++-v3/acinclude.m4 +@@ -804,14 +804,8 @@ + # Calculate glibcxx_toolexecdir, glibcxx_toolexeclibdir + # Install a library built with a cross compiler in tooldir, not libdir. + if test x"$glibcxx_toolexecdir" = x"no"; then +- if test -n "$with_cross_host" && +- test x"$with_cross_host" != x"no"; then +- glibcxx_toolexecdir='${exec_prefix}/${host_alias}' +- glibcxx_toolexeclibdir='${toolexecdir}/lib' +- else +- glibcxx_toolexecdir='${libdir}/gcc/${host_alias}' +- glibcxx_toolexeclibdir='${libdir}' +- fi ++ glibcxx_toolexecdir='${libdir}/gcc/${host_alias}' ++ glibcxx_toolexeclibdir='${libdir}' + multi_os_directory=`$CXX -print-multi-os-directory` + case $multi_os_directory in + .) ;; # Avoid trailing /. +--- a/src/zlib/configure.ac ++++ b/src/zlib/configure.ac +@@ -91,14 +91,9 @@ + + AC_CHECK_HEADERS(unistd.h) + +-if test -n "$with_cross_host" && +- test x"$with_cross_host" != x"no"; then +- toolexecdir='$(exec_prefix)/$(target_alias)' +- toolexeclibdir='$(toolexecdir)/lib' +-else +- toolexecdir='$(libdir)/gcc-lib/$(target_alias)' +- toolexeclibdir='$(libdir)' +-fi ++toolexecdir='$(libdir)/gcc-lib/$(target_alias)' ++toolexeclibdir='$(libdir)' ++ + if test "$GCC" = yes && $CC -print-multi-os-directory > /dev/null 2>&1; then + multiosdir=/`$CC -print-multi-os-directory` + case $multiosdir in diff -Nru gcc-4.7-4.7.2/debian/patches/cross-no-locale-include.diff gcc-4.7-4.7.3/debian/patches/cross-no-locale-include.diff --- gcc-4.7-4.7.2/debian/patches/cross-no-locale-include.diff 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/cross-no-locale-include.diff 2013-06-25 15:26:04.000000000 +0000 @@ -0,0 +1,17 @@ +# DP: Don't add /usr/local/include for cross compilers. Assume that +# DP: /usr/include is ready for multiarch, but not /usr/local/include. + +--- a/src/gcc/cppdefault.c ++++ b/src/gcc/cppdefault.c +@@ -66,8 +66,11 @@ + #ifdef LOCAL_INCLUDE_DIR + /* /usr/local/include comes before the fixincluded header files. */ + { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 2 }, ++#if 0 ++ /* Unsafe to assume that /usr/local/include is ready for multiarch. */ + { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 0 }, + #endif ++#endif + #ifdef PREFIX_INCLUDE_DIR + { PREFIX_INCLUDE_DIR, 0, 0, 1, 0, 0 }, + #endif diff -Nru gcc-4.7-4.7.2/debian/patches/g++-multiarch-incdir.diff gcc-4.7-4.7.3/debian/patches/g++-multiarch-incdir.diff --- gcc-4.7-4.7.2/debian/patches/g++-multiarch-incdir.diff 2013-06-25 15:26:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/g++-multiarch-incdir.diff 2013-06-25 15:26:04.000000000 +0000 @@ -31,7 +31,7 @@ =================================================================== --- a/src/gcc/Makefile.in +++ b/src/gcc/Makefile.in -@@ -1120,6 +1120,7 @@ +@@ -1118,6 +1118,7 @@ "prefix=$(prefix)" \ "local_prefix=$(local_prefix)" \ "gxx_include_dir=$(gcc_gxx_include_dir)" \ @@ -39,7 +39,7 @@ "build_tooldir=$(build_tooldir)" \ "gcc_tooldir=$(gcc_tooldir)" \ "bindir=$(bindir)" \ -@@ -1548,6 +1549,14 @@ +@@ -1546,6 +1547,14 @@ include $(xmake_file) endif @@ -54,7 +54,7 @@ # all-tree.def includes all the tree.def files. all-tree.def: s-alltree; @true s-alltree: Makefile -@@ -3989,7 +3998,7 @@ +@@ -3978,7 +3987,7 @@ -DFIXED_INCLUDE_DIR=\"$(libsubdir)/include-fixed\" \ -DGPLUSPLUS_INCLUDE_DIR=\"$(gcc_gxx_include_dir)\" \ -DGPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT=$(gcc_gxx_include_dir_add_sysroot) \ @@ -116,92 +116,3 @@ } add_path (str, SYSTEM, p->cxx_aware, false); -Index: b/src/gcc/config/sparc/t-linux64 -=================================================================== ---- a/src/gcc/config/sparc/t-linux64 -+++ b/src/gcc/config/sparc/t-linux64 -@@ -28,3 +28,5 @@ - MULTILIB_DIRNAMES = 64 32 - MULTILIB_OSDIRNAMES = ../lib64$(call if_multiarch,:sparc64-linux-gnu) - MULTILIB_OSDIRNAMES += $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:sparc-linux-gnu) -+ -+MULTIARCH_DIRNAME = $(call if_multiarch,sparc$(if $(findstring 64,$(target)),64)-linux-gnu) -Index: b/src/gcc/config/s390/t-linux64 -=================================================================== ---- a/src/gcc/config/s390/t-linux64 -+++ b/src/gcc/config/s390/t-linux64 -@@ -9,3 +9,5 @@ - MULTILIB_DIRNAMES = 64 32 - MULTILIB_OSDIRNAMES = ../lib64$(call if_multiarch,:s390x-linux-gnu) - MULTILIB_OSDIRNAMES += $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:s390-linux-gnu) -+ -+MULTIARCH_DIRNAME = $(call if_multiarch,s390$(if $(findstring s390x,$(target)),x)-linux-gnu) -Index: b/src/gcc/config/rs6000/t-linux64 -=================================================================== ---- a/src/gcc/config/rs6000/t-linux64 -+++ b/src/gcc/config/rs6000/t-linux64 -@@ -34,3 +34,5 @@ - MULTILIB_OSDIRNAMES = ../lib64$(call if_multiarch,:powerpc64-linux-gnu) - MULTILIB_OSDIRNAMES += $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:powerpc-linux-gnu) - MULTILIB_MATCHES = -+ -+MULTIARCH_DIRNAME = $(call if_multiarch,powerpc$(if $(findstring 64,$(target)),64)-linux-gnu) -Index: b/src/gcc/config/i386/t-linux64 -=================================================================== ---- a/src/gcc/config/i386/t-linux64 -+++ b/src/gcc/config/i386/t-linux64 -@@ -37,3 +37,13 @@ - MULTILIB_OSDIRNAMES = m64=../lib64$(call if_multiarch,:x86_64-linux-gnu) - MULTILIB_OSDIRNAMES+= m32=$(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:i386-linux-gnu) - MULTILIB_OSDIRNAMES+= mx32=../libx32$(call if_multiarch,:x86_64-linux-gnux32) -+ -+ifneq (,$(findstring x86_64,$(target))) -+ ifneq (,$(findstring biarchx32.h,$(tm_include_list))) -+ MULTIARCH_DIRNAME = $(call if_multiarch,x86_64-linux-gnux32) -+ else -+ MULTIARCH_DIRNAME = $(call if_multiarch,x86_64-linux-gnu) -+ endif -+else -+ MULTIARCH_DIRNAME = $(call if_multiarch,i386-linux-gnu) -+endif -Index: b/src/gcc/config/i386/t-kfreebsd -=================================================================== ---- a/src/gcc/config/i386/t-kfreebsd -+++ b/src/gcc/config/i386/t-kfreebsd -@@ -3,3 +3,5 @@ - # MULTILIB_OSDIRNAMES are set in t-linux64. - KFREEBSD_OS = $(filter kfreebsd%, $(word 3, $(subst -, ,$(target)))) - MULTILIB_OSDIRNAMES := $(filter-out mx32=%,$(subst linux,$(KFREEBSD_OS),$(MULTILIB_OSDIRNAMES))) -+ -+MULTIARCH_DIRNAME := $(subst linux,$(KFREEBSD_OS),$(MULTIARCH_DIRNAME)) -Index: b/src/gcc/config/mips/t-linux64 -=================================================================== ---- a/src/gcc/config/mips/t-linux64 -+++ b/src/gcc/config/mips/t-linux64 -@@ -24,3 +24,13 @@ - ../lib32$(call if_multiarch,:mips64$(MIPS_EL)-linux-gnuabin32$(MIPS_SOFT)) \ - ../lib$(call if_multiarch,:mips$(MIPS_EL)-linux-gnu$(MIPS_SOFT)) \ - ../lib64$(call if_multiarch,:mips64$(MIPS_EL)-linux-gnuabi64$(MIPS_SOFT)) -+ -+ifneq (,$(findstring abin32,$(target))) -+MULTIARCH_DIRNAME = $(call if_multiarch,mips64$(MIPS_EL)-linux-gnuabin32$(MIPS_SOFT)) -+else -+ifneq (,$(findstring abi64,$(target))) -+MULTIARCH_DIRNAME = $(call if_multiarch,mips64$(MIPS_EL)-linux-gnuabi64$(MIPS_SOFT)) -+else -+MULTIARCH_DIRNAME = $(call if_multiarch,mips$(MIPS_EL)-linux-gnu$(MIPS_SOFT)) -+endif -+endif -Index: b/src/gcc/config.gcc -=================================================================== ---- a/src/gcc/config.gcc -+++ b/src/gcc/config.gcc -@@ -3607,7 +3607,7 @@ - i[34567]86-*-darwin* | x86_64-*-darwin*) - ;; - i[34567]86-*-linux* | x86_64-*-linux*) -- tmake_file="$tmake_file i386/t-linux" -+ tmake_file="i386/t-linux $tmake_file" - ;; - i[34567]86-*-kfreebsd*-gnu | x86_64-*-kfreebsd*-gnu) - tmake_file="$tmake_file i386/t-kfreebsd" diff -Nru gcc-4.7-4.7.2/debian/patches/gcc-base-version.diff gcc-4.7-4.7.3/debian/patches/gcc-base-version.diff --- gcc-4.7-4.7.2/debian/patches/gcc-base-version.diff 2013-06-25 15:26:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/gcc-base-version.diff 2013-06-25 15:26:04.000000000 +0000 @@ -5,19 +5,19 @@ --- a/src/gcc/BASE-VER +++ b/src/gcc/BASE-VER @@ -1 +1 @@ --4.7.2 +-4.7.3 +4.7 Index: b/src/gcc/FULL-VER =================================================================== --- /dev/null +++ b/src/gcc/FULL-VER @@ -0,0 +1 @@ -+4.7.2 ++4.7.3 Index: b/src/gcc/Makefile.in =================================================================== --- a/src/gcc/Makefile.in +++ b/src/gcc/Makefile.in -@@ -793,11 +793,13 @@ +@@ -808,11 +808,13 @@ TM_H = $(GTM_H) insn-flags.h $(OPTIONS_H) # Variables for version information. @@ -32,7 +32,7 @@ BASEVER_c := $(shell cat $(BASEVER)) DEVPHASE_c := $(shell cat $(DEVPHASE)) DATESTAMP_c := $(shell cat $(DATESTAMP)) -@@ -816,7 +818,7 @@ +@@ -831,7 +833,7 @@ # development phase collapsed to the empty string in release mode # (i.e. if DEVPHASE_c is empty). The space immediately after the # comma in the $(if ...) constructs is significant - do not remove it. @@ -41,7 +41,7 @@ DEVPHASE_s := "\"$(if $(DEVPHASE_c), ($(DEVPHASE_c)))\"" DATESTAMP_s := "\"$(if $(DEVPHASE_c), $(DATESTAMP_c))\"" PKGVERSION_s:= "\"@PKGVERSION@\"" -@@ -2067,9 +2069,9 @@ +@@ -2083,9 +2085,9 @@ intl.h prefix.h coretypes.h $(TM_H) cppdefault.h $(TARGET_H) \ $(MACHMODE_H) @@ -53,7 +53,7 @@ # Language-independent files. -@@ -2147,11 +2149,11 @@ +@@ -2163,11 +2165,11 @@ dumpvers: dumpvers.c @@ -67,7 +67,7 @@ gtype-desc.o: gtype-desc.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ $(HASHTAB_H) $(SPLAY_TREE_H) $(OBSTACK_H) $(BITMAP_H) \ -@@ -2737,10 +2739,10 @@ +@@ -2753,10 +2755,10 @@ coretypes.h $(INPUT_H) $(TM_H) $(COMMON_TARGET_H) common/common-targhooks.h bversion.h: s-bversion; @true @@ -82,7 +82,7 @@ echo "#define BUILDING_GCC_VERSION (BUILDING_GCC_MAJOR * 1000 + BUILDING_GCC_MINOR)" >> bversion.h $(STAMP) s-bversion -@@ -3792,9 +3794,9 @@ +@@ -3808,9 +3810,9 @@ ## build/version.o is compiled by the $(COMPILER_FOR_BUILD) but needs ## several C macro definitions, just like version.o build/version.o: version.c version.h \ @@ -94,7 +94,7 @@ -DREVISION=$(REVISION_s) \ -DDEVPHASE=$(DEVPHASE_s) -DPKGVERSION=$(PKGVERSION_s) \ -DBUGURL=$(BUGURL_s) -o $@ $< -@@ -3970,7 +3972,7 @@ +@@ -3986,7 +3988,7 @@ -DSTANDARD_EXEC_PREFIX=\"$(libdir)/gcc/\" \ @TARGET_SYSTEM_ROOT_DEFINE@ @@ -103,7 +103,7 @@ cppbuiltin.o: cppbuiltin.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ $(TREE_H) cppbuiltin.h Makefile -@@ -3990,8 +3992,8 @@ +@@ -4006,8 +4008,8 @@ build/gcov-iov.o -o $@ gcov-iov.h: s-iov @@ -114,7 +114,7 @@ > tmp-gcov-iov.h $(SHELL) $(srcdir)/../move-if-change tmp-gcov-iov.h gcov-iov.h $(STAMP) s-iov -@@ -4256,8 +4258,8 @@ +@@ -4272,8 +4274,8 @@ TEXI_CPPINT_FILES = cppinternals.texi gcc-common.texi gcc-vers.texi # gcc-vers.texi is generated from the version files. @@ -125,7 +125,7 @@ if [ "$(DEVPHASE_c)" = "experimental" ]; \ then echo "@set DEVELOPMENT"; \ else echo "@clear DEVELOPMENT"; \ -@@ -4631,9 +4633,11 @@ +@@ -4647,9 +4649,11 @@ install-driver: installdirs xgcc$(exeext) -rm -f $(DESTDIR)$(bindir)/$(GCC_INSTALL_NAME)$(exeext) -$(INSTALL_PROGRAM) xgcc$(exeext) $(DESTDIR)$(bindir)/$(GCC_INSTALL_NAME)$(exeext) diff -Nru gcc-4.7-4.7.2/debian/patches/gcc-cloog-dl.diff gcc-4.7-4.7.3/debian/patches/gcc-cloog-dl.diff --- gcc-4.7-4.7.2/debian/patches/gcc-cloog-dl.diff 2013-06-25 15:26:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/gcc-cloog-dl.diff 2013-06-25 15:26:04.000000000 +0000 @@ -1,7 +1,7 @@ # DP: Link against -ldl instead of -lcloog -lppl. Exit with an error when using # DP: the Graphite loop transformation infrastructure without having the -# DP: libcloog-ppl0 package installed. Packages using these optimizations -# DP: should build-depend on libcloog-ppl0. +# DP: libcloog-ppl[01] package installed. Packages using these optimizations +# DP: should build-depend on libcloog-ppl1 | libcloog-ppl0. 2011-01-04 Jakub Jelinek @@ -22,7 +22,7 @@ =================================================================== --- a/src/gcc/Makefile.in +++ b/src/gcc/Makefile.in -@@ -965,6 +965,8 @@ +@@ -980,6 +980,8 @@ PLUGIN_H = plugin.h $(GCC_PLUGIN_H) PLUGIN_VERSION_H = plugin-version.h configargs.h LIBFUNCS_H = libfuncs.h $(HASHTAB_H) @@ -31,7 +31,7 @@ # # Now figure out from those variables how to compile and link. -@@ -1019,7 +1021,7 @@ +@@ -1034,7 +1036,7 @@ # and the system's installed libraries. LIBS = @LIBS@ libcommon.a $(CPPLIB) $(LIBINTL) $(LIBICONV) $(LIBIBERTY) \ $(LIBDECNUMBER) $(HOST_LIBS) @@ -40,7 +40,7 @@ $(ZLIB) # Any system libraries needed just for GNAT. SYSLIBS = @GNAT_LIBEXC@ -@@ -2605,40 +2607,40 @@ +@@ -2621,40 +2623,40 @@ $(TREE_FLOW_H) $(CFGLOOP_H) $(TREE_DATA_REF_H) tree-pass.h value-prof.h graphite.o : graphite.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(DIAGNOSTIC_CORE_H) \ $(TREE_FLOW_H) $(TREE_DUMP_H) $(CFGLOOP_H) $(TREE_DATA_REF_H) sese.h \ @@ -95,7 +95,7 @@ graphite-sese-to-poly.h tree-vect-loop.o: tree-vect-loop.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \ $(TM_H) $(GGC_H) $(TREE_H) $(BASIC_BLOCK_H) $(DIAGNOSTIC_H) $(TREE_FLOW_H) \ -@@ -3457,6 +3459,15 @@ +@@ -3473,6 +3475,15 @@ $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) \ $< $(OUTPUT_OPTION) @@ -399,7 +399,7 @@ =================================================================== --- a/src/gcc/graphite.c +++ b/src/gcc/graphite.c -@@ -56,6 +56,35 @@ +@@ -56,6 +56,37 @@ CloogState *cloog_state; @@ -412,7 +412,9 @@ + + if (cloog_pointers__.inited) + return cloog_pointers__.h != NULL; -+ h = dlopen ("libcloog-debian.so.0", RTLD_LAZY); ++ h = dlopen ("libcloog-ppl.so.1", RTLD_LAZY); ++ if (!h) ++ h = dlopen ("libcloog-ppl.so.0", RTLD_LAZY); + cloog_pointers__.h = h; + if (h == NULL) + return false; @@ -435,13 +437,13 @@ /* Print global statistics to FILE. */ static void -@@ -201,6 +230,12 @@ +@@ -201,6 +232,12 @@ return false; } + if (!init_cloog_pointers ()) + { -+ sorry ("Graphite loop optimizations can only be used if the libcloog-ppl0 package is installed"); ++ sorry ("Graphite loop optimizations can only be used if the libcloog-ppl1 or libcloog-ppl0 package is installed"); + return false; + } + diff -Nru gcc-4.7-4.7.2/debian/patches/gcc-default-relro.diff gcc-4.7-4.7.3/debian/patches/gcc-default-relro.diff --- gcc-4.7-4.7.2/debian/patches/gcc-default-relro.diff 2013-06-25 15:26:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/gcc-default-relro.diff 2013-06-25 15:26:04.000000000 +0000 @@ -19,11 +19,11 @@ Pretend the symbol @var{symbol} is undefined, to force linking of --- a/src/gcc/gcc.c +++ b/src/gcc/gcc.c -@@ -661,6 +661,7 @@ - }"PLUGIN_COND_CLOSE" \ - %{flto|flto=*:%= MIN_FATAL_STATUS) { @@ -62,7 +62,7 @@ if (WEXITSTATUS (status) > greatest_status) greatest_status = WEXITSTATUS (status); ret_code = -1; -@@ -2790,6 +2803,9 @@ +@@ -2808,6 +2821,9 @@ } } @@ -72,7 +72,7 @@ return ret_code; } } -@@ -5899,6 +5915,227 @@ +@@ -5919,6 +5935,227 @@ switches[switchnum].validated = 1; } diff -Nru gcc-4.7-4.7.2/debian/patches/gcc-linaro-doc.diff gcc-4.7-4.7.3/debian/patches/gcc-linaro-doc.diff --- gcc-4.7-4.7.2/debian/patches/gcc-linaro-doc.diff 2013-06-25 15:26:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/gcc-linaro-doc.diff 2013-06-25 15:26:04.000000000 +0000 @@ -1,15 +1,38 @@ -# DP: Changes for the Linaro 4.7-2012.11 release (documentation). +# DP: Changes for the Linaro 4.7-2013.04 release (documentation). +--- a/src/gcc/doc/extend.texi ++++ b/src/gcc/doc/extend.texi +@@ -8575,12 +8575,17 @@ + are @code{long double}. + @end deftypefn + +-@deftypefn {Built-in Function} int32_t __builtin_bswap32 (int32_t x) ++@deftypefn {Built-in Function} int16_t __builtin_bswap16 (int16_t x) + Returns @var{x} with the order of the bytes reversed; for example, +-@code{0xaabbccdd} becomes @code{0xddccbbaa}. Byte here always means ++@code{0xaabb} becomes @code{0xbbaa}. Byte here always means + exactly 8 bits. + @end deftypefn + ++@deftypefn {Built-in Function} int32_t __builtin_bswap32 (int32_t x) ++Similar to @code{__builtin_bswap16}, except the argument and return types ++are 32-bit. ++@end deftypefn ++ + @deftypefn {Built-in Function} int64_t __builtin_bswap64 (int64_t x) + Similar to @code{__builtin_bswap32}, except the argument and return types + are 64-bit. +@@ -13466,7 +13471,6 @@ + double __builtin_recipdiv (double, double); + double __builtin_rsqrt (double); + long __builtin_bpermd (long, long); +-int __builtin_bswap16 (int); + @end smallexample + + The @code{vec_rsqrt}, @code{__builtin_rsqrt}, and --- a/src/gcc/doc/fragments.texi +++ b/src/gcc/doc/fragments.texi -@@ -1,5 +1,5 @@ - @c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, --@c 1999, 2000, 2001, 2003, 2004, 2005, 2008, 2011 -+@c 1999, 2000, 2001, 2003, 2004, 2005, 2008, 2011, 2012 - @c Free Software Foundation, Inc. - @c This is part of the GCC manual. - @c For copying conditions, see the file gcc.texi. -@@ -121,6 +121,29 @@ +@@ -127,6 +127,29 @@ *mthumb/*mhard-float* @end smallexample @@ -39,42 +62,35 @@ @findex MULTILIB_EXTRA_OPTS @item MULTILIB_EXTRA_OPTS Sometimes it is desirable that when building multiple versions of ---- a/src/gcc/doc/fsf-funding.7 -+++ b/src/gcc/doc/fsf-funding.7 -@@ -124,7 +124,7 @@ - .\" ======================================================================== - .\" - .IX Title "FSF-FUNDING 7" --.TH FSF-FUNDING 7 "2012-09-20" "gcc-4.7.2" "GNU" -+.TH FSF-FUNDING 7 "2012-11-06" "gcc-4.7.3" "GNU" - .\" For nroff, turn off justification. Always turn off hyphenation; it makes - .\" way too many mistakes in technical documents. - .if n .ad l ---- a/src/gcc/doc/gfdl.7 -+++ b/src/gcc/doc/gfdl.7 -@@ -124,7 +124,7 @@ - .\" ======================================================================== - .\" - .IX Title "GFDL 7" --.TH GFDL 7 "2012-09-20" "gcc-4.7.2" "GNU" -+.TH GFDL 7 "2012-11-06" "gcc-4.7.3" "GNU" - .\" For nroff, turn off justification. Always turn off hyphenation; it makes - .\" way too many mistakes in technical documents. - .if n .ad l ---- a/src/gcc/doc/gpl.7 -+++ b/src/gcc/doc/gpl.7 -@@ -124,7 +124,7 @@ - .\" ======================================================================== - .\" - .IX Title "GPL 7" --.TH GPL 7 "2012-09-20" "gcc-4.7.2" "GNU" -+.TH GPL 7 "2012-11-06" "gcc-4.7.3" "GNU" - .\" For nroff, turn off justification. Always turn off hyphenation; it makes - .\" way too many mistakes in technical documents. - .if n .ad l +--- a/src/gcc/doc/install.texi ++++ b/src/gcc/doc/install.texi +@@ -1047,6 +1047,15 @@ + conventions, etc.@: should not be built. The default is to build a + predefined set of them. + ++@item --enable-multiarch ++Specify whether to enable or disable multiarch support. The default is ++to check for glibc start files in a multiarch location, and enable it ++if the files are found. The auto detection is enabled for native builds, ++and for cross builds configured with @option{--with-sysroot}, and without ++@option{--with-native-system-header-dir}. ++More documentation about multiarch can be found at ++@uref{http://wiki.debian.org/Multiarch}. ++ + Some targets provide finer-grained control over which multilibs are built + (e.g., @option{--disable-softfloat}): + @table @code --- a/src/gcc/doc/invoke.texi +++ b/src/gcc/doc/invoke.texi -@@ -409,7 +409,8 @@ +@@ -403,13 +403,15 @@ + -fsplit-ivs-in-unroller -fsplit-wide-types -fstack-protector @gol + -fstack-protector-all -fstrict-aliasing -fstrict-overflow @gol + -fthread-jumps -ftracer -ftree-bit-ccp @gol +--ftree-builtin-call-dce -ftree-ccp -ftree-ch -ftree-copy-prop @gol ++-ftree-builtin-call-dce -ftree-ccp -ftree-ch @gol ++-ftree-coalesce-inline-vars -ftree-coalesce-vars -ftree-copy-prop @gol + -ftree-copyrename -ftree-dce -ftree-dominator-opts -ftree-dse @gol + -ftree-forwprop -ftree-fre -ftree-loop-if-convert @gol -ftree-loop-if-convert-stores -ftree-loop-im @gol -ftree-phiprop -ftree-loop-distribution -ftree-loop-distribute-patterns @gol -ftree-loop-ivcanon -ftree-loop-linear -ftree-loop-optimize @gol @@ -84,7 +100,7 @@ -ftree-sink -ftree-sra -ftree-switch-conversion -ftree-tail-merge @gol -ftree-ter -ftree-vect-loop-version -ftree-vectorize -ftree-vrp @gol -funit-at-a-time -funroll-all-loops -funroll-loops @gol -@@ -460,6 +461,15 @@ +@@ -460,6 +462,15 @@ @c Try and put the significant identifier (CPU or system) first, @c so users have a clue at guessing where the ones they want will be. @@ -100,16 +116,17 @@ @emph{Adapteva Epiphany Options} @gccoptlist{-mhalf-reg-file -mprefer-short-insn-regs @gol -mbranch-cost=@var{num} -mcmove -mnops=@var{num} -msoft-cmpsf @gol -@@ -626,7 +636,7 @@ - -mincoming-stack-boundary=@var{num} @gol - -mcld -mcx16 -msahf -mmovbe -mcrc32 @gol - -mrecip -mrecip=@var{opt} @gol ---mvzeroupper @gol -+-mvzeroupper -mprefer-avx128 @gol - -mmmx -msse -msse2 -msse3 -mssse3 -msse4.1 -msse4.2 -msse4 -mavx @gol - -mavx2 -maes -mpclmul -mfsgsbase -mrdrnd -mf16c -mfma @gol - -msse4a -m3dnow -mpopcnt -mabm -mbmi -mtbm -mfma4 -mxop -mlzcnt @gol -@@ -6233,8 +6243,8 @@ +@@ -494,7 +505,8 @@ + -mtp=@var{name} -mtls-dialect=@var{dialect} @gol + -mword-relocations @gol + -mfix-cortex-m3-ldrd @gol +--munaligned-access} ++-munaligned-access @gol ++-mneon-for-64bits} + + @emph{AVR Options} + @gccoptlist{-mmcu=@var{mcu} -maccumulate-args -mbranch-cost=@var{cost} @gol +@@ -6237,8 +6249,8 @@ Optimize yet more. @option{-O3} turns on all optimizations specified by @option{-O2} and also turns on the @option{-finline-functions}, @option{-funswitch-loops}, @option{-fpredictive-commoning}, @@ -120,7 +137,7 @@ @item -O0 @opindex O0 -@@ -7029,6 +7039,11 @@ +@@ -7033,6 +7045,11 @@ Perform partial redundancy elimination (PRE) on trees. This flag is enabled by default at @option{-O2} and @option{-O3}. @@ -132,7 +149,32 @@ @item -ftree-forwprop @opindex ftree-forwprop Perform forward propagation on trees. This flag is enabled by default -@@ -10325,6 +10340,7 @@ +@@ -7428,6 +7445,24 @@ + variable names which more closely resemble the original variables. This flag + is enabled by default at @option{-O} and higher. + ++@item -ftree-coalesce-inlined-vars ++Tell the copyrename pass (see @option{-ftree-copyrename}) to attempt to ++combine small user-defined variables too, but only if they were inlined ++from other functions. It is a more limited form of ++@option{-ftree-coalesce-vars}. This may harm debug information of such ++inlined variables, but it will keep variables of the inlined-into ++function apart from each other, such that they are more likely to ++contain the expected values in a debugging session. This was the ++default in GCC versions older than 4.7. ++ ++@item -ftree-coalesce-vars ++Tell the copyrename pass (see @option{-ftree-copyrename}) to attempt to ++combine small user-defined variables too, instead of just compiler ++temporaries. This may severely limit the ability to debug an optimized ++program compiled with @option{-fno-var-tracking-assignments}. In the ++negated form, this flag prevents SSA coalescing of user variables, ++including inlined ones. This option is enabled by default. ++ + @item -ftree-ter + @opindex ftree-ter + Perform temporary expression replacement during the SSA->normal phase. Single +@@ -10329,6 +10364,7 @@ @c in Machine Dependent Options @menu @@ -140,7 +182,7 @@ * Adapteva Epiphany Options:: * ARM Options:: * AVR Options:: -@@ -10533,6 +10549,125 @@ +@@ -10537,6 +10573,125 @@ @end table @@ -266,217 +308,21 @@ @node ARM Options @subsection ARM Options @cindex ARM options -@@ -10955,9 +11090,6 @@ - @opindex mmcu - Specify Atmel AVR instruction set architectures (ISA) or MCU type. - --For a complete list of @var{mcu} values that are supported by @command{avr-gcc}, --see the compiler output when called with the @option{--help=target} --command line option. - The default for this option is@tie{}@code{avr2}. - - GCC supports the following AVR devices and ISAs: -@@ -10966,22 +11098,22 @@ - - @item avr2 - ``Classic'' devices with up to 8@tie{}KiB of program memory. --@*@var{mcu}@tie{}= @code{at90c8534}, @code{at90s2313}, --@code{at90s2323}, @code{at90s2333}, @code{at90s2343}, --@code{at90s4414}, @code{at90s4433}, @code{at90s4434}, --@code{at90s8515}, @code{at90s8535}, @code{attiny22}, @code{attiny26}. -+@*@var{mcu}@tie{}= @code{attiny22}, @code{attiny26}, @code{at90c8534}, -+@code{at90s2313}, @code{at90s2323}, @code{at90s2333}, -+@code{at90s2343}, @code{at90s4414}, @code{at90s4433}, -+@code{at90s4434}, @code{at90s8515}, @code{at90s8535}. - - @item avr25 - ``Classic'' devices with up to 8@tie{}KiB of program memory and with - the @code{MOVW} instruction. --@*@var{mcu}@tie{}= @code{at86rf401}, @code{ata6289}, @code{attiny13}, --@code{attiny13a}, @code{attiny2313}, @code{attiny2313a}, --@code{attiny24}, @code{attiny24a}, @code{attiny25}, @code{attiny261}, --@code{attiny261a}, @code{attiny4313}, @code{attiny43u}, -+@*@var{mcu}@tie{}= @code{ata6289}, @code{attiny13}, @code{attiny13a}, -+@code{attiny2313}, @code{attiny2313a}, @code{attiny24}, -+@code{attiny24a}, @code{attiny25}, @code{attiny261}, -+@code{attiny261a}, @code{attiny43u}, @code{attiny4313}, - @code{attiny44}, @code{attiny44a}, @code{attiny45}, @code{attiny461}, - @code{attiny461a}, @code{attiny48}, @code{attiny84}, @code{attiny84a}, - @code{attiny85}, @code{attiny861}, @code{attiny861a}, @code{attiny87}, --@code{attiny88}. -+@code{attiny88}, @code{at86rf401}. - - @item avr3 - ``Classic'' devices with 16@tie{}KiB up to 64@tie{}KiB of program memory. -@@ -10989,57 +11121,58 @@ - - @item avr31 - ``Classic'' devices with 128@tie{}KiB of program memory. --@*@var{mcu}@tie{}= @code{at43usb320}, @code{atmega103}. -+@*@var{mcu}@tie{}= @code{atmega103}, @code{at43usb320}. - - @item avr35 - ``Classic'' devices with 16@tie{}KiB up to 64@tie{}KiB of program - memory and with the @code{MOVW} instruction. --@*@var{mcu}@tie{}= @code{at90usb162}, @code{at90usb82}, --@code{atmega16u2}, @code{atmega32u2}, @code{atmega8u2}, --@code{attiny167}. -+@*@var{mcu}@tie{}= @code{atmega16u2}, @code{atmega32u2}, -+@code{atmega8u2}, @code{attiny167}, @code{at90usb162}, -+@code{at90usb82}. - - @item avr4 - ``Enhanced'' devices with up to 8@tie{}KiB of program memory. --@*@var{mcu}@tie{}= @code{at90pwm1}, @code{at90pwm2}, @code{at90pwm2b}, --@code{at90pwm3}, @code{at90pwm3b}, @code{at90pwm81}, @code{atmega48}, --@code{atmega48a}, @code{atmega48p}, @code{atmega8}, @code{atmega8515}, --@code{atmega8535}, @code{atmega88}, @code{atmega88a}, --@code{atmega88p}, @code{atmega88pa}, @code{atmega8hva}. -+@*@var{mcu}@tie{}= @code{atmega48}, @code{atmega48a}, -+@code{atmega48p}, @code{atmega8}, @code{atmega8hva}, -+@code{atmega8515}, @code{atmega8535}, @code{atmega88}, -+@code{atmega88a}, @code{atmega88p}, @code{atmega88pa}, -+@code{at90pwm1}, @code{at90pwm2}, @code{at90pwm2b}, @code{at90pwm3}, -+@code{at90pwm3b}, @code{at90pwm81}. - - @item avr5 - ``Enhanced'' devices with 16@tie{}KiB up to 64@tie{}KiB of program memory. --@*@var{mcu}@tie{}= @code{at90can32}, @code{at90can64}, --@code{at90pwm216}, @code{at90pwm316}, @code{at90scr100}, --@code{at90usb646}, @code{at90usb647}, @code{at94k}, @code{atmega16}, --@code{atmega161}, @code{atmega162}, @code{atmega163}, --@code{atmega164a}, @code{atmega164p}, @code{atmega165}, --@code{atmega165a}, @code{atmega165p}, @code{atmega168}, --@code{atmega168a}, @code{atmega168p}, @code{atmega169}, --@code{atmega169a}, @code{atmega169p}, @code{atmega169pa}, --@code{atmega16a}, @code{atmega16hva}, @code{atmega16hva2}, --@code{atmega16hvb}, @code{atmega16m1}, @code{atmega16u4}, --@code{atmega32}, @code{atmega323}, @code{atmega324a}, --@code{atmega324p}, @code{atmega324pa}, @code{atmega325}, -+@*@var{mcu}@tie{}= @code{atmega16}, @code{atmega16a}, -+@code{atmega16hva}, @code{atmega16hva2}, @code{atmega16hvb}, -+@code{atmega16m1}, @code{atmega16u4}, @code{atmega161}, -+@code{atmega162}, @code{atmega163}, @code{atmega164a}, -+@code{atmega164p}, @code{atmega165}, @code{atmega165a}, -+@code{atmega165p}, @code{atmega168}, @code{atmega168a}, -+@code{atmega168p}, @code{atmega169}, @code{atmega169a}, -+@code{atmega169p}, @code{atmega169pa}, @code{atmega32}, -+@code{atmega32c1}, @code{atmega32hvb}, @code{atmega32m1}, -+@code{atmega32u4}, @code{atmega32u6}, @code{atmega323}, -+@code{atmega324a}, @code{atmega324p}, @code{atmega324pa}, -+@code{atmega325}, @code{atmega325a}, @code{atmega325p}, - @code{atmega3250}, @code{atmega3250a}, @code{atmega3250p}, --@code{atmega325a}, @code{atmega325p}, @code{atmega328}, --@code{atmega328p}, @code{atmega329}, @code{atmega3290}, --@code{atmega3290a}, @code{atmega3290p}, @code{atmega329a}, --@code{atmega329p}, @code{atmega329pa}, @code{atmega32c1}, --@code{atmega32hvb}, @code{atmega32m1}, @code{atmega32u4}, --@code{atmega32u6}, @code{atmega406}, @code{atmega64}, --@code{atmega640}, @code{atmega644}, @code{atmega644a}, --@code{atmega644p}, @code{atmega644pa}, @code{atmega645}, --@code{atmega6450}, @code{atmega6450a}, @code{atmega6450p}, --@code{atmega645a}, @code{atmega645p}, @code{atmega649}, --@code{atmega6490}, @code{atmega649a}, @code{atmega649p}, --@code{atmega64c1}, @code{atmega64hve}, @code{atmega64m1}, -+@code{atmega328}, @code{atmega328p}, @code{atmega329}, -+@code{atmega329a}, @code{atmega329p}, @code{atmega329pa}, -+@code{atmega3290}, @code{atmega3290a}, @code{atmega3290p}, -+@code{atmega406}, @code{atmega64}, @code{atmega64c1}, -+@code{atmega64hve}, @code{atmega64m1}, @code{atmega640}, -+@code{atmega644}, @code{atmega644a}, @code{atmega644p}, -+@code{atmega644pa}, @code{atmega645}, @code{atmega645a}, -+@code{atmega645p}, @code{atmega6450}, @code{atmega6450a}, -+@code{atmega6450p}, @code{atmega649}, @code{atmega649a}, -+@code{atmega649p}, @code{atmega6490}, @code{at90can32}, -+@code{at90can64}, @code{at90pwm216}, @code{at90pwm316}, -+@code{at90scr100}, @code{at90usb646}, @code{at90usb647}, @code{at94k}, - @code{m3000}. - - @item avr51 - ``Enhanced'' devices with 128@tie{}KiB of program memory. --@*@var{mcu}@tie{}= @code{at90can128}, @code{at90usb1286}, --@code{at90usb1287}, @code{atmega128}, @code{atmega1280}, --@code{atmega1281}, @code{atmega1284p}, @code{atmega128rfa1}. -+@*@var{mcu}@tie{}= @code{atmega128}, @code{atmega128rfa1}, -+@code{atmega1280}, @code{atmega1281}, @code{atmega1284p}, -+@code{at90can128}, @code{at90usb1286}, @code{at90usb1287}. - - @item avr6 - ``Enhanced'' devices with 3-byte PC, i.e.@: with more than -@@ -11077,8 +11210,8 @@ - @item avr1 - This ISA is implemented by the minimal AVR core and supported for - assembler only. --@*@var{mcu}@tie{}= @code{at90s1200}, @code{attiny11}, @code{attiny12}, --@code{attiny15}, @code{attiny28}. -+@*@var{mcu}@tie{}= @code{attiny11}, @code{attiny12}, @code{attiny15}, -+@code{attiny28}, @code{at90s1200}. - +@@ -10948,6 +11103,11 @@ + preprocessor symbol @code{__ARM_FEATURE_UNALIGNED} will also be + defined. + ++@item -mneon-for-64bits ++@opindex mneon-for-64bits ++Enables using Neon to handle scalar 64-bits operations. This is ++disabled by default since the cost of moving data from core registers ++to Neon is high. @end table -@@ -11139,10 +11272,12 @@ - - @item -mshort-calls - @opindex mshort-calls -+This option has been deprecated and will be removed in GCC 4.8. -+See @code{-mrelax} for a replacement. -+ - Use @code{RCALL}/@code{RJMP} instructions even on devices with - 16@tie{}KiB or more of program memory, i.e.@: on devices that - have the @code{CALL} and @code{JMP} instructions. --See also the @code{-mrelax} command line option. - - @item -msp8 - @opindex msp8 -@@ -11373,6 +11508,23 @@ - - @table @code - -+@item __AVR_ARCH__ -+Build-in macro that resolves to a decimal number that identifies the -+architecture and depends on the @code{-mmcu=@var{mcu}} option. -+Possible values are: -+ -+@code{2}, @code{25}, @code{3}, @code{31}, @code{35}, -+@code{4}, @code{5}, @code{51}, @code{6}, @code{102}, @code{104}, -+@code{105}, @code{106}, @code{107} -+ -+for @var{mcu}=@code{avr2}, @code{avr25}, @code{avr3}, -+@code{avr31}, @code{avr35}, @code{avr4}, @code{avr5}, @code{avr51}, -+@code{avr6}, @code{avrxmega2}, @code{avrxmega4}, @code{avrxmega5}, -+@code{avrxmega6}, @code{avrxmega7}, respectively. -+If @var{mcu} specifies a device, this built-in macro is set -+accordingly. For example, with @code{-mmcu=atmega8} the macro will be -+defined to @code{4}. -+ - @item __AVR_@var{Device}__ - Setting @code{-mmcu=@var{device}} defines this built-in macro which reflects - the device's name. For example, @code{-mmcu=atmega8} defines the -@@ -11385,6 +11537,9 @@ - @var{Device} in the built-in macro and @var{device} in - @code{-mmcu=@var{device}} is that the latter is always lowercase. - -+If @var{device} is not a device but only a core architecture like -+@code{avr51}, this macro will not be defined. -+ - @item __AVR_HAVE_ELPM__ - The device has the the @code{ELPM} instruction. - -@@ -13679,6 +13834,11 @@ - AVX to SSE transition penalty as well as remove unnecessary zeroupper - intrinsics. - -+@item -mprefer-avx128 -+@opindex mprefer-avx128 -+This option instructs GCC to use 128-bit AVX instructions instead of -+256-bit AVX instructions in the auto-vectorizer. -+ - @item -mcx16 - @opindex mcx16 - This option will enable GCC to use CMPXCHG16B instruction in generated code. + @node AVR Options --- a/src/gcc/doc/md.texi +++ b/src/gcc/doc/md.texi -@@ -1653,6 +1653,65 @@ +@@ -1653,6 +1653,62 @@ the meanings of that architecture's constraints. @table @emph @@ -534,15 +380,23 @@ +A memory address suitable for a load/store pair instruction in SI, DI, SF and +DF modes + -+@item Utf -+A memory address suitable for a load/store pair instruction in TF mode -+ +@end table + @item ARM family---@file{config/arm/arm.h} @table @code @item f -@@ -8888,6 +8947,7 @@ +@@ -4736,6 +4792,10 @@ + Vector shift and rotate instructions that take vectors as operand 2 + instead of a scalar type. + ++@cindex @code{bswap@var{m}2} instruction pattern ++@item @samp{bswap@var{m}2} ++Reverse the order of bytes of operand 1 and store the result in operand 0. ++ + @cindex @code{neg@var{m}2} instruction pattern + @cindex @code{ssneg@var{m}2} instruction pattern + @cindex @code{usneg@var{m}2} instruction pattern +@@ -8888,6 +8948,7 @@ @menu * Mode Iterators:: Generating variations of patterns for different modes. * Code Iterators:: Doing the same for codes. @@ -550,7 +404,7 @@ @end menu @node Mode Iterators -@@ -9159,4 +9219,81 @@ +@@ -9159,4 +9220,81 @@ @dots{} @end smallexample @@ -632,3 +486,42 @@ +@end smallexample + @end ifset +--- a/src/gcc/doc/sourcebuild.texi ++++ b/src/gcc/doc/sourcebuild.texi +@@ -1502,11 +1502,19 @@ + @item arm_neon_hw + Test system supports executing NEON instructions. + ++@item arm_neonv2_hw ++Test system supports executing NEON v2 instructions. ++ + @item arm_neon_ok + @anchor{arm_neon_ok} + ARM Target supports @code{-mfpu=neon -mfloat-abi=softfp} or compatible + options. Some multilibs may be incompatible with these options. + ++@item arm_neonv2_ok ++@anchor{arm_neon2_ok} ++ARM Target supports @code{-mfpu=neon -mfloat-abi=softfp} or compatible ++options. Some multilibs may be incompatible with these options. ++ + @item arm_neon_fp16_ok + @anchor{arm_neon_fp16_ok} + ARM Target supports @code{-mfpu=neon-fp16 -mfloat-abi=softfp} or compatible +--- a/src/INSTALL/configure.html ++++ b/src/INSTALL/configure.html +@@ -446,6 +446,14 @@ + conventions, etc. should not be built. The default is to build a + predefined set of them. + ++
--enable-multiarch
Specify whether to enable or disable multiarch support. The default is ++to check for glibc start files in a multiarch location, and enable it ++if the files are found. The auto detection is enabled for native builds, ++and for cross builds configured with --with-sysroot, and without ++--with-native-system-header-dir. ++More documentation about multiarch can be found at ++http://wiki.debian.org/Multiarch. ++ +

Some targets provide finer-grained control over which multilibs are built + (e.g., --disable-softfloat): +

diff -Nru gcc-4.7-4.7.2/debian/patches/gcc-linaro-updates.diff gcc-4.7-4.7.3/debian/patches/gcc-linaro-updates.diff --- gcc-4.7-4.7.2/debian/patches/gcc-linaro-updates.diff 2013-06-25 15:26:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/gcc-linaro-updates.diff 2013-06-25 15:26:04.000000000 +0000 @@ -1,2 +1,2 @@ -# DP: Linaro updates from the 4.7-2012.xx-stable branch: +# DP: Linaro updates from the 4.7-2013.xx-stable branch: diff -Nru gcc-4.7-4.7.2/debian/patches/gcc-linaro.diff gcc-4.7-4.7.3/debian/patches/gcc-linaro.diff --- gcc-4.7-4.7.2/debian/patches/gcc-linaro.diff 2013-06-25 15:26:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/gcc-linaro.diff 2013-06-25 15:26:04.000000000 +0000 @@ -1,530 +1,1461 @@ -# DP: Changes for the Linaro 4.7-2012.11 release. +# DP: Changes for the Linaro 4.7-2013.04 release. ---- a/src/boehm-gc/ChangeLog -+++ b/src/boehm-gc/ChangeLog -@@ -1,3 +1,11 @@ -+2012-09-20 Jakub Jelinek -+ -+ PR other/43620 -+ * Makefile.am (AUTOMAKE_OPTIONS): Add no-dist. -+ * Makefile.in: Regenerated. -+ * include/Makefile.in: Regenerated. -+ * testsuite/Makefile.in: Regenerated. -+ - 2012-09-20 Release Manager - - * GCC 4.7.2 released. ---- a/src/boehm-gc/include/Makefile.in -+++ b/src/boehm-gc/include/Makefile.in -@@ -36,9 +36,9 @@ - host_triplet = @host@ - target_triplet = @target@ - subdir = include --DIST_COMMON = $(noinst_HEADERS) $(srcdir)/Makefile.am \ -- $(srcdir)/Makefile.in $(srcdir)/gc_config.h.in \ -- $(srcdir)/gc_ext_config.h.in -+DIST_COMMON = $(srcdir)/Makefile.in $(srcdir)/Makefile.am \ -+ $(srcdir)/gc_config.h.in $(srcdir)/gc_ext_config.h.in \ -+ $(noinst_HEADERS) - ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 - am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \ - $(top_srcdir)/../config/depstand.m4 \ -@@ -55,11 +55,9 @@ - CONFIG_CLEAN_FILES = - CONFIG_CLEAN_VPATH_FILES = - SOURCES = --DIST_SOURCES = - HEADERS = $(noinst_HEADERS) - ETAGS = etags - CTAGS = ctags --DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) - ACLOCAL = @ACLOCAL@ - AMTAR = @AMTAR@ - AM_CPPFLAGS = @AM_CPPFLAGS@ -@@ -323,37 +321,6 @@ - - distclean-tags: - -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags -- --distdir: $(DISTFILES) -- @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \ -- topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \ -- list='$(DISTFILES)'; \ -- dist_files=`for file in $$list; do echo $$file; done | \ -- sed -e "s|^$$srcdirstrip/||;t" \ -- -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \ -- case $$dist_files in \ -- */*) $(MKDIR_P) `echo "$$dist_files" | \ -- sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \ -- sort -u` ;; \ -- esac; \ -- for file in $$dist_files; do \ -- if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \ -- if test -d $$d/$$file; then \ -- dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \ -- if test -d "$(distdir)/$$file"; then \ -- find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \ -- fi; \ -- if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \ -- cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \ -- find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \ -- fi; \ -- cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \ -- else \ -- test -f "$(distdir)/$$file" \ -- || cp -p $$d/$$file "$(distdir)/$$file" \ -- || exit 1; \ -- fi; \ -- done - check-am: all-am - check: check-am - all-am: Makefile $(HEADERS) gc_config.h gc_ext_config.h -@@ -453,16 +420,15 @@ - - .PHONY: CTAGS GTAGS all all-am check check-am clean clean-generic \ - clean-libtool ctags distclean distclean-generic distclean-hdr \ -- distclean-libtool distclean-tags distdir dvi dvi-am html \ -- html-am info info-am install install-am install-data \ -- install-data-am install-dvi install-dvi-am install-exec \ -- install-exec-am install-html install-html-am install-info \ -- install-info-am install-man install-pdf install-pdf-am \ -- install-ps install-ps-am install-strip installcheck \ -- installcheck-am installdirs maintainer-clean \ -- maintainer-clean-generic mostlyclean mostlyclean-generic \ -- mostlyclean-libtool pdf pdf-am ps ps-am tags uninstall \ -- uninstall-am -+ distclean-libtool distclean-tags dvi dvi-am html html-am info \ -+ info-am install install-am install-data install-data-am \ -+ install-dvi install-dvi-am install-exec install-exec-am \ -+ install-html install-html-am install-info install-info-am \ -+ install-man install-pdf install-pdf-am install-ps \ -+ install-ps-am install-strip installcheck installcheck-am \ -+ installdirs maintainer-clean maintainer-clean-generic \ -+ mostlyclean mostlyclean-generic mostlyclean-libtool pdf pdf-am \ -+ ps ps-am tags uninstall uninstall-am - - - # Tell versions [3.59,3.63) of GNU make to not export all variables. ---- a/src/boehm-gc/Makefile.am -+++ b/src/boehm-gc/Makefile.am -@@ -4,7 +4,7 @@ - ## files that should be in the distribution are not mentioned in this - ## Makefile.am. - --AUTOMAKE_OPTIONS = foreign subdir-objects -+AUTOMAKE_OPTIONS = foreign subdir-objects no-dist - ACLOCAL_AMFLAGS = -I .. -I ../config - - SUBDIRS = include testsuite ---- a/src/boehm-gc/Makefile.in -+++ b/src/boehm-gc/Makefile.in -@@ -36,13 +36,10 @@ - host_triplet = @host@ - target_triplet = @target@ - subdir = . --DIST_COMMON = $(am__configure_deps) $(srcdir)/../compile \ -- $(srcdir)/../config.guess $(srcdir)/../config.sub \ -- $(srcdir)/../depcomp $(srcdir)/../install-sh \ -- $(srcdir)/../ltmain.sh $(srcdir)/../missing \ -- $(srcdir)/../mkinstalldirs $(srcdir)/Makefile.am \ -- $(srcdir)/Makefile.in $(srcdir)/threads.mk.in \ -- $(top_srcdir)/configure ChangeLog depcomp -+DIST_COMMON = ChangeLog $(srcdir)/Makefile.in $(srcdir)/Makefile.am \ -+ $(top_srcdir)/configure $(am__configure_deps) \ -+ $(srcdir)/../mkinstalldirs $(srcdir)/threads.mk.in \ -+ $(srcdir)/../depcomp - ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 - am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \ - $(top_srcdir)/../config/depstand.m4 \ -@@ -63,14 +60,6 @@ - CONFIG_CLEAN_VPATH_FILES = - LTLIBRARIES = $(noinst_LTLIBRARIES) - am__DEPENDENCIES_1 = --am__libgcjgc_la_SOURCES_DIST = allchblk.c alloc.c blacklst.c \ -- checksums.c dbg_mlc.c dyn_load.c finalize.c gc_dlopen.c \ -- gcj_mlc.c headers.c malloc.c mallocx.c mark.c mark_rts.c \ -- misc.c new_hblk.c obj_map.c os_dep.c pcr_interface.c \ -- ptr_chck.c real_malloc.c reclaim.c specific.c stubborn.c \ -- typd_mlc.c backgraph.c win32_threads.c pthread_support.c \ -- pthread_stop_world.c darwin_stop_world.c \ -- powerpc_darwin_mach_dep.s - @POWERPC_DARWIN_TRUE@am__objects_1 = powerpc_darwin_mach_dep.lo - am_libgcjgc_la_OBJECTS = allchblk.lo alloc.lo blacklst.lo checksums.lo \ - dbg_mlc.lo dyn_load.lo finalize.lo gc_dlopen.lo gcj_mlc.lo \ -@@ -80,14 +69,6 @@ - backgraph.lo win32_threads.lo pthread_support.lo \ - pthread_stop_world.lo darwin_stop_world.lo $(am__objects_1) - libgcjgc_la_OBJECTS = $(am_libgcjgc_la_OBJECTS) --am__libgcjgc_convenience_la_SOURCES_DIST = allchblk.c alloc.c \ -- blacklst.c checksums.c dbg_mlc.c dyn_load.c finalize.c \ -- gc_dlopen.c gcj_mlc.c headers.c malloc.c mallocx.c mark.c \ -- mark_rts.c misc.c new_hblk.c obj_map.c os_dep.c \ -- pcr_interface.c ptr_chck.c real_malloc.c reclaim.c specific.c \ -- stubborn.c typd_mlc.c backgraph.c win32_threads.c \ -- pthread_support.c pthread_stop_world.c darwin_stop_world.c \ -- powerpc_darwin_mach_dep.s - am__objects_2 = allchblk.lo alloc.lo blacklst.lo checksums.lo \ - dbg_mlc.lo dyn_load.lo finalize.lo gc_dlopen.lo gcj_mlc.lo \ - headers.lo malloc.lo mallocx.lo mark.lo mark_rts.lo misc.lo \ -@@ -115,8 +96,6 @@ - LTCCASCOMPILE = $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ - --mode=compile $(CCAS) $(AM_CCASFLAGS) $(CCASFLAGS) - SOURCES = $(libgcjgc_la_SOURCES) $(libgcjgc_convenience_la_SOURCES) --DIST_SOURCES = $(am__libgcjgc_la_SOURCES_DIST) \ -- $(am__libgcjgc_convenience_la_SOURCES_DIST) - MULTISRCTOP = - MULTIBUILDTOP = - MULTIDIRS = -@@ -133,47 +112,10 @@ - RECURSIVE_CLEAN_TARGETS = mostlyclean-recursive clean-recursive \ - distclean-recursive maintainer-clean-recursive - AM_RECURSIVE_TARGETS = $(RECURSIVE_TARGETS:-recursive=) \ -- $(RECURSIVE_CLEAN_TARGETS:-recursive=) tags TAGS ctags CTAGS \ -- distdir dist dist-all distcheck -+ $(RECURSIVE_CLEAN_TARGETS:-recursive=) tags TAGS ctags CTAGS - ETAGS = etags - CTAGS = ctags - DIST_SUBDIRS = $(SUBDIRS) --DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) --distdir = $(PACKAGE)-$(VERSION) --top_distdir = $(distdir) --am__remove_distdir = \ -- { test ! -d "$(distdir)" \ -- || { find "$(distdir)" -type d ! -perm -200 -exec chmod u+w {} ';' \ -- && rm -fr "$(distdir)"; }; } --am__relativize = \ -- dir0=`pwd`; \ -- sed_first='s,^\([^/]*\)/.*$$,\1,'; \ -- sed_rest='s,^[^/]*/*,,'; \ -- sed_last='s,^.*/\([^/]*\)$$,\1,'; \ -- sed_butlast='s,/*[^/]*$$,,'; \ -- while test -n "$$dir1"; do \ -- first=`echo "$$dir1" | sed -e "$$sed_first"`; \ -- if test "$$first" != "."; then \ -- if test "$$first" = ".."; then \ -- dir2=`echo "$$dir0" | sed -e "$$sed_last"`/"$$dir2"; \ -- dir0=`echo "$$dir0" | sed -e "$$sed_butlast"`; \ -- else \ -- first2=`echo "$$dir2" | sed -e "$$sed_first"`; \ -- if test "$$first2" = "$$first"; then \ -- dir2=`echo "$$dir2" | sed -e "$$sed_rest"`; \ -- else \ -- dir2="../$$dir2"; \ -- fi; \ -- dir0="$$dir0"/"$$first"; \ -- fi; \ -- fi; \ -- dir1=`echo "$$dir1" | sed -e "$$sed_rest"`; \ -- done; \ -- reldir="$$dir2" --DIST_ARCHIVES = $(distdir).tar.gz --GZIP_ENV = --best --distuninstallcheck_listfiles = find . -type f -print --distcleancheck_listfiles = find . -type f -print - ACLOCAL = @ACLOCAL@ - AMTAR = @AMTAR@ - AM_CPPFLAGS = @AM_CPPFLAGS@ -@@ -314,7 +256,7 @@ - top_build_prefix = @top_build_prefix@ - top_builddir = @top_builddir@ - top_srcdir = @top_srcdir@ --AUTOMAKE_OPTIONS = foreign subdir-objects -+AUTOMAKE_OPTIONS = foreign subdir-objects no-dist - ACLOCAL_AMFLAGS = -I .. -I ../config - SUBDIRS = include testsuite - noinst_LTLIBRARIES = libgcjgc.la libgcjgc_convenience.la -@@ -672,182 +614,6 @@ - - distclean-tags: - -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags -- --distdir: $(DISTFILES) -- $(am__remove_distdir) -- test -d "$(distdir)" || mkdir "$(distdir)" -- @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \ -- topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \ -- list='$(DISTFILES)'; \ -- dist_files=`for file in $$list; do echo $$file; done | \ -- sed -e "s|^$$srcdirstrip/||;t" \ -- -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \ -- case $$dist_files in \ -- */*) $(MKDIR_P) `echo "$$dist_files" | \ -- sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \ -- sort -u` ;; \ -- esac; \ -- for file in $$dist_files; do \ -- if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \ -- if test -d $$d/$$file; then \ -- dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \ -- if test -d "$(distdir)/$$file"; then \ -- find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \ -- fi; \ -- if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \ -- cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \ -- find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \ -- fi; \ -- cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \ -- else \ -- test -f "$(distdir)/$$file" \ -- || cp -p $$d/$$file "$(distdir)/$$file" \ -- || exit 1; \ -- fi; \ -- done -- @list='$(DIST_SUBDIRS)'; for subdir in $$list; do \ -- if test "$$subdir" = .; then :; else \ -- test -d "$(distdir)/$$subdir" \ -- || $(MKDIR_P) "$(distdir)/$$subdir" \ -- || exit 1; \ -- fi; \ -- done -- @list='$(DIST_SUBDIRS)'; for subdir in $$list; do \ -- if test "$$subdir" = .; then :; else \ -- dir1=$$subdir; dir2="$(distdir)/$$subdir"; \ -- $(am__relativize); \ -- new_distdir=$$reldir; \ -- dir1=$$subdir; dir2="$(top_distdir)"; \ -- $(am__relativize); \ -- new_top_distdir=$$reldir; \ -- echo " (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) top_distdir="$$new_top_distdir" distdir="$$new_distdir" \\"; \ -- echo " am__remove_distdir=: am__skip_length_check=: am__skip_mode_fix=: distdir)"; \ -- ($(am__cd) $$subdir && \ -- $(MAKE) $(AM_MAKEFLAGS) \ -- top_distdir="$$new_top_distdir" \ -- distdir="$$new_distdir" \ -- am__remove_distdir=: \ -- am__skip_length_check=: \ -- am__skip_mode_fix=: \ -- distdir) \ -- || exit 1; \ -- fi; \ -- done -- -test -n "$(am__skip_mode_fix)" \ -- || find "$(distdir)" -type d ! -perm -755 \ -- -exec chmod u+rwx,go+rx {} \; -o \ -- ! -type d ! -perm -444 -links 1 -exec chmod a+r {} \; -o \ -- ! -type d ! -perm -400 -exec chmod a+r {} \; -o \ -- ! -type d ! -perm -444 -exec $(install_sh) -c -m a+r {} {} \; \ -- || chmod -R a+r "$(distdir)" --dist-gzip: distdir -- tardir=$(distdir) && $(am__tar) | GZIP=$(GZIP_ENV) gzip -c >$(distdir).tar.gz -- $(am__remove_distdir) -- --dist-bzip2: distdir -- tardir=$(distdir) && $(am__tar) | bzip2 -9 -c >$(distdir).tar.bz2 -- $(am__remove_distdir) -- --dist-lzma: distdir -- tardir=$(distdir) && $(am__tar) | lzma -9 -c >$(distdir).tar.lzma -- $(am__remove_distdir) -- --dist-xz: distdir -- tardir=$(distdir) && $(am__tar) | xz -c >$(distdir).tar.xz -- $(am__remove_distdir) -- --dist-tarZ: distdir -- tardir=$(distdir) && $(am__tar) | compress -c >$(distdir).tar.Z -- $(am__remove_distdir) -- --dist-shar: distdir -- shar $(distdir) | GZIP=$(GZIP_ENV) gzip -c >$(distdir).shar.gz -- $(am__remove_distdir) -- --dist-zip: distdir -- -rm -f $(distdir).zip -- zip -rq $(distdir).zip $(distdir) -- $(am__remove_distdir) -- --dist dist-all: distdir -- tardir=$(distdir) && $(am__tar) | GZIP=$(GZIP_ENV) gzip -c >$(distdir).tar.gz -- $(am__remove_distdir) -- --# This target untars the dist file and tries a VPATH configuration. Then --# it guarantees that the distribution is self-contained by making another --# tarfile. --distcheck: dist -- case '$(DIST_ARCHIVES)' in \ -- *.tar.gz*) \ -- GZIP=$(GZIP_ENV) gzip -dc $(distdir).tar.gz | $(am__untar) ;;\ -- *.tar.bz2*) \ -- bzip2 -dc $(distdir).tar.bz2 | $(am__untar) ;;\ -- *.tar.lzma*) \ -- lzma -dc $(distdir).tar.lzma | $(am__untar) ;;\ -- *.tar.xz*) \ -- xz -dc $(distdir).tar.xz | $(am__untar) ;;\ -- *.tar.Z*) \ -- uncompress -c $(distdir).tar.Z | $(am__untar) ;;\ -- *.shar.gz*) \ -- GZIP=$(GZIP_ENV) gzip -dc $(distdir).shar.gz | unshar ;;\ -- *.zip*) \ -- unzip $(distdir).zip ;;\ -- esac -- chmod -R a-w $(distdir); chmod a+w $(distdir) -- mkdir $(distdir)/_build -- mkdir $(distdir)/_inst -- chmod a-w $(distdir) -- test -d $(distdir)/_build || exit 0; \ -- dc_install_base=`$(am__cd) $(distdir)/_inst && pwd | sed -e 's,^[^:\\/]:[\\/],/,'` \ -- && dc_destdir="$${TMPDIR-/tmp}/am-dc-$$$$/" \ -- && am__cwd=`pwd` \ -- && $(am__cd) $(distdir)/_build \ -- && ../configure --srcdir=.. --prefix="$$dc_install_base" \ -- $(DISTCHECK_CONFIGURE_FLAGS) \ -- && $(MAKE) $(AM_MAKEFLAGS) \ -- && $(MAKE) $(AM_MAKEFLAGS) dvi \ -- && $(MAKE) $(AM_MAKEFLAGS) check \ -- && $(MAKE) $(AM_MAKEFLAGS) install \ -- && $(MAKE) $(AM_MAKEFLAGS) installcheck \ -- && $(MAKE) $(AM_MAKEFLAGS) uninstall \ -- && $(MAKE) $(AM_MAKEFLAGS) distuninstallcheck_dir="$$dc_install_base" \ -- distuninstallcheck \ -- && chmod -R a-w "$$dc_install_base" \ -- && ({ \ -- (cd ../.. && umask 077 && mkdir "$$dc_destdir") \ -- && $(MAKE) $(AM_MAKEFLAGS) DESTDIR="$$dc_destdir" install \ -- && $(MAKE) $(AM_MAKEFLAGS) DESTDIR="$$dc_destdir" uninstall \ -- && $(MAKE) $(AM_MAKEFLAGS) DESTDIR="$$dc_destdir" \ -- distuninstallcheck_dir="$$dc_destdir" distuninstallcheck; \ -- } || { rm -rf "$$dc_destdir"; exit 1; }) \ -- && rm -rf "$$dc_destdir" \ -- && $(MAKE) $(AM_MAKEFLAGS) dist \ -- && rm -rf $(DIST_ARCHIVES) \ -- && $(MAKE) $(AM_MAKEFLAGS) distcleancheck \ -- && cd "$$am__cwd" \ -- || exit 1 -- $(am__remove_distdir) -- @(echo "$(distdir) archives ready for distribution: "; \ -- list='$(DIST_ARCHIVES)'; for i in $$list; do echo $$i; done) | \ -- sed -e 1h -e 1s/./=/g -e 1p -e 1x -e '$$p' -e '$$x' --distuninstallcheck: -- @$(am__cd) '$(distuninstallcheck_dir)' \ -- && test `$(distuninstallcheck_listfiles) | wc -l` -le 1 \ -- || { echo "ERROR: files left after uninstall:" ; \ -- if test -n "$(DESTDIR)"; then \ -- echo " (check DESTDIR support)"; \ -- fi ; \ -- $(distuninstallcheck_listfiles) ; \ -- exit 1; } >&2 --distcleancheck: distclean -- @if test '$(srcdir)' = . ; then \ -- echo "ERROR: distcleancheck can only run from a VPATH build" ; \ -- exit 1 ; \ -- fi -- @test `$(distcleancheck_listfiles) | wc -l` -eq 0 \ -- || { echo "ERROR: files left in build directory after distclean:" ; \ -- $(distcleancheck_listfiles) ; \ -- exit 1; } >&2 - check-am: all-am - check: check-recursive - all-am: Makefile $(LTLIBRARIES) all-multi -@@ -960,21 +726,19 @@ - .PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \ - all all-am all-multi am--refresh check check-am clean \ - clean-generic clean-libtool clean-multi \ -- clean-noinstLTLIBRARIES ctags ctags-recursive dist dist-all \ -- dist-bzip2 dist-gzip dist-lzma dist-shar dist-tarZ dist-xz \ -- dist-zip distcheck distclean distclean-compile \ -- distclean-generic distclean-libtool distclean-multi \ -- distclean-tags distcleancheck distdir distuninstallcheck dvi \ -- dvi-am html html-am info info-am install install-am \ -- install-data install-data-am install-dvi install-dvi-am \ -- install-exec install-exec-am install-html install-html-am \ -- install-info install-info-am install-man install-multi \ -- install-pdf install-pdf-am install-ps install-ps-am \ -- install-strip installcheck installcheck-am installdirs \ -- installdirs-am maintainer-clean maintainer-clean-generic \ -- maintainer-clean-multi mostlyclean mostlyclean-compile \ -- mostlyclean-generic mostlyclean-libtool mostlyclean-multi pdf \ -- pdf-am ps ps-am tags tags-recursive uninstall uninstall-am -+ clean-noinstLTLIBRARIES ctags ctags-recursive distclean \ -+ distclean-compile distclean-generic distclean-libtool \ -+ distclean-multi distclean-tags dvi dvi-am html html-am info \ -+ info-am install install-am install-data install-data-am \ -+ install-dvi install-dvi-am install-exec install-exec-am \ -+ install-html install-html-am install-info install-info-am \ -+ install-man install-multi install-pdf install-pdf-am \ -+ install-ps install-ps-am install-strip installcheck \ -+ installcheck-am installdirs installdirs-am maintainer-clean \ -+ maintainer-clean-generic maintainer-clean-multi mostlyclean \ -+ mostlyclean-compile mostlyclean-generic mostlyclean-libtool \ -+ mostlyclean-multi pdf pdf-am ps ps-am tags tags-recursive \ -+ uninstall uninstall-am - - override CFLAGS := $(filter-out $(O0_CFLAGS), $(CFLAGS)) $(O0_CFLAGS) - ---- a/src/boehm-gc/testsuite/Makefile.in -+++ b/src/boehm-gc/testsuite/Makefile.in -@@ -35,7 +35,7 @@ - host_triplet = @host@ - target_triplet = @target@ - subdir = testsuite --DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in -+DIST_COMMON = $(srcdir)/Makefile.in $(srcdir)/Makefile.am - ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 - am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \ - $(top_srcdir)/../config/depstand.m4 \ -@@ -53,10 +53,8 @@ - CONFIG_CLEAN_FILES = - CONFIG_CLEAN_VPATH_FILES = - SOURCES = --DIST_SOURCES = - RUNTESTDEFAULTFLAGS = --tool $$tool --srcdir $$srcdir - RUNTEST = runtest --DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) - ACLOCAL = @ACLOCAL@ - AMTAR = @AMTAR@ - AM_CPPFLAGS = @AM_CPPFLAGS@ -@@ -267,37 +265,6 @@ - -l='$(DEJATOOL)'; for tool in $$l; do \ - rm -f $$tool.sum $$tool.log; \ - done -- --distdir: $(DISTFILES) -- @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \ -- topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \ -- list='$(DISTFILES)'; \ -- dist_files=`for file in $$list; do echo $$file; done | \ -- sed -e "s|^$$srcdirstrip/||;t" \ -- -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \ -- case $$dist_files in \ -- */*) $(MKDIR_P) `echo "$$dist_files" | \ -- sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \ -- sort -u` ;; \ -- esac; \ -- for file in $$dist_files; do \ -- if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \ -- if test -d $$d/$$file; then \ -- dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \ -- if test -d "$(distdir)/$$file"; then \ -- find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \ -- fi; \ -- if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \ -- cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \ -- find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \ -- fi; \ -- cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \ -- else \ -- test -f "$(distdir)/$$file" \ -- || cp -p $$d/$$file "$(distdir)/$$file" \ -- || exit 1; \ -- fi; \ -- done - check-am: all-am - $(MAKE) $(AM_MAKEFLAGS) check-DEJAGNU - check: check-am -@@ -399,8 +366,8 @@ - - .PHONY: all all-am check check-DEJAGNU check-am clean clean-generic \ - clean-libtool distclean distclean-DEJAGNU distclean-generic \ -- distclean-libtool distdir dvi dvi-am html html-am info info-am \ -- install install-am install-data install-data-am install-dvi \ -+ distclean-libtool dvi dvi-am html html-am info info-am install \ -+ install-am install-data install-data-am install-dvi \ - install-dvi-am install-exec install-exec-am install-html \ - install-html-am install-info install-info-am install-man \ - install-pdf install-pdf-am install-ps install-ps-am \ --- a/src/ChangeLog.linaro +++ b/src/ChangeLog.linaro -@@ -0,0 +1,1037 @@ +@@ -0,0 +1,2490 @@ ++2013-04-08 Yvan Roux ++ ++ gcc/ ++ * LINARO-VERSION: Bump version. ++ ++2013-04-08 Yvan Roux ++ ++ GCC Linaro 4.7-2013.04 released. ++ ++ gcc/ ++ * LINARO-VERSION: Update. ++ ++2013-04-08 Matthew Gretton-Dann ++ ++ Merge from FSF arm/aarch64-4.7-branch r196346..r196381. ++ ++ Backport /work/sources/gcc-bzr/arm-aarch64-4.7 r196346: ++ [AArch64/AArch64-4.7] Fix warning - aarch64_simd_make_constant has no prototype. ++ ++ gcc/ ++ * config/aarch64/aarch64.c ++ (aarch64_simd_make_constant): Make static. ++ ++ Backport /work/sources/gcc-bzr/arm-aarch64-4.7 r196348: ++ [AArch64/AArch64-4.7] Fix warning - No previous prototype for aarch64_init_simd_builtins. ++ ++ gcc/ ++ * config/aarch64/aarch64-builtins.c ++ (aarch64_init_simd_builtins): Make static. ++ ++ Backport /work/sources/gcc-bzr/arm-aarch64-4.7 r196351: ++ [AArch64/AArch64-4.7] Fix warning - aarch64_mangle_type has no prototype. ++ ++ gcc/ ++ * config/aarch64/aarch64.c (aarch64_mangle_type): Make static. ++ ++ Backport /work/sources/gcc-bzr/arm-aarch64-4.7 r196353: ++ [AArch64/AArch64-4.7] Fix warning - Unused variable in aarch64_float_const_representable. ++ ++ gcc/ ++ * config/aarch64/aarch64.c ++ (aarch64_float_const_representable): Remove unused variable. ++ ++ Backport /work/sources/gcc-bzr/arm-aarch64-4.7 r196375: ++ [AArch64-4.7] Fix warning: TARGET_FIXED_CONDITION_CODE_REGS redefined. ++ ++ gcc/ ++ * config/aarch64/aarch64.c: ++ Fix typo in `#undef TARGET_FIXED_CONDITION_CODE_REGS' ++ ++ Backport /work/sources/gcc-bzr/arm-aarch64-4.7 r196381: ++ [AArch64/AArch64-4.7][libgcc] Silence warnings in sync-cache.c ++ ++ libgcc/ ++ * config/aarch64/sync-cache.c ++ (__aarch64_sync_cache_range): Silence warnings. ++ ++2013-04-08 Matthew Gretton-Dann ++ ++ Merge from FSF GCC 4.7.3 (svn branches/gcc-4_7-branch 197188). ++ ++2013-04-03 Christophe Lyon ++ ++ Partial backport from mainline r195977: ++ 2013-02-12 Christophe Lyon ++ ++ * config/arm/arm-protos.h (struct cpu_vec_costs): New struct type. ++ (struct tune_params): Add vec_costs field. ++ * config/arm/arm.c (arm_builtin_vectorization_cost): New function. ++ (TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST): Define. ++ (arm_default_vec_cost): New struct of type cpu_vec_costs. ++ (arm_slowmul_tune, arm_fastmul_tune, arm_strongarm_tune) ++ (arm_xscale_tune, arm_9e_tune, arm_v6t2_tune, arm_cortex_tune) ++ (arm_cortex_a15_tune, arm_cortex_a5_tune, arm_cortex_a9_tune) ++ (arm_v6m_tune, arm_fa726te_tune): Define new vec_costs field. ++ ++2013-04-02 Christophe Lyon ++ ++ Backport from mainline r196876: ++ 2013-02-12 Christophe Lyon ++ ++ gcc/ ++ * config/arm/arm-protos.h (tune_params): Add ++ prefer_neon_for_64bits field. ++ * config/arm/arm.c (prefer_neon_for_64bits): New variable. ++ (arm_slowmul_tune): Default prefer_neon_for_64bits to false. ++ (arm_fastmul_tune, arm_strongarm_tune, arm_xscale_tune): Ditto. ++ (arm_9e_tune, arm_v6t2_tune, arm_cortex_tune): Ditto. ++ (arm_cortex_a5_tune, arm_cortex_a15_tune): Ditto. ++ (arm_cortex_a9_tune, arm_fa726te_tune): Ditto. ++ (arm_option_override): Handle -mneon-for-64bits new option. ++ * config/arm/arm.h (TARGET_PREFER_NEON_64BITS): New macro. ++ (prefer_neon_for_64bits): Declare new variable. ++ * config/arm/arm.md (arch): Rename neon_onlya8 and neon_nota8 to ++ avoid_neon_for_64bits and neon_for_64bits. Remove onlya8 and ++ nota8. ++ (arch_enabled): Handle new arch types. Remove support for onlya8 ++ and nota8. ++ (one_cmpldi2): Use new arch names. ++ * config/arm/arm.opt (mneon-for-64bits): Add option. ++ * config/arm/neon.md (adddi3_neon, subdi3_neon, iordi3_neon) ++ (anddi3_neon, xordi3_neon, ashldi3_neon, di3_neon): Use ++ neon_for_64bits instead of nota8 and avoid_neon_for_64bits instead ++ of onlya8. ++ * doc/invoke.texi (-mneon-for-64bits): Document. ++ ++ gcc/testsuite/ ++ * gcc.target/arm/neon-for-64bits-1.c: New tests. ++ * gcc.target/arm/neon-for-64bits-2.c: Likewise. ++ ++2013-03-11 Matthew Gretton-Dann ++ ++ gcc/ ++ * LINARO-VERSION: Bump version. ++ ++2013-03-11 Matthew Gretton-Dann ++ ++ GCC Linaro 4.7-2013.03 released. ++ ++ gcc/ ++ * LINARO-VERSION: Update. ++ ++2013-03-06 Venkataramanan Kumar ++ ++ 2013-03-05 Jakub Jelinek ++ ++ PR rtl-optimization/56484 ++ * ifcvt.c (noce_process_if_block): If else_bb is NULL, avoid extending ++ lifetimes of hard registers on small register class machines. ++ ++ * gcc.c-torture/compile/pr56484.c: New test. ++ ++2013-02-26 Matthew Gretton-Dann ++ ++ Merge from FSF arm/aarch64-4.7-branch r196014..r196225. ++ ++ Backport /work/sources/gcc-bzr/arm-aarch64-4.7 r196014: ++ [AArch64-4.7] Backport: Implement section anchors ++ ++ gcc/ ++ * common/config/aarch64/aarch64-common.c ++ (aarch_option_optimization_table): New. ++ (TARGET_OPTION_OPTIMIZATION_TABLE): Define. ++ * gcc/config/aarch64/aarch64-elf.h (ASM_OUTPUT_DEF): New definition. ++ * gcc/config/aarch64/aarch64.c (TARGET_MIN_ANCHOR_OFFSET): Define. ++ (TARGET_MAX_ANCHOR_OFFSET): Likewise. ++ ++ Backport /work/sources/gcc-bzr/arm-aarch64-4.7 r196015: ++ [AArch64-4.7] Backport: Fix g++.dg/abi/aarch64_guard1.C ++ ++ gcc/testsuite/ ++ * g++.dg/abi/aarch64_guard1.C: Add -fno-section-anchors. ++ ++ Backport /work/sources/gcc-bzr/arm-aarch64-4.7 r196225: ++ Subject: [AArch64] Add missing copyright and build dependency for aarch64-simd-builtins.def ++ ++ gcc/ ++ * config/aarch64/aarch64-simd-builtins.def: Add copyright header. ++ * config/aarch64/t-aarch64 ++ (aarch64-builtins.o): Depend on aarch64-simd-builtins.def. ++ ++2013-02-26 Matthew Gretton-Dann ++ ++ Merge from FSF GCC 4.7.3 (svn branches/gcc-4_7-branch 196272). ++ ++2013-02-18 Yvan Roux ++ ++ gcc/ ++ * LINARO-VERSION: Bump version. ++ ++2013-02-18 Yvan Roux ++ ++ GCC Linaro 4.7-2013.02-01 released. ++ ++ gcc/ ++ * LINARO-VERSION: Update. ++ ++2013-02-14 Yvan Roux ++ Matthias Klose ++ ++ gcc/ ++ * config/i386/t-linux64: Fix multiarch merge issues. ++ * config/i386/t-kfreebsd: Likewise. ++ ++2013-02-11 Christophe Lyon ++ ++ gcc/ ++ * LINARO-VERSION: Bump version. ++ ++2013-02-11 Christophe Lyon ++ ++ GCC Linaro 4.7-2013.02 released. ++ ++ gcc/ ++ * LINARO-VERSION: Update. ++ ++2013-02-10 Yvan Roux ++ Matthias Klose ++ ++ * Makefile.in (s-mlib): Fix revno 115051 merge issues. ++ * configure.ac: Likewise. ++ * configure: Regenerate. ++ ++2013-02-09 Yvan Roux ++ ++ Merge from FSF arm/aarch64-4.7-branch r194976..r195716. ++ ++ Backport arm-aarch64-4.7 r194976: ++ 2013-01-07 Tejas Belagod ++ ++ * config/aarch64/arm_neon.h (vmovn_high_is16, vmovn_high_s32, ++ vmovn_high_s64, vmovn_high_u16, vmovn_high_u32, vmovn_high_u64, ++ vqmovn_high_s16, vqmovn_high_s32, vqmovn_high_s64, vqmovn_high_u16, ++ vqmovn_high_u32, vqmovn_high_u64, vqmovun_high_s16, vqmovun_high_s32, ++ vqmovun_high_s64): Fix source operand number and update copyright. ++ ++ Backport arm-aarch64-4.7 r195010: ++ [AARCH64-4.7] Backport: Add support for vector and scalar floating-point immediate loads. ++ ++ gcc/ ++ * config/aarch64/aarch64-protos.h ++ (aarch64_const_double_zero_rtx_p): Rename to... ++ (aarch64_float_const_zero_rtx_p): ...this. ++ (aarch64_float_const_representable_p): New. ++ (aarch64_output_simd_mov_immediate): Likewise. ++ * config/aarch64/aarch64-simd.md (*aarch64_simd_mov): Refactor ++ move immediate case. ++ * config/aarch64/aarch64.c ++ (aarch64_const_double_zero_rtx_p): Rename to... ++ (aarch64_float_const_zero_rtx_p): ...this. ++ (aarch64_print_operand): Allow printing of new constants. ++ (aarch64_valid_floating_const): New. ++ (aarch64_legitimate_constant_p): Check for valid floating-point ++ constants. ++ (aarch64_simd_valid_immediate): Likewise. ++ (aarch64_vect_float_const_representable_p): New. ++ (aarch64_float_const_representable_p): Likewise. ++ (aarch64_simd_imm_zero_p): Also allow for floating-point 0.0. ++ (aarch64_output_simd_mov_immediate): New. ++ * config/aarch64/aarch64.md (*movsf_aarch64): Add new alternative. ++ (*movdf_aarch64): Likewise. ++ * config/aarch64/constraints.md (Ufc): New. ++ (Y): call aarch64_float_const_zero_rtx. ++ * config/aarch64/predicates.md (aarch64_fp_compare_operand): New. ++ ++ gcc/testsuite/ ++ * gcc.target/aarch64/fmovd.c: New. ++ * gcc.target/aarch64/fmovf.c: Likewise. ++ * gcc.target/aarch64/fmovd-zero.c: Likewise. ++ * gcc.target/aarch64/fmovf-zero.c: Likewise. ++ * gcc.target/aarch64/vect-fmovd.c: Likewise. ++ * gcc.target/aarch64/vect-fmovf.c: Likewise. ++ * gcc.target/aarch64/vect-fmovd-zero.c: Likewise. ++ * gcc.target/aarch64/vect-fmovf-zero.c: Likewise. ++ ++ Backport arm-aarch64-4.7 r195011: ++ [AARCH64-4.7] Backport: Make argument of ld1 intrinsics const. ++ ++ gcc/ ++ 2013-01-08 James Greenhalgh ++ ++ Backport from mainline. ++ 2013-01-07 James Greenhalgh ++ ++ * config/aarch64/arm_neon.h (vld1_dup_*): Make argument const. ++ (vld1q_dup_*): Likewise. ++ (vld1_*): Likewise. ++ (vld1q_*): Likewise. ++ (vld1_lane_*): Likewise. ++ (vld1q_lane_*): Likewise. ++ ++ Backport arm-aarch64-4.7 r195021: ++ 2013-01-08 Tejas Belagod ++ ++ * config/aarch64/aarch64-simd.md (aarch64_simd_vec_mult_lo_, ++ aarch64_simd_vec_mult_hi_): Separate instruction and operand ++ with tab instead of space. ++ ++ Backport arm-aarch64-4.7 r195022: ++ 2013-01-08 Tejas Belagod ++ ++ * gcc.target/aarch64/vect-mull-compile.c: Explicitly scan for ++ instructions generated instead of number of occurances. ++ ++ Backport arm-aarch64-4.7 r195026: ++ 2013-01-08 Tejas Belagod ++ ++ * config/aarch64/aarch64-simd.md (vec_init): New. ++ * config/aarch64/aarch64-protos.h (aarch64_expand_vector_init): Declare. ++ * config/aarch64/aarch64.c (aarch64_simd_dup_constant, ++ aarch64_simd_make_constant, aarch64_expand_vector_init): New. ++ ++ Backport arm-aarch64-4.7 r195079: ++ * config/aarch64/aarch64.c (aarch64_print_operand): Replace %r ++ in asm_fprintf with reg_names. ++ (aarch64_print_operand_address): Likewise. ++ (aarch64_return_addr): Likewise. ++ * config/aarch64/aarch64.h (ASM_FPRINTF_EXTENSIONS): Remove. ++ ++ Backport arm-aarch64-4.7 r195090: ++ [AARCH64-4.7] Backport: Fix support for vectorization over sqrt (), sqrtf (). ++ ++ gcc/ ++ * config/aarch64/aarch64-builtins.c ++ (aarch64_builtin_vectorized_function): Handle sqrt, sqrtf. ++ ++ gcc/testsuite/ ++ * gcc.target/aarch64/vsqrt.c (test_square_root_v2sf): Use ++ endian-safe float pool loading. ++ (test_square_root_v4sf): Likewise. ++ (test_square_root_v2df): Likewise. ++ * lib/target-supports.exp ++ (check_effective_target_vect_call_sqrtf): Add AArch64. ++ ++ Backport arm-aarch64-4.7 r195157: ++ 2013-01-14 Tejas Belagod ++ ++ gcc/ ++ * config/aarch64/aarch64-simd.md (*aarch64_simd_ld1r): New. ++ * config/aarch64/iterators.md (VALLDI): New. ++ ++ testsuite/ ++ * gcc.target/aarch64/aarch64/vect-ld1r-compile-fp.c: New. ++ * gcc.target/aarch64/vect-ld1r-compile.c: New. ++ * gcc.target/aarch64/vect-ld1r-fp.c: New. ++ * gcc.target/aarch64/vect-ld1r.c: New. ++ * gcc.target/aarch64/vect-ld1r.x: New. ++ ++ Backport arm-aarch64-4.7 r195206: ++ [AARCH64] Fix __clear_cache. ++ ++ Backport arm-aarch64-4.7 r195267: ++ 2013-01-17 Yufeng Zhang ++ ++ * config/aarch64/sync-cache.c (__aarch64_sync_cache_range): Cast the ++ results of (dcache_lsize - 1) and (icache_lsize - 1) to the type ++ __UINTPTR_TYPE__; also cast 'base' to the same type before the ++ alignment operation. ++ ++ Backport arm-aarch64-4.7 r195269: ++ Moved change logs of backported changes to ChangeLog.aarch64 in libgcc. ++ ++ Backport arm-aarch64-4.7 r195294: ++ 2013-01-18 Tejas Belagod ++ ++ gcc/ ++ * config/aarch64/arm_neon.h: Map scalar types to standard types. ++ ++ Backport arm-aarch64-4.7 r195298: ++ [AArch64-4.7] Backport: Add support for floating-point vcond. ++ ++ gcc/ ++ * config/aarch64/aarch64-simd.md ++ (aarch64_simd_bsl_internal): Add floating-point modes. ++ (aarch64_simd_bsl): Likewise. ++ (aarch64_vcond_internal): Likewise. ++ (vcond): Likewise. ++ (aarch64_cm): Fix constraints, add new modes. ++ * config/aarch64/iterators.md (V_cmp_result): Add V2DF. ++ gcc/testsuite/ ++ * gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c: New. ++ * gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-f.c: Likewise. ++ * gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-d.c: Likewise. ++ * gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-f.c: Likewise. ++ * gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-d.c: Likewise. ++ * gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-f.c: Likewise. ++ * gcc/testsuite/gcc.target/aarch64/vect-fcm.x: Likewise. ++ * gcc/testsuite/lib/target-supports.exp ++ (check_effective_target_vect_cond): Enable for AArch64. ++ ++ Backport arm-aarch64-4.7 r195300: ++ [AArch64-4.7] Backport: Fix unordered comparisons to floating-point vcond. ++ ++ gcc/ ++ * config/aarch64/aarch64-simd.md ++ (aarch64_vcond_internal): Handle unordered cases. ++ * config/aarch64/iterators.md (v_cmp_result): New. ++ gcc/testsuite/ ++ * gcc.target/aarch64/vect-fcm-gt-f.c: Change expected output. ++ * gcc.target/aarch64/vect-fcm-gt-d.c: Likewise. ++ * gcc.target/aarch64/vect-fcm-ge-f.c: Likewise. ++ * gcc.target/aarch64/vect-fcm-ge-d.c: Likewise. ++ * gcc.target/aarch64/vect-fcm-eq-f.c: Likewise. ++ ++ Backport arm-aarch64-4.7 r195466: ++ 2013-01-25 Tejas Belagod ++ ++ * config/aarch64/aarch64-simd-builtins.def: Separate sqdmulh_lane ++ entries into lane and laneq entries. ++ * config/aarch64/aarch64-simd.md (aarch64_sqdmulh_lane): Remove ++ AdvSIMD scalar modes. ++ (aarch64_sqdmulh_laneq): New. ++ (aarch64_sqdmulh_lane): New RTL pattern for Scalar AdvSIMD ++ modes. ++ * config/aarch64/arm_neon.h: Fix all the vqdmulh_lane* intrinsics' ++ builtin implementations to relfect changes in RTL in aarch64-simd.md. ++ * config/aarch64/iterators.md (VCOND): New. ++ (VCONQ): New. ++ ++ Backport arm-aarch64-4.7 r195670: ++ Back port from mainline implementaion of target hook TARGET_FIXED_CONDITION_CODE_REGS to optimize cmp for some cases ++ ++ Backport arm-aarch64-4.7 r195671: ++ Added test case that tests the implementation of TARGET_FIXED_CONDITION_CODE_REGS ++ ++ Backport arm-aarch64-4.7 r195710: ++ [AARCH64-4.7] Fix warning - Initialise generic_tunings. ++ ++ gcc/ ++ * config/aarch64/aarch64.c (generic_tunings): Initialise. ++ ++ Backport arm-aarch64-4.7 r195711: ++ [AARCH64-4.7] Fix warning - aarch64_add_constant mixed code and declarations. ++ ++ gcc/ ++ * config/aarch64/aarch64.c ++ (aarch64_add_constant): Move declaration of 'shift' above code. ++ ++ Backport arm-aarch64-4.7 r195712: ++ [AARCH64-4.7] Fix warning - aarch64_legitimize_reload_address passes the ++ wrong type to push_reload. ++ ++ gcc/ ++ * config/aarch64/aarch64.c ++ (aarch64_legitimize_reload_address): Cast 'type' before ++ passing to push_reload. ++ ++ Backport arm-aarch64-4.7 r195714: ++ [AARCH64-4.7] Fix warning - aarch64_trampoline_init passes the wrong type to emit_library_call. ++ ++ gcc/ ++ * config/aarch64/aarch64.c ++ (aarch64_trampoline_init): Pass 'LCT_NORMAL' rather than '0' ++ to emit_library_call. ++ ++ Backport arm-aarch64-4.7 r195715: ++ [AARCH64-4.7] Fix warning - Mixed code and declarations in aarch64_simd_const_bounds. ++ ++ gcc/ ++ * config/aarch64/aarch64.c ++ (aarch64_simd_const_bounds): Move declaration of 'lane' above code. ++ ++ Backport arm-aarch64-4.7 r195716: ++ [AARCH64-4.7] Backport: Fix warning in aarch64.md ++ ++ gcc/ ++ * config/aarch64/aarch64.md (insv_imm): Add modes ++ for source operands. ++ ++2013-02-05 Yvan Roux ++ ++ Merge from FSF GCC 4.7.3 (svn branches/gcc-4_7-branch 195745). ++ ++2013-02-05 Yvan Roux ++ ++ Backport from mainline r193508 ++ ++ 2012-11-14 Matthias Klose ++ ++ * doc/invoke.texi: Document -print-multiarch. ++ * doc/install.texi: Document --enable-multiarch. ++ * doc/fragments.texi: Document MULTILIB_OSDIRNAMES, MULTIARCH_DIRNAME. ++ * configure.ac: Add --enable-multiarch option. ++ * configure: Regenerate. ++ * Makefile.in (s-mlib): Pass MULTIARCH_DIRNAME to genmultilib. ++ enable_multiarch, with_float: New macros. ++ if_multiarch: New macro, define in terms of enable_multiarch. ++ * genmultilib: Add new argument for the multiarch name. ++ * gcc.c (multiarch_dir): Define. ++ (for_each_path): Search for multiarch suffixes. ++ (driver_handle_option): Handle multiarch option. ++ (do_spec_1): Pass -imultiarch if defined. ++ (main): Print multiarch. ++ (set_multilib_dir): Separate multilib and multiarch names ++ from multilib_select. ++ (print_multilib_info): Ignore multiarch names in multilib_select. ++ * incpath.c (add_standard_paths): Search the multiarch include dirs. ++ * cppdefault.h (default_include): Document multiarch in multilib ++ member. ++ * cppdefault.c: [LOCAL_INCLUDE_DIR, STANDARD_INCLUDE_DIR] Add an ++ include directory for multiarch directories. ++ * common.opt: New options --print-multiarch and -imultilib. ++ * config.gcc (tmake_file): ++ Include i386/t-linux. ++ (tmake_file): ++ Include i386/t-kfreebsd. ++ (tmake_file): Include i386/t-gnu. ++ * config/i386/t-linux64: Add multiarch names in ++ MULTILIB_OSDIRNAMES, define MULTIARCH_DIRNAME. ++ * config/i386/t-gnu: New file. ++ * config/i386/t-kfreebsd: Likewise. ++ * config/i386/t-linux: Likewise. ++ ++2013-02-05 Kugan Vivekanandarajah ++ ++ Backport from mainline r195555: ++ 2013-01-29 Greta Yorsh ++ ++ * config/arm/cortex-a7.md (cortex_a7_neon, cortex_a7_all): Remove. ++ (cortex_a7_idiv): Use cortex_a7_both instead of cortex_a7_all. ++ ++ Backport from mainline r195554: ++ 2013-01-29 Greta Yorsh ++ ++ * config/arm/arm.c (cortexa7_younger): Return true for TYPE_CALL. ++ * config/arm/cortex-a7.md (cortex_a7_call): Update required units. ++ ++ Backport from mainline r195553: ++ 2013-01-29 Greta Yorsh ++ ++ * config/arm/arm-protos.h (arm_mac_accumulator_is_result): New ++ declaration. ++ * config/arm/arm.c (arm_mac_accumulator_is_result): New function. ++ * config/arm/cortex-a7.md: New bypasses using ++ arm_mac_accumulator_is_result. ++ ++ Backport from mainline r195552: ++ 2013-01-29 Greta Yorsh ++ ++ * config/arm/cortex-a7.md (cortex_a7_neon_mul): New reservation. ++ (cortex_a7_neon_mla): Likewise. ++ (cortex_a7_fpfmad): New reservation. ++ (cortex_a7_fpmacs): Use ffmas and update required units. ++ (cortex_a7_fpmuld): Update required units and latency. ++ (cortex_a7_fpmacd): Likewise. ++ (cortex_a7_fdivs, cortex_a7_fdivd): Likewise. ++ (cortex_a7_neon). Likewise. ++ (bypass) Update participating units. ++ ++ Backport from mainline r195551: ++ 2013-01-29 Greta Yorsh ++ ++ * config/arm/arm.md (type): Add ffmas and ffmad to "type" attribute. ++ * config/arm/vfp.md (fma,fmsub,fnmsub,fnmadd): Change type ++ from fmac to ffma. ++ * config/arm/vfp11.md (vfp_farith): Use ffmas. ++ (vfp_fmul): Use ffmad. ++ * config/arm/cortex-r4f.md (cortex_r4_fmacs): Use ffmas. ++ (cortex_r4_fmacd): Use ffmad. ++ * config/arm/cortex-m4-fpu.md (cortex_m4_fmacs): Use ffmas. ++ * config/arm/cortex-a9.md (cortex_a9_fmacs): Use ffmas. ++ (cortex_a9_fmacd): Use ffmad. ++ * config/arm/cortex-a8-neon.md (cortex_a8_vfp_macs): Use ffmas. ++ (cortex_a8_vfp_macd): Use ffmad. ++ * config/arm/cortex-a5.md (cortex_a5_fpmacs): Use ffmas. ++ (cortex_a5_fpmacd): Use ffmad. ++ * config/arm/cortex-a15-neon.md (cortex_a15_vfp_macs) Use ffmas. ++ (cortex_a15_vfp_macd): Use ffmad. ++ * config/arm/arm1020e.md (v10_fmul): Use ffmas and ffmad. ++ ++ Backport from mainline r194656: ++ 2012-12-21 Greta Yorsh ++ ++ * config/arm/cortex-a7.md: New file. ++ * config/arm/t-arm (MD_INCLUDES): Add cortex-a7.md. ++ * config/arm/arm.md: Include cortex-a7.md. ++ (generic_sched): Don't use generic scheduler for Cortex-A7. ++ (generic_vfp): Likewise. ++ * config/arm/arm.c: (TARGET_SCHED_REORDER): Use arm_sched_reorder. ++ (arm_sched_reorder,cortexa7_sched_reorder): New function. ++ (cortexa7_older_only,cortexa7_younger): Likewise. ++ (arm_issue_rate): Add Cortex-A7. ++ ++ ++ Backport from mainline r194557: ++ 2012-12-17 Greta Yorsh ++ ++ * config/arm/arm.md (type): Add "simple_alu_shift" to attribute "type". ++ (core_cycles): Update for simple_alu_shift. ++ (thumb1_zero_extendhisi2,arm_zero_extendhisi2_v6): Use simple_alu_shift ++ instead of a CPU-speicific condition for "type" attribute. ++ (thumb1_zero_extendqisi2_v6,arm_zero_extendqisi2_v6): Likewise. ++ (thumb1_extendhisi2,arm_extendhisi2_v6,arm_extendqisi_v6): Likewise. ++ (thumb1_extendqisi2): Likewise. ++ * config/arm/thumb2.md (thumb2_extendqisi_v6): Likewise. ++ (thumb2_zero_extendhisi2_v6,thumb2_zero_extendqisi2_v6) Likewise. ++ * config/arm/arm1020e.md (alu_shift_op): Use simple_alu_shift. ++ * config/arm/arm1026ejs.md (alu_shift_op): Likewise. ++ * config/arm/arm1136jfs.md (11_alu_shift_op): Likewise. ++ * config/arm/arm926ejs.md (9_alu_op): Likewise. ++ * config/arm/cortex-a15.md (cortex_a15_alu_shift): Likewise. ++ * config/arm/cortex-a5.md (cortex_a5_alu_shift): Likewise. ++ * config/arm/cortex-a8.md (cortex_a8_alu_shift,cortex_a8_mov): Likewise. ++ * config/arm/cortex-a9.md (cortex_a9_dp,cortex_a9_dp_shift): Likewise. ++ * config/arm/cortex-m4.md (cortex_m4_alu): Likewise. ++ * config/arm/cortex-r4.md (cortex_r4_alu_shift): Likewise. ++ * config/arm/fa526.md (526_alu_shift_op): Likewise. ++ * config/arm/fa606te.md (fa606te_core): Likewise. ++ * config/arm/fa626te.md (626te_alu_shift_op): Likewise. ++ * config/arm/fa726te.md (726te_alu_shift_op): Likewise. ++ * config/arm/fmp626.md (mp626_alu_shift_op): Likewise. ++ ++ ++ Backport from mainline r193996: ++ 2012-11-30 Ramana Radhakrishnan ++ Greta Yorsh ++ ++ * config/arm/arm.md (type): Subdivide "alu" into "alu_reg" ++ and "simple_alu_imm". ++ (core_cycles): Use new names. ++ (arm_addsi3): Set type of patterns to use to alu_reg and simple_alu_imm. ++ (addsi3_compare0, addsi3_compare0_scratch): Likewise. ++ (addsi3_compare_op1, addsi3_compare_op2, compare_addsi2_op0): Likewise. ++ (compare_addsi2_op1, arm_subsi3_insn, subsi3_compare0): Likewise. ++ (subsi3_compare, arm_decscc,arm_andsi3_insn): Likewise. ++ (thumb1_andsi3_insn, andsi3_compare0_scratch): Likewise. ++ (zeroextractsi_compare0_scratch,iorsi3_insn,iorsi3_compare0): Likewise. ++ (iorsi3_compare0_scratch, arm_xorsi3, thumb1_xorsi3_insn): Likewise. ++ (xorsi3_compare0, xorsi3_compare0_scratch): Likewise. ++ (thumb1_zero_extendhisi2,arm_zero_extendhisi2_v6): Likewise. ++ (thumb1_zero_extendqisi2_v, arm_zero_extendqisi2_v6): Likewise. ++ (thumb1_extendhisi2, arm_extendqisi_v6): Likewise. ++ (thumb1_extendqisi2, arm_movsi_insn): Likewise. ++ (movsi_compare0, movhi_insn_arch4, movhi_bytes): Likewise. ++ (arm_movqi_insn, thumb1_movqi_insn, arm_cmpsi_insn): Likewise. ++ (movsicc_insn, if_plus_move, if_move_plus): Likewise. ++ * config/arm/neon.md (neon_mov/VDX): Likewise. ++ (neon_mov/VQXMOV): Likewise. ++ * config/arm/arm1020e.md (1020alu_op): Likewise. ++ * config/arm/fmp626.md (mp626_alu_op): Likewise. ++ * config/arm/fa726te.md (726te_alu_op): Likewise. ++ * config/arm/fa626te.md (626te_alu_op): Likewise. ++ * config/arm/fa606te.md (606te_alu_op): Likewise. ++ * config/arm/fa526.md (526_alu_op): Likewise. ++ * config/arm/cortex-r4.md (cortex_r4_alu, cortex_r4_mov): Likewise. ++ * config/arm/cortex-m4.md (cortex_m4_alu): Likewise. ++ * config/arm/cortex-a9.md (cprtex_a9_dp): Likewise. ++ * config/arm/cortex-a8.md (cortex_a8_alu, cortex_a8_mov): Likewise. ++ * config/arm/cortex-a5.md (cortex_a5_alu): Likewise. ++ * config/arm/cortex-a15.md (cortex_a15_alu): Likewise. ++ * config/arm/arm926ejs.md (9_alu_op): Likewise. ++ * config/arm/arm1136jfs.md (11_alu_op): Likewise. ++ * config/arm/arm1026ejs.md (alu_op): Likewise. ++ ++2013-02-05 Kugan Vivekanandarajah ++ ++ Backport from mainline r194587: ++ 2012-12-18 Kyrylo Tkachov ++ ++ * config/arm/driver-arm.c (arm_cpu_table): ++ Add Cortex-A7. ++ ++2013-01-15 Matthew Gretton-Dann ++ ++ gcc/ ++ * LINARO-VERSION: Bump version. ++ ++2013-01-15 Matthew Gretton-Dann ++ ++ GCC Linaro 4.7-2013.01 released. ++ ++ gcc/ ++ * LINARO-VERSION: Update. ++ ++2013-01-10 Matthew Gretton-Dann ++ ++ Merge from FSF GCC 4.7.3 (svn branches/gcc-4_7-branch 194772). ++ ++2013-01-10 Matthew Gretton-Dann ++ ++ Merge from FSF arm/aarch64-4.7-branch r194220..r194808. ++ ++ Backport arm-aarch64-4.7 r194220: ++ gcc/ ++ ++ 2012-12-05 Yufeng Zhang ++ ++ * config/aarch64/aarch64.c (aarch64_mangle_type): New function. ++ (TARGET_MANGLE_TYPE): Define. ++ ++ gcc/testsuite/ ++ ++ 2012-12-05 Yufeng Zhang ++ ++ * g++.dg/abi/arm_va_list.C: Also test on aarch64*-*-*. ++ ++ Backport arm-aarch64-4.7 r194222: ++ [AARCH64-4.7] Backport vectorize standard math patterns. ++ ++ gcc/ ++ ++ * config/aarch64/aarch64-builtins.c ++ (aarch64_builtin_vectorized_function): New. ++ * config/aarch64/aarch64-protos.h ++ (aarch64_builtin_vectorized_function): Declare. ++ * config/aarch64/aarch64-simd-builtins.def (frintz, frintp): Add. ++ (frintm, frinti, frintx, frinta, fcvtzs, fcvtzu): Likewise. ++ (fcvtas, fcvtau, fcvtps, fcvtpu, fcvtms, fcvtmu): Likewise. ++ * config/aarch64/aarch64-simd.md ++ (aarch64_frint_): New. ++ (2): Likewise. ++ (aarch64_fcvt): Likewise. ++ (l2): Likewise. ++ * config/aarch64/aarch64.c (TARGET_VECTORIZE_BUILTINS): Define. ++ (TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Likewise. ++ * config/aarch64/aarch64.md ++ (btrunc2, ceil2, floor2) ++ (round2, rint2, nearbyint2): Consolidate as... ++ (2): ...this. ++ (lceil2, lfloor2) ++ (lround2) ++ (lrint2): Consolidate as... ++ (l2): ... this. ++ * config/aarch64/iterators.md (fcvt_target): New. ++ (FCVT_TARGET): Likewise. ++ (FRINT): Likewise. ++ (FCVT): Likewise. ++ (frint_pattern): Likewise. ++ (frint_suffix): Likewise. ++ (fcvt_pattern): Likewise. ++ ++ gcc/testsuite/ ++ ++ * gcc.dg/vect/vect-rounding-btrunc.c: New test. ++ * gcc.dg/vect/vect-rounding-btruncf.c: Likewise. ++ * gcc.dg/vect/vect-rounding-ceil.c: Likewise. ++ * gcc.dg/vect/vect-rounding-ceilf.c: Likewise. ++ * gcc.dg/vect/vect-rounding-floor.c: Likewise. ++ * gcc.dg/vect/vect-rounding-floorf.c: Likewise. ++ * gcc.dg/vect/vect-rounding-lceil.c: Likewise. ++ * gcc.dg/vect/vect-rounding-lfloor.c: Likewise. ++ * gcc.dg/vect/vect-rounding-nearbyint.c: Likewise. ++ * gcc.dg/vect/vect-rounding-nearbyintf.c: Likewise. ++ * gcc.dg/vect/vect-rounding-round.c: Likewise. ++ * gcc.dg/vect/vect-rounding-roundf.c: Likewise. ++ * target-supports.exp ++ (check_effective_target_vect_call_btrunc): New. ++ (check_effective_target_vect_call_btruncf): Likewise. ++ (check_effective_target_vect_call_ceil): Likewise. ++ (check_effective_target_vect_call_ceilf): Likewise. ++ (check_effective_target_vect_call_floor): Likewise. ++ (check_effective_target_vect_call_floorf): Likewise. ++ (check_effective_target_vect_call_lceil): Likewise. ++ (check_effective_target_vect_call_lfloor): Likewise. ++ (check_effective_target_vect_call_nearbyint): Likewise. ++ (check_effective_target_vect_call_nearbyintf): Likewise. ++ (check_effective_target_vect_call_round): Likewise. ++ (check_effective_target_vect_call_roundf): Likewise. ++ ++ Backport arm-aarch64-4.7 r194246: ++ gcc/ ++ ++ 2012-12-05 Yufeng Zhang ++ ++ * config/aarch64/aarch64.c (aarch64_simd_mangle_map_entry): New ++ typedef. ++ (aarch64_simd_mangle_map): New table. ++ (aarch64_mangle_type): Locate and return the mangled name for ++ a given AdvSIMD vector type. ++ ++ gcc/testsuite/ ++ ++ 2012-12-05 Yufeng Zhang ++ ++ * g++.dg/abi/mangle-neon-aarch64.C: New test. ++ ++ Backport arm-aarch64-4.7 r194259: ++ [AARCH64-4.7] Backport fix to slp-perm-8.c ++ ++ gcc/testsuite/ ++ ++ Backport from mainline. ++ 2012-05-31 Greta Yorsh ++ ++ * lib/target-supports.exp (check_effective_target_vect_char_mult): Add ++ arm32 to targets. ++ * gcc.dg/vect/slp-perm-8.c (main): Prevent vectorization ++ of the initialization loop. ++ (dg-final): Adjust the expected number of vectorized loops depending ++ on vect_char_mult target selector. ++ ++ Backport arm-aarch64-4.7 r194260: ++ [AARCH64] Implement Vector Permute Support. ++ ++ gcc/ ++ Backport from mainline. ++ 2012-12-05 James Greenhalgh ++ ++ * config/aarch64/aarch64-protos.h ++ (aarch64_split_combinev16qi): New. ++ (aarch64_expand_vec_perm): Likewise. ++ (aarch64_expand_vec_perm_const): Likewise. ++ * config/aarch64/aarch64-simd.md (vec_perm_const): New. ++ (vec_perm): Likewise. ++ (aarch64_tbl1): Likewise. ++ (aarch64_tbl2v16qi): Likewise. ++ (aarch64_combinev16qi): New. ++ * config/aarch64/aarch64.c ++ (aarch64_vectorize_vec_perm_const_ok): New. ++ (aarch64_split_combinev16qi): Likewise. ++ (MAX_VECT_LEN): Define. ++ (expand_vec_perm_d): New. ++ (aarch64_expand_vec_perm_1): Likewise. ++ (aarch64_expand_vec_perm): Likewise. ++ (aarch64_evpc_tbl): Likewise. ++ (aarch64_expand_vec_perm_const_1): Likewise. ++ (aarch64_expand_vec_perm_const): Likewise. ++ (aarch64_vectorize_vec_perm_const_ok): Likewise. ++ (TARGET_VECTORIZE_VEC_PERM_CONST_OK): Likewise. ++ * config/aarch64/iterators.md ++ (unspec): Add UNSPEC_TBL, UNSPEC_CONCAT. ++ (V_cmp_result): Add mapping for V2DF. ++ ++ gcc/testsuite/ ++ ++ Backport from mainline. ++ 2012-12-05 James Greenhalgh ++ ++ * lib/target-supports.exp ++ (check_effective_target_vect_perm): Allow aarch64*-*-*. ++ (check_effective_target_vect_perm_byte): Likewise. ++ (check_effective_target_vect_perm_short): Likewise. ++ (check_effective_target_vect_char_mult): Likewise. ++ (check_effective_target_vect_extract_even_odd): Likewise. ++ (check_effective_target_vect_interleave): Likewise. ++ ++ Backport arm-aarch64-4.7 r194261: ++ [AARCH64-4.7] Add zip{1, 2}, uzp{1, 2}, trn{1, 2} support for vector permute. ++ ++ gcc/ ++ Backport from mainline. ++ 2012-12-05 James Greenhalgh ++ ++ * config/aarch64/aarch64-simd-builtins.def: Add new builtins. ++ * config/aarch64/aarch64-simd.md (simd_type): Add uzp. ++ (aarch64_): New. ++ * config/aarch64/aarch64.c (aarch64_evpc_trn): New. ++ (aarch64_evpc_uzp): Likewise. ++ (aarch64_evpc_zip): Likewise. ++ (aarch64_expand_vec_perm_const_1): Check for trn, zip, uzp patterns. ++ * config/aarch64/iterators.md (unspec): Add neccessary unspecs. ++ (PERMUTE): New. ++ (perm_insn): Likewise. ++ (perm_hilo): Likewise. ++ ++ Backport arm-aarch64-4.7 r194553: ++ [AARCH64] Backport support for TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES. ++ ++ gcc/ ++ ++ * config/aarch64/aarch64.c ++ (aarch64_autovectorize_vector_sizes): New. ++ (TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES): Define. ++ ++ gcc/testsuite/ ++ ++ * lib/target-supports.exp ++ (check_effective_target_vect_multiple_sizes): Enable for AArch64. ++ ++ Backport arm-aarch64-4.7 r194673: ++ Make zero_extends explicit for common AArch64 SI mode patterns ++ ++ Backport arm-aarch64-4.7 r194808: ++ [AArch64] Backport: Fix some warnings about unused variables. ++ ++ gcc/ ++ * config/aarch64/aarch64.c (aarch64_simd_attr_length_move): ++ Remove unused variables. ++ (aarch64_split_compare_and_swap): Likewise. ++ ++2012-12-20 Brice Dobry ++ ++ Backport from mainline r191181 ++ ++ 2012-09-11 Tobias Burnus ++ ++ * doc/sourcebuild.texi (arm_neon_v2_ok): Fix @anchor. ++ ++2012-12-20 Brice Dobry ++ ++ Blueprints: backport-the-fma-intrinsic, fused-multiply-add-support ++ ++ Backport from mainline r192560 ++ ++ 2012-10-18 Matthew Gretton-Dann ++ Ramana Radhakrishnan ++ ++ * config/arm/arm.c (neon_builtin_data): Add vfma and vfms ++ builtins. ++ * config/arm/neon-docgen.ml (intrinsic_groups): Add ++ fused-multiply-* groups. ++ * config/neon-gen.ml (print_feature_test_start): New function. ++ (print_feature_test_end): Likewise. ++ (print_variant): Print feature test macros. ++ * config/arm/neon-testgen.ml (emit_prologue): Allow different ++ tests to require different effective targets. ++ (effective_target): New function. ++ (test_intrinsic): Specify correct effective targets. ++ * gcc/config/arm/neon.md (fma4_intrinsic): New pattern. ++ (fmsub4_intrinsic): Likewise. ++ (neon_vfma): New expand. ++ (neon_vfms): Likewise. ++ * config/neon.ml (opcode): Add Vfma and Vfms. ++ (features): Add Requires_feature. ++ (ops): Add VFMA and VFMS intrinsics. ++ * config/arm/arm_neon.h: Regenerate. ++ * doc/arm-neon-intrinsics.texi: Likewise. ++ ++ ++2012-12-20 Brice Dobry ++ ++ Blueprints: backport-the-fma-intrinsic, fused-multiply-add-support ++ ++ Backport from mainline r191180 ++ ++ 2012-09-11 Ramana Radhakrishnan ++ Matthew Gretton-Dann ++ ++ * config/arm/neon.md (fma4): New pattern. ++ (*fmsub4): Likewise. ++ * doc/sourcebuild.texi (arm_neon_v2_ok, arm_neon_v2_hw): Document it. ++ ++2012-12-20 Brice Dobry ++ ++ Blueprints: backport-the-fma-intrinsic, fused-multiply-add-support ++ ++ Backport from mainline r189283 ++ ++ 2012-07-05 Matthew Gretton-Dann ++ ++ * config/arm/iterators.md (SDF): New mode iterator. ++ (V_if_elem): Add support for SF and DF modes. ++ (V_reg): Likewise. ++ (F_constraint): New mode iterator attribute. ++ (F_fma_type): Likewise. ++ config/arm/vfp.md (fma4): New pattern. ++ (*fmsub4): Likewise. ++ (*fmnsub4): Likewise. ++ (*fmnadd4): Likewise. ++ ++2012-12-20 Brice Dobry ++ ++ Blueprints: backport-the-fma-intrinsic, fused-multiply-add-support ++ ++ Partial backport from mainline r188946 ++ ++ 2012-06-25 Matthew Gretton-Dann ++ James Greenhalgh ++ * config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Add new built-ins. ++ (TARGET_FMA): New macro. ++ ++2012-12-20 Ulrich Weigand ++ ++ Backport from mainline ++ ++ gcc/ ++ 2012-12-17 Andrew Stubbs ++ Ulrich Weigand ++ ++ * config/arm/arm.md (zero_extenddi2): Add extra alternatives ++ for NEON registers. ++ Add alternative for one-instruction extend-in-place. ++ (extenddi2): Likewise. ++ Add constraints for Thumb-mode memory loads. ++ Prevent extend splitters doing NEON alternatives. ++ * config/arm/iterators.md (qhs_extenddi_cstr, qhs_zextenddi_cstr): ++ Adjust constraints to add new alternatives. ++ * config/arm/neon.md: Add splitters for zero- and sign-extend. ++ ++ gcc/testsuite/ ++ 2012-12-17 Andrew Stubbs ++ Ulrich Weigand ++ ++ * gcc.target/arm/neon-extend-1.c: New file. ++ * gcc.target/arm/neon-extend-2.c: New file. ++ ++ gcc/testsuite/ ++ 2012-10-01 Ulrich Weigand ++ ++ * gcc.dg/lower-subreg-1.c: Disable on arm*-*-* targets. ++ ++ gcc/ ++ 2012-09-27 Ulrich Weigand ++ ++ * lower-subreg.c (enum classify_move_insn): Rename ++ SIMPLE_PSEUDO_REG_MOVE to DECOMPOSABLE_SIMPLE_MOVE. ++ (find_decomposable_subregs): Update. ++ (decompose_multiword_subregs): Add DECOMPOSE_COPIES parameter. ++ Only mark pseudo-to-pseudo copies as DECOMPOSABLE_SIMPLE_MOVE ++ if that parameter is true. ++ (rest_of_handle_lower_subreg): Call decompose_multiword_subregs ++ with DECOMPOSE_COPIES false. ++ (rest_of_handle_lower_subreg2): Call decompose_multiword_subregs ++ with DECOMPOSE_COPIES true. ++ ++ gcc/testsuite/ ++ 2012-09-27 Ulrich Weigand ++ ++ * gcc.dg/lower-subreg-1.c: Disable on arm-*-* targets. ++ ++2012-12-19 Christophe Lyon ++ ++ gcc/testsuite/ ++ * gcc.target/arm/builtin-bswap16-1.c: Replace armv6 by armv7a to ++ avoid failure when testing on hard-float+thumb target. ++ * gcc.target/arm/builtin-bswap-1.c: Likewise. ++ ++ ++ Backport from mainline r191760: ++ ++ 2012-09-21 Christophe Lyon ++ ++ gcc/ ++ * tree-ssa-math-opts.c (bswap_stats): Add found_16bit field. ++ (execute_optimize_bswap): Add support for builtin_bswap16. ++ ++ gcc/testsuite/ ++ * gcc.target/arm/builtin-bswap16-1.c: New testcase. ++ ++ ++ Backport from mainline r188526: ++ ++ 2012-06-13 Alexandre Oliva ++ ++ gcc/ ++ * common.opt (ftree-coalesce-inlined-vars): New. ++ (ftree-coalesce-vars): New. ++ * doc/invoke.texi: Document them. ++ * tree-ssa-copyrename.c (copy_rename_partition_coalesce): ++ Implement them. ++ ++ gcc/testsuite/ ++ * g++.dg/tree-ssa/ivopts-2.C: Adjust for coalescing. ++ * gcc.dg/tree-ssa/forwprop-11.c: Likewise. ++ * gcc.dg/tree-ssa/ssa-fre-1.c: Likewise. ++ ++ ++ Backport from mainline r191243: ++ ++ 2012-09-13 Christophe Lyon ++ Richard Earnshaw ++ ++ gcc/ ++ * config/arm/arm.md (arm_rev): Factorize thumb1, thumb2 and arm ++ variants for rev instruction.. ++ (thumb1_rev): Delete pattern. ++ (arm_revsh): New pattern to support builtin_bswap16. ++ (arm_rev16, bswaphi2): Likewise. ++ ++ gcc/testsuite/ ++ * gcc.target/arm/builtin-bswap-1.c: New testcase. ++ ++ ++ Backport from mainline r186308: ++ ++ PR target/52624 ++ gcc/ ++ * doc/extend.texi (Other Builtins): Document __builtin_bswap16. ++ (PowerPC AltiVec/VSX Built-in Functions): Remove it. ++ * doc/md.texi (Standard Names): Add bswap. ++ * builtin-types.def (BT_UINT16): New primitive type. ++ (BT_FN_UINT16_UINT16): New function type. ++ * builtins.def (BUILT_IN_BSWAP16): New. ++ * builtins.c (expand_builtin_bswap): Add TARGET_MODE argument. ++ (expand_builtin) : New case. Pass TARGET_MODE to ++ expand_builtin_bswap. ++ (fold_builtin_bswap): Add BUILT_IN_BSWAP16 case. ++ (fold_builtin_1): Likewise. ++ (is_inexpensive_builtin): Likewise. ++ * optabs.c (expand_unop): Deal with bswap in HImode specially. Add ++ missing bits for bswap to libcall code. ++ * tree.c (build_common_tree_nodes): Build uint16_type_node. ++ * tree.h (enum tree_index): Add TI_UINT16_TYPE. ++ (uint16_type_node): New define. ++ * config/rs6000/rs6000-builtin.def (RS6000_BUILTIN_BSWAP_HI): Delete. ++ * config/rs6000/rs6000.c (rs6000_expand_builtin): Remove handling of ++ above builtin. ++ (rs6000_init_builtins): Likewise. ++ * config/rs6000/rs6000.md (bswaphi2): Add TARGET_POWERPC predicate. ++ ++ gcc/c-family/ ++ * c-common.h (uint16_type_node): Rename into... ++ (c_uint16_type_node): ...this. ++ * c-common.c (c_common_nodes_and_builtins): Adjust for above renaming. ++ * c-cppbuiltin.c (builtin_define_stdint_macros): Likewise. ++ ++ gcc/testsuite/ ++ * gcc.dg/builtin-bswap-1.c: Test __builtin_bswap16 & __builtin_bswap64. ++ * gcc.dg/builtin-bswap-4.c: Test __builtin_bswap16. ++ * gcc.dg/builtin-bswap-5.c: Likewise. ++ * gcc.target/i386/builtin-bswap-4.c: New test. ++ ++2012-12-17 Ulrich Weigand ++ ++ LP 1088898 ++ ++ Backport from mainline ++ ++ gcc/ ++ 2012-09-24 Richard Guenther ++ ++ PR tree-optimization/54684 ++ * tree-ssa-ccp.c (optimize_unreachable): Properly update stmts. ++ ++ gcc/testsuite/ ++ 2012-09-24 Richard Guenther ++ ++ PR tree-optimization/54684 ++ * g++.dg/torture/pr54684.C: New testcase. ++ ++2012-12-14 Michael Hope ++ ++ Backport from mainline r192569: ++ ++ gcc/ ++ 2012-10-18 Matthew Gretton-Dann ++ Ramana Radhakrishnan ++ Sameera Deshpande ++ ++ * config/arm/cortex-a15-neon.md: New file. ++ * config/arm/cortex-a15.md (cortex_a15_call): Adjust reservation. ++ (cortex_a15_load1): Likewise. ++ (cortex_a15_load3): Likewise. ++ (cortex_a15_store1): Likewise. ++ (cortex_a15_store3): Likewise. ++ (cortex-a15-neon.md): Include. ++ ++2012-12-14 Michael Hope ++ ++ Backport from mainline r193724: ++ ++ gcc/ ++ 2012-11-20 Kyrylo Tkachov ++ ++ * config/arm/arm.md (*arm_abssi2): Define predicable attribute. ++ (*arm_neg_abssi2): Likewise. ++ * config/arm/thumb2.md (*thumb2_abssi2): Likewise. ++ (*thumb2_neg_abssi2): Likewise. ++ ++ Backport from mainline r194398: ++ ++ gcc/ ++ 2012-12-11 Kyrylo Tkachov ++ ++ PR target/55642 ++ * config/arm/thumb2.md (*thumb2_abssi2): ++ Set ce_count attribute to 2. ++ (*thumb2_neg_abssi2): Likewise. ++ ++ gcc/testsuite/ ++ 2012-12-11 Kyrylo Tkachov ++ ++ PR target/55642 ++ * gcc.target/arm/pr55642.c: New testcase. ++ ++2012-12-11 Yvan Roux ++ ++ gcc/ ++ * LINARO-VERSION: Bump version. ++ ++2012-12-11 Yvan Roux ++ ++ GCC Linaro 4.7-2012.12 released. ++ ++ gcc/ ++ * LINARO-VERSION: Update. ++ ++2012-12-05 Michael Hope ++ ++ Merge from FSF arm/aarch64-4.7-branch r193937..r194154. ++ ++ Backport arm-aarch64-4.7 r193937: ++ gcc/ChangeLog.aarch64 ++ ++ Backport from mainline. ++ 2012-11-20 James Greenhalgh ++ Tejas Belagod ++ ++ * config/aarch64/aarch64-builtins.c ++ (aarch64_simd_builtin_type_bits): Rename to... ++ (aarch64_simd_builtin_type_mode): ...this, make sequential. ++ (aarch64_simd_builtin_datum): Refactor members. ++ (VAR1, VAR2, ..., VAR12): Update accordingly. ++ (aarch64_simd_builtin_data): Include from aarch64-simd-builtins.def. ++ (aarch64_builtins): Update accordingly. ++ (init_aarch64_simd_builtins): Refactor, rename to... ++ (aarch64_init_simd_builtins): ...this. ++ (aarch64_simd_builtin_compare): Remove. ++ (locate_simd_builtin_icode): Likewise. ++ * config/aarch64/aarch64-protos.h (aarch64_init_builtins): New. ++ (aarch64_expand_builtin): Likewise. ++ (aarch64_load_tp): Likewise. ++ * config/aarch64/aarch64-simd-builtins.def: New file. ++ * config/aarch64/aarch64.c (aarch64_init_builtins): ++ Move to aarch64-builtins.c. ++ (aarch64_expand_builtin): Likewise. ++ (aarch64_load_tp): Remove static designation. ++ * config/aarch64/aarch64.h ++ (aarch64_builtins): Move to aarch64-builtins.c. ++ ++ Backport arm-aarch64-4.7 r193939: ++ gcc/ ++ ++ Backport from mainline. ++ 2012-11-26 James Greenhalgh ++ ++ * config/aarch64/aarch64-builtins.c (aarch64_builtin_decls): New. ++ (aarch64_init_simd_builtins): Store declaration after builtin ++ initialisation. ++ (aarch64_init_builtins): Likewise. ++ (aarch64_builtin_decl): New. ++ * config/aarch64/aarch64-protos.h (aarch64_builtin_decl): New. ++ * config/aarch64/aarch64.c (TARGET_BUILTIN_DECL): Define. ++ ++ Backport arm-aarch64-4.7 r194079: ++ [AARCH64-4.7] Refactor constant generation. ++ ++ 2012-12-03 Sofiane Naci ++ ++ * config/aarch64/aarch64.c (aarch64_build_constant): Update prototype. ++ Call emit_move_insn instead of printing movi/movn/movz instructions. ++ Call gen_insv_immdi instead of printing movk instruction. ++ (aarch64_add_constant): Update prototype. ++ Generate RTL instead of printing add/sub instructions. ++ (aarch64_output_mi_thunk): Update calls to aarch64_build_constant ++ and aarch64_add_constant. ++ ++ Backport arm-aarch64-4.7 r194089: ++ [AARCH64-4.7] Backport - Add vcond, vcondu support. ++ ++ Backport of revision 192985. ++ ++ gcc/ ++ * config/aarch64/aarch64-simd.md ++ (aarch64_simd_bsl_internal): New pattern. ++ (aarch64_simd_bsl): Likewise. ++ (aarch64_vcond_internal): Likewise. ++ (vcondu): Likewise. ++ (vcond): Likewise. ++ * config/aarch64/iterators.md (UNSPEC_BSL): Add to define_constants. ++ ++ Backport arm-aarch64-4.7 r194131: ++ ++ 2012-12-04 Tejas Belagod ++ ++ * config/aarch64/aarch64.c (aarch64_simd_vector_alignment, ++ aarch64_simd_vector_alignment_reachable): New. ++ (TARGET_VECTOR_ALIGNMENT, TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE): ++ Define. ++ ++ Backport arm-aarch64-4.7 r194148: ++ AArch64: Fix ICE due to missing TYPE_STUB_DECL on builtin va_list. ++ ++ 2012-12-04 Marcus Shawcroft ++ ++ * config/aarch64/aarch64.c (aarch64_build_builtin_va_list): Set ++ TYPE_STUB_DECL. ++ ++ Backport arm-aarch64-4.7 r194153: ++ AArch64-4.7: Backport refactor of sfp-machine.h ++ ++ Backport arm-aarch64-4.7 r194154: ++ AArch64-4.7: Backport implement FP_TRAPPING_EXCEPTIONS. ++ ++2012-12-05 Yvan Roux ++ ++ Merge from FSF GCC 4.7.2 (svn branches/gcc-4_7-branch 194184). ++ ++2012-11-26 Michael Hope ++ ++ Merge from FSF arm/aarch64-4.7-branch r193473..r193768. ++ ++ Backport arm-aarch64-4.7 r193473: ++ Backport from mainline: Optimise comparison where intermediate result not used (AArch64) ++ ++ Backport arm-aarch64-4.7 r193474: ++ Backport from mainline: Use CSINC instead of CSEL to return 1 (AArch64) ++ ++ Backport arm-aarch64-4.7 r193496: ++ Fixed up changelogs ++ ++ Backport arm-aarch64-4.7 r193533: ++ Update soft-fp from glibc. ++ ++ 2012-11-15 Marcus Shawcroft ++ ++ * soft-fp: Updated from glibc upstream. ++ ++ Backport arm-aarch64-4.7 r193541: ++ Move ChangeLog entry to ChangeLog.aarch64. ++ ++ The previous commit put the ChangeLog entry into the wrong file. ++ ++ Backport arm-aarch64-4.7 r193572: ++ Fix commit of testcase which got truncated somehow. ++ ++ Backport arm-aarch64-4.7 r193650: ++ Backport from mainline: r193630. ++ ++ gcc/ ++ * config/aarch64/aarch64.c ++ (aarch64_output_mi_thunk): Refactor to generate RTL patterns. ++ ++ Backport arm-aarch64-4.7 r193652: ++ Backport from trunk revision 193651. ++ ++ gcc/ ++ * config/aarch64/aarch64.md ++ (define_attr "sync_*"): Remove. ++ (define_attr "length"): Update. ++ Include atomics.md. ++ * config/aarch64/aarch64-protos.h ++ (aarch64_expand_compare_and_swap): Add function prototype. ++ (aarch64_split_compare_and_swap): Likewise. ++ (aarch64_split_atomic_op): Likewise. ++ (aarch64_expand_sync): Remove function prototype. ++ (aarch64_output_sync_insn): Likewise. ++ (aarch64_output_sync_lock_release): Likewise. ++ (aarch64_sync_loop_insns): Likewise. ++ (struct aarch64_sync_generator): Remove. ++ (enum aarch64_sync_generator_tag): Likewise. ++ * config/aarch64/aarch64.c ++ (aarch64_legitimize_sync_memory): Remove function. ++ (aarch64_emit): Likewise. ++ (aarch64_insn_count): Likewise. ++ (aarch64_output_asm_insn): Likewise. ++ (aarch64_load_store_suffix): Likewise. ++ (aarch64_output_sync_load): Likewise. ++ (aarch64_output_sync_store): Likewise. ++ (aarch64_output_op2): Likewise. ++ (aarch64_output_op3): Likewise. ++ (aarch64_output_sync_loop): Likewise. ++ (aarch64_get_sync_operand): Likewise. ++ (aarch64_process_output_sync_insn): Likewise. ++ (aarch64_output_sync_insn): Likewise. ++ (aarch64_output_sync_lock_release): Likewise. ++ (aarch64_sync_loop_insns): Likewise. ++ (aarch64_call_generator): Likewise. ++ (aarch64_expand_sync): Likewise. ++ (* emit_f): Remove variable. ++ (aarch64_insn_count): Likewise. ++ (FETCH_SYNC_OPERAND): Likewise. ++ (aarch64_emit_load_exclusive): New function. ++ (aarch64_emit_store_exclusive): Likewise. ++ (aarch64_emit_unlikely_jump): Likewise. ++ (aarch64_expand_compare_and_swap): Likewise. ++ (aarch64_split_compare_and_swap): Likewise. ++ (aarch64_split_atomic_op): Likewise. ++ * config/aarch64/iterators.md ++ (atomic_sfx): New mode attribute. ++ (atomic_optab): New code attribute. ++ (atomic_op_operand): Likewise. ++ (atomic_op_str): Likewise. ++ (syncop): Rename to atomic_op. ++ * config/aarch64/sync.md: Delete. ++ * config/aarch64/atomics.md: New file. ++ ++ gcc/testsuite ++ * gcc.target/aarch64/atomic-comp-swap-release-acquire.c: New testcase. ++ * gcc.target/aarch64/atomic-op-acq_rel.c: Likewise. ++ * gcc.target/aarch64/atomic-op-acquire.c: Likewise. ++ * gcc.target/aarch64/atomic-op-char.c: Likewise. ++ * gcc.target/aarch64/atomic-op-consume.c: Likewise. ++ * gcc.target/aarch64/atomic-op-imm.c: Likewise. ++ * gcc.target/aarch64/atomic-op-int.c: Likewise. ++ * gcc.target/aarch64/atomic-op-long.c: Likewise. ++ * gcc.target/aarch64/atomic-op-relaxed.c: Likewise. ++ * gcc.target/aarch64/atomic-op-release.c: Likewise. ++ * gcc.target/aarch64/atomic-op-seq_cst.c: Likewise. ++ * gcc.target/aarch64/atomic-op-short.c: Likewise. ++ ++ Backport arm-aarch64-4.7 r193655: ++ Fix to commit 193652. ++ ++ gcc/ ++ * config/aarch64/atomics.md: Actually add this file. ++ ++ gcc/testsuite/ ++ * gcc.target/aarch64/atomic-comp-swap-release-acquire.c: ++ Actually add this file. ++ * gcc.target/aarch64/atomic-op-acq_rel.c: Likewise. ++ * gcc.target/aarch64/atomic-op-acquire.c: Likewise. ++ * gcc.target/aarch64/atomic-op-char.c: Likewise. ++ * gcc.target/aarch64/atomic-op-consume.c: Likewise. ++ * gcc.target/aarch64/atomic-op-imm.c: Likewise. ++ * gcc.target/aarch64/atomic-op-int.c: Likewise. ++ * gcc.target/aarch64/atomic-op-long.c: Likewise. ++ * gcc.target/aarch64/atomic-op-relaxed.c: Likewise. ++ * gcc.target/aarch64/atomic-op-release.c: Likewise. ++ * gcc.target/aarch64/atomic-op-seq_cst.c: Likewise. ++ * gcc.target/aarch64/atomic-op-short.c: Likewise. ++ ++ Backport arm-aarch64-4.7 r193689: ++ gcc/ ++ * config/aarch64/aarch64.c ++ (aarch64_output_mi_thunk): Use 4.7 API for plus_constant. ++ ++ Backport arm-aarch64-4.7 r193693: ++ Fix race in parallel build. ++ ++ The gengtype-lex.c is built twice, once for BUILD and once for HOST, but the ++ HOST flavour is missing a dependency on $(BCONFIG_H). ++ ++ 2012-11-21 Marcus Shawcroft ++ ++ * Makefile.in (gengtype-lex.o): Add dependency on $(BCONFIG_H). ++ ++ Backport arm-aarch64-4.7 r193696: ++ gcc/ ++ * ChangeLog: Move recent entries to... ++ * ChangeLog.aarch64: ...Here. ++ ++ gcc/testsuite/ ++ * ChangeLog: Move recent entries to... ++ * ChangeLog.aarch64: ...Here ++ ++ Backport arm-aarch64-4.7 r193730: ++ Backport of Implement bswaphi2 with rev16 (AArch64) ++ ++ Backport arm-aarch64-4.7 r193733: ++ [AARCH64-47] Backported removal of Utf documentation. ++ ++ 2012-11-22 Marcus Shawcroft ++ ++ * doc/md.texi (AArch64 family): Remove Utf. ++ ++ Backport arm-aarch64-4.7 r193765: ++ Backport of builtin_bswap16 support ++ ++ Backport arm-aarch64-4.7 r193768: ++ [AARCH64-47] Reverting backport of builtin_bswap16. ++ ++ Reverted: ++ r193765 | ibolton | 2012-11-23 17:53:08 +0000 (Fri, 23 Nov 2012) | 1 line ++ ++ Backport of builtin_bswap16 support ++ ++2012-11-19 Ulrich Weigand ++ ++ Backport from mainline ++ ++ gcc/ ++ 2012-11-13 Andrew Stubbs ++ Ulrich Weigand ++ ++ * config/arm/arm.c (arm_emit_coreregs_64bit_shift): Fix comment. ++ * config/arm/arm.md (opt, opt_enabled): New attributes. ++ (enabled): Use opt_enabled. ++ (ashldi3, ashrdi3, lshrdi3): Add TARGET_NEON case. ++ (ashldi3): Allow general operands for TARGET_NEON case. ++ * config/arm/iterators.md (rshifts): New code iterator. ++ (shift, shifttype): New code attributes. ++ * config/arm/neon.md (UNSPEC_LOAD_COUNT): New unspec type. ++ (neon_load_count, ashldi3_neon_noclobber, ashldi3_neon, ++ signed_shift_di3_neon, unsigned_shift_di3_neon, ++ ashrdi3_neon_imm_noclobber, lshrdi3_neon_imm_noclobber, ++ di3_neon): New patterns. ++ ++2012-11-13 Matthew Gretton-Dann ++ ++ gcc/ ++ * LINARO-VERSION: Bump version. ++ +2012-11-13 Matthew Gretton-Dann + + GCC Linaro 4.7-2012.11 released. @@ -1911,689 +2842,760 @@ ;; m68*-cisco) os=-aout ---- a/src/gcc/ada/ChangeLog -+++ b/src/gcc/ada/ChangeLog -@@ -1,3 +1,36 @@ -+2012-10-30 Eric Botcazou -+ -+ * gcc-interface/Make-lang.in: Fix and clean up rules for C files. -+ -+2012-10-22 Eric Botcazou -+ -+ * gcc-interface/decl.c (gnat_to_gnu_entity) : Force -+ BLKmode on the type if it is passed by reference. -+ : Likewise. -+ : Guard the call to Is_By_Reference_Type predicate. -+ : Likewise. -+ -+ * gcc-interface/Makefile.in: Remove outdated comment and reference to -+ non-existing file. -+ -+2012-10-22 Eric Botcazou -+ -+ * gcc-interface/trans.c (Loop_Statement_to_gnu): Use gnat_type_for_size -+ directly to obtain an unsigned version of the base type. -+ -+2012-10-22 Eric Botcazou -+ -+ * gcc-interface/decl.c (gnat_to_gnu_entity) : Do not -+ generate the special PARM_DECL for an Out parameter in LTO mode. -+ -+2012-10-02 Eric Botcazou -+ -+ * gcc-interfaces/decl.c (elaborate_expression_1): Use the variable for -+ bounds of loop iteraration scheme only for locally defined subtypes. -+ -+ * gcc-interface/trans.c (build_return_expr): Apply the NRV optimization -+ only for BLKmode. -+ - 2012-09-20 Release Manager - - * GCC 4.7.2 released. ---- a/src/gcc/ada/gcc-interface/decl.c -+++ b/src/gcc/ada/gcc-interface/decl.c -@@ -1508,7 +1508,11 @@ - the VAR_DECL. Suppress debug info for the latter but make sure it - will live on the stack so that it can be accessed from within the - debugger through the PARM_DECL. */ -- if (kind == E_Out_Parameter && definition && !optimize && debug_info_p) -+ if (kind == E_Out_Parameter -+ && definition -+ && debug_info_p -+ && !optimize -+ && !flag_generate_lto) - { - tree param = create_param_decl (gnu_entity_name, gnu_type, false); - gnat_pushdecl (param, gnat_entity); -@@ -2251,6 +2255,12 @@ - TYPE_MULTI_ARRAY_P (tem) = (index > 0); - if (array_type_has_nonaliased_component (tem, gnat_entity)) - TYPE_NONALIASED_COMPONENT (tem) = 1; -+ -+ /* If it is passed by reference, force BLKmode to ensure that -+ objects of this type will always be put in memory. */ -+ if (TYPE_MODE (tem) != BLKmode -+ && Is_By_Reference_Type (gnat_entity)) -+ SET_TYPE_MODE (tem, BLKmode); - } - - /* If an alignment is specified, use it if valid. But ignore it -@@ -2590,6 +2600,11 @@ - TYPE_MULTI_ARRAY_P (gnu_type) = (index > 0); - if (array_type_has_nonaliased_component (gnu_type, gnat_entity)) - TYPE_NONALIASED_COMPONENT (gnu_type) = 1; -+ -+ /* See the E_Array_Type case for the rationale. */ -+ if (TYPE_MODE (gnu_type) != BLKmode -+ && Is_By_Reference_Type (gnat_entity)) -+ SET_TYPE_MODE (gnu_type, BLKmode); - } +--- a/src/gcc/builtins.c ++++ b/src/gcc/builtins.c +@@ -4626,13 +4626,15 @@ + return result; + } - /* Attach the TYPE_STUB_DECL in case we have a parallel type. */ -@@ -3158,7 +3173,8 @@ +-/* Expand a call to a bswap builtin with argument ARG0. MODE +- is the mode to expand with. */ ++/* Expand a call to bswap builtin in EXP. ++ Return NULL_RTX if a normal call should be emitted rather than expanding the ++ function in-line. If convenient, the result should be placed in TARGET. ++ SUBTARGET may be used as the target for computing one of EXP's operands. */ - /* If it is passed by reference, force BLKmode to ensure that objects - of this type will always be put in memory. */ -- if (Is_By_Reference_Type (gnat_entity)) -+ if (TYPE_MODE (gnu_type) != BLKmode -+ && Is_By_Reference_Type (gnat_entity)) - SET_TYPE_MODE (gnu_type, BLKmode); - - /* We used to remove the associations of the discriminants and _Parent -@@ -3526,12 +3542,12 @@ - modify it below. */ - gnu_field_list = nreverse (gnu_field_list); - finish_record_type (gnu_type, gnu_field_list, 2, false); -+ compute_record_mode (gnu_type); - - /* See the E_Record_Type case for the rationale. */ -- if (Is_By_Reference_Type (gnat_entity)) -+ if (TYPE_MODE (gnu_type) != BLKmode -+ && Is_By_Reference_Type (gnat_entity)) - SET_TYPE_MODE (gnu_type, BLKmode); -- else -- compute_record_mode (gnu_type); + static rtx +-expand_builtin_bswap (tree exp, rtx target, rtx subtarget) ++expand_builtin_bswap (enum machine_mode target_mode, tree exp, rtx target, ++ rtx subtarget) + { +- enum machine_mode mode; + tree arg; + rtx op0; - TYPE_VOLATILE (gnu_type) = Treat_As_Volatile (gnat_entity); +@@ -4640,14 +4642,18 @@ + return NULL_RTX; -@@ -6346,6 +6362,7 @@ - use_variable = expr_variable_p - && (expr_global_p - || (!optimize -+ && definition - && Is_Itype (gnat_entity) - && Nkind (Associated_Node_For_Itype (gnat_entity)) - == N_Loop_Parameter_Specification)); ---- a/src/gcc/ada/gcc-interface/Makefile.in -+++ b/src/gcc/ada/gcc-interface/Makefile.in -@@ -1242,7 +1242,6 @@ - s-taprop.adb TYPE_PRECISION (size_type_node)) -- gnu_base_type = gnat_unsigned_type (gnu_base_type); -+ gnu_base_type -+ = gnat_type_for_size (TYPE_PRECISION (gnu_base_type), 1); - else - gnu_base_type = size_type_node; +-/* Fold function call to builtin_bswap and the long and long long ++/* Fold function call to builtin_bswap and the short, long and long long + variants. Return NULL_TREE if no simplification can be made. */ + static tree + fold_builtin_bswap (tree fndecl, tree arg) +@@ -8189,15 +8195,15 @@ + { + HOST_WIDE_INT hi, width, r_hi = 0; + unsigned HOST_WIDE_INT lo, r_lo = 0; +- tree type; ++ tree type = TREE_TYPE (TREE_TYPE (fndecl)); + +- type = TREE_TYPE (arg); + width = TYPE_PRECISION (type); + lo = TREE_INT_CST_LOW (arg); + hi = TREE_INT_CST_HIGH (arg); -@@ -3123,6 +3124,7 @@ - if (optimize - && AGGREGATE_TYPE_P (operation_type) - && !TYPE_IS_FAT_POINTER_P (operation_type) -+ && TYPE_MODE (operation_type) == BLKmode - && aggregate_value_p (operation_type, current_function_decl)) + switch (DECL_FUNCTION_CODE (fndecl)) { - /* Recognize the temporary created for a return value with variable ---- a/src/gcc/cfgexpand.c -+++ b/src/gcc/cfgexpand.c -@@ -697,6 +697,8 @@ - (void *)(size_t) uid)) = part; - *((tree *) pointer_map_insert (cfun->gimple_df->decls_to_pointers, - decl)) = name; -+ if (TREE_ADDRESSABLE (decl)) -+ TREE_ADDRESSABLE (name) = 1; ++ case BUILT_IN_BSWAP16: + case BUILT_IN_BSWAP32: + case BUILT_IN_BSWAP64: + { +@@ -8227,9 +8233,9 @@ } - /* Make the SSA name point to all partition members. */ ---- a/src/gcc/ChangeLog -+++ b/src/gcc/ChangeLog -@@ -1,3 +1,439 @@ -+2012-11-05 H.J. Lu + if (width < HOST_BITS_PER_WIDE_INT) +- return build_int_cst (TREE_TYPE (TREE_TYPE (fndecl)), r_lo); ++ return build_int_cst (type, r_lo); + else +- return build_int_cst_wide (TREE_TYPE (TREE_TYPE (fndecl)), r_lo, r_hi); ++ return build_int_cst_wide (type, r_lo, r_hi); + } + + return NULL_TREE; +@@ -10582,6 +10588,7 @@ + CASE_FLT_FN (BUILT_IN_LLRINT): + return fold_fixed_mathfn (loc, fndecl, arg0); + ++ case BUILT_IN_BSWAP16: + case BUILT_IN_BSWAP32: + case BUILT_IN_BSWAP64: + return fold_builtin_bswap (fndecl, arg0); +@@ -14346,6 +14353,7 @@ + case BUILT_IN_ABS: + case BUILT_IN_ALLOCA: + case BUILT_IN_ALLOCA_WITH_ALIGN: ++ case BUILT_IN_BSWAP16: + case BUILT_IN_BSWAP32: + case BUILT_IN_BSWAP64: + case BUILT_IN_CLZ: +--- a/src/gcc/builtins.def ++++ b/src/gcc/builtins.def +@@ -628,6 +628,7 @@ + DEF_EXT_LIB_BUILTIN (BUILT_IN_ALLOCA, "alloca", BT_FN_PTR_SIZE, ATTR_MALLOC_NOTHROW_LEAF_LIST) + DEF_GCC_BUILTIN (BUILT_IN_APPLY, "apply", BT_FN_PTR_PTR_FN_VOID_VAR_PTR_SIZE, ATTR_NULL) + DEF_GCC_BUILTIN (BUILT_IN_APPLY_ARGS, "apply_args", BT_FN_PTR_VAR, ATTR_LEAF_LIST) ++DEF_GCC_BUILTIN (BUILT_IN_BSWAP16, "bswap16", BT_FN_UINT16_UINT16, ATTR_CONST_NOTHROW_LEAF_LIST) + DEF_GCC_BUILTIN (BUILT_IN_BSWAP32, "bswap32", BT_FN_UINT32_UINT32, ATTR_CONST_NOTHROW_LEAF_LIST) + DEF_GCC_BUILTIN (BUILT_IN_BSWAP64, "bswap64", BT_FN_UINT64_UINT64, ATTR_CONST_NOTHROW_LEAF_LIST) + DEF_EXT_LIB_BUILTIN (BUILT_IN_CLEAR_CACHE, "__clear_cache", BT_FN_VOID_PTR_PTR, ATTR_NOTHROW_LEAF_LIST) +--- a/src/gcc/builtin-types.def ++++ b/src/gcc/builtin-types.def +@@ -76,6 +76,7 @@ + DEF_PRIMITIVE_TYPE (BT_UINT128, int128_unsigned_type_node) + DEF_PRIMITIVE_TYPE (BT_INTMAX, intmax_type_node) + DEF_PRIMITIVE_TYPE (BT_UINTMAX, uintmax_type_node) ++DEF_PRIMITIVE_TYPE (BT_UINT16, uint16_type_node) + DEF_PRIMITIVE_TYPE (BT_UINT32, uint32_type_node) + DEF_PRIMITIVE_TYPE (BT_UINT64, uint64_type_node) + DEF_PRIMITIVE_TYPE (BT_WORD, (*lang_hooks.types.type_for_mode) (word_mode, 1)) +@@ -226,6 +227,7 @@ + DEF_FUNCTION_TYPE_1 (BT_FN_UINT_UINT, BT_UINT, BT_UINT) + DEF_FUNCTION_TYPE_1 (BT_FN_ULONG_ULONG, BT_ULONG, BT_ULONG) + DEF_FUNCTION_TYPE_1 (BT_FN_ULONGLONG_ULONGLONG, BT_ULONGLONG, BT_ULONGLONG) ++DEF_FUNCTION_TYPE_1 (BT_FN_UINT16_UINT16, BT_UINT16, BT_UINT16) + DEF_FUNCTION_TYPE_1 (BT_FN_UINT32_UINT32, BT_UINT32, BT_UINT32) + DEF_FUNCTION_TYPE_1 (BT_FN_UINT64_UINT64, BT_UINT64, BT_UINT64) + +--- a/src/gcc/c-family/c-common.c ++++ b/src/gcc/c-family/c-common.c +@@ -4992,7 +4992,7 @@ + uint8_type_node = + TREE_TYPE (identifier_global_value (c_get_ident (UINT8_TYPE))); + if (UINT16_TYPE) +- uint16_type_node = ++ c_uint16_type_node = + TREE_TYPE (identifier_global_value (c_get_ident (UINT16_TYPE))); + if (UINT32_TYPE) + c_uint32_type_node = +--- a/src/gcc/c-family/c-common.h ++++ b/src/gcc/c-family/c-common.h +@@ -390,7 +390,7 @@ + #define int32_type_node c_global_trees[CTI_INT32_TYPE] + #define int64_type_node c_global_trees[CTI_INT64_TYPE] + #define uint8_type_node c_global_trees[CTI_UINT8_TYPE] +-#define uint16_type_node c_global_trees[CTI_UINT16_TYPE] ++#define c_uint16_type_node c_global_trees[CTI_UINT16_TYPE] + #define c_uint32_type_node c_global_trees[CTI_UINT32_TYPE] + #define c_uint64_type_node c_global_trees[CTI_UINT64_TYPE] + #define int_least8_type_node c_global_trees[CTI_INT_LEAST8_TYPE] +--- a/src/gcc/c-family/c-cppbuiltin.c ++++ b/src/gcc/c-family/c-cppbuiltin.c +@@ -448,8 +448,8 @@ + builtin_define_type_max ("__INT64_MAX__", int64_type_node); + if (uint8_type_node) + builtin_define_type_max ("__UINT8_MAX__", uint8_type_node); +- if (uint16_type_node) +- builtin_define_type_max ("__UINT16_MAX__", uint16_type_node); ++ if (c_uint16_type_node) ++ builtin_define_type_max ("__UINT16_MAX__", c_uint16_type_node); + if (c_uint32_type_node) + builtin_define_type_max ("__UINT32_MAX__", c_uint32_type_node); + if (c_uint64_type_node) +--- a/src/gcc/ChangeLog.aarch64 ++++ b/src/gcc/ChangeLog.aarch64 +@@ -0,0 +1,1070 @@ ++2013-03-01 James Greenhalgh + -+ * config/i386/i386.c (print_reg): Replace REX_INT_REG_P with -+ REX_INT_REGNO_P. ++ * config/aarch64/aarch64.c: ++ Fix typo in `#undef TARGET_FIXED_CONDITION_CODE_REGS' + -+2012-11-05 Eric Botcazou ++2013-02-28 James Greenhalgh + -+ PR tree-optimization/54986 -+ * gimple-fold.c (canonicalize_constructor_val): Strip again all no-op -+ conversions on entry but add them back on exit if needed. ++ * config/aarch64/aarch64.c ++ (aarch64_float_const_representable): Remove unused variable. + -+2012-11-05 Richard Sandiford ++2013-02-28 James Greenhalgh + -+ PR target/55204 -+ * config/i386/i386.c (ix86_address_subreg_operand): Remove stack -+ pointer check. -+ (print_reg): Use true_regnum rather than REGNO. -+ (ix86_print_operand_address): Remove SUBREG handling. ++ * config/aarch64/aarch64.c (aarch64_mangle_type): Make static. + -+2012-11-05 Jakub Jelinek ++2013-02-28 James Greenhalgh + -+ Backported from mainline -+ 2012-10-24 Jakub Jelinek ++ * config/aarch64/aarch64-builtins.c ++ (aarch64_init_simd_builtins): Make static. + -+ PR debug/54828 -+ * gimple.h (is_gimple_sizepos): New inline function. -+ * gimplify.c (gimplify_one_sizepos): Use it. Remove useless -+ final assignment to expr variable. -+ * tree.c (RETURN_TRUE_IF_VAR): Return true also if -+ !TYPE_SIZES_GIMPLIFIED (type) and _t is going to be gimplified -+ into a local temporary. ++2013-02-28 James Greenhalgh + -+ 2012-10-10 Jakub Jelinek ++ * config/aarch64/aarch64.c ++ (aarch64_simd_make_constant): Make static. + -+ PR tree-optimization/54877 -+ * tree-vect-loop.c (vect_is_simple_reduction_1): For MINUS_EXPR -+ use make_ssa_name instead of copy_ssa_name. ++2013-02-22 James Greenhalgh + -+2012-11-03 Peter Bergner ++ * config/aarch64/aarch64-simd-builtins.def: Add copyright header. ++ * config/aarch64/t-aarch64 ++ (aarch64-builtins.o): Depend on aarch64-simd-builtins.def. + -+ Backport from mainline -+ 2012-10-31 Jakub Jelinek ++2013-02-13 James Greenhalgh + -+ PR tree-optimization/53708 -+ * tree-vect-data-refs.c (vect_can_force_dr_alignment_p): Preserve -+ user-supplied alignment when used with an explicit section name. ++ Backport from aarch64-branch. ++ 2012-09-06 James Greenhalgh ++ Richard Earnshaw ++ ++ * common/config/aarch64/aarch64-common.c ++ (aarch_option_optimization_table): New. ++ (TARGET_OPTION_OPTIMIZATION_TABLE): Define. ++ * gcc/config/aarch64/aarch64-elf.h (ASM_OUTPUT_DEF): New definition. ++ * gcc/config/aarch64/aarch64.c (TARGET_MIN_ANCHOR_OFFSET): Define. ++ (TARGET_MAX_ANCHOR_OFFSET): Likewise. + -+2012-11-02 Jeff Law ++2013-02-04 James Greenhalgh + -+ PR tree-optimization/54985 -+ * tree-ssa-threadedge.c (cond_arg_set_in_bb): New function extracted -+ from thread_across_edge. -+ (thread_across_edge): Use it in all cases where we might thread -+ across a back edge. ++ Backport from mainline. ++ 2012-12-18 James Greenhalgh + -+2012-10-31 Eric Botcazou ++ * config/aarch64/aarch64.md (insv_imm): Add modes ++ for source operands. + -+ * config/i386/i386.c (ix86_expand_prologue): Emit frame info for the -+ special register pushes before frame probing and allocation. ++2013-02-04 James Greenhalgh + -+2012-10-31 Ralf Corsépius , -+ Joel Sherrill ++ * config/aarch64/aarch64.c ++ (aarch64_simd_const_bounds): Move declaration of 'lane' above code. + -+ * config/sparc/t-rtems: New (Custom multilibs). -+ * config/sparc/t-rtems-64: New (Custom multilibs). -+ * config.gcc (sparc64-*-rtems*): Add sparc/t-rtems-64. -+ (sparc-*-rtems*): Add sparc/t-rtems. ++2013-02-04 James Greenhalgh + -+2012-10-30 Eric Botcazou ++ * config/aarch64/aarch64.c ++ (aarch64_trampoline_init): Pass 'LCT_NORMAL' rather than '0' ++ to emit_library_call. + -+ * cse.c (hash_rtx_cb): Replace RTX_UNCHANGING_P with MEM_READONLY_P in -+ head comment. -+ (hash_rtx): Likewise. ++2013-02-04 James Greenhalgh + -+2012-10-29 Terry Guo ++ * config/aarch64/aarch64.c ++ (aarch64_legitimize_reload_address): Cast 'type' before ++ passing to push_reload. + -+ Backport from mainline -+ 2012-10-11 Terry Guo ++2013-02-04 James Greenhalgh + -+ * config/arm/arm.c (arm_arch6m): New variable to denote armv6-m -+ architecture. -+ * config/arm/arm.h (TARGET_HAVE_DMB): The armv6-m also has DMB -+ instruction. ++ * config/aarch64/aarch64.c ++ (aarch64_add_constant): Move declaration of 'shift' above code. + -+2012-10-26 Gunther Nikl ++2013-02-04 James Greenhalgh + -+ * common/config/m68k/m68k-common.c (m68k_handle_option): Set -+ gcc_options fields of opts_set for -m68020-40 and -m68020-60. ++ * config/aarch64/aarch64.c (generic_tunings): Initialise. + -+2012-10-26 Ralf Corsépius ++2013-02-01 Venkataramanan Kumar + -+ * config/avr/t-rtems: Revert previous commit. ++ backport from mainline. ++ 2013-01-04 Andrew Pinski + -+2012-10-26 Terry Guo ++ * gcc/testsuite/gcc.target/aarch64: ++ New test case cmp-1.c added to test the hook ++ TARGET_FIXED_CONDITION_CODE_REGS + -+ Backport from mainline -+ 2012-10-23 Terry Guo ++2013-02-01 Venkataramanan Kumar + -+ PR target/55019 -+ * config/arm/arm.c (thumb1_expand_prologue): Don't push high regs with -+ live argument regs. ++ Backport from mainline. ++ 2013-01-04 Andrew Pinski + -+2012-10-26 Ralf Corsépius ++ * config/aarch64/aarch64.c (aarch64_fixed_condition_code_regs): ++ New function. ++ (TARGET_FIXED_CONDITION_CODE_REGS): Define + -+ * config/avr/rtems.h (TARGET_OS_CPP_BUILTINS): Remove -+ __USE_INIT_FINI__. -+ * config/avr/t-rtems (LIB1ASMFUNCS): Filter out _exit. ++2013-01-25 Tejas Belagod + -+2012-10-25 Ralf Corsépius ++ * config/aarch64/aarch64-simd-builtins.def: Separate sqdmulh_lane ++ entries into lane and laneq entries. ++ * config/aarch64/aarch64-simd.md (aarch64_sqdmulh_lane): Remove ++ AdvSIMD scalar modes. ++ (aarch64_sqdmulh_laneq): New. ++ (aarch64_sqdmulh_lane): New RTL pattern for Scalar AdvSIMD ++ modes. ++ * config/aarch64/arm_neon.h: Fix all the vqdmulh_lane* intrinsics' ++ builtin implementations to relfect changes in RTL in aarch64-simd.md. ++ * config/aarch64/iterators.md (VCOND): New. ++ (VCONQ): New. + -+ * config.gcc (microblaze*-*-rtems*): New target. -+ * config/microblaze/rtems.h: New. -+ * config/microblaze/t-rtems: New. ++2013-01-18 James Greenhalgh + -+2012-10-25 Richard Biener ++ Backport from mainline. ++ 2013-01-18 James Greenhalgh + -+ PR tree-optimization/54902 -+ * tree-ssa-pre.c (fini_pre): Return TODO. -+ (execute_pre): Adjust. -+ * tree-ssa-tailmerge.c (tail_merge_optimize): Delete unreachable -+ blocks before computing dominators. ++ * config/aarch64/aarch64-simd.md ++ (aarch64_vcond_internal): Handle unordered cases. ++ * config/aarch64/iterators.md (v_cmp_result): New. + -+2012-10-24 Uros Bizjak ++2013-01-18 James Greenhalgh + -+ Backport from mainline -+ 2012-10-22 Uros Bizjak ++ Backport from mainline. ++ 2013-01-08 James Greenhalgh + -+ * config/i386/i386.c (memory_address_length): Assert that non-null -+ base or index RTXes are registers. Do not check for REG RTXes. -+ Determine addr32 prefix using SImode_address_operand or -+ from original base and index RTXes. Simplify code. ++ * config/aarch64/aarch64-simd.md ++ (aarch64_simd_bsl_internal): Add floating-point modes. ++ (aarch64_simd_bsl): Likewise. ++ (aarch64_vcond_internal): Likewise. ++ (vcond): Likewise. ++ (aarch64_cm): Fix constraints, add new modes. ++ * config/aarch64/iterators.md (V_cmp_result): Add V2DF. + -+ 2012-10-21 Uros Bizjak ++2013-01-18 Tejas Belagod + -+ * config/i386/i386-protos.h (memory_address_length): Add new bool -+ argument. Update all uses. -+ * config/i386/i386.c (memory_address_length): If not LEA insn, then -+ add length of addr32 prefix based on mode of base or index register. -+ (ix86_attr_length_address_default) : Do not handle SImode -+ addresses here. Update call to memory_address_length. -+ (ix86_print_address_operand): Use SImode_address_operand predicate. -+ * config/i386/predicates.md (SImode_address_operand): New. -+ * config/i386/i386.md (lea): Use SImode_address_operand -+ to calculate "mode" attribute. Use SImode_address_operand predicate -+ instead of open-coding accepted RTX codes. ++ * config/aarch64/arm_neon.h: Map scalar types to standard types. + -+2012-10-22 Georg-Johann Lay ++2013-01-14 Tejas Belagod + -+ Backport from 2012-10-22 trunk r192685. -+ * doc/invoke.texi (AVR Options): Document __AVR_ARCH__. -+ Note __AVR___ is not defined for cores. -+ Don't point to --help=target. -+ Order --mcu= documentation according to trunk:/gcc/doc/avr-mmcu.texi. ++ * config/aarch64/aarch64-simd.md (*aarch64_simd_ld1r): New. ++ * config/aarch64/iterators.md (VALLDI): New. + -+2012-10-19 Marek Polacek ++2013-01-10 James Greenhalgh + -+ Backported from mainline -+ 2012-10-19 Marek Polacek ++ Backport from mainline. ++ 2013-01-08 James Greenhalgh + -+ PR middle-end/54945 -+ * fold-const.c (fold_sign_changed_comparison): Punt if folding -+ pointer/non-pointer comparison. ++ * config/aarch64/aarch64-builtins.c ++ (aarch64_builtin_vectorized_function): Handle sqrt, sqrtf. + -+2012-10-19 Zhenqiang Chen ++2013-01-09 Naveen H.S + -+ Backported from mainline -+ 2012-10-19 Zhenqiang Chen ++ * config/aarch64/aarch64.c (aarch64_print_operand): Replace %r ++ in asm_fprintf with reg_names. ++ (aarch64_print_operand_address): Likewise. ++ (aarch64_return_addr): Likewise. ++ * config/aarch64/aarch64.h (ASM_FPRINTF_EXTENSIONS): Remove. + -+ PR target/54892 -+ * config/arm/arm.c (arm_expand_compare_and_swap): Use SImode to make -+ sure the mode is correct when falling through from above cases. ++2013-01-08 Tejas Belagod + -+2012-10-19 Alan Modra ++ * config/aarch64/aarch64-simd.md (vec_init): New. ++ * config/aarch64/aarch64-protos.h (aarch64_expand_vector_init): Declare. ++ * config/aarch64/aarch64.c (aarch64_simd_dup_constant, ++ aarch64_simd_make_constant, aarch64_expand_vector_init): New. + -+ * configure.ac (HAVE_LD_NO_DOT_SYMS): Set if using gold. -+ (HAVE_LD_LARGE_TOC): Likewise. -+ * configure: Regenerate. ++2013-01-08 Tejas Belagod + -+2012-10-19 Alan Modra ++ * config/aarch64/aarch64-simd.md (aarch64_simd_vec_mult_lo_, ++ aarch64_simd_vec_mult_hi_): Separate instruction and operand ++ with tab instead of space. + -+ * config/rs6000/predicates.md (splat_input_operand): Don't call -+ input_operand for MEMs. Instead check for volatile and call -+ memory_address_addr_space_p with modified mode. ++2013-01-08 James Greenhalgh + -+2012-10-17 Matthew Gretton-Dann ++ Backport from mainline. ++ 2013-01-07 James Greenhalgh + -+ Backported from mainline -+ 2012-07-23 Ulrich Weigand ++ * config/aarch64/arm_neon.h (vld1_dup_*): Make argument const. ++ (vld1q_dup_*): Likewise. ++ (vld1_*): Likewise. ++ (vld1q_*): Likewise. ++ (vld1_lane_*): Likewise. ++ (vld1q_lane_*): Likewise. + -+ * config/arm/arm.c (arm_reorg): Ensure all insns are split. ++2013-01-08 James Greenhalgh + -+2012-10-16 Eric Botcazou ++ Backport from mainline. ++ 2013-01-07 James Greenhalgh + -+ PR rtl-optimization/54870 -+ * tree.h (TREE_ADDRESSABLE): Document special usage on SSA_NAME. -+ * cfgexpand.c (update_alias_info_with_stack_vars ): Set it on the -+ SSA_NAME pointer that points to a partition if there is at least -+ one variable with it set in the partition. -+ * dse.c (local_variable_can_escape): New predicate. -+ (can_escape): Call it. -+ * gimplify.c (mark_addressable): If this is a partitioned decl, also -+ mark the SSA_NAME pointer that points to a partition. ++ * config/aarch64/aarch64-protos.h ++ (aarch64_const_double_zero_rtx_p): Rename to... ++ (aarch64_float_const_zero_rtx_p): ...this. ++ (aarch64_float_const_representable_p): New. ++ (aarch64_output_simd_mov_immediate): Likewise. ++ * config/aarch64/aarch64-simd.md (*aarch64_simd_mov): Refactor ++ move immediate case. ++ * config/aarch64/aarch64.c ++ (aarch64_const_double_zero_rtx_p): Rename to... ++ (aarch64_float_const_zero_rtx_p): ...this. ++ (aarch64_print_operand): Allow printing of new constants. ++ (aarch64_valid_floating_const): New. ++ (aarch64_legitimate_constant_p): Check for valid floating-point ++ constants. ++ (aarch64_simd_valid_immediate): Likewise. ++ (aarch64_vect_float_const_representable_p): New. ++ (aarch64_float_const_representable_p): Likewise. ++ (aarch64_simd_imm_zero_p): Also allow for floating-point 0.0. ++ (aarch64_output_simd_mov_immediate): New. ++ * config/aarch64/aarch64.md (*movsf_aarch64): Add new alternative. ++ (*movdf_aarch64): Likewise. ++ * config/aarch64/constraints.md (Ufc): New. ++ (Y): call aarch64_float_const_zero_rtx. ++ * config/aarch64/predicates.md (aarch64_fp_compare_operand): New. ++ ++2013-01-07 Tejas Belagod ++ ++ * config/aarch64/arm_neon.h (vmovn_high_is16, vmovn_high_s32, ++ vmovn_high_s64, vmovn_high_u16, vmovn_high_u32, vmovn_high_u64, ++ vqmovn_high_s16, vqmovn_high_s32, vqmovn_high_s64, vqmovn_high_u16, ++ vqmovn_high_u32, vqmovn_high_u64, vqmovun_high_s16, vqmovun_high_s32, ++ vqmovun_high_s64): Fix source operand number and update copyright. ++ ++2013-01-02 James Greenhalgh ++ ++ Backport from mainline. ++ 2012-12-18 James Greenhalgh ++ ++ * config/aarch64/aarch64.c (aarch64_simd_attr_length_move): ++ Remove unused variables. ++ (aarch64_split_compare_and_swap): Likewise. + -+2012-10-16 Andrey Belevantsev ++2012-12-20 Ian Bolton + + Backport from mainline -+ 2012-08-09 Andrey Belevantsev ++ 2012-12-20 Ian Bolton + -+ PR rtl-optimization/53701 -+ * sel-sched.c (vinsn_vec_has_expr_p): Clarify function comment. -+ rocess not only expr's vinsns but all old vinsns from expr's -+ istory of changes. ++ * gcc/config/aarch64/aarch64.md ++ (*addsi3_aarch64_uxtw): New pattern. ++ (*addsi3_compare0_uxtw): New pattern. ++ (*add__si_uxtw): New pattern. ++ (*add__si_uxtw): New pattern. ++ (*add__shft_si_uxtw): New pattern. ++ (*add__mult_si_uxtw): New pattern. ++ (*add_si_multp2_uxtw): New pattern. ++ (*addsi3_carryin_uxtw): New pattern. ++ (*addsi3_carryin_alt1_uxtw): New pattern. ++ (*addsi3_carryin_alt2_uxtw): New pattern. ++ (*addsi3_carryin_alt3_uxtw): New pattern. ++ (*add_uxtsi_multp2_uxtw): New pattern. ++ (*subsi3_uxtw): New pattern. ++ (*subsi3_compare0_uxtw): New pattern. ++ (*sub__si_uxtw): New pattern. ++ (*sub_mul_imm_si_uxtw): New pattern. ++ (*sub__si_uxtw): New pattern. ++ (*sub__shft_si_uxtw): New pattern. ++ (*sub_si_multp2_uxtw): New pattern. ++ (*sub_uxtsi_multp2_uxtw): New pattern. ++ (*negsi2_uxtw): New pattern. ++ (*negsi2_compare0_uxtw): New pattern. ++ (*neg__si2_uxtw): New pattern. ++ (*neg_mul_imm_si2_uxtw): New pattern. ++ (*mulsi3_uxtw): New pattern. ++ (*maddsi_uxtw): New pattern. ++ (*msubsi_uxtw): New pattern. ++ (*mulsi_neg_uxtw): New pattern. ++ (*divsi3_uxtw): New pattern. ++ ++2012-12-17 James Greenhalgh ++ ++ Backport from mainline. ++ 2012-12-17 James Greenhalgh ++ Tejas Belagod + -+2012-10-16 Andrey Belevantsev ++ * config/aarch64/aarch64.c ++ (aarch64_autovectorize_vector_sizes): New. ++ (TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES): Define. + -+ Backport from mainline -+ 2012-07-31 Andrey Belevantsev -+ PR target/53975 ++2012-12-06 James Greenhalgh + -+ * sel-sched-ir.c (has_dependence_note_reg_use): Clarify comment. -+ Revert -+ 2011-08-04 Sergey Grechanik -+ * sel-sched-ir.c (has_dependence_note_reg_use): Call ds_full_merge -+ only if producer writes to the register given by regno. ++ Backport from mainline. ++ 2012-12-05 James Greenhalgh + -+2012-09-15 Uros Bizjak ++ * config/aarch64/aarch64-simd-builtins.def: Add new builtins. ++ * config/aarch64/aarch64-simd.md (simd_type): Add uzp. ++ (aarch64_): New. ++ * config/aarch64/aarch64.c (aarch64_evpc_trn): New. ++ (aarch64_evpc_uzp): Likewise. ++ (aarch64_evpc_zip): Likewise. ++ (aarch64_expand_vec_perm_const_1): Check for trn, zip, uzp patterns. ++ * config/aarch64/iterators.md (unspec): Add neccessary unspecs. ++ (PERMUTE): New. ++ (perm_insn): Likewise. ++ (perm_hilo): Likewise. ++ ++2012-12-06 James Greenhalgh ++ ++ Backport from mainline. ++ 2012-12-05 James Greenhalgh ++ ++ * config/aarch64/aarch64-protos.h ++ (aarch64_split_combinev16qi): New. ++ (aarch64_expand_vec_perm): Likewise. ++ (aarch64_expand_vec_perm_const): Likewise. ++ * config/aarch64/aarch64-simd.md (vec_perm_const): New. ++ (vec_perm): Likewise. ++ (aarch64_tbl1): Likewise. ++ (aarch64_tbl2v16qi): Likewise. ++ (aarch64_combinev16qi): New. ++ * config/aarch64/aarch64.c ++ (aarch64_vectorize_vec_perm_const_ok): New. ++ (aarch64_split_combinev16qi): Likewise. ++ (MAX_VECT_LEN): Define. ++ (expand_vec_perm_d): New. ++ (aarch64_expand_vec_perm_1): Likewise. ++ (aarch64_expand_vec_perm): Likewise. ++ (aarch64_evpc_tbl): Likewise. ++ (aarch64_expand_vec_perm_const_1): Likewise. ++ (aarch64_expand_vec_perm_const): Likewise. ++ (aarch64_vectorize_vec_perm_const_ok): Likewise. ++ (TARGET_VECTORIZE_VEC_PERM_CONST_OK): Likewise. ++ * config/aarch64/iterators.md ++ (unspec): Add UNSPEC_TBL, UNSPEC_CONCAT. ++ (V_cmp_result): Add mapping for V2DF. ++ ++2012-12-06 Yufeng Zhang + + Backport from mainline -+ 2012-10-15 Uros Bizjak ++ 2012-12-05 Yufeng Zhang ++ * config/aarch64/aarch64.c (aarch64_simd_mangle_map_entry): New ++ typedef. ++ (aarch64_simd_mangle_map): New table. ++ (aarch64_mangle_type): Locate and return the mangled name for ++ a given AdvSIMD vector type. ++ ++2012-12-05 James Greenhalgh ++ ++ Backport from mainline. ++ 2012-12-05 James Greenhalgh ++ ++ * config/aarch64/aarch64-builtins.c ++ (aarch64_builtin_vectorized_function): New. ++ * config/aarch64/aarch64-protos.h ++ (aarch64_builtin_vectorized_function): Declare. ++ * config/aarch64/aarch64-simd-builtins.def (frintz, frintp): Add. ++ (frintm, frinti, frintx, frinta, fcvtzs, fcvtzu): Likewise. ++ (fcvtas, fcvtau, fcvtps, fcvtpu, fcvtms, fcvtmu): Likewise. ++ * config/aarch64/aarch64-simd.md ++ (aarch64_frint_): New. ++ (2): Likewise. ++ (aarch64_fcvt): Likewise. ++ (l2): Likewise. ++ * config/aarch64/aarch64.c (TARGET_VECTORIZE_BUILTINS): Define. ++ (TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Likewise. ++ * config/aarch64/aarch64.md ++ (btrunc2, ceil2, floor2) ++ (round2, rint2, nearbyint2): Consolidate as... ++ (2): ...this. ++ (lceil2, lfloor2) ++ (lround2) ++ (lrint2): Consolidate as... ++ (l2): ... this. ++ * config/aarch64/iterators.md (fcvt_target): New. ++ (FCVT_TARGET): Likewise. ++ (FRINT): Likewise. ++ (FCVT): Likewise. ++ (frint_pattern): Likewise. ++ (frint_suffix): Likewise. ++ (fcvt_pattern): Likewise. + -+ * config/i386/sse.md (UNSPEC_MOVU): Remove. -+ (UNSPEC_LOADU): New. -+ (UNSPEC_STOREU): Ditto. -+ (_movu): Split to ... -+ (_loadu): ... this and ... -+ (_storeu) ... this. -+ (_movdqu): Split to ... -+ (_loaddqu): ... this and ... -+ (_storedqu): ... this. -+ (*sse4_2_pcmpestr_unaligned): Update. -+ (*sse4_2_pcmpistr_unaligned): Ditto. ++2012-12-05 Yufeng Zhang + -+ * config/i386/i386.c (ix86_avx256_split_vector_move_misalign): Use -+ gen_avx_load{dqu,ups,upd}256 to load from unaligned memory and -+ gen_avx_store{dqu,ups,upd}256 to store to unaligned memory. -+ (ix86_expand_vector_move_misalign): Use gen_sse_loadups or -+ gen_sse2_load{dqu,upd} to load from unaligned memory and -+ gen_sse_loadups or gen_sse2_store{dqu,upd}256 to store to -+ unaligned memory. -+ (struct builtin_description bdesc_spec) : -+ Use CODE_FOR_sse_loadups. -+ : Use CODE_FOR_sse2_loadupd. -+ : Use CODE_FOR_sse2_loaddqu. -+ : Use CODE_FOR_sse_storeups. -+ : Use CODE_FOR_sse2_storeupd. -+ : Use CODE_FOR_sse2_storedqu. -+ : Use CODE_FOR_avx_loadups256. -+ : Use CODE_FOR_avx_loadupd256. -+ : Use CODE_FOR_avx_loaddqu256. -+ : Use CODE_FOR_avx_storeups256. -+ : Use CODE_FOR_avx_storeupd256. -+ : Use CODE_FOR_avx_storedqu256. ++ Backport from mainline ++ 2012-12-05 Yufeng Zhang + -+2012-10-15 Steven Bosscher ++ * config/aarch64/aarch64.c (aarch64_mangle_type): New function. ++ (TARGET_MANGLE_TYPE): Define. + -+ Backport from trunk (r190222): ++2012-12-04 Marcus Shawcroft + -+ PR tree-optimization/54146 -+ * ifcvt.c: Include pointer-set.h. -+ (cond_move_process_if_block): Change type of then_regs and -+ else_regs from alloca'd array to pointer_sets. -+ (check_cond_move_block): Update for this change. -+ (cond_move_convert_if_block): Likewise. -+ * Makefile.in: Fix dependencies for ifcvt.o. ++ Backport from mainline ++ 2012-12-04 Marcus Shawcroft + -+2012-10-15 Richard Guenther ++ * config/aarch64/aarch64.c (aarch64_build_builtin_va_list): Set ++ TYPE_STUB_DECL. + -+ PR tree-optimization/54920 -+ * tree-ssa-pre.c (create_expression_by_pieces): Properly -+ allocate temporary storage for all NARY elements. ++2012-12-04 Tejas Belagod + -+2012-10-08 Georg-Johann Lay ++ * config/aarch64/aarch64.c (aarch64_simd_vector_alignment, ++ aarch64_simd_vector_alignment_reachable): New. ++ (TARGET_VECTOR_ALIGNMENT, TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE): ++ Define. ++ ++2012-12-03 James Greenhalgh ++ ++ Backport from mainline. ++ 2012-10-30 James Greenhalgh ++ Tejas Belagod ++ ++ * config/aarch64/aarch64-simd.md ++ (aarch64_simd_bsl_internal): New pattern. ++ (aarch64_simd_bsl): Likewise. ++ (aarch64_vcond_internal): Likewise. ++ (vcondu): Likewise. ++ (vcond): Likewise. ++ * config/aarch64/iterators.md (UNSPEC_BSL): Add to define_constants. ++ ++2012-12-03 Sofiane Naci ++ ++ * config/aarch64/aarch64.c (aarch64_build_constant): Update prototype. ++ Call emit_move_insn instead of printing movi/movn/movz instructions. ++ Call gen_insv_immdi instead of printing movk instruction. ++ (aarch64_add_constant): Update prototype. ++ Generate RTL instead of printing add/sub instructions. ++ (aarch64_output_mi_thunk): Update calls to aarch64_build_constant ++ and aarch64_add_constant. ++ ++2012-11-29 James Greenhalgh ++ ++ Backport from mainline. ++ 2012-11-26 James Greenhalgh ++ ++ * config/aarch64/aarch64-builtins.c (aarch64_builtin_decls): New. ++ (aarch64_init_simd_builtins): Store declaration after builtin ++ initialisation. ++ (aarch64_init_builtins): Likewise. ++ (aarch64_builtin_decl): New. ++ * config/aarch64/aarch64-protos.h (aarch64_builtin_decl): New. ++ * config/aarch64/aarch64.c (TARGET_BUILTIN_DECL): Define. ++ ++2012-11-29 James Greenhalgh ++ ++ Backport from mainline. ++ 2012-11-20 James Greenhalgh ++ Tejas Belagod ++ ++ * config/aarch64/aarch64-builtins.c ++ (aarch64_simd_builtin_type_bits): Rename to... ++ (aarch64_simd_builtin_type_mode): ...this, make sequential. ++ (aarch64_simd_builtin_datum): Refactor members. ++ (VAR1, VAR2, ..., VAR12): Update accordingly. ++ (aarch64_simd_builtin_data): Include from aarch64-simd-builtins.def. ++ (aarch64_builtins): Update accordingly. ++ (init_aarch64_simd_builtins): Refactor, rename to... ++ (aarch64_init_simd_builtins): ...this. ++ (aarch64_simd_builtin_compare): Remove. ++ (locate_simd_builtin_icode): Likewise. ++ * config/aarch64/aarch64-protos.h (aarch64_init_builtins): New. ++ (aarch64_expand_builtin): Likewise. ++ (aarch64_load_tp): Likewise. ++ * config/aarch64/aarch64-simd-builtins.def: New file. ++ * config/aarch64/aarch64.c (aarch64_init_builtins): ++ Move to aarch64-builtins.c. ++ (aarch64_expand_builtin): Likewise. ++ (aarch64_load_tp): Remove static designation. ++ * config/aarch64/aarch64.h ++ (aarch64_builtins): Move to aarch64-builtins.c. + -+ PR target/54854 -+ * doc/invoke.texi (AVR Options): Deprecate -mshort-calls. ++2012-11-22 Marcus Shawcroft + -+2012-10-05 Mark Kettenis ++ * doc/md.texi (AArch64 family): Remove Utf. + -+ * config.gcc (*-*-openbsd4.[3-9]|*-*-openbsd[5-9]*): Set -+ default_use_cxa_atexit to yes. ++2012-11-22 Ian Bolton + -+2012-10-05 John David Anglin ++ Backport from mainline ++ 2012-11-22 Ian Bolton + -+ * config/pa/pa.md: Adjust unamed HImode add insn pattern. ++ * config/aarch64/aarch64.md (bswaphi2): New pattern. + -+2012-10-05 Jan Hubicka -+ Jakub Jelinek ++2012-11-21 Marcus Shawcroft + -+ PR tree-optimization/33763 -+ * tree-inline.c (expand_call_inline): Silently ignore always_inline -+ attribute for redefined extern inline functions. ++ * Makefile.in (gengtype-lex.o): Add dependency on $(BCONFIG_H). + -+2012-10-03 H.J. Lu ++2012-11-21 James Greenhalgh + -+ Backported from mainline -+ 2012-10-03 Andrew W. Nosenko ++ * config/aarch64/aarch64.c ++ (aarch64_output_mi_thunk): Use 4.7 API for plus_constant. + -+ * config/i386/driver-i386.c (host_detect_local_cpu): Fix logic -+ in SSE and YMM state support check for -march=native. ++2012-11-20 Sofiane Naci + -+2012-10-03 Alexandre Oliva ++ Backport from mainline ++ 2012-11-20 Sofiane Naci + -+ PR debug/53135 -+ * dwarf2out.c (value_format): Use block4 for dw_val_class_loc -+ when needed. -+ -+2012-10-02 H.J. Lu -+ -+ Backported from mainline -+ 2012-10-02 H.J. Lu -+ -+ PR target/54785 -+ * doc/invoke.texi: Document -mprefer-avx128. -+ -+2012-10-02 H.J. Lu -+ -+ Backported from mainline -+ 2012-10-02 H.J. Lu -+ -+ PR target/54741 -+ * config/i386/driver-i386.c (XCR_XFEATURE_ENABLED_MASK): New. -+ (XSTATE_FP): Likewise. -+ (XSTATE_SSE): Likewise. -+ (XSTATE_YMM): Likewise. -+ (host_detect_local_cpu): Disable AVX, AVX2, FMA, FMA4 and XOP if -+ SSE and YMM states aren't supported. -+ -+2012-10-01 Tom de Vries -+ -+ * var-tracking.c (set_dv_changed): Add an 'inline' function specifier to -+ the prototype. -+ -+2012-10-01 Andreas Krebbel -+ -+ PR target/54746 -+ * config/s390/s390.c (s390_option_override): Add missing break. ++ * config/aarch64/aarch64.md ++ (define_attr "sync_*"): Remove. ++ (define_attr "length"): Update. ++ Include atomics.md. ++ * config/aarch64/aarch64-protos.h ++ (aarch64_expand_compare_and_swap): Add function prototype. ++ (aarch64_split_compare_and_swap): Likewise. ++ (aarch64_split_atomic_op): Likewise. ++ (aarch64_expand_sync): Remove function prototype. ++ (aarch64_output_sync_insn): Likewise. ++ (aarch64_output_sync_lock_release): Likewise. ++ (aarch64_sync_loop_insns): Likewise. ++ (struct aarch64_sync_generator): Remove. ++ (enum aarch64_sync_generator_tag): Likewise. ++ * config/aarch64/aarch64.c ++ (aarch64_legitimize_sync_memory): Remove function. ++ (aarch64_emit): Likewise. ++ (aarch64_insn_count): Likewise. ++ (aarch64_output_asm_insn): Likewise. ++ (aarch64_load_store_suffix): Likewise. ++ (aarch64_output_sync_load): Likewise. ++ (aarch64_output_sync_store): Likewise. ++ (aarch64_output_op2): Likewise. ++ (aarch64_output_op3): Likewise. ++ (aarch64_output_sync_loop): Likewise. ++ (aarch64_get_sync_operand): Likewise. ++ (aarch64_process_output_sync_insn): Likewise. ++ (aarch64_output_sync_insn): Likewise. ++ (aarch64_output_sync_lock_release): Likewise. ++ (aarch64_sync_loop_insns): Likewise. ++ (aarch64_call_generator): Likewise. ++ (aarch64_expand_sync): Likewise. ++ (* emit_f): Remove variable. ++ (aarch64_insn_count): Likewise. ++ (FETCH_SYNC_OPERAND): Likewise. ++ (aarch64_emit_load_exclusive): New function. ++ (aarch64_emit_store_exclusive): Likewise. ++ (aarch64_emit_unlikely_jump): Likewise. ++ (aarch64_expand_compare_and_swap): Likewise. ++ (aarch64_split_compare_and_swap): Likewise. ++ (aarch64_split_atomic_op): Likewise. ++ * config/aarch64/iterators.md ++ (atomic_sfx): New mode attribute. ++ (atomic_optab): New code attribute. ++ (atomic_op_operand): Likewise. ++ (atomic_op_str): Likewise. ++ (syncop): Rename to atomic_op. ++ * config/aarch64/sync.md: Delete. ++ * config/aarch64/atomics.md: New file. + -+2012-09-29 Andreas Tobler ++2012-11-19 Sofiane Naci + + Backport from mainline -+ 2012-09-29 Andreas Tobler ++ 2012-11-19 Sofiane Naci + -+ * config.gcc: Replace 'host' with 'target' when configuring for -+ powerpc64*-*-freebsd. ++ * config/aarch64/aarch64.c ++ (aarch64_output_mi_thunk): Refactor to generate RTL patterns. + -+2012-09-28 Meador Inge ++2012-11-13 Ian Bolton + + Backport from mainline -+ 2012-09-27 Meador Inge -+ -+ * gcc-ar.c (main): Handle the returning of the sub-process error -+ code correctly. ++ 2012-11-12 Ian Bolton + -+2012-09-28 Georg-Johann Lay ++ * config/aarch64/aarch64.md (cmov_insn): Emit CSINC when ++ one of the alternatives is constant 1. ++ * config/aarch64/constraints.md: New constraint. ++ * config/aarch64/predicates.md: Rename predicate ++ aarch64_reg_zero_or_m1 to aarch64_reg_zero_or_m1_or_1. + -+ Backport from 2012-09-28 trunk r191821. -+ * config/avr/avr.c (avr_pgm_check_var_decl): Fix non-error diagnostic. ++2012-11-13 Ian Bolton + -+2012-09-27 Jakub Jelinek ++ Backport from mainline ++ 2012-11-12 Ian Bolton ++ ++ * config/aarch64/aarch64.md (*compare_neg): New pattern. + -+ PR target/54703 -+ * simplify-rtx.c (simplify_binary_operation_1): Perform -+ (x - (x & y)) -> (x & ~y) optimization only for integral modes. ++2012-11-08 Yufeng Zhang + -+2012-09-24 Eric Botcazou ++ Revert: ++ 2012-11-07 Yufeng Zhang + -+ * tree-streamer-in.c (unpack_ts_type_common_value_fields): Stream in -+ TYPE_NONALIASED_COMPONENT flag. -+ * tree-streamer-out.c (pack_ts_type_common_value_fields): Stream out -+ TYPE_NONALIASED_COMPONENT flag. ++ * config/aarch64/aarch64.c (aarch64_expand_prologue): add the missing ++ argument 'Pmode' to the 'plus_constant' call. + -+2012-09-21 Richard Guenther ++2012-11-07 Yufeng Zhang + -+ PR middle-end/54638 -+ Backport from mainline -+ 2012-04-19 Richard Guenther ++ * config/aarch64/aarch64.c (aarch64_expand_prologue): add the missing ++ argument 'Pmode' to the 'plus_constant' call. + -+ * ira-int.h (ira_allocno_object_iter_cond): Avoid out-of-bound -+ array access. ++2012-11-07 Yufeng Zhang + -+2012-09-20 Joseph Myers ++ * config/aarch64/aarch64.c (aarch64_expand_prologue): For the ++ load-pair with writeback instruction, replace ++ aarch64_set_frame_expr with add_reg_note (REG_CFA_ADJUST_CFA); ++ add new local variable 'cfa_reg' and use it. + -+ PR c/54552 -+ * c-typeck.c (c_cast_expr): When casting to a type requiring -+ C_MAYBE_CONST_EXPR to be created, pass the inner expression to -+ c_fully_fold first. -+ -+2012-09-20 Joseph Myers -+ -+ PR c/54103 -+ * c-typeck.c (build_unary_op): Pass original argument of -+ TRUTH_NOT_EXPR to c_objc_common_truthvalue_conversion, then remove -+ any C_MAYBE_CONST_EXPR, if it has integer operands. -+ (build_binary_op): Pass original arguments of TRUTH_ANDIF_EXPR, -+ TRUTH_ORIF_EXPR, TRUTH_AND_EXPR, TRUTH_OR_EXPR and TRUTH_XOR_EXPR -+ to c_objc_common_truthvalue_conversion, then remove any -+ C_MAYBE_CONST_EXPR, if they have integer operands. Use -+ c_objc_common_truthvalue_conversion not -+ c_common_truthvalue_conversion. -+ (c_objc_common_truthvalue_conversion): Build NE_EXPR directly and -+ call note_integer_operands for arguments with integer operands -+ that are not integer constants. -+ -+2012-09-20 Jakub Jelinek -+ -+ Backported from mainline -+ 2012-09-17 Jakub Jelinek -+ -+ PR tree-optimization/54563 -+ * tree-ssa-math-opts.c (execute_cse_sincos): Call -+ gimple_purge_dead_eh_edges if last call has been changed. -+ -+ 2012-09-14 Jakub Jelinek -+ -+ PR target/54564 -+ * config/i386/sse.md (fmai_vmfmadd_): Use (match_dup 1) -+ instead of (match_dup 0) as second argument to vec_merge. -+ (*fmai_fmadd_, *fmai_fmsub_): Likewise. -+ Remove third alternative. -+ (*fmai_fnmadd_, *fmai_fnmsub_): Likewise. Negate -+ operand 2 instead of operand 1, but put it as first argument -+ of fma. -+ * config/i386/fmaintrin.h (_mm_fnmadd_sd, _mm_fnmadd_ss, -+ _mm_fnmsub_sd, _mm_fnmsub_ss): Negate the second argument instead -+ of the first. -+ - 2012-09-20 Release Manager - - * GCC 4.7.2 released. -@@ -7,12 +468,12 @@ - Backport from mainline - 2012-09-07 Andi Kleen - -- * gcc/lto-streamer.h (res_pair): Add. -- (lto_file_decl_data): Replace resolutions with respairs. -- Add max_index. -- * gcc/lto/lto.c (lto_resolution_read): Remove max_index. Add rp. -- Initialize respairs. -- (lto_file_finalize): Set up resolutions vector lazily from respairs. -+ * gcc/lto-streamer.h (res_pair): Add. -+ (lto_file_decl_data): Replace resolutions with respairs. -+ Add max_index. -+ * gcc/lto/lto.c (lto_resolution_read): Remove max_index. Add rp. -+ Initialize respairs. -+ (lto_file_finalize): Set up resolutions vector lazily from respairs. - - 2012-09-14 Walter Lee - -@@ -78,7 +539,7 @@ - - 2012-09-12 Christian Bruel - -- * config/sh/newlib.h (NO_IMPLICIT_EXTERN_C): Define. -+ * config/sh/newlib.h (NO_IMPLICIT_EXTERN_C): Define. - - 2012-09-12 Jakub Jelinek - ---- a/src/gcc/ChangeLog.aarch64 -+++ b/src/gcc/ChangeLog.aarch64 -@@ -0,0 +1,495 @@ +2012-10-17 Sofiane Naci + + * config/aarch64/aarch64.md (3): Update constraint @@ -3144,7 +4146,7 @@ return x; --- a/src/gcc/common/config/aarch64/aarch64-common.c +++ b/src/gcc/common/config/aarch64/aarch64-common.c -@@ -0,0 +1,77 @@ +@@ -0,0 +1,88 @@ +/* Common hooks for AArch64. + Copyright (C) 2012 Free Software Foundation, Inc. + Contributed by ARM Ltd. @@ -3183,6 +4185,17 @@ +#undef TARGET_HANDLE_OPTION +#define TARGET_HANDLE_OPTION aarch64_handle_option + ++#undef TARGET_OPTION_OPTIMIZATION_TABLE ++#define TARGET_OPTION_OPTIMIZATION_TABLE aarch_option_optimization_table ++ ++/* Set default optimization options. */ ++static const struct default_options aarch_option_optimization_table[] = ++ { ++ /* Enable section anchors by default at -O1 or higher. */ ++ { OPT_LEVELS_1_PLUS, OPT_fsection_anchors, NULL, 1 }, ++ { OPT_LEVELS_NONE, 0, NULL, 0 } ++ }; ++ +/* Implement TARGET_HANDLE_OPTION. + This function handles the target specific options for CPU/target selection. + @@ -3236,45 +4249,9 @@ /* Enable section anchors by default at -O1 or higher. */ { OPT_LEVELS_1_PLUS, OPT_fsection_anchors, NULL, 1 }, { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, ---- a/src/gcc/common/config/m68k/m68k-common.c -+++ b/src/gcc/common/config/m68k/m68k-common.c -@@ -1,6 +1,6 @@ - /* Common hooks for Motorola 68000 family. - Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, -- 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 -+ 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012 - Free Software Foundation, Inc. - - This file is part of GCC. -@@ -33,7 +33,7 @@ - - static bool - m68k_handle_option (struct gcc_options *opts, -- struct gcc_options *opts_set ATTRIBUTE_UNUSED, -+ struct gcc_options *opts_set, - const struct cl_decoded_option *decoded, - location_t loc) - { -@@ -45,12 +45,16 @@ - { - case OPT_m68020_40: - opts->x_m68k_tune_option = u68020_40; -+ opts_set->x_m68k_tune_option = (enum uarch_type) 1; - opts->x_m68k_cpu_option = m68020; -+ opts_set->x_m68k_cpu_option = (enum target_device) 1; - return true; - - case OPT_m68020_60: - opts->x_m68k_tune_option = u68020_60; -+ opts_set->x_m68k_tune_option = (enum uarch_type) 1; - opts->x_m68k_cpu_option = m68020; -+ opts_set->x_m68k_cpu_option = (enum target_device) 1; - return true; - - case OPT_mshared_library_id_: --- a/src/gcc/common.opt +++ b/src/gcc/common.opt -@@ -1655,6 +1655,19 @@ +@@ -1658,6 +1658,19 @@ Common Report Var(flag_sched_pressure) Init(0) Optimization Enable register pressure sensitive insn scheduling @@ -3294,7 +4271,22 @@ fsched-spec Common Report Var(flag_schedule_speculative) Init(1) Optimization Allow speculative motion of non-loads -@@ -2010,6 +2023,10 @@ +@@ -1929,6 +1942,14 @@ + Common Report Var(flag_tree_ch) Optimization + Enable loop header copying on trees + ++ftree-coalesce-inlined-vars ++Common Report Var(flag_ssa_coalesce_vars,1) Init(2) RejectNegative Optimization ++Enable coalescing of copy-related user variables that are inlined ++ ++ftree-coalesce-vars ++Common Report Var(flag_ssa_coalesce_vars,2) Optimization ++Enable coalescing of all copy-related user variables ++ + ftree-copyrename + Common Report Var(flag_tree_copyrename) Optimization + Replace SSA temporaries with better names in copies +@@ -2013,6 +2034,10 @@ Common Report Var(flag_tree_pre) Optimization Enable SSA-PRE optimization on trees @@ -3339,7 +4331,7 @@ +AARCH64_ARCH("armv8-a", generic, 8, AARCH64_FL_FOR_ARCH8) --- a/src/gcc/config/aarch64/aarch64-builtins.c +++ b/src/gcc/config/aarch64/aarch64-builtins.c -@@ -0,0 +1,1320 @@ +@@ -0,0 +1,1307 @@ +/* Builtins' description for AArch64 SIMD architecture. + Copyright (C) 2011, 2012 Free Software Foundation, Inc. + Contributed by ARM Ltd. @@ -3373,27 +4365,28 @@ +#include "diagnostic-core.h" +#include "optabs.h" + -+enum aarch64_simd_builtin_type_bits ++enum aarch64_simd_builtin_type_mode +{ -+ T_V8QI = 0x0001, -+ T_V4HI = 0x0002, -+ T_V2SI = 0x0004, -+ T_V2SF = 0x0008, -+ T_DI = 0x0010, -+ T_DF = 0x0020, -+ T_V16QI = 0x0040, -+ T_V8HI = 0x0080, -+ T_V4SI = 0x0100, -+ T_V4SF = 0x0200, -+ T_V2DI = 0x0400, -+ T_V2DF = 0x0800, -+ T_TI = 0x1000, -+ T_EI = 0x2000, -+ T_OI = 0x4000, -+ T_XI = 0x8000, -+ T_SI = 0x10000, -+ T_HI = 0x20000, -+ T_QI = 0x40000 ++ T_V8QI, ++ T_V4HI, ++ T_V2SI, ++ T_V2SF, ++ T_DI, ++ T_DF, ++ T_V16QI, ++ T_V8HI, ++ T_V4SI, ++ T_V4SF, ++ T_V2DI, ++ T_V2DF, ++ T_TI, ++ T_EI, ++ T_OI, ++ T_XI, ++ T_SI, ++ T_HI, ++ T_QI, ++ T_MAX +}; + +#define v8qi_UP T_V8QI @@ -3418,8 +4411,6 @@ + +#define UP(X) X##_UP + -+#define T_MAX 19 -+ +typedef enum +{ + AARCH64_SIMD_BINOP, @@ -3466,253 +4457,175 @@ +{ + const char *name; + const aarch64_simd_itype itype; -+ const int bits; -+ const enum insn_code codes[T_MAX]; -+ const unsigned int num_vars; -+ unsigned int base_fcode; ++ enum aarch64_simd_builtin_type_mode mode; ++ const enum insn_code code; ++ unsigned int fcode; +} aarch64_simd_builtin_datum; + +#define CF(N, X) CODE_FOR_aarch64_##N##X + +#define VAR1(T, N, A) \ -+ #N, AARCH64_SIMD_##T, UP (A), { CF (N, A) }, 1, 0 ++ {#N, AARCH64_SIMD_##T, UP (A), CF (N, A), 0}, +#define VAR2(T, N, A, B) \ -+ #N, AARCH64_SIMD_##T, UP (A) | UP (B), { CF (N, A), CF (N, B) }, 2, 0 ++ VAR1 (T, N, A) \ ++ VAR1 (T, N, B) +#define VAR3(T, N, A, B, C) \ -+ #N, AARCH64_SIMD_##T, UP (A) | UP (B) | UP (C), \ -+ { CF (N, A), CF (N, B), CF (N, C) }, 3, 0 ++ VAR2 (T, N, A, B) \ ++ VAR1 (T, N, C) +#define VAR4(T, N, A, B, C, D) \ -+ #N, AARCH64_SIMD_##T, UP (A) | UP (B) | UP (C) | UP (D), \ -+ { CF (N, A), CF (N, B), CF (N, C), CF (N, D) }, 4, 0 ++ VAR3 (T, N, A, B, C) \ ++ VAR1 (T, N, D) +#define VAR5(T, N, A, B, C, D, E) \ -+ #N, AARCH64_SIMD_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E), \ -+ { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E) }, 5, 0 ++ VAR4 (T, N, A, B, C, D) \ ++ VAR1 (T, N, E) +#define VAR6(T, N, A, B, C, D, E, F) \ -+ #N, AARCH64_SIMD_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F), \ -+ { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F) }, 6, 0 ++ VAR5 (T, N, A, B, C, D, E) \ ++ VAR1 (T, N, F) +#define VAR7(T, N, A, B, C, D, E, F, G) \ -+ #N, AARCH64_SIMD_##T, UP (A) | UP (B) | UP (C) | UP (D) \ -+ | UP (E) | UP (F) | UP (G), \ -+ { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ -+ CF (N, G) }, 7, 0 ++ VAR6 (T, N, A, B, C, D, E, F) \ ++ VAR1 (T, N, G) +#define VAR8(T, N, A, B, C, D, E, F, G, H) \ -+ #N, AARCH64_SIMD_##T, UP (A) | UP (B) | UP (C) | UP (D) \ -+ | UP (E) | UP (F) | UP (G) \ -+ | UP (H), \ -+ { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ -+ CF (N, G), CF (N, H) }, 8, 0 ++ VAR7 (T, N, A, B, C, D, E, F, G) \ ++ VAR1 (T, N, H) +#define VAR9(T, N, A, B, C, D, E, F, G, H, I) \ -+ #N, AARCH64_SIMD_##T, UP (A) | UP (B) | UP (C) | UP (D) \ -+ | UP (E) | UP (F) | UP (G) \ -+ | UP (H) | UP (I), \ -+ { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ -+ CF (N, G), CF (N, H), CF (N, I) }, 9, 0 ++ VAR8 (T, N, A, B, C, D, E, F, G, H) \ ++ VAR1 (T, N, I) +#define VAR10(T, N, A, B, C, D, E, F, G, H, I, J) \ -+ #N, AARCH64_SIMD_##T, UP (A) | UP (B) | UP (C) | UP (D) \ -+ | UP (E) | UP (F) | UP (G) \ -+ | UP (H) | UP (I) | UP (J), \ -+ { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ -+ CF (N, G), CF (N, H), CF (N, I), CF (N, J) }, 10, 0 -+ ++ VAR9 (T, N, A, B, C, D, E, F, G, H, I) \ ++ VAR1 (T, N, J) +#define VAR11(T, N, A, B, C, D, E, F, G, H, I, J, K) \ -+ #N, AARCH64_SIMD_##T, UP (A) | UP (B) | UP (C) | UP (D) \ -+ | UP (E) | UP (F) | UP (G) \ -+ | UP (H) | UP (I) | UP (J) | UP (K), \ -+ { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ -+ CF (N, G), CF (N, H), CF (N, I), CF (N, J), CF (N, K) }, 11, 0 -+ ++ VAR10 (T, N, A, B, C, D, E, F, G, H, I, J) \ ++ VAR1 (T, N, K) +#define VAR12(T, N, A, B, C, D, E, F, G, H, I, J, K, L) \ -+ #N, AARCH64_SIMD_##T, UP (A) | UP (B) | UP (C) | UP (D) \ -+ | UP (E) | UP (F) | UP (G) \ -+ | UP (H) | UP (I) | UP (J) | UP (K) | UP (L), \ -+ { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ -+ CF (N, G), CF (N, H), CF (N, I), CF (N, J), CF (N, K), CF (N, L) }, 12, 0 -+ -+ -+/* The mode entries in the following table correspond to the "key" type of the -+ instruction variant, i.e. equivalent to that which would be specified after -+ the assembler mnemonic, which usually refers to the last vector operand. -+ (Signed/unsigned/polynomial types are not differentiated between though, and -+ are all mapped onto the same mode for a given element size.) The modes -+ listed per instruction should be the same as those defined for that -+ instruction's pattern in aarch64_simd.md. -+ WARNING: Variants should be listed in the same increasing order as -+ aarch64_simd_builtin_type_bits. */ ++ VAR11 (T, N, A, B, C, D, E, F, G, H, I, J, K) \ ++ VAR1 (T, N, L) ++ ++/* BUILTIN_ macros should expand to cover the same range of ++ modes as is given for each define_mode_iterator in ++ config/aarch64/iterators.md. */ ++ ++#define BUILTIN_DX(T, N) \ ++ VAR2 (T, N, di, df) ++#define BUILTIN_SDQ_I(T, N) \ ++ VAR4 (T, N, qi, hi, si, di) ++#define BUILTIN_SD_HSI(T, N) \ ++ VAR2 (T, N, hi, si) ++#define BUILTIN_V2F(T, N) \ ++ VAR2 (T, N, v2sf, v2df) ++#define BUILTIN_VALL(T, N) \ ++ VAR10 (T, N, v8qi, v16qi, v4hi, v8hi, v2si, v4si, v2di, v2sf, v4sf, v2df) ++#define BUILTIN_VB(T, N) \ ++ VAR2 (T, N, v8qi, v16qi) ++#define BUILTIN_VD(T, N) \ ++ VAR4 (T, N, v8qi, v4hi, v2si, v2sf) ++#define BUILTIN_VDC(T, N) \ ++ VAR6 (T, N, v8qi, v4hi, v2si, v2sf, di, df) ++#define BUILTIN_VDIC(T, N) \ ++ VAR3 (T, N, v8qi, v4hi, v2si) ++#define BUILTIN_VDN(T, N) \ ++ VAR3 (T, N, v4hi, v2si, di) ++#define BUILTIN_VDQ(T, N) \ ++ VAR7 (T, N, v8qi, v16qi, v4hi, v8hi, v2si, v4si, v2di) ++#define BUILTIN_VDQF(T, N) \ ++ VAR3 (T, N, v2sf, v4sf, v2df) ++#define BUILTIN_VDQHS(T, N) \ ++ VAR4 (T, N, v4hi, v8hi, v2si, v4si) ++#define BUILTIN_VDQIF(T, N) \ ++ VAR9 (T, N, v8qi, v16qi, v4hi, v8hi, v2si, v4si, v2sf, v4sf, v2df) ++#define BUILTIN_VDQM(T, N) \ ++ VAR6 (T, N, v8qi, v16qi, v4hi, v8hi, v2si, v4si) ++#define BUILTIN_VDQV(T, N) \ ++ VAR5 (T, N, v8qi, v16qi, v4hi, v8hi, v4si) ++#define BUILTIN_VDQ_BHSI(T, N) \ ++ VAR6 (T, N, v8qi, v16qi, v4hi, v8hi, v2si, v4si) ++#define BUILTIN_VDQ_I(T, N) \ ++ VAR7 (T, N, v8qi, v16qi, v4hi, v8hi, v2si, v4si, v2di) ++#define BUILTIN_VDW(T, N) \ ++ VAR3 (T, N, v8qi, v4hi, v2si) ++#define BUILTIN_VD_BHSI(T, N) \ ++ VAR3 (T, N, v8qi, v4hi, v2si) ++#define BUILTIN_VD_HSI(T, N) \ ++ VAR2 (T, N, v4hi, v2si) ++#define BUILTIN_VD_RE(T, N) \ ++ VAR6 (T, N, v8qi, v4hi, v2si, v2sf, di, df) ++#define BUILTIN_VQ(T, N) \ ++ VAR6 (T, N, v16qi, v8hi, v4si, v2di, v4sf, v2df) ++#define BUILTIN_VQN(T, N) \ ++ VAR3 (T, N, v8hi, v4si, v2di) ++#define BUILTIN_VQW(T, N) \ ++ VAR3 (T, N, v16qi, v8hi, v4si) ++#define BUILTIN_VQ_HSI(T, N) \ ++ VAR2 (T, N, v8hi, v4si) ++#define BUILTIN_VQ_S(T, N) \ ++ VAR6 (T, N, v8qi, v16qi, v4hi, v8hi, v2si, v4si) ++#define BUILTIN_VSDQ_HSI(T, N) \ ++ VAR6 (T, N, v4hi, v8hi, v2si, v4si, hi, si) ++#define BUILTIN_VSDQ_I(T, N) \ ++ VAR11 (T, N, v8qi, v16qi, v4hi, v8hi, v2si, v4si, v2di, qi, hi, si, di) ++#define BUILTIN_VSDQ_I_BHSI(T, N) \ ++ VAR10 (T, N, v8qi, v16qi, v4hi, v8hi, v2si, v4si, v2di, qi, hi, si) ++#define BUILTIN_VSDQ_I_DI(T, N) \ ++ VAR8 (T, N, v8qi, v16qi, v4hi, v8hi, v2si, v4si, v2di, di) ++#define BUILTIN_VSD_HSI(T, N) \ ++ VAR4 (T, N, v4hi, v2si, hi, si) ++#define BUILTIN_VSQN_HSDI(T, N) \ ++ VAR6 (T, N, v8hi, v4si, v2di, hi, si, di) ++#define BUILTIN_VSTRUCT(T, N) \ ++ VAR3 (T, N, oi, ci, xi) + +static aarch64_simd_builtin_datum aarch64_simd_builtin_data[] = { -+ {VAR6 (CREATE, create, v8qi, v4hi, v2si, v2sf, di, df)}, -+ {VAR6 (GETLANE, get_lane_signed, -+ v8qi, v4hi, v2si, v16qi, v8hi, v4si)}, -+ {VAR7 (GETLANE, get_lane_unsigned, -+ v8qi, v4hi, v2si, v16qi, v8hi, v4si, v2di)}, -+ {VAR4 (GETLANE, get_lane, v2sf, di, v4sf, v2df)}, -+ {VAR6 (GETLANE, get_dregoi, v8qi, v4hi, v2si, v2sf, di, df)}, -+ {VAR6 (GETLANE, get_qregoi, v16qi, v8hi, v4si, v4sf, v2di, v2df)}, -+ {VAR6 (GETLANE, get_dregci, v8qi, v4hi, v2si, v2sf, di, df)}, -+ {VAR6 (GETLANE, get_qregci, v16qi, v8hi, v4si, v4sf, v2di, v2df)}, -+ {VAR6 (GETLANE, get_dregxi, v8qi, v4hi, v2si, v2sf, di, df)}, -+ {VAR6 (GETLANE, get_qregxi, v16qi, v8hi, v4si, v4sf, v2di, v2df)}, -+ {VAR6 (SETLANE, set_qregoi, v16qi, v8hi, v4si, v4sf, v2di, v2df)}, -+ {VAR6 (SETLANE, set_qregci, v16qi, v8hi, v4si, v4sf, v2di, v2df)}, -+ {VAR6 (SETLANE, set_qregxi, v16qi, v8hi, v4si, v4sf, v2di, v2df)}, -+ -+ {VAR5 (REINTERP, reinterpretv8qi, v8qi, v4hi, v2si, v2sf, di)}, -+ {VAR5 (REINTERP, reinterpretv4hi, v8qi, v4hi, v2si, v2sf, di)}, -+ {VAR5 (REINTERP, reinterpretv2si, v8qi, v4hi, v2si, v2sf, di)}, -+ {VAR5 (REINTERP, reinterpretv2sf, v8qi, v4hi, v2si, v2sf, di)}, -+ {VAR5 (REINTERP, reinterpretdi, v8qi, v4hi, v2si, v2sf, di)}, -+ {VAR6 (REINTERP, reinterpretv16qi, v16qi, v8hi, v4si, v4sf, v2di, v2df)}, -+ {VAR6 (REINTERP, reinterpretv8hi, v16qi, v8hi, v4si, v4sf, v2di, v2df)}, -+ {VAR6 (REINTERP, reinterpretv4si, v16qi, v8hi, v4si, v4sf, v2di, v2df)}, -+ {VAR6 (REINTERP, reinterpretv4sf, v16qi, v8hi, v4si, v4sf, v2di, v2df)}, -+ {VAR6 (REINTERP, reinterpretv2di, v16qi, v8hi, v4si, v4sf, v2di, v2df)}, -+ {VAR6 (COMBINE, combine, v8qi, v4hi, v2si, v2sf, di, df)}, -+ -+ {VAR3 (BINOP, saddl, v8qi, v4hi, v2si)}, -+ {VAR3 (BINOP, uaddl, v8qi, v4hi, v2si)}, -+ {VAR3 (BINOP, saddl2, v16qi, v8hi, v4si)}, -+ {VAR3 (BINOP, uaddl2, v16qi, v8hi, v4si)}, -+ {VAR3 (BINOP, saddw, v8qi, v4hi, v2si)}, -+ {VAR3 (BINOP, uaddw, v8qi, v4hi, v2si)}, -+ {VAR3 (BINOP, saddw2, v16qi, v8hi, v4si)}, -+ {VAR3 (BINOP, uaddw2, v16qi, v8hi, v4si)}, -+ {VAR6 (BINOP, shadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si)}, -+ {VAR6 (BINOP, uhadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si)}, -+ {VAR6 (BINOP, srhadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si)}, -+ {VAR6 (BINOP, urhadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si)}, -+ {VAR3 (BINOP, addhn, v8hi, v4si, v2di)}, -+ {VAR3 (BINOP, raddhn, v8hi, v4si, v2di)}, -+ {VAR3 (TERNOP, addhn2, v8hi, v4si, v2di)}, -+ {VAR3 (TERNOP, raddhn2, v8hi, v4si, v2di)}, -+ {VAR3 (BINOP, ssubl, v8qi, v4hi, v2si)}, -+ {VAR3 (BINOP, usubl, v8qi, v4hi, v2si)}, -+ {VAR3 (BINOP, ssubl2, v16qi, v8hi, v4si) }, -+ {VAR3 (BINOP, usubl2, v16qi, v8hi, v4si) }, -+ {VAR3 (BINOP, ssubw, v8qi, v4hi, v2si) }, -+ {VAR3 (BINOP, usubw, v8qi, v4hi, v2si) }, -+ {VAR3 (BINOP, ssubw2, v16qi, v8hi, v4si) }, -+ {VAR3 (BINOP, usubw2, v16qi, v8hi, v4si) }, -+ {VAR11 (BINOP, sqadd, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di, -+ si, hi, qi)}, -+ {VAR11 (BINOP, uqadd, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di, -+ si, hi, qi)}, -+ {VAR11 (BINOP, sqsub, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di, -+ si, hi, qi)}, -+ {VAR11 (BINOP, uqsub, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di, -+ si, hi, qi)}, -+ {VAR11 (BINOP, suqadd, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di, -+ si, hi, qi)}, -+ {VAR11 (BINOP, usqadd, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di, -+ si, hi, qi)}, -+ {VAR6 (UNOP, sqmovun, di, v8hi, v4si, v2di, si, hi)}, -+ {VAR6 (UNOP, sqmovn, di, v8hi, v4si, v2di, si, hi)}, -+ {VAR6 (UNOP, uqmovn, di, v8hi, v4si, v2di, si, hi)}, -+ {VAR10 (UNOP, sqabs, v8qi, v4hi, v2si, v16qi, v8hi, v4si, v2di, si, hi, qi)}, -+ {VAR10 (UNOP, sqneg, v8qi, v4hi, v2si, v16qi, v8hi, v4si, v2di, si, hi, qi)}, -+ {VAR2 (BINOP, pmul, v8qi, v16qi)}, -+ {VAR4 (TERNOP, sqdmlal, v4hi, v2si, si, hi)}, -+ {VAR4 (QUADOP, sqdmlal_lane, v4hi, v2si, si, hi) }, -+ {VAR2 (QUADOP, sqdmlal_laneq, v4hi, v2si) }, -+ {VAR2 (TERNOP, sqdmlal_n, v4hi, v2si) }, -+ {VAR2 (TERNOP, sqdmlal2, v8hi, v4si)}, -+ {VAR2 (QUADOP, sqdmlal2_lane, v8hi, v4si) }, -+ {VAR2 (QUADOP, sqdmlal2_laneq, v8hi, v4si) }, -+ {VAR2 (TERNOP, sqdmlal2_n, v8hi, v4si) }, -+ {VAR4 (TERNOP, sqdmlsl, v4hi, v2si, si, hi)}, -+ {VAR4 (QUADOP, sqdmlsl_lane, v4hi, v2si, si, hi) }, -+ {VAR2 (QUADOP, sqdmlsl_laneq, v4hi, v2si) }, -+ {VAR2 (TERNOP, sqdmlsl_n, v4hi, v2si) }, -+ {VAR2 (TERNOP, sqdmlsl2, v8hi, v4si)}, -+ {VAR2 (QUADOP, sqdmlsl2_lane, v8hi, v4si) }, -+ {VAR2 (QUADOP, sqdmlsl2_laneq, v8hi, v4si) }, -+ {VAR2 (TERNOP, sqdmlsl2_n, v8hi, v4si) }, -+ {VAR4 (BINOP, sqdmull, v4hi, v2si, si, hi)}, -+ {VAR4 (TERNOP, sqdmull_lane, v4hi, v2si, si, hi) }, -+ {VAR2 (TERNOP, sqdmull_laneq, v4hi, v2si) }, -+ {VAR2 (BINOP, sqdmull_n, v4hi, v2si) }, -+ {VAR2 (BINOP, sqdmull2, v8hi, v4si) }, -+ {VAR2 (TERNOP, sqdmull2_lane, v8hi, v4si) }, -+ {VAR2 (TERNOP, sqdmull2_laneq, v8hi, v4si) }, -+ {VAR2 (BINOP, sqdmull2_n, v8hi, v4si) }, -+ {VAR6 (BINOP, sqdmulh, v4hi, v2si, v8hi, v4si, si, hi)}, -+ {VAR6 (BINOP, sqrdmulh, v4hi, v2si, v8hi, v4si, si, hi)}, -+ {VAR8 (BINOP, sshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR3 (SHIFTIMM, sshll_n, v8qi, v4hi, v2si) }, -+ {VAR3 (SHIFTIMM, ushll_n, v8qi, v4hi, v2si) }, -+ {VAR3 (SHIFTIMM, sshll2_n, v16qi, v8hi, v4si) }, -+ {VAR3 (SHIFTIMM, ushll2_n, v16qi, v8hi, v4si) }, -+ {VAR8 (BINOP, ushl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR8 (BINOP, sshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR8 (BINOP, ushl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR11 (BINOP, sqshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di, -+ si, hi, qi) }, -+ {VAR11 (BINOP, uqshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di, -+ si, hi, qi) }, -+ {VAR8 (BINOP, srshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR8 (BINOP, urshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR11 (BINOP, sqrshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di, -+ si, hi, qi) }, -+ {VAR11 (BINOP, uqrshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di, -+ si, hi, qi) }, -+ {VAR8 (SHIFTIMM, sshr_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR8 (SHIFTIMM, ushr_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR8 (SHIFTIMM, srshr_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR8 (SHIFTIMM, urshr_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR8 (SHIFTACC, ssra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR8 (SHIFTACC, usra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR8 (SHIFTACC, srsra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR8 (SHIFTACC, ursra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR8 (SHIFTINSERT, ssri_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR8 (SHIFTINSERT, usri_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR8 (SHIFTINSERT, ssli_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR8 (SHIFTINSERT, usli_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR11 (SHIFTIMM, sqshlu_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di, -+ si, hi, qi) }, -+ {VAR11 (SHIFTIMM, sqshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di, -+ si, hi, qi) }, -+ {VAR11 (SHIFTIMM, uqshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di, -+ si, hi, qi) }, -+ { VAR6 (SHIFTIMM, sqshrun_n, di, v8hi, v4si, v2di, si, hi) }, -+ { VAR6 (SHIFTIMM, sqrshrun_n, di, v8hi, v4si, v2di, si, hi) }, -+ { VAR6 (SHIFTIMM, sqshrn_n, di, v8hi, v4si, v2di, si, hi) }, -+ { VAR6 (SHIFTIMM, uqshrn_n, di, v8hi, v4si, v2di, si, hi) }, -+ { VAR6 (SHIFTIMM, sqrshrn_n, di, v8hi, v4si, v2di, si, hi) }, -+ { VAR6 (SHIFTIMM, uqrshrn_n, di, v8hi, v4si, v2di, si, hi) }, -+ { VAR8 (BINOP, cmeq, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ { VAR8 (BINOP, cmge, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ { VAR8 (BINOP, cmgt, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ { VAR8 (BINOP, cmle, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ { VAR8 (BINOP, cmlt, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ { VAR8 (BINOP, cmhs, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ { VAR8 (BINOP, cmhi, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ { VAR8 (BINOP, cmtst, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ { VAR6 (TERNOP, sqdmulh_lane, v4hi, v2si, v8hi, v4si, si, hi) }, -+ { VAR6 (TERNOP, sqrdmulh_lane, v4hi, v2si, v8hi, v4si, si, hi) }, -+ { VAR3 (BINOP, addp, v8qi, v4hi, v2si) }, -+ { VAR1 (UNOP, addp, di) }, -+ { VAR11 (BINOP, dup_lane, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di, -+ si, hi, qi) }, -+ { VAR3 (BINOP, fmax, v2sf, v4sf, v2df) }, -+ { VAR3 (BINOP, fmin, v2sf, v4sf, v2df) }, -+ { VAR6 (BINOP, smax, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, -+ { VAR6 (BINOP, smin, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, -+ { VAR6 (BINOP, umax, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, -+ { VAR6 (BINOP, umin, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, -+ { VAR3 (UNOP, sqrt, v2sf, v4sf, v2df) }, -+ {VAR12 (LOADSTRUCT, ld2, -+ v8qi, v4hi, v2si, v2sf, di, df, v16qi, v8hi, v4si, v4sf, v2di, v2df)}, -+ {VAR12 (LOADSTRUCT, ld3, -+ v8qi, v4hi, v2si, v2sf, di, df, v16qi, v8hi, v4si, v4sf, v2di, v2df)}, -+ {VAR12 (LOADSTRUCT, ld4, -+ v8qi, v4hi, v2si, v2sf, di, df, v16qi, v8hi, v4si, v4sf, v2di, v2df)}, -+ {VAR12 (STORESTRUCT, st2, -+ v8qi, v4hi, v2si, v2sf, di, df, v16qi, v8hi, v4si, v4sf, v2di, v2df)}, -+ {VAR12 (STORESTRUCT, st3, -+ v8qi, v4hi, v2si, v2sf, di, df, v16qi, v8hi, v4si, v4sf, v2di, v2df)}, -+ {VAR12 (STORESTRUCT, st4, -+ v8qi, v4hi, v2si, v2sf, di, df, v16qi, v8hi, v4si, v4sf, v2di, v2df)}, ++#include "aarch64-simd-builtins.def" ++}; ++ ++#undef VAR1 ++#define VAR1(T, N, A) \ ++ AARCH64_SIMD_BUILTIN_##N##A, ++ ++enum aarch64_builtins ++{ ++ AARCH64_BUILTIN_MIN, ++ AARCH64_BUILTIN_THREAD_POINTER, ++ AARCH64_SIMD_BUILTIN_BASE, ++#include "aarch64-simd-builtins.def" ++ AARCH64_SIMD_BUILTIN_MAX = AARCH64_SIMD_BUILTIN_BASE ++ + ARRAY_SIZE (aarch64_simd_builtin_data), ++ AARCH64_BUILTIN_MAX +}; + ++#undef BUILTIN_DX ++#undef BUILTIN_SDQ_I ++#undef BUILTIN_SD_HSI ++#undef BUILTIN_V2F ++#undef BUILTIN_VALL ++#undef BUILTIN_VB ++#undef BUILTIN_VD ++#undef BUILTIN_VDC ++#undef BUILTIN_VDIC ++#undef BUILTIN_VDN ++#undef BUILTIN_VDQ ++#undef BUILTIN_VDQF ++#undef BUILTIN_VDQHS ++#undef BUILTIN_VDQIF ++#undef BUILTIN_VDQM ++#undef BUILTIN_VDQV ++#undef BUILTIN_VDQ_BHSI ++#undef BUILTIN_VDQ_I ++#undef BUILTIN_VDW ++#undef BUILTIN_VD_BHSI ++#undef BUILTIN_VD_HSI ++#undef BUILTIN_VD_RE ++#undef BUILTIN_VQ ++#undef BUILTIN_VQN ++#undef BUILTIN_VQW ++#undef BUILTIN_VQ_HSI ++#undef BUILTIN_VQ_S ++#undef BUILTIN_VSDQ_HSI ++#undef BUILTIN_VSDQ_I ++#undef BUILTIN_VSDQ_I_BHSI ++#undef BUILTIN_VSDQ_I_DI ++#undef BUILTIN_VSD_HSI ++#undef BUILTIN_VSQN_HSDI ++#undef BUILTIN_VSTRUCT +#undef CF +#undef VAR1 +#undef VAR2 @@ -3726,13 +4639,15 @@ +#undef VAR10 +#undef VAR11 + ++static GTY(()) tree aarch64_builtin_decls[AARCH64_BUILTIN_MAX]; ++ +#define NUM_DREG_TYPES 6 +#define NUM_QREG_TYPES 6 + -+void -+init_aarch64_simd_builtins (void) ++static void ++aarch64_init_simd_builtins (void) +{ -+ unsigned int i, fcode = AARCH64_SIMD_BUILTIN_BASE; ++ unsigned int i, fcode = AARCH64_SIMD_BUILTIN_BASE + 1; + + /* Scalar type nodes. */ + tree aarch64_simd_intQI_type_node; @@ -4022,417 +4937,388 @@ + } + } + -+ for (i = 0; i < ARRAY_SIZE (aarch64_simd_builtin_data); i++) ++ for (i = 0; i < ARRAY_SIZE (aarch64_simd_builtin_data); i++, fcode++) + { + aarch64_simd_builtin_datum *d = &aarch64_simd_builtin_data[i]; -+ unsigned int j, codeidx = 0; ++ const char *const modenames[] = ++ { ++ "v8qi", "v4hi", "v2si", "v2sf", "di", "df", ++ "v16qi", "v8hi", "v4si", "v4sf", "v2di", "v2df", ++ "ti", "ei", "oi", "xi", "si", "hi", "qi" ++ }; ++ char namebuf[60]; ++ tree ftype = NULL; ++ tree fndecl = NULL; ++ int is_load = 0; ++ int is_store = 0; ++ ++ gcc_assert (ARRAY_SIZE (modenames) == T_MAX); ++ ++ d->fcode = fcode; ++ ++ switch (d->itype) ++ { ++ case AARCH64_SIMD_LOAD1: ++ case AARCH64_SIMD_LOAD1LANE: ++ case AARCH64_SIMD_LOADSTRUCT: ++ case AARCH64_SIMD_LOADSTRUCTLANE: ++ is_load = 1; ++ /* Fall through. */ ++ case AARCH64_SIMD_STORE1: ++ case AARCH64_SIMD_STORE1LANE: ++ case AARCH64_SIMD_STORESTRUCT: ++ case AARCH64_SIMD_STORESTRUCTLANE: ++ if (!is_load) ++ is_store = 1; ++ /* Fall through. */ ++ case AARCH64_SIMD_UNOP: ++ case AARCH64_SIMD_BINOP: ++ case AARCH64_SIMD_TERNOP: ++ case AARCH64_SIMD_QUADOP: ++ case AARCH64_SIMD_COMBINE: ++ case AARCH64_SIMD_CONVERT: ++ case AARCH64_SIMD_CREATE: ++ case AARCH64_SIMD_DUP: ++ case AARCH64_SIMD_DUPLANE: ++ case AARCH64_SIMD_FIXCONV: ++ case AARCH64_SIMD_GETLANE: ++ case AARCH64_SIMD_LANEMAC: ++ case AARCH64_SIMD_LANEMUL: ++ case AARCH64_SIMD_LANEMULH: ++ case AARCH64_SIMD_LANEMULL: ++ case AARCH64_SIMD_LOGICBINOP: ++ case AARCH64_SIMD_SCALARMAC: ++ case AARCH64_SIMD_SCALARMUL: ++ case AARCH64_SIMD_SCALARMULH: ++ case AARCH64_SIMD_SCALARMULL: ++ case AARCH64_SIMD_SELECT: ++ case AARCH64_SIMD_SETLANE: ++ case AARCH64_SIMD_SHIFTACC: ++ case AARCH64_SIMD_SHIFTIMM: ++ case AARCH64_SIMD_SHIFTINSERT: ++ case AARCH64_SIMD_SPLIT: ++ case AARCH64_SIMD_VTBL: ++ case AARCH64_SIMD_VTBX: ++ { ++ int k; ++ tree return_type = void_type_node, args = void_list_node; ++ tree eltype; ++ /* Build a function type directly from the insn_data for this ++ builtin. The build_function_type () function takes care of ++ removing duplicates for us. */ + -+ d->base_fcode = fcode; ++ for (k = insn_data[d->code].n_operands -1; k >= 0; k--) ++ { ++ /* Skip an internal operand for vget_{low, high}. */ ++ if (k == 2 && d->itype == AARCH64_SIMD_SPLIT) ++ continue; + -+ for (j = 0; j < T_MAX; j++) -+ { -+ const char *const modenames[] = { -+ "v8qi", "v4hi", "v2si", "v2sf", "di", "df", -+ "v16qi", "v8hi", "v4si", "v4sf", "v2di", "v2df", -+ "ti", "ei", "oi", "xi", "si", "hi", "qi" -+ }; -+ char namebuf[60]; -+ tree ftype = NULL; -+ enum insn_code icode; -+ int is_load = 0; -+ int is_store = 0; -+ -+ /* Skip if particular mode not supported. */ -+ if ((d->bits & (1 << j)) == 0) -+ continue; ++ if (is_load && k == 1) ++ { ++ /* AdvSIMD load patterns always have the memory operand ++ (a DImode pointer) in the operand 1 position. We ++ want a const pointer to the element type in that ++ position. */ ++ gcc_assert (insn_data[d->code].operand[k].mode == DImode); + -+ icode = d->codes[codeidx++]; ++ switch (d->mode) ++ { ++ case T_V8QI: ++ case T_V16QI: ++ eltype = const_intQI_pointer_node; ++ break; + -+ switch (d->itype) -+ { -+ case AARCH64_SIMD_LOAD1: -+ case AARCH64_SIMD_LOAD1LANE: -+ case AARCH64_SIMD_LOADSTRUCTLANE: -+ case AARCH64_SIMD_LOADSTRUCT: -+ is_load = 1; -+ /* Fall through. */ -+ case AARCH64_SIMD_STORE1: -+ case AARCH64_SIMD_STORE1LANE: -+ case AARCH64_SIMD_STORESTRUCTLANE: -+ case AARCH64_SIMD_STORESTRUCT: -+ if (!is_load) -+ is_store = 1; -+ /* Fall through. */ -+ case AARCH64_SIMD_UNOP: -+ case AARCH64_SIMD_BINOP: -+ case AARCH64_SIMD_LOGICBINOP: -+ case AARCH64_SIMD_SHIFTINSERT: -+ case AARCH64_SIMD_TERNOP: -+ case AARCH64_SIMD_QUADOP: -+ case AARCH64_SIMD_GETLANE: -+ case AARCH64_SIMD_SETLANE: -+ case AARCH64_SIMD_CREATE: -+ case AARCH64_SIMD_DUP: -+ case AARCH64_SIMD_DUPLANE: -+ case AARCH64_SIMD_SHIFTIMM: -+ case AARCH64_SIMD_SHIFTACC: -+ case AARCH64_SIMD_COMBINE: -+ case AARCH64_SIMD_SPLIT: -+ case AARCH64_SIMD_CONVERT: -+ case AARCH64_SIMD_FIXCONV: -+ case AARCH64_SIMD_LANEMUL: -+ case AARCH64_SIMD_LANEMULL: -+ case AARCH64_SIMD_LANEMULH: -+ case AARCH64_SIMD_LANEMAC: -+ case AARCH64_SIMD_SCALARMUL: -+ case AARCH64_SIMD_SCALARMULL: -+ case AARCH64_SIMD_SCALARMULH: -+ case AARCH64_SIMD_SCALARMAC: -+ case AARCH64_SIMD_SELECT: -+ case AARCH64_SIMD_VTBL: -+ case AARCH64_SIMD_VTBX: -+ { -+ int k; -+ tree return_type = void_type_node, args = void_list_node; ++ case T_V4HI: ++ case T_V8HI: ++ eltype = const_intHI_pointer_node; ++ break; + -+ /* Build a function type directly from the insn_data for this -+ builtin. The build_function_type() function takes care of -+ removing duplicates for us. */ -+ for (k = insn_data[icode].n_operands - 1; k >= 0; k--) -+ { -+ tree eltype; ++ case T_V2SI: ++ case T_V4SI: ++ eltype = const_intSI_pointer_node; ++ break; + -+ /* Skip an internal operand for vget_{low, high}. */ -+ if (k == 2 && d->itype == AARCH64_SIMD_SPLIT) -+ continue; ++ case T_V2SF: ++ case T_V4SF: ++ eltype = const_float_pointer_node; ++ break; + -+ if (is_load && k == 1) -+ { -+ /* AdvSIMD load patterns always have the memory operand -+ (a DImode pointer) in the operand 1 position. We -+ want a const pointer to the element type in that -+ position. */ -+ gcc_assert (insn_data[icode].operand[k].mode == -+ DImode); -+ -+ switch (1 << j) -+ { -+ case T_V8QI: -+ case T_V16QI: -+ eltype = const_intQI_pointer_node; -+ break; -+ -+ case T_V4HI: -+ case T_V8HI: -+ eltype = const_intHI_pointer_node; -+ break; -+ -+ case T_V2SI: -+ case T_V4SI: -+ eltype = const_intSI_pointer_node; -+ break; -+ -+ case T_V2SF: -+ case T_V4SF: -+ eltype = const_float_pointer_node; -+ break; -+ -+ case T_DI: -+ case T_V2DI: -+ eltype = const_intDI_pointer_node; -+ break; -+ -+ case T_DF: -+ case T_V2DF: -+ eltype = const_double_pointer_node; -+ break; -+ -+ default: -+ gcc_unreachable (); -+ } ++ case T_DI: ++ case T_V2DI: ++ eltype = const_intDI_pointer_node; ++ break; ++ ++ case T_DF: ++ case T_V2DF: ++ eltype = const_double_pointer_node; ++ break; ++ ++ default: ++ gcc_unreachable (); + } -+ else if (is_store && k == 0) ++ } ++ else if (is_store && k == 0) ++ { ++ /* Similarly, AdvSIMD store patterns use operand 0 as ++ the memory location to store to (a DImode pointer). ++ Use a pointer to the element type of the store in ++ that position. */ ++ gcc_assert (insn_data[d->code].operand[k].mode == DImode); ++ ++ switch (d->mode) + { -+ /* Similarly, AdvSIMD store patterns use operand 0 as -+ the memory location to store to (a DImode pointer). -+ Use a pointer to the element type of the store in -+ that position. */ -+ gcc_assert (insn_data[icode].operand[k].mode == -+ DImode); -+ -+ switch (1 << j) -+ { -+ case T_V8QI: -+ case T_V16QI: -+ eltype = intQI_pointer_node; -+ break; -+ -+ case T_V4HI: -+ case T_V8HI: -+ eltype = intHI_pointer_node; -+ break; -+ -+ case T_V2SI: -+ case T_V4SI: -+ eltype = intSI_pointer_node; -+ break; -+ -+ case T_V2SF: -+ case T_V4SF: -+ eltype = float_pointer_node; -+ break; -+ -+ case T_DI: -+ case T_V2DI: -+ eltype = intDI_pointer_node; -+ break; -+ -+ case T_DF: -+ case T_V2DF: -+ eltype = double_pointer_node; -+ break; -+ -+ default: -+ gcc_unreachable (); -+ } ++ case T_V8QI: ++ case T_V16QI: ++ eltype = intQI_pointer_node; ++ break; ++ ++ case T_V4HI: ++ case T_V8HI: ++ eltype = intHI_pointer_node; ++ break; ++ ++ case T_V2SI: ++ case T_V4SI: ++ eltype = intSI_pointer_node; ++ break; ++ ++ case T_V2SF: ++ case T_V4SF: ++ eltype = float_pointer_node; ++ break; ++ ++ case T_DI: ++ case T_V2DI: ++ eltype = intDI_pointer_node; ++ break; ++ ++ case T_DF: ++ case T_V2DF: ++ eltype = double_pointer_node; ++ break; ++ ++ default: ++ gcc_unreachable (); + } -+ else ++ } ++ else ++ { ++ switch (insn_data[d->code].operand[k].mode) + { -+ switch (insn_data[icode].operand[k].mode) -+ { -+ case VOIDmode: -+ eltype = void_type_node; -+ break; -+ /* Scalars. */ -+ case QImode: -+ eltype = aarch64_simd_intQI_type_node; -+ break; -+ case HImode: -+ eltype = aarch64_simd_intHI_type_node; -+ break; -+ case SImode: -+ eltype = aarch64_simd_intSI_type_node; -+ break; -+ case SFmode: -+ eltype = aarch64_simd_float_type_node; -+ break; -+ case DFmode: -+ eltype = aarch64_simd_double_type_node; -+ break; -+ case DImode: -+ eltype = aarch64_simd_intDI_type_node; -+ break; -+ case TImode: -+ eltype = intTI_type_node; -+ break; -+ case EImode: -+ eltype = intEI_type_node; -+ break; -+ case OImode: -+ eltype = intOI_type_node; -+ break; -+ case CImode: -+ eltype = intCI_type_node; -+ break; -+ case XImode: -+ eltype = intXI_type_node; -+ break; -+ /* 64-bit vectors. */ -+ case V8QImode: -+ eltype = V8QI_type_node; -+ break; -+ case V4HImode: -+ eltype = V4HI_type_node; -+ break; -+ case V2SImode: -+ eltype = V2SI_type_node; -+ break; -+ case V2SFmode: -+ eltype = V2SF_type_node; -+ break; -+ /* 128-bit vectors. */ -+ case V16QImode: -+ eltype = V16QI_type_node; -+ break; -+ case V8HImode: -+ eltype = V8HI_type_node; -+ break; -+ case V4SImode: -+ eltype = V4SI_type_node; -+ break; -+ case V4SFmode: -+ eltype = V4SF_type_node; -+ break; -+ case V2DImode: -+ eltype = V2DI_type_node; -+ break; -+ case V2DFmode: -+ eltype = V2DF_type_node; -+ break; -+ default: -+ gcc_unreachable (); -+ } ++ case VOIDmode: ++ eltype = void_type_node; ++ break; ++ /* Scalars. */ ++ case QImode: ++ eltype = aarch64_simd_intQI_type_node; ++ break; ++ case HImode: ++ eltype = aarch64_simd_intHI_type_node; ++ break; ++ case SImode: ++ eltype = aarch64_simd_intSI_type_node; ++ break; ++ case SFmode: ++ eltype = aarch64_simd_float_type_node; ++ break; ++ case DFmode: ++ eltype = aarch64_simd_double_type_node; ++ break; ++ case DImode: ++ eltype = aarch64_simd_intDI_type_node; ++ break; ++ case TImode: ++ eltype = intTI_type_node; ++ break; ++ case EImode: ++ eltype = intEI_type_node; ++ break; ++ case OImode: ++ eltype = intOI_type_node; ++ break; ++ case CImode: ++ eltype = intCI_type_node; ++ break; ++ case XImode: ++ eltype = intXI_type_node; ++ break; ++ /* 64-bit vectors. */ ++ case V8QImode: ++ eltype = V8QI_type_node; ++ break; ++ case V4HImode: ++ eltype = V4HI_type_node; ++ break; ++ case V2SImode: ++ eltype = V2SI_type_node; ++ break; ++ case V2SFmode: ++ eltype = V2SF_type_node; ++ break; ++ /* 128-bit vectors. */ ++ case V16QImode: ++ eltype = V16QI_type_node; ++ break; ++ case V8HImode: ++ eltype = V8HI_type_node; ++ break; ++ case V4SImode: ++ eltype = V4SI_type_node; ++ break; ++ case V4SFmode: ++ eltype = V4SF_type_node; ++ break; ++ case V2DImode: ++ eltype = V2DI_type_node; ++ break; ++ case V2DFmode: ++ eltype = V2DF_type_node; ++ break; ++ default: ++ gcc_unreachable (); + } -+ -+ if (k == 0 && !is_store) -+ return_type = eltype; -+ else -+ args = tree_cons (NULL_TREE, eltype, args); + } + -+ ftype = build_function_type (return_type, args); ++ if (k == 0 && !is_store) ++ return_type = eltype; ++ else ++ args = tree_cons (NULL_TREE, eltype, args); + } -+ break; ++ ftype = build_function_type (return_type, args); ++ } ++ break; + -+ case AARCH64_SIMD_RESULTPAIR: ++ case AARCH64_SIMD_RESULTPAIR: ++ { ++ switch (insn_data[d->code].operand[1].mode) + { -+ switch (insn_data[icode].operand[1].mode) -+ { -+ case V8QImode: -+ ftype = void_ftype_pv8qi_v8qi_v8qi; -+ break; -+ case V4HImode: -+ ftype = void_ftype_pv4hi_v4hi_v4hi; -+ break; -+ case V2SImode: -+ ftype = void_ftype_pv2si_v2si_v2si; -+ break; -+ case V2SFmode: -+ ftype = void_ftype_pv2sf_v2sf_v2sf; -+ break; -+ case DImode: -+ ftype = void_ftype_pdi_di_di; -+ break; -+ case V16QImode: -+ ftype = void_ftype_pv16qi_v16qi_v16qi; -+ break; -+ case V8HImode: -+ ftype = void_ftype_pv8hi_v8hi_v8hi; -+ break; -+ case V4SImode: -+ ftype = void_ftype_pv4si_v4si_v4si; -+ break; -+ case V4SFmode: -+ ftype = void_ftype_pv4sf_v4sf_v4sf; -+ break; -+ case V2DImode: -+ ftype = void_ftype_pv2di_v2di_v2di; -+ break; -+ case V2DFmode: -+ ftype = void_ftype_pv2df_v2df_v2df; -+ break; -+ default: -+ gcc_unreachable (); -+ } ++ case V8QImode: ++ ftype = void_ftype_pv8qi_v8qi_v8qi; ++ break; ++ case V4HImode: ++ ftype = void_ftype_pv4hi_v4hi_v4hi; ++ break; ++ case V2SImode: ++ ftype = void_ftype_pv2si_v2si_v2si; ++ break; ++ case V2SFmode: ++ ftype = void_ftype_pv2sf_v2sf_v2sf; ++ break; ++ case DImode: ++ ftype = void_ftype_pdi_di_di; ++ break; ++ case V16QImode: ++ ftype = void_ftype_pv16qi_v16qi_v16qi; ++ break; ++ case V8HImode: ++ ftype = void_ftype_pv8hi_v8hi_v8hi; ++ break; ++ case V4SImode: ++ ftype = void_ftype_pv4si_v4si_v4si; ++ break; ++ case V4SFmode: ++ ftype = void_ftype_pv4sf_v4sf_v4sf; ++ break; ++ case V2DImode: ++ ftype = void_ftype_pv2di_v2di_v2di; ++ break; ++ case V2DFmode: ++ ftype = void_ftype_pv2df_v2df_v2df; ++ break; ++ default: ++ gcc_unreachable (); + } -+ break; ++ } ++ break; + -+ case AARCH64_SIMD_REINTERP: ++ case AARCH64_SIMD_REINTERP: ++ { ++ /* We iterate over 6 doubleword types, then 6 quadword ++ types. */ ++ int rhs_d = d->mode % NUM_DREG_TYPES; ++ int rhs_q = (d->mode - NUM_DREG_TYPES) % NUM_QREG_TYPES; ++ switch (insn_data[d->code].operand[0].mode) + { -+ /* We iterate over 6 doubleword types, then 6 quadword -+ types. */ -+ int rhs_d = j % NUM_DREG_TYPES; -+ int rhs_q = (j - NUM_DREG_TYPES) % NUM_QREG_TYPES; -+ switch (insn_data[icode].operand[0].mode) -+ { -+ case V8QImode: -+ ftype = reinterp_ftype_dreg[0][rhs_d]; -+ break; -+ case V4HImode: -+ ftype = reinterp_ftype_dreg[1][rhs_d]; -+ break; -+ case V2SImode: -+ ftype = reinterp_ftype_dreg[2][rhs_d]; -+ break; -+ case V2SFmode: -+ ftype = reinterp_ftype_dreg[3][rhs_d]; -+ break; -+ case DImode: -+ ftype = reinterp_ftype_dreg[4][rhs_d]; -+ break; -+ case DFmode: -+ ftype = reinterp_ftype_dreg[5][rhs_d]; -+ break; -+ case V16QImode: -+ ftype = reinterp_ftype_qreg[0][rhs_q]; -+ break; -+ case V8HImode: -+ ftype = reinterp_ftype_qreg[1][rhs_q]; -+ break; -+ case V4SImode: -+ ftype = reinterp_ftype_qreg[2][rhs_q]; -+ break; -+ case V4SFmode: -+ ftype = reinterp_ftype_qreg[3][rhs_q]; -+ break; -+ case V2DImode: -+ ftype = reinterp_ftype_qreg[4][rhs_q]; -+ break; -+ case V2DFmode: -+ ftype = reinterp_ftype_qreg[5][rhs_q]; -+ break; -+ default: -+ gcc_unreachable (); -+ } ++ case V8QImode: ++ ftype = reinterp_ftype_dreg[0][rhs_d]; ++ break; ++ case V4HImode: ++ ftype = reinterp_ftype_dreg[1][rhs_d]; ++ break; ++ case V2SImode: ++ ftype = reinterp_ftype_dreg[2][rhs_d]; ++ break; ++ case V2SFmode: ++ ftype = reinterp_ftype_dreg[3][rhs_d]; ++ break; ++ case DImode: ++ ftype = reinterp_ftype_dreg[4][rhs_d]; ++ break; ++ case DFmode: ++ ftype = reinterp_ftype_dreg[5][rhs_d]; ++ break; ++ case V16QImode: ++ ftype = reinterp_ftype_qreg[0][rhs_q]; ++ break; ++ case V8HImode: ++ ftype = reinterp_ftype_qreg[1][rhs_q]; ++ break; ++ case V4SImode: ++ ftype = reinterp_ftype_qreg[2][rhs_q]; ++ break; ++ case V4SFmode: ++ ftype = reinterp_ftype_qreg[3][rhs_q]; ++ break; ++ case V2DImode: ++ ftype = reinterp_ftype_qreg[4][rhs_q]; ++ break; ++ case V2DFmode: ++ ftype = reinterp_ftype_qreg[5][rhs_q]; ++ break; ++ default: ++ gcc_unreachable (); + } -+ break; -+ -+ default: -+ gcc_unreachable (); -+ } ++ } ++ break; + -+ gcc_assert (ftype != NULL); ++ default: ++ gcc_unreachable (); ++ } ++ gcc_assert (ftype != NULL); + -+ snprintf (namebuf, sizeof (namebuf), "__builtin_aarch64_%s%s", -+ d->name, modenames[j]); ++ snprintf (namebuf, sizeof (namebuf), "__builtin_aarch64_%s%s", ++ d->name, modenames[d->mode]); + -+ add_builtin_function (namebuf, ftype, fcode++, BUILT_IN_MD, NULL, -+ NULL_TREE); -+ } ++ fndecl = add_builtin_function (namebuf, ftype, fcode, BUILT_IN_MD, ++ NULL, NULL_TREE); ++ aarch64_builtin_decls[fcode] = fndecl; + } +} + -+static int -+aarch64_simd_builtin_compare (const void *a, const void *b) ++void ++aarch64_init_builtins (void) +{ -+ const aarch64_simd_builtin_datum *const key = -+ (const aarch64_simd_builtin_datum *) a; -+ const aarch64_simd_builtin_datum *const memb = -+ (const aarch64_simd_builtin_datum *) b; -+ unsigned int soughtcode = key->base_fcode; ++ tree ftype, decl = NULL; + -+ if (soughtcode >= memb->base_fcode -+ && soughtcode < memb->base_fcode + memb->num_vars) -+ return 0; -+ else if (soughtcode < memb->base_fcode) -+ return -1; -+ else -+ return 1; -+} ++ ftype = build_function_type (ptr_type_node, void_list_node); ++ decl = add_builtin_function ("__builtin_thread_pointer", ftype, ++ AARCH64_BUILTIN_THREAD_POINTER, BUILT_IN_MD, ++ NULL, NULL_TREE); ++ TREE_NOTHROW (decl) = 1; ++ TREE_READONLY (decl) = 1; ++ aarch64_builtin_decls[AARCH64_BUILTIN_THREAD_POINTER] = decl; + ++ if (TARGET_SIMD) ++ aarch64_init_simd_builtins (); ++} + -+static enum insn_code -+locate_simd_builtin_icode (int fcode, aarch64_simd_itype * itype) ++tree ++aarch64_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED) +{ -+ aarch64_simd_builtin_datum key -+ = { NULL, (aarch64_simd_itype) 0, 0, {CODE_FOR_nothing}, 0, 0}; -+ aarch64_simd_builtin_datum *found; -+ int idx; -+ -+ key.base_fcode = fcode; -+ found = (aarch64_simd_builtin_datum *) -+ bsearch (&key, &aarch64_simd_builtin_data[0], -+ ARRAY_SIZE (aarch64_simd_builtin_data), -+ sizeof (aarch64_simd_builtin_data[0]), -+ aarch64_simd_builtin_compare); -+ gcc_assert (found); -+ idx = fcode - (int) found->base_fcode; -+ gcc_assert (idx >= 0 && idx < T_MAX && idx < (int) found->num_vars); -+ -+ if (itype) -+ *itype = found->itype; ++ if (code >= AARCH64_BUILTIN_MAX) ++ return error_mark_node; + -+ return found->codes[idx]; ++ return aarch64_builtin_decls[code]; +} + +typedef enum @@ -4567,8 +5453,10 @@ +rtx +aarch64_simd_expand_builtin (int fcode, tree exp, rtx target) +{ -+ aarch64_simd_itype itype; -+ enum insn_code icode = locate_simd_builtin_icode (fcode, &itype); ++ aarch64_simd_builtin_datum *d = ++ &aarch64_simd_builtin_data[fcode - (AARCH64_SIMD_BUILTIN_BASE + 1)]; ++ aarch64_simd_itype itype = d->itype; ++ enum insn_code icode = d->code; + + switch (itype) + { @@ -4660,11 +5548,102 @@ + gcc_unreachable (); + } +} ++ ++/* Expand an expression EXP that calls a built-in function, ++ with result going to TARGET if that's convenient. */ ++rtx ++aarch64_expand_builtin (tree exp, ++ rtx target, ++ rtx subtarget ATTRIBUTE_UNUSED, ++ enum machine_mode mode ATTRIBUTE_UNUSED, ++ int ignore ATTRIBUTE_UNUSED) ++{ ++ tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); ++ int fcode = DECL_FUNCTION_CODE (fndecl); ++ ++ if (fcode == AARCH64_BUILTIN_THREAD_POINTER) ++ return aarch64_load_tp (target); ++ ++ if (fcode >= AARCH64_SIMD_BUILTIN_BASE) ++ return aarch64_simd_expand_builtin (fcode, exp, target); ++ ++ return NULL_RTX; ++} ++ ++tree ++aarch64_builtin_vectorized_function (tree fndecl, tree type_out, tree type_in) ++{ ++ enum machine_mode in_mode, out_mode; ++ int in_n, out_n; ++ ++ if (TREE_CODE (type_out) != VECTOR_TYPE ++ || TREE_CODE (type_in) != VECTOR_TYPE) ++ return NULL_TREE; ++ ++ out_mode = TYPE_MODE (TREE_TYPE (type_out)); ++ out_n = TYPE_VECTOR_SUBPARTS (type_out); ++ in_mode = TYPE_MODE (TREE_TYPE (type_in)); ++ in_n = TYPE_VECTOR_SUBPARTS (type_in); ++ ++#undef AARCH64_CHECK_BUILTIN_MODE ++#define AARCH64_CHECK_BUILTIN_MODE(C, N) 1 ++#define AARCH64_FIND_FRINT_VARIANT(N) \ ++ (AARCH64_CHECK_BUILTIN_MODE (2, D) \ ++ ? aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_##N##v2df] \ ++ : (AARCH64_CHECK_BUILTIN_MODE (4, S) \ ++ ? aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_##N##v4sf] \ ++ : (AARCH64_CHECK_BUILTIN_MODE (2, S) \ ++ ? aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_##N##v2sf] \ ++ : NULL_TREE))) ++ if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_NORMAL) ++ { ++ enum built_in_function fn = DECL_FUNCTION_CODE (fndecl); ++ switch (fn) ++ { ++#undef AARCH64_CHECK_BUILTIN_MODE ++#define AARCH64_CHECK_BUILTIN_MODE(C, N) \ ++ (out_mode == N##Fmode && out_n == C \ ++ && in_mode == N##Fmode && in_n == C) ++ case BUILT_IN_FLOOR: ++ case BUILT_IN_FLOORF: ++ return AARCH64_FIND_FRINT_VARIANT (frintm); ++ case BUILT_IN_CEIL: ++ case BUILT_IN_CEILF: ++ return AARCH64_FIND_FRINT_VARIANT (frintp); ++ case BUILT_IN_TRUNC: ++ case BUILT_IN_TRUNCF: ++ return AARCH64_FIND_FRINT_VARIANT (frintz); ++ case BUILT_IN_ROUND: ++ case BUILT_IN_ROUNDF: ++ return AARCH64_FIND_FRINT_VARIANT (frinta); ++ case BUILT_IN_NEARBYINT: ++ case BUILT_IN_NEARBYINTF: ++ return AARCH64_FIND_FRINT_VARIANT (frinti); ++ case BUILT_IN_SQRT: ++ case BUILT_IN_SQRTF: ++ return AARCH64_FIND_FRINT_VARIANT (sqrt); ++#undef AARCH64_CHECK_BUILTIN_MODE ++#define AARCH64_CHECK_BUILTIN_MODE(C, N) \ ++ (out_mode == N##Imode && out_n == C \ ++ && in_mode == N##Fmode && in_n == C) ++ case BUILT_IN_LFLOOR: ++ return AARCH64_FIND_FRINT_VARIANT (fcvtms); ++ case BUILT_IN_LCEIL: ++ return AARCH64_FIND_FRINT_VARIANT (fcvtps); ++ default: ++ return NULL_TREE; ++ } ++ } ++ ++ return NULL_TREE; ++} ++#undef AARCH64_CHECK_BUILTIN_MODE ++#undef AARCH64_FIND_FRINT_VARIANT --- a/src/gcc/config/aarch64/aarch64.c +++ b/src/gcc/config/aarch64/aarch64.c -@@ -0,0 +1,6999 @@ +@@ -0,0 +1,7965 @@ +/* Machine description for AArch64 architecture. -+ Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. ++ Copyright (C) 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc. + Contributed by ARM Ltd. + + This file is part of GCC. @@ -4767,7 +5746,6 @@ + bool *); +static void aarch64_elf_asm_constructor (rtx, int) ATTRIBUTE_UNUSED; +static void aarch64_elf_asm_destructor (rtx, int) ATTRIBUTE_UNUSED; -+static rtx aarch64_load_tp (rtx); +static void aarch64_override_options_after_change (void); +static int aarch64_simd_valid_immediate (rtx, enum machine_mode, int, rtx *, + int *, unsigned char *, int *, int *); @@ -4776,6 +5754,9 @@ +static bool aarch64_const_vec_all_same_int_p (rtx, + HOST_WIDE_INT, HOST_WIDE_INT); + ++static bool aarch64_vectorize_vec_perm_const_ok (enum machine_mode vmode, ++ const unsigned char *sel); ++ +/* The processor for which instructions should be scheduled. */ +enum aarch64_processor aarch64_tune = generic; + @@ -4788,8 +5769,70 @@ +/* Mask to specify which instruction scheduling options should be used. */ +unsigned long aarch64_tune_flags = 0; + -+/* Tuning models. */ -+static const struct tune_params generic_tunings; ++/* Tuning parameters. */ ++ ++#if HAVE_DESIGNATED_INITIALIZERS ++#define NAMED_PARAM(NAME, VAL) .NAME = (VAL) ++#else ++#define NAMED_PARAM(NAME, VAL) (VAL) ++#endif ++ ++#if HAVE_DESIGNATED_INITIALIZERS && GCC_VERSION >= 2007 ++__extension__ ++#endif ++static const struct cpu_rtx_cost_table generic_rtx_cost_table = ++{ ++ NAMED_PARAM (memory_load, COSTS_N_INSNS (1)), ++ NAMED_PARAM (memory_store, COSTS_N_INSNS (0)), ++ NAMED_PARAM (register_shift, COSTS_N_INSNS (1)), ++ NAMED_PARAM (int_divide, COSTS_N_INSNS (6)), ++ NAMED_PARAM (float_divide, COSTS_N_INSNS (2)), ++ NAMED_PARAM (double_divide, COSTS_N_INSNS (6)), ++ NAMED_PARAM (int_multiply, COSTS_N_INSNS (1)), ++ NAMED_PARAM (int_multiply_extend, COSTS_N_INSNS (1)), ++ NAMED_PARAM (int_multiply_add, COSTS_N_INSNS (1)), ++ NAMED_PARAM (int_multiply_extend_add, COSTS_N_INSNS (1)), ++ NAMED_PARAM (float_multiply, COSTS_N_INSNS (0)), ++ NAMED_PARAM (double_multiply, COSTS_N_INSNS (1)) ++}; ++ ++#if HAVE_DESIGNATED_INITIALIZERS && GCC_VERSION >= 2007 ++__extension__ ++#endif ++static const struct cpu_addrcost_table generic_addrcost_table = ++{ ++ NAMED_PARAM (pre_modify, 0), ++ NAMED_PARAM (post_modify, 0), ++ NAMED_PARAM (register_offset, 0), ++ NAMED_PARAM (register_extend, 0), ++ NAMED_PARAM (imm_offset, 0) ++}; ++ ++#if HAVE_DESIGNATED_INITIALIZERS && GCC_VERSION >= 2007 ++__extension__ ++#endif ++static const struct cpu_regmove_cost generic_regmove_cost = ++{ ++ NAMED_PARAM (GP2GP, 1), ++ NAMED_PARAM (GP2FP, 2), ++ NAMED_PARAM (FP2GP, 2), ++ /* We currently do not provide direct support for TFmode Q->Q move. ++ Therefore we need to raise the cost above 2 in order to have ++ reload handle the situation. */ ++ NAMED_PARAM (FP2FP, 4) ++}; ++ ++#if HAVE_DESIGNATED_INITIALIZERS && GCC_VERSION >= 2007 ++__extension__ ++#endif ++ ++static const struct tune_params generic_tunings = ++{ ++ &generic_rtx_cost_table, ++ &generic_addrcost_table, ++ &generic_regmove_cost, ++ NAMED_PARAM (memmov_cost, 4) ++}; + +/* A processor implementing AArch64. */ +struct processor @@ -6832,12 +7875,10 @@ + +/* Output code to build up a constant in a register. */ +static void -+aarch64_build_constant (FILE *file, -+ int regnum, -+ HOST_WIDE_INT val) ++aarch64_build_constant (int regnum, HOST_WIDE_INT val) +{ + if (aarch64_bitmask_imm (val, DImode)) -+ asm_fprintf (file, "\tmovi\t%r, %wd\n", regnum, val); ++ emit_move_insn (gen_rtx_REG (Pmode, regnum), GEN_INT (val)); + else + { + int i; @@ -6868,12 +7909,14 @@ + the same. */ + if (ncount < zcount) + { -+ asm_fprintf (file, "\tmovn\t%r, %wd\n", regnum, (~val) & 0xffff); ++ emit_move_insn (gen_rtx_REG (Pmode, regnum), ++ GEN_INT ((~val) & 0xffff)); + tval = 0xffff; + } + else + { -+ asm_fprintf (file, "\tmovz\t%r, %wd\n", regnum, val & 0xffff); ++ emit_move_insn (gen_rtx_REG (Pmode, regnum), ++ GEN_INT (val & 0xffff)); + tval = 0; + } + @@ -6882,39 +7925,49 @@ + for (i = 16; i < 64; i += 16) + { + if ((val & 0xffff) != tval) -+ asm_fprintf (file, "\tmovk\t%r, %wd, lsl %d\n", -+ regnum, val & 0xffff, i); ++ emit_insn (gen_insv_immdi (gen_rtx_REG (Pmode, regnum), ++ GEN_INT (i), GEN_INT (val & 0xffff))); + val >>= 16; + } + } +} + +static void -+aarch64_add_constant (FILE *file, int regnum, int scratchreg, -+ HOST_WIDE_INT delta) ++aarch64_add_constant (int regnum, int scratchreg, HOST_WIDE_INT delta) +{ + HOST_WIDE_INT mdelta = delta; ++ rtx this_rtx = gen_rtx_REG (Pmode, regnum); ++ rtx scratch_rtx = gen_rtx_REG (Pmode, scratchreg); + + if (mdelta < 0) + mdelta = -mdelta; + + if (mdelta >= 4096 * 4096) + { -+ aarch64_build_constant (file, scratchreg, delta); -+ asm_fprintf (file, "\tadd\t%r, %r, %r\n", regnum, regnum, -+ scratchreg); ++ aarch64_build_constant (scratchreg, delta); ++ emit_insn (gen_add3_insn (this_rtx, this_rtx, scratch_rtx)); + } + else if (mdelta > 0) + { -+ const char *const mi_op = delta < 0 ? "sub" : "add"; -+ + if (mdelta >= 4096) -+ asm_fprintf (file, "\t%s\t%r, %r, %wd, lsl 12\n", mi_op, regnum, regnum, -+ mdelta / 4096); ++ { ++ rtx shift; + ++ emit_insn (gen_rtx_SET (Pmode, scratch_rtx, GEN_INT (mdelta / 4096))); ++ shift = gen_rtx_ASHIFT (Pmode, scratch_rtx, GEN_INT (12)); ++ if (delta < 0) ++ emit_insn (gen_rtx_SET (Pmode, this_rtx, ++ gen_rtx_MINUS (Pmode, this_rtx, shift))); ++ else ++ emit_insn (gen_rtx_SET (Pmode, this_rtx, ++ gen_rtx_PLUS (Pmode, this_rtx, shift))); ++ } + if (mdelta % 4096 != 0) -+ asm_fprintf (file, "\t%s\t%r, %r, %wd\n", mi_op, regnum, regnum, -+ mdelta % 4096); ++ { ++ scratch_rtx = GEN_INT ((delta < 0 ? -1 : 1) * (mdelta % 4096)); ++ emit_insn (gen_rtx_SET (Pmode, this_rtx, ++ gen_rtx_PLUS (Pmode, this_rtx, scratch_rtx))); ++ } + } +} + @@ -6931,47 +7984,66 @@ + to return a pointer to an aggregate. On AArch64 a result value + pointer will be in x8. */ + int this_regno = R0_REGNUM; ++ rtx this_rtx, temp0, temp1, addr, insn, funexp; + -+ /* Make sure unwind info is emitted for the thunk if needed. */ -+ final_start_function (emit_barrier (), file, 1); ++ reload_completed = 1; ++ emit_note (NOTE_INSN_PROLOGUE_END); + + if (vcall_offset == 0) -+ aarch64_add_constant (file, this_regno, IP1_REGNUM, delta); ++ aarch64_add_constant (this_regno, IP1_REGNUM, delta); + else + { + gcc_assert ((vcall_offset & 0x7) == 0); + -+ if (delta == 0) -+ asm_fprintf (file, "\tldr\t%r, [%r]\n", IP0_REGNUM, this_regno); -+ else if (delta >= -256 && delta < 256) -+ asm_fprintf (file, "\tldr\t%r, [%r,%wd]!\n", IP0_REGNUM, this_regno, -+ delta); -+ else -+ { -+ aarch64_add_constant (file, this_regno, IP1_REGNUM, delta); -+ -+ asm_fprintf (file, "\tldr\t%r, [%r]\n", IP0_REGNUM, this_regno); ++ this_rtx = gen_rtx_REG (Pmode, this_regno); ++ temp0 = gen_rtx_REG (Pmode, IP0_REGNUM); ++ temp1 = gen_rtx_REG (Pmode, IP1_REGNUM); ++ ++ addr = this_rtx; ++ if (delta != 0) ++ { ++ if (delta >= -256 && delta < 256) ++ addr = gen_rtx_PRE_MODIFY (Pmode, this_rtx, ++ plus_constant (this_rtx, delta)); ++ else ++ aarch64_add_constant (this_regno, IP1_REGNUM, delta); + } + ++ aarch64_emit_move (temp0, gen_rtx_MEM (Pmode, addr)); ++ + if (vcall_offset >= -256 && vcall_offset < 32768) -+ asm_fprintf (file, "\tldr\t%r, [%r,%wd]\n", IP1_REGNUM, IP0_REGNUM, -+ vcall_offset); ++ addr = plus_constant (temp0, vcall_offset); + else + { -+ aarch64_build_constant (file, IP1_REGNUM, vcall_offset); -+ asm_fprintf (file, "\tldr\t%r, [%r,%r]\n", IP1_REGNUM, IP0_REGNUM, -+ IP1_REGNUM); ++ aarch64_build_constant (IP1_REGNUM, vcall_offset); ++ addr = gen_rtx_PLUS (Pmode, temp0, temp1); + } + -+ asm_fprintf (file, "\tadd\t%r, %r, %r\n", this_regno, this_regno, -+ IP1_REGNUM); ++ aarch64_emit_move (temp1, gen_rtx_MEM (Pmode,addr)); ++ emit_insn (gen_add2_insn (this_rtx, temp1)); + } + -+ output_asm_insn ("b\t%a0", &XEXP (DECL_RTL (function), 0)); ++ /* Generate a tail call to the target function. */ ++ if (!TREE_USED (function)) ++ { ++ assemble_external (function); ++ TREE_USED (function) = 1; ++ } ++ funexp = XEXP (DECL_RTL (function), 0); ++ funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); ++ insn = emit_call_insn (gen_sibcall (funexp, const0_rtx, NULL_RTX)); ++ SIBLING_CALL_P (insn) = 1; ++ ++ insn = get_insns (); ++ shorten_branches (insn); ++ final_start_function (insn, file, 1); ++ final (insn, file, 1); + final_end_function (); ++ ++ /* Stop pretending to be a post-reload pass. */ ++ reload_completed = 0; +} + -+ +static int +aarch64_tls_operand_p_1 (rtx *x, void *data ATTRIBUTE_UNUSED) +{ @@ -7594,7 +8666,7 @@ + +/* Return TRUE if rtx X is immediate constant 0.0 */ +bool -+aarch64_const_double_zero_rtx_p (rtx x) ++aarch64_float_const_zero_rtx_p (rtx x) +{ + REAL_VALUE_TYPE r; + @@ -7607,6 +8679,16 @@ + return REAL_VALUES_EQUAL (r, dconst0); +} + ++/* Return the fixed registers used for condition codes. */ ++ ++static bool ++aarch64_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2) ++{ ++ *p1 = CC_REGNUM; ++ *p2 = INVALID_REGNUM; ++ return true; ++} ++ +enum machine_mode +aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y) +{ @@ -7834,7 +8916,7 @@ + return; + } + -+ asm_fprintf (f, "%r", REGNO (x) + 1); ++ asm_fprintf (f, "%s", reg_names [REGNO (x) + 1]); + break; + + case 'Q': @@ -7844,7 +8926,7 @@ + output_operand_lossage ("invalid operand for '%%%c'", code); + return; + } -+ asm_fprintf (f, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)); ++ asm_fprintf (f, "%s", reg_names [REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)]); + break; + + case 'R': @@ -7854,7 +8936,7 @@ + output_operand_lossage ("invalid operand for '%%%c'", code); + return; + } -+ asm_fprintf (f, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)); ++ asm_fprintf (f, "%s", reg_names [REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)]); + break; + + case 'm': @@ -7925,7 +9007,8 @@ + case 'x': + /* Print a general register name or the zero register (32-bit or + 64-bit). */ -+ if (x == const0_rtx) ++ if (x == const0_rtx ++ || (CONST_DOUBLE_P (x) && aarch64_float_const_zero_rtx_p (x))) + { + asm_fprintf (f, "%s%czr", REGISTER_PREFIX, code); + break; @@ -7958,7 +9041,7 @@ + switch (GET_CODE (x)) + { + case REG: -+ asm_fprintf (f, "%r", REGNO (x)); ++ asm_fprintf (f, "%s", reg_names [REGNO (x)]); + break; + + case MEM: @@ -7976,11 +9059,46 @@ + break; + + case CONST_VECTOR: -+ gcc_assert (aarch64_const_vec_all_same_int_p (x, HOST_WIDE_INT_MIN, -+ HOST_WIDE_INT_MAX)); -+ asm_fprintf (f, "%wd", INTVAL (CONST_VECTOR_ELT (x, 0))); ++ if (GET_MODE_CLASS (GET_MODE (x)) == MODE_VECTOR_INT) ++ { ++ gcc_assert (aarch64_const_vec_all_same_int_p (x, ++ HOST_WIDE_INT_MIN, ++ HOST_WIDE_INT_MAX)); ++ asm_fprintf (f, "%wd", INTVAL (CONST_VECTOR_ELT (x, 0))); ++ } ++ else if (aarch64_simd_imm_zero_p (x, GET_MODE (x))) ++ { ++ fputc ('0', f); ++ } ++ else ++ gcc_unreachable (); + break; + ++ case CONST_DOUBLE: ++ /* CONST_DOUBLE can represent a double-width integer. ++ In this case, the mode of x is VOIDmode. */ ++ if (GET_MODE (x) == VOIDmode) ++ ; /* Do Nothing. */ ++ else if (aarch64_float_const_zero_rtx_p (x)) ++ { ++ fputc ('0', f); ++ break; ++ } ++ else if (aarch64_float_const_representable_p (x)) ++ { ++#define buf_size 20 ++ char float_buf[buf_size] = {'\0'}; ++ REAL_VALUE_TYPE r; ++ REAL_VALUE_FROM_CONST_DOUBLE (r, x); ++ real_to_decimal_for_mode (float_buf, &r, ++ buf_size, buf_size, ++ 1, GET_MODE (x)); ++ asm_fprintf (asm_out_file, "%s", float_buf); ++ break; ++#undef buf_size ++ } ++ output_operand_lossage ("invalid constant"); ++ return; + default: + output_operand_lossage ("invalid operand"); + return; @@ -8078,36 +9196,36 @@ + { + case ADDRESS_REG_IMM: + if (addr.offset == const0_rtx) -+ asm_fprintf (f, "[%r]", REGNO (addr.base)); ++ asm_fprintf (f, "[%s]", reg_names [REGNO (addr.base)]); + else -+ asm_fprintf (f, "[%r,%wd]", REGNO (addr.base), ++ asm_fprintf (f, "[%s,%wd]", reg_names [REGNO (addr.base)], + INTVAL (addr.offset)); + return; + + case ADDRESS_REG_REG: + if (addr.shift == 0) -+ asm_fprintf (f, "[%r,%r]", REGNO (addr.base), -+ REGNO (addr.offset)); ++ asm_fprintf (f, "[%s,%s]", reg_names [REGNO (addr.base)], ++ reg_names [REGNO (addr.offset)]); + else -+ asm_fprintf (f, "[%r,%r,lsl %u]", REGNO (addr.base), -+ REGNO (addr.offset), addr.shift); ++ asm_fprintf (f, "[%s,%s,lsl %u]", reg_names [REGNO (addr.base)], ++ reg_names [REGNO (addr.offset)], addr.shift); + return; + + case ADDRESS_REG_UXTW: + if (addr.shift == 0) -+ asm_fprintf (f, "[%r,w%d,uxtw]", REGNO (addr.base), ++ asm_fprintf (f, "[%s,w%d,uxtw]", reg_names [REGNO (addr.base)], + REGNO (addr.offset) - R0_REGNUM); + else -+ asm_fprintf (f, "[%r,w%d,uxtw %u]", REGNO (addr.base), ++ asm_fprintf (f, "[%s,w%d,uxtw %u]", reg_names [REGNO (addr.base)], + REGNO (addr.offset) - R0_REGNUM, addr.shift); + return; + + case ADDRESS_REG_SXTW: + if (addr.shift == 0) -+ asm_fprintf (f, "[%r,w%d,sxtw]", REGNO (addr.base), ++ asm_fprintf (f, "[%s,w%d,sxtw]", reg_names [REGNO (addr.base)], + REGNO (addr.offset) - R0_REGNUM); + else -+ asm_fprintf (f, "[%r,w%d,sxtw %u]", REGNO (addr.base), ++ asm_fprintf (f, "[%s,w%d,sxtw %u]", reg_names [REGNO (addr.base)], + REGNO (addr.offset) - R0_REGNUM, addr.shift); + return; + @@ -8115,27 +9233,27 @@ + switch (GET_CODE (x)) + { + case PRE_INC: -+ asm_fprintf (f, "[%r,%d]!", REGNO (addr.base), ++ asm_fprintf (f, "[%s,%d]!", reg_names [REGNO (addr.base)], + GET_MODE_SIZE (aarch64_memory_reference_mode)); + return; + case POST_INC: -+ asm_fprintf (f, "[%r],%d", REGNO (addr.base), ++ asm_fprintf (f, "[%s],%d", reg_names [REGNO (addr.base)], + GET_MODE_SIZE (aarch64_memory_reference_mode)); + return; + case PRE_DEC: -+ asm_fprintf (f, "[%r,-%d]!", REGNO (addr.base), ++ asm_fprintf (f, "[%s,-%d]!", reg_names [REGNO (addr.base)], + GET_MODE_SIZE (aarch64_memory_reference_mode)); + return; + case POST_DEC: -+ asm_fprintf (f, "[%r],-%d", REGNO (addr.base), ++ asm_fprintf (f, "[%s],-%d", reg_names [REGNO (addr.base)], + GET_MODE_SIZE (aarch64_memory_reference_mode)); + return; + case PRE_MODIFY: -+ asm_fprintf (f, "[%r,%wd]!", REGNO (addr.base), ++ asm_fprintf (f, "[%s,%wd]!", reg_names [REGNO (addr.base)], + INTVAL (addr.offset)); + return; + case POST_MODIFY: -+ asm_fprintf (f, "[%r],%wd", REGNO (addr.base), ++ asm_fprintf (f, "[%s],%wd", reg_names [REGNO (addr.base)], + INTVAL (addr.offset)); + return; + default: @@ -8144,7 +9262,7 @@ + break; + + case ADDRESS_LO_SUM: -+ asm_fprintf (f, "[%r,#:lo12:", REGNO (addr.base)); ++ asm_fprintf (f, "[%s,#:lo12:", reg_names [REGNO (addr.base)]); + output_addr_const (f, addr.offset); + asm_fprintf (f, "]"); + return; @@ -8238,7 +9356,7 @@ + x = copy_rtx (x); + push_reload (orig_rtx, NULL_RTX, x_p, NULL, + BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, -+ opnum, type); ++ opnum, (enum reload_type) type); + return x; + } + @@ -8251,7 +9369,7 @@ + { + push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, + BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, -+ opnum, type); ++ opnum, (enum reload_type) type); + return x; + } + @@ -8315,7 +9433,7 @@ + + push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, + BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, -+ opnum, type); ++ opnum, (enum reload_type) type); + return x; + } + @@ -8456,9 +9574,9 @@ +static void +aarch64_asm_trampoline_template (FILE *f) +{ -+ asm_fprintf (f, "\tldr\t%r, .+16\n", IP1_REGNUM); -+ asm_fprintf (f, "\tldr\t%r, .+20\n", STATIC_CHAIN_REGNUM); -+ asm_fprintf (f, "\tbr\t%r\n", IP1_REGNUM); ++ asm_fprintf (f, "\tldr\t%s, .+16\n", reg_names [IP1_REGNUM]); ++ asm_fprintf (f, "\tldr\t%s, .+20\n", reg_names [STATIC_CHAIN_REGNUM]); ++ asm_fprintf (f, "\tbr\t%s\n", reg_names [IP1_REGNUM]); + assemble_aligned_integer (4, const0_rtx); + assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); + assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); @@ -8489,7 +9607,7 @@ + gen_clear_cache(). */ + a_tramp = XEXP (m_tramp, 0); + emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), -+ 0, VOIDmode, 2, a_tramp, Pmode, ++ LCT_NORMAL, VOIDmode, 2, a_tramp, Pmode, + plus_constant (a_tramp, TRAMPOLINE_SIZE), Pmode); +} + @@ -9104,71 +10222,6 @@ + +static void initialize_aarch64_code_model (void); + -+/* Tuning parameters. */ -+ -+#if HAVE_DESIGNATED_INITIALIZERS -+#define NAMED_PARAM(NAME, VAL) .NAME = (VAL) -+#else -+#define NAMED_PARAM(NAME, VAL) (VAL) -+#endif -+ -+#if HAVE_DESIGNATED_INITIALIZERS && GCC_VERSION >= 2007 -+__extension__ -+#endif -+static const struct cpu_rtx_cost_table generic_rtx_cost_table = -+{ -+ NAMED_PARAM (memory_load, COSTS_N_INSNS (1)), -+ NAMED_PARAM (memory_store, COSTS_N_INSNS (0)), -+ NAMED_PARAM (register_shift, COSTS_N_INSNS (1)), -+ NAMED_PARAM (int_divide, COSTS_N_INSNS (6)), -+ NAMED_PARAM (float_divide, COSTS_N_INSNS (2)), -+ NAMED_PARAM (double_divide, COSTS_N_INSNS (6)), -+ NAMED_PARAM (int_multiply, COSTS_N_INSNS (1)), -+ NAMED_PARAM (int_multiply_extend, COSTS_N_INSNS (1)), -+ NAMED_PARAM (int_multiply_add, COSTS_N_INSNS (1)), -+ NAMED_PARAM (int_multiply_extend_add, COSTS_N_INSNS (1)), -+ NAMED_PARAM (float_multiply, COSTS_N_INSNS (0)), -+ NAMED_PARAM (double_multiply, COSTS_N_INSNS (1)) -+}; -+ -+#if HAVE_DESIGNATED_INITIALIZERS && GCC_VERSION >= 2007 -+__extension__ -+#endif -+static const struct cpu_addrcost_table generic_addrcost_table = -+{ -+ NAMED_PARAM (pre_modify, 0), -+ NAMED_PARAM (post_modify, 0), -+ NAMED_PARAM (register_offset, 0), -+ NAMED_PARAM (register_extend, 0), -+ NAMED_PARAM (imm_offset, 0) -+}; -+ -+#if HAVE_DESIGNATED_INITIALIZERS && GCC_VERSION >= 2007 -+__extension__ -+#endif -+static const struct cpu_regmove_cost generic_regmove_cost = -+{ -+ NAMED_PARAM (GP2GP, 1), -+ NAMED_PARAM (GP2FP, 2), -+ NAMED_PARAM (FP2GP, 2), -+ /* We currently do not provide direct support for TFmode Q->Q move. -+ Therefore we need to raise the cost above 2 in order to have -+ reload handle the situation. */ -+ NAMED_PARAM (FP2FP, 4) -+}; -+ -+#if HAVE_DESIGNATED_INITIALIZERS && GCC_VERSION >= 2007 -+__extension__ -+#endif -+static const struct tune_params generic_tunings = -+{ -+ &generic_rtx_cost_table, -+ &generic_addrcost_table, -+ &generic_regmove_cost, -+ NAMED_PARAM (memmov_cost, 4) -+}; -+ -+ +/* Parse the architecture extension string. */ + +static void @@ -9626,6 +10679,27 @@ + return true; +} + ++/* Return true if X holds either a quarter-precision or ++ floating-point +0.0 constant. */ ++static bool ++aarch64_valid_floating_const (enum machine_mode mode, rtx x) ++{ ++ if (!CONST_DOUBLE_P (x)) ++ return false; ++ ++ /* TODO: We could handle moving 0.0 to a TFmode register, ++ but first we would like to refactor the movtf_aarch64 ++ to be more amicable to split moves properly and ++ correctly gate on TARGET_SIMD. For now - reject all ++ constants which are not to SFmode or DFmode registers. */ ++ if (!(mode == SFmode || mode == DFmode)) ++ return false; ++ ++ if (aarch64_float_const_zero_rtx_p (x)) ++ return true; ++ return aarch64_float_const_representable_p (x); ++} ++ +static bool +aarch64_legitimate_constant_p (enum machine_mode mode, rtx x) +{ @@ -9639,8 +10713,8 @@ + if ((GET_CODE (x) == CONST_VECTOR + && aarch64_simd_valid_immediate (x, mode, false, + NULL, NULL, NULL, NULL, NULL) != -1) -+ || CONST_INT_P (x)) -+ return !targetm.cannot_force_const_mem (mode, x); ++ || CONST_INT_P (x) || aarch64_valid_floating_const (mode, x)) ++ return !targetm.cannot_force_const_mem (mode, x); + + if (GET_CODE (x) == HIGH + && aarch64_valid_symref (XEXP (x, 0), GET_MODE (XEXP (x, 0)))) @@ -9649,23 +10723,7 @@ + return aarch64_constant_address_p (x); +} + -+static void -+aarch64_init_builtins (void) -+{ -+ tree ftype, decl = NULL; -+ -+ ftype = build_function_type (ptr_type_node, void_list_node); -+ decl = add_builtin_function ("__builtin_thread_pointer", ftype, -+ AARCH64_BUILTIN_THREAD_POINTER, BUILT_IN_MD, -+ NULL, NULL_TREE); -+ TREE_NOTHROW (decl) = 1; -+ TREE_READONLY (decl) = 1; -+ -+ if (TARGET_SIMD) -+ init_aarch64_simd_builtins (); -+} -+ -+static rtx ++rtx +aarch64_load_tp (rtx target) +{ + if (!target @@ -9678,27 +10736,6 @@ + return target; +} + -+/* Expand an expression EXP that calls a built-in function, -+ with result going to TARGET if that's convenient. */ -+static rtx -+aarch64_expand_builtin (tree exp, -+ rtx target, -+ rtx subtarget ATTRIBUTE_UNUSED, -+ enum machine_mode mode ATTRIBUTE_UNUSED, -+ int ignore ATTRIBUTE_UNUSED) -+{ -+ tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); -+ int fcode = DECL_FUNCTION_CODE (fndecl); -+ -+ if (fcode == AARCH64_BUILTIN_THREAD_POINTER) -+ return aarch64_load_tp (target); -+ -+ if (fcode >= AARCH64_SIMD_BUILTIN_BASE) -+ return aarch64_simd_expand_builtin (fcode, exp, target); -+ -+ return NULL_RTX; -+} -+ +/* On AAPCS systems, this is the "struct __va_list". */ +static GTY(()) tree va_list_type; + @@ -9731,6 +10768,7 @@ + va_list_type); + DECL_ARTIFICIAL (va_list_name) = 1; + TYPE_NAME (va_list_type) = va_list_name; ++ TYPE_STUB_DECL (va_list_type) = va_list_name; + + /* Create the fields. */ + f_stack = build_decl (BUILTINS_LOCATION, @@ -10531,396 +11569,144 @@ + return word_mode; +} + -+/* Legitimize a memory reference for sync primitive implemented using -+ LDXR/STXR instructions. We currently force the form of the reference -+ to be indirect without offset. */ -+static rtx -+aarch64_legitimize_sync_memory (rtx memory) -+{ -+ rtx addr = force_reg (Pmode, XEXP (memory, 0)); -+ rtx legitimate_memory = gen_rtx_MEM (GET_MODE (memory), addr); -+ -+ set_mem_alias_set (legitimate_memory, ALIAS_SET_MEMORY_BARRIER); -+ MEM_VOLATILE_P (legitimate_memory) = MEM_VOLATILE_P (memory); -+ return legitimate_memory; -+} -+ -+/* An instruction emitter. */ -+typedef void (* emit_f) (int label, const char *, rtx *); -+ -+/* An instruction emitter that emits via the conventional -+ output_asm_insn. */ -+static void -+aarch64_emit (int label ATTRIBUTE_UNUSED, const char *pattern, rtx *operands) -+{ -+ output_asm_insn (pattern, operands); -+} -+ -+/* Count the number of emitted synchronization instructions. */ -+static unsigned aarch64_insn_count; -+ -+/* An emitter that counts emitted instructions but does not actually -+ emit instruction into the the instruction stream. */ -+static void -+aarch64_count (int label, -+ const char *pattern ATTRIBUTE_UNUSED, -+ rtx *operands ATTRIBUTE_UNUSED) ++/* Return the bitmask of possible vector sizes for the vectorizer ++ to iterate over. */ ++static unsigned int ++aarch64_autovectorize_vector_sizes (void) +{ -+ if (! label) -+ ++ aarch64_insn_count; ++ return (16 | 8); +} + -+static void -+aarch64_output_asm_insn (emit_f, int, rtx *, -+ const char *, ...) ATTRIBUTE_PRINTF_4; -+ -+/* Construct a pattern using conventional output formatting and feed -+ it to output_asm_insn. Provides a mechanism to construct the -+ output pattern on the fly. Note the hard limit on the pattern -+ buffer size. */ -+static void -+aarch64_output_asm_insn (emit_f emit, int label, rtx *operands, -+ const char *pattern, ...) ++/* A table to help perform AArch64-specific name mangling for AdvSIMD ++ vector types in order to conform to the AAPCS64 (see "Procedure ++ Call Standard for the ARM 64-bit Architecture", Appendix A). To ++ qualify for emission with the mangled names defined in that document, ++ a vector type must not only be of the correct mode but also be ++ composed of AdvSIMD vector element types (e.g. ++ _builtin_aarch64_simd_qi); these types are registered by ++ aarch64_init_simd_builtins (). In other words, vector types defined ++ in other ways e.g. via vector_size attribute will get default ++ mangled names. */ ++typedef struct +{ -+ va_list ap; -+ char buffer[256]; ++ enum machine_mode mode; ++ const char *element_type_name; ++ const char *mangled_name; ++} aarch64_simd_mangle_map_entry; ++ ++static aarch64_simd_mangle_map_entry aarch64_simd_mangle_map[] = { ++ /* 64-bit containerized types. */ ++ { V8QImode, "__builtin_aarch64_simd_qi", "10__Int8x8_t" }, ++ { V8QImode, "__builtin_aarch64_simd_uqi", "11__Uint8x8_t" }, ++ { V4HImode, "__builtin_aarch64_simd_hi", "11__Int16x4_t" }, ++ { V4HImode, "__builtin_aarch64_simd_uhi", "12__Uint16x4_t" }, ++ { V2SImode, "__builtin_aarch64_simd_si", "11__Int32x2_t" }, ++ { V2SImode, "__builtin_aarch64_simd_usi", "12__Uint32x2_t" }, ++ { V2SFmode, "__builtin_aarch64_simd_sf", "13__Float32x2_t" }, ++ { V8QImode, "__builtin_aarch64_simd_poly8", "11__Poly8x8_t" }, ++ { V4HImode, "__builtin_aarch64_simd_poly16", "12__Poly16x4_t" }, ++ /* 128-bit containerized types. */ ++ { V16QImode, "__builtin_aarch64_simd_qi", "11__Int8x16_t" }, ++ { V16QImode, "__builtin_aarch64_simd_uqi", "12__Uint8x16_t" }, ++ { V8HImode, "__builtin_aarch64_simd_hi", "11__Int16x8_t" }, ++ { V8HImode, "__builtin_aarch64_simd_uhi", "12__Uint16x8_t" }, ++ { V4SImode, "__builtin_aarch64_simd_si", "11__Int32x4_t" }, ++ { V4SImode, "__builtin_aarch64_simd_usi", "12__Uint32x4_t" }, ++ { V2DImode, "__builtin_aarch64_simd_di", "11__Int64x2_t" }, ++ { V2DImode, "__builtin_aarch64_simd_udi", "12__Uint64x2_t" }, ++ { V4SFmode, "__builtin_aarch64_simd_sf", "13__Float32x4_t" }, ++ { V2DFmode, "__builtin_aarch64_simd_df", "13__Float64x2_t" }, ++ { V16QImode, "__builtin_aarch64_simd_poly8", "12__Poly8x16_t" }, ++ { V8HImode, "__builtin_aarch64_simd_poly16", "12__Poly16x8_t" }, ++ { VOIDmode, NULL, NULL } ++}; + -+ va_start (ap, pattern); -+ vsnprintf (buffer, sizeof (buffer), pattern, ap); -+ va_end (ap); -+ emit (label, buffer, operands); -+} ++/* Implement TARGET_MANGLE_TYPE. */ + -+/* Helper to figure out the instruction suffix required on LDXR/STXR -+ instructions for operations on an object of the specified mode. */ +static const char * -+aarch64_load_store_suffix (enum machine_mode mode) ++aarch64_mangle_type (const_tree type) +{ -+ switch (mode) ++ /* The AArch64 ABI documents say that "__va_list" has to be ++ managled as if it is in the "std" namespace. */ ++ if (lang_hooks.types_compatible_p (CONST_CAST_TREE (type), va_list_type)) ++ return "St9__va_list"; ++ ++ /* Check the mode of the vector type, and the name of the vector ++ element type, against the table. */ ++ if (TREE_CODE (type) == VECTOR_TYPE) + { -+ case QImode: return "b"; -+ case HImode: return "h"; -+ case SImode: return ""; -+ case DImode: return ""; -+ default: -+ gcc_unreachable (); -+ } -+ return ""; -+} ++ aarch64_simd_mangle_map_entry *pos = aarch64_simd_mangle_map; + -+/* Emit an excluive load instruction appropriate for the specified -+ mode. */ -+static void -+aarch64_output_sync_load (emit_f emit, -+ enum machine_mode mode, -+ rtx target, -+ rtx memory, -+ bool with_barrier) -+{ -+ const char *suffix = aarch64_load_store_suffix (mode); -+ rtx operands[2]; -+ -+ operands[0] = target; -+ operands[1] = memory; -+ aarch64_output_asm_insn (emit, 0, operands, "ld%sxr%s\t%%%s0, %%1", -+ with_barrier ? "a" : "", suffix, -+ mode == DImode ? "x" : "w"); -+} ++ while (pos->mode != VOIDmode) ++ { ++ tree elt_type = TREE_TYPE (type); + -+/* Emit an exclusive store instruction appropriate for the specified -+ mode. */ -+static void -+aarch64_output_sync_store (emit_f emit, -+ enum machine_mode mode, -+ rtx result, -+ rtx value, -+ rtx memory, -+ bool with_barrier) -+{ -+ const char *suffix = aarch64_load_store_suffix (mode); -+ rtx operands[3]; -+ -+ operands[0] = result; -+ operands[1] = value; -+ operands[2] = memory; -+ aarch64_output_asm_insn (emit, 0, operands, -+ "st%sxr%s\t%%w0, %%%s1, %%2", -+ with_barrier ? "l" : "", -+ suffix, -+ mode == DImode ? "x" : "w"); -+} ++ if (pos->mode == TYPE_MODE (type) ++ && TREE_CODE (TYPE_NAME (elt_type)) == TYPE_DECL ++ && !strcmp (IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (elt_type))), ++ pos->element_type_name)) ++ return pos->mangled_name; + -+/* Helper to emit a two operand instruction. */ -+static void -+aarch64_output_op2 (emit_f emit, const char *mnemonic, rtx d, rtx s) -+{ -+ rtx operands[2]; -+ enum machine_mode mode; -+ const char *constraint; ++ pos++; ++ } ++ } + -+ mode = GET_MODE (d); -+ operands[0] = d; -+ operands[1] = s; -+ constraint = mode == DImode ? "" : "w"; -+ aarch64_output_asm_insn (emit, 0, operands, "%s\t%%%s0, %%%s1", mnemonic, -+ constraint, constraint); ++ /* Use the default mangling. */ ++ return NULL; +} + -+/* Helper to emit a three operand instruction. */ -+static void -+aarch64_output_op3 (emit_f emit, const char *mnemonic, rtx d, rtx a, rtx b) ++/* Return the equivalent letter for size. */ ++static unsigned char ++sizetochar (int size) +{ -+ rtx operands[3]; -+ enum machine_mode mode; -+ const char *constraint; -+ -+ mode = GET_MODE (d); -+ operands[0] = d; -+ operands[1] = a; -+ operands[2] = b; -+ -+ constraint = mode == DImode ? "" : "w"; -+ aarch64_output_asm_insn (emit, 0, operands, "%s\t%%%s0, %%%s1, %%%s2", -+ mnemonic, constraint, constraint, constraint); ++ switch (size) ++ { ++ case 64: return 'd'; ++ case 32: return 's'; ++ case 16: return 'h'; ++ case 8 : return 'b'; ++ default: gcc_unreachable (); ++ } +} + -+/* Emit a load store exclusive synchronization loop. -+ -+ do -+ old_value = [mem] -+ if old_value != required_value -+ break; -+ t1 = sync_op (old_value, new_value) -+ [mem] = t1, t2 = [0|1] -+ while ! t2 -+ -+ Note: -+ t1 == t2 is not permitted -+ t1 == old_value is permitted -+ -+ required_value: -+ -+ RTX register or const_int representing the required old_value for -+ the modify to continue, if NULL no comparsion is performed. */ -+static void -+aarch64_output_sync_loop (emit_f emit, -+ enum machine_mode mode, -+ rtx old_value, -+ rtx memory, -+ rtx required_value, -+ rtx new_value, -+ rtx t1, -+ rtx t2, -+ enum attr_sync_op sync_op, -+ int acquire_barrier, -+ int release_barrier) ++/* Return true iff x is a uniform vector of floating-point ++ constants, and the constant can be represented in ++ quarter-precision form. Note, as aarch64_float_const_representable ++ rejects both +0.0 and -0.0, we will also reject +0.0 and -0.0. */ ++static bool ++aarch64_vect_float_const_representable_p (rtx x) +{ -+ rtx operands[1]; ++ int i = 0; ++ REAL_VALUE_TYPE r0, ri; ++ rtx x0, xi; + -+ gcc_assert (t1 != t2); ++ if (GET_MODE_CLASS (GET_MODE (x)) != MODE_VECTOR_FLOAT) ++ return false; + -+ aarch64_output_asm_insn (emit, 1, operands, "%sLSYT%%=:", LOCAL_LABEL_PREFIX); ++ x0 = CONST_VECTOR_ELT (x, 0); ++ if (!CONST_DOUBLE_P (x0)) ++ return false; + -+ aarch64_output_sync_load (emit, mode, old_value, memory, acquire_barrier); ++ REAL_VALUE_FROM_CONST_DOUBLE (r0, x0); + -+ if (required_value) ++ for (i = 1; i < CONST_VECTOR_NUNITS (x); i++) + { -+ rtx operands[2]; ++ xi = CONST_VECTOR_ELT (x, i); ++ if (!CONST_DOUBLE_P (xi)) ++ return false; + -+ operands[0] = old_value; -+ operands[1] = required_value; -+ aarch64_output_asm_insn (emit, 0, operands, "cmp\t%%0, %%1"); -+ aarch64_output_asm_insn (emit, 0, operands, "bne\t%sLSYB%%=", -+ LOCAL_LABEL_PREFIX); ++ REAL_VALUE_FROM_CONST_DOUBLE (ri, xi); ++ if (!REAL_VALUES_EQUAL (r0, ri)) ++ return false; + } + -+ switch (sync_op) -+ { -+ case SYNC_OP_ADD: -+ aarch64_output_op3 (emit, "add", t1, old_value, new_value); -+ break; -+ -+ case SYNC_OP_SUB: -+ aarch64_output_op3 (emit, "sub", t1, old_value, new_value); -+ break; -+ -+ case SYNC_OP_IOR: -+ aarch64_output_op3 (emit, "orr", t1, old_value, new_value); -+ break; -+ -+ case SYNC_OP_XOR: -+ aarch64_output_op3 (emit, "eor", t1, old_value, new_value); -+ break; -+ -+ case SYNC_OP_AND: -+ aarch64_output_op3 (emit,"and", t1, old_value, new_value); -+ break; -+ -+ case SYNC_OP_NAND: -+ aarch64_output_op3 (emit, "and", t1, old_value, new_value); -+ aarch64_output_op2 (emit, "mvn", t1, t1); -+ break; -+ -+ case SYNC_OP_NONE: -+ t1 = new_value; -+ break; -+ } -+ -+ aarch64_output_sync_store (emit, mode, t2, t1, memory, release_barrier); -+ operands[0] = t2; -+ aarch64_output_asm_insn (emit, 0, operands, "cbnz\t%%w0, %sLSYT%%=", -+ LOCAL_LABEL_PREFIX); -+ -+ aarch64_output_asm_insn (emit, 1, operands, "%sLSYB%%=:", LOCAL_LABEL_PREFIX); -+} -+ -+static rtx -+aarch64_get_sync_operand (rtx *operands, int index, rtx default_value) -+{ -+ if (index > 0) -+ default_value = operands[index - 1]; -+ -+ return default_value; -+} -+ -+#define FETCH_SYNC_OPERAND(NAME, DEFAULT) \ -+ aarch64_get_sync_operand (operands, (int) get_attr_sync_##NAME (insn), \ -+ DEFAULT); -+ -+/* Extract the operands for a synchroniztion instruction from the -+ instructions attributes and emit the instruction. */ -+static void -+aarch64_process_output_sync_insn (emit_f emit, rtx insn, rtx *operands) -+{ -+ rtx result, memory, required_value, new_value, t1, t2; -+ int release_barrier; -+ int acquire_barrier = 1; -+ enum machine_mode mode; -+ enum attr_sync_op sync_op; -+ -+ result = FETCH_SYNC_OPERAND (result, 0); -+ memory = FETCH_SYNC_OPERAND (memory, 0); -+ required_value = FETCH_SYNC_OPERAND (required_value, 0); -+ new_value = FETCH_SYNC_OPERAND (new_value, 0); -+ t1 = FETCH_SYNC_OPERAND (t1, 0); -+ t2 = FETCH_SYNC_OPERAND (t2, 0); -+ release_barrier = -+ get_attr_sync_release_barrier (insn) == SYNC_RELEASE_BARRIER_YES; -+ sync_op = get_attr_sync_op (insn); -+ mode = GET_MODE (memory); -+ -+ aarch64_output_sync_loop (emit, mode, result, memory, required_value, -+ new_value, t1, t2, sync_op, acquire_barrier, -+ release_barrier); -+} -+ -+/* Emit a synchronization instruction loop. */ -+const char * -+aarch64_output_sync_insn (rtx insn, rtx *operands) -+{ -+ aarch64_process_output_sync_insn (aarch64_emit, insn, operands); -+ return ""; -+} -+ -+/* Emit a store release instruction appropriate for the specified -+ mode. */ -+const char * -+aarch64_output_sync_lock_release (rtx value, rtx memory) -+{ -+ const char *suffix; -+ enum machine_mode mode; -+ rtx operands[2]; -+ operands[0] = value; -+ operands[1] = memory; -+ mode = GET_MODE (memory); -+ suffix = aarch64_load_store_suffix (mode); -+ aarch64_output_asm_insn (aarch64_emit, 0, operands, -+ "stlr%s\t%%%s0, %%1", -+ suffix, -+ mode == DImode ? "x" : "w"); -+ return ""; -+} -+ -+/* Count the number of machine instruction that will be emitted for a -+ synchronization instruction. Note that the emitter used does not -+ emit instructions, it just counts instructions being careful not -+ to count labels. */ -+unsigned int -+aarch64_sync_loop_insns (rtx insn, rtx *operands) -+{ -+ aarch64_insn_count = 0; -+ aarch64_process_output_sync_insn (aarch64_count, insn, operands); -+ return aarch64_insn_count; -+} -+ -+/* Helper to call a target sync instruction generator, dealing with -+ the variation in operands required by the different generators. */ -+static rtx -+aarch64_call_generator (struct aarch64_sync_generator *generator, rtx old_value, -+ rtx memory, rtx required_value, rtx new_value) -+{ -+ switch (generator->op) -+ { -+ case aarch64_sync_generator_omn: -+ gcc_assert (! required_value); -+ return generator->u.omn (old_value, memory, new_value); -+ -+ case aarch64_sync_generator_omrn: -+ gcc_assert (required_value); -+ return generator->u.omrn (old_value, memory, required_value, new_value); -+ } -+ -+ return NULL; -+} -+ -+/* Expand a synchronization loop. The synchronization loop is -+ expanded as an opaque block of instructions in order to ensure that -+ we do not subsequently get extraneous memory accesses inserted -+ within the critical region. The exclusive access property of -+ LDXR/STXR instructions is only guaranteed if there are no intervening -+ memory accesses. */ -+void -+aarch64_expand_sync (enum machine_mode mode, -+ struct aarch64_sync_generator *generator, -+ rtx target, rtx memory, rtx required_value, rtx new_value) -+{ -+ if (target == NULL) -+ target = gen_reg_rtx (mode); -+ -+ memory = aarch64_legitimize_sync_memory (memory); -+ if (mode != SImode && mode != DImode) -+ { -+ rtx load_temp = gen_reg_rtx (SImode); -+ -+ if (required_value) -+ required_value = convert_modes (SImode, mode, required_value, true); -+ -+ new_value = convert_modes (SImode, mode, new_value, true); -+ emit_insn (aarch64_call_generator (generator, load_temp, memory, -+ required_value, new_value)); -+ emit_move_insn (target, gen_lowpart (mode, load_temp)); -+ } -+ else -+ { -+ emit_insn (aarch64_call_generator (generator, target, memory, -+ required_value, new_value)); -+ } -+} -+ -+/* Return the equivalent letter for size. */ -+static unsigned char -+sizetochar (int size) -+{ -+ switch (size) -+ { -+ case 64: return 'd'; -+ case 32: return 's'; -+ case 16: return 'h'; -+ case 8 : return 'b'; -+ default: gcc_unreachable (); -+ } -+} ++ return aarch64_float_const_representable_p (x0); ++} + ++/* TODO: This function returns values similar to those ++ returned by neon_valid_immediate in gcc/config/arm/arm.c ++ but the API here is different enough that these magic numbers ++ are not used. It should be sufficient to return true or false. */ +static int +aarch64_simd_valid_immediate (rtx op, enum machine_mode mode, int inverse, + rtx *modconst, int *elementwidth, @@ -10950,9 +11736,32 @@ + unsigned int invmask = inverse ? 0xff : 0; + int eshift, emvn; + -+ /* TODO: Vectors of float constants. */ + if (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) -+ return -1; ++ { ++ bool simd_imm_zero = aarch64_simd_imm_zero_p (op, mode); ++ int elem_width = GET_MODE_BITSIZE (GET_MODE (CONST_VECTOR_ELT (op, 0))); ++ ++ if (!(simd_imm_zero ++ || aarch64_vect_float_const_representable_p (op))) ++ return -1; ++ ++ if (modconst) ++ *modconst = CONST_VECTOR_ELT (op, 0); ++ ++ if (elementwidth) ++ *elementwidth = elem_width; ++ ++ if (elementchar) ++ *elementchar = sizetochar (elem_width); ++ ++ if (shift) ++ *shift = 0; ++ ++ if (simd_imm_zero) ++ return 19; ++ else ++ return 18; ++ } + + /* Splat vector constant out into a byte vector. */ + for (i = 0; i < n_elts; i++) @@ -11107,8 +11916,8 @@ + +/* Return TRUE if rtx X is legal for use as either a AdvSIMD MOVI instruction + (or, implicitly, MVNI) immediate. Write back width per element -+ to *ELEMENTWIDTH (or zero for float elements), and a modified constant -+ (whatever should be output for a MOVI instruction) in *MODCONST. */ ++ to *ELEMENTWIDTH, and a modified constant (whatever should be output ++ for a MOVI instruction) in *MODCONST. */ +int +aarch64_simd_immediate_valid_for_move (rtx op, enum machine_mode mode, + rtx *modconst, int *elementwidth, @@ -11179,22 +11988,13 @@ + return aarch64_const_vec_all_same_int_p (x, 1, bit_width); +} + ++/* Return true if X is a uniform vector where all elements ++ are either the floating-point constant 0.0 or the ++ integer constant 0. */ +bool +aarch64_simd_imm_zero_p (rtx x, enum machine_mode mode) +{ -+ int nunits; -+ int i; -+ -+ if (GET_CODE (x) != CONST_VECTOR) -+ return false; -+ -+ nunits = GET_MODE_NUNITS (mode); -+ -+ for (i = 0; i < nunits; i++) -+ if (INTVAL (CONST_VECTOR_ELT (x, i)) != 0) -+ return false; -+ -+ return true; ++ return x == CONST0_RTX (mode); +} + +bool @@ -11261,8 +12061,10 @@ +void +aarch64_simd_const_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high) +{ ++ HOST_WIDE_INT lane; ++ + gcc_assert (GET_CODE (operand) == CONST_INT); -+ HOST_WIDE_INT lane = INTVAL (operand); ++ lane = INTVAL (operand); + + if (lane < low || lane >= high) + error ("constant out of range"); @@ -11338,8 +12140,6 @@ +int +aarch64_simd_attr_length_move (rtx insn) +{ -+ rtx reg, mem, addr; -+ int load; + enum machine_mode mode; + + extract_insn_cached (insn); @@ -11362,6 +12162,191 @@ + return 4; +} + ++/* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum ++ alignment of a vector to 128 bits. */ ++static HOST_WIDE_INT ++aarch64_simd_vector_alignment (const_tree type) ++{ ++ HOST_WIDE_INT align = tree_low_cst (TYPE_SIZE (type), 0); ++ return MIN (align, 128); ++} ++ ++/* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */ ++static bool ++aarch64_simd_vector_alignment_reachable (const_tree type, bool is_packed) ++{ ++ if (is_packed) ++ return false; ++ ++ /* We guarantee alignment for vectors up to 128-bits. */ ++ if (tree_int_cst_compare (TYPE_SIZE (type), ++ bitsize_int (BIGGEST_ALIGNMENT)) > 0) ++ return false; ++ ++ /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */ ++ return true; ++} ++ ++/* If VALS is a vector constant that can be loaded into a register ++ using DUP, generate instructions to do so and return an RTX to ++ assign to the register. Otherwise return NULL_RTX. */ ++static rtx ++aarch64_simd_dup_constant (rtx vals) ++{ ++ enum machine_mode mode = GET_MODE (vals); ++ enum machine_mode inner_mode = GET_MODE_INNER (mode); ++ int n_elts = GET_MODE_NUNITS (mode); ++ bool all_same = true; ++ rtx x; ++ int i; ++ ++ if (GET_CODE (vals) != CONST_VECTOR) ++ return NULL_RTX; ++ ++ for (i = 1; i < n_elts; ++i) ++ { ++ x = CONST_VECTOR_ELT (vals, i); ++ if (!rtx_equal_p (x, CONST_VECTOR_ELT (vals, 0))) ++ all_same = false; ++ } ++ ++ if (!all_same) ++ return NULL_RTX; ++ ++ /* We can load this constant by using DUP and a constant in a ++ single ARM register. This will be cheaper than a vector ++ load. */ ++ x = copy_to_mode_reg (inner_mode, CONST_VECTOR_ELT (vals, 0)); ++ return gen_rtx_VEC_DUPLICATE (mode, x); ++} ++ ++ ++/* Generate code to load VALS, which is a PARALLEL containing only ++ constants (for vec_init) or CONST_VECTOR, efficiently into a ++ register. Returns an RTX to copy into the register, or NULL_RTX ++ for a PARALLEL that can not be converted into a CONST_VECTOR. */ ++static rtx ++aarch64_simd_make_constant (rtx vals) ++{ ++ enum machine_mode mode = GET_MODE (vals); ++ rtx const_dup; ++ rtx const_vec = NULL_RTX; ++ int n_elts = GET_MODE_NUNITS (mode); ++ int n_const = 0; ++ int i; ++ ++ if (GET_CODE (vals) == CONST_VECTOR) ++ const_vec = vals; ++ else if (GET_CODE (vals) == PARALLEL) ++ { ++ /* A CONST_VECTOR must contain only CONST_INTs and ++ CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF). ++ Only store valid constants in a CONST_VECTOR. */ ++ for (i = 0; i < n_elts; ++i) ++ { ++ rtx x = XVECEXP (vals, 0, i); ++ if (CONST_INT_P (x) || CONST_DOUBLE_P (x)) ++ n_const++; ++ } ++ if (n_const == n_elts) ++ const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)); ++ } ++ else ++ gcc_unreachable (); ++ ++ if (const_vec != NULL_RTX ++ && aarch64_simd_immediate_valid_for_move (const_vec, mode, NULL, NULL, ++ NULL, NULL, NULL)) ++ /* Load using MOVI/MVNI. */ ++ return const_vec; ++ else if ((const_dup = aarch64_simd_dup_constant (vals)) != NULL_RTX) ++ /* Loaded using DUP. */ ++ return const_dup; ++ else if (const_vec != NULL_RTX) ++ /* Load from constant pool. We can not take advantage of single-cycle ++ LD1 because we need a PC-relative addressing mode. */ ++ return const_vec; ++ else ++ /* A PARALLEL containing something not valid inside CONST_VECTOR. ++ We can not construct an initializer. */ ++ return NULL_RTX; ++} ++ ++void ++aarch64_expand_vector_init (rtx target, rtx vals) ++{ ++ enum machine_mode mode = GET_MODE (target); ++ enum machine_mode inner_mode = GET_MODE_INNER (mode); ++ int n_elts = GET_MODE_NUNITS (mode); ++ int n_var = 0, one_var = -1; ++ bool all_same = true; ++ rtx x, mem; ++ int i; ++ ++ x = XVECEXP (vals, 0, 0); ++ if (!CONST_INT_P (x) && !CONST_DOUBLE_P (x)) ++ n_var = 1, one_var = 0; ++ ++ for (i = 1; i < n_elts; ++i) ++ { ++ x = XVECEXP (vals, 0, i); ++ if (!CONST_INT_P (x) && !CONST_DOUBLE_P (x)) ++ ++n_var, one_var = i; ++ ++ if (!rtx_equal_p (x, XVECEXP (vals, 0, 0))) ++ all_same = false; ++ } ++ ++ if (n_var == 0) ++ { ++ rtx constant = aarch64_simd_make_constant (vals); ++ if (constant != NULL_RTX) ++ { ++ emit_move_insn (target, constant); ++ return; ++ } ++ } ++ ++ /* Splat a single non-constant element if we can. */ ++ if (all_same) ++ { ++ x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, 0)); ++ aarch64_emit_move (target, gen_rtx_VEC_DUPLICATE (mode, x)); ++ return; ++ } ++ ++ /* One field is non-constant. Load constant then overwrite varying ++ field. This is more efficient than using the stack. */ ++ if (n_var == 1) ++ { ++ rtx copy = copy_rtx (vals); ++ rtx index = GEN_INT (one_var); ++ enum insn_code icode; ++ ++ /* Load constant part of vector, substitute neighboring value for ++ varying element. */ ++ XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, one_var ^ 1); ++ aarch64_expand_vector_init (target, copy); ++ ++ /* Insert variable. */ ++ x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, one_var)); ++ icode = optab_handler (vec_set_optab, mode); ++ gcc_assert (icode != CODE_FOR_nothing); ++ emit_insn (GEN_FCN (icode) (target, x, index)); ++ return; ++ } ++ ++ /* Construct the vector in memory one field at a time ++ and load the whole vector. */ ++ mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0); ++ for (i = 0; i < n_elts; i++) ++ emit_move_insn (adjust_address_nv (mem, inner_mode, ++ i * GET_MODE_SIZE (inner_mode)), ++ XVECEXP (vals, 0, i)); ++ emit_move_insn (target, mem); ++ ++} ++ +static unsigned HOST_WIDE_INT +aarch64_shift_truncation_mask (enum machine_mode mode) +{ @@ -11467,6 +12452,241 @@ + return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type; +} + ++/* Emit load exclusive. */ ++ ++static void ++aarch64_emit_load_exclusive (enum machine_mode mode, rtx rval, ++ rtx mem, rtx model_rtx) ++{ ++ rtx (*gen) (rtx, rtx, rtx); ++ ++ switch (mode) ++ { ++ case QImode: gen = gen_aarch64_load_exclusiveqi; break; ++ case HImode: gen = gen_aarch64_load_exclusivehi; break; ++ case SImode: gen = gen_aarch64_load_exclusivesi; break; ++ case DImode: gen = gen_aarch64_load_exclusivedi; break; ++ default: ++ gcc_unreachable (); ++ } ++ ++ emit_insn (gen (rval, mem, model_rtx)); ++} ++ ++/* Emit store exclusive. */ ++ ++static void ++aarch64_emit_store_exclusive (enum machine_mode mode, rtx bval, ++ rtx rval, rtx mem, rtx model_rtx) ++{ ++ rtx (*gen) (rtx, rtx, rtx, rtx); ++ ++ switch (mode) ++ { ++ case QImode: gen = gen_aarch64_store_exclusiveqi; break; ++ case HImode: gen = gen_aarch64_store_exclusivehi; break; ++ case SImode: gen = gen_aarch64_store_exclusivesi; break; ++ case DImode: gen = gen_aarch64_store_exclusivedi; break; ++ default: ++ gcc_unreachable (); ++ } ++ ++ emit_insn (gen (bval, rval, mem, model_rtx)); ++} ++ ++/* Mark the previous jump instruction as unlikely. */ ++ ++static void ++aarch64_emit_unlikely_jump (rtx insn) ++{ ++ rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1); ++ ++ insn = emit_jump_insn (insn); ++ add_reg_note (insn, REG_BR_PROB, very_unlikely); ++} ++ ++/* Expand a compare and swap pattern. */ ++ ++void ++aarch64_expand_compare_and_swap (rtx operands[]) ++{ ++ rtx bval, rval, mem, oldval, newval, is_weak, mod_s, mod_f, x; ++ enum machine_mode mode, cmp_mode; ++ rtx (*gen) (rtx, rtx, rtx, rtx, rtx, rtx, rtx); ++ ++ bval = operands[0]; ++ rval = operands[1]; ++ mem = operands[2]; ++ oldval = operands[3]; ++ newval = operands[4]; ++ is_weak = operands[5]; ++ mod_s = operands[6]; ++ mod_f = operands[7]; ++ mode = GET_MODE (mem); ++ cmp_mode = mode; ++ ++ /* Normally the succ memory model must be stronger than fail, but in the ++ unlikely event of fail being ACQUIRE and succ being RELEASE we need to ++ promote succ to ACQ_REL so that we don't lose the acquire semantics. */ ++ ++ if (INTVAL (mod_f) == MEMMODEL_ACQUIRE ++ && INTVAL (mod_s) == MEMMODEL_RELEASE) ++ mod_s = GEN_INT (MEMMODEL_ACQ_REL); ++ ++ switch (mode) ++ { ++ case QImode: ++ case HImode: ++ /* For short modes, we're going to perform the comparison in SImode, ++ so do the zero-extension now. */ ++ cmp_mode = SImode; ++ rval = gen_reg_rtx (SImode); ++ oldval = convert_modes (SImode, mode, oldval, true); ++ /* Fall through. */ ++ ++ case SImode: ++ case DImode: ++ /* Force the value into a register if needed. */ ++ if (!aarch64_plus_operand (oldval, mode)) ++ oldval = force_reg (cmp_mode, oldval); ++ break; ++ ++ default: ++ gcc_unreachable (); ++ } ++ ++ switch (mode) ++ { ++ case QImode: gen = gen_atomic_compare_and_swapqi_1; break; ++ case HImode: gen = gen_atomic_compare_and_swaphi_1; break; ++ case SImode: gen = gen_atomic_compare_and_swapsi_1; break; ++ case DImode: gen = gen_atomic_compare_and_swapdi_1; break; ++ default: ++ gcc_unreachable (); ++ } ++ ++ emit_insn (gen (rval, mem, oldval, newval, is_weak, mod_s, mod_f)); ++ ++ if (mode == QImode || mode == HImode) ++ emit_move_insn (operands[1], gen_lowpart (mode, rval)); ++ ++ x = gen_rtx_REG (CCmode, CC_REGNUM); ++ x = gen_rtx_EQ (SImode, x, const0_rtx); ++ emit_insn (gen_rtx_SET (VOIDmode, bval, x)); ++} ++ ++/* Split a compare and swap pattern. */ ++ ++void ++aarch64_split_compare_and_swap (rtx operands[]) ++{ ++ rtx rval, mem, oldval, newval, scratch; ++ enum machine_mode mode; ++ bool is_weak; ++ rtx label1, label2, x, cond; ++ ++ rval = operands[0]; ++ mem = operands[1]; ++ oldval = operands[2]; ++ newval = operands[3]; ++ is_weak = (operands[4] != const0_rtx); ++ scratch = operands[7]; ++ mode = GET_MODE (mem); ++ ++ label1 = NULL_RTX; ++ if (!is_weak) ++ { ++ label1 = gen_label_rtx (); ++ emit_label (label1); ++ } ++ label2 = gen_label_rtx (); ++ ++ aarch64_emit_load_exclusive (mode, rval, mem, operands[5]); ++ ++ cond = aarch64_gen_compare_reg (NE, rval, oldval); ++ x = gen_rtx_NE (VOIDmode, cond, const0_rtx); ++ x = gen_rtx_IF_THEN_ELSE (VOIDmode, x, ++ gen_rtx_LABEL_REF (Pmode, label2), pc_rtx); ++ aarch64_emit_unlikely_jump (gen_rtx_SET (VOIDmode, pc_rtx, x)); ++ ++ aarch64_emit_store_exclusive (mode, scratch, mem, newval, operands[5]); ++ ++ if (!is_weak) ++ { ++ x = gen_rtx_NE (VOIDmode, scratch, const0_rtx); ++ x = gen_rtx_IF_THEN_ELSE (VOIDmode, x, ++ gen_rtx_LABEL_REF (Pmode, label1), pc_rtx); ++ aarch64_emit_unlikely_jump (gen_rtx_SET (VOIDmode, pc_rtx, x)); ++ } ++ else ++ { ++ cond = gen_rtx_REG (CCmode, CC_REGNUM); ++ x = gen_rtx_COMPARE (CCmode, scratch, const0_rtx); ++ emit_insn (gen_rtx_SET (VOIDmode, cond, x)); ++ } ++ ++ emit_label (label2); ++} ++ ++/* Split an atomic operation. */ ++ ++void ++aarch64_split_atomic_op (enum rtx_code code, rtx old_out, rtx new_out, rtx mem, ++ rtx value, rtx model_rtx, rtx cond) ++{ ++ enum machine_mode mode = GET_MODE (mem); ++ enum machine_mode wmode = (mode == DImode ? DImode : SImode); ++ rtx label, x; ++ ++ label = gen_label_rtx (); ++ emit_label (label); ++ ++ if (new_out) ++ new_out = gen_lowpart (wmode, new_out); ++ if (old_out) ++ old_out = gen_lowpart (wmode, old_out); ++ else ++ old_out = new_out; ++ value = simplify_gen_subreg (wmode, value, mode, 0); ++ ++ aarch64_emit_load_exclusive (mode, old_out, mem, model_rtx); ++ ++ switch (code) ++ { ++ case SET: ++ new_out = value; ++ break; ++ ++ case NOT: ++ x = gen_rtx_AND (wmode, old_out, value); ++ emit_insn (gen_rtx_SET (VOIDmode, new_out, x)); ++ x = gen_rtx_NOT (wmode, new_out); ++ emit_insn (gen_rtx_SET (VOIDmode, new_out, x)); ++ break; ++ ++ case MINUS: ++ if (CONST_INT_P (value)) ++ { ++ value = GEN_INT (-INTVAL (value)); ++ code = PLUS; ++ } ++ /* Fall through. */ ++ ++ default: ++ x = gen_rtx_fmt_ee (code, wmode, old_out, value); ++ emit_insn (gen_rtx_SET (VOIDmode, new_out, x)); ++ break; ++ } ++ ++ aarch64_emit_store_exclusive (mode, cond, mem, ++ gen_lowpart (mode, new_out), model_rtx); ++ ++ x = gen_rtx_NE (VOIDmode, cond, const0_rtx); ++ x = gen_rtx_IF_THEN_ELSE (VOIDmode, x, ++ gen_rtx_LABEL_REF (Pmode, label), pc_rtx); ++ aarch64_emit_unlikely_jump (gen_rtx_SET (VOIDmode, pc_rtx, x)); ++} ++ +static void +aarch64_start_file (void) +{ @@ -11487,6 +12707,687 @@ + return VOIDmode; +} + ++/* We can only represent floating point constants which will fit in ++ "quarter-precision" values. These values are characterised by ++ a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given ++ by: ++ ++ (-1)^s * (n/16) * 2^r ++ ++ Where: ++ 's' is the sign bit. ++ 'n' is an integer in the range 16 <= n <= 31. ++ 'r' is an integer in the range -3 <= r <= 4. */ ++ ++/* Return true iff X can be represented by a quarter-precision ++ floating point immediate operand X. Note, we cannot represent 0.0. */ ++bool ++aarch64_float_const_representable_p (rtx x) ++{ ++ /* This represents our current view of how many bits ++ make up the mantissa. */ ++ int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1; ++ int exponent; ++ unsigned HOST_WIDE_INT mantissa, mask; ++ HOST_WIDE_INT m1, m2; ++ REAL_VALUE_TYPE r, m; ++ ++ if (!CONST_DOUBLE_P (x)) ++ return false; ++ ++ REAL_VALUE_FROM_CONST_DOUBLE (r, x); ++ ++ /* We cannot represent infinities, NaNs or +/-zero. We won't ++ know if we have +zero until we analyse the mantissa, but we ++ can reject the other invalid values. */ ++ if (REAL_VALUE_ISINF (r) || REAL_VALUE_ISNAN (r) ++ || REAL_VALUE_MINUS_ZERO (r)) ++ return false; ++ ++ /* Extract exponent. */ ++ r = real_value_abs (&r); ++ exponent = REAL_EXP (&r); ++ ++ /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the ++ highest (sign) bit, with a fixed binary point at bit point_pos. ++ m1 holds the low part of the mantissa, m2 the high part. ++ WARNING: If we ever have a representation using more than 2 * H_W_I - 1 ++ bits for the mantissa, this can fail (low bits will be lost). */ ++ real_ldexp (&m, &r, point_pos - exponent); ++ REAL_VALUE_TO_INT (&m1, &m2, m); ++ ++ /* If the low part of the mantissa has bits set we cannot represent ++ the value. */ ++ if (m1 != 0) ++ return false; ++ /* We have rejected the lower HOST_WIDE_INT, so update our ++ understanding of how many bits lie in the mantissa and ++ look only at the high HOST_WIDE_INT. */ ++ mantissa = m2; ++ point_pos -= HOST_BITS_PER_WIDE_INT; ++ ++ /* We can only represent values with a mantissa of the form 1.xxxx. */ ++ mask = ((unsigned HOST_WIDE_INT)1 << (point_pos - 5)) - 1; ++ if ((mantissa & mask) != 0) ++ return false; ++ ++ /* Having filtered unrepresentable values, we may now remove all ++ but the highest 5 bits. */ ++ mantissa >>= point_pos - 5; ++ ++ /* We cannot represent the value 0.0, so reject it. This is handled ++ elsewhere. */ ++ if (mantissa == 0) ++ return false; ++ ++ /* Then, as bit 4 is always set, we can mask it off, leaving ++ the mantissa in the range [0, 15]. */ ++ mantissa &= ~(1 << 4); ++ gcc_assert (mantissa <= 15); ++ ++ /* GCC internally does not use IEEE754-like encoding (where normalized ++ significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c). ++ Our mantissa values are shifted 4 places to the left relative to ++ normalized IEEE754 so we must modify the exponent returned by REAL_EXP ++ by 5 places to correct for GCC's representation. */ ++ exponent = 5 - exponent; ++ ++ return (exponent >= 0 && exponent <= 7); ++} ++ ++char* ++aarch64_output_simd_mov_immediate (rtx *const_vector, ++ enum machine_mode mode, ++ unsigned width) ++{ ++ int is_valid; ++ unsigned char widthc; ++ int lane_width_bits; ++ static char templ[40]; ++ int shift = 0, mvn = 0; ++ const char *mnemonic; ++ unsigned int lane_count = 0; ++ ++ is_valid = ++ aarch64_simd_immediate_valid_for_move (*const_vector, mode, ++ const_vector, &lane_width_bits, ++ &widthc, &mvn, &shift); ++ gcc_assert (is_valid); ++ ++ mode = GET_MODE_INNER (mode); ++ if (mode == SFmode || mode == DFmode) ++ { ++ bool zero_p = ++ aarch64_float_const_zero_rtx_p (*const_vector); ++ gcc_assert (shift == 0); ++ mnemonic = zero_p ? "movi" : "fmov"; ++ } ++ else ++ mnemonic = mvn ? "mvni" : "movi"; ++ ++ gcc_assert (lane_width_bits != 0); ++ lane_count = width / lane_width_bits; ++ ++ if (lane_count == 1) ++ snprintf (templ, sizeof (templ), "%s\t%%d0, %%1", mnemonic); ++ else if (shift) ++ snprintf (templ, sizeof (templ), "%s\t%%0.%d%c, %%1, lsl %d", ++ mnemonic, lane_count, widthc, shift); ++ else ++ snprintf (templ, sizeof (templ), "%s\t%%0.%d%c, %%1", ++ mnemonic, lane_count, widthc); ++ return templ; ++} ++ ++/* Split operands into moves from op[1] + op[2] into op[0]. */ ++ ++void ++aarch64_split_combinev16qi (rtx operands[3]) ++{ ++ unsigned int dest = REGNO (operands[0]); ++ unsigned int src1 = REGNO (operands[1]); ++ unsigned int src2 = REGNO (operands[2]); ++ enum machine_mode halfmode = GET_MODE (operands[1]); ++ unsigned int halfregs = HARD_REGNO_NREGS (src1, halfmode); ++ rtx destlo, desthi; ++ ++ gcc_assert (halfmode == V16QImode); ++ ++ if (src1 == dest && src2 == dest + halfregs) ++ { ++ /* No-op move. Can't split to nothing; emit something. */ ++ emit_note (NOTE_INSN_DELETED); ++ return; ++ } ++ ++ /* Preserve register attributes for variable tracking. */ ++ destlo = gen_rtx_REG_offset (operands[0], halfmode, dest, 0); ++ desthi = gen_rtx_REG_offset (operands[0], halfmode, dest + halfregs, ++ GET_MODE_SIZE (halfmode)); ++ ++ /* Special case of reversed high/low parts. */ ++ if (reg_overlap_mentioned_p (operands[2], destlo) ++ && reg_overlap_mentioned_p (operands[1], desthi)) ++ { ++ emit_insn (gen_xorv16qi3 (operands[1], operands[1], operands[2])); ++ emit_insn (gen_xorv16qi3 (operands[2], operands[1], operands[2])); ++ emit_insn (gen_xorv16qi3 (operands[1], operands[1], operands[2])); ++ } ++ else if (!reg_overlap_mentioned_p (operands[2], destlo)) ++ { ++ /* Try to avoid unnecessary moves if part of the result ++ is in the right place already. */ ++ if (src1 != dest) ++ emit_move_insn (destlo, operands[1]); ++ if (src2 != dest + halfregs) ++ emit_move_insn (desthi, operands[2]); ++ } ++ else ++ { ++ if (src2 != dest + halfregs) ++ emit_move_insn (desthi, operands[2]); ++ if (src1 != dest) ++ emit_move_insn (destlo, operands[1]); ++ } ++} ++ ++/* vec_perm support. */ ++ ++#define MAX_VECT_LEN 16 ++ ++struct expand_vec_perm_d ++{ ++ rtx target, op0, op1; ++ unsigned char perm[MAX_VECT_LEN]; ++ enum machine_mode vmode; ++ unsigned char nelt; ++ bool one_vector_p; ++ bool testing_p; ++}; ++ ++/* Generate a variable permutation. */ ++ ++static void ++aarch64_expand_vec_perm_1 (rtx target, rtx op0, rtx op1, rtx sel) ++{ ++ enum machine_mode vmode = GET_MODE (target); ++ bool one_vector_p = rtx_equal_p (op0, op1); ++ ++ gcc_checking_assert (vmode == V8QImode || vmode == V16QImode); ++ gcc_checking_assert (GET_MODE (op0) == vmode); ++ gcc_checking_assert (GET_MODE (op1) == vmode); ++ gcc_checking_assert (GET_MODE (sel) == vmode); ++ gcc_checking_assert (TARGET_SIMD); ++ ++ if (one_vector_p) ++ { ++ if (vmode == V8QImode) ++ { ++ /* Expand the argument to a V16QI mode by duplicating it. */ ++ rtx pair = gen_reg_rtx (V16QImode); ++ emit_insn (gen_aarch64_combinev8qi (pair, op0, op0)); ++ emit_insn (gen_aarch64_tbl1v8qi (target, pair, sel)); ++ } ++ else ++ { ++ emit_insn (gen_aarch64_tbl1v16qi (target, op0, sel)); ++ } ++ } ++ else ++ { ++ rtx pair; ++ ++ if (vmode == V8QImode) ++ { ++ pair = gen_reg_rtx (V16QImode); ++ emit_insn (gen_aarch64_combinev8qi (pair, op0, op1)); ++ emit_insn (gen_aarch64_tbl1v8qi (target, pair, sel)); ++ } ++ else ++ { ++ pair = gen_reg_rtx (OImode); ++ emit_insn (gen_aarch64_combinev16qi (pair, op0, op1)); ++ emit_insn (gen_aarch64_tbl2v16qi (target, pair, sel)); ++ } ++ } ++} ++ ++void ++aarch64_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel) ++{ ++ enum machine_mode vmode = GET_MODE (target); ++ unsigned int i, nelt = GET_MODE_NUNITS (vmode); ++ bool one_vector_p = rtx_equal_p (op0, op1); ++ rtx rmask[MAX_VECT_LEN], mask; ++ ++ gcc_checking_assert (!BYTES_BIG_ENDIAN); ++ ++ /* The TBL instruction does not use a modulo index, so we must take care ++ of that ourselves. */ ++ mask = GEN_INT (one_vector_p ? nelt - 1 : 2 * nelt - 1); ++ for (i = 0; i < nelt; ++i) ++ rmask[i] = mask; ++ mask = gen_rtx_CONST_VECTOR (vmode, gen_rtvec_v (nelt, rmask)); ++ sel = expand_simple_binop (vmode, AND, sel, mask, NULL, 0, OPTAB_LIB_WIDEN); ++ ++ aarch64_expand_vec_perm_1 (target, op0, op1, sel); ++} ++ ++/* Recognize patterns suitable for the TRN instructions. */ ++static bool ++aarch64_evpc_trn (struct expand_vec_perm_d *d) ++{ ++ unsigned int i, odd, mask, nelt = d->nelt; ++ rtx out, in0, in1, x; ++ rtx (*gen) (rtx, rtx, rtx); ++ enum machine_mode vmode = d->vmode; ++ ++ if (GET_MODE_UNIT_SIZE (vmode) > 8) ++ return false; ++ ++ /* Note that these are little-endian tests. ++ We correct for big-endian later. */ ++ if (d->perm[0] == 0) ++ odd = 0; ++ else if (d->perm[0] == 1) ++ odd = 1; ++ else ++ return false; ++ mask = (d->one_vector_p ? nelt - 1 : 2 * nelt - 1); ++ ++ for (i = 0; i < nelt; i += 2) ++ { ++ if (d->perm[i] != i + odd) ++ return false; ++ if (d->perm[i + 1] != ((i + nelt + odd) & mask)) ++ return false; ++ } ++ ++ /* Success! */ ++ if (d->testing_p) ++ return true; ++ ++ in0 = d->op0; ++ in1 = d->op1; ++ if (BYTES_BIG_ENDIAN) ++ { ++ x = in0, in0 = in1, in1 = x; ++ odd = !odd; ++ } ++ out = d->target; ++ ++ if (odd) ++ { ++ switch (vmode) ++ { ++ case V16QImode: gen = gen_aarch64_trn2v16qi; break; ++ case V8QImode: gen = gen_aarch64_trn2v8qi; break; ++ case V8HImode: gen = gen_aarch64_trn2v8hi; break; ++ case V4HImode: gen = gen_aarch64_trn2v4hi; break; ++ case V4SImode: gen = gen_aarch64_trn2v4si; break; ++ case V2SImode: gen = gen_aarch64_trn2v2si; break; ++ case V2DImode: gen = gen_aarch64_trn2v2di; break; ++ case V4SFmode: gen = gen_aarch64_trn2v4sf; break; ++ case V2SFmode: gen = gen_aarch64_trn2v2sf; break; ++ case V2DFmode: gen = gen_aarch64_trn2v2df; break; ++ default: ++ return false; ++ } ++ } ++ else ++ { ++ switch (vmode) ++ { ++ case V16QImode: gen = gen_aarch64_trn1v16qi; break; ++ case V8QImode: gen = gen_aarch64_trn1v8qi; break; ++ case V8HImode: gen = gen_aarch64_trn1v8hi; break; ++ case V4HImode: gen = gen_aarch64_trn1v4hi; break; ++ case V4SImode: gen = gen_aarch64_trn1v4si; break; ++ case V2SImode: gen = gen_aarch64_trn1v2si; break; ++ case V2DImode: gen = gen_aarch64_trn1v2di; break; ++ case V4SFmode: gen = gen_aarch64_trn1v4sf; break; ++ case V2SFmode: gen = gen_aarch64_trn1v2sf; break; ++ case V2DFmode: gen = gen_aarch64_trn1v2df; break; ++ default: ++ return false; ++ } ++ } ++ ++ emit_insn (gen (out, in0, in1)); ++ return true; ++} ++ ++/* Recognize patterns suitable for the UZP instructions. */ ++static bool ++aarch64_evpc_uzp (struct expand_vec_perm_d *d) ++{ ++ unsigned int i, odd, mask, nelt = d->nelt; ++ rtx out, in0, in1, x; ++ rtx (*gen) (rtx, rtx, rtx); ++ enum machine_mode vmode = d->vmode; ++ ++ if (GET_MODE_UNIT_SIZE (vmode) > 8) ++ return false; ++ ++ /* Note that these are little-endian tests. ++ We correct for big-endian later. */ ++ if (d->perm[0] == 0) ++ odd = 0; ++ else if (d->perm[0] == 1) ++ odd = 1; ++ else ++ return false; ++ mask = (d->one_vector_p ? nelt - 1 : 2 * nelt - 1); ++ ++ for (i = 0; i < nelt; i++) ++ { ++ unsigned elt = (i * 2 + odd) & mask; ++ if (d->perm[i] != elt) ++ return false; ++ } ++ ++ /* Success! */ ++ if (d->testing_p) ++ return true; ++ ++ in0 = d->op0; ++ in1 = d->op1; ++ if (BYTES_BIG_ENDIAN) ++ { ++ x = in0, in0 = in1, in1 = x; ++ odd = !odd; ++ } ++ out = d->target; ++ ++ if (odd) ++ { ++ switch (vmode) ++ { ++ case V16QImode: gen = gen_aarch64_uzp2v16qi; break; ++ case V8QImode: gen = gen_aarch64_uzp2v8qi; break; ++ case V8HImode: gen = gen_aarch64_uzp2v8hi; break; ++ case V4HImode: gen = gen_aarch64_uzp2v4hi; break; ++ case V4SImode: gen = gen_aarch64_uzp2v4si; break; ++ case V2SImode: gen = gen_aarch64_uzp2v2si; break; ++ case V2DImode: gen = gen_aarch64_uzp2v2di; break; ++ case V4SFmode: gen = gen_aarch64_uzp2v4sf; break; ++ case V2SFmode: gen = gen_aarch64_uzp2v2sf; break; ++ case V2DFmode: gen = gen_aarch64_uzp2v2df; break; ++ default: ++ return false; ++ } ++ } ++ else ++ { ++ switch (vmode) ++ { ++ case V16QImode: gen = gen_aarch64_uzp1v16qi; break; ++ case V8QImode: gen = gen_aarch64_uzp1v8qi; break; ++ case V8HImode: gen = gen_aarch64_uzp1v8hi; break; ++ case V4HImode: gen = gen_aarch64_uzp1v4hi; break; ++ case V4SImode: gen = gen_aarch64_uzp1v4si; break; ++ case V2SImode: gen = gen_aarch64_uzp1v2si; break; ++ case V2DImode: gen = gen_aarch64_uzp1v2di; break; ++ case V4SFmode: gen = gen_aarch64_uzp1v4sf; break; ++ case V2SFmode: gen = gen_aarch64_uzp1v2sf; break; ++ case V2DFmode: gen = gen_aarch64_uzp1v2df; break; ++ default: ++ return false; ++ } ++ } ++ ++ emit_insn (gen (out, in0, in1)); ++ return true; ++} ++ ++/* Recognize patterns suitable for the ZIP instructions. */ ++static bool ++aarch64_evpc_zip (struct expand_vec_perm_d *d) ++{ ++ unsigned int i, high, mask, nelt = d->nelt; ++ rtx out, in0, in1, x; ++ rtx (*gen) (rtx, rtx, rtx); ++ enum machine_mode vmode = d->vmode; ++ ++ if (GET_MODE_UNIT_SIZE (vmode) > 8) ++ return false; ++ ++ /* Note that these are little-endian tests. ++ We correct for big-endian later. */ ++ high = nelt / 2; ++ if (d->perm[0] == high) ++ /* Do Nothing. */ ++ ; ++ else if (d->perm[0] == 0) ++ high = 0; ++ else ++ return false; ++ mask = (d->one_vector_p ? nelt - 1 : 2 * nelt - 1); ++ ++ for (i = 0; i < nelt / 2; i++) ++ { ++ unsigned elt = (i + high) & mask; ++ if (d->perm[i * 2] != elt) ++ return false; ++ elt = (elt + nelt) & mask; ++ if (d->perm[i * 2 + 1] != elt) ++ return false; ++ } ++ ++ /* Success! */ ++ if (d->testing_p) ++ return true; ++ ++ in0 = d->op0; ++ in1 = d->op1; ++ if (BYTES_BIG_ENDIAN) ++ { ++ x = in0, in0 = in1, in1 = x; ++ high = !high; ++ } ++ out = d->target; ++ ++ if (high) ++ { ++ switch (vmode) ++ { ++ case V16QImode: gen = gen_aarch64_zip2v16qi; break; ++ case V8QImode: gen = gen_aarch64_zip2v8qi; break; ++ case V8HImode: gen = gen_aarch64_zip2v8hi; break; ++ case V4HImode: gen = gen_aarch64_zip2v4hi; break; ++ case V4SImode: gen = gen_aarch64_zip2v4si; break; ++ case V2SImode: gen = gen_aarch64_zip2v2si; break; ++ case V2DImode: gen = gen_aarch64_zip2v2di; break; ++ case V4SFmode: gen = gen_aarch64_zip2v4sf; break; ++ case V2SFmode: gen = gen_aarch64_zip2v2sf; break; ++ case V2DFmode: gen = gen_aarch64_zip2v2df; break; ++ default: ++ return false; ++ } ++ } ++ else ++ { ++ switch (vmode) ++ { ++ case V16QImode: gen = gen_aarch64_zip1v16qi; break; ++ case V8QImode: gen = gen_aarch64_zip1v8qi; break; ++ case V8HImode: gen = gen_aarch64_zip1v8hi; break; ++ case V4HImode: gen = gen_aarch64_zip1v4hi; break; ++ case V4SImode: gen = gen_aarch64_zip1v4si; break; ++ case V2SImode: gen = gen_aarch64_zip1v2si; break; ++ case V2DImode: gen = gen_aarch64_zip1v2di; break; ++ case V4SFmode: gen = gen_aarch64_zip1v4sf; break; ++ case V2SFmode: gen = gen_aarch64_zip1v2sf; break; ++ case V2DFmode: gen = gen_aarch64_zip1v2df; break; ++ default: ++ return false; ++ } ++ } ++ ++ emit_insn (gen (out, in0, in1)); ++ return true; ++} ++ ++static bool ++aarch64_evpc_tbl (struct expand_vec_perm_d *d) ++{ ++ rtx rperm[MAX_VECT_LEN], sel; ++ enum machine_mode vmode = d->vmode; ++ unsigned int i, nelt = d->nelt; ++ ++ /* TODO: ARM's TBL indexing is little-endian. In order to handle GCC's ++ numbering of elements for big-endian, we must reverse the order. */ ++ if (BYTES_BIG_ENDIAN) ++ return false; ++ ++ if (d->testing_p) ++ return true; ++ ++ /* Generic code will try constant permutation twice. Once with the ++ original mode and again with the elements lowered to QImode. ++ So wait and don't do the selector expansion ourselves. */ ++ if (vmode != V8QImode && vmode != V16QImode) ++ return false; ++ ++ for (i = 0; i < nelt; ++i) ++ rperm[i] = GEN_INT (d->perm[i]); ++ sel = gen_rtx_CONST_VECTOR (vmode, gen_rtvec_v (nelt, rperm)); ++ sel = force_reg (vmode, sel); ++ ++ aarch64_expand_vec_perm_1 (d->target, d->op0, d->op1, sel); ++ return true; ++} ++ ++static bool ++aarch64_expand_vec_perm_const_1 (struct expand_vec_perm_d *d) ++{ ++ /* The pattern matching functions above are written to look for a small ++ number to begin the sequence (0, 1, N/2). If we begin with an index ++ from the second operand, we can swap the operands. */ ++ if (d->perm[0] >= d->nelt) ++ { ++ unsigned i, nelt = d->nelt; ++ rtx x; ++ ++ for (i = 0; i < nelt; ++i) ++ d->perm[i] = (d->perm[i] + nelt) & (2 * nelt - 1); ++ ++ x = d->op0; ++ d->op0 = d->op1; ++ d->op1 = x; ++ } ++ ++ if (TARGET_SIMD) ++ { ++ if (aarch64_evpc_zip (d)) ++ return true; ++ else if (aarch64_evpc_uzp (d)) ++ return true; ++ else if (aarch64_evpc_trn (d)) ++ return true; ++ return aarch64_evpc_tbl (d); ++ } ++ return false; ++} ++ ++/* Expand a vec_perm_const pattern. */ ++ ++bool ++aarch64_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel) ++{ ++ struct expand_vec_perm_d d; ++ int i, nelt, which; ++ ++ d.target = target; ++ d.op0 = op0; ++ d.op1 = op1; ++ ++ d.vmode = GET_MODE (target); ++ gcc_assert (VECTOR_MODE_P (d.vmode)); ++ d.nelt = nelt = GET_MODE_NUNITS (d.vmode); ++ d.testing_p = false; ++ ++ for (i = which = 0; i < nelt; ++i) ++ { ++ rtx e = XVECEXP (sel, 0, i); ++ int ei = INTVAL (e) & (2 * nelt - 1); ++ which |= (ei < nelt ? 1 : 2); ++ d.perm[i] = ei; ++ } ++ ++ switch (which) ++ { ++ default: ++ gcc_unreachable (); ++ ++ case 3: ++ d.one_vector_p = false; ++ if (!rtx_equal_p (op0, op1)) ++ break; ++ ++ /* The elements of PERM do not suggest that only the first operand ++ is used, but both operands are identical. Allow easier matching ++ of the permutation by folding the permutation into the single ++ input vector. */ ++ /* Fall Through. */ ++ case 2: ++ for (i = 0; i < nelt; ++i) ++ d.perm[i] &= nelt - 1; ++ d.op0 = op1; ++ d.one_vector_p = true; ++ break; ++ ++ case 1: ++ d.op1 = op0; ++ d.one_vector_p = true; ++ break; ++ } ++ ++ return aarch64_expand_vec_perm_const_1 (&d); ++} ++ ++static bool ++aarch64_vectorize_vec_perm_const_ok (enum machine_mode vmode, ++ const unsigned char *sel) ++{ ++ struct expand_vec_perm_d d; ++ unsigned int i, nelt, which; ++ bool ret; ++ ++ d.vmode = vmode; ++ d.nelt = nelt = GET_MODE_NUNITS (d.vmode); ++ d.testing_p = true; ++ memcpy (d.perm, sel, nelt); ++ ++ /* Calculate whether all elements are in one vector. */ ++ for (i = which = 0; i < nelt; ++i) ++ { ++ unsigned char e = d.perm[i]; ++ gcc_assert (e < 2 * nelt); ++ which |= (e < nelt ? 1 : 2); ++ } ++ ++ /* If all elements are from the second vector, reindex as if from the ++ first vector. */ ++ if (which == 2) ++ for (i = 0; i < nelt; ++i) ++ d.perm[i] -= nelt; ++ ++ /* Check whether the mask can be applied to a single vector. */ ++ d.one_vector_p = (which != 3); ++ ++ d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1); ++ d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2); ++ if (!d.one_vector_p) ++ d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3); ++ ++ start_sequence (); ++ ret = aarch64_expand_vec_perm_const_1 (&d); ++ end_sequence (); ++ ++ return ret; ++} ++ +#undef TARGET_ADDRESS_COST +#define TARGET_ADDRESS_COST aarch64_address_cost + @@ -11553,12 +13454,18 @@ +#undef TARGET_CLASS_MAX_NREGS +#define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs + ++#undef TARGET_BUILTIN_DECL ++#define TARGET_BUILTIN_DECL aarch64_builtin_decl ++ +#undef TARGET_EXPAND_BUILTIN +#define TARGET_EXPAND_BUILTIN aarch64_expand_builtin + +#undef TARGET_EXPAND_BUILTIN_VA_START +#define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start + ++#undef TARGET_FIXED_CONDITION_CODE_REGS ++#define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs ++ +#undef TARGET_FUNCTION_ARG +#define TARGET_FUNCTION_ARG aarch64_function_arg + @@ -11595,6 +13502,9 @@ +#undef TARGET_LIBGCC_CMP_RETURN_MODE +#define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode + ++#undef TARGET_MANGLE_TYPE ++#define TARGET_MANGLE_TYPE aarch64_mangle_type ++ +#undef TARGET_MEMORY_MOVE_COST +#define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost + @@ -11659,16 +13569,51 @@ +#undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE +#define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode + -+struct gcc_target targetm = TARGET_INITIALIZER; ++#undef TARGET_VECTOR_ALIGNMENT ++#define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment + -+#include "gt-aarch64.h" ---- a/src/gcc/config/aarch64/aarch64-cores.def -+++ b/src/gcc/config/aarch64/aarch64-cores.def -@@ -0,0 +1,38 @@ -+/* Copyright (C) 2011, 2012 Free Software Foundation, Inc. -+ Contributed by ARM Ltd. ++#undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE ++#define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \ ++ aarch64_simd_vector_alignment_reachable + -+ This file is part of GCC. ++#undef TARGET_VECTORIZE_BUILTINS ++#define TARGET_VECTORIZE_BUILTINS ++ ++#undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION ++#define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \ ++ aarch64_builtin_vectorized_function ++ ++#undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES ++#define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \ ++ aarch64_autovectorize_vector_sizes ++ ++/* vec_perm support. */ ++ ++#undef TARGET_VECTORIZE_VEC_PERM_CONST_OK ++#define TARGET_VECTORIZE_VEC_PERM_CONST_OK \ ++ aarch64_vectorize_vec_perm_const_ok ++ ++/* Section anchor support. */ ++ ++#undef TARGET_MIN_ANCHOR_OFFSET ++#define TARGET_MIN_ANCHOR_OFFSET -256 ++ ++/* Limit the maximum anchor offset to 4k-1, since that's the limit for a ++ byte offset; we can do much more for larger data types, but have no way ++ to determine the size of the access. We assume accesses are aligned. */ ++#undef TARGET_MAX_ANCHOR_OFFSET ++#define TARGET_MAX_ANCHOR_OFFSET 4095 ++ ++struct gcc_target targetm = TARGET_INITIALIZER; ++ ++#include "gt-aarch64.h" +--- a/src/gcc/config/aarch64/aarch64-cores.def ++++ b/src/gcc/config/aarch64/aarch64-cores.def +@@ -0,0 +1,38 @@ ++/* Copyright (C) 2011, 2012 Free Software Foundation, Inc. ++ Contributed by ARM Ltd. ++ ++ This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by @@ -11705,7 +13650,7 @@ +AARCH64_CORE("example-2", small, 8, AARCH64_FL_FPSIMD, generic) --- a/src/gcc/config/aarch64/aarch64-elf.h +++ b/src/gcc/config/aarch64/aarch64-elf.h -@@ -0,0 +1,123 @@ +@@ -0,0 +1,132 @@ +/* Machine description for AArch64 architecture. + Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. + Contributed by ARM Ltd. @@ -11733,6 +13678,15 @@ +#define ASM_OUTPUT_LABELREF(FILE, NAME) \ + aarch64_asm_output_labelref (FILE, NAME) + ++#define ASM_OUTPUT_DEF(FILE, NAME1, NAME2) \ ++ do \ ++ { \ ++ assemble_name (FILE, NAME1); \ ++ fputs (" = ", FILE); \ ++ assemble_name (FILE, NAME2); \ ++ fputc ('\n', FILE); \ ++ } while (0) ++ +#define TEXT_SECTION_ASM_OP "\t.text" +#define DATA_SECTION_ASM_OP "\t.data" +#define BSS_SECTION_ASM_OP "\t.bss" @@ -11907,7 +13861,7 @@ + "core") --- a/src/gcc/config/aarch64/aarch64.h +++ b/src/gcc/config/aarch64/aarch64.h -@@ -0,0 +1,842 @@ +@@ -0,0 +1,823 @@ +/* Machine description for AArch64 architecture. + Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. + Contributed by ARM Ltd. @@ -12683,16 +14637,6 @@ +#define ASM_APP_ON "\t" ASM_COMMENT_START " Start of user assembly\n" +#define ASM_APP_OFF "\t" ASM_COMMENT_START " End of user assembly\n" + -+#define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ -+ case '@': \ -+ fputs (ASM_COMMENT_START, FILE); \ -+ break; \ -+ \ -+ case 'r': \ -+ fputs (REGISTER_PREFIX, FILE); \ -+ fputs (reg_names[va_arg (ARGS, int)], FILE); \ -+ break; -+ +#define CONSTANT_POOL_BEFORE_FUNCTION 0 + +/* This definition should be relocated to aarch64-elf-raw.h. This macro @@ -12704,15 +14648,6 @@ + extern void __aarch64_sync_cache_range (void *, void *); \ + __aarch64_sync_cache_range (beg, end) + -+/* This should be integrated with the equivalent in the 32 bit -+ world. */ -+enum aarch64_builtins -+{ -+ AARCH64_BUILTIN_MIN, -+ AARCH64_BUILTIN_THREAD_POINTER, -+ AARCH64_SIMD_BUILTIN_BASE -+}; -+ +/* VFP registers may only be accessed in the mode they + were set. */ +#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ @@ -12799,9 +14734,9 @@ +#endif /* GCC_AARCH64_LINUX_H */ --- a/src/gcc/config/aarch64/aarch64.md +++ b/src/gcc/config/aarch64/aarch64.md -@@ -0,0 +1,2926 @@ +@@ -0,0 +1,3216 @@ +;; Machine description for AArch64 architecture. -+;; Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. ++;; Copyright (C) 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc. +;; Contributed by ARM Ltd. +;; +;; This file is part of GCC. @@ -12906,60 +14841,6 @@ +(include "iterators.md") + +;; ------------------------------------------------------------------- -+;; Synchronization Builtins -+;; ------------------------------------------------------------------- -+ -+;; The following sync_* attributes are applied to sychronization -+;; instruction patterns to control the way in which the -+;; synchronization loop is expanded. -+;; All instruction patterns that call aarch64_output_sync_insn () -+;; should define these attributes. Refer to the comment above -+;; aarch64.c:aarch64_output_sync_loop () for more detail on the use of -+;; these attributes. -+ -+;; Attribute specifies the operand number which contains the -+;; result of a synchronization operation. The result is the old value -+;; loaded from SYNC_MEMORY. -+(define_attr "sync_result" "none,0,1,2,3,4,5" (const_string "none")) -+ -+;; Attribute specifies the operand number which contains the memory -+;; address to which the synchronization operation is being applied. -+(define_attr "sync_memory" "none,0,1,2,3,4,5" (const_string "none")) -+ -+;; Attribute specifies the operand number which contains the required -+;; old value expected in the memory location. This attribute may be -+;; none if no required value test should be performed in the expanded -+;; code. -+(define_attr "sync_required_value" "none,0,1,2,3,4,5" (const_string "none")) -+ -+;; Attribute specifies the operand number of the new value to be stored -+;; into the memory location identitifed by the sync_memory attribute. -+(define_attr "sync_new_value" "none,0,1,2,3,4,5" (const_string "none")) -+ -+;; Attribute specifies the operand number of a temporary register -+;; which can be clobbered by the synchronization instruction sequence. -+;; The register provided byn SYNC_T1 may be the same as SYNC_RESULT is -+;; which case the result value will be clobbered and not available -+;; after the synchronization loop exits. -+(define_attr "sync_t1" "none,0,1,2,3,4,5" (const_string "none")) -+ -+;; Attribute specifies the operand number of a temporary register -+;; which can be clobbered by the synchronization instruction sequence. -+;; This register is used to collect the result of a store exclusive -+;; instruction. -+(define_attr "sync_t2" "none,0,1,2,3,4,5" (const_string "none")) -+ -+;; Attribute that specifies whether or not the emitted synchronization -+;; loop must contain a release barrier. -+(define_attr "sync_release_barrier" "yes,no" (const_string "yes")) -+ -+;; Attribute that specifies the operation that the synchronization -+;; loop should apply to the old and new values to generate the value -+;; written back to memory. -+(define_attr "sync_op" "none,add,sub,ior,xor,and,nand" -+ (const_string "none")) -+ -+;; ------------------------------------------------------------------- +;; Instruction types and attributes +;; ------------------------------------------------------------------- + @@ -13172,9 +15053,7 @@ +(define_attr "simd" "no,yes" (const_string "no")) + +(define_attr "length" "" -+ (cond [(not (eq_attr "sync_memory" "none")) -+ (symbol_ref "aarch64_sync_loop_insns (insn, operands) * 4") -+ ] (const_int 4))) ++ (const_int 4)) + +;; Attribute that controls whether an alternative is enabled or not. +;; Currently it is only used to disable alternatives which touch fp or simd @@ -13698,8 +15577,8 @@ +(define_insn "insv_imm" + [(set (zero_extract:GPI (match_operand:GPI 0 "register_operand" "+r") + (const_int 16) -+ (match_operand 1 "const_int_operand" "n")) -+ (match_operand 2 "const_int_operand" "n"))] ++ (match_operand:GPI 1 "const_int_operand" "n")) ++ (match_operand:GPI 2 "const_int_operand" "n"))] + "INTVAL (operands[1]) < GET_MODE_BITSIZE (mode) + && INTVAL (operands[1]) % 16 == 0 + && INTVAL (operands[2]) <= 0xffff" @@ -13773,38 +15652,44 @@ +) + +(define_insn "*movsf_aarch64" -+ [(set (match_operand:SF 0 "nonimmediate_operand" "= w,?r,w,w,m,r,m ,r") -+ (match_operand:SF 1 "general_operand" "?rY, w,w,m,w,m,rY,r"))] ++ [(set (match_operand:SF 0 "nonimmediate_operand" "=w, ?r,w,w ,w,m,r,m ,r") ++ (match_operand:SF 1 "general_operand" "?rY, w,w,Ufc,m,w,m,rY,r"))] + "TARGET_FLOAT && (register_operand (operands[0], SFmode) + || register_operand (operands[1], SFmode))" + "@ + fmov\\t%s0, %w1 + fmov\\t%w0, %s1 + fmov\\t%s0, %s1 ++ fmov\\t%s0, %1 + ldr\\t%s0, %1 + str\\t%s1, %0 + ldr\\t%w0, %1 + str\\t%w1, %0 + mov\\t%w0, %w1" -+ [(set_attr "v8type" "fmovi2f,fmovf2i,fmov,fpsimd_load,fpsimd_store,fpsimd_load,fpsimd_store,fmov") ++ [(set_attr "v8type" "fmovi2f,fmovf2i,\ ++ fmov,fconst,fpsimd_load,\ ++ fpsimd_store,fpsimd_load,fpsimd_store,fmov") + (set_attr "mode" "SF")] +) + +(define_insn "*movdf_aarch64" -+ [(set (match_operand:DF 0 "nonimmediate_operand" "= w,?r,w,w,m,r,m ,r") -+ (match_operand:DF 1 "general_operand" "?rY, w,w,m,w,m,rY,r"))] ++ [(set (match_operand:DF 0 "nonimmediate_operand" "=w, ?r,w,w ,w,m,r,m ,r") ++ (match_operand:DF 1 "general_operand" "?rY, w,w,Ufc,m,w,m,rY,r"))] + "TARGET_FLOAT && (register_operand (operands[0], DFmode) + || register_operand (operands[1], DFmode))" + "@ + fmov\\t%d0, %x1 + fmov\\t%x0, %d1 + fmov\\t%d0, %d1 ++ fmov\\t%d0, %1 + ldr\\t%d0, %1 + str\\t%d1, %0 + ldr\\t%x0, %1 + str\\t%x1, %0 + mov\\t%x0, %x1" -+ [(set_attr "v8type" "fmovi2f,fmovf2i,fmov,fpsimd_load,fpsimd_store,fpsimd_load,fpsimd_store,move") ++ [(set_attr "v8type" "fmovi2f,fmovf2i,\ ++ fmov,fconst,fpsimd_load,\ ++ fpsimd_store,fpsimd_load,fpsimd_store,move") + (set_attr "mode" "DF")] +) + @@ -13849,7 +15734,6 @@ + (set_attr "simd" "yes,*,*,*,yes,*,*,*,*,*")] +) + -+ +;; Operands 1 and 3 are tied together by the final condition; so we allow +;; fairly lax checking on the second memory operation. +(define_insn "load_pair" @@ -14069,6 +15953,22 @@ + (set_attr "mode" "SI")] +) + ++;; zero_extend version of above ++(define_insn "*addsi3_aarch64_uxtw" ++ [(set ++ (match_operand:DI 0 "register_operand" "=rk,rk,rk") ++ (zero_extend:DI ++ (plus:SI (match_operand:SI 1 "register_operand" "%rk,rk,rk") ++ (match_operand:SI 2 "aarch64_plus_operand" "I,r,J"))))] ++ "" ++ "@ ++ add\\t%w0, %w1, %2 ++ add\\t%w0, %w1, %w2 ++ sub\\t%w0, %w1, #%n2" ++ [(set_attr "v8type" "alu") ++ (set_attr "mode" "SI")] ++) ++ +(define_insn "*adddi3_aarch64" + [(set + (match_operand:DI 0 "register_operand" "=rk,rk,rk,!w") @@ -14102,6 +16002,23 @@ + (set_attr "mode" "")] +) + ++;; zero_extend version of above ++(define_insn "*addsi3_compare0_uxtw" ++ [(set (reg:CC_NZ CC_REGNUM) ++ (compare:CC_NZ ++ (plus:SI (match_operand:SI 1 "register_operand" "%r,r") ++ (match_operand:SI 2 "aarch64_plus_operand" "rI,J")) ++ (const_int 0))) ++ (set (match_operand:DI 0 "register_operand" "=r,r") ++ (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))] ++ "" ++ "@ ++ adds\\t%w0, %w1, %w2 ++ subs\\t%w0, %w1, #%n2" ++ [(set_attr "v8type" "alus") ++ (set_attr "mode" "SI")] ++) ++ +(define_insn "*add3nr_compare0" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ @@ -14116,6 +16033,17 @@ + (set_attr "mode" "")] +) + ++(define_insn "*compare_neg" ++ [(set (reg:CC CC_REGNUM) ++ (compare:CC ++ (match_operand:GPI 0 "register_operand" "r") ++ (neg:GPI (match_operand:GPI 1 "register_operand" "r"))))] ++ "" ++ "cmn\\t%0, %1" ++ [(set_attr "v8type" "alus") ++ (set_attr "mode" "")] ++) ++ +(define_insn "*add__" + [(set (match_operand:GPI 0 "register_operand" "=rk") + (plus:GPI (ASHIFT:GPI (match_operand:GPI 1 "register_operand" "r") @@ -14127,6 +16055,19 @@ + (set_attr "mode" "")] +) + ++;; zero_extend version of above ++(define_insn "*add__si_uxtw" ++ [(set (match_operand:DI 0 "register_operand" "=rk") ++ (zero_extend:DI ++ (plus:SI (ASHIFT:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:QI 2 "aarch64_shift_imm_si" "n")) ++ (match_operand:SI 3 "register_operand" "r"))))] ++ "" ++ "add\\t%w0, %w3, %w1, %2" ++ [(set_attr "v8type" "alu_shift") ++ (set_attr "mode" "SI")] ++) ++ +(define_insn "*add_mul_imm_" + [(set (match_operand:GPI 0 "register_operand" "=rk") + (plus:GPI (mult:GPI (match_operand:GPI 1 "register_operand" "r") @@ -14148,6 +16089,18 @@ + (set_attr "mode" "")] +) + ++;; zero_extend version of above ++(define_insn "*add__si_uxtw" ++ [(set (match_operand:DI 0 "register_operand" "=rk") ++ (zero_extend:DI ++ (plus:SI (ANY_EXTEND:SI (match_operand:SHORT 1 "register_operand" "r")) ++ (match_operand:GPI 2 "register_operand" "r"))))] ++ "" ++ "add\\t%w0, %w2, %w1, xt" ++ [(set_attr "v8type" "alu_ext") ++ (set_attr "mode" "SI")] ++) ++ +(define_insn "*add__shft_" + [(set (match_operand:GPI 0 "register_operand" "=rk") + (plus:GPI (ashift:GPI (ANY_EXTEND:GPI @@ -14160,6 +16113,20 @@ + (set_attr "mode" "")] +) + ++;; zero_extend version of above ++(define_insn "*add__shft_si_uxtw" ++ [(set (match_operand:DI 0 "register_operand" "=rk") ++ (zero_extend:DI ++ (plus:SI (ashift:SI (ANY_EXTEND:SI ++ (match_operand:SHORT 1 "register_operand" "r")) ++ (match_operand 2 "aarch64_imm3" "Ui3")) ++ (match_operand:SI 3 "register_operand" "r"))))] ++ "" ++ "add\\t%w0, %w3, %w1, xt %2" ++ [(set_attr "v8type" "alu_ext") ++ (set_attr "mode" "SI")] ++) ++ +(define_insn "*add__mult_" + [(set (match_operand:GPI 0 "register_operand" "=rk") + (plus:GPI (mult:GPI (ANY_EXTEND:GPI @@ -14172,6 +16139,19 @@ + (set_attr "mode" "")] +) + ++;; zero_extend version of above ++(define_insn "*add__mult_si_uxtw" ++ [(set (match_operand:DI 0 "register_operand" "=rk") ++ (zero_extend:DI (plus:SI (mult:SI (ANY_EXTEND:SI ++ (match_operand:SHORT 1 "register_operand" "r")) ++ (match_operand 2 "aarch64_pwr_imm3" "Up3")) ++ (match_operand:SI 3 "register_operand" "r"))))] ++ "" ++ "add\\t%w0, %w3, %w1, xt %p2" ++ [(set_attr "v8type" "alu_ext") ++ (set_attr "mode" "SI")] ++) ++ +(define_insn "*add__multp2" + [(set (match_operand:GPI 0 "register_operand" "=rk") + (plus:GPI (ANY_EXTRACT:GPI @@ -14186,6 +16166,22 @@ + (set_attr "mode" "")] +) + ++;; zero_extend version of above ++(define_insn "*add_si_multp2_uxtw" ++ [(set (match_operand:DI 0 "register_operand" "=rk") ++ (zero_extend:DI ++ (plus:SI (ANY_EXTRACT:SI ++ (mult:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand 2 "aarch64_pwr_imm3" "Up3")) ++ (match_operand 3 "const_int_operand" "n") ++ (const_int 0)) ++ (match_operand:SI 4 "register_operand" "r"))))] ++ "aarch64_is_extend_from_extract (SImode, operands[2], operands[3])" ++ "add\\t%w0, %w4, %w1, xt%e3 %p2" ++ [(set_attr "v8type" "alu_ext") ++ (set_attr "mode" "SI")] ++) ++ +(define_insn "*add3_carryin" + [(set + (match_operand:GPI 0 "register_operand" "=r") @@ -14199,6 +16195,21 @@ + (set_attr "mode" "")] +) + ++;; zero_extend version of above ++(define_insn "*addsi3_carryin_uxtw" ++ [(set ++ (match_operand:DI 0 "register_operand" "=r") ++ (zero_extend:DI ++ (plus:SI (geu:SI (reg:CC CC_REGNUM) (const_int 0)) ++ (plus:SI ++ (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "register_operand" "r")))))] ++ "" ++ "adc\\t%w0, %w1, %w2" ++ [(set_attr "v8type" "adc") ++ (set_attr "mode" "SI")] ++) ++ +(define_insn "*add3_carryin_alt1" + [(set + (match_operand:GPI 0 "register_operand" "=r") @@ -14212,6 +16223,21 @@ + (set_attr "mode" "")] +) + ++;; zero_extend version of above ++(define_insn "*addsi3_carryin_alt1_uxtw" ++ [(set ++ (match_operand:DI 0 "register_operand" "=r") ++ (zero_extend:DI ++ (plus:SI (plus:SI ++ (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "register_operand" "r")) ++ (geu:SI (reg:CC CC_REGNUM) (const_int 0)))))] ++ "" ++ "adc\\t%w0, %w1, %w2" ++ [(set_attr "v8type" "adc") ++ (set_attr "mode" "SI")] ++) ++ +(define_insn "*add3_carryin_alt2" + [(set + (match_operand:GPI 0 "register_operand" "=r") @@ -14225,6 +16251,21 @@ + (set_attr "mode" "")] +) + ++;; zero_extend version of above ++(define_insn "*addsi3_carryin_alt2_uxtw" ++ [(set ++ (match_operand:DI 0 "register_operand" "=r") ++ (zero_extend:DI ++ (plus:SI (plus:SI ++ (geu:SI (reg:CC CC_REGNUM) (const_int 0)) ++ (match_operand:SI 1 "register_operand" "r")) ++ (match_operand:SI 2 "register_operand" "r"))))] ++ "" ++ "adc\\t%w0, %w1, %w2" ++ [(set_attr "v8type" "adc") ++ (set_attr "mode" "SI")] ++) ++ +(define_insn "*add3_carryin_alt3" + [(set + (match_operand:GPI 0 "register_operand" "=r") @@ -14238,6 +16279,21 @@ + (set_attr "mode" "")] +) + ++;; zero_extend version of above ++(define_insn "*addsi3_carryin_alt3_uxtw" ++ [(set ++ (match_operand:DI 0 "register_operand" "=r") ++ (zero_extend:DI ++ (plus:SI (plus:SI ++ (geu:SI (reg:CC CC_REGNUM) (const_int 0)) ++ (match_operand:SI 2 "register_operand" "r")) ++ (match_operand:SI 1 "register_operand" "r"))))] ++ "" ++ "adc\\t%w0, %w1, %w2" ++ [(set_attr "v8type" "adc") ++ (set_attr "mode" "SI")] ++) ++ +(define_insn "*add_uxt_multp2" + [(set (match_operand:GPI 0 "register_operand" "=rk") + (plus:GPI (and:GPI @@ -14254,6 +16310,24 @@ + (set_attr "mode" "")] +) + ++;; zero_extend version of above ++(define_insn "*add_uxtsi_multp2_uxtw" ++ [(set (match_operand:DI 0 "register_operand" "=rk") ++ (zero_extend:DI ++ (plus:SI (and:SI ++ (mult:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand 2 "aarch64_pwr_imm3" "Up3")) ++ (match_operand 3 "const_int_operand" "n")) ++ (match_operand:SI 4 "register_operand" "r"))))] ++ "aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), INTVAL (operands[3])) != 0" ++ "* ++ operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), ++ INTVAL (operands[3]))); ++ return \"add\t%w0, %w4, %w1, uxt%e3 %p2\";" ++ [(set_attr "v8type" "alu_ext") ++ (set_attr "mode" "SI")] ++) ++ +(define_insn "subsi3" + [(set (match_operand:SI 0 "register_operand" "=rk") + (minus:SI (match_operand:SI 1 "register_operand" "r") @@ -14264,6 +16338,18 @@ + (set_attr "mode" "SI")] +) + ++;; zero_extend version of above ++(define_insn "*subsi3_uxtw" ++ [(set (match_operand:DI 0 "register_operand" "=rk") ++ (zero_extend:DI ++ (minus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "register_operand" "r"))))] ++ "" ++ "sub\\t%w0, %w1, %w2" ++ [(set_attr "v8type" "alu") ++ (set_attr "mode" "SI")] ++) ++ +(define_insn "subdi3" + [(set (match_operand:DI 0 "register_operand" "=rk,!w") + (minus:DI (match_operand:DI 1 "register_operand" "r,!w") @@ -14291,6 +16377,20 @@ + (set_attr "mode" "")] +) + ++;; zero_extend version of above ++(define_insn "*subsi3_compare0_uxtw" ++ [(set (reg:CC_NZ CC_REGNUM) ++ (compare:CC_NZ (minus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "register_operand" "r")) ++ (const_int 0))) ++ (set (match_operand:DI 0 "register_operand" "=r") ++ (zero_extend:DI (minus:SI (match_dup 1) (match_dup 2))))] ++ "" ++ "subs\\t%w0, %w1, %w2" ++ [(set_attr "v8type" "alus") ++ (set_attr "mode" "SI")] ++) ++ +(define_insn "*sub__" + [(set (match_operand:GPI 0 "register_operand" "=rk") + (minus:GPI (match_operand:GPI 3 "register_operand" "r") @@ -14303,6 +16403,20 @@ + (set_attr "mode" "")] +) + ++;; zero_extend version of above ++(define_insn "*sub__si_uxtw" ++ [(set (match_operand:DI 0 "register_operand" "=rk") ++ (zero_extend:DI ++ (minus:SI (match_operand:SI 3 "register_operand" "r") ++ (ASHIFT:SI ++ (match_operand:SI 1 "register_operand" "r") ++ (match_operand:QI 2 "aarch64_shift_imm_si" "n")))))] ++ "" ++ "sub\\t%w0, %w3, %w1, %2" ++ [(set_attr "v8type" "alu_shift") ++ (set_attr "mode" "SI")] ++) ++ +(define_insn "*sub_mul_imm_" + [(set (match_operand:GPI 0 "register_operand" "=rk") + (minus:GPI (match_operand:GPI 3 "register_operand" "r") @@ -14315,6 +16429,20 @@ + (set_attr "mode" "")] +) + ++;; zero_extend version of above ++(define_insn "*sub_mul_imm_si_uxtw" ++ [(set (match_operand:DI 0 "register_operand" "=rk") ++ (zero_extend:DI ++ (minus:SI (match_operand:SI 3 "register_operand" "r") ++ (mult:SI ++ (match_operand:SI 1 "register_operand" "r") ++ (match_operand:QI 2 "aarch64_pwr_2_si" "n")))))] ++ "" ++ "sub\\t%w0, %w3, %w1, lsl %p2" ++ [(set_attr "v8type" "alu_shift") ++ (set_attr "mode" "SI")] ++) ++ +(define_insn "*sub__" + [(set (match_operand:GPI 0 "register_operand" "=rk") + (minus:GPI (match_operand:GPI 1 "register_operand" "r") @@ -14326,6 +16454,19 @@ + (set_attr "mode" "")] +) + ++;; zero_extend version of above ++(define_insn "*sub__si_uxtw" ++ [(set (match_operand:DI 0 "register_operand" "=rk") ++ (zero_extend:DI ++ (minus:SI (match_operand:SI 1 "register_operand" "r") ++ (ANY_EXTEND:SI ++ (match_operand:SHORT 2 "register_operand" "r")))))] ++ "" ++ "sub\\t%w0, %w1, %w2, xt" ++ [(set_attr "v8type" "alu_ext") ++ (set_attr "mode" "SI")] ++) ++ +(define_insn "*sub__shft_" + [(set (match_operand:GPI 0 "register_operand" "=rk") + (minus:GPI (match_operand:GPI 1 "register_operand" "r") @@ -14338,6 +16479,20 @@ + (set_attr "mode" "")] +) + ++;; zero_extend version of above ++(define_insn "*sub__shft_si_uxtw" ++ [(set (match_operand:DI 0 "register_operand" "=rk") ++ (zero_extend:DI ++ (minus:SI (match_operand:SI 1 "register_operand" "r") ++ (ashift:SI (ANY_EXTEND:SI ++ (match_operand:SHORT 2 "register_operand" "r")) ++ (match_operand 3 "aarch64_imm3" "Ui3")))))] ++ "" ++ "sub\\t%w0, %w1, %w2, xt %3" ++ [(set_attr "v8type" "alu_ext") ++ (set_attr "mode" "SI")] ++) ++ +(define_insn "*sub__multp2" + [(set (match_operand:GPI 0 "register_operand" "=rk") + (minus:GPI (match_operand:GPI 4 "register_operand" "r") @@ -14352,6 +16507,22 @@ + (set_attr "mode" "")] +) + ++;; zero_extend version of above ++(define_insn "*sub_si_multp2_uxtw" ++ [(set (match_operand:DI 0 "register_operand" "=rk") ++ (zero_extend:DI ++ (minus:SI (match_operand:SI 4 "register_operand" "r") ++ (ANY_EXTRACT:SI ++ (mult:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand 2 "aarch64_pwr_imm3" "Up3")) ++ (match_operand 3 "const_int_operand" "n") ++ (const_int 0)))))] ++ "aarch64_is_extend_from_extract (SImode, operands[2], operands[3])" ++ "sub\\t%w0, %w4, %w1, xt%e3 %p2" ++ [(set_attr "v8type" "alu_ext") ++ (set_attr "mode" "SI")] ++) ++ +(define_insn "*sub_uxt_multp2" + [(set (match_operand:GPI 0 "register_operand" "=rk") + (minus:GPI (match_operand:GPI 4 "register_operand" "r") @@ -14368,6 +16539,24 @@ + (set_attr "mode" "")] +) + ++;; zero_extend version of above ++(define_insn "*sub_uxtsi_multp2_uxtw" ++ [(set (match_operand:DI 0 "register_operand" "=rk") ++ (zero_extend:DI ++ (minus:SI (match_operand:SI 4 "register_operand" "r") ++ (and:SI ++ (mult:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand 2 "aarch64_pwr_imm3" "Up3")) ++ (match_operand 3 "const_int_operand" "n")))))] ++ "aarch64_uxt_size (exact_log2 (INTVAL (operands[2])),INTVAL (operands[3])) != 0" ++ "* ++ operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), ++ INTVAL (operands[3]))); ++ return \"sub\t%w0, %w4, %w1, uxt%e3 %p2\";" ++ [(set_attr "v8type" "alu_ext") ++ (set_attr "mode" "SI")] ++) ++ +(define_insn "neg2" + [(set (match_operand:GPI 0 "register_operand" "=r") + (neg:GPI (match_operand:GPI 1 "register_operand" "r")))] @@ -14377,6 +16566,16 @@ + (set_attr "mode" "")] +) + ++;; zero_extend version of above ++(define_insn "*negsi2_uxtw" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (zero_extend:DI (neg:SI (match_operand:SI 1 "register_operand" "r"))))] ++ "" ++ "neg\\t%w0, %w1" ++ [(set_attr "v8type" "alu") ++ (set_attr "mode" "SI")] ++) ++ +(define_insn "*neg2_compare0" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (neg:GPI (match_operand:GPI 1 "register_operand" "r")) @@ -14389,6 +16588,19 @@ + (set_attr "mode" "")] +) + ++;; zero_extend version of above ++(define_insn "*negsi2_compare0_uxtw" ++ [(set (reg:CC_NZ CC_REGNUM) ++ (compare:CC_NZ (neg:SI (match_operand:SI 1 "register_operand" "r")) ++ (const_int 0))) ++ (set (match_operand:DI 0 "register_operand" "=r") ++ (zero_extend:DI (neg:SI (match_dup 1))))] ++ "" ++ "negs\\t%w0, %w1" ++ [(set_attr "v8type" "alus") ++ (set_attr "mode" "SI")] ++) ++ +(define_insn "*neg__2" + [(set (match_operand:GPI 0 "register_operand" "=r") + (neg:GPI (ASHIFT:GPI @@ -14400,6 +16612,19 @@ + (set_attr "mode" "")] +) + ++;; zero_extend version of above ++(define_insn "*neg__si2_uxtw" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (zero_extend:DI ++ (neg:SI (ASHIFT:SI ++ (match_operand:SI 1 "register_operand" "r") ++ (match_operand:QI 2 "aarch64_shift_imm_si" "n")))))] ++ "" ++ "neg\\t%w0, %w1, %2" ++ [(set_attr "v8type" "alu_shift") ++ (set_attr "mode" "SI")] ++) ++ +(define_insn "*neg_mul_imm_2" + [(set (match_operand:GPI 0 "register_operand" "=r") + (neg:GPI (mult:GPI @@ -14411,6 +16636,19 @@ + (set_attr "mode" "")] +) + ++;; zero_extend version of above ++(define_insn "*neg_mul_imm_si2_uxtw" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (zero_extend:DI ++ (neg:SI (mult:SI ++ (match_operand:SI 1 "register_operand" "r") ++ (match_operand:QI 2 "aarch64_pwr_2_si" "n")))))] ++ "" ++ "neg\\t%w0, %w1, lsl %p2" ++ [(set_attr "v8type" "alu_shift") ++ (set_attr "mode" "SI")] ++) ++ +(define_insn "mul3" + [(set (match_operand:GPI 0 "register_operand" "=r") + (mult:GPI (match_operand:GPI 1 "register_operand" "r") @@ -14421,6 +16659,18 @@ + (set_attr "mode" "")] +) + ++;; zero_extend version of above ++(define_insn "*mulsi3_uxtw" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (zero_extend:DI ++ (mult:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "register_operand" "r"))))] ++ "" ++ "mul\\t%w0, %w1, %w2" ++ [(set_attr "v8type" "mult") ++ (set_attr "mode" "SI")] ++) ++ +(define_insn "*madd" + [(set (match_operand:GPI 0 "register_operand" "=r") + (plus:GPI (mult:GPI (match_operand:GPI 1 "register_operand" "r") @@ -14432,6 +16682,19 @@ + (set_attr "mode" "")] +) + ++;; zero_extend version of above ++(define_insn "*maddsi_uxtw" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (zero_extend:DI ++ (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "register_operand" "r")) ++ (match_operand:SI 3 "register_operand" "r"))))] ++ "" ++ "madd\\t%w0, %w1, %w2, %w3" ++ [(set_attr "v8type" "madd") ++ (set_attr "mode" "SI")] ++) ++ +(define_insn "*msub" + [(set (match_operand:GPI 0 "register_operand" "=r") + (minus:GPI (match_operand:GPI 3 "register_operand" "r") @@ -14444,6 +16707,20 @@ + (set_attr "mode" "")] +) + ++;; zero_extend version of above ++(define_insn "*msubsi_uxtw" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (zero_extend:DI ++ (minus:SI (match_operand:SI 3 "register_operand" "r") ++ (mult:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "register_operand" "r")))))] ++ ++ "" ++ "msub\\t%w0, %w1, %w2, %w3" ++ [(set_attr "v8type" "madd") ++ (set_attr "mode" "SI")] ++) ++ +(define_insn "*mul_neg" + [(set (match_operand:GPI 0 "register_operand" "=r") + (mult:GPI (neg:GPI (match_operand:GPI 1 "register_operand" "r")) @@ -14455,6 +16732,19 @@ + (set_attr "mode" "")] +) + ++;; zero_extend version of above ++(define_insn "*mulsi_neg_uxtw" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (zero_extend:DI ++ (mult:SI (neg:SI (match_operand:SI 1 "register_operand" "r")) ++ (match_operand:SI 2 "register_operand" "r"))))] ++ ++ "" ++ "mneg\\t%w0, %w1, %w2" ++ [(set_attr "v8type" "mult") ++ (set_attr "mode" "SI")] ++) ++ +(define_insn "mulsidi3" + [(set (match_operand:DI 0 "register_operand" "=r") + (mult:DI (ANY_EXTEND:DI (match_operand:SI 1 "register_operand" "r")) @@ -14525,6 +16815,18 @@ + (set_attr "mode" "")] +) + ++;; zero_extend version of above ++(define_insn "*divsi3_uxtw" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (zero_extend:DI ++ (ANY_DIV:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "register_operand" "r"))))] ++ "" ++ "div\\t%w0, %w1, %w2" ++ [(set_attr "v8type" "div") ++ (set_attr "mode" "SI")] ++) ++ +;; ------------------------------------------------------------------- +;; Comparison insns +;; ------------------------------------------------------------------- @@ -14672,19 +16974,23 @@ +) + +(define_insn "*cmov_insn" -+ [(set (match_operand:ALLI 0 "register_operand" "=r,r,r,r") ++ [(set (match_operand:ALLI 0 "register_operand" "=r,r,r,r,r,r,r") + (if_then_else:ALLI + (match_operator 1 "aarch64_comparison_operator" + [(match_operand 2 "cc_register" "") (const_int 0)]) -+ (match_operand:ALLI 3 "aarch64_reg_zero_or_m1" "rZ,rZ,UsM,UsM") -+ (match_operand:ALLI 4 "aarch64_reg_zero_or_m1" "rZ,UsM,rZ,UsM")))] -+ "" -+ ;; Final alternative should be unreachable, but included for completeness ++ (match_operand:ALLI 3 "aarch64_reg_zero_or_m1_or_1" "rZ,rZ,UsM,rZ,Ui1,UsM,Ui1") ++ (match_operand:ALLI 4 "aarch64_reg_zero_or_m1_or_1" "rZ,UsM,rZ,Ui1,rZ,UsM,Ui1")))] ++ "!((operands[3] == const1_rtx && operands[4] == constm1_rtx) ++ || (operands[3] == constm1_rtx && operands[4] == const1_rtx))" ++ ;; Final two alternatives should be unreachable, but included for completeness + "@ + csel\\t%0, %3, %4, %m1 + csinv\\t%0, %3, zr, %m1 + csinv\\t%0, %4, zr, %M1 -+ mov\\t%0, -1" ++ csinc\\t%0, %3, zr, %m1 ++ csinc\\t%0, %4, zr, %M1 ++ mov\\t%0, -1 ++ mov\\t%0, 1" + [(set_attr "v8type" "csel") + (set_attr "mode" "")] +) @@ -15151,121 +17457,40 @@ + (set_attr "mode" "")] +) + ++(define_insn "bswaphi2" ++ [(set (match_operand:HI 0 "register_operand" "=r") ++ (bswap:HI (match_operand:HI 1 "register_operand" "r")))] ++ "" ++ "rev16\\t%w0, %w1" ++ [(set_attr "v8type" "rev") ++ (set_attr "mode" "HI")] ++) ++ +;; ------------------------------------------------------------------- +;; Floating-point intrinsics +;; ------------------------------------------------------------------- + -+;; trunc - nothrow -+ -+(define_insn "btrunc2" -+ [(set (match_operand:GPF 0 "register_operand" "=w") -+ (unspec:GPF [(match_operand:GPF 1 "register_operand" "w")] -+ UNSPEC_FRINTZ))] -+ "TARGET_FLOAT" -+ "frintz\\t%0, %1" -+ [(set_attr "v8type" "frint") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*lbtrunc2" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (FIXUORS:GPI (unspec:GPF [(match_operand:GPF 1 "register_operand" "w")] -+ UNSPEC_FRINTZ)))] -+ "TARGET_FLOAT" -+ "fcvtz\\t%0, %1" -+ [(set_attr "v8type" "fcvtf2i") -+ (set_attr "mode" "") -+ (set_attr "mode2" "")] -+) -+ -+;; ceil - nothrow -+ -+(define_insn "ceil2" -+ [(set (match_operand:GPF 0 "register_operand" "=w") -+ (unspec:GPF [(match_operand:GPF 1 "register_operand" "w")] -+ UNSPEC_FRINTP))] -+ "TARGET_FLOAT" -+ "frintp\\t%0, %1" -+ [(set_attr "v8type" "frint") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "lceil2" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (FIXUORS:GPI (unspec:GPF [(match_operand:GPF 1 "register_operand" "w")] -+ UNSPEC_FRINTP)))] -+ "TARGET_FLOAT" -+ "fcvtp\\t%0, %1" -+ [(set_attr "v8type" "fcvtf2i") -+ (set_attr "mode" "") -+ (set_attr "mode2" "")] -+) -+ -+;; floor - nothrow -+ -+(define_insn "floor2" -+ [(set (match_operand:GPF 0 "register_operand" "=w") -+ (unspec:GPF [(match_operand:GPF 1 "register_operand" "w")] -+ UNSPEC_FRINTM))] -+ "TARGET_FLOAT" -+ "frintm\\t%0, %1" -+ [(set_attr "v8type" "frint") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "lfloor2" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (FIXUORS:GPI (unspec:GPF [(match_operand:GPF 1 "register_operand" "w")] -+ UNSPEC_FRINTM)))] -+ "TARGET_FLOAT" -+ "fcvtm\\t%0, %1" -+ [(set_attr "v8type" "fcvtf2i") -+ (set_attr "mode" "") -+ (set_attr "mode2" "")] -+) -+ -+;; nearbyint - nothrow -+ -+(define_insn "nearbyint2" -+ [(set (match_operand:GPF 0 "register_operand" "=w") -+ (unspec:GPF [(match_operand:GPF 1 "register_operand" "w")] -+ UNSPEC_FRINTI))] -+ "TARGET_FLOAT" -+ "frinti\\t%0, %1" -+ [(set_attr "v8type" "frint") -+ (set_attr "mode" "")] -+) -+ -+;; rint -+ -+(define_insn "rint2" -+ [(set (match_operand:GPF 0 "register_operand" "=w") -+ (unspec:GPF [(match_operand:GPF 1 "register_operand" "w")] -+ UNSPEC_FRINTX))] -+ "TARGET_FLOAT" -+ "frintx\\t%0, %1" -+ [(set_attr "v8type" "frint") -+ (set_attr "mode" "")] -+) -+ -+;; round - nothrow ++;; frint floating-point round to integral standard patterns. ++;; Expands to btrunc, ceil, floor, nearbyint, rint, round. + -+(define_insn "round2" ++(define_insn "2" + [(set (match_operand:GPF 0 "register_operand" "=w") -+ (unspec:GPF [(match_operand:GPF 1 "register_operand" "w")] -+ UNSPEC_FRINTA))] ++ (unspec:GPF [(match_operand:GPF 1 "register_operand" "w")] ++ FRINT))] + "TARGET_FLOAT" -+ "frinta\\t%0, %1" ++ "frint\\t%0, %1" + [(set_attr "v8type" "frint") + (set_attr "mode" "")] +) + -+(define_insn "lround2" ++;; frcvt floating-point round to integer and convert standard patterns. ++;; Expands to lbtrunc, lceil, lfloor, lround. ++(define_insn "l2" + [(set (match_operand:GPI 0 "register_operand" "=r") -+ (FIXUORS:GPI (unspec:GPF [(match_operand:GPF 1 "register_operand" "w")] -+ UNSPEC_FRINTA)))] ++ (FIXUORS:GPI (unspec:GPF [(match_operand:GPF 1 "register_operand" "w")] ++ FCVT)))] + "TARGET_FLOAT" -+ "fcvta\\t%0, %1" ++ "fcvt\\t%0, %1" + [(set_attr "v8type" "fcvtf2i") + (set_attr "mode" "") + (set_attr "mode2" "")] @@ -15724,8 +17949,8 @@ +;; AdvSIMD Stuff +(include "aarch64-simd.md") + -+;; Synchronization Builtins -+(include "sync.md") ++;; Atomic Operations ++(include "atomics.md") --- a/src/gcc/config/aarch64/aarch64-modes.def +++ b/src/gcc/config/aarch64/aarch64-modes.def @@ -0,0 +1,54 @@ @@ -15995,9 +18220,9 @@ +#endif --- a/src/gcc/config/aarch64/aarch64-protos.h +++ b/src/gcc/config/aarch64/aarch64-protos.h -@@ -0,0 +1,260 @@ +@@ -0,0 +1,254 @@ +/* Machine description for AArch64 architecture. -+ Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. ++ Copyright (C) 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc. + Contributed by ARM Ltd. + + This file is part of GCC. @@ -16020,35 +18245,6 @@ +#ifndef GCC_AARCH64_PROTOS_H +#define GCC_AARCH64_PROTOS_H + -+ /* This generator struct and enum is used to wrap a function pointer -+ to a function that generates an RTX fragment but takes either 3 or -+ 4 operands. -+ -+ The omn flavour, wraps a function that generates a synchronization -+ instruction from 3 operands: old value, memory and new value. -+ -+ The omrn flavour, wraps a function that generates a synchronization -+ instruction from 4 operands: old value, memory, required value and -+ new value. */ -+ -+enum aarch64_sync_generator_tag -+{ -+ aarch64_sync_generator_omn, -+ aarch64_sync_generator_omrn -+}; -+ -+ /* Wrapper to pass around a polymorphic pointer to a sync instruction -+ generator and. */ -+struct aarch64_sync_generator -+{ -+ enum aarch64_sync_generator_tag op; -+ union -+ { -+ rtx (*omn) (rtx, rtx, rtx); -+ rtx (*omrn) (rtx, rtx, rtx, rtx); -+ } u; -+}; -+ +/* + SYMBOL_CONTEXT_ADR + The symbol is used in a load-address operation. @@ -16163,8 +18359,8 @@ + +HOST_WIDE_INT aarch64_initial_elimination_offset (unsigned, unsigned); +bool aarch64_bitmask_imm (HOST_WIDE_INT val, enum machine_mode); -+bool aarch64_const_double_zero_rtx_p (rtx); +bool aarch64_constant_address_p (rtx); ++bool aarch64_float_const_zero_rtx_p (rtx); +bool aarch64_function_arg_regno_p (unsigned); +bool aarch64_gen_movmemqi (rtx *); +bool aarch64_is_extend_from_extract (enum machine_mode, rtx, rtx); @@ -16184,8 +18380,6 @@ + enum aarch64_symbol_type *); +bool aarch64_uimm12_shift (HOST_WIDE_INT); +const char *aarch64_output_casesi (rtx *); -+const char *aarch64_output_sync_insn (rtx, rtx *); -+const char *aarch64_output_sync_lock_release (rtx, rtx); +enum aarch64_symbol_type aarch64_classify_symbol (rtx, + enum aarch64_symbol_context); +enum aarch64_symbol_type aarch64_classify_tls_symbol (rtx); @@ -16208,14 +18402,12 @@ +unsigned aarch64_dbx_register_number (unsigned); +unsigned aarch64_regno_regclass (unsigned); +unsigned aarch64_trampoline_size (void); -+unsigned aarch64_sync_loop_insns (rtx, rtx *); +void aarch64_asm_output_labelref (FILE *, const char *); +void aarch64_elf_asm_named_section (const char *, unsigned, tree); +void aarch64_expand_epilogue (bool); +void aarch64_expand_mov_immediate (rtx, rtx); +void aarch64_expand_prologue (void); -+void aarch64_expand_sync (enum machine_mode, struct aarch64_sync_generator *, -+ rtx, rtx, rtx, rtx); ++void aarch64_expand_vector_init (rtx, rtx); +void aarch64_function_profiler (FILE *, int); +void aarch64_init_cumulative_args (CUMULATIVE_ARGS *, const_tree, rtx, + const_tree, unsigned); @@ -16247,20 +18439,308 @@ + +bool aarch64_split_128bit_move_p (rtx, rtx); + ++/* Check for a legitimate floating point constant for FMOV. */ ++bool aarch64_float_const_representable_p (rtx); ++ +#if defined (RTX_CODE) + +bool aarch64_legitimate_address_p (enum machine_mode, rtx, RTX_CODE, bool); +enum machine_mode aarch64_select_cc_mode (RTX_CODE, rtx, rtx); +rtx aarch64_gen_compare_reg (RTX_CODE, rtx, rtx); + ++void aarch64_expand_compare_and_swap (rtx op[]); ++void aarch64_split_compare_and_swap (rtx op[]); ++void aarch64_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx); ++ +#endif /* RTX_CODE */ + ++rtx aarch64_load_tp (rtx target); ++void aarch64_init_builtins (void); ++rtx aarch64_expand_builtin (tree exp, ++ rtx target, ++ rtx subtarget ATTRIBUTE_UNUSED, ++ enum machine_mode mode ATTRIBUTE_UNUSED, ++ int ignore ATTRIBUTE_UNUSED); ++tree aarch64_builtin_decl (unsigned, bool ATTRIBUTE_UNUSED); ++ ++tree ++aarch64_builtin_vectorized_function (tree fndecl, ++ tree type_out, ++ tree type_in); ++ ++extern void aarch64_split_combinev16qi (rtx operands[3]); ++extern void aarch64_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel); ++extern bool ++aarch64_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel); ++ ++char* aarch64_output_simd_mov_immediate (rtx *, enum machine_mode, unsigned); +#endif /* GCC_AARCH64_PROTOS_H */ +--- a/src/gcc/config/aarch64/aarch64-simd-builtins.def ++++ b/src/gcc/config/aarch64/aarch64-simd-builtins.def +@@ -0,0 +1,258 @@ ++/* Machine description for AArch64 architecture. ++ Copyright (C) 2012-2013 Free Software Foundation, Inc. ++ Contributed by ARM Ltd. ++ ++ This file is part of GCC. ++ ++ GCC is free software; you can redistribute it and/or modify it ++ under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3, or (at your option) ++ any later version. ++ ++ GCC is distributed in the hope that it will be useful, but ++ WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with GCC; see the file COPYING3. If not see ++ . */ ++ ++/* In the list below, the BUILTIN_ macros should ++ correspond to the iterator used to construct the instruction's ++ patterns in aarch64-simd.md. A helpful idiom to follow when ++ adding new builtins is to add a line for each pattern in the md ++ file. Thus, ADDP, which has one pattern defined for the VD_BHSI ++ iterator, and one for DImode, has two entries below. */ ++ ++ BUILTIN_VD_RE (CREATE, create) ++ BUILTIN_VQ_S (GETLANE, get_lane_signed) ++ BUILTIN_VDQ (GETLANE, get_lane_unsigned) ++ BUILTIN_VDQF (GETLANE, get_lane) ++ VAR1 (GETLANE, get_lane, di) ++ BUILTIN_VDC (COMBINE, combine) ++ BUILTIN_VB (BINOP, pmul) ++ BUILTIN_VDQF (UNOP, sqrt) ++ BUILTIN_VD_BHSI (BINOP, addp) ++ VAR1 (UNOP, addp, di) ++ ++ BUILTIN_VD_RE (REINTERP, reinterpretdi) ++ BUILTIN_VDC (REINTERP, reinterpretv8qi) ++ BUILTIN_VDC (REINTERP, reinterpretv4hi) ++ BUILTIN_VDC (REINTERP, reinterpretv2si) ++ BUILTIN_VDC (REINTERP, reinterpretv2sf) ++ BUILTIN_VQ (REINTERP, reinterpretv16qi) ++ BUILTIN_VQ (REINTERP, reinterpretv8hi) ++ BUILTIN_VQ (REINTERP, reinterpretv4si) ++ BUILTIN_VQ (REINTERP, reinterpretv4sf) ++ BUILTIN_VQ (REINTERP, reinterpretv2di) ++ BUILTIN_VQ (REINTERP, reinterpretv2df) ++ ++ BUILTIN_VDQ_I (BINOP, dup_lane) ++ BUILTIN_SDQ_I (BINOP, dup_lane) ++ /* Implemented by aarch64_qshl. */ ++ BUILTIN_VSDQ_I (BINOP, sqshl) ++ BUILTIN_VSDQ_I (BINOP, uqshl) ++ BUILTIN_VSDQ_I (BINOP, sqrshl) ++ BUILTIN_VSDQ_I (BINOP, uqrshl) ++ /* Implemented by aarch64_. */ ++ BUILTIN_VSDQ_I (BINOP, sqadd) ++ BUILTIN_VSDQ_I (BINOP, uqadd) ++ BUILTIN_VSDQ_I (BINOP, sqsub) ++ BUILTIN_VSDQ_I (BINOP, uqsub) ++ /* Implemented by aarch64_qadd. */ ++ BUILTIN_VSDQ_I (BINOP, suqadd) ++ BUILTIN_VSDQ_I (BINOP, usqadd) ++ ++ /* Implemented by aarch64_get_dreg. */ ++ BUILTIN_VDC (GETLANE, get_dregoi) ++ BUILTIN_VDC (GETLANE, get_dregci) ++ BUILTIN_VDC (GETLANE, get_dregxi) ++ /* Implemented by aarch64_get_qreg. */ ++ BUILTIN_VQ (GETLANE, get_qregoi) ++ BUILTIN_VQ (GETLANE, get_qregci) ++ BUILTIN_VQ (GETLANE, get_qregxi) ++ /* Implemented by aarch64_set_qreg. */ ++ BUILTIN_VQ (SETLANE, set_qregoi) ++ BUILTIN_VQ (SETLANE, set_qregci) ++ BUILTIN_VQ (SETLANE, set_qregxi) ++ /* Implemented by aarch64_ld. */ ++ BUILTIN_VDC (LOADSTRUCT, ld2) ++ BUILTIN_VDC (LOADSTRUCT, ld3) ++ BUILTIN_VDC (LOADSTRUCT, ld4) ++ /* Implemented by aarch64_ld. */ ++ BUILTIN_VQ (LOADSTRUCT, ld2) ++ BUILTIN_VQ (LOADSTRUCT, ld3) ++ BUILTIN_VQ (LOADSTRUCT, ld4) ++ /* Implemented by aarch64_st. */ ++ BUILTIN_VDC (STORESTRUCT, st2) ++ BUILTIN_VDC (STORESTRUCT, st3) ++ BUILTIN_VDC (STORESTRUCT, st4) ++ /* Implemented by aarch64_st. */ ++ BUILTIN_VQ (STORESTRUCT, st2) ++ BUILTIN_VQ (STORESTRUCT, st3) ++ BUILTIN_VQ (STORESTRUCT, st4) ++ ++ BUILTIN_VQW (BINOP, saddl2) ++ BUILTIN_VQW (BINOP, uaddl2) ++ BUILTIN_VQW (BINOP, ssubl2) ++ BUILTIN_VQW (BINOP, usubl2) ++ BUILTIN_VQW (BINOP, saddw2) ++ BUILTIN_VQW (BINOP, uaddw2) ++ BUILTIN_VQW (BINOP, ssubw2) ++ BUILTIN_VQW (BINOP, usubw2) ++ /* Implemented by aarch64_l. */ ++ BUILTIN_VDW (BINOP, saddl) ++ BUILTIN_VDW (BINOP, uaddl) ++ BUILTIN_VDW (BINOP, ssubl) ++ BUILTIN_VDW (BINOP, usubl) ++ /* Implemented by aarch64_w. */ ++ BUILTIN_VDW (BINOP, saddw) ++ BUILTIN_VDW (BINOP, uaddw) ++ BUILTIN_VDW (BINOP, ssubw) ++ BUILTIN_VDW (BINOP, usubw) ++ /* Implemented by aarch64_h. */ ++ BUILTIN_VQ_S (BINOP, shadd) ++ BUILTIN_VQ_S (BINOP, uhadd) ++ BUILTIN_VQ_S (BINOP, srhadd) ++ BUILTIN_VQ_S (BINOP, urhadd) ++ /* Implemented by aarch64_hn. */ ++ BUILTIN_VQN (BINOP, addhn) ++ BUILTIN_VQN (BINOP, raddhn) ++ /* Implemented by aarch64_hn2. */ ++ BUILTIN_VQN (TERNOP, addhn2) ++ BUILTIN_VQN (TERNOP, raddhn2) ++ ++ BUILTIN_VSQN_HSDI (UNOP, sqmovun) ++ /* Implemented by aarch64_qmovn. */ ++ BUILTIN_VSQN_HSDI (UNOP, sqmovn) ++ BUILTIN_VSQN_HSDI (UNOP, uqmovn) ++ /* Implemented by aarch64_s. */ ++ BUILTIN_VSDQ_I_BHSI (UNOP, sqabs) ++ BUILTIN_VSDQ_I_BHSI (UNOP, sqneg) ++ ++ BUILTIN_VSD_HSI (QUADOP, sqdmlal_lane) ++ BUILTIN_VSD_HSI (QUADOP, sqdmlsl_lane) ++ BUILTIN_VSD_HSI (QUADOP, sqdmlal_laneq) ++ BUILTIN_VSD_HSI (QUADOP, sqdmlsl_laneq) ++ BUILTIN_VQ_HSI (TERNOP, sqdmlal2) ++ BUILTIN_VQ_HSI (TERNOP, sqdmlsl2) ++ BUILTIN_VQ_HSI (QUADOP, sqdmlal2_lane) ++ BUILTIN_VQ_HSI (QUADOP, sqdmlsl2_lane) ++ BUILTIN_VQ_HSI (QUADOP, sqdmlal2_laneq) ++ BUILTIN_VQ_HSI (QUADOP, sqdmlsl2_laneq) ++ BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n) ++ BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n) ++ /* Implemented by aarch64_sqdmll. */ ++ BUILTIN_VSD_HSI (TERNOP, sqdmlal) ++ BUILTIN_VSD_HSI (TERNOP, sqdmlsl) ++ /* Implemented by aarch64_sqdmll_n. */ ++ BUILTIN_VD_HSI (TERNOP, sqdmlal_n) ++ BUILTIN_VD_HSI (TERNOP, sqdmlsl_n) ++ ++ BUILTIN_VSD_HSI (BINOP, sqdmull) ++ BUILTIN_VSD_HSI (TERNOP, sqdmull_lane) ++ BUILTIN_VD_HSI (TERNOP, sqdmull_laneq) ++ BUILTIN_VD_HSI (BINOP, sqdmull_n) ++ BUILTIN_VQ_HSI (BINOP, sqdmull2) ++ BUILTIN_VQ_HSI (TERNOP, sqdmull2_lane) ++ BUILTIN_VQ_HSI (TERNOP, sqdmull2_laneq) ++ BUILTIN_VQ_HSI (BINOP, sqdmull2_n) ++ /* Implemented by aarch64_sqdmulh. */ ++ BUILTIN_VSDQ_HSI (BINOP, sqdmulh) ++ BUILTIN_VSDQ_HSI (BINOP, sqrdmulh) ++ /* Implemented by aarch64_sqdmulh_lane. */ ++ BUILTIN_VDQHS (TERNOP, sqdmulh_lane) ++ BUILTIN_VDQHS (TERNOP, sqdmulh_laneq) ++ BUILTIN_VDQHS (TERNOP, sqrdmulh_lane) ++ BUILTIN_VDQHS (TERNOP, sqrdmulh_laneq) ++ BUILTIN_SD_HSI (TERNOP, sqdmulh_lane) ++ BUILTIN_SD_HSI (TERNOP, sqrdmulh_lane) ++ ++ BUILTIN_VSDQ_I_DI (BINOP, sshl_n) ++ BUILTIN_VSDQ_I_DI (BINOP, ushl_n) ++ /* Implemented by aarch64_shl. */ ++ BUILTIN_VSDQ_I_DI (BINOP, sshl) ++ BUILTIN_VSDQ_I_DI (BINOP, ushl) ++ BUILTIN_VSDQ_I_DI (BINOP, srshl) ++ BUILTIN_VSDQ_I_DI (BINOP, urshl) ++ ++ BUILTIN_VSDQ_I_DI (SHIFTIMM, sshr_n) ++ BUILTIN_VSDQ_I_DI (SHIFTIMM, ushr_n) ++ /* Implemented by aarch64_shr_n. */ ++ BUILTIN_VSDQ_I_DI (SHIFTIMM, srshr_n) ++ BUILTIN_VSDQ_I_DI (SHIFTIMM, urshr_n) ++ /* Implemented by aarch64_sra_n. */ ++ BUILTIN_VSDQ_I_DI (SHIFTACC, ssra_n) ++ BUILTIN_VSDQ_I_DI (SHIFTACC, usra_n) ++ BUILTIN_VSDQ_I_DI (SHIFTACC, srsra_n) ++ BUILTIN_VSDQ_I_DI (SHIFTACC, ursra_n) ++ /* Implemented by aarch64_shll_n. */ ++ BUILTIN_VDW (SHIFTIMM, sshll_n) ++ BUILTIN_VDW (SHIFTIMM, ushll_n) ++ /* Implemented by aarch64_shll2_n. */ ++ BUILTIN_VQW (SHIFTIMM, sshll2_n) ++ BUILTIN_VQW (SHIFTIMM, ushll2_n) ++ /* Implemented by aarch64_qshrn_n. */ ++ BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrun_n) ++ BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrun_n) ++ BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrn_n) ++ BUILTIN_VSQN_HSDI (SHIFTIMM, uqshrn_n) ++ BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrn_n) ++ BUILTIN_VSQN_HSDI (SHIFTIMM, uqrshrn_n) ++ /* Implemented by aarch64_si_n. */ ++ BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n) ++ BUILTIN_VSDQ_I_DI (SHIFTINSERT, usri_n) ++ BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n) ++ BUILTIN_VSDQ_I_DI (SHIFTINSERT, usli_n) ++ /* Implemented by aarch64_qshl_n. */ ++ BUILTIN_VSDQ_I (SHIFTIMM, sqshlu_n) ++ BUILTIN_VSDQ_I (SHIFTIMM, sqshl_n) ++ BUILTIN_VSDQ_I (SHIFTIMM, uqshl_n) ++ ++ /* Implemented by aarch64_cm. */ ++ BUILTIN_VSDQ_I_DI (BINOP, cmeq) ++ BUILTIN_VSDQ_I_DI (BINOP, cmge) ++ BUILTIN_VSDQ_I_DI (BINOP, cmgt) ++ BUILTIN_VSDQ_I_DI (BINOP, cmle) ++ BUILTIN_VSDQ_I_DI (BINOP, cmlt) ++ /* Implemented by aarch64_cm. */ ++ BUILTIN_VSDQ_I_DI (BINOP, cmhs) ++ BUILTIN_VSDQ_I_DI (BINOP, cmhi) ++ BUILTIN_VSDQ_I_DI (BINOP, cmtst) ++ ++ /* Implemented by aarch64_. */ ++ BUILTIN_VDQF (BINOP, fmax) ++ BUILTIN_VDQF (BINOP, fmin) ++ /* Implemented by aarch64_. */ ++ BUILTIN_VDQ_BHSI (BINOP, smax) ++ BUILTIN_VDQ_BHSI (BINOP, smin) ++ BUILTIN_VDQ_BHSI (BINOP, umax) ++ BUILTIN_VDQ_BHSI (BINOP, umin) ++ ++ /* Implemented by aarch64_frint. */ ++ BUILTIN_VDQF (UNOP, frintz) ++ BUILTIN_VDQF (UNOP, frintp) ++ BUILTIN_VDQF (UNOP, frintm) ++ BUILTIN_VDQF (UNOP, frinti) ++ BUILTIN_VDQF (UNOP, frintx) ++ BUILTIN_VDQF (UNOP, frinta) ++ ++ /* Implemented by aarch64_fcvt. */ ++ BUILTIN_VDQF (UNOP, fcvtzs) ++ BUILTIN_VDQF (UNOP, fcvtzu) ++ BUILTIN_VDQF (UNOP, fcvtas) ++ BUILTIN_VDQF (UNOP, fcvtau) ++ BUILTIN_VDQF (UNOP, fcvtps) ++ BUILTIN_VDQF (UNOP, fcvtpu) ++ BUILTIN_VDQF (UNOP, fcvtms) ++ BUILTIN_VDQF (UNOP, fcvtmu) ++ ++ /* Implemented by ++ aarch64_. */ ++ BUILTIN_VALL (BINOP, zip1) ++ BUILTIN_VALL (BINOP, zip2) ++ BUILTIN_VALL (BINOP, uzp1) ++ BUILTIN_VALL (BINOP, uzp2) ++ BUILTIN_VALL (BINOP, trn1) ++ BUILTIN_VALL (BINOP, trn2) --- a/src/gcc/config/aarch64/aarch64-simd.md +++ b/src/gcc/config/aarch64/aarch64-simd.md -@@ -0,0 +1,3264 @@ +@@ -0,0 +1,3692 @@ +;; Machine description for AArch64 AdvSIMD architecture. -+;; Copyright (C) 2011, 2012 Free Software Foundation, Inc. ++;; Copyright (C) 2011, 2012, 2013 Free Software Foundation, Inc. +;; Contributed by ARM Ltd. +;; +;; This file is part of GCC. @@ -16389,7 +18869,8 @@ +; simd_store4s store single structure from one lane for four registers (ST4 [index]). +; simd_tbl table lookup. +; simd_trn transpose. -+; simd_zip zip/unzip. ++; simd_uzp unzip. ++; simd_zip zip. + +(define_attr "simd_type" + "simd_abd,\ @@ -16491,6 +18972,7 @@ + simd_store4s,\ + simd_tbl,\ + simd_trn,\ ++ simd_uzp,\ + simd_zip,\ + none" + (const_string "none")) @@ -16653,34 +19135,8 @@ + case 4: return "ins\t%0.d[0], %1"; + case 5: return "mov\t%0, %1"; + case 6: -+ { -+ int is_valid; -+ unsigned char widthc; -+ int width; -+ static char templ[40]; -+ int shift = 0, mvn = 0; -+ const char *mnemonic; -+ int length = 0; -+ -+ is_valid = -+ aarch64_simd_immediate_valid_for_move (operands[1], mode, -+ &operands[1], &width, &widthc, -+ &mvn, &shift); -+ gcc_assert (is_valid != 0); -+ -+ mnemonic = mvn ? "mvni" : "movi"; -+ if (widthc != 'd') -+ length += snprintf (templ, sizeof (templ), -+ "%s\t%%0.%d%c, %%1", -+ mnemonic, 64 / width, widthc); -+ else -+ length += snprintf (templ, sizeof (templ), "%s\t%%d0, %%1", mnemonic); -+ -+ if (shift != 0) -+ length += snprintf (templ + length, sizeof (templ) - length, -+ ", lsl %d", shift); -+ return templ; -+ } ++ return aarch64_output_simd_mov_immediate (&operands[1], ++ mode, 64); + default: gcc_unreachable (); + } +} @@ -16697,39 +19153,19 @@ + && (register_operand (operands[0], mode) + || register_operand (operands[1], mode))" +{ -+ switch (which_alternative) -+ { -+ case 0: return "ld1\t{%0.}, %1"; -+ case 1: return "st1\t{%1.}, %0"; -+ case 2: return "orr\t%0., %1., %1."; -+ case 3: return "umov\t%0, %1.d[0]\;umov\t%H0, %1.d[1]"; -+ case 4: return "ins\t%0.d[0], %1\;ins\t%0.d[1], %H1"; -+ case 5: return "#"; -+ case 6: -+ { -+ int is_valid; -+ unsigned char widthc; -+ int width; -+ static char templ[40]; -+ int shift = 0, mvn = 0; -+ -+ is_valid = -+ aarch64_simd_immediate_valid_for_move (operands[1], mode, -+ &operands[1], &width, &widthc, -+ &mvn, &shift); -+ gcc_assert (is_valid != 0); -+ if (shift) -+ snprintf (templ, sizeof (templ), "%s\t%%0.%d%c, %%1, lsl %d", -+ mvn ? "mvni" : "movi", -+ 128 / width, widthc, shift); -+ else -+ snprintf (templ, sizeof (templ), "%s\t%%0.%d%c, %%1", -+ mvn ? "mvni" : "movi", -+ 128 / width, widthc); -+ return templ; -+ } -+ default: gcc_unreachable (); -+ } ++ switch (which_alternative) ++ { ++ case 0: return "ld1\t{%0.}, %1"; ++ case 1: return "st1\t{%1.}, %0"; ++ case 2: return "orr\t%0., %1., %1."; ++ case 3: return "umov\t%0, %1.d[0]\;umov\t%H0, %1.d[1]"; ++ case 4: return "ins\t%0.d[0], %1\;ins\t%0.d[1], %H1"; ++ case 5: return "#"; ++ case 6: ++ return aarch64_output_simd_mov_immediate (&operands[1], ++ mode, 128); ++ default: gcc_unreachable (); ++ } +} + [(set_attr "simd_type" "simd_load1,simd_store1,simd_move,simd_movgp,simd_insgp,simd_move,simd_move_imm") + (set_attr "simd_mode" "") @@ -17359,7 +19795,7 @@ + (match_operand:VQW 2 "register_operand" "w") + (match_dup 3)))))] + "TARGET_SIMD" -+ "mull %0., %1., %2." ++ "mull\\t%0., %1., %2." + [(set_attr "simd_type" "simd_mull") + (set_attr "simd_mode" "")] +) @@ -17387,7 +19823,7 @@ + (match_operand:VQW 2 "register_operand" "w") + (match_dup 3)))))] + "TARGET_SIMD" -+ "mull2 %0., %1., %2." ++ "mull2\\t%0., %1., %2." + [(set_attr "simd_type" "simd_mull") + (set_attr "simd_mode" "")] +) @@ -17501,6 +19937,46 @@ + (set_attr "simd_mode" "")] +) + ++(define_insn "aarch64_frint" ++ [(set (match_operand:VDQF 0 "register_operand" "=w") ++ (unspec:VDQF [(match_operand:VDQF 1 "register_operand" "w")] ++ FRINT))] ++ "TARGET_SIMD" ++ "frint\\t%0., %1." ++ [(set_attr "simd_type" "simd_frint") ++ (set_attr "simd_mode" "")] ++) ++ ++;; Vector versions of the floating-point frint patterns. ++;; Expands to btrunc, ceil, floor, nearbyint, rint, round. ++(define_expand "2" ++ [(set (match_operand:VDQF 0 "register_operand") ++ (unspec:VDQF [(match_operand:VDQF 1 "register_operand")] ++ FRINT))] ++ "TARGET_SIMD" ++ {}) ++ ++(define_insn "aarch64_fcvt" ++ [(set (match_operand: 0 "register_operand" "=w") ++ (FIXUORS: (unspec: ++ [(match_operand:VDQF 1 "register_operand" "w")] ++ FCVT)))] ++ "TARGET_SIMD" ++ "fcvt\\t%0., %1." ++ [(set_attr "simd_type" "simd_fcvti") ++ (set_attr "simd_mode" "")] ++) ++ ++;; Vector versions of the fcvt standard patterns. ++;; Expands to lbtrunc, lround, lceil, lfloor ++(define_expand "l2" ++ [(set (match_operand: 0 "register_operand") ++ (FIXUORS: (unspec: ++ [(match_operand:VDQF 1 "register_operand")] ++ FCVT)))] ++ "TARGET_SIMD" ++ {}) ++ +(define_insn "aarch64_vmls" + [(set (match_operand:VDQF 0 "register_operand" "=w") + (minus:VDQF (match_operand:VDQF 1 "register_operand" "0") @@ -17728,6 +20204,292 @@ + (set_attr "simd_mode" "V2SI")] +) + ++;; vbsl_* intrinsics may compile to any of bsl/bif/bit depending on register ++;; allocation. For an intrinsic of form: ++;; vD = bsl_* (vS, vN, vM) ++;; We can use any of: ++;; bsl vS, vN, vM (if D = S) ++;; bit vD, vN, vS (if D = M, so 1-bits in vS choose bits from vN, else vM) ++;; bif vD, vM, vS (if D = N, so 0-bits in vS choose bits from vM, else vN) ++ ++(define_insn "aarch64_simd_bsl_internal" ++ [(set (match_operand:VALL 0 "register_operand" "=w,w,w") ++ (unspec:VALL ++ [(match_operand: 1 "register_operand" " 0,w,w") ++ (match_operand:VALL 2 "register_operand" " w,w,0") ++ (match_operand:VALL 3 "register_operand" " w,0,w")] ++ UNSPEC_BSL))] ++ "TARGET_SIMD" ++ "@ ++ bsl\\t%0., %2., %3. ++ bit\\t%0., %2., %1. ++ bif\\t%0., %3., %1." ++) ++ ++(define_expand "aarch64_simd_bsl" ++ [(set (match_operand:VALL 0 "register_operand") ++ (unspec:VALL [(match_operand: 1 "register_operand") ++ (match_operand:VALL 2 "register_operand") ++ (match_operand:VALL 3 "register_operand")] ++ UNSPEC_BSL))] ++ "TARGET_SIMD" ++{ ++ /* We can't alias operands together if they have different modes. */ ++ operands[1] = gen_lowpart (mode, operands[1]); ++}) ++ ++(define_expand "aarch64_vcond_internal" ++ [(set (match_operand:VDQ 0 "register_operand") ++ (if_then_else:VDQ ++ (match_operator 3 "comparison_operator" ++ [(match_operand:VDQ 4 "register_operand") ++ (match_operand:VDQ 5 "nonmemory_operand")]) ++ (match_operand:VDQ 1 "register_operand") ++ (match_operand:VDQ 2 "register_operand")))] ++ "TARGET_SIMD" ++{ ++ int inverse = 0, has_zero_imm_form = 0; ++ rtx mask = gen_reg_rtx (mode); ++ ++ switch (GET_CODE (operands[3])) ++ { ++ case LE: ++ case LT: ++ case NE: ++ inverse = 1; ++ /* Fall through. */ ++ case GE: ++ case GT: ++ case EQ: ++ has_zero_imm_form = 1; ++ break; ++ case LEU: ++ case LTU: ++ inverse = 1; ++ break; ++ default: ++ break; ++ } ++ ++ if (!REG_P (operands[5]) ++ && (operands[5] != CONST0_RTX (mode) || !has_zero_imm_form)) ++ operands[5] = force_reg (mode, operands[5]); ++ ++ switch (GET_CODE (operands[3])) ++ { ++ case LT: ++ case GE: ++ emit_insn (gen_aarch64_cmge (mask, operands[4], operands[5])); ++ break; ++ ++ case LE: ++ case GT: ++ emit_insn (gen_aarch64_cmgt (mask, operands[4], operands[5])); ++ break; ++ ++ case LTU: ++ case GEU: ++ emit_insn (gen_aarch64_cmhs (mask, operands[4], operands[5])); ++ break; ++ ++ case LEU: ++ case GTU: ++ emit_insn (gen_aarch64_cmhi (mask, operands[4], operands[5])); ++ break; ++ ++ case NE: ++ case EQ: ++ emit_insn (gen_aarch64_cmeq (mask, operands[4], operands[5])); ++ break; ++ ++ default: ++ gcc_unreachable (); ++ } ++ ++ if (inverse) ++ emit_insn (gen_aarch64_simd_bsl (operands[0], mask, operands[2], ++ operands[1])); ++ else ++ emit_insn (gen_aarch64_simd_bsl (operands[0], mask, operands[1], ++ operands[2])); ++ ++ DONE; ++}) ++ ++(define_expand "aarch64_vcond_internal" ++ [(set (match_operand:VDQF 0 "register_operand") ++ (if_then_else:VDQF ++ (match_operator 3 "comparison_operator" ++ [(match_operand:VDQF 4 "register_operand") ++ (match_operand:VDQF 5 "nonmemory_operand")]) ++ (match_operand:VDQF 1 "register_operand") ++ (match_operand:VDQF 2 "register_operand")))] ++ "TARGET_SIMD" ++{ ++ int inverse = 0; ++ int swap_bsl_operands = 0; ++ rtx mask = gen_reg_rtx (mode); ++ rtx tmp = gen_reg_rtx (mode); ++ ++ rtx (*base_comparison) (rtx, rtx, rtx); ++ rtx (*complimentary_comparison) (rtx, rtx, rtx); ++ ++ switch (GET_CODE (operands[3])) ++ { ++ case GE: ++ case LE: ++ case EQ: ++ if (!REG_P (operands[5]) ++ && (operands[5] != CONST0_RTX (mode))) ++ operands[5] = force_reg (mode, operands[5]); ++ break; ++ default: ++ if (!REG_P (operands[5])) ++ operands[5] = force_reg (mode, operands[5]); ++ } ++ ++ switch (GET_CODE (operands[3])) ++ { ++ case LT: ++ case UNLT: ++ inverse = 1; ++ /* Fall through. */ ++ case GE: ++ case UNGE: ++ case ORDERED: ++ case UNORDERED: ++ base_comparison = gen_aarch64_cmge; ++ complimentary_comparison = gen_aarch64_cmgt; ++ break; ++ case LE: ++ case UNLE: ++ inverse = 1; ++ /* Fall through. */ ++ case GT: ++ case UNGT: ++ base_comparison = gen_aarch64_cmgt; ++ complimentary_comparison = gen_aarch64_cmge; ++ break; ++ case EQ: ++ case NE: ++ case UNEQ: ++ base_comparison = gen_aarch64_cmeq; ++ complimentary_comparison = gen_aarch64_cmeq; ++ break; ++ default: ++ gcc_unreachable (); ++ } ++ ++ switch (GET_CODE (operands[3])) ++ { ++ case LT: ++ case LE: ++ case GT: ++ case GE: ++ case EQ: ++ /* The easy case. Here we emit one of FCMGE, FCMGT or FCMEQ. ++ As a LT b <=> b GE a && a LE b <=> b GT a. Our transformations are: ++ a GE b -> a GE b ++ a GT b -> a GT b ++ a LE b -> b GE a ++ a LT b -> b GT a ++ a EQ b -> a EQ b */ ++ ++ if (!inverse) ++ emit_insn (base_comparison (mask, operands[4], operands[5])); ++ else ++ emit_insn (complimentary_comparison (mask, operands[5], operands[4])); ++ break; ++ case UNLT: ++ case UNLE: ++ case UNGT: ++ case UNGE: ++ case NE: ++ /* FCM returns false for lanes which are unordered, so if we use ++ the inverse of the comparison we actually want to emit, then ++ swap the operands to BSL, we will end up with the correct result. ++ Note that a NE NaN and NaN NE b are true for all a, b. ++ ++ Our transformations are: ++ a GE b -> !(b GT a) ++ a GT b -> !(b GE a) ++ a LE b -> !(a GT b) ++ a LT b -> !(a GE b) ++ a NE b -> !(a EQ b) */ ++ ++ if (inverse) ++ emit_insn (base_comparison (mask, operands[4], operands[5])); ++ else ++ emit_insn (complimentary_comparison (mask, operands[5], operands[4])); ++ ++ swap_bsl_operands = 1; ++ break; ++ case UNEQ: ++ /* We check (a > b || b > a). combining these comparisons give us ++ true iff !(a != b && a ORDERED b), swapping the operands to BSL ++ will then give us (a == b || a UNORDERED b) as intended. */ ++ ++ emit_insn (gen_aarch64_cmgt (mask, operands[4], operands[5])); ++ emit_insn (gen_aarch64_cmgt (tmp, operands[5], operands[4])); ++ emit_insn (gen_ior3 (mask, mask, tmp)); ++ swap_bsl_operands = 1; ++ break; ++ case UNORDERED: ++ /* Operands are ORDERED iff (a > b || b >= a). ++ Swapping the operands to BSL will give the UNORDERED case. */ ++ swap_bsl_operands = 1; ++ /* Fall through. */ ++ case ORDERED: ++ emit_insn (gen_aarch64_cmgt (tmp, operands[4], operands[5])); ++ emit_insn (gen_aarch64_cmge (mask, operands[5], operands[4])); ++ emit_insn (gen_ior3 (mask, mask, tmp)); ++ break; ++ default: ++ gcc_unreachable (); ++ } ++ ++ if (swap_bsl_operands) ++ emit_insn (gen_aarch64_simd_bsl (operands[0], mask, operands[2], ++ operands[1])); ++ else ++ emit_insn (gen_aarch64_simd_bsl (operands[0], mask, operands[1], ++ operands[2])); ++ DONE; ++}) ++ ++(define_expand "vcond" ++ [(set (match_operand:VALL 0 "register_operand") ++ (if_then_else:VALL ++ (match_operator 3 "comparison_operator" ++ [(match_operand:VALL 4 "register_operand") ++ (match_operand:VALL 5 "nonmemory_operand")]) ++ (match_operand:VALL 1 "register_operand") ++ (match_operand:VALL 2 "register_operand")))] ++ "TARGET_SIMD" ++{ ++ emit_insn (gen_aarch64_vcond_internal (operands[0], operands[1], ++ operands[2], operands[3], ++ operands[4], operands[5])); ++ DONE; ++}) ++ ++ ++(define_expand "vcondu" ++ [(set (match_operand:VDQ 0 "register_operand") ++ (if_then_else:VDQ ++ (match_operator 3 "comparison_operator" ++ [(match_operand:VDQ 4 "register_operand") ++ (match_operand:VDQ 5 "nonmemory_operand")]) ++ (match_operand:VDQ 1 "register_operand") ++ (match_operand:VDQ 2 "register_operand")))] ++ "TARGET_SIMD" ++{ ++ emit_insn (gen_aarch64_vcond_internal (operands[0], operands[1], ++ operands[2], operands[3], ++ operands[4], operands[5])); ++ DONE; ++}) ++ +;; Patterns for AArch64 SIMD Intrinsics. + +(define_expand "aarch64_create" @@ -18189,17 +20951,49 @@ +;; sqdmulh_lane + +(define_insn "aarch64_sqdmulh_lane" -+ [(set (match_operand:VSDQ_HSI 0 "register_operand" "=w") -+ (unspec:VSDQ_HSI -+ [(match_operand:VSDQ_HSI 1 "register_operand" "w") ++ [(set (match_operand:VDQHS 0 "register_operand" "=w") ++ (unspec:VDQHS ++ [(match_operand:VDQHS 1 "register_operand" "w") ++ (vec_select: ++ (match_operand: 2 "register_operand" "") ++ (parallel [(match_operand:SI 3 "immediate_operand" "i")]))] ++ VQDMULH))] ++ "TARGET_SIMD" ++ "* ++ aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); ++ return \"sqdmulh\\t%0., %1., %2.[%3]\";" ++ [(set_attr "simd_type" "simd_sat_mul") ++ (set_attr "simd_mode" "")] ++) ++ ++(define_insn "aarch64_sqdmulh_laneq" ++ [(set (match_operand:VDQHS 0 "register_operand" "=w") ++ (unspec:VDQHS ++ [(match_operand:VDQHS 1 "register_operand" "w") ++ (vec_select: ++ (match_operand: 2 "register_operand" "") ++ (parallel [(match_operand:SI 3 "immediate_operand" "i")]))] ++ VQDMULH))] ++ "TARGET_SIMD" ++ "* ++ aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); ++ return \"sqdmulh\\t%0., %1., %2.[%3]\";" ++ [(set_attr "simd_type" "simd_sat_mul") ++ (set_attr "simd_mode" "")] ++) ++ ++(define_insn "aarch64_sqdmulh_lane" ++ [(set (match_operand:SD_HSI 0 "register_operand" "=w") ++ (unspec:SD_HSI ++ [(match_operand:SD_HSI 1 "register_operand" "w") + (vec_select: -+ (match_operand: 2 "register_operand" "") ++ (match_operand: 2 "register_operand" "") + (parallel [(match_operand:SI 3 "immediate_operand" "i")]))] + VQDMULH))] + "TARGET_SIMD" + "* -+ aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); -+ return \"sqdmulh\\t%0, %1, %2.[%3]\";" ++ aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); ++ return \"sqdmulh\\t%0, %1, %2.[%3]\";" + [(set_attr "simd_type" "simd_sat_mul") + (set_attr "simd_mode" "")] +) @@ -18987,6 +21781,22 @@ + (set_attr "simd_mode" "")] +) + ++;; fcm(eq|ge|le|lt|gt) ++ ++(define_insn "aarch64_cm" ++ [(set (match_operand: 0 "register_operand" "=w,w") ++ (unspec: ++ [(match_operand:VDQF 1 "register_operand" "w,w") ++ (match_operand:VDQF 2 "aarch64_simd_reg_or_zero" "w,Dz")] ++ VCMP_S))] ++ "TARGET_SIMD" ++ "@ ++ fcm\t%0, %1, %2 ++ fcm\t%0, %1, 0" ++ [(set_attr "simd_type" "simd_fcmp") ++ (set_attr "simd_mode" "")] ++) ++ +;; addp + +(define_insn "aarch64_addp" @@ -19415,6 +22225,85 @@ + +;; Permuted-store expanders for neon intrinsics. + ++;; Permute instructions ++ ++;; vec_perm support ++ ++(define_expand "vec_perm_const" ++ [(match_operand:VALL 0 "register_operand") ++ (match_operand:VALL 1 "register_operand") ++ (match_operand:VALL 2 "register_operand") ++ (match_operand: 3)] ++ "TARGET_SIMD" ++{ ++ if (aarch64_expand_vec_perm_const (operands[0], operands[1], ++ operands[2], operands[3])) ++ DONE; ++ else ++ FAIL; ++}) ++ ++(define_expand "vec_perm" ++ [(match_operand:VB 0 "register_operand") ++ (match_operand:VB 1 "register_operand") ++ (match_operand:VB 2 "register_operand") ++ (match_operand:VB 3 "register_operand")] ++ "TARGET_SIMD" ++{ ++ aarch64_expand_vec_perm (operands[0], operands[1], ++ operands[2], operands[3]); ++ DONE; ++}) ++ ++(define_insn "aarch64_tbl1" ++ [(set (match_operand:VB 0 "register_operand" "=w") ++ (unspec:VB [(match_operand:V16QI 1 "register_operand" "w") ++ (match_operand:VB 2 "register_operand" "w")] ++ UNSPEC_TBL))] ++ "TARGET_SIMD" ++ "tbl\\t%0., {%1.16b}, %2." ++ [(set_attr "simd_type" "simd_tbl") ++ (set_attr "simd_mode" "")] ++) ++ ++;; Two source registers. ++ ++(define_insn "aarch64_tbl2v16qi" ++ [(set (match_operand:V16QI 0 "register_operand" "=w") ++ (unspec:V16QI [(match_operand:OI 1 "register_operand" "w") ++ (match_operand:V16QI 2 "register_operand" "w")] ++ UNSPEC_TBL))] ++ "TARGET_SIMD" ++ "tbl\\t%0.16b, {%S1.16b - %T1.16b}, %2.16b" ++ [(set_attr "simd_type" "simd_tbl") ++ (set_attr "simd_mode" "V16QI")] ++) ++ ++(define_insn_and_split "aarch64_combinev16qi" ++ [(set (match_operand:OI 0 "register_operand" "=w") ++ (unspec:OI [(match_operand:V16QI 1 "register_operand" "w") ++ (match_operand:V16QI 2 "register_operand" "w")] ++ UNSPEC_CONCAT))] ++ "TARGET_SIMD" ++ "#" ++ "&& reload_completed" ++ [(const_int 0)] ++{ ++ aarch64_split_combinev16qi (operands); ++ DONE; ++}) ++ ++(define_insn "aarch64_" ++ [(set (match_operand:VALL 0 "register_operand" "=w") ++ (unspec:VALL [(match_operand:VALL 1 "register_operand" "w") ++ (match_operand:VALL 2 "register_operand" "w")] ++ PERMUTE))] ++ "TARGET_SIMD" ++ "\\t%0., %1., %2." ++ [(set_attr "simd_type" "simd_") ++ (set_attr "simd_mode" "")] ++) ++ +(define_insn "aarch64_st2_dreg" + [(set (match_operand:TI 0 "aarch64_simd_struct_operand" "=Utv") + (unspec:TI [(match_operand:OI 1 "register_operand" "w") @@ -19523,20 +22412,39 @@ + DONE; +}) + ---- a/src/gcc/config/aarch64/aarch64-tune.md -+++ b/src/gcc/config/aarch64/aarch64-tune.md -@@ -0,0 +1,5 @@ -+;; -*- buffer-read-only: t -*- -+;; Generated automatically by gentune.sh from aarch64-cores.def ++;; Standard pattern name vec_init. ++ ++(define_expand "vec_init" ++ [(match_operand:VALL 0 "register_operand" "") ++ (match_operand 1 "" "")] ++ "TARGET_SIMD" ++{ ++ aarch64_expand_vector_init (operands[0], operands[1]); ++ DONE; ++}) ++ ++(define_insn "*aarch64_simd_ld1r" ++ [(set (match_operand:VALLDI 0 "register_operand" "=w") ++ (vec_duplicate:VALLDI ++ (match_operand: 1 "aarch64_simd_struct_operand" "Utv")))] ++ "TARGET_SIMD" ++ "ld1r\\t{%0.}, %1" ++ [(set_attr "simd_type" "simd_load1r") ++ (set_attr "simd_mode" "")]) +--- a/src/gcc/config/aarch64/aarch64-tune.md ++++ b/src/gcc/config/aarch64/aarch64-tune.md +@@ -0,0 +1,5 @@ ++;; -*- buffer-read-only: t -*- ++;; Generated automatically by gentune.sh from aarch64-cores.def +(define_attr "tune" + "large,small" + (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) --- a/src/gcc/config/aarch64/arm_neon.h +++ b/src/gcc/config/aarch64/arm_neon.h -@@ -0,0 +1,25543 @@ +@@ -0,0 +1,25535 @@ +/* ARM NEON intrinsics include file. + -+ Copyright (C) 2011, 2012 Free Software Foundation, Inc. ++ Copyright (C) 2011-2013 Free Software Foundation, Inc. + Contributed by ARM Ltd. + + This file is part of GCC. @@ -19571,11 +22479,11 @@ + __attribute__ ((__vector_size__ (8))); +typedef __builtin_aarch64_simd_si int32x2_t + __attribute__ ((__vector_size__ (8))); -+typedef __builtin_aarch64_simd_di int64x1_t; -+typedef __builtin_aarch64_simd_si int32x1_t; -+typedef __builtin_aarch64_simd_hi int16x1_t; -+typedef __builtin_aarch64_simd_qi int8x1_t; -+typedef __builtin_aarch64_simd_df float64x1_t; ++typedef int64_t int64x1_t; ++typedef int32_t int32x1_t; ++typedef int16_t int16x1_t; ++typedef int8_t int8x1_t; ++typedef double float64x1_t; +typedef __builtin_aarch64_simd_sf float32x2_t + __attribute__ ((__vector_size__ (8))); +typedef __builtin_aarch64_simd_poly8 poly8x8_t @@ -19588,10 +22496,10 @@ + __attribute__ ((__vector_size__ (8))); +typedef __builtin_aarch64_simd_usi uint32x2_t + __attribute__ ((__vector_size__ (8))); -+typedef __builtin_aarch64_simd_udi uint64x1_t; -+typedef __builtin_aarch64_simd_usi uint32x1_t; -+typedef __builtin_aarch64_simd_uhi uint16x1_t; -+typedef __builtin_aarch64_simd_uqi uint8x1_t; ++typedef uint64_t uint64x1_t; ++typedef uint32_t uint32x1_t; ++typedef uint16_t uint16x1_t; ++typedef uint8_t uint8x1_t; +typedef __builtin_aarch64_simd_qi int8x16_t + __attribute__ ((__vector_size__ (16))); +typedef __builtin_aarch64_simd_hi int16x8_t @@ -27923,7 +30831,7 @@ +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vld1_dup_f32 (float32_t * a) ++vld1_dup_f32 (const float32_t * a) +{ + float32x2_t result; + __asm__ ("ld1r {%0.2s},[%1]" @@ -27934,7 +30842,7 @@ +} + +__extension__ static __inline float64x1_t __attribute__ ((__always_inline__)) -+vld1_dup_f64 (float64_t * a) ++vld1_dup_f64 (const float64_t * a) +{ + float64x1_t result; + __asm__ ("ld1 {%0.1d},[%1]" @@ -27945,7 +30853,7 @@ +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vld1_dup_p8 (poly8_t * a) ++vld1_dup_p8 (const poly8_t * a) +{ + poly8x8_t result; + __asm__ ("ld1r {%0.8b},[%1]" @@ -27956,7 +30864,7 @@ +} + +__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) -+vld1_dup_p16 (poly16_t * a) ++vld1_dup_p16 (const poly16_t * a) +{ + poly16x4_t result; + __asm__ ("ld1r {%0.4h},[%1]" @@ -27967,7 +30875,7 @@ +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vld1_dup_s8 (int8_t * a) ++vld1_dup_s8 (const int8_t * a) +{ + int8x8_t result; + __asm__ ("ld1r {%0.8b},[%1]" @@ -27978,7 +30886,7 @@ +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vld1_dup_s16 (int16_t * a) ++vld1_dup_s16 (const int16_t * a) +{ + int16x4_t result; + __asm__ ("ld1r {%0.4h},[%1]" @@ -27989,7 +30897,7 @@ +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vld1_dup_s32 (int32_t * a) ++vld1_dup_s32 (const int32_t * a) +{ + int32x2_t result; + __asm__ ("ld1r {%0.2s},[%1]" @@ -28000,7 +30908,7 @@ +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vld1_dup_s64 (int64_t * a) ++vld1_dup_s64 (const int64_t * a) +{ + int64x1_t result; + __asm__ ("ld1 {%0.1d},[%1]" @@ -28011,7 +30919,7 @@ +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vld1_dup_u8 (uint8_t * a) ++vld1_dup_u8 (const uint8_t * a) +{ + uint8x8_t result; + __asm__ ("ld1r {%0.8b},[%1]" @@ -28022,7 +30930,7 @@ +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vld1_dup_u16 (uint16_t * a) ++vld1_dup_u16 (const uint16_t * a) +{ + uint16x4_t result; + __asm__ ("ld1r {%0.4h},[%1]" @@ -28033,7 +30941,7 @@ +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vld1_dup_u32 (uint32_t * a) ++vld1_dup_u32 (const uint32_t * a) +{ + uint32x2_t result; + __asm__ ("ld1r {%0.2s},[%1]" @@ -28044,7 +30952,7 @@ +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vld1_dup_u64 (uint64_t * a) ++vld1_dup_u64 (const uint64_t * a) +{ + uint64x1_t result; + __asm__ ("ld1 {%0.1d},[%1]" @@ -28055,7 +30963,7 @@ +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vld1_f32 (float32_t * a) ++vld1_f32 (const float32_t * a) +{ + float32x2_t result; + __asm__ ("ld1 {%0.2s},[%1]" @@ -28066,7 +30974,7 @@ +} + +__extension__ static __inline float64x1_t __attribute__ ((__always_inline__)) -+vld1_f64 (float64_t * a) ++vld1_f64 (const float64_t * a) +{ + float64x1_t result; + __asm__ ("ld1 {%0.1d},[%1]" @@ -28080,7 +30988,7 @@ + __extension__ \ + ({ \ + float32x2_t b_ = (b); \ -+ float32_t * a_ = (a); \ ++ const float32_t * a_ = (a); \ + float32x2_t result; \ + __asm__ ("ld1 {%0.s}[%3],[%1]" \ + : "=w"(result) \ @@ -28093,7 +31001,7 @@ + __extension__ \ + ({ \ + float64x1_t b_ = (b); \ -+ float64_t * a_ = (a); \ ++ const float64_t * a_ = (a); \ + float64x1_t result; \ + __asm__ ("ld1 {%0.d}[%3],[%1]" \ + : "=w"(result) \ @@ -28106,7 +31014,7 @@ + __extension__ \ + ({ \ + poly8x8_t b_ = (b); \ -+ poly8_t * a_ = (a); \ ++ const poly8_t * a_ = (a); \ + poly8x8_t result; \ + __asm__ ("ld1 {%0.b}[%3],[%1]" \ + : "=w"(result) \ @@ -28119,7 +31027,7 @@ + __extension__ \ + ({ \ + poly16x4_t b_ = (b); \ -+ poly16_t * a_ = (a); \ ++ const poly16_t * a_ = (a); \ + poly16x4_t result; \ + __asm__ ("ld1 {%0.h}[%3],[%1]" \ + : "=w"(result) \ @@ -28132,7 +31040,7 @@ + __extension__ \ + ({ \ + int8x8_t b_ = (b); \ -+ int8_t * a_ = (a); \ ++ const int8_t * a_ = (a); \ + int8x8_t result; \ + __asm__ ("ld1 {%0.b}[%3],[%1]" \ + : "=w"(result) \ @@ -28145,7 +31053,7 @@ + __extension__ \ + ({ \ + int16x4_t b_ = (b); \ -+ int16_t * a_ = (a); \ ++ const int16_t * a_ = (a); \ + int16x4_t result; \ + __asm__ ("ld1 {%0.h}[%3],[%1]" \ + : "=w"(result) \ @@ -28158,7 +31066,7 @@ + __extension__ \ + ({ \ + int32x2_t b_ = (b); \ -+ int32_t * a_ = (a); \ ++ const int32_t * a_ = (a); \ + int32x2_t result; \ + __asm__ ("ld1 {%0.s}[%3],[%1]" \ + : "=w"(result) \ @@ -28171,7 +31079,7 @@ + __extension__ \ + ({ \ + int64x1_t b_ = (b); \ -+ int64_t * a_ = (a); \ ++ const int64_t * a_ = (a); \ + int64x1_t result; \ + __asm__ ("ld1 {%0.d}[%3],[%1]" \ + : "=w"(result) \ @@ -28184,7 +31092,7 @@ + __extension__ \ + ({ \ + uint8x8_t b_ = (b); \ -+ uint8_t * a_ = (a); \ ++ const uint8_t * a_ = (a); \ + uint8x8_t result; \ + __asm__ ("ld1 {%0.b}[%3],[%1]" \ + : "=w"(result) \ @@ -28197,7 +31105,7 @@ + __extension__ \ + ({ \ + uint16x4_t b_ = (b); \ -+ uint16_t * a_ = (a); \ ++ const uint16_t * a_ = (a); \ + uint16x4_t result; \ + __asm__ ("ld1 {%0.h}[%3],[%1]" \ + : "=w"(result) \ @@ -28210,7 +31118,7 @@ + __extension__ \ + ({ \ + uint32x2_t b_ = (b); \ -+ uint32_t * a_ = (a); \ ++ const uint32_t * a_ = (a); \ + uint32x2_t result; \ + __asm__ ("ld1 {%0.s}[%3],[%1]" \ + : "=w"(result) \ @@ -28223,7 +31131,7 @@ + __extension__ \ + ({ \ + uint64x1_t b_ = (b); \ -+ uint64_t * a_ = (a); \ ++ const uint64_t * a_ = (a); \ + uint64x1_t result; \ + __asm__ ("ld1 {%0.d}[%3],[%1]" \ + : "=w"(result) \ @@ -28233,7 +31141,7 @@ + }) + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vld1_p8 (poly8_t * a) ++vld1_p8 (const poly8_t * a) +{ + poly8x8_t result; + __asm__ ("ld1 {%0.8b}, [%1]" @@ -28244,7 +31152,7 @@ +} + +__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) -+vld1_p16 (poly16_t * a) ++vld1_p16 (const poly16_t * a) +{ + poly16x4_t result; + __asm__ ("ld1 {%0.4h}, [%1]" @@ -28255,7 +31163,7 @@ +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vld1_s8 (int8_t * a) ++vld1_s8 (const int8_t * a) +{ + int8x8_t result; + __asm__ ("ld1 {%0.8b},[%1]" @@ -28266,7 +31174,7 @@ +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vld1_s16 (int16_t * a) ++vld1_s16 (const int16_t * a) +{ + int16x4_t result; + __asm__ ("ld1 {%0.4h},[%1]" @@ -28277,7 +31185,7 @@ +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vld1_s32 (int32_t * a) ++vld1_s32 (const int32_t * a) +{ + int32x2_t result; + __asm__ ("ld1 {%0.2s},[%1]" @@ -28288,7 +31196,7 @@ +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vld1_s64 (int64_t * a) ++vld1_s64 (const int64_t * a) +{ + int64x1_t result; + __asm__ ("ld1 {%0.1d},[%1]" @@ -28299,7 +31207,7 @@ +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vld1_u8 (uint8_t * a) ++vld1_u8 (const uint8_t * a) +{ + uint8x8_t result; + __asm__ ("ld1 {%0.8b},[%1]" @@ -28310,7 +31218,7 @@ +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vld1_u16 (uint16_t * a) ++vld1_u16 (const uint16_t * a) +{ + uint16x4_t result; + __asm__ ("ld1 {%0.4h},[%1]" @@ -28321,7 +31229,7 @@ +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vld1_u32 (uint32_t * a) ++vld1_u32 (const uint32_t * a) +{ + uint32x2_t result; + __asm__ ("ld1 {%0.2s},[%1]" @@ -28332,7 +31240,7 @@ +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vld1_u64 (uint64_t * a) ++vld1_u64 (const uint64_t * a) +{ + uint64x1_t result; + __asm__ ("ld1 {%0.1d},[%1]" @@ -28343,7 +31251,7 @@ +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vld1q_dup_f32 (float32_t * a) ++vld1q_dup_f32 (const float32_t * a) +{ + float32x4_t result; + __asm__ ("ld1r {%0.4s},[%1]" @@ -28354,7 +31262,7 @@ +} + +__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vld1q_dup_f64 (float64_t * a) ++vld1q_dup_f64 (const float64_t * a) +{ + float64x2_t result; + __asm__ ("ld1r {%0.2d},[%1]" @@ -28365,7 +31273,7 @@ +} + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vld1q_dup_p8 (poly8_t * a) ++vld1q_dup_p8 (const poly8_t * a) +{ + poly8x16_t result; + __asm__ ("ld1r {%0.16b},[%1]" @@ -28376,7 +31284,7 @@ +} + +__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) -+vld1q_dup_p16 (poly16_t * a) ++vld1q_dup_p16 (const poly16_t * a) +{ + poly16x8_t result; + __asm__ ("ld1r {%0.8h},[%1]" @@ -28387,7 +31295,7 @@ +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vld1q_dup_s8 (int8_t * a) ++vld1q_dup_s8 (const int8_t * a) +{ + int8x16_t result; + __asm__ ("ld1r {%0.16b},[%1]" @@ -28398,7 +31306,7 @@ +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vld1q_dup_s16 (int16_t * a) ++vld1q_dup_s16 (const int16_t * a) +{ + int16x8_t result; + __asm__ ("ld1r {%0.8h},[%1]" @@ -28409,7 +31317,7 @@ +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vld1q_dup_s32 (int32_t * a) ++vld1q_dup_s32 (const int32_t * a) +{ + int32x4_t result; + __asm__ ("ld1r {%0.4s},[%1]" @@ -28420,7 +31328,7 @@ +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vld1q_dup_s64 (int64_t * a) ++vld1q_dup_s64 (const int64_t * a) +{ + int64x2_t result; + __asm__ ("ld1r {%0.2d},[%1]" @@ -28431,7 +31339,7 @@ +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vld1q_dup_u8 (uint8_t * a) ++vld1q_dup_u8 (const uint8_t * a) +{ + uint8x16_t result; + __asm__ ("ld1r {%0.16b},[%1]" @@ -28442,7 +31350,7 @@ +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vld1q_dup_u16 (uint16_t * a) ++vld1q_dup_u16 (const uint16_t * a) +{ + uint16x8_t result; + __asm__ ("ld1r {%0.8h},[%1]" @@ -28453,7 +31361,7 @@ +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vld1q_dup_u32 (uint32_t * a) ++vld1q_dup_u32 (const uint32_t * a) +{ + uint32x4_t result; + __asm__ ("ld1r {%0.4s},[%1]" @@ -28464,7 +31372,7 @@ +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vld1q_dup_u64 (uint64_t * a) ++vld1q_dup_u64 (const uint64_t * a) +{ + uint64x2_t result; + __asm__ ("ld1r {%0.2d},[%1]" @@ -28475,7 +31383,7 @@ +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vld1q_f32 (float32_t * a) ++vld1q_f32 (const float32_t * a) +{ + float32x4_t result; + __asm__ ("ld1 {%0.4s},[%1]" @@ -28486,7 +31394,7 @@ +} + +__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vld1q_f64 (float64_t * a) ++vld1q_f64 (const float64_t * a) +{ + float64x2_t result; + __asm__ ("ld1 {%0.2d},[%1]" @@ -28500,7 +31408,7 @@ + __extension__ \ + ({ \ + float32x4_t b_ = (b); \ -+ float32_t * a_ = (a); \ ++ const float32_t * a_ = (a); \ + float32x4_t result; \ + __asm__ ("ld1 {%0.s}[%3],[%1]" \ + : "=w"(result) \ @@ -28513,7 +31421,7 @@ + __extension__ \ + ({ \ + float64x2_t b_ = (b); \ -+ float64_t * a_ = (a); \ ++ const float64_t * a_ = (a); \ + float64x2_t result; \ + __asm__ ("ld1 {%0.d}[%3],[%1]" \ + : "=w"(result) \ @@ -28526,7 +31434,7 @@ + __extension__ \ + ({ \ + poly8x16_t b_ = (b); \ -+ poly8_t * a_ = (a); \ ++ const poly8_t * a_ = (a); \ + poly8x16_t result; \ + __asm__ ("ld1 {%0.b}[%3],[%1]" \ + : "=w"(result) \ @@ -28539,7 +31447,7 @@ + __extension__ \ + ({ \ + poly16x8_t b_ = (b); \ -+ poly16_t * a_ = (a); \ ++ const poly16_t * a_ = (a); \ + poly16x8_t result; \ + __asm__ ("ld1 {%0.h}[%3],[%1]" \ + : "=w"(result) \ @@ -28552,7 +31460,7 @@ + __extension__ \ + ({ \ + int8x16_t b_ = (b); \ -+ int8_t * a_ = (a); \ ++ const int8_t * a_ = (a); \ + int8x16_t result; \ + __asm__ ("ld1 {%0.b}[%3],[%1]" \ + : "=w"(result) \ @@ -28565,7 +31473,7 @@ + __extension__ \ + ({ \ + int16x8_t b_ = (b); \ -+ int16_t * a_ = (a); \ ++ const int16_t * a_ = (a); \ + int16x8_t result; \ + __asm__ ("ld1 {%0.h}[%3],[%1]" \ + : "=w"(result) \ @@ -28578,7 +31486,7 @@ + __extension__ \ + ({ \ + int32x4_t b_ = (b); \ -+ int32_t * a_ = (a); \ ++ const int32_t * a_ = (a); \ + int32x4_t result; \ + __asm__ ("ld1 {%0.s}[%3],[%1]" \ + : "=w"(result) \ @@ -28591,7 +31499,7 @@ + __extension__ \ + ({ \ + int64x2_t b_ = (b); \ -+ int64_t * a_ = (a); \ ++ const int64_t * a_ = (a); \ + int64x2_t result; \ + __asm__ ("ld1 {%0.d}[%3],[%1]" \ + : "=w"(result) \ @@ -28604,7 +31512,7 @@ + __extension__ \ + ({ \ + uint8x16_t b_ = (b); \ -+ uint8_t * a_ = (a); \ ++ const uint8_t * a_ = (a); \ + uint8x16_t result; \ + __asm__ ("ld1 {%0.b}[%3],[%1]" \ + : "=w"(result) \ @@ -28617,7 +31525,7 @@ + __extension__ \ + ({ \ + uint16x8_t b_ = (b); \ -+ uint16_t * a_ = (a); \ ++ const uint16_t * a_ = (a); \ + uint16x8_t result; \ + __asm__ ("ld1 {%0.h}[%3],[%1]" \ + : "=w"(result) \ @@ -28630,7 +31538,7 @@ + __extension__ \ + ({ \ + uint32x4_t b_ = (b); \ -+ uint32_t * a_ = (a); \ ++ const uint32_t * a_ = (a); \ + uint32x4_t result; \ + __asm__ ("ld1 {%0.s}[%3],[%1]" \ + : "=w"(result) \ @@ -28643,7 +31551,7 @@ + __extension__ \ + ({ \ + uint64x2_t b_ = (b); \ -+ uint64_t * a_ = (a); \ ++ const uint64_t * a_ = (a); \ + uint64x2_t result; \ + __asm__ ("ld1 {%0.d}[%3],[%1]" \ + : "=w"(result) \ @@ -28653,7 +31561,7 @@ + }) + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vld1q_p8 (poly8_t * a) ++vld1q_p8 (const poly8_t * a) +{ + poly8x16_t result; + __asm__ ("ld1 {%0.16b},[%1]" @@ -28664,7 +31572,7 @@ +} + +__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) -+vld1q_p16 (poly16_t * a) ++vld1q_p16 (const poly16_t * a) +{ + poly16x8_t result; + __asm__ ("ld1 {%0.8h},[%1]" @@ -28675,7 +31583,7 @@ +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vld1q_s8 (int8_t * a) ++vld1q_s8 (const int8_t * a) +{ + int8x16_t result; + __asm__ ("ld1 {%0.16b},[%1]" @@ -28686,7 +31594,7 @@ +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vld1q_s16 (int16_t * a) ++vld1q_s16 (const int16_t * a) +{ + int16x8_t result; + __asm__ ("ld1 {%0.8h},[%1]" @@ -28697,7 +31605,7 @@ +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vld1q_s32 (int32_t * a) ++vld1q_s32 (const int32_t * a) +{ + int32x4_t result; + __asm__ ("ld1 {%0.4s},[%1]" @@ -28708,7 +31616,7 @@ +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vld1q_s64 (int64_t * a) ++vld1q_s64 (const int64_t * a) +{ + int64x2_t result; + __asm__ ("ld1 {%0.2d},[%1]" @@ -28719,7 +31627,7 @@ +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vld1q_u8 (uint8_t * a) ++vld1q_u8 (const uint8_t * a) +{ + uint8x16_t result; + __asm__ ("ld1 {%0.16b},[%1]" @@ -28730,7 +31638,7 @@ +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vld1q_u16 (uint16_t * a) ++vld1q_u16 (const uint16_t * a) +{ + uint16x8_t result; + __asm__ ("ld1 {%0.8h},[%1]" @@ -28741,7 +31649,7 @@ +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vld1q_u32 (uint32_t * a) ++vld1q_u32 (const uint32_t * a) +{ + uint32x4_t result; + __asm__ ("ld1 {%0.4s},[%1]" @@ -28752,7 +31660,7 @@ +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vld1q_u64 (uint64_t * a) ++vld1q_u64 (const uint64_t * a) +{ + uint64x2_t result; + __asm__ ("ld1 {%0.2d},[%1]" @@ -31183,7 +34091,7 @@ +vmovn_high_s16 (int8x8_t a, int16x8_t b) +{ + int8x16_t result = vcombine_s8 (a, vcreate_s8 (UINT64_C (0x0))); -+ __asm__ ("xtn2 %0.16b,%2.8h" ++ __asm__ ("xtn2 %0.16b,%1.8h" + : "+w"(result) + : "w"(b) + : /* No clobbers */); @@ -31194,7 +34102,7 @@ +vmovn_high_s32 (int16x4_t a, int32x4_t b) +{ + int16x8_t result = vcombine_s16 (a, vcreate_s16 (UINT64_C (0x0))); -+ __asm__ ("xtn2 %0.8h,%2.4s" ++ __asm__ ("xtn2 %0.8h,%1.4s" + : "+w"(result) + : "w"(b) + : /* No clobbers */); @@ -31205,7 +34113,7 @@ +vmovn_high_s64 (int32x2_t a, int64x2_t b) +{ + int32x4_t result = vcombine_s32 (a, vcreate_s32 (UINT64_C (0x0))); -+ __asm__ ("xtn2 %0.4s,%2.2d" ++ __asm__ ("xtn2 %0.4s,%1.2d" + : "+w"(result) + : "w"(b) + : /* No clobbers */); @@ -31216,7 +34124,7 @@ +vmovn_high_u16 (uint8x8_t a, uint16x8_t b) +{ + uint8x16_t result = vcombine_u8 (a, vcreate_u8 (UINT64_C (0x0))); -+ __asm__ ("xtn2 %0.16b,%2.8h" ++ __asm__ ("xtn2 %0.16b,%1.8h" + : "+w"(result) + : "w"(b) + : /* No clobbers */); @@ -31227,7 +34135,7 @@ +vmovn_high_u32 (uint16x4_t a, uint32x4_t b) +{ + uint16x8_t result = vcombine_u16 (a, vcreate_u16 (UINT64_C (0x0))); -+ __asm__ ("xtn2 %0.8h,%2.4s" ++ __asm__ ("xtn2 %0.8h,%1.4s" + : "+w"(result) + : "w"(b) + : /* No clobbers */); @@ -31238,7 +34146,7 @@ +vmovn_high_u64 (uint32x2_t a, uint64x2_t b) +{ + uint32x4_t result = vcombine_u32 (a, vcreate_u32 (UINT64_C (0x0))); -+ __asm__ ("xtn2 %0.4s,%2.2d" ++ __asm__ ("xtn2 %0.4s,%1.2d" + : "+w"(result) + : "w"(b) + : /* No clobbers */); @@ -33657,7 +36565,7 @@ +vqmovn_high_s16 (int8x8_t a, int16x8_t b) +{ + int8x16_t result = vcombine_s8 (a, vcreate_s8 (UINT64_C (0x0))); -+ __asm__ ("sqxtn2 %0.16b, %2.8h" ++ __asm__ ("sqxtn2 %0.16b, %1.8h" + : "+w"(result) + : "w"(b) + : /* No clobbers */); @@ -33668,7 +36576,7 @@ +vqmovn_high_s32 (int16x4_t a, int32x4_t b) +{ + int16x8_t result = vcombine_s16 (a, vcreate_s16 (UINT64_C (0x0))); -+ __asm__ ("sqxtn2 %0.8h, %2.4s" ++ __asm__ ("sqxtn2 %0.8h, %1.4s" + : "+w"(result) + : "w"(b) + : /* No clobbers */); @@ -33679,7 +36587,7 @@ +vqmovn_high_s64 (int32x2_t a, int64x2_t b) +{ + int32x4_t result = vcombine_s32 (a, vcreate_s32 (UINT64_C (0x0))); -+ __asm__ ("sqxtn2 %0.4s, %2.2d" ++ __asm__ ("sqxtn2 %0.4s, %1.2d" + : "+w"(result) + : "w"(b) + : /* No clobbers */); @@ -33690,7 +36598,7 @@ +vqmovn_high_u16 (uint8x8_t a, uint16x8_t b) +{ + uint8x16_t result = vcombine_u8 (a, vcreate_u8 (UINT64_C (0x0))); -+ __asm__ ("uqxtn2 %0.16b, %2.8h" ++ __asm__ ("uqxtn2 %0.16b, %1.8h" + : "+w"(result) + : "w"(b) + : /* No clobbers */); @@ -33701,7 +36609,7 @@ +vqmovn_high_u32 (uint16x4_t a, uint32x4_t b) +{ + uint16x8_t result = vcombine_u16 (a, vcreate_u16 (UINT64_C (0x0))); -+ __asm__ ("uqxtn2 %0.8h, %2.4s" ++ __asm__ ("uqxtn2 %0.8h, %1.4s" + : "+w"(result) + : "w"(b) + : /* No clobbers */); @@ -33712,7 +36620,7 @@ +vqmovn_high_u64 (uint32x2_t a, uint64x2_t b) +{ + uint32x4_t result = vcombine_u32 (a, vcreate_u32 (UINT64_C (0x0))); -+ __asm__ ("uqxtn2 %0.4s, %2.2d" ++ __asm__ ("uqxtn2 %0.4s, %1.2d" + : "+w"(result) + : "w"(b) + : /* No clobbers */); @@ -33723,7 +36631,7 @@ +vqmovun_high_s16 (uint8x8_t a, int16x8_t b) +{ + uint8x16_t result = vcombine_u8 (a, vcreate_u8 (UINT64_C (0x0))); -+ __asm__ ("sqxtun2 %0.16b, %2.8h" ++ __asm__ ("sqxtun2 %0.16b, %1.8h" + : "+w"(result) + : "w"(b) + : /* No clobbers */); @@ -33734,7 +36642,7 @@ +vqmovun_high_s32 (uint16x4_t a, int32x4_t b) +{ + uint16x8_t result = vcombine_u16 (a, vcreate_u16 (UINT64_C (0x0))); -+ __asm__ ("sqxtun2 %0.8h, %2.4s" ++ __asm__ ("sqxtun2 %0.8h, %1.4s" + : "+w"(result) + : "w"(b) + : /* No clobbers */); @@ -33745,7 +36653,7 @@ +vqmovun_high_s64 (uint32x2_t a, int64x2_t b) +{ + uint32x4_t result = vcombine_u32 (a, vcreate_u32 (UINT64_C (0x0))); -+ __asm__ ("sqxtun2 %0.4s, %2.2d" ++ __asm__ ("sqxtun2 %0.4s, %1.2d" + : "+w"(result) + : "w"(b) + : /* No clobbers */); @@ -38413,49 +41321,49 @@ +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vqdmulh_laneq_s16 (int16x4_t __a, int16x8_t __b, const int __c) +{ -+ return __builtin_aarch64_sqdmulh_lanev4hi (__a, __b, __c); ++ return __builtin_aarch64_sqdmulh_laneqv4hi (__a, __b, __c); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vqdmulh_laneq_s32 (int32x2_t __a, int32x4_t __b, const int __c) +{ -+ return __builtin_aarch64_sqdmulh_lanev2si (__a, __b, __c); ++ return __builtin_aarch64_sqdmulh_laneqv2si (__a, __b, __c); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vqdmulhq_laneq_s16 (int16x8_t __a, int16x8_t __b, const int __c) +{ -+ return __builtin_aarch64_sqdmulh_lanev8hi (__a, __b, __c); ++ return __builtin_aarch64_sqdmulh_laneqv8hi (__a, __b, __c); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vqdmulhq_laneq_s32 (int32x4_t __a, int32x4_t __b, const int __c) +{ -+ return __builtin_aarch64_sqdmulh_lanev4si (__a, __b, __c); ++ return __builtin_aarch64_sqdmulh_laneqv4si (__a, __b, __c); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vqrdmulh_laneq_s16 (int16x4_t __a, int16x8_t __b, const int __c) +{ -+ return __builtin_aarch64_sqrdmulh_lanev4hi (__a, __b, __c); ++ return __builtin_aarch64_sqrdmulh_laneqv4hi (__a, __b, __c); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vqrdmulh_laneq_s32 (int32x2_t __a, int32x4_t __b, const int __c) +{ -+ return __builtin_aarch64_sqrdmulh_lanev2si (__a, __b, __c); ++ return __builtin_aarch64_sqrdmulh_laneqv2si (__a, __b, __c); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vqrdmulhq_laneq_s16 (int16x8_t __a, int16x8_t __b, const int __c) +{ -+ return __builtin_aarch64_sqrdmulh_lanev8hi (__a, __b, __c); ++ return __builtin_aarch64_sqrdmulh_laneqv8hi (__a, __b, __c); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vqrdmulhq_laneq_s32 (int32x4_t __a, int32x4_t __b, const int __c) +{ -+ return __builtin_aarch64_sqrdmulh_lanev4si (__a, __b, __c); ++ return __builtin_aarch64_sqrdmulh_laneqv4si (__a, __b, __c); +} + +/* Table intrinsics. */ @@ -41510,29 +44418,25 @@ +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vqdmulh_lane_s16 (int16x4_t __a, int16x4_t __b, const int __c) +{ -+ int16x8_t __tmp = vcombine_s16 (__b, vcreate_s16 (INT64_C (0))); -+ return __builtin_aarch64_sqdmulh_lanev4hi (__a, __tmp, __c); ++ return __builtin_aarch64_sqdmulh_lanev4hi (__a, __b, __c); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vqdmulh_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c) +{ -+ int32x4_t __tmp = vcombine_s32 (__b, vcreate_s32 (INT64_C (0))); -+ return __builtin_aarch64_sqdmulh_lanev2si (__a, __tmp, __c); ++ return __builtin_aarch64_sqdmulh_lanev2si (__a, __b, __c); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vqdmulhq_lane_s16 (int16x8_t __a, int16x4_t __b, const int __c) +{ -+ int16x8_t __tmp = vcombine_s16 (__b, vcreate_s16 (INT64_C (0))); -+ return __builtin_aarch64_sqdmulh_lanev8hi (__a, __tmp, __c); ++ return __builtin_aarch64_sqdmulh_lanev8hi (__a, __b, __c); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vqdmulhq_lane_s32 (int32x4_t __a, int32x2_t __b, const int __c) +{ -+ int32x4_t __tmp = vcombine_s32 (__b, vcreate_s32 (INT64_C (0))); -+ return __builtin_aarch64_sqdmulh_lanev4si (__a, __tmp, __c); ++ return __builtin_aarch64_sqdmulh_lanev4si (__a, __b, __c); +} + +__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) @@ -41826,29 +44730,25 @@ +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vqrdmulh_lane_s16 (int16x4_t __a, int16x4_t __b, const int __c) +{ -+ int16x8_t __tmp = vcombine_s16 (__b, vcreate_s16 (INT64_C (0))); -+ return __builtin_aarch64_sqrdmulh_lanev4hi (__a, __tmp, __c); ++ return __builtin_aarch64_sqrdmulh_lanev4hi (__a, __b, __c); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vqrdmulh_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c) +{ -+ int32x4_t __tmp = vcombine_s32 (__b, vcreate_s32 (INT64_C (0))); -+ return __builtin_aarch64_sqrdmulh_lanev2si (__a, __tmp, __c); ++ return __builtin_aarch64_sqrdmulh_lanev2si (__a, __b, __c); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vqrdmulhq_lane_s16 (int16x8_t __a, int16x4_t __b, const int __c) +{ -+ int16x8_t __tmp = vcombine_s16 (__b, vcreate_s16 (INT64_C (0))); -+ return __builtin_aarch64_sqrdmulh_lanev8hi (__a, __tmp, __c); ++ return __builtin_aarch64_sqrdmulh_lanev8hi (__a, __b, __c); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vqrdmulhq_lane_s32 (int32x4_t __a, int32x2_t __b, const int __c) +{ -+ int32x4_t __tmp = vcombine_s32 (__b, vcreate_s32 (INT64_C (0))); -+ return __builtin_aarch64_sqrdmulh_lanev4si (__a, __tmp, __c); ++ return __builtin_aarch64_sqrdmulh_lanev4si (__a, __b, __c); +} + +__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) @@ -45077,11 +47977,396 @@ +/* End of optimal implementations in approved order. */ + +#endif +--- a/src/gcc/config/aarch64/atomics.md ++++ b/src/gcc/config/aarch64/atomics.md +@@ -0,0 +1,382 @@ ++;; Machine description for AArch64 processor synchronization primitives. ++;; Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. ++;; Contributed by ARM Ltd. ++;; ++;; This file is part of GCC. ++;; ++;; GCC is free software; you can redistribute it and/or modify it ++;; under the terms of the GNU General Public License as published by ++;; the Free Software Foundation; either version 3, or (at your option) ++;; any later version. ++;; ++;; GCC is distributed in the hope that it will be useful, but ++;; WITHOUT ANY WARRANTY; without even the implied warranty of ++;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++;; General Public License for more details. ++;; ++;; You should have received a copy of the GNU General Public License ++;; along with GCC; see the file COPYING3. If not see ++;; . ++ ++(define_c_enum "unspecv" ++ [ ++ UNSPECV_LX ; Represent a load-exclusive. ++ UNSPECV_SX ; Represent a store-exclusive. ++ UNSPECV_LDA ; Represent an atomic load or load-acquire. ++ UNSPECV_STL ; Represent an atomic store or store-release. ++ UNSPECV_ATOMIC_CMPSW ; Represent an atomic compare swap. ++ UNSPECV_ATOMIC_EXCHG ; Represent an atomic exchange. ++ UNSPECV_ATOMIC_OP ; Represent an atomic operation. ++]) ++ ++(define_expand "atomic_compare_and_swap" ++ [(match_operand:SI 0 "register_operand" "") ;; bool out ++ (match_operand:ALLI 1 "register_operand" "") ;; val out ++ (match_operand:ALLI 2 "aarch64_sync_memory_operand" "") ;; memory ++ (match_operand:ALLI 3 "general_operand" "") ;; expected ++ (match_operand:ALLI 4 "register_operand" "") ;; desired ++ (match_operand:SI 5 "const_int_operand") ;; is_weak ++ (match_operand:SI 6 "const_int_operand") ;; mod_s ++ (match_operand:SI 7 "const_int_operand")] ;; mod_f ++ "" ++ { ++ aarch64_expand_compare_and_swap (operands); ++ DONE; ++ } ++) ++ ++(define_insn_and_split "atomic_compare_and_swap_1" ++ [(set (reg:CC CC_REGNUM) ;; bool out ++ (unspec_volatile:CC [(const_int 0)] UNSPECV_ATOMIC_CMPSW)) ++ (set (match_operand:SI 0 "register_operand" "=&r") ;; val out ++ (zero_extend:SI ++ (match_operand:SHORT 1 "aarch64_sync_memory_operand" "+Q"))) ;; memory ++ (set (match_dup 1) ++ (unspec_volatile:SHORT ++ [(match_operand:SI 2 "aarch64_plus_operand" "rI") ;; expected ++ (match_operand:SHORT 3 "register_operand" "r") ;; desired ++ (match_operand:SI 4 "const_int_operand") ;; is_weak ++ (match_operand:SI 5 "const_int_operand") ;; mod_s ++ (match_operand:SI 6 "const_int_operand")] ;; mod_f ++ UNSPECV_ATOMIC_CMPSW)) ++ (clobber (match_scratch:SI 7 "=&r"))] ++ "" ++ "#" ++ "&& reload_completed" ++ [(const_int 0)] ++ { ++ aarch64_split_compare_and_swap (operands); ++ DONE; ++ } ++) ++ ++(define_insn_and_split "atomic_compare_and_swap_1" ++ [(set (reg:CC CC_REGNUM) ;; bool out ++ (unspec_volatile:CC [(const_int 0)] UNSPECV_ATOMIC_CMPSW)) ++ (set (match_operand:GPI 0 "register_operand" "=&r") ;; val out ++ (match_operand:GPI 1 "aarch64_sync_memory_operand" "+Q")) ;; memory ++ (set (match_dup 1) ++ (unspec_volatile:GPI ++ [(match_operand:GPI 2 "aarch64_plus_operand" "rI") ;; expect ++ (match_operand:GPI 3 "register_operand" "r") ;; desired ++ (match_operand:SI 4 "const_int_operand") ;; is_weak ++ (match_operand:SI 5 "const_int_operand") ;; mod_s ++ (match_operand:SI 6 "const_int_operand")] ;; mod_f ++ UNSPECV_ATOMIC_CMPSW)) ++ (clobber (match_scratch:SI 7 "=&r"))] ++ "" ++ "#" ++ "&& reload_completed" ++ [(const_int 0)] ++ { ++ aarch64_split_compare_and_swap (operands); ++ DONE; ++ } ++) ++ ++(define_insn_and_split "atomic_exchange" ++ [(set (match_operand:ALLI 0 "register_operand" "=&r") ;; output ++ (match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q")) ;; memory ++ (set (match_dup 1) ++ (unspec_volatile:ALLI ++ [(match_operand:ALLI 2 "register_operand" "r") ;; input ++ (match_operand:SI 3 "const_int_operand" "")] ;; model ++ UNSPECV_ATOMIC_EXCHG)) ++ (clobber (reg:CC CC_REGNUM)) ++ (clobber (match_scratch:SI 4 "=&r"))] ++ "" ++ "#" ++ "&& reload_completed" ++ [(const_int 0)] ++ { ++ aarch64_split_atomic_op (SET, operands[0], NULL, operands[1], ++ operands[2], operands[3], operands[4]); ++ DONE; ++ } ++) ++ ++(define_insn_and_split "atomic_" ++ [(set (match_operand:ALLI 0 "aarch64_sync_memory_operand" "+Q") ++ (unspec_volatile:ALLI ++ [(atomic_op:ALLI (match_dup 0) ++ (match_operand:ALLI 1 "" "rn")) ++ (match_operand:SI 2 "const_int_operand")] ;; model ++ UNSPECV_ATOMIC_OP)) ++ (clobber (reg:CC CC_REGNUM)) ++ (clobber (match_scratch:ALLI 3 "=&r")) ++ (clobber (match_scratch:SI 4 "=&r"))] ++ "" ++ "#" ++ "&& reload_completed" ++ [(const_int 0)] ++ { ++ aarch64_split_atomic_op (, NULL, operands[3], operands[0], ++ operands[1], operands[2], operands[4]); ++ DONE; ++ } ++) ++ ++(define_insn_and_split "atomic_nand" ++ [(set (match_operand:ALLI 0 "aarch64_sync_memory_operand" "+Q") ++ (unspec_volatile:ALLI ++ [(not:ALLI ++ (and:ALLI (match_dup 0) ++ (match_operand:ALLI 1 "aarch64_logical_operand" "rn"))) ++ (match_operand:SI 2 "const_int_operand")] ;; model ++ UNSPECV_ATOMIC_OP)) ++ (clobber (reg:CC CC_REGNUM)) ++ (clobber (match_scratch:ALLI 3 "=&r")) ++ (clobber (match_scratch:SI 4 "=&r"))] ++ "" ++ "#" ++ "&& reload_completed" ++ [(const_int 0)] ++ { ++ aarch64_split_atomic_op (NOT, NULL, operands[3], operands[0], ++ operands[1], operands[2], operands[4]); ++ DONE; ++ } ++) ++ ++(define_insn_and_split "atomic_fetch_" ++ [(set (match_operand:ALLI 0 "register_operand" "=&r") ++ (match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q")) ++ (set (match_dup 1) ++ (unspec_volatile:ALLI ++ [(atomic_op:ALLI (match_dup 1) ++ (match_operand:ALLI 2 "" "rn")) ++ (match_operand:SI 3 "const_int_operand")] ;; model ++ UNSPECV_ATOMIC_OP)) ++ (clobber (reg:CC CC_REGNUM)) ++ (clobber (match_scratch:ALLI 4 "=&r")) ++ (clobber (match_scratch:SI 5 "=&r"))] ++ "" ++ "#" ++ "&& reload_completed" ++ [(const_int 0)] ++ { ++ aarch64_split_atomic_op (, operands[0], operands[4], operands[1], ++ operands[2], operands[3], operands[5]); ++ DONE; ++ } ++) ++ ++(define_insn_and_split "atomic_fetch_nand" ++ [(set (match_operand:ALLI 0 "register_operand" "=&r") ++ (match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q")) ++ (set (match_dup 1) ++ (unspec_volatile:ALLI ++ [(not:ALLI ++ (and:ALLI (match_dup 1) ++ (match_operand:ALLI 2 "aarch64_logical_operand" "rn"))) ++ (match_operand:SI 3 "const_int_operand")] ;; model ++ UNSPECV_ATOMIC_OP)) ++ (clobber (reg:CC CC_REGNUM)) ++ (clobber (match_scratch:ALLI 4 "=&r")) ++ (clobber (match_scratch:SI 5 "=&r"))] ++ "" ++ "#" ++ "&& reload_completed" ++ [(const_int 0)] ++ { ++ aarch64_split_atomic_op (NOT, operands[0], operands[4], operands[1], ++ operands[2], operands[3], operands[5]); ++ DONE; ++ } ++) ++ ++(define_insn_and_split "atomic__fetch" ++ [(set (match_operand:ALLI 0 "register_operand" "=&r") ++ (atomic_op:ALLI ++ (match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q") ++ (match_operand:ALLI 2 "" "rn"))) ++ (set (match_dup 1) ++ (unspec_volatile:ALLI ++ [(match_dup 1) (match_dup 2) ++ (match_operand:SI 3 "const_int_operand")] ;; model ++ UNSPECV_ATOMIC_OP)) ++ (clobber (reg:CC CC_REGNUM)) ++ (clobber (match_scratch:SI 4 "=&r"))] ++ "" ++ "#" ++ "&& reload_completed" ++ [(const_int 0)] ++ { ++ aarch64_split_atomic_op (, NULL, operands[0], operands[1], ++ operands[2], operands[3], operands[4]); ++ DONE; ++ } ++) ++ ++(define_insn_and_split "atomic_nand_fetch" ++ [(set (match_operand:ALLI 0 "register_operand" "=&r") ++ (not:ALLI ++ (and:ALLI ++ (match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q") ++ (match_operand:ALLI 2 "aarch64_logical_operand" "rn")))) ++ (set (match_dup 1) ++ (unspec_volatile:ALLI ++ [(match_dup 1) (match_dup 2) ++ (match_operand:SI 3 "const_int_operand")] ;; model ++ UNSPECV_ATOMIC_OP)) ++ (clobber (reg:CC CC_REGNUM)) ++ (clobber (match_scratch:SI 4 "=&r"))] ++ "" ++ "#" ++ "&& reload_completed" ++ [(const_int 0)] ++ { ++ aarch64_split_atomic_op (NOT, NULL, operands[0], operands[1], ++ operands[2], operands[3], operands[4]); ++ DONE; ++ } ++) ++ ++(define_insn "atomic_load" ++ [(set (match_operand:ALLI 0 "register_operand" "=r") ++ (unspec_volatile:ALLI ++ [(match_operand:ALLI 1 "aarch64_sync_memory_operand" "Q") ++ (match_operand:SI 2 "const_int_operand")] ;; model ++ UNSPECV_LDA))] ++ "" ++ { ++ enum memmodel model = (enum memmodel) INTVAL (operands[2]); ++ if (model == MEMMODEL_RELAXED ++ || model == MEMMODEL_CONSUME ++ || model == MEMMODEL_RELEASE) ++ return "ldr\t%0, %1"; ++ else ++ return "ldar\t%0, %1"; ++ } ++) ++ ++(define_insn "atomic_store" ++ [(set (match_operand:ALLI 0 "memory_operand" "=Q") ++ (unspec_volatile:ALLI ++ [(match_operand:ALLI 1 "general_operand" "rZ") ++ (match_operand:SI 2 "const_int_operand")] ;; model ++ UNSPECV_STL))] ++ "" ++ { ++ enum memmodel model = (enum memmodel) INTVAL (operands[2]); ++ if (model == MEMMODEL_RELAXED ++ || model == MEMMODEL_CONSUME ++ || model == MEMMODEL_ACQUIRE) ++ return "str\t%1, %0"; ++ else ++ return "stlr\t%1, %0"; ++ } ++) ++ ++(define_insn "aarch64_load_exclusive" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (zero_extend:SI ++ (unspec_volatile:SHORT ++ [(match_operand:SHORT 1 "aarch64_sync_memory_operand" "Q") ++ (match_operand:SI 2 "const_int_operand")] ++ UNSPECV_LX)))] ++ "" ++ { ++ enum memmodel model = (enum memmodel) INTVAL (operands[2]); ++ if (model == MEMMODEL_RELAXED ++ || model == MEMMODEL_CONSUME ++ || model == MEMMODEL_RELEASE) ++ return "ldxr\t%w0, %1"; ++ else ++ return "ldaxr\t%w0, %1"; ++ } ++) ++ ++(define_insn "aarch64_load_exclusive" ++ [(set (match_operand:GPI 0 "register_operand" "=r") ++ (unspec_volatile:GPI ++ [(match_operand:GPI 1 "aarch64_sync_memory_operand" "Q") ++ (match_operand:SI 2 "const_int_operand")] ++ UNSPECV_LX))] ++ "" ++ { ++ enum memmodel model = (enum memmodel) INTVAL (operands[2]); ++ if (model == MEMMODEL_RELAXED ++ || model == MEMMODEL_CONSUME ++ || model == MEMMODEL_RELEASE) ++ return "ldxr\t%0, %1"; ++ else ++ return "ldaxr\t%0, %1"; ++ } ++) ++ ++(define_insn "aarch64_store_exclusive" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec_volatile:SI [(const_int 0)] UNSPECV_SX)) ++ (set (match_operand:ALLI 1 "aarch64_sync_memory_operand" "=Q") ++ (unspec_volatile:ALLI ++ [(match_operand:ALLI 2 "register_operand" "r") ++ (match_operand:SI 3 "const_int_operand")] ++ UNSPECV_SX))] ++ "" ++ { ++ enum memmodel model = (enum memmodel) INTVAL (operands[3]); ++ if (model == MEMMODEL_RELAXED ++ || model == MEMMODEL_CONSUME ++ || model == MEMMODEL_ACQUIRE) ++ return "stxr\t%w0, %2, %1"; ++ else ++ return "stlxr\t%w0, %2, %1"; ++ } ++) ++ ++(define_expand "mem_thread_fence" ++ [(match_operand:SI 0 "const_int_operand" "")] ++ "" ++ { ++ enum memmodel model = (enum memmodel) INTVAL (operands[0]); ++ if (model != MEMMODEL_RELAXED && model != MEMMODEL_CONSUME) ++ emit_insn (gen_dmb (operands[0])); ++ DONE; ++ } ++) ++ ++(define_expand "dmb" ++ [(set (match_dup 1) ++ (unspec:BLK [(match_dup 1) (match_operand:SI 0 "const_int_operand")] ++ UNSPEC_MB))] ++ "" ++ { ++ operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); ++ MEM_VOLATILE_P (operands[1]) = 1; ++ } ++) ++ ++(define_insn "*dmb" ++ [(set (match_operand:BLK 0 "" "") ++ (unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")] ++ UNSPEC_MB))] ++ "" ++ { ++ enum memmodel model = (enum memmodel) INTVAL (operands[1]); ++ if (model == MEMMODEL_ACQUIRE) ++ return "dmb\\tishld"; ++ else ++ return "dmb\\tish"; ++ } ++) --- a/src/gcc/config/aarch64/constraints.md +++ b/src/gcc/config/aarch64/constraints.md -@@ -0,0 +1,167 @@ +@@ -0,0 +1,178 @@ +;; Machine description for AArch64 architecture. -+;; Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. ++;; Copyright (C) 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc. +;; Contributed by ARM Ltd. +;; +;; This file is part of GCC. @@ -45151,7 +48436,7 @@ +(define_constraint "Y" + "Floating point constant zero." + (and (match_code "const_double") -+ (match_test "aarch64_const_double_zero_rtx_p (op)"))) ++ (match_test "aarch64_float_const_zero_rtx_p (op)"))) + +(define_constraint "Z" + "Integer constant zero." @@ -45184,6 +48469,11 @@ + A constraint that matches the immediate constant -1." + (match_test "op == constm1_rtx")) + ++(define_constraint "Ui1" ++ "@internal ++ A constraint that matches the immediate constant +1." ++ (match_test "op == const1_rtx")) ++ +(define_constraint "Ui3" + "@internal + A constraint that matches the integers 0...4." @@ -45215,6 +48505,12 @@ + (and (match_code "mem") + (match_test "aarch64_simd_mem_operand_p (op)"))) + ++(define_constraint "Ufc" ++ "A floating point constant which can be used with an\ ++ FMOV immediate operation." ++ (and (match_code "const_double") ++ (match_test "aarch64_float_const_representable_p (op)"))) ++ +(define_constraint "Dn" + "@internal + A constraint that matches vector of immediates." @@ -45284,7 +48580,7 @@ +echo " (const (symbol_ref \"((enum attr_tune) aarch64_tune)\")))" --- a/src/gcc/config/aarch64/iterators.md +++ b/src/gcc/config/aarch64/iterators.md -@@ -0,0 +1,716 @@ +@@ -0,0 +1,802 @@ +;; Machine description for AArch64 architecture. +;; Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. +;; Contributed by ARM Ltd. @@ -45376,6 +48672,9 @@ +;; All modes. +(define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF]) + ++;; All vector modes and DI. ++(define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI]) ++ +;; Vector modes for Integer reduction across lanes. +(define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI]) + @@ -45514,6 +48813,15 @@ + UNSPEC_CMTST ; Used in aarch64-simd.md. + UNSPEC_FMAX ; Used in aarch64-simd.md. + UNSPEC_FMIN ; Used in aarch64-simd.md. ++ UNSPEC_BSL ; Used in aarch64-simd.md. ++ UNSPEC_TBL ; Used in vector permute patterns. ++ UNSPEC_CONCAT ; Used in vector permute patterns. ++ UNSPEC_ZIP1 ; Used in vector permute patterns. ++ UNSPEC_ZIP2 ; Used in vector permute patterns. ++ UNSPEC_UZP1 ; Used in vector permute patterns. ++ UNSPEC_UZP2 ; Used in vector permute patterns. ++ UNSPEC_TRN1 ; Used in vector permute patterns. ++ UNSPEC_TRN2 ; Used in vector permute patterns. +]) + +;; ------------------------------------------------------------------- @@ -45615,6 +48923,22 @@ + (QI "QI")]) + +;; Define container mode for lane selection. ++(define_mode_attr VCOND [(V4HI "V4HI") (V8HI "V4HI") ++ (V2SI "V2SI") (V4SI "V2SI") ++ (DI "DI") (V2DI "DI") ++ (V2SF "V2SF") (V4SF "V2SF") ++ (V2DF "DF")]) ++ ++;; Define container mode for lane selection. ++(define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI") ++ (V4HI "V8HI") (V8HI "V8HI") ++ (V2SI "V4SI") (V4SI "V4SI") ++ (DI "V2DI") (V2DI "V2DI") ++ (V2SF "V2SF") (V4SF "V4SF") ++ (V2DF "V2DF") (SI "V4SI") ++ (HI "V8HI") (QI "V16QI")]) ++ ++;; Define container mode for lane selection. +(define_mode_attr VCON [(V8QI "V16QI") (V16QI "V16QI") + (V4HI "V8HI") (V8HI "V8HI") + (V2SI "V4SI") (V4SI "V4SI") @@ -45701,8 +49025,17 @@ +(define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI") + (V4HI "V4HI") (V8HI "V8HI") + (V2SI "V2SI") (V4SI "V4SI") ++ (DI "DI") (V2DI "V2DI") + (V2SF "V2SI") (V4SF "V4SI") -+ (DI "DI") (V2DI "V2DI")]) ++ (V2DF "V2DI")]) ++ ++;; Lower case mode of results of comparison operations. ++(define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi") ++ (V4HI "v4hi") (V8HI "v8hi") ++ (V2SI "v2si") (V4SI "v4si") ++ (DI "di") (V2DI "v2di") ++ (V2SF "v2si") (V4SF "v4si") ++ (V2DF "v2di")]) + +;; Vm for lane instructions is restricted to FP_LO_REGS. +(define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x") @@ -45735,6 +49068,13 @@ + +(define_mode_attr VSTRUCT_DREG [(OI "TI") (CI "EI") (XI "OI")]) + ++;; Mode for atomic operation suffixes ++(define_mode_attr atomic_sfx ++ [(QI "b") (HI "h") (SI "") (DI "")]) ++ ++(define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si")]) ++(define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI")]) ++ +;; ------------------------------------------------------------------- +;; Code Iterators +;; ------------------------------------------------------------------- @@ -45766,7 +49106,7 @@ +;; Iterator for __sync_ operations that where the operation can be +;; represented directly RTL. This is all of the sync operations bar +;; nand. -+(define_code_iterator syncop [plus minus ior xor and]) ++(define_code_iterator atomic_op [plus minus ior xor and]) + +;; Iterator for integer conversions +(define_code_iterator FIXUORS [fix unsigned_fix]) @@ -45861,6 +49201,16 @@ +;; MLA/MLS attributes. +(define_code_attr as [(ss_plus "a") (ss_minus "s")]) + ++;; Atomic operations ++(define_code_attr atomic_optab ++ [(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")]) ++ ++(define_code_attr atomic_op_operand ++ [(ior "aarch64_logical_operand") ++ (xor "aarch64_logical_operand") ++ (and "aarch64_logical_operand") ++ (plus "aarch64_plus_operand") ++ (minus "aarch64_plus_operand")]) + +;; ------------------------------------------------------------------- +;; Int Iterators. @@ -45918,6 +49268,15 @@ + +(define_int_iterator VCMP_U [UNSPEC_CMHS UNSPEC_CMHI UNSPEC_CMTST]) + ++(define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2 ++ UNSPEC_TRN1 UNSPEC_TRN2 ++ UNSPEC_UZP1 UNSPEC_UZP2]) ++ ++(define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM ++ UNSPEC_FRINTI UNSPEC_FRINTX UNSPEC_FRINTA]) ++ ++(define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM ++ UNSPEC_FRINTA]) + +;; ------------------------------------------------------------------- +;; Int Iterators Attributes. @@ -46001,6 +49360,29 @@ +(define_int_attr offsetlr [(UNSPEC_SSLI "1") (UNSPEC_USLI "1") + (UNSPEC_SSRI "0") (UNSPEC_USRI "0")]) + ++;; Standard pattern names for floating-point rounding instructions. ++(define_int_attr frint_pattern [(UNSPEC_FRINTZ "btrunc") ++ (UNSPEC_FRINTP "ceil") ++ (UNSPEC_FRINTM "floor") ++ (UNSPEC_FRINTI "nearbyint") ++ (UNSPEC_FRINTX "rint") ++ (UNSPEC_FRINTA "round")]) ++ ++;; frint suffix for floating-point rounding instructions. ++(define_int_attr frint_suffix [(UNSPEC_FRINTZ "z") (UNSPEC_FRINTP "p") ++ (UNSPEC_FRINTM "m") (UNSPEC_FRINTI "i") ++ (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a")]) ++ ++(define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round") ++ (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor")]) ++ ++(define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip") ++ (UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn") ++ (UNSPEC_UZP1 "uzp") (UNSPEC_UZP2 "uzp")]) ++ ++(define_int_attr perm_hilo [(UNSPEC_ZIP1 "1") (UNSPEC_ZIP2 "2") ++ (UNSPEC_TRN1 "1") (UNSPEC_TRN2 "2") ++ (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")]) --- a/src/gcc/config/aarch64/large.md +++ b/src/gcc/config/aarch64/large.md @@ -0,0 +1,312 @@ @@ -46318,9 +49700,9 @@ + large_cpu_f2i") --- a/src/gcc/config/aarch64/predicates.md +++ b/src/gcc/config/aarch64/predicates.md -@@ -0,0 +1,297 @@ +@@ -0,0 +1,298 @@ +;; Machine description for AArch64 architecture. -+;; Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. ++;; Copyright (C) 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc. +;; Contributed by ARM Ltd. +;; +;; This file is part of GCC. @@ -46352,16 +49734,17 @@ + (ior (match_operand 0 "register_operand") + (match_test "op == const0_rtx")))) + -+(define_predicate "aarch64_reg_zero_or_m1" ++(define_predicate "aarch64_reg_zero_or_m1_or_1" + (and (match_code "reg,subreg,const_int") + (ior (match_operand 0 "register_operand") + (ior (match_test "op == const0_rtx") -+ (match_test "op == constm1_rtx"))))) ++ (ior (match_test "op == constm1_rtx") ++ (match_test "op == const1_rtx")))))) + +(define_predicate "aarch64_fp_compare_operand" + (ior (match_operand 0 "register_operand") + (and (match_code "const_double") -+ (match_test "aarch64_const_double_zero_rtx_p (op)")))) ++ (match_test "aarch64_float_const_zero_rtx_p (op)")))) + +(define_predicate "aarch64_plus_immediate" + (and (match_code "const_int") @@ -46906,479 +50289,9 @@ + "small_cpu_fpalu, small_cpu_fpmuld,\ + small_cpu_fdivs, small_cpu_fdivd,\ + small_cpu_f2i") ---- a/src/gcc/config/aarch64/sync.md -+++ b/src/gcc/config/aarch64/sync.md -@@ -0,0 +1,467 @@ -+;; Machine description for AArch64 processor synchronization primitives. -+;; Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. -+;; Contributed by ARM Ltd. -+;; -+;; This file is part of GCC. -+;; -+;; GCC is free software; you can redistribute it and/or modify it -+;; under the terms of the GNU General Public License as published by -+;; the Free Software Foundation; either version 3, or (at your option) -+;; any later version. -+;; -+;; GCC is distributed in the hope that it will be useful, but -+;; WITHOUT ANY WARRANTY; without even the implied warranty of -+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+;; General Public License for more details. -+;; -+;; You should have received a copy of the GNU General Public License -+;; along with GCC; see the file COPYING3. If not see -+;; . -+ -+(define_c_enum "unspecv" -+ [ -+ UNSPECV_SYNC_COMPARE_AND_SWAP ; Represent a sync_compare_and_swap. -+ UNSPECV_SYNC_LOCK ; Represent a sync_lock_test_and_set. -+ UNSPECV_SYNC_LOCK_RELEASE ; Represent a sync_lock_release. -+ UNSPECV_SYNC_OP ; Represent a sync_ -+ UNSPECV_SYNC_NEW_OP ; Represent a sync_new_ -+ UNSPECV_SYNC_OLD_OP ; Represent a sync_old_ -+]) -+ -+(define_expand "sync_compare_and_swap" -+ [(set (match_operand:ALLI 0 "register_operand") -+ (unspec_volatile:ALLI [(match_operand:ALLI 1 "memory_operand") -+ (match_operand:ALLI 2 "register_operand") -+ (match_operand:ALLI 3 "register_operand")] -+ UNSPECV_SYNC_COMPARE_AND_SWAP))] -+ "" -+ { -+ struct aarch64_sync_generator generator; -+ generator.op = aarch64_sync_generator_omrn; -+ generator.u.omrn = gen_aarch64_sync_compare_and_swap; -+ aarch64_expand_sync (mode, &generator, operands[0], operands[1], -+ operands[2], operands[3]); -+ DONE; -+ }) -+ -+(define_expand "sync_lock_test_and_set" -+ [(match_operand:ALLI 0 "register_operand") -+ (match_operand:ALLI 1 "memory_operand") -+ (match_operand:ALLI 2 "register_operand")] -+ "" -+ { -+ struct aarch64_sync_generator generator; -+ generator.op = aarch64_sync_generator_omn; -+ generator.u.omn = gen_aarch64_sync_lock_test_and_set; -+ aarch64_expand_sync (mode, &generator, operands[0], operands[1], -+ NULL, operands[2]); -+ DONE; -+ }) -+ -+(define_expand "sync_" -+ [(match_operand:ALLI 0 "memory_operand") -+ (match_operand:ALLI 1 "register_operand") -+ (syncop:ALLI (match_dup 0) (match_dup 1))] -+ "" -+ { -+ struct aarch64_sync_generator generator; -+ generator.op = aarch64_sync_generator_omn; -+ generator.u.omn = gen_aarch64_sync_new_; -+ aarch64_expand_sync (mode, &generator, NULL, operands[0], NULL, -+ operands[1]); -+ DONE; -+ }) -+ -+(define_expand "sync_nand" -+ [(match_operand:ALLI 0 "memory_operand") -+ (match_operand:ALLI 1 "register_operand") -+ (not:ALLI (and:ALLI (match_dup 0) (match_dup 1)))] -+ "" -+ { -+ struct aarch64_sync_generator generator; -+ generator.op = aarch64_sync_generator_omn; -+ generator.u.omn = gen_aarch64_sync_new_nand; -+ aarch64_expand_sync (mode, &generator, NULL, operands[0], NULL, -+ operands[1]); -+ DONE; -+ }) -+ -+(define_expand "sync_new_" -+ [(match_operand:ALLI 0 "register_operand") -+ (match_operand:ALLI 1 "memory_operand") -+ (match_operand:ALLI 2 "register_operand") -+ (syncop:ALLI (match_dup 1) (match_dup 2))] -+ "" -+ { -+ struct aarch64_sync_generator generator; -+ generator.op = aarch64_sync_generator_omn; -+ generator.u.omn = gen_aarch64_sync_new_; -+ aarch64_expand_sync (mode, &generator, operands[0], operands[1], -+ NULL, operands[2]); -+ DONE; -+ }) -+ -+(define_expand "sync_new_nand" -+ [(match_operand:ALLI 0 "register_operand") -+ (match_operand:ALLI 1 "memory_operand") -+ (match_operand:ALLI 2 "register_operand") -+ (not:ALLI (and:ALLI (match_dup 1) (match_dup 2)))] -+ "" -+ { -+ struct aarch64_sync_generator generator; -+ generator.op = aarch64_sync_generator_omn; -+ generator.u.omn = gen_aarch64_sync_new_nand; -+ aarch64_expand_sync (mode, &generator, operands[0], operands[1], -+ NULL, operands[2]); -+ DONE; -+ }); -+ -+(define_expand "sync_old_" -+ [(match_operand:ALLI 0 "register_operand") -+ (match_operand:ALLI 1 "memory_operand") -+ (match_operand:ALLI 2 "register_operand") -+ (syncop:ALLI (match_dup 1) (match_dup 2))] -+ "" -+ { -+ struct aarch64_sync_generator generator; -+ generator.op = aarch64_sync_generator_omn; -+ generator.u.omn = gen_aarch64_sync_old_; -+ aarch64_expand_sync (mode, &generator, operands[0], operands[1], -+ NULL, operands[2]); -+ DONE; -+ }) -+ -+(define_expand "sync_old_nand" -+ [(match_operand:ALLI 0 "register_operand") -+ (match_operand:ALLI 1 "memory_operand") -+ (match_operand:ALLI 2 "register_operand") -+ (not:ALLI (and:ALLI (match_dup 1) (match_dup 2)))] -+ "" -+ { -+ struct aarch64_sync_generator generator; -+ generator.op = aarch64_sync_generator_omn; -+ generator.u.omn = gen_aarch64_sync_old_nand; -+ aarch64_expand_sync (mode, &generator, operands[0], operands[1], -+ NULL, operands[2]); -+ DONE; -+ }) -+ -+(define_expand "memory_barrier" -+ [(set (match_dup 0) (unspec:BLK [(match_dup 0)] UNSPEC_MB))] -+ "" -+{ -+ operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); -+ MEM_VOLATILE_P (operands[0]) = 1; -+}) -+ -+(define_insn "aarch64_sync_compare_and_swap" -+ [(set (match_operand:GPI 0 "register_operand" "=&r") -+ (unspec_volatile:GPI -+ [(match_operand:GPI 1 "aarch64_sync_memory_operand" "+Q") -+ (match_operand:GPI 2 "register_operand" "r") -+ (match_operand:GPI 3 "register_operand" "r")] -+ UNSPECV_SYNC_COMPARE_AND_SWAP)) -+ (set (match_dup 1) (unspec_volatile:GPI [(match_dup 2)] -+ UNSPECV_SYNC_COMPARE_AND_SWAP)) -+ (clobber:GPI (match_scratch:GPI 4 "=&r")) -+ (set (reg:CC CC_REGNUM) (unspec_volatile:CC [(match_dup 1)] -+ UNSPECV_SYNC_COMPARE_AND_SWAP)) -+ ] -+ "" -+ { -+ return aarch64_output_sync_insn (insn, operands); -+ } -+ [(set_attr "sync_result" "0") -+ (set_attr "sync_memory" "1") -+ (set_attr "sync_required_value" "2") -+ (set_attr "sync_new_value" "3") -+ (set_attr "sync_t1" "0") -+ (set_attr "sync_t2" "4") -+ ]) -+ -+(define_insn "aarch64_sync_compare_and_swap" -+ [(set (match_operand:SI 0 "register_operand" "=&r") -+ (zero_extend:SI -+ (unspec_volatile:SHORT -+ [(match_operand:SHORT 1 "aarch64_sync_memory_operand" "+Q") -+ (match_operand:SI 2 "register_operand" "r") -+ (match_operand:SI 3 "register_operand" "r")] -+ UNSPECV_SYNC_COMPARE_AND_SWAP))) -+ (set (match_dup 1) (unspec_volatile:SHORT [(match_dup 2)] -+ UNSPECV_SYNC_COMPARE_AND_SWAP)) -+ (clobber:SI (match_scratch:SI 4 "=&r")) -+ (set (reg:CC CC_REGNUM) (unspec_volatile:CC [(match_dup 1)] -+ UNSPECV_SYNC_COMPARE_AND_SWAP)) -+ ] -+ "" -+ { -+ return aarch64_output_sync_insn (insn, operands); -+ } -+ [(set_attr "sync_result" "0") -+ (set_attr "sync_memory" "1") -+ (set_attr "sync_required_value" "2") -+ (set_attr "sync_new_value" "3") -+ (set_attr "sync_t1" "0") -+ (set_attr "sync_t2" "4") -+ ]) -+ -+(define_insn "aarch64_sync_lock_test_and_set" -+ [(set (match_operand:GPI 0 "register_operand" "=&r") -+ (match_operand:GPI 1 "aarch64_sync_memory_operand" "+Q")) -+ (set (match_dup 1) -+ (unspec_volatile:GPI [(match_operand:GPI 2 "register_operand" "r")] -+ UNSPECV_SYNC_LOCK)) -+ (clobber (reg:CC CC_REGNUM)) -+ (clobber (match_scratch:GPI 3 "=&r"))] -+ "" -+ { -+ return aarch64_output_sync_insn (insn, operands); -+ } -+ [(set_attr "sync_release_barrier" "no") -+ (set_attr "sync_result" "0") -+ (set_attr "sync_memory" "1") -+ (set_attr "sync_new_value" "2") -+ (set_attr "sync_t1" "0") -+ (set_attr "sync_t2" "3") -+ ]) -+ -+(define_insn "aarch64_sync_lock_test_and_set" -+ [(set (match_operand:SI 0 "register_operand" "=&r") -+ (zero_extend:SI (match_operand:SHORT 1 -+ "aarch64_sync_memory_operand" "+Q"))) -+ (set (match_dup 1) -+ (unspec_volatile:SHORT [(match_operand:SI 2 "register_operand" "r")] -+ UNSPECV_SYNC_LOCK)) -+ (clobber (reg:CC CC_REGNUM)) -+ (clobber (match_scratch:SI 3 "=&r"))] -+ "" -+ { -+ return aarch64_output_sync_insn (insn, operands); -+ } -+ [(set_attr "sync_release_barrier" "no") -+ (set_attr "sync_result" "0") -+ (set_attr "sync_memory" "1") -+ (set_attr "sync_new_value" "2") -+ (set_attr "sync_t1" "0") -+ (set_attr "sync_t2" "3") -+ ]) -+ -+(define_insn "aarch64_sync_new_" -+ [(set (match_operand:GPI 0 "register_operand" "=&r") -+ (unspec_volatile:GPI -+ [(syncop:GPI -+ (match_operand:GPI 1 "aarch64_sync_memory_operand" "+Q") -+ (match_operand:GPI 2 "register_operand" "r"))] -+ UNSPECV_SYNC_NEW_OP)) -+ (set (match_dup 1) -+ (unspec_volatile:GPI [(match_dup 1) (match_dup 2)] -+ UNSPECV_SYNC_NEW_OP)) -+ (clobber (reg:CC CC_REGNUM)) -+ (clobber (match_scratch:GPI 3 "=&r"))] -+ "" -+ { -+ return aarch64_output_sync_insn (insn, operands); -+ } -+ [(set_attr "sync_result" "0") -+ (set_attr "sync_memory" "1") -+ (set_attr "sync_new_value" "2") -+ (set_attr "sync_t1" "0") -+ (set_attr "sync_t2" "3") -+ (set_attr "sync_op" "") -+ ]) -+ -+(define_insn "aarch64_sync_new_nand" -+ [(set (match_operand:GPI 0 "register_operand" "=&r") -+ (unspec_volatile:GPI -+ [(not:GPI (and:GPI -+ (match_operand:GPI 1 "aarch64_sync_memory_operand" "+Q") -+ (match_operand:GPI 2 "register_operand" "r")))] -+ UNSPECV_SYNC_NEW_OP)) -+ (set (match_dup 1) -+ (unspec_volatile:GPI [(match_dup 1) (match_dup 2)] -+ UNSPECV_SYNC_NEW_OP)) -+ (clobber (reg:CC CC_REGNUM)) -+ (clobber (match_scratch:GPI 3 "=&r"))] -+ "" -+ { -+ return aarch64_output_sync_insn (insn, operands); -+ } -+ [(set_attr "sync_result" "0") -+ (set_attr "sync_memory" "1") -+ (set_attr "sync_new_value" "2") -+ (set_attr "sync_t1" "0") -+ (set_attr "sync_t2" "3") -+ (set_attr "sync_op" "nand") -+ ]) -+ -+(define_insn "aarch64_sync_new_" -+ [(set (match_operand:SI 0 "register_operand" "=&r") -+ (unspec_volatile:SI -+ [(syncop:SI -+ (zero_extend:SI -+ (match_operand:SHORT 1 "aarch64_sync_memory_operand" "+Q")) -+ (match_operand:SI 2 "register_operand" "r"))] -+ UNSPECV_SYNC_NEW_OP)) -+ (set (match_dup 1) -+ (unspec_volatile:SHORT [(match_dup 1) (match_dup 2)] -+ UNSPECV_SYNC_NEW_OP)) -+ (clobber (reg:CC CC_REGNUM)) -+ (clobber (match_scratch:SI 3 "=&r"))] -+ "" -+ { -+ return aarch64_output_sync_insn (insn, operands); -+ } -+ [(set_attr "sync_result" "0") -+ (set_attr "sync_memory" "1") -+ (set_attr "sync_new_value" "2") -+ (set_attr "sync_t1" "0") -+ (set_attr "sync_t2" "3") -+ (set_attr "sync_op" "") -+ ]) -+ -+(define_insn "aarch64_sync_new_nand" -+ [(set (match_operand:SI 0 "register_operand" "=&r") -+ (unspec_volatile:SI -+ [(not:SI -+ (and:SI -+ (zero_extend:SI -+ (match_operand:SHORT 1 "aarch64_sync_memory_operand" "+Q")) -+ (match_operand:SI 2 "register_operand" "r"))) -+ ] UNSPECV_SYNC_NEW_OP)) -+ (set (match_dup 1) -+ (unspec_volatile:SHORT [(match_dup 1) (match_dup 2)] -+ UNSPECV_SYNC_NEW_OP)) -+ (clobber (reg:CC CC_REGNUM)) -+ (clobber (match_scratch:SI 3 "=&r"))] -+ "" -+ { -+ return aarch64_output_sync_insn (insn, operands); -+ } -+ [(set_attr "sync_result" "0") -+ (set_attr "sync_memory" "1") -+ (set_attr "sync_new_value" "2") -+ (set_attr "sync_t1" "0") -+ (set_attr "sync_t2" "3") -+ (set_attr "sync_op" "nand") -+ ]) -+ -+(define_insn "aarch64_sync_old_" -+ [(set (match_operand:GPI 0 "register_operand" "=&r") -+ (unspec_volatile:GPI -+ [(syncop:GPI -+ (match_operand:GPI 1 "aarch64_sync_memory_operand" "+Q") -+ (match_operand:GPI 2 "register_operand" "r"))] -+ UNSPECV_SYNC_OLD_OP)) -+ (set (match_dup 1) -+ (unspec_volatile:GPI [(match_dup 1) (match_dup 2)] -+ UNSPECV_SYNC_OLD_OP)) -+ (clobber (reg:CC CC_REGNUM)) -+ (clobber (match_scratch:GPI 3 "=&r")) -+ (clobber (match_scratch:GPI 4 "=&r"))] -+ "" -+ { -+ return aarch64_output_sync_insn (insn, operands); -+ } -+ [(set_attr "sync_result" "0") -+ (set_attr "sync_memory" "1") -+ (set_attr "sync_new_value" "2") -+ (set_attr "sync_t1" "3") -+ (set_attr "sync_t2" "4") -+ (set_attr "sync_op" "") -+ ]) -+ -+(define_insn "aarch64_sync_old_nand" -+ [(set (match_operand:GPI 0 "register_operand" "=&r") -+ (unspec_volatile:GPI -+ [(not:GPI (and:GPI -+ (match_operand:GPI 1 "aarch64_sync_memory_operand" "+Q") -+ (match_operand:GPI 2 "register_operand" "r")))] -+ UNSPECV_SYNC_OLD_OP)) -+ (set (match_dup 1) -+ (unspec_volatile:GPI [(match_dup 1) (match_dup 2)] -+ UNSPECV_SYNC_OLD_OP)) -+ (clobber (reg:CC CC_REGNUM)) -+ (clobber (match_scratch:GPI 3 "=&r")) -+ (clobber (match_scratch:GPI 4 "=&r"))] -+ "" -+ { -+ return aarch64_output_sync_insn (insn, operands); -+ } -+ [(set_attr "sync_result" "0") -+ (set_attr "sync_memory" "1") -+ (set_attr "sync_new_value" "2") -+ (set_attr "sync_t1" "3") -+ (set_attr "sync_t2" "4") -+ (set_attr "sync_op" "nand") -+ ]) -+ -+(define_insn "aarch64_sync_old_" -+ [(set (match_operand:SI 0 "register_operand" "=&r") -+ (unspec_volatile:SI -+ [(syncop:SI -+ (zero_extend:SI -+ (match_operand:SHORT 1 "aarch64_sync_memory_operand" "+Q")) -+ (match_operand:SI 2 "register_operand" "r"))] -+ UNSPECV_SYNC_OLD_OP)) -+ (set (match_dup 1) -+ (unspec_volatile:SHORT [(match_dup 1) (match_dup 2)] -+ UNSPECV_SYNC_OLD_OP)) -+ (clobber (reg:CC CC_REGNUM)) -+ (clobber (match_scratch:SI 3 "=&r")) -+ (clobber (match_scratch:SI 4 "=&r"))] -+ "" -+ { -+ return aarch64_output_sync_insn (insn, operands); -+ } -+ [(set_attr "sync_result" "0") -+ (set_attr "sync_memory" "1") -+ (set_attr "sync_new_value" "2") -+ (set_attr "sync_t1" "3") -+ (set_attr "sync_t2" "4") -+ (set_attr "sync_op" "") -+ ]) -+ -+(define_insn "aarch64_sync_old_nand" -+ [(set (match_operand:SI 0 "register_operand" "=&r") -+ (unspec_volatile:SI -+ [(not:SI -+ (and:SI -+ (zero_extend:SI -+ (match_operand:SHORT 1 "aarch64_sync_memory_operand" "+Q")) -+ (match_operand:SI 2 "register_operand" "r")))] -+ UNSPECV_SYNC_OLD_OP)) -+ (set (match_dup 1) -+ (unspec_volatile:SHORT [(match_dup 1) (match_dup 2)] -+ UNSPECV_SYNC_OLD_OP)) -+ (clobber (reg:CC CC_REGNUM)) -+ (clobber (match_scratch:SI 3 "=&r")) -+ (clobber (match_scratch:SI 4 "=&r"))] -+ "" -+ { -+ return aarch64_output_sync_insn (insn, operands); -+ } -+ [(set_attr "sync_result" "0") -+ (set_attr "sync_memory" "1") -+ (set_attr "sync_new_value" "2") -+ (set_attr "sync_t1" "3") -+ (set_attr "sync_t2" "4") -+ (set_attr "sync_op" "nand") -+ ]) -+ -+(define_insn "*memory_barrier" -+ [(set (match_operand:BLK 0 "" "") -+ (unspec:BLK [(match_dup 0)] UNSPEC_MB))] -+ "" -+ "dmb\\tish" -+) -+ -+(define_insn "sync_lock_release" -+ [(set (match_operand:ALLI 0 "memory_operand" "+Q") -+ (unspec_volatile:ALLI [(match_operand:ALLI 1 "register_operand" "r")] -+ UNSPECV_SYNC_LOCK_RELEASE))] -+ -+ "" -+ { -+ return aarch64_output_sync_lock_release (operands[1], operands[0]); -+ }) -+ --- a/src/gcc/config/aarch64/t-aarch64 +++ b/src/gcc/config/aarch64/t-aarch64 -@@ -0,0 +1,32 @@ +@@ -0,0 +1,33 @@ +# Machine description for AArch64 architecture. +# Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. +# Contributed by ARM Ltd. @@ -47408,7 +50321,8 @@ +aarch64-builtins.o: $(srcdir)/config/aarch64/aarch64-builtins.c $(CONFIG_H) \ + $(SYSTEM_H) coretypes.h $(TM_H) \ + $(RTL_H) $(TREE_H) expr.h $(TM_P_H) $(RECOG_H) langhooks.h \ -+ $(DIAGNOSTIC_CORE_H) $(OPTABS_H) ++ $(DIAGNOSTIC_CORE_H) $(OPTABS_H) \ ++ $(srcdir)/config/aarch64/aarch64-simd-builtins.def + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ + $(srcdir)/config/aarch64/aarch64-builtins.c --- a/src/gcc/config/aarch64/t-aarch64-linux @@ -47436,27 +50350,292 @@ + +LIB1ASMSRC = aarch64/lib1funcs.asm +LIB1ASMFUNCS = _aarch64_sync_cache_range +--- a/src/gcc/config/arm/arm1020e.md ++++ b/src/gcc/config/arm/arm1020e.md +@@ -66,13 +66,13 @@ + ;; ALU operations with no shifted operand + (define_insn_reservation "1020alu_op" 1 + (and (eq_attr "tune" "arm1020e,arm1022e") +- (eq_attr "type" "alu")) ++ (eq_attr "type" "alu_reg,simple_alu_imm")) + "1020a_e,1020a_m,1020a_w") + + ;; ALU operations with a shift-by-constant operand + (define_insn_reservation "1020alu_shift_op" 1 + (and (eq_attr "tune" "arm1020e,arm1022e") +- (eq_attr "type" "alu_shift")) ++ (eq_attr "type" "simple_alu_shift,alu_shift")) + "1020a_e,1020a_m,1020a_w") + + ;; ALU operations with a shift-by-register operand +@@ -284,7 +284,7 @@ + + (define_insn_reservation "v10_fmul" 6 + (and (eq_attr "vfp10" "yes") +- (eq_attr "type" "fmuls,fmacs,fmuld,fmacd")) ++ (eq_attr "type" "fmuls,fmacs,ffmas,fmuld,fmacd,ffmad")) + "1020a_e+v10_fmac*2") + + (define_insn_reservation "v10_fdivs" 18 +--- a/src/gcc/config/arm/arm1026ejs.md ++++ b/src/gcc/config/arm/arm1026ejs.md +@@ -66,13 +66,13 @@ + ;; ALU operations with no shifted operand + (define_insn_reservation "alu_op" 1 + (and (eq_attr "tune" "arm1026ejs") +- (eq_attr "type" "alu")) ++ (eq_attr "type" "alu_reg,simple_alu_imm")) + "a_e,a_m,a_w") + + ;; ALU operations with a shift-by-constant operand + (define_insn_reservation "alu_shift_op" 1 + (and (eq_attr "tune" "arm1026ejs") +- (eq_attr "type" "alu_shift")) ++ (eq_attr "type" "simple_alu_shift,alu_shift")) + "a_e,a_m,a_w") + + ;; ALU operations with a shift-by-register operand +--- a/src/gcc/config/arm/arm1136jfs.md ++++ b/src/gcc/config/arm/arm1136jfs.md +@@ -75,13 +75,13 @@ + ;; ALU operations with no shifted operand + (define_insn_reservation "11_alu_op" 2 + (and (eq_attr "tune" "arm1136js,arm1136jfs") +- (eq_attr "type" "alu")) ++ (eq_attr "type" "alu_reg,simple_alu_imm")) + "e_1,e_2,e_3,e_wb") + + ;; ALU operations with a shift-by-constant operand + (define_insn_reservation "11_alu_shift_op" 2 + (and (eq_attr "tune" "arm1136js,arm1136jfs") +- (eq_attr "type" "alu_shift")) ++ (eq_attr "type" "simple_alu_shift,alu_shift")) + "e_1,e_2,e_3,e_wb") + + ;; ALU operations with a shift-by-register operand +--- a/src/gcc/config/arm/arm926ejs.md ++++ b/src/gcc/config/arm/arm926ejs.md +@@ -58,7 +58,7 @@ + ;; ALU operations with no shifted operand + (define_insn_reservation "9_alu_op" 1 + (and (eq_attr "tune" "arm926ejs") +- (eq_attr "type" "alu,alu_shift")) ++ (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,alu_shift")) + "e,m,w") + + ;; ALU operations with a shift-by-register operand --- a/src/gcc/config/arm/arm.c +++ b/src/gcc/config/arm/arm.c -@@ -745,6 +745,9 @@ - /* Nonzero if this chip supports the ARM 6K extensions. */ - int arm_arch6k = 0; - -+/* Nonzero if instructions present in ARMv6-M can be used. */ -+int arm_arch6m = 0; -+ - /* Nonzero if this chip supports the ARM 7 extensions. */ - int arm_arch7 = 0; - -@@ -1704,6 +1707,7 @@ - arm_arch6 = (insn_flags & FL_ARCH6) != 0; - arm_arch6k = (insn_flags & FL_ARCH6K) != 0; - arm_arch_notm = (insn_flags & FL_NOTM) != 0; -+ arm_arch6m = arm_arch6 && !arm_arch_notm; - arm_arch7 = (insn_flags & FL_ARCH7) != 0; - arm_arch7em = (insn_flags & FL_ARCH7EM) != 0; - arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0; -@@ -2497,6 +2501,28 @@ +@@ -133,6 +133,7 @@ + static int arm_comp_type_attributes (const_tree, const_tree); + static void arm_set_default_type_attributes (tree); + static int arm_adjust_cost (rtx, rtx, rtx, int); ++static int arm_sched_reorder (FILE *, int, rtx *, int *, int); + static int optimal_immediate_sequence (enum rtx_code code, + unsigned HOST_WIDE_INT val, + struct four_ints *return_sequence); +@@ -273,6 +274,11 @@ + static bool arm_vectorize_vec_perm_const_ok (enum machine_mode vmode, + const unsigned char *sel); + ++ ++static int arm_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost, ++ tree vectype, ++ int misalign ATTRIBUTE_UNUSED); ++ + + /* Table of machine attributes. */ + static const struct attribute_spec arm_attribute_table[] = +@@ -369,6 +375,9 @@ + #undef TARGET_SCHED_ADJUST_COST + #define TARGET_SCHED_ADJUST_COST arm_adjust_cost + ++#undef TARGET_SCHED_REORDER ++#define TARGET_SCHED_REORDER arm_sched_reorder ++ + #undef TARGET_REGISTER_MOVE_COST + #define TARGET_REGISTER_MOVE_COST arm_register_move_cost + +@@ -623,6 +632,10 @@ + #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \ + arm_vectorize_vec_perm_const_ok + ++#undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST ++#define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \ ++ arm_builtin_vectorization_cost ++ + struct gcc_target targetm = TARGET_INITIALIZER; + + /* Obstack for minipool constant handling. */ +@@ -802,6 +815,10 @@ + int arm_arch_arm_hwdiv; + int arm_arch_thumb_hwdiv; + ++/* Nonzero if we should use Neon to handle 64-bits operations rather ++ than core registers. */ ++int prefer_neon_for_64bits = 0; ++ + /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, + we must report the mode of the memory reference from + TARGET_PRINT_OPERAND to TARGET_PRINT_OPERAND_ADDRESS. */ +@@ -869,6 +886,23 @@ + l1_size, \ + l1_line_size + ++/* arm generic vectorizer costs. */ ++static const ++struct cpu_vec_costs arm_default_vec_cost = { ++ 1, /* scalar_stmt_cost. */ ++ 1, /* scalar load_cost. */ ++ 1, /* scalar_store_cost. */ ++ 1, /* vec_stmt_cost. */ ++ 1, /* vec_to_scalar_cost. */ ++ 1, /* scalar_to_vec_cost. */ ++ 1, /* vec_align_load_cost. */ ++ 1, /* vec_unalign_load_cost. */ ++ 1, /* vec_unalign_store_cost. */ ++ 1, /* vec_store_cost. */ ++ 3, /* cond_taken_branch_cost. */ ++ 1, /* cond_not_taken_branch_cost. */ ++}; ++ + const struct tune_params arm_slowmul_tune = + { + arm_slowmul_rtx_costs, +@@ -877,7 +911,10 @@ + 5, /* Max cond insns. */ + ARM_PREFETCH_NOT_BENEFICIAL, + true, /* Prefer constant pool. */ +- arm_default_branch_cost ++ arm_default_branch_cost, ++ false, /* Prefer Neon for ++ 64-bits bitops. */ ++ &arm_default_vec_cost, /* Vectorizer costs. */ + }; + + const struct tune_params arm_fastmul_tune = +@@ -888,7 +925,10 @@ + 5, /* Max cond insns. */ + ARM_PREFETCH_NOT_BENEFICIAL, + true, /* Prefer constant pool. */ +- arm_default_branch_cost ++ arm_default_branch_cost, ++ false, /* Prefer Neon for ++ 64-bits bitops. */ ++ &arm_default_vec_cost, /* Vectorizer costs. */ + }; + + /* StrongARM has early execution of branches, so a sequence that is worth +@@ -902,7 +942,10 @@ + 3, /* Max cond insns. */ + ARM_PREFETCH_NOT_BENEFICIAL, + true, /* Prefer constant pool. */ +- arm_default_branch_cost ++ arm_default_branch_cost, ++ false, /* Prefer Neon for ++ 64-bits bitops. */ ++ &arm_default_vec_cost, /* Vectorizer costs. */ + }; + + const struct tune_params arm_xscale_tune = +@@ -913,7 +956,10 @@ + 3, /* Max cond insns. */ + ARM_PREFETCH_NOT_BENEFICIAL, + true, /* Prefer constant pool. */ +- arm_default_branch_cost ++ arm_default_branch_cost, ++ false, /* Prefer Neon for ++ 64-bits bitops. */ ++ &arm_default_vec_cost, /* Vectorizer costs. */ + }; + + const struct tune_params arm_9e_tune = +@@ -924,7 +970,10 @@ + 5, /* Max cond insns. */ + ARM_PREFETCH_NOT_BENEFICIAL, + true, /* Prefer constant pool. */ +- arm_default_branch_cost ++ arm_default_branch_cost, ++ false, /* Prefer Neon for ++ 64-bits bitops. */ ++ &arm_default_vec_cost, /* Vectorizer costs. */ + }; + + const struct tune_params arm_v6t2_tune = +@@ -935,7 +984,10 @@ + 5, /* Max cond insns. */ + ARM_PREFETCH_NOT_BENEFICIAL, + false, /* Prefer constant pool. */ +- arm_default_branch_cost ++ arm_default_branch_cost, ++ false, /* Prefer Neon for ++ 64-bits bitops. */ ++ &arm_default_vec_cost, /* Vectorizer costs. */ + }; + + /* Generic Cortex tuning. Use more specific tunings if appropriate. */ +@@ -947,7 +999,10 @@ + 5, /* Max cond insns. */ + ARM_PREFETCH_NOT_BENEFICIAL, + false, /* Prefer constant pool. */ +- arm_default_branch_cost ++ arm_default_branch_cost, ++ false, /* Prefer Neon for ++ 64-bits bitops. */ ++ &arm_default_vec_cost, /* Vectorizer costs. */ + }; + + /* Branches can be dual-issued on Cortex-A5, so conditional execution is +@@ -961,7 +1016,10 @@ + 1, /* Max cond insns. */ + ARM_PREFETCH_NOT_BENEFICIAL, + false, /* Prefer constant pool. */ +- arm_cortex_a5_branch_cost ++ arm_cortex_a5_branch_cost, ++ false, /* Prefer Neon for ++ 64-bits bitops. */ ++ &arm_default_vec_cost, /* Vectorizer costs. */ + }; + + const struct tune_params arm_cortex_a9_tune = +@@ -972,7 +1030,10 @@ + 5, /* Max cond insns. */ + ARM_PREFETCH_BENEFICIAL(4,32,32), + false, /* Prefer constant pool. */ +- arm_default_branch_cost ++ arm_default_branch_cost, ++ false, /* Prefer Neon for ++ 64-bits bitops. */ ++ &arm_default_vec_cost, /* Vectorizer costs. */ + }; + + const struct tune_params arm_fa726te_tune = +@@ -983,7 +1044,10 @@ + 5, /* Max cond insns. */ + ARM_PREFETCH_NOT_BENEFICIAL, + true, /* Prefer constant pool. */ +- arm_default_branch_cost ++ arm_default_branch_cost, ++ false, /* Prefer Neon for ++ 64-bits bitops. */ ++ &arm_default_vec_cost, /* Vectorizer costs. */ + }; + + +@@ -2034,6 +2098,12 @@ + global_options.x_param_values, + global_options_set.x_param_values); + ++ /* Use Neon to perform 64-bits operations rather than core ++ registers. */ ++ prefer_neon_for_64bits = current_tune->prefer_neon_for_64bits; ++ if (use_neon_for_64bits == 1) ++ prefer_neon_for_64bits = true; ++ + /* Register global variables with the garbage collector. */ + arm_add_gc_roots (); + } +@@ -2501,6 +2571,28 @@ } } @@ -47485,7 +50664,7 @@ /* Emit a sequence of insns to handle a large constant. CODE is the code of the operation required, it can be any of SET, PLUS, IOR, AND, XOR, MINUS; -@@ -2944,6 +2970,31 @@ +@@ -2948,6 +3040,31 @@ return 1; } @@ -47517,7 +50696,7 @@ /* Calculate a few attributes that may be useful for specific optimizations. */ /* Count number of leading zeros. */ -@@ -7634,6 +7685,28 @@ +@@ -7640,6 +7757,28 @@ return true; case SET: @@ -47546,7 +50725,7 @@ return false; case UNSPEC: -@@ -7645,6 +7718,17 @@ +@@ -7651,6 +7790,17 @@ } return true; @@ -47564,7 +50743,7 @@ default: *total = COSTS_N_INSNS (4); return false; -@@ -7985,6 +8069,17 @@ +@@ -7991,6 +8141,17 @@ *total = COSTS_N_INSNS (4); return true; @@ -47582,7 +50761,230 @@ case HIGH: case LO_SUM: /* We prefer constant pool entries to MOVW/MOVT pairs, so bump the -@@ -8852,11 +8947,14 @@ +@@ -8578,6 +8739,222 @@ + } + } + ++ ++/* Vectorizer cost model implementation. */ ++ ++/* Implement targetm.vectorize.builtin_vectorization_cost. */ ++static int ++arm_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost, ++ tree vectype, ++ int misalign ATTRIBUTE_UNUSED) ++{ ++ unsigned elements; ++ ++ switch (type_of_cost) ++ { ++ case scalar_stmt: ++ return current_tune->vec_costs->scalar_stmt_cost; ++ ++ case scalar_load: ++ return current_tune->vec_costs->scalar_load_cost; ++ ++ case scalar_store: ++ return current_tune->vec_costs->scalar_store_cost; ++ ++ case vector_stmt: ++ return current_tune->vec_costs->vec_stmt_cost; ++ ++ case vector_load: ++ return current_tune->vec_costs->vec_align_load_cost; ++ ++ case vector_store: ++ return current_tune->vec_costs->vec_store_cost; ++ ++ case vec_to_scalar: ++ return current_tune->vec_costs->vec_to_scalar_cost; ++ ++ case scalar_to_vec: ++ return current_tune->vec_costs->scalar_to_vec_cost; ++ ++ case unaligned_load: ++ return current_tune->vec_costs->vec_unalign_load_cost; ++ ++ case unaligned_store: ++ return current_tune->vec_costs->vec_unalign_store_cost; ++ ++ case cond_branch_taken: ++ return current_tune->vec_costs->cond_taken_branch_cost; ++ ++ case cond_branch_not_taken: ++ return current_tune->vec_costs->cond_not_taken_branch_cost; ++ ++ case vec_perm: ++ case vec_promote_demote: ++ return current_tune->vec_costs->vec_stmt_cost; ++ ++ default: ++ gcc_unreachable (); ++ } ++} ++ ++/* Return true if and only if this insn can dual-issue only as older. */ ++static bool ++cortexa7_older_only (rtx insn) ++{ ++ if (recog_memoized (insn) < 0) ++ return false; ++ ++ if (get_attr_insn (insn) == INSN_MOV) ++ return false; ++ ++ switch (get_attr_type (insn)) ++ { ++ case TYPE_ALU_REG: ++ case TYPE_LOAD_BYTE: ++ case TYPE_LOAD1: ++ case TYPE_STORE1: ++ case TYPE_FFARITHS: ++ case TYPE_FADDS: ++ case TYPE_FFARITHD: ++ case TYPE_FADDD: ++ case TYPE_FCPYS: ++ case TYPE_F_CVT: ++ case TYPE_FCMPS: ++ case TYPE_FCMPD: ++ case TYPE_FCONSTS: ++ case TYPE_FCONSTD: ++ case TYPE_FMULS: ++ case TYPE_FMACS: ++ case TYPE_FMULD: ++ case TYPE_FMACD: ++ case TYPE_FDIVS: ++ case TYPE_FDIVD: ++ case TYPE_F_2_R: ++ case TYPE_F_FLAG: ++ case TYPE_F_LOADS: ++ case TYPE_F_STORES: ++ return true; ++ default: ++ return false; ++ } ++} ++ ++/* Return true if and only if this insn can dual-issue as younger. */ ++static bool ++cortexa7_younger (FILE *file, int verbose, rtx insn) ++{ ++ if (recog_memoized (insn) < 0) ++ { ++ if (verbose > 5) ++ fprintf (file, ";; not cortexa7_younger %d\n", INSN_UID (insn)); ++ return false; ++ } ++ ++ if (get_attr_insn (insn) == INSN_MOV) ++ return true; ++ ++ switch (get_attr_type (insn)) ++ { ++ case TYPE_SIMPLE_ALU_IMM: ++ case TYPE_SIMPLE_ALU_SHIFT: ++ case TYPE_BRANCH: ++ case TYPE_CALL: ++ return true; ++ default: ++ return false; ++ } ++} ++ ++ ++/* Look for an instruction that can dual issue only as an older ++ instruction, and move it in front of any instructions that can ++ dual-issue as younger, while preserving the relative order of all ++ other instructions in the ready list. This is a hueuristic to help ++ dual-issue in later cycles, by postponing issue of more flexible ++ instructions. This heuristic may affect dual issue opportunities ++ in the current cycle. */ ++static void ++cortexa7_sched_reorder (FILE *file, int verbose, rtx *ready, int *n_readyp, ++ int clock) ++{ ++ int i; ++ int first_older_only = -1, first_younger = -1; ++ ++ if (verbose > 5) ++ fprintf (file, ++ ";; sched_reorder for cycle %d with %d insns in ready list\n", ++ clock, ++ *n_readyp); ++ ++ /* Traverse the ready list from the head (the instruction to issue ++ first), and looking for the first instruction that can issue as ++ younger and the first instruction that can dual-issue only as ++ older. */ ++ for (i = *n_readyp - 1; i >= 0; i--) ++ { ++ rtx insn = ready[i]; ++ if (cortexa7_older_only (insn)) ++ { ++ first_older_only = i; ++ if (verbose > 5) ++ fprintf (file, ";; reorder older found %d\n", INSN_UID (insn)); ++ break; ++ } ++ else if (cortexa7_younger (file, verbose, insn) && first_younger == -1) ++ first_younger = i; ++ } ++ ++ /* Nothing to reorder because either no younger insn found or insn ++ that can dual-issue only as older appears before any insn that ++ can dual-issue as younger. */ ++ if (first_younger == -1) ++ { ++ if (verbose > 5) ++ fprintf (file, ";; sched_reorder nothing to reorder as no younger\n"); ++ return; ++ } ++ ++ /* Nothing to reorder because no older-only insn in the ready list. */ ++ if (first_older_only == -1) ++ { ++ if (verbose > 5) ++ fprintf (file, ";; sched_reorder nothing to reorder as no older_only\n"); ++ return; ++ } ++ ++ /* Move first_older_only insn before first_younger. */ ++ if (verbose > 5) ++ fprintf (file, ";; cortexa7_sched_reorder insn %d before %d\n", ++ INSN_UID(ready [first_older_only]), ++ INSN_UID(ready [first_younger])); ++ rtx first_older_only_insn = ready [first_older_only]; ++ for (i = first_older_only; i < first_younger; i++) ++ { ++ ready[i] = ready[i+1]; ++ } ++ ++ ready[i] = first_older_only_insn; ++ return; ++} ++ ++/* Implement TARGET_SCHED_REORDER. */ ++static int ++arm_sched_reorder (FILE *file, int verbose, rtx *ready, int *n_readyp, ++ int clock) ++{ ++ switch (arm_tune) ++ { ++ case cortexa7: ++ cortexa7_sched_reorder (file, verbose, ready, n_readyp, clock); ++ break; ++ default: ++ /* Do nothing for other cores. */ ++ break; ++ } ++ ++ return arm_issue_rate (); ++} ++ + /* This function implements the target macro TARGET_SCHED_ADJUST_COST. + It corrects the value of COST based on the relationship between + INSN and DEP through the dependence LINK. It returns the new +@@ -8858,11 +9235,14 @@ vmov i64 17 aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh vmov f32 18 aBbbbbbc defgh000 00000000 00000000 @@ -47597,7 +50999,7 @@ Variants 0-5 (inclusive) may also be used as immediates for the second operand of VORR/VBIC instructions. -@@ -8887,11 +8985,25 @@ +@@ -8893,11 +9273,25 @@ break; \ } @@ -47625,7 +51027,7 @@ /* Vectors of float constants. */ if (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) -@@ -8899,7 +9011,7 @@ +@@ -8905,7 +9299,7 @@ rtx el0 = CONST_VECTOR_ELT (op, 0); REAL_VALUE_TYPE r0; @@ -47634,7 +51036,7 @@ return -1; REAL_VALUE_FROM_CONST_DOUBLE (r0, el0); -@@ -8921,13 +9033,16 @@ +@@ -8927,13 +9321,16 @@ if (elementwidth) *elementwidth = 0; @@ -47653,7 +51055,7 @@ unsigned HOST_WIDE_INT elpart; unsigned int part, parts; -@@ -9638,7 +9753,11 @@ +@@ -9644,7 +10041,11 @@ && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) && GET_CODE (XEXP (ind, 1)) == CONST_INT && INTVAL (XEXP (ind, 1)) > -1024 @@ -47666,7 +51068,7 @@ && (INTVAL (XEXP (ind, 1)) & 3) == 0) return TRUE; -@@ -10041,6 +10160,42 @@ +@@ -10047,6 +10448,42 @@ } } @@ -47709,7 +51111,7 @@ /* Return 1 if memory locations are adjacent. */ int adjacent_mem_locations (rtx a, rtx b) -@@ -13271,47 +13426,148 @@ +@@ -13277,47 +13714,148 @@ FOR_BB_INSNS_REVERSE (bb, insn) { if (NONJUMP_INSN_P (insn) @@ -47780,9 +51182,7 @@ + && low_register_operand (op1, SImode)) + action = CONV; + break; - -- PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec); -- INSN_CODE (insn) = -1; ++ + case MULT: + /* MULS ,, + As an exception to the rule, this is only used @@ -47849,9 +51249,11 @@ + /* MOVS and MOV with registers have different + encodings, so are not relevant here. */ + break; -+ -+ default: -+ break; + +- PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec); +- INSN_CODE (insn) = -1; ++ default: ++ break; } - /* We can also handle a commutative operation where the - second operand matches the destination. */ @@ -47886,21 +51288,7 @@ } } -@@ -13337,6 +13593,13 @@ - if (TARGET_THUMB2) - thumb2_reorg (); - -+ /* Ensure all insns that must be split have been split at this point. -+ Otherwise, the pool placement code below may compute incorrect -+ insn lengths. Note that when optimizing, all insns have already -+ been split at this point. */ -+ if (!optimize) -+ split_all_insns_noflow (); -+ - minipool_fix_head = minipool_fix_tail = NULL; - - /* The first insn must always be a note, or the code below won't -@@ -14533,15 +14796,16 @@ +@@ -14546,15 +15084,16 @@ return ""; } @@ -47924,7 +51312,7 @@ For example, the in-memory ordering of a big-endian a quadword vector with 16-bit elements when stored from register pair {d0,d1} -@@ -14555,13 +14819,28 @@ +@@ -14568,13 +15107,28 @@ dN -> (rN+1, rN), dN+1 -> (rN+3, rN+2) So that STM/LDM can be used on vectors in ARM registers, and the @@ -47955,7 +51343,7 @@ const char *templ; char buff[50]; enum machine_mode mode; -@@ -14573,6 +14852,7 @@ +@@ -14586,6 +15140,7 @@ gcc_assert (REG_P (reg)); regno = REGNO (reg); @@ -47963,7 +51351,7 @@ gcc_assert (VFP_REGNO_OK_FOR_DOUBLE (regno) || NEON_REGNO_OK_FOR_QUAD (regno)); gcc_assert (VALID_NEON_DREG_MODE (mode) -@@ -14589,13 +14869,23 @@ +@@ -14602,13 +15157,23 @@ switch (GET_CODE (addr)) { case POST_INC: @@ -47990,7 +51378,7 @@ templ = "v%smdb%%?\t%%0!, %%h1"; ops[0] = XEXP (addr, 0); ops[1] = reg; -@@ -14608,7 +14898,6 @@ +@@ -14621,7 +15186,6 @@ case LABEL_REF: case PLUS: { @@ -47998,7 +51386,7 @@ int i; int overlap = -1; for (i = 0; i < nregs; i++) -@@ -14639,7 +14928,12 @@ +@@ -14652,7 +15216,12 @@ } default: @@ -48012,7 +51400,7 @@ ops[0] = mem; ops[1] = reg; } -@@ -17258,6 +17552,19 @@ +@@ -17287,6 +17856,19 @@ } return; @@ -48032,38 +51420,87 @@ case 'B': if (GET_CODE (x) == CONST_INT) { -@@ -22286,12 +22593,18 @@ - { - unsigned pushable_regs; - unsigned next_hi_reg; -+ unsigned arg_regs_num = TARGET_AAPCS_BASED ? crtl->args.info.aapcs_ncrn -+ : crtl->args.info.nregs; -+ unsigned arg_regs_mask = (1 << arg_regs_num) - 1; - - for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--) - if (live_regs_mask & (1 << next_hi_reg)) - break; - -- pushable_regs = l_mask & 0xff; -+ /* Here we need to mask out registers used for passing arguments -+ even if they can be pushed. This is to avoid using them to stash the high -+ registers. Such kind of stash may clobber the use of arguments. */ -+ pushable_regs = l_mask & (~arg_regs_mask) & 0xff; - - if (pushable_regs == 0) - pushable_regs = 1 << thumb_find_work_register (live_regs_mask); -@@ -24852,8 +25165,8 @@ - case SImode: - /* Force the value into a register if needed. We waited until after - the zero-extension above to do this properly. */ -- if (!arm_add_operand (oldval, mode)) -- oldval = force_reg (mode, oldval); -+ if (!arm_add_operand (oldval, SImode)) -+ oldval = force_reg (SImode, oldval); - break; - - case DImode: -@@ -25294,20 +25607,20 @@ +@@ -19101,6 +19683,8 @@ + VAR8 (BINOP, vmul, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), + VAR8 (TERNOP, vmla, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), + VAR3 (TERNOP, vmlal, v8qi, v4hi, v2si), ++ VAR2 (TERNOP, vfma, v2sf, v4sf), ++ VAR2 (TERNOP, vfms, v2sf, v4sf), + VAR8 (TERNOP, vmls, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), + VAR3 (TERNOP, vmlsl, v8qi, v4hi, v2si), + VAR4 (BINOP, vqdmulh, v4hi, v2si, v8hi, v4si), +@@ -23485,6 +24069,62 @@ + return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node; + } + ++/* Return non-zero iff the consumer (a multiply-accumulate or a ++ multiple-subtract instruction) has an accumulator dependency on the ++ result of the producer and no other dependency on that result. It ++ does not check if the producer is multiply-accumulate instruction. */ ++int ++arm_mac_accumulator_is_result (rtx producer, rtx consumer) ++{ ++ rtx result; ++ rtx op0, op1, acc; ++ ++ producer = PATTERN (producer); ++ consumer = PATTERN (consumer); ++ ++ if (GET_CODE (producer) == COND_EXEC) ++ producer = COND_EXEC_CODE (producer); ++ if (GET_CODE (consumer) == COND_EXEC) ++ consumer = COND_EXEC_CODE (consumer); ++ ++ if (GET_CODE (producer) != SET) ++ return 0; ++ ++ result = XEXP (producer, 0); ++ ++ if (GET_CODE (consumer) != SET) ++ return 0; ++ ++ /* Check that the consumer is of the form ++ (set (...) (plus (mult ...) (...))) ++ or ++ (set (...) (minus (...) (mult ...))). */ ++ if (GET_CODE (XEXP (consumer, 1)) == PLUS) ++ { ++ if (GET_CODE (XEXP (XEXP (consumer, 1), 0)) != MULT) ++ return 0; ++ ++ op0 = XEXP (XEXP (XEXP (consumer, 1), 0), 0); ++ op1 = XEXP (XEXP (XEXP (consumer, 1), 0), 1); ++ acc = XEXP (XEXP (consumer, 1), 1); ++ } ++ else if (GET_CODE (XEXP (consumer, 1)) == MINUS) ++ { ++ if (GET_CODE (XEXP (XEXP (consumer, 1), 1)) != MULT) ++ return 0; ++ ++ op0 = XEXP (XEXP (XEXP (consumer, 1), 1), 0); ++ op1 = XEXP (XEXP (XEXP (consumer, 1), 1), 1); ++ acc = XEXP (XEXP (consumer, 1), 0); ++ } ++ else ++ return 0; ++ ++ return (reg_overlap_mentioned_p (result, acc) ++ && !reg_overlap_mentioned_p (result, op0) ++ && !reg_overlap_mentioned_p (result, op1)); ++} ++ + /* Return non-zero if the consumer (a multiply-accumulate instruction) + has an accumulator dependency on the result of the producer (a + multiplication instruction) and no other dependency on that result. */ +@@ -24439,6 +25079,7 @@ + case cortexr5: + case genericv7a: + case cortexa5: ++ case cortexa7: + case cortexa8: + case cortexa9: + case fa726te: +@@ -25374,20 +26015,20 @@ default: return false; } @@ -48091,7 +51528,7 @@ /* Success! */ if (d->testing_p) return true; -@@ -25382,6 +25695,72 @@ +@@ -25462,6 +26103,72 @@ return true; } @@ -48164,7 +51601,7 @@ /* The NEON VTBL instruction is a fully variable permuation that's even stronger than what we expose via VEC_PERM_EXPR. What it doesn't do is mask the index operand as VEC_PERM_EXPR requires. Therefore we -@@ -25421,6 +25800,12 @@ +@@ -25501,6 +26208,12 @@ static bool arm_expand_vec_perm_const_1 (struct expand_vec_perm_d *d) { @@ -48177,7 +51614,7 @@ /* The pattern matching functions above are written to look for a small number to begin the sequence (0, 1, N/2). If we begin with an index from the second operand, we can swap the operands. */ -@@ -25551,5 +25936,303 @@ +@@ -25631,5 +26344,302 @@ return ret; } @@ -48194,8 +51631,7 @@ + Input requirements: + - It is safe for the input and output to be the same register, but + early-clobber rules apply for the shift amount and scratch registers. -+ - Shift by register requires both scratch registers. Shift by a constant -+ less than 32 in Thumb2 mode requires SCRATCH1 only. In all other cases ++ - Shift by register requires both scratch registers. In all other cases + the scratch registers may be NULL. + - Ashiftrt by a register also clobbers the CC register. */ +void @@ -48502,26 +51938,48 @@ + (set_attr "insn" "sat")]) --- a/src/gcc/config/arm/arm.h +++ b/src/gcc/config/arm/arm.h -@@ -267,7 +267,7 @@ - #define TARGET_UNIFIED_ASM TARGET_THUMB2 - - /* Nonzero if this chip provides the DMB instruction. */ --#define TARGET_HAVE_DMB (arm_arch7) -+#define TARGET_HAVE_DMB (arm_arch6m || arm_arch7) - - /* Nonzero if this chip implements a memory barrier via CP15. */ - #define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \ -@@ -383,6 +383,9 @@ - /* Nonzero if this chip supports the ARM Architecture 6k extensions. */ - extern int arm_arch6k; - -+/* Nonzero if instructions present in ARMv6-M can be used. */ -+extern int arm_arch6m; +@@ -79,6 +79,9 @@ + if (TARGET_VFP) \ + builtin_define ("__VFP_FP__"); \ + \ ++ if (TARGET_FMA) \ ++ builtin_define ("__ARM_FEATURE_FMA"); \ ++ \ + if (TARGET_NEON) \ + builtin_define ("__ARM_NEON__"); \ + \ +@@ -244,6 +247,9 @@ + /* FPU supports VFP half-precision floating-point. */ + #define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16) + ++/* FPU supports fused-multiply-add operations. */ ++#define TARGET_FMA (TARGET_VFP && arm_fpu_desc->rev >= 4) ++ + /* FPU supports Neon instructions. The setting of this macro gets + revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT + and TARGET_HARD_FLOAT to ensure that NEON instructions are +@@ -290,6 +296,9 @@ + #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \ + || (TARGET_THUMB2 && arm_arch_thumb_hwdiv)) + ++/* Should NEON be used for 64-bits bitops. */ ++#define TARGET_PREFER_NEON_64BITS (prefer_neon_for_64bits) ++ + /* True iff the full BPABI is being used. If TARGET_BPABI is true, + then TARGET_AAPCS_BASED must be true -- but the converse does not + hold. TARGET_BPABI implies the use of the BPABI runtime library, +@@ -441,6 +450,10 @@ + /* Nonzero if chip supports integer division instruction in Thumb mode. */ + extern int arm_arch_thumb_hwdiv; + ++/* Nonzero if we should use Neon to handle 64-bits operations rather ++ than core registers. */ ++extern int prefer_neon_for_64bits; + - /* Nonzero if this chip supports the ARM Architecture 7 extensions. */ - extern int arm_arch7; - -@@ -1623,6 +1626,30 @@ + #ifndef TARGET_DEFAULT + #define TARGET_DEFAULT (MASK_APCS_FRAME) + #endif +@@ -1633,6 +1646,30 @@ #define HAVE_PRE_MODIFY_REG TARGET_32BIT #define HAVE_POST_MODIFY_REG TARGET_32BIT @@ -48559,30 +52017,67 @@ ; arm_arch6. This attribute is used to compute attribute "enabled", ; use type "any" to enable an alternative in all cases. -(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,onlya8,nota8" -+(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,onlya8,neon_onlya8,nota8,neon_nota8" ++(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,neon_for_64bits,avoid_neon_for_64bits" (const_string "any")) (define_attr "arch_enabled" "no,yes" -@@ -235,8 +235,18 @@ - (eq_attr "tune" "cortexa8")) +@@ -231,12 +231,30 @@ + (match_test "TARGET_32BIT && !arm_arch6")) (const_string "yes") -+ (and (eq_attr "arch" "neon_onlya8") -+ (eq_attr "tune" "cortexa8") -+ (match_test "TARGET_NEON")) -+ (const_string "yes") +- (and (eq_attr "arch" "onlya8") +- (eq_attr "tune" "cortexa8")) ++ (and (eq_attr "arch" "avoid_neon_for_64bits") ++ (match_test "TARGET_NEON") ++ (not (match_test "TARGET_PREFER_NEON_64BITS"))) + (const_string "yes") + +- (and (eq_attr "arch" "nota8") +- (not (eq_attr "tune" "cortexa8"))) ++ (and (eq_attr "arch" "neon_for_64bits") ++ (match_test "TARGET_NEON") ++ (match_test "TARGET_PREFER_NEON_64BITS")) ++ (const_string "yes")] ++ (const_string "no"))) + - (and (eq_attr "arch" "nota8") - (not (eq_attr "tune" "cortexa8"))) ++(define_attr "opt" "any,speed,size" ++ (const_string "any")) ++ ++(define_attr "opt_enabled" "no,yes" ++ (cond [(eq_attr "opt" "any") ++ (const_string "yes") ++ ++ (and (eq_attr "opt" "speed") ++ (match_test "optimize_function_for_speed_p (cfun)")) + (const_string "yes") + -+ (and (eq_attr "arch" "neon_nota8") -+ (not (eq_attr "tune" "cortexa8")) -+ (match_test "TARGET_NEON")) ++ (and (eq_attr "opt" "size") ++ (match_test "optimize_function_for_size_p (cfun)")) (const_string "yes")] (const_string "no"))) -@@ -283,7 +293,7 @@ +@@ -247,11 +265,15 @@ + + ; Enable all alternatives that are both arch_enabled and insn_enabled. + (define_attr "enabled" "no,yes" +- (if_then_else (eq_attr "insn_enabled" "yes") +- (if_then_else (eq_attr "arch_enabled" "yes") +- (const_string "yes") +- (const_string "no")) +- (const_string "no"))) ++ (cond [(eq_attr "insn_enabled" "no") ++ (const_string "no") ++ ++ (eq_attr "arch_enabled" "no") ++ (const_string "no") ++ ++ (eq_attr "opt_enabled" "no") ++ (const_string "no")] ++ (const_string "yes"))) + + ; POOL_RANGE is how far away from a constant pool entry that this insn + ; can be placed. If the distance is zero, then this insn will never +@@ -283,7 +305,7 @@ ;; scheduling information. (define_attr "insn" @@ -48591,7 +52086,39 @@ (const_string "other")) ; TYPE attribute is used to detect floating point instructions which, if -@@ -356,8 +366,6 @@ +@@ -294,8 +316,15 @@ + ; Classification of each insn + ; Note: vfp.md has different meanings for some of these, and some further + ; types as well. See that file for details. +-; alu any alu instruction that doesn't hit memory or fp +-; regs or have a shifted source operand ++; simple_alu_imm a simple alu instruction that doesn't hit memory or fp ++; regs or have a shifted source operand and has an immediate ++; operand. This currently only tracks very basic immediate ++; alu operations. ++; alu_reg any alu instruction that doesn't hit memory or fp ++; regs or have a shifted source operand ++; and does not have an immediate operand. This is ++; also the default ++; simple_alu_shift covers UXTH, UXTB, SXTH, SXTB + ; alu_shift any data instruction that doesn't hit memory or fp + ; regs, but has a source operand shifted by a constant + ; alu_shift_reg any data instruction that doesn't hit memory or fp +@@ -338,11 +367,11 @@ + ; + + (define_attr "type" +- "alu,alu_shift,alu_shift_reg,mult,block,float,fdivx,fdivd,fdivs,fmul,fmuls,fmuld,fmacs,fmacd,ffmul,farith,ffarith,f_flag,float_em,f_fpa_load,f_fpa_store,f_loads,f_loadd,f_stores,f_stored,f_mem_r,r_mem_f,f_2_r,r_2_f,f_cvt,branch,call,load_byte,load1,load2,load3,load4,store1,store2,store3,store4,mav_farith,mav_dmult,fconsts,fconstd,fadds,faddd,ffariths,ffarithd,fcmps,fcmpd,fcpys" ++ "simple_alu_imm,alu_reg,simple_alu_shift,alu_shift,alu_shift_reg,mult,block,float,fdivx,fdivd,fdivs,fmul,fmuls,fmuld,fmacs,fmacd,ffmas,ffmad,ffmul,farith,ffarith,f_flag,float_em,f_fpa_load,f_fpa_store,f_loads,f_loadd,f_stores,f_stored,f_mem_r,r_mem_f,f_2_r,r_2_f,f_cvt,branch,call,load_byte,load1,load2,load3,load4,store1,store2,store3,store4,mav_farith,mav_dmult,fconsts,fconstd,fadds,faddd,ffariths,ffarithd,fcmps,fcmpd,fcpys" + (if_then_else + (eq_attr "insn" "smulxy,smlaxy,smlalxy,smulwy,smlawx,mul,muls,mla,mlas,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals") + (const_string "mult") +- (const_string "alu"))) ++ (const_string "alu_reg"))) + + ; Is this an (integer side) multiply with a 64-bit result? + (define_attr "mul64" "no,yes" +@@ -356,8 +385,6 @@ (define_attr "ldsched" "no,yes" (const (symbol_ref "arm_ld_sched"))) ;; Classification of NEON instructions for scheduling purposes. @@ -48600,7 +52127,42 @@ (define_attr "neon_type" "neon_int_1,\ neon_int_2,\ -@@ -563,7 +571,7 @@ +@@ -477,7 +504,7 @@ + ; than one on the main cpu execution unit. + (define_attr "core_cycles" "single,multi" + (if_then_else (eq_attr "type" +- "alu,alu_shift,float,fdivx,fdivd,fdivs,fmul,ffmul,farith,ffarith") ++ "simple_alu_imm,alu_reg,simple_alu_shift,alu_shift,float,fdivx,fdivd,fdivs,fmul,ffmul,farith,ffarith") + (const_string "single") + (const_string "multi"))) + +@@ -514,7 +541,7 @@ + + (define_attr "generic_sched" "yes,no" + (const (if_then_else +- (ior (eq_attr "tune" "fa526,fa626,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9,cortexa15,cortexm4") ++ (ior (eq_attr "tune" "fa526,fa626,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa7,cortexa8,cortexa9,cortexa15,cortexm4") + (eq_attr "tune_cortexr4" "yes")) + (const_string "no") + (const_string "yes")))) +@@ -522,7 +549,7 @@ + (define_attr "generic_vfp" "yes,no" + (const (if_then_else + (and (eq_attr "fpu" "vfp") +- (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa8,cortexa9,cortexm4") ++ (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa7,cortexa8,cortexa9,cortexm4") + (eq_attr "tune_cortexr4" "no")) + (const_string "yes") + (const_string "no")))) +@@ -538,6 +565,7 @@ + (include "fmp626.md") + (include "fa726te.md") + (include "cortex-a5.md") ++(include "cortex-a7.md") + (include "cortex-a8.md") + (include "cortex-a9.md") + (include "cortex-a15.md") +@@ -563,7 +591,7 @@ [(parallel [(set (match_operand:DI 0 "s_register_operand" "") (plus:DI (match_operand:DI 1 "s_register_operand" "") @@ -48609,7 +52171,7 @@ (clobber (reg:CC CC_REGNUM))])] "TARGET_EITHER" " -@@ -599,9 +607,9 @@ +@@ -599,9 +627,9 @@ ) (define_insn_and_split "*arm_adddi3" @@ -48622,7 +52184,7 @@ (clobber (reg:CC CC_REGNUM))] "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) && !TARGET_NEON" "#" -@@ -619,7 +627,7 @@ +@@ -619,7 +647,7 @@ operands[0] = gen_lowpart (SImode, operands[0]); operands[4] = gen_highpart (SImode, operands[1]); operands[1] = gen_lowpart (SImode, operands[1]); @@ -48631,7 +52193,146 @@ operands[2] = gen_lowpart (SImode, operands[2]); }" [(set_attr "conds" "clob") -@@ -969,22 +977,26 @@ +@@ -746,7 +774,11 @@ + " + [(set_attr "length" "4,4,4,4,4,4,4,4,4,16") + (set_attr "predicable" "yes") +- (set_attr "arch" "*,*,*,t2,t2,*,*,t2,t2,*")] ++ (set_attr "arch" "*,*,*,t2,t2,*,*,t2,t2,*") ++ (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") ++ (const_string "simple_alu_imm") ++ (const_string "alu_reg"))) ++ ] + ) + + (define_insn_and_split "*thumb1_addsi3" +@@ -815,30 +847,35 @@ + (define_insn "addsi3_compare0" + [(set (reg:CC_NOOV CC_REGNUM) + (compare:CC_NOOV +- (plus:SI (match_operand:SI 1 "s_register_operand" "r, r") +- (match_operand:SI 2 "arm_add_operand" "rI,L")) ++ (plus:SI (match_operand:SI 1 "s_register_operand" "r, r,r") ++ (match_operand:SI 2 "arm_add_operand" "I,L,r")) + (const_int 0))) +- (set (match_operand:SI 0 "s_register_operand" "=r,r") ++ (set (match_operand:SI 0 "s_register_operand" "=r,r,r") + (plus:SI (match_dup 1) (match_dup 2)))] + "TARGET_ARM" + "@ + add%.\\t%0, %1, %2 +- sub%.\\t%0, %1, #%n2" +- [(set_attr "conds" "set")] ++ sub%.\\t%0, %1, #%n2 ++ add%.\\t%0, %1, %2" ++ [(set_attr "conds" "set") ++ (set_attr "type" "simple_alu_imm, simple_alu_imm, *")] + ) + + (define_insn "*addsi3_compare0_scratch" + [(set (reg:CC_NOOV CC_REGNUM) + (compare:CC_NOOV +- (plus:SI (match_operand:SI 0 "s_register_operand" "r, r") +- (match_operand:SI 1 "arm_add_operand" "rI,L")) ++ (plus:SI (match_operand:SI 0 "s_register_operand" "r, r, r") ++ (match_operand:SI 1 "arm_add_operand" "I,L, r")) + (const_int 0)))] + "TARGET_ARM" + "@ + cmn%?\\t%0, %1 +- cmp%?\\t%0, #%n1" ++ cmp%?\\t%0, #%n1 ++ cmn%?\\t%0, %1" + [(set_attr "conds" "set") +- (set_attr "predicable" "yes")] ++ (set_attr "predicable" "yes") ++ (set_attr "type" "simple_alu_imm, simple_alu_imm, *") ++ ] + ) + + (define_insn "*compare_negsi_si" +@@ -913,78 +950,90 @@ + (define_insn "*addsi3_compare_op1" + [(set (reg:CC_C CC_REGNUM) + (compare:CC_C +- (plus:SI (match_operand:SI 1 "s_register_operand" "r,r") +- (match_operand:SI 2 "arm_add_operand" "rI,L")) ++ (plus:SI (match_operand:SI 1 "s_register_operand" "r,r,r") ++ (match_operand:SI 2 "arm_add_operand" "I,L,r")) + (match_dup 1))) +- (set (match_operand:SI 0 "s_register_operand" "=r,r") ++ (set (match_operand:SI 0 "s_register_operand" "=r,r,r") + (plus:SI (match_dup 1) (match_dup 2)))] + "TARGET_32BIT" + "@ + add%.\\t%0, %1, %2 +- sub%.\\t%0, %1, #%n2" +- [(set_attr "conds" "set")] ++ sub%.\\t%0, %1, #%n2 ++ add%.\\t%0, %1, %2" ++ [(set_attr "conds" "set") ++ (set_attr "type" "simple_alu_imm,simple_alu_imm,*")] + ) + + (define_insn "*addsi3_compare_op2" + [(set (reg:CC_C CC_REGNUM) + (compare:CC_C +- (plus:SI (match_operand:SI 1 "s_register_operand" "r,r") +- (match_operand:SI 2 "arm_add_operand" "rI,L")) ++ (plus:SI (match_operand:SI 1 "s_register_operand" "r,r,r") ++ (match_operand:SI 2 "arm_add_operand" "I,L,r")) + (match_dup 2))) +- (set (match_operand:SI 0 "s_register_operand" "=r,r") ++ (set (match_operand:SI 0 "s_register_operand" "=r,r,r") + (plus:SI (match_dup 1) (match_dup 2)))] + "TARGET_32BIT" + "@ + add%.\\t%0, %1, %2 ++ add%.\\t%0, %1, %2 + sub%.\\t%0, %1, #%n2" +- [(set_attr "conds" "set")] ++ [(set_attr "conds" "set") ++ (set_attr "type" "simple_alu_imm,simple_alu_imm,*")] + ) + + (define_insn "*compare_addsi2_op0" + [(set (reg:CC_C CC_REGNUM) + (compare:CC_C +- (plus:SI (match_operand:SI 0 "s_register_operand" "r,r") +- (match_operand:SI 1 "arm_add_operand" "rI,L")) ++ (plus:SI (match_operand:SI 0 "s_register_operand" "r,r,r") ++ (match_operand:SI 1 "arm_add_operand" "I,L,r")) + (match_dup 0)))] + "TARGET_32BIT" + "@ + cmn%?\\t%0, %1 +- cmp%?\\t%0, #%n1" ++ cmp%?\\t%0, #%n1 ++ cmn%?\\t%0, %1" + [(set_attr "conds" "set") +- (set_attr "predicable" "yes")] ++ (set_attr "predicable" "yes") ++ (set_attr "type" "simple_alu_imm,simple_alu_imm,*")] + ) + + (define_insn "*compare_addsi2_op1" + [(set (reg:CC_C CC_REGNUM) + (compare:CC_C +- (plus:SI (match_operand:SI 0 "s_register_operand" "r,r") +- (match_operand:SI 1 "arm_add_operand" "rI,L")) ++ (plus:SI (match_operand:SI 0 "s_register_operand" "r,r,r") ++ (match_operand:SI 1 "arm_add_operand" "I,L,r")) + (match_dup 1)))] + "TARGET_32BIT" + "@ + cmn%?\\t%0, %1 +- cmp%?\\t%0, #%n1" ++ cmp%?\\t%0, #%n1 ++ cmn%?\\t%0, %1" + [(set_attr "conds" "set") +- (set_attr "predicable" "yes")] ++ (set_attr "predicable" "yes") ++ (set_attr "type" "simple_alu_imm,simple_alu_imm,*")] ) (define_insn "*addsi3_carryin_" @@ -48666,7 +52367,320 @@ [(set_attr "conds" "use")] ) -@@ -3446,6 +3458,60 @@ +@@ -1214,14 +1263,15 @@ + + ; ??? Check Thumb-2 split length + (define_insn_and_split "*arm_subsi3_insn" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r,rk,r") +- (minus:SI (match_operand:SI 1 "reg_or_int_operand" "rI,r,k,?n") +- (match_operand:SI 2 "reg_or_int_operand" "r,rI,r, r")))] ++ [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,rk,r") ++ (minus:SI (match_operand:SI 1 "reg_or_int_operand" "rI,r,r,k,?n") ++ (match_operand:SI 2 "reg_or_int_operand" "r,I,r,r, r")))] + "TARGET_32BIT" + "@ + rsb%?\\t%0, %2, %1 + sub%?\\t%0, %1, %2 + sub%?\\t%0, %1, %2 ++ sub%?\\t%0, %1, %2 + #" + "&& (GET_CODE (operands[1]) == CONST_INT + && !const_ok_for_arm (INTVAL (operands[1])))" +@@ -1231,8 +1281,9 @@ + INTVAL (operands[1]), operands[0], operands[2], 0); + DONE; + " +- [(set_attr "length" "4,4,4,16") +- (set_attr "predicable" "yes")] ++ [(set_attr "length" "4,4,4,4,16") ++ (set_attr "predicable" "yes") ++ (set_attr "type" "*,simple_alu_imm,*,*,*")] + ) + + (define_peephole2 +@@ -1251,29 +1302,33 @@ + (define_insn "*subsi3_compare0" + [(set (reg:CC_NOOV CC_REGNUM) + (compare:CC_NOOV +- (minus:SI (match_operand:SI 1 "arm_rhs_operand" "r,I") +- (match_operand:SI 2 "arm_rhs_operand" "rI,r")) ++ (minus:SI (match_operand:SI 1 "arm_rhs_operand" "r,r,I") ++ (match_operand:SI 2 "arm_rhs_operand" "I,r,r")) + (const_int 0))) +- (set (match_operand:SI 0 "s_register_operand" "=r,r") ++ (set (match_operand:SI 0 "s_register_operand" "=r,r,r") + (minus:SI (match_dup 1) (match_dup 2)))] + "TARGET_32BIT" + "@ + sub%.\\t%0, %1, %2 ++ sub%.\\t%0, %1, %2 + rsb%.\\t%0, %2, %1" +- [(set_attr "conds" "set")] ++ [(set_attr "conds" "set") ++ (set_attr "type" "simple_alu_imm,*,*")] + ) + + (define_insn "*subsi3_compare" + [(set (reg:CC CC_REGNUM) +- (compare:CC (match_operand:SI 1 "arm_rhs_operand" "r,I") +- (match_operand:SI 2 "arm_rhs_operand" "rI,r"))) +- (set (match_operand:SI 0 "s_register_operand" "=r,r") ++ (compare:CC (match_operand:SI 1 "arm_rhs_operand" "r,r,I") ++ (match_operand:SI 2 "arm_rhs_operand" "I,r,r"))) ++ (set (match_operand:SI 0 "s_register_operand" "=r,r,r") + (minus:SI (match_dup 1) (match_dup 2)))] + "TARGET_32BIT" + "@ + sub%.\\t%0, %1, %2 ++ sub%.\\t%0, %1, %2 + rsb%.\\t%0, %2, %1" +- [(set_attr "conds" "set")] ++ [(set_attr "conds" "set") ++ (set_attr "type" "simple_alu_imm,*,*")] + ) + + (define_expand "decscc" +@@ -1295,7 +1350,8 @@ + sub%d2\\t%0, %1, #1 + mov%D2\\t%0, %1\;sub%d2\\t%0, %1, #1" + [(set_attr "conds" "use") +- (set_attr "length" "*,8")] ++ (set_attr "length" "*,8") ++ (set_attr "type" "simple_alu_imm,*")] + ) + + (define_expand "subsf3" +@@ -2187,13 +2243,14 @@ + + ; ??? Check split length for Thumb-2 + (define_insn_and_split "*arm_andsi3_insn" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") +- (and:SI (match_operand:SI 1 "s_register_operand" "r,r,r") +- (match_operand:SI 2 "reg_or_int_operand" "rI,K,?n")))] ++ [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r") ++ (and:SI (match_operand:SI 1 "s_register_operand" "r,r,r,r") ++ (match_operand:SI 2 "reg_or_int_operand" "I,K,r,?n")))] + "TARGET_32BIT" + "@ + and%?\\t%0, %1, %2 + bic%?\\t%0, %1, #%B2 ++ and%?\\t%0, %1, %2 + #" + "TARGET_32BIT + && GET_CODE (operands[2]) == CONST_INT +@@ -2205,8 +2262,9 @@ + INTVAL (operands[2]), operands[0], operands[1], 0); + DONE; + " +- [(set_attr "length" "4,4,16") +- (set_attr "predicable" "yes")] ++ [(set_attr "length" "4,4,4,16") ++ (set_attr "predicable" "yes") ++ (set_attr "type" "simple_alu_imm,simple_alu_imm,*,simple_alu_imm")] + ) + + (define_insn "*thumb1_andsi3_insn" +@@ -2216,35 +2274,40 @@ + "TARGET_THUMB1" + "and\\t%0, %2" + [(set_attr "length" "2") ++ (set_attr "type" "simple_alu_imm") + (set_attr "conds" "set")]) + + (define_insn "*andsi3_compare0" + [(set (reg:CC_NOOV CC_REGNUM) + (compare:CC_NOOV +- (and:SI (match_operand:SI 1 "s_register_operand" "r,r") +- (match_operand:SI 2 "arm_not_operand" "rI,K")) ++ (and:SI (match_operand:SI 1 "s_register_operand" "r,r,r") ++ (match_operand:SI 2 "arm_not_operand" "I,K,r")) + (const_int 0))) +- (set (match_operand:SI 0 "s_register_operand" "=r,r") ++ (set (match_operand:SI 0 "s_register_operand" "=r,r,r") + (and:SI (match_dup 1) (match_dup 2)))] + "TARGET_32BIT" + "@ + and%.\\t%0, %1, %2 +- bic%.\\t%0, %1, #%B2" +- [(set_attr "conds" "set")] ++ bic%.\\t%0, %1, #%B2 ++ and%.\\t%0, %1, %2" ++ [(set_attr "conds" "set") ++ (set_attr "type" "simple_alu_imm,simple_alu_imm,*")] + ) + + (define_insn "*andsi3_compare0_scratch" + [(set (reg:CC_NOOV CC_REGNUM) + (compare:CC_NOOV +- (and:SI (match_operand:SI 0 "s_register_operand" "r,r") +- (match_operand:SI 1 "arm_not_operand" "rI,K")) ++ (and:SI (match_operand:SI 0 "s_register_operand" "r,r,r") ++ (match_operand:SI 1 "arm_not_operand" "I,K,r")) + (const_int 0))) +- (clobber (match_scratch:SI 2 "=X,r"))] ++ (clobber (match_scratch:SI 2 "=X,r,X"))] + "TARGET_32BIT" + "@ + tst%?\\t%0, %1 +- bic%.\\t%2, %0, #%B1" +- [(set_attr "conds" "set")] ++ bic%.\\t%2, %0, #%B1 ++ tst%?\\t%0, %1" ++ [(set_attr "conds" "set") ++ (set_attr "type" "simple_alu_imm,simple_alu_imm,*")] + ) + + (define_insn "*zeroextractsi_compare0_scratch" +@@ -2266,7 +2329,8 @@ + return \"\"; + " + [(set_attr "conds" "set") +- (set_attr "predicable" "yes")] ++ (set_attr "predicable" "yes") ++ (set_attr "type" "simple_alu_imm")] + ) + + (define_insn_and_split "*ne_zeroextractsi" +@@ -2913,13 +2977,14 @@ + ) + + (define_insn_and_split "*iorsi3_insn" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") +- (ior:SI (match_operand:SI 1 "s_register_operand" "%r,r,r") +- (match_operand:SI 2 "reg_or_int_operand" "rI,K,?n")))] ++ [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r") ++ (ior:SI (match_operand:SI 1 "s_register_operand" "%r,r,r,r") ++ (match_operand:SI 2 "reg_or_int_operand" "I,K,r,?n")))] + "TARGET_32BIT" + "@ + orr%?\\t%0, %1, %2 + orn%?\\t%0, %1, #%B2 ++ orr%?\\t%0, %1, %2 + #" + "TARGET_32BIT + && GET_CODE (operands[2]) == CONST_INT +@@ -2931,9 +2996,11 @@ + INTVAL (operands[2]), operands[0], operands[1], 0); + DONE; + } +- [(set_attr "length" "4,4,16") +- (set_attr "arch" "32,t2,32") +- (set_attr "predicable" "yes")]) ++ [(set_attr "length" "4,4,4,16") ++ (set_attr "arch" "32,t2,32,32") ++ (set_attr "predicable" "yes") ++ (set_attr "type" "simple_alu_imm,simple_alu_imm,*,*")] ++) + + (define_insn "*thumb1_iorsi3_insn" + [(set (match_operand:SI 0 "register_operand" "=l") +@@ -2959,25 +3026,27 @@ + + (define_insn "*iorsi3_compare0" + [(set (reg:CC_NOOV CC_REGNUM) +- (compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r") +- (match_operand:SI 2 "arm_rhs_operand" "rI")) ++ (compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r,r") ++ (match_operand:SI 2 "arm_rhs_operand" "I,r")) + (const_int 0))) +- (set (match_operand:SI 0 "s_register_operand" "=r") ++ (set (match_operand:SI 0 "s_register_operand" "=r,r") + (ior:SI (match_dup 1) (match_dup 2)))] + "TARGET_32BIT" + "orr%.\\t%0, %1, %2" +- [(set_attr "conds" "set")] ++ [(set_attr "conds" "set") ++ (set_attr "type" "simple_alu_imm,*")] + ) + + (define_insn "*iorsi3_compare0_scratch" + [(set (reg:CC_NOOV CC_REGNUM) +- (compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r") +- (match_operand:SI 2 "arm_rhs_operand" "rI")) ++ (compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r,r") ++ (match_operand:SI 2 "arm_rhs_operand" "I,r")) + (const_int 0))) +- (clobber (match_scratch:SI 0 "=r"))] ++ (clobber (match_scratch:SI 0 "=r,r"))] + "TARGET_32BIT" + "orr%.\\t%0, %1, %2" +- [(set_attr "conds" "set")] ++ [(set_attr "conds" "set") ++ (set_attr "type" "simple_alu_imm, *")] + ) + + (define_expand "xordi3" +@@ -3051,12 +3120,13 @@ + ) + + (define_insn_and_split "*arm_xorsi3" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r") +- (xor:SI (match_operand:SI 1 "s_register_operand" "%r,r") +- (match_operand:SI 2 "reg_or_int_operand" "rI,?n")))] ++ [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") ++ (xor:SI (match_operand:SI 1 "s_register_operand" "%r,r,r") ++ (match_operand:SI 2 "reg_or_int_operand" "I,r,?n")))] + "TARGET_32BIT" + "@ + eor%?\\t%0, %1, %2 ++ eor%?\\t%0, %1, %2 + #" + "TARGET_32BIT + && GET_CODE (operands[2]) == CONST_INT +@@ -3067,8 +3137,9 @@ + INTVAL (operands[2]), operands[0], operands[1], 0); + DONE; + } +- [(set_attr "length" "4,16") +- (set_attr "predicable" "yes")] ++ [(set_attr "length" "4,4,16") ++ (set_attr "predicable" "yes") ++ (set_attr "type" "simple_alu_imm,*,*")] + ) + + (define_insn "*thumb1_xorsi3_insn" +@@ -3078,28 +3149,32 @@ + "TARGET_THUMB1" + "eor\\t%0, %2" + [(set_attr "length" "2") +- (set_attr "conds" "set")]) ++ (set_attr "conds" "set") ++ (set_attr "type" "simple_alu_imm")] ++) + + (define_insn "*xorsi3_compare0" + [(set (reg:CC_NOOV CC_REGNUM) +- (compare:CC_NOOV (xor:SI (match_operand:SI 1 "s_register_operand" "r") +- (match_operand:SI 2 "arm_rhs_operand" "rI")) ++ (compare:CC_NOOV (xor:SI (match_operand:SI 1 "s_register_operand" "r,r") ++ (match_operand:SI 2 "arm_rhs_operand" "I,r")) + (const_int 0))) +- (set (match_operand:SI 0 "s_register_operand" "=r") ++ (set (match_operand:SI 0 "s_register_operand" "=r,r") + (xor:SI (match_dup 1) (match_dup 2)))] + "TARGET_32BIT" + "eor%.\\t%0, %1, %2" +- [(set_attr "conds" "set")] ++ [(set_attr "conds" "set") ++ (set_attr "type" "simple_alu_imm,*")] + ) + + (define_insn "*xorsi3_compare0_scratch" + [(set (reg:CC_NOOV CC_REGNUM) +- (compare:CC_NOOV (xor:SI (match_operand:SI 0 "s_register_operand" "r") +- (match_operand:SI 1 "arm_rhs_operand" "rI")) ++ (compare:CC_NOOV (xor:SI (match_operand:SI 0 "s_register_operand" "r,r") ++ (match_operand:SI 1 "arm_rhs_operand" "I,r")) + (const_int 0)))] + "TARGET_32BIT" + "teq%?\\t%0, %1" +- [(set_attr "conds" "set")] ++ [(set_attr "conds" "set") ++ (set_attr "type" "simple_alu_imm, *")] + ) + + ; By splitting (IOR (AND (NOT A) (NOT B)) C) as D = AND (IOR A B) (NOT C), +@@ -3446,30 +3521,114 @@ (const_int 12)))] ) @@ -48727,17 +52741,34 @@ ;; Shift and rotation insns -@@ -3455,21 +3521,37 @@ - (match_operand:SI 2 "reg_or_int_operand" "")))] + (define_expand "ashldi3" + [(set (match_operand:DI 0 "s_register_operand" "") + (ashift:DI (match_operand:DI 1 "s_register_operand" "") +- (match_operand:SI 2 "reg_or_int_operand" "")))] ++ (match_operand:SI 2 "general_operand" "")))] "TARGET_32BIT" " - if (GET_CODE (operands[2]) == CONST_INT) ++ if (TARGET_NEON) ++ { ++ /* Delay the decision whether to use NEON or core-regs until ++ register allocation. */ ++ emit_insn (gen_ashldi3_neon (operands[0], operands[1], operands[2])); ++ DONE; ++ } ++ else + { +- if ((HOST_WIDE_INT) INTVAL (operands[2]) == 1) ++ /* Only the NEON case can handle in-memory shift counts. */ ++ if (!reg_or_int_operand (operands[2], SImode)) ++ operands[2] = force_reg (SImode, operands[2]); ++ } ++ + if (!CONST_INT_P (operands[2]) + && (TARGET_REALLY_IWMMXT || (TARGET_HARD_FLOAT && TARGET_MAVERICK))) + ; /* No special preparation statements; expand pattern as above. */ + else - { -- if ((HOST_WIDE_INT) INTVAL (operands[2]) == 1) ++ { + rtx scratch1, scratch2; + + if (CONST_INT_P (operands[2]) @@ -48774,11 +52805,19 @@ " ) -@@ -3514,21 +3596,37 @@ +@@ -3514,21 +3673,45 @@ (match_operand:SI 2 "reg_or_int_operand" "")))] "TARGET_32BIT" " - if (GET_CODE (operands[2]) == CONST_INT) ++ if (TARGET_NEON) ++ { ++ /* Delay the decision whether to use NEON or core-regs until ++ register allocation. */ ++ emit_insn (gen_ashrdi3_neon (operands[0], operands[1], operands[2])); ++ DONE; ++ } ++ + if (!CONST_INT_P (operands[2]) + && (TARGET_REALLY_IWMMXT || (TARGET_HARD_FLOAT && TARGET_MAVERICK))) + ; /* No special preparation statements; expand pattern as above. */ @@ -48821,11 +52860,19 @@ " ) -@@ -3571,21 +3669,37 @@ +@@ -3571,21 +3754,45 @@ (match_operand:SI 2 "reg_or_int_operand" "")))] "TARGET_32BIT" " - if (GET_CODE (operands[2]) == CONST_INT) ++ if (TARGET_NEON) ++ { ++ /* Delay the decision whether to use NEON or core-regs until ++ register allocation. */ ++ emit_insn (gen_lshrdi3_neon (operands[0], operands[1], operands[2])); ++ DONE; ++ } ++ + if (!CONST_INT_P (operands[2]) + && (TARGET_REALLY_IWMMXT || (TARGET_HARD_FLOAT && TARGET_MAVERICK))) + ; /* No special preparation statements; expand pattern as above. */ @@ -48868,7 +52915,7 @@ " ) -@@ -4037,7 +4151,13 @@ +@@ -4037,7 +4244,13 @@ (neg:DI (match_operand:DI 1 "s_register_operand" ""))) (clobber (reg:CC CC_REGNUM))])] "TARGET_EITHER" @@ -48883,7 +52930,25 @@ ) ;; The constraints here are to prevent a *partial* overlap (where %Q0 == %R1). -@@ -4196,11 +4316,16 @@ +@@ -4125,7 +4338,7 @@ + eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31" + [(set_attr "conds" "clob,*") + (set_attr "shift" "1") +- ;; predicable can't be set based on the variant, so left as no ++ (set_attr "predicable" "no, yes") + (set_attr "length" "8")] + ) + +@@ -4153,7 +4366,7 @@ + eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31" + [(set_attr "conds" "clob,*") + (set_attr "shift" "1") +- ;; predicable can't be set based on the variant, so left as no ++ (set_attr "predicable" "no, yes") + (set_attr "length" "8")] + ) + +@@ -4196,11 +4409,16 @@ "") (define_insn_and_split "one_cmpldi2" @@ -48904,7 +52969,7 @@ [(set (match_dup 0) (not:SI (match_dup 1))) (set (match_dup 2) (not:SI (match_dup 3)))] " -@@ -4210,8 +4335,10 @@ +@@ -4210,8 +4428,10 @@ operands[3] = gen_highpart (SImode, operands[1]); operands[1] = gen_lowpart (SImode, operands[1]); }" @@ -48913,11 +52978,245 @@ + [(set_attr "length" "*,8,8,*") + (set_attr "predicable" "no,yes,yes,no") + (set_attr "neon_type" "neon_int_1,*,*,neon_int_1") -+ (set_attr "arch" "neon_nota8,*,*,neon_onlya8")] ++ (set_attr "arch" "neon_for_64bits,*,*,avoid_neon_for_64bits")] ) (define_expand "one_cmplsi2" -@@ -7659,7 +7786,7 @@ +@@ -4399,33 +4619,36 @@ + ;; Zero and sign extension instructions. + + (define_insn "zero_extenddi2" +- [(set (match_operand:DI 0 "s_register_operand" "=r") ++ [(set (match_operand:DI 0 "s_register_operand" "=w,r,?r") + (zero_extend:DI (match_operand:QHSI 1 "" + "")))] + "TARGET_32BIT " + "#" +- [(set_attr "length" "8") ++ [(set_attr "length" "8,4,8") + (set_attr "ce_count" "2") + (set_attr "predicable" "yes")] + ) + + (define_insn "extenddi2" +- [(set (match_operand:DI 0 "s_register_operand" "=r") ++ [(set (match_operand:DI 0 "s_register_operand" "=w,r,?r,?r") + (sign_extend:DI (match_operand:QHSI 1 "" + "")))] + "TARGET_32BIT " + "#" +- [(set_attr "length" "8") ++ [(set_attr "length" "8,4,8,8") + (set_attr "ce_count" "2") + (set_attr "shift" "1") +- (set_attr "predicable" "yes")] ++ (set_attr "predicable" "yes") ++ (set_attr "arch" "*,*,a,t")] + ) + + ;; Splits for all extensions to DImode + (define_split + [(set (match_operand:DI 0 "s_register_operand" "") + (zero_extend:DI (match_operand 1 "nonimmediate_operand" "")))] +- "TARGET_32BIT" ++ "TARGET_32BIT && (!TARGET_NEON ++ || (reload_completed ++ && !(IS_VFP_REGNUM (REGNO (operands[0])))))" + [(set (match_dup 0) (match_dup 1))] + { + rtx lo_part = gen_lowpart (SImode, operands[0]); +@@ -4451,7 +4674,9 @@ + (define_split + [(set (match_operand:DI 0 "s_register_operand" "") + (sign_extend:DI (match_operand 1 "nonimmediate_operand" "")))] +- "TARGET_32BIT" ++ "TARGET_32BIT && (!TARGET_NEON ++ || (reload_completed ++ && !(IS_VFP_REGNUM (REGNO (operands[0])))))" + [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 31)))] + { + rtx lo_part = gen_lowpart (SImode, operands[0]); +@@ -4544,7 +4769,7 @@ + [(if_then_else (eq_attr "is_arch6" "yes") + (const_int 2) (const_int 4)) + (const_int 4)]) +- (set_attr "type" "alu_shift,load_byte")] ++ (set_attr "type" "simple_alu_shift, load_byte")] + ) + + (define_insn "*arm_zero_extendhisi2" +@@ -4565,8 +4790,8 @@ + "@ + uxth%?\\t%0, %1 + ldr%(h%)\\t%0, %1" +- [(set_attr "type" "alu_shift,load_byte") +- (set_attr "predicable" "yes")] ++ [(set_attr "predicable" "yes") ++ (set_attr "type" "simple_alu_shift,load_byte")] + ) + + (define_insn "*arm_zero_extendhisi2addsi" +@@ -4636,7 +4861,7 @@ + uxtb\\t%0, %1 + ldrb\\t%0, %1" + [(set_attr "length" "2") +- (set_attr "type" "alu_shift,load_byte")] ++ (set_attr "type" "simple_alu_shift,load_byte")] + ) + + (define_insn "*arm_zero_extendqisi2" +@@ -4658,7 +4883,7 @@ + "@ + uxtb%(%)\\t%0, %1 + ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2" +- [(set_attr "type" "alu_shift,load_byte") ++ [(set_attr "type" "simple_alu_shift,load_byte") + (set_attr "predicable" "yes")] + ) + +@@ -4832,7 +5057,7 @@ + [(if_then_else (eq_attr "is_arch6" "yes") + (const_int 2) (const_int 4)) + (const_int 4)]) +- (set_attr "type" "alu_shift,load_byte") ++ (set_attr "type" "simple_alu_shift,load_byte") + (set_attr "pool_range" "*,1020")] + ) + +@@ -4904,7 +5129,7 @@ + "@ + sxth%?\\t%0, %1 + ldr%(sh%)\\t%0, %1" +- [(set_attr "type" "alu_shift,load_byte") ++ [(set_attr "type" "simple_alu_shift,load_byte") + (set_attr "predicable" "yes") + (set_attr "pool_range" "*,256") + (set_attr "neg_pool_range" "*,244")] +@@ -5004,7 +5229,7 @@ + "@ + sxtb%?\\t%0, %1 + ldr%(sb%)\\t%0, %1" +- [(set_attr "type" "alu_shift,load_byte") ++ [(set_attr "type" "simple_alu_shift,load_byte") + (set_attr "predicable" "yes") + (set_attr "pool_range" "*,256") + (set_attr "neg_pool_range" "*,244")] +@@ -5117,7 +5342,7 @@ + (const_int 2) + (if_then_else (eq_attr "is_arch6" "yes") + (const_int 4) (const_int 6))]) +- (set_attr "type" "alu_shift,load_byte,load_byte")] ++ (set_attr "type" "simple_alu_shift,load_byte,load_byte")] + ) + + (define_expand "extendsfdf2" +@@ -5500,7 +5725,7 @@ + movw%?\\t%0, %1 + ldr%?\\t%0, %1 + str%?\\t%1, %0" +- [(set_attr "type" "*,*,*,*,load1,store1") ++ [(set_attr "type" "*,simple_alu_imm,simple_alu_imm,simple_alu_imm,load1,store1") + (set_attr "insn" "mov,mov,mvn,mov,*,*") + (set_attr "predicable" "yes") + (set_attr "pool_range" "*,*,*,*,4096,*") +@@ -5766,7 +5991,8 @@ + "@ + cmp%?\\t%0, #0 + sub%.\\t%0, %1, #0" +- [(set_attr "conds" "set")] ++ [(set_attr "conds" "set") ++ (set_attr "type" "simple_alu_imm,simple_alu_imm")] + ) + + ;; Subroutine to store a half word from a register into memory. +@@ -6179,22 +6405,30 @@ + mvn%?\\t%0, #%B1\\t%@ movhi + str%(h%)\\t%1, %0\\t%@ movhi + ldr%(h%)\\t%0, %1\\t%@ movhi" +- [(set_attr "type" "*,*,store1,load1") +- (set_attr "predicable" "yes") ++ [(set_attr "predicable" "yes") + (set_attr "insn" "mov,mvn,*,*") + (set_attr "pool_range" "*,*,*,256") +- (set_attr "neg_pool_range" "*,*,*,244")] ++ (set_attr "neg_pool_range" "*,*,*,244") ++ (set_attr_alternative "type" ++ [(if_then_else (match_operand 1 "const_int_operand" "") ++ (const_string "simple_alu_imm" ) ++ (const_string "*")) ++ (const_string "simple_alu_imm") ++ (const_string "store1") ++ (const_string "load1")])] + ) + + (define_insn "*movhi_bytes" +- [(set (match_operand:HI 0 "s_register_operand" "=r,r") +- (match_operand:HI 1 "arm_rhs_operand" "rI,K"))] ++ [(set (match_operand:HI 0 "s_register_operand" "=r,r,r") ++ (match_operand:HI 1 "arm_rhs_operand" "I,r,K"))] + "TARGET_ARM" + "@ + mov%?\\t%0, %1\\t%@ movhi ++ mov%?\\t%0, %1\\t%@ movhi + mvn%?\\t%0, #%B1\\t%@ movhi" + [(set_attr "predicable" "yes") +- (set_attr "insn" "mov,mvn")] ++ (set_attr "insn" "mov, mov,mvn") ++ (set_attr "type" "simple_alu_imm,*,simple_alu_imm")] + ) + + (define_expand "thumb_movhi_clobber" +@@ -6319,23 +6553,24 @@ + + + (define_insn "*arm_movqi_insn" +- [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,l,Uu,r,m") +- (match_operand:QI 1 "general_operand" "rI,K,Uu,l,m,r"))] ++ [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,l,Uu,r,m") ++ (match_operand:QI 1 "general_operand" "r,I,K,Uu,l,m,r"))] + "TARGET_32BIT + && ( register_operand (operands[0], QImode) + || register_operand (operands[1], QImode))" + "@ + mov%?\\t%0, %1 ++ mov%?\\t%0, %1 + mvn%?\\t%0, #%B1 + ldr%(b%)\\t%0, %1 + str%(b%)\\t%1, %0 + ldr%(b%)\\t%0, %1 + str%(b%)\\t%1, %0" +- [(set_attr "type" "*,*,load1,store1,load1,store1") +- (set_attr "insn" "mov,mvn,*,*,*,*") ++ [(set_attr "type" "*,simple_alu_imm,simple_alu_imm,load1, store1, load1, store1") ++ (set_attr "insn" "mov,mov,mvn,*,*,*,*") + (set_attr "predicable" "yes") +- (set_attr "arch" "any,any,t2,t2,any,any") +- (set_attr "length" "4,4,2,2,4,4")] ++ (set_attr "arch" "any,any,any,t2,t2,any,any") ++ (set_attr "length" "4,4,4,2,2,4,4")] + ) + + (define_insn "*thumb1_movqi_insn" +@@ -6352,7 +6587,7 @@ + mov\\t%0, %1 + mov\\t%0, %1" + [(set_attr "length" "2") +- (set_attr "type" "*,load1,store1,*,*,*") ++ (set_attr "type" "simple_alu_imm,load1,store1,*,*,simple_alu_imm") + (set_attr "insn" "*,*,*,mov,mov,mov") + (set_attr "pool_range" "*,32,*,*,*,*") + (set_attr "conds" "clob,nocond,nocond,nocond,nocond,clob")]) +@@ -7499,7 +7734,8 @@ + [(set_attr "conds" "set") + (set_attr "arch" "t2,t2,any,any") + (set_attr "length" "2,2,4,4") +- (set_attr "predicable" "yes")] ++ (set_attr "predicable" "yes") ++ (set_attr "type" "*,*,*,simple_alu_imm")] + ) + + (define_insn "*cmpsi_shiftsi" +@@ -7655,7 +7891,7 @@ ;; Patterns to match conditional branch insns. ;; @@ -48926,6 +53225,180 @@ [(set (pc) (if_then_else (match_operator 1 "arm_comparison_operator" [(match_operand 2 "cc_register" "") (const_int 0)]) +@@ -8111,7 +8347,20 @@ + mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2" + [(set_attr "length" "4,4,4,4,8,8,8,8") + (set_attr "conds" "use") +- (set_attr "insn" "mov,mvn,mov,mvn,mov,mov,mvn,mvn")] ++ (set_attr "insn" "mov,mvn,mov,mvn,mov,mov,mvn,mvn") ++ (set_attr_alternative "type" ++ [(if_then_else (match_operand 2 "const_int_operand" "") ++ (const_string "simple_alu_imm") ++ (const_string "*")) ++ (const_string "simple_alu_imm") ++ (if_then_else (match_operand 1 "const_int_operand" "") ++ (const_string "simple_alu_imm") ++ (const_string "*")) ++ (const_string "simple_alu_imm") ++ (const_string "*") ++ (const_string "*") ++ (const_string "*") ++ (const_string "*")])] + ) + + (define_insn "*movsfcc_soft_insn" +@@ -9882,7 +10131,13 @@ + sub%d4\\t%0, %2, #%n3\;mov%D4\\t%0, %1" + [(set_attr "conds" "use") + (set_attr "length" "4,4,8,8") +- (set_attr "type" "*,*,*,*")] ++ (set_attr_alternative "type" ++ [(if_then_else (match_operand 3 "const_int_operand" "") ++ (const_string "simple_alu_imm" ) ++ (const_string "*")) ++ (const_string "simple_alu_imm") ++ (const_string "*") ++ (const_string "*")])] + ) + + (define_insn "*ifcompare_move_plus" +@@ -9918,7 +10173,13 @@ + sub%D4\\t%0, %2, #%n3\;mov%d4\\t%0, %1" + [(set_attr "conds" "use") + (set_attr "length" "4,4,8,8") +- (set_attr "type" "*,*,*,*")] ++ (set_attr_alternative "type" ++ [(if_then_else (match_operand 3 "const_int_operand" "") ++ (const_string "simple_alu_imm" ) ++ (const_string "*")) ++ (const_string "simple_alu_imm") ++ (const_string "*") ++ (const_string "*")])] + ) + + (define_insn "*ifcompare_arith_arith" +@@ -11225,20 +11486,15 @@ + ) + + (define_insn "*arm_rev" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (bswap:SI (match_operand:SI 1 "s_register_operand" "r")))] +- "TARGET_32BIT && arm_arch6" +- "rev%?\t%0, %1" +- [(set_attr "predicable" "yes") +- (set_attr "length" "4")] +-) +- +-(define_insn "*thumb1_rev" +- [(set (match_operand:SI 0 "s_register_operand" "=l") +- (bswap:SI (match_operand:SI 1 "s_register_operand" "l")))] +- "TARGET_THUMB1 && arm_arch6" +- "rev\t%0, %1" +- [(set_attr "length" "2")] ++ [(set (match_operand:SI 0 "s_register_operand" "=l,l,r") ++ (bswap:SI (match_operand:SI 1 "s_register_operand" "l,l,r")))] ++ "arm_arch6" ++ "@ ++ rev\t%0, %1 ++ rev%?\t%0, %1 ++ rev%?\t%0, %1" ++ [(set_attr "arch" "t1,t2,32") ++ (set_attr "length" "2,2,4")] + ) + + (define_expand "arm_legacy_rev" +@@ -11326,6 +11582,40 @@ + " + ) + ++;; bswap16 patterns: use revsh and rev16 instructions for the signed ++;; and unsigned variants, respectively. For rev16, expose ++;; byte-swapping in the lower 16 bits only. ++(define_insn "*arm_revsh" ++ [(set (match_operand:SI 0 "s_register_operand" "=l,l,r") ++ (sign_extend:SI (bswap:HI (match_operand:HI 1 "s_register_operand" "l,l,r"))))] ++ "arm_arch6" ++ "@ ++ revsh\t%0, %1 ++ revsh%?\t%0, %1 ++ revsh%?\t%0, %1" ++ [(set_attr "arch" "t1,t2,32") ++ (set_attr "length" "2,2,4")] ++) ++ ++(define_insn "*arm_rev16" ++ [(set (match_operand:HI 0 "s_register_operand" "=l,l,r") ++ (bswap:HI (match_operand:HI 1 "s_register_operand" "l,l,r")))] ++ "arm_arch6" ++ "@ ++ rev16\t%0, %1 ++ rev16%?\t%0, %1 ++ rev16%?\t%0, %1" ++ [(set_attr "arch" "t1,t2,32") ++ (set_attr "length" "2,2,4")] ++) ++ ++(define_expand "bswaphi2" ++ [(set (match_operand:HI 0 "s_register_operand" "=r") ++ (bswap:HI (match_operand:HI 1 "s_register_operand" "r")))] ++"arm_arch6" ++"" ++) ++ + ;; Load the load/store multiple patterns + (include "ldmstm.md") + ;; Load the FPA co-processor patterns +--- a/src/gcc/config/arm/arm_neon.h ++++ b/src/gcc/config/arm/arm_neon.h +@@ -1350,6 +1350,38 @@ + return (int64x2_t)__builtin_neon_vqdmlslv2si (__a, __b, __c, 1); + } + ++#ifdef __ARM_FEATURE_FMA ++__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) ++vfma_f32 (float32x2_t __a, float32x2_t __b, float32x2_t __c) ++{ ++ return (float32x2_t)__builtin_neon_vfmav2sf (__a, __b, __c, 3); ++} ++ ++#endif ++#ifdef __ARM_FEATURE_FMA ++__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) ++vfmaq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c) ++{ ++ return (float32x4_t)__builtin_neon_vfmav4sf (__a, __b, __c, 3); ++} ++ ++#endif ++#ifdef __ARM_FEATURE_FMA ++__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) ++vfms_f32 (float32x2_t __a, float32x2_t __b, float32x2_t __c) ++{ ++ return (float32x2_t)__builtin_neon_vfmsv2sf (__a, __b, __c, 3); ++} ++ ++#endif ++#ifdef __ARM_FEATURE_FMA ++__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) ++vfmsq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c) ++{ ++ return (float32x4_t)__builtin_neon_vfmsv4sf (__a, __b, __c, 3); ++} ++ ++#endif + __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) + vsub_s8 (int8x8_t __a, int8x8_t __b) + { +--- a/src/gcc/config/arm/arm.opt ++++ b/src/gcc/config/arm/arm.opt +@@ -267,3 +267,7 @@ + munaligned-access + Target Report Var(unaligned_access) Init(2) + Enable unaligned word and halfword accesses to packed data. ++ ++mneon-for-64bits ++Target Report RejectNegative Var(use_neon_for_64bits) Init(0) ++Use Neon to perform 64-bits operations rather than core registers. --- a/src/gcc/config/arm/arm-protos.h +++ b/src/gcc/config/arm/arm-protos.h @@ -49,6 +49,7 @@ @@ -48936,7 +53409,14 @@ extern int arm_split_constant (RTX_CODE, enum machine_mode, rtx, HOST_WIDE_INT, rtx, rtx, int); extern RTX_CODE arm_canonicalize_comparison (RTX_CODE, rtx *, rtx *); -@@ -107,6 +108,7 @@ +@@ -101,12 +102,14 @@ + extern int arm_no_early_alu_shift_dep (rtx, rtx); + extern int arm_no_early_alu_shift_value_dep (rtx, rtx); + extern int arm_no_early_mul_dep (rtx, rtx); ++extern int arm_mac_accumulator_is_result (rtx, rtx); + extern int arm_mac_accumulator_is_mul_result (rtx, rtx); + + extern int tls_mentioned_p (rtx); extern int symbol_mentioned_p (rtx); extern int label_mentioned_p (rtx); extern RTX_CODE minmax_code (rtx); @@ -48944,7 +53424,43 @@ extern int adjacent_mem_locations (rtx, rtx); extern bool gen_ldm_seq (rtx *, int, bool); extern bool gen_stm_seq (rtx *, int); -@@ -242,9 +244,14 @@ +@@ -222,6 +225,27 @@ + + extern void arm_order_regs_for_local_alloc (void); + ++/* Vectorizer cost model implementation. */ ++struct cpu_vec_costs { ++ const int scalar_stmt_cost; /* Cost of any scalar operation, excluding ++ load and store. */ ++ const int scalar_load_cost; /* Cost of scalar load. */ ++ const int scalar_store_cost; /* Cost of scalar store. */ ++ const int vec_stmt_cost; /* Cost of any vector operation, excluding ++ load, store, vector-to-scalar and ++ scalar-to-vector operation. */ ++ const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */ ++ const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */ ++ const int vec_align_load_cost; /* Cost of aligned vector load. */ ++ const int vec_unalign_load_cost; /* Cost of unaligned vector load. */ ++ const int vec_unalign_store_cost; /* Cost of unaligned vector load. */ ++ const int vec_store_cost; /* Cost of vector store. */ ++ const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer ++ cost model. */ ++ const int cond_not_taken_branch_cost;/* Cost of not taken branch for ++ vectorizer cost model. */ ++}; ++ + #ifdef RTX_CODE + /* This needs to be here because we need RTX_CODE and similar. */ + +@@ -238,13 +262,22 @@ + int l1_cache_line_size; + bool prefer_constant_pool; + int (*branch_cost) (bool, bool); ++ /* Prefer Neon for 64-bit bitops. */ ++ bool prefer_neon_for_64bits; ++ /* Vectorizer costs. */ ++ const struct cpu_vec_costs* vec_costs; + }; extern const struct tune_params *current_tune; extern int vfp3_const_double_for_fract_bits (rtx); @@ -48996,6 +53512,2075 @@ (match_test "TARGET_32BIT && imm_for_neon_mov_operand (op, GET_MODE (op))"))) +--- a/src/gcc/config/arm/cortex-a15.md ++++ b/src/gcc/config/arm/cortex-a15.md +@@ -24,7 +24,7 @@ + ;; The Cortex-A15 core is modelled as a triple issue pipeline that has + ;; the following dispatch units. + ;; 1. Two pipelines for simple integer operations: SX1, SX2 +-;; 2. Two pipelines for Neon and FP data-processing operations: CX1, CX2 ++;; 2. Individual units for Neon and FP operations as in cortex-a15-neon.md + ;; 3. One pipeline for branch operations: BX + ;; 4. One pipeline for integer multiply and divide operations: MX + ;; 5. Two pipelines for load and store operations: LS1, LS2 +@@ -44,7 +44,6 @@ + + ;; The main dispatch units + (define_cpu_unit "ca15_sx1, ca15_sx2" "cortex_a15") +-(define_cpu_unit "ca15_cx1, ca15_cx2" "cortex_a15") + (define_cpu_unit "ca15_ls1, ca15_ls2" "cortex_a15") + (define_cpu_unit "ca15_bx, ca15_mx" "cortex_a15") + +@@ -62,14 +61,14 @@ + ;; Simple ALU without shift + (define_insn_reservation "cortex_a15_alu" 2 + (and (eq_attr "tune" "cortexa15") +- (and (eq_attr "type" "alu") ++ (and (eq_attr "type" "alu_reg,simple_alu_imm") + (eq_attr "neon_type" "none"))) + "ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)") + + ;; ALU ops with immediate shift + (define_insn_reservation "cortex_a15_alu_shift" 3 + (and (eq_attr "tune" "cortexa15") +- (and (eq_attr "type" "alu_shift") ++ (and (eq_attr "type" "simple_alu_shift,alu_shift") + (eq_attr "neon_type" "none"))) + "ca15_issue1,(ca15_sx1,ca15_sx1+ca15_sx1_shf,ca15_sx1_alu)\ + |(ca15_sx2,ca15_sx2+ca15_sx2_shf,ca15_sx2_alu)") +@@ -129,20 +128,6 @@ + (eq_attr "neon_type" "none"))) + "ca15_issue1,ca15_bx") + +- +-;; We lie with calls. They take up all issue slots, and form a block in the +-;; pipeline. The result however is available the next cycle. +-;; +-;; Addition of new units requires this to be updated. +-(define_insn_reservation "cortex_a15_call" 1 +- (and (eq_attr "tune" "cortexa15") +- (and (eq_attr "type" "call") +- (eq_attr "neon_type" "none"))) +- "ca15_issue3,\ +- ca15_sx1+ca15_sx2+ca15_bx+ca15_mx+ca15_cx1+ca15_cx2+ca15_ls1+ca15_ls2,\ +- ca15_sx1_alu+ca15_sx1_shf+ca15_sx1_sat+ca15_sx2_alu+ca15_sx2_shf\ +- +ca15_sx2_sat+ca15_ldr+ca15_str") +- + ;; Load-store execution Unit + ;; + ;; Loads of up to two words. +@@ -173,6 +158,23 @@ + (eq_attr "neon_type" "none"))) + "ca15_issue2,ca15_ls1+ca15_ls2,ca15_str,ca15_str") + ++;; We include Neon.md here to ensure that the branch can block the Neon units. ++(include "cortex-a15-neon.md") ++ ++;; We lie with calls. They take up all issue slots, and form a block in the ++;; pipeline. The result however is available the next cycle. ++(define_insn_reservation "cortex_a15_call" 1 ++ (and (eq_attr "tune" "cortexa15") ++ (and (eq_attr "type" "call") ++ (eq_attr "neon_type" "none"))) ++ "ca15_issue3,\ ++ ca15_sx1+ca15_sx2+ca15_bx+ca15_mx+ca15_cx_ij+ca15_cx_ik+ca15_ls1+ca15_ls2+\ ++ ca15_cx_imac1+ca15_cx_ialu1+ca15_cx_ialu2+ca15_cx_ishf+\ ++ ca15_cx_acc+ca15_cx_fmul1+ca15_cx_fmul2+ca15_cx_fmul3+ca15_cx_fmul4+\ ++ ca15_cx_falu1+ca15_cx_falu2+ca15_cx_falu3+ca15_cx_falu4+ca15_cx_vfp_i,\ ++ ca15_sx1_alu+ca15_sx1_shf+ca15_sx1_sat+ca15_sx2_alu+\ ++ ca15_sx2_shf+ca15_sx2_sat+ca15_ldr+ca15_str") ++ + ;; Simple execution unit bypasses + (define_bypass 1 "cortex_a15_alu" + "cortex_a15_alu,cortex_a15_alu_shift,cortex_a15_alu_shift_reg") +--- a/src/gcc/config/arm/cortex-a15-neon.md ++++ b/src/gcc/config/arm/cortex-a15-neon.md +@@ -0,0 +1,1215 @@ ++;; ARM Cortex-A15 NEON pipeline description ++;; Copyright (C) 2012 Free Software Foundation, Inc. ++;; ++;; This file is part of GCC. ++;; ++;; GCC is free software; you can redistribute it and/or modify it ++;; under the terms of the GNU General Public License as published by ++;; the Free Software Foundation; either version 3, or (at your option) ++;; any later version. ++;; ++;; GCC is distributed in the hope that it will be useful, but ++;; WITHOUT ANY WARRANTY; without even the implied warranty of ++;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++;; General Public License for more details. ++;; ++;; You should have received a copy of the GNU General Public License ++;; along with GCC; see the file COPYING3. If not see ++;; . ++ ++(define_automaton "cortex_a15_neon") ++ ++;; Dispatch unit. ++(define_cpu_unit "ca15_cx_ij, ca15_cx_ik" "cortex_a15_neon") ++ ++;; Accumulate. ++(define_cpu_unit "ca15_cx_acc" "cortex_a15_neon") ++ ++;; The 32x32 integer multiply-accumulate pipeline. ++(define_cpu_unit "ca15_cx_imac1" "cortex_a15_neon") ++(define_reservation "ca15_cx_imac" "(ca15_cx_ij+ca15_cx_imac1)") ++ ++ ++;; The 64-bit ALU pipeline. ++(define_cpu_unit "ca15_cx_ialu1, ca15_cx_ialu2" "cortex_a15_neon") ++ ++;; IALU with accumulate. ++(define_reservation "ca15_cx_ialu_with_acc" "ca15_cx_ik+ca15_cx_ialu2+ca15_cx_acc") ++ ++(define_reservation "ca15_cx_ialu" ++ "((ca15_cx_ij+ca15_cx_ialu1)|(ca15_cx_ik+ca15_cx_ialu2))") ++ ++;; Integer shift pipeline. ++(define_cpu_unit "ca15_cx_ishf" "cortex_a15_neon") ++(define_reservation "ca15_cx_ishf_with_acc" "ca15_cx_ik+ca15_cx_ishf+ca15_cx_acc") ++ ++;; SIMD multiply pipeline. ++(define_cpu_unit "ca15_cx_fmul1, ca15_cx_fmul2, ca15_cx_fmul3, ca15_cx_fmul4" ++ "cortex_a15_neon") ++ ++(define_reservation "ca15_cx_fmul" ++ "(ca15_cx_ij+(ca15_cx_fmul1|ca15_cx_fmul2))|\ ++ (ca15_cx_ik+(ca15_cx_fmul3|ca15_cx_fmul4))") ++ ++(define_reservation "ca15_cx_fmul_2" ++ "(ca15_cx_ij+(ca15_cx_fmul1|ca15_cx_fmul2))+\ ++ (ca15_cx_ik+(ca15_cx_fmul3|ca15_cx_fmul4))") ++ ++;; SIMD ALU pipeline. ++(define_cpu_unit "ca15_cx_falu1, ca15_cx_falu2, ca15_cx_falu3, ca15_cx_falu4" ++ "cortex_a15_neon") ++ ++(define_reservation "ca15_cx_falu" ++ "(ca15_cx_ij+(ca15_cx_falu1|ca15_cx_falu2))|\ ++ (ca15_cx_ik+(ca15_cx_falu3|ca15_cx_falu4))") ++ ++(define_reservation "ca15_cx_falu_2" ++ "(ca15_cx_ij+(ca15_cx_falu1|ca15_cx_falu2))+\ ++ (ca15_cx_ik+(ca15_cx_falu3|ca15_cx_falu4))") ++ ++;; SIMD multiply-accumulate pipeline. ++;; This can be used if fmul and falu are not reserved. ++(define_reservation "ca15_cx_fmac" ++ "((ca15_cx_ij+ca15_cx_fmul1),nothing*2,ca15_cx_falu1)|\ ++ ((ca15_cx_ij+ca15_cx_fmul2),nothing*2,ca15_cx_falu2)|\ ++ ((ca15_cx_ik+ca15_cx_fmul3),nothing*2,ca15_cx_falu3)|\ ++ ((ca15_cx_ik+ca15_cx_fmul4),nothing*2,ca15_cx_falu4)") ++ ++(define_reservation "ca15_cx_fmac_2" ++ "(((ca15_cx_ij+ca15_cx_fmul1),nothing*2,ca15_cx_falu1)|\ ++ ((ca15_cx_ij+ca15_cx_fmul2),nothing*2,ca15_cx_falu2))+\ ++ (((ca15_cx_ik+ca15_cx_fmul3),nothing*2,ca15_cx_falu3)|\ ++ ((ca15_cx_ik+ca15_cx_fmul4),nothing*2,ca15_cx_falu4))") ++ ++ ++;; Vector FP multiply pipeline ++(define_cpu_unit "ca15_cx_vfp_i" "cortex_a15_neon") ++ ++(define_reservation "ca15_cx_vfp" "ca15_cx_ik+ca15_cx_vfp_i") ++ ++;; Load permute pipeline ++(define_reservation "ca15_cx_perm" "ca15_cx_ij|ca15_cx_ik") ++(define_reservation "ca15_cx_perm_2" "ca15_cx_ij+ca15_cx_ik") ++ ++(define_insn_reservation "cortex_a15_neon_int_1" 5 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" "neon_int_1")) ++ "ca15_issue1,ca15_cx_ialu") ++ ++(define_insn_reservation "cortex_a15_neon_int_2" 5 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" "neon_int_2")) ++ "ca15_issue1,ca15_cx_ialu") ++ ++(define_insn_reservation "cortex_a15_neon_int_3" 5 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" "neon_int_3")) ++ "ca15_issue1,ca15_cx_ialu") ++ ++(define_insn_reservation "cortex_a15_neon_int_4" 5 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" "neon_int_4")) ++ "ca15_issue1,ca15_cx_ialu") ++ ++(define_insn_reservation "cortex_a15_neon_int_5" 5 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" "neon_int_5")) ++ "ca15_issue1,ca15_cx_ialu") ++ ++(define_insn_reservation "cortex_a15_neon_vqneg_vqabs" 5 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" "neon_vqneg_vqabs")) ++ "ca15_issue1,ca15_cx_ialu") ++ ++(define_insn_reservation "cortex_a15_neon_vmov" 5 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" "neon_vmov")) ++ "ca15_issue1,ca15_cx_ialu") ++ ++(define_insn_reservation "cortex_a15_neon_vaba" 7 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" "neon_vaba")) ++ "ca15_issue1,ca15_cx_ialu_with_acc") ++ ++(define_insn_reservation "cortex_a15_neon_vaba_qqq" 8 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" "neon_vaba_qqq")) ++ "ca15_issue2,ca15_cx_ialu_with_acc*2") ++ ++(define_insn_reservation ++ "cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" 6 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")) ++ "ca15_issue1,ca15_cx_imac") ++ ++(define_insn_reservation "cortex_a15_neon_mul_qqq_8_16_32_ddd_32" 7 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" "neon_mul_qqq_8_16_32_ddd_32")) ++ "ca15_issue1,ca15_cx_imac*2") ++ ++(define_insn_reservation ++ "cortex_a15_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" 7 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")) ++ "ca15_issue1,ca15_cx_imac*2") ++ ++(define_insn_reservation ++ "cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" 6 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")) ++ "ca15_issue1,ca15_cx_imac") ++ ++(define_insn_reservation ++ "cortex_a15_neon_mla_qqq_8_16" 7 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_mla_qqq_8_16")) ++ "ca15_issue1,ca15_cx_imac*2") ++ ++(define_insn_reservation ++ "cortex_a15_neon_mla_ddd_32_qqd_16_ddd_32_scalar_\ ++ qdd_64_32_long_scalar_qdd_64_32_long" 7 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")) ++ "ca15_issue1,ca15_cx_imac") ++ ++(define_insn_reservation ++ "cortex_a15_neon_mla_qqq_32_qqd_32_scalar" 7 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_mla_qqq_32_qqd_32_scalar")) ++ "ca15_issue1,ca15_cx_imac*2") ++ ++(define_insn_reservation ++ "cortex_a15_neon_mul_ddd_16_scalar_32_16_long_scalar" 6 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_mul_ddd_16_scalar_32_16_long_scalar")) ++ "ca15_issue1,ca15_cx_imac") ++ ++(define_insn_reservation ++ "cortex_a15_neon_mul_qqd_32_scalar" 7 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_mul_qqd_32_scalar")) ++ "ca15_issue1,ca15_cx_imac*2") ++ ++(define_insn_reservation ++ "cortex_a15_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" 6 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")) ++ "ca15_issue1,ca15_cx_imac") ++ ++(define_insn_reservation ++ "cortex_a15_neon_shift_1" 5 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_shift_1")) ++ "ca15_issue1,ca15_cx_ik+ca15_cx_ishf") ++ ++(define_insn_reservation ++ "cortex_a15_neon_shift_2" 5 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_shift_2")) ++ "ca15_issue1,ca15_cx_ik+ca15_cx_ishf") ++ ++(define_insn_reservation ++ "cortex_a15_neon_shift_3" 6 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_shift_3")) ++ "ca15_issue2,(ca15_cx_ik+ca15_cx_ishf)*2") ++ ++(define_insn_reservation ++ "cortex_a15_neon_vshl_ddd" 5 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_vshl_ddd")) ++ "ca15_issue1,ca15_cx_ik+ca15_cx_ishf") ++ ++(define_insn_reservation ++ "cortex_a15_neon_vqshl_vrshl_vqrshl_qqq" 6 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_vqshl_vrshl_vqrshl_qqq")) ++ "ca15_issue2,(ca15_cx_ik+ca15_cx_ishf)*2") ++ ++(define_insn_reservation ++ "cortex_a15_neon_vsra_vrsra" 7 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_vsra_vrsra")) ++ "ca15_issue1,ca15_cx_ishf_with_acc") ++ ++(define_insn_reservation ++ "cortex_a15_neon_fp_vadd_ddd_vabs_dd" 6 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_fp_vadd_ddd_vabs_dd")) ++ "ca15_issue1,ca15_cx_falu") ++ ++(define_insn_reservation ++ "cortex_a15_neon_fp_vadd_qqq_vabs_qq" 7 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_fp_vadd_qqq_vabs_qq")) ++ "ca15_issue2,ca15_cx_falu_2") ++ ++(define_insn_reservation ++ "cortex_a15_neon_fp_vmul_ddd" 5 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_fp_vmul_ddd")) ++ "ca15_issue1,ca15_cx_fmul") ++ ++(define_insn_reservation ++ "cortex_a15_neon_fp_vmul_qqd" 6 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_fp_vmul_qqd")) ++ "ca15_issue2,ca15_cx_fmul_2") ++ ++(define_insn_reservation ++ "cortex_a15_neon_fp_vmla_ddd" 9 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_fp_vmla_ddd")) ++ "ca15_issue1,ca15_cx_fmac") ++ ++(define_insn_reservation ++ "cortex_a15_neon_fp_vmla_qqq" 11 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_fp_vmla_qqq")) ++ "ca15_issue2,ca15_cx_fmac_2") ++ ++(define_insn_reservation ++ "cortex_a15_neon_fp_vmla_ddd_scalar" 9 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_fp_vmla_ddd_scalar")) ++ "ca15_issue1,ca15_cx_fmac") ++ ++(define_insn_reservation ++ "cortex_a15_neon_fp_vmla_qqq_scalar" 11 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_fp_vmla_qqq_scalar")) ++ "ca15_issue2,ca15_cx_fmac_2") ++ ++(define_insn_reservation ++ "cortex_a15_neon_fp_vrecps_vrsqrts_ddd" 9 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_fp_vrecps_vrsqrts_ddd")) ++ "ca15_issue1,ca15_cx_fmac") ++ ++(define_insn_reservation ++ "cortex_a15_neon_fp_vrecps_vrsqrts_qqq" 11 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_fp_vrecps_vrsqrts_qqq")) ++ "ca15_issue2,ca15_cx_fmac_2") ++ ++(define_insn_reservation ++ "cortex_a15_neon_bp_simple" 4 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_bp_simple")) ++ "ca15_issue3,ca15_ls+ca15_cx_perm_2,ca15_cx_perm") ++ ++(define_insn_reservation ++ "cortex_a15_neon_bp_2cycle" 4 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_bp_2cycle")) ++ "ca15_issue1,ca15_cx_perm") ++ ++(define_insn_reservation ++ "cortex_a15_neon_bp_3cycle" 7 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_bp_3cycle")) ++ "ca15_issue3,ca15_cx_ialu+ca15_cx_perm_2,ca15_cx_perm") ++ ++(define_insn_reservation ++ "cortex_a15_neon_vld1_1_2_regs" 7 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_vld1_1_2_regs")) ++ "ca15_issue2,ca15_ls,ca15_ldr") ++ ++(define_insn_reservation ++ "cortex_a15_neon_vld1_3_4_regs" 8 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_vld1_3_4_regs")) ++ "ca15_issue3,ca15_ls1+ca15_ls2,ca15_ldr,ca15_ldr") ++ ++(define_insn_reservation ++ "cortex_a15_neon_vld2_2_regs_vld1_vld2_all_lanes" 9 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_vld2_2_regs_vld1_vld2_all_lanes")) ++ "ca15_issue3,ca15_ls,ca15_ldr") ++ ++(define_insn_reservation ++ "cortex_a15_neon_vld2_4_regs" 12 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_vld2_4_regs")) ++ "ca15_issue3,ca15_issue3+ca15_ls1+ca15_ls2,ca15_ldr*2") ++ ++(define_insn_reservation ++ "cortex_a15_neon_vld3_vld4" 12 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_vld3_vld4")) ++ "ca15_issue3,ca15_issue3+ca15_ls1+ca15_ls2,ca15_ldr*2") ++ ++(define_insn_reservation ++ "cortex_a15_neon_vst1_1_2_regs_vst2_2_regs" 0 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_vst1_1_2_regs_vst2_2_regs")) ++ "ca15_issue3,ca15_issue3+ca15_cx_perm+ca15_ls1+ca15_ls2,ca15_str*2") ++ ++(define_insn_reservation ++ "cortex_a15_neon_vst1_3_4_regs" 0 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_vst1_3_4_regs")) ++ "ca15_issue3,ca15_issue3+ca15_ls1+ca15_ls2,ca15_str*3") ++ ++(define_insn_reservation ++ "cortex_a15_neon_vst2_4_regs_vst3_vst4" 0 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_vst2_4_regs_vst3_vst4")) ++ "ca15_issue3,ca15_issue3+ca15_cx_perm_2+ca15_ls1+ca15_ls2,\ ++ ca15_issue3+ca15_str,ca15_str*3") ++ ++(define_insn_reservation ++ "cortex_a15_neon_vst3_vst4" 0 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_vst3_vst4")) ++ "ca15_issue3,ca15_issue3+ca15_cx_perm_2+ca15_ls1+ca15_ls2,ca15_str*4") ++ ++(define_insn_reservation ++ "cortex_a15_neon_vld1_vld2_lane" 9 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_vld1_vld2_lane")) ++ "ca15_issue3,ca15_ls,ca15_ldr") ++ ++(define_insn_reservation ++ "cortex_a15_neon_vld3_vld4_lane" 10 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_vld3_vld4_lane")) ++ "ca15_issue3,ca15_issue3+ca15_ls,ca15_issue3+ca15_ldr") ++ ++(define_insn_reservation ++ "cortex_a15_neon_vst1_vst2_lane" 0 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_vst1_vst2_lane")) ++ "ca15_issue3,ca15_cx_perm+ca15_ls,ca15_str") ++ ++(define_insn_reservation ++ "cortex_a15_neon_vst3_vst4_lane" 0 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_vst3_vst4_lane")) ++ "ca15_issue3,ca15_issue3+ca15_cx_perm+ca15_ls1+ca15_ls2,ca15_str*2") ++ ++(define_insn_reservation ++ "cortex_a15_neon_vld3_vld4_all_lanes" 11 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_vld3_vld4_all_lanes")) ++ "ca15_issue3,ca15_issue3+ca15_ls,ca15_ldr") ++ ++(define_insn_reservation ++ "cortex_a15_neon_ldm_2" 20 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_ldm_2")) ++ "ca15_issue3*6") ++ ++(define_insn_reservation ++ "cortex_a15_neon_stm_2" 0 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_stm_2")) ++ "ca15_issue3*6") ++ ++(define_insn_reservation ++ "cortex_a15_neon_mcr" 6 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_mcr")) ++ "ca15_issue2,ca15_ls,ca15_cx_perm") ++ ++(define_insn_reservation ++ "cortex_a15_neon_mcr_2_mcrr" 6 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_mcr_2_mcrr")) ++ "ca15_issue2,ca15_ls1+ca15_ls2") ++ ++(define_insn_reservation ++ "cortex_a15_neon_mrc" 5 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_mrc")) ++ "ca15_issue1,ca15_ls") ++ ++(define_insn_reservation ++ "cortex_a15_neon_mrrc" 6 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "neon_type" ++ "neon_mrrc")) ++ "ca15_issue2,ca15_ls1+ca15_ls2") ++ ++(define_insn_reservation "cortex_a15_vfp_const" 4 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "type" "fconsts,fconstd")) ++ "ca15_issue1,ca15_cx_perm") ++ ++(define_insn_reservation "cortex_a15_vfp_adds_subs" 6 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "type" "fadds")) ++ "ca15_issue1,ca15_cx_vfp") ++ ++(define_insn_reservation "cortex_a15_vfp_addd_subd" 10 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "type" "faddd")) ++ "ca15_issue2,ca15_cx_vfp*2") ++ ++(define_insn_reservation "cortex_a15_vfp_muls" 7 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "type" "fmuls")) ++ "ca15_issue1,ca15_cx_vfp") ++ ++(define_insn_reservation "cortex_a15_vfp_muld" 12 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "type" "fmuld")) ++ "ca15_issue2,ca15_cx_vfp*2") ++ ++(define_insn_reservation "cortex_a15_vfp_macs" 6 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "type" "fmacs,ffmas")) ++ "ca15_issue1,ca15_cx_vfp") ++ ++(define_insn_reservation "cortex_a15_vfp_macd" 11 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "type" "fmacd,ffmad")) ++ "ca15_issue2,ca15_cx_vfp*2") ++ ++(define_insn_reservation "cortex_a15_vfp_cvt" 6 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "type" "f_cvt")) ++ "ca15_issue1,ca15_cx_vfp") ++ ++(define_insn_reservation "cortex_a15_vfp_cmpd" 8 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "type" "fcmpd")) ++ "ca15_issue2,ca15_cx_perm,ca15_cx_vfp") ++ ++(define_insn_reservation "cortex_a15_vfp_cmps" 8 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "type" "fcmps")) ++ "ca15_issue2,ca15_cx_perm,ca15_cx_vfp") ++ ++(define_insn_reservation "cortex_a15_vfp_arithd" 7 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "type" "ffarithd")) ++ "ca15_issue2,ca15_cx_perm*2") ++ ++(define_insn_reservation "cortex_a15_vfp_cpys" 4 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "type" "fcpys")) ++ "ca15_issue1,ca15_cx_perm") ++ ++(define_insn_reservation "cortex_a15_vfp_ariths" 7 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "type" "ffariths")) ++ "ca15_issue1,ca15_cx_perm") ++ ++(define_insn_reservation "cortex_a15_vfp_divs" 10 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "type" "fdivs")) ++ "ca15_issue1,ca15_cx_ik") ++ ++(define_insn_reservation "cortex_a15_vfp_divd" 18 ++ (and (eq_attr "tune" "cortexa15") ++ (eq_attr "type" "fdivd")) ++ "ca15_issue1,ca15_cx_ik") ++ ++;; Define bypasses. ++(define_bypass 5 "cortex_a15_neon_mcr_2_mcrr" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a15_neon_mcr" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 10 "cortex_a15_neon_vld3_vld4_all_lanes" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 9 "cortex_a15_neon_vld3_vld4_lane" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 8 "cortex_a15_neon_vld1_vld2_lane" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 11 "cortex_a15_neon_vld3_vld4" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 11 "cortex_a15_neon_vld2_4_regs" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 8 "cortex_a15_neon_vld2_2_regs_vld1_vld2_all_lanes" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 7 "cortex_a15_neon_vld1_3_4_regs" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 6 "cortex_a15_neon_vld1_1_2_regs" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 6 "cortex_a15_neon_bp_3cycle" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a15_neon_bp_2cycle" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a15_neon_bp_simple" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 10 "cortex_a15_neon_fp_vrecps_vrsqrts_qqq" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 8 "cortex_a15_neon_fp_vrecps_vrsqrts_ddd" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 10 "cortex_a15_neon_fp_vmla_qqq_scalar" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 8 "cortex_a15_neon_fp_vmla_ddd_scalar" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 10 "cortex_a15_neon_fp_vmla_qqq" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 8 "cortex_a15_neon_fp_vmla_ddd" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a15_neon_fp_vmul_qqd" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a15_neon_fp_vmul_ddd" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 6 "cortex_a15_neon_fp_vadd_qqq_vabs_qq" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a15_neon_fp_vadd_ddd_vabs_dd" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 6 "cortex_a15_neon_vsra_vrsra" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a15_neon_vqshl_vrshl_vqrshl_qqq" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a15_neon_vshl_ddd" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a15_neon_shift_3" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a15_neon_shift_2" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a15_neon_shift_1" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a15_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 6 "cortex_a15_neon_mul_qqd_32_scalar" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a15_neon_mul_ddd_16_scalar_32_16_long_scalar" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 6 "cortex_a15_neon_mla_qqq_32_qqd_32_scalar" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 6 "cortex_a15_neon_mla_qqq_8_16" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 6 ++ "cortex_a15_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 6 "cortex_a15_neon_mul_qqq_8_16_32_ddd_32" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 7 "cortex_a15_neon_vaba_qqq" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 6 "cortex_a15_neon_vaba" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a15_neon_vmov" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a15_neon_vqneg_vqabs" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a15_neon_int_5" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a15_neon_int_4" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a15_neon_int_3" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a15_neon_int_2" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a15_neon_int_1" ++ "cortex_a15_neon_int_1,\ ++ cortex_a15_neon_int_4,\ ++ cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a15_neon_mla_qqq_8_16,\ ++ cortex_a15_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a15_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a15_neon_fp_vmla_ddd,\ ++ cortex_a15_neon_fp_vmla_qqq,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a15_neon_fp_vrecps_vrsqrts_qqq") ++ +--- a/src/gcc/config/arm/cortex-a5.md ++++ b/src/gcc/config/arm/cortex-a5.md +@@ -58,12 +58,12 @@ + + (define_insn_reservation "cortex_a5_alu" 2 + (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "alu")) ++ (eq_attr "type" "alu_reg,simple_alu_imm")) + "cortex_a5_ex1") + + (define_insn_reservation "cortex_a5_alu_shift" 2 + (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "alu_shift,alu_shift_reg")) ++ (eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg")) + "cortex_a5_ex1") + + ;; Forwarding path for unshifted operands. +@@ -185,7 +185,7 @@ + + (define_insn_reservation "cortex_a5_fpmacs" 8 + (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "fmacs")) ++ (eq_attr "type" "fmacs,ffmas")) + "cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe") + + ;; Non-multiply instructions can issue in the middle two instructions of a +@@ -201,7 +201,7 @@ + + (define_insn_reservation "cortex_a5_fpmacd" 11 + (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "fmacd")) ++ (eq_attr "type" "fmacd,ffmad")) + "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\ + cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe") + +--- a/src/gcc/config/arm/cortex-a7.md ++++ b/src/gcc/config/arm/cortex-a7.md +@@ -0,0 +1,407 @@ ++;; ARM Cortex-A7 pipeline description ++;; Copyright (C) 2012 Free Software Foundation, Inc. ++;; ++;; Contributed by ARM Ltd. ++;; Based on cortex-a5.md which was originally contributed by CodeSourcery. ++;; ++;; This file is part of GCC. ++;; ++;; GCC is free software; you can redistribute it and/or modify it ++;; under the terms of the GNU General Public License as published by ++;; the Free Software Foundation; either version 3, or (at your option) ++;; any later version. ++;; ++;; GCC is distributed in the hope that it will be useful, but ++;; WITHOUT ANY WARRANTY; without even the implied warranty of ++;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++;; General Public License for more details. ++;; ++;; You should have received a copy of the GNU General Public License ++;; along with GCC; see the file COPYING3. If not see ++;; . ++ ++(define_automaton "cortex_a7") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; Functional units. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++;; The Cortex-A7 pipeline integer and vfp pipeline. ++;; The decode is the same for all instructions, so do not model it. ++;; We only model the first execution stage because ++;; instructions always advance one stage per cycle in order. ++;; We model all of the LS, Branch, ALU, MAC and FPU pipelines together. ++ ++(define_cpu_unit "cortex_a7_ex1, cortex_a7_ex2" "cortex_a7") ++ ++(define_reservation "cortex_a7_both" "cortex_a7_ex1+cortex_a7_ex2") ++ ++(define_cpu_unit "cortex_a7_branch" "cortex_a7") ++ ++;; Cortex-A7 is in order and can dual-issue under limited circumstances. ++;; ex2 can be reserved only after ex1 is reserved. ++ ++(final_presence_set "cortex_a7_ex2" "cortex_a7_ex1") ++ ++;; Pseudo-unit for blocking the multiply pipeline when a double-precision ++;; multiply is in progress. ++ ++(define_cpu_unit "cortex_a7_fpmul_pipe" "cortex_a7") ++ ++;; The floating-point add pipeline (ex1/f1 stage), used to model the usage ++;; of the add pipeline by fmac instructions, etc. ++ ++(define_cpu_unit "cortex_a7_fpadd_pipe" "cortex_a7") ++ ++;; Floating-point div/sqrt (long latency, out-of-order completion). ++ ++(define_cpu_unit "cortex_a7_fp_div_sqrt" "cortex_a7") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; Branches. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++;; A direct branch can dual issue either as younger or older instruction, ++;; but branches cannot dual issue with branches. ++;; No latency as there is no result. ++ ++(define_insn_reservation "cortex_a7_branch" 0 ++ (and (eq_attr "tune" "cortexa7") ++ (and (eq_attr "type" "branch") ++ (eq_attr "neon_type" "none"))) ++ "(cortex_a7_ex2|cortex_a7_ex1)+cortex_a7_branch") ++ ++;; Call cannot dual-issue as an older instruction. It can dual-issue ++;; as a younger instruction, or single-issue. Call cannot dual-issue ++;; with another branch instruction. The result is available the next ++;; cycle. ++(define_insn_reservation "cortex_a7_call" 1 ++ (and (eq_attr "tune" "cortexa7") ++ (and (eq_attr "type" "call") ++ (eq_attr "neon_type" "none"))) ++ "(cortex_a7_ex2|cortex_a7_both)+cortex_a7_branch") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; ALU instructions. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++;; ALU instruction with an immediate operand can dual-issue. ++(define_insn_reservation "cortex_a7_alu_imm" 2 ++ (and (eq_attr "tune" "cortexa7") ++ (and (ior (eq_attr "type" "simple_alu_imm") ++ (ior (eq_attr "type" "simple_alu_shift") ++ (and (eq_attr "insn" "mov") ++ (not (eq_attr "length" "8"))))) ++ (eq_attr "neon_type" "none"))) ++ "cortex_a7_ex2|cortex_a7_ex1") ++ ++;; ALU instruction with register operands can dual-issue ++;; with a younger immediate-based instruction. ++(define_insn_reservation "cortex_a7_alu_reg" 2 ++ (and (eq_attr "tune" "cortexa7") ++ (and (eq_attr "type" "alu_reg") ++ (eq_attr "neon_type" "none"))) ++ "cortex_a7_ex1") ++ ++(define_insn_reservation "cortex_a7_alu_shift" 2 ++ (and (eq_attr "tune" "cortexa7") ++ (and (eq_attr "type" "alu_shift,alu_shift_reg") ++ (eq_attr "neon_type" "none"))) ++ "cortex_a7_ex1") ++ ++;; Forwarding path for unshifted operands. ++(define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_alu_shift" ++ "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_mul") ++ ++(define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_alu_shift" ++ "cortex_a7_store*" ++ "arm_no_early_store_addr_dep") ++ ++(define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_alu_shift" ++ "cortex_a7_alu_shift" ++ "arm_no_early_alu_shift_dep") ++ ++;; The multiplier pipeline can forward results from wr stage only so ++;; there's no need to specify bypasses. ++;; Multiply instructions cannot dual-issue. ++ ++(define_insn_reservation "cortex_a7_mul" 2 ++ (and (eq_attr "tune" "cortexa7") ++ (and (eq_attr "type" "mult") ++ (eq_attr "neon_type" "none"))) ++ "cortex_a7_both") ++ ++;; Forward the result of a multiply operation to the accumulator ++;; of the following multiply and accumulate instruction. ++(define_bypass 1 "cortex_a7_mul" ++ "cortex_a7_mul" ++ "arm_mac_accumulator_is_result") ++ ++;; The latency depends on the operands, so we use an estimate here. ++(define_insn_reservation "cortex_a7_idiv" 5 ++ (and (eq_attr "tune" "cortexa7") ++ (eq_attr "insn" "udiv,sdiv")) ++ "cortex_a7_both*5") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; Load/store instructions. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++;; Address-generation happens in the issue stage. ++;; Double-word accesses can be issued in a single cycle, ++;; and occupy only one pipeline stage. ++ ++(define_insn_reservation "cortex_a7_load1" 2 ++ (and (eq_attr "tune" "cortexa7") ++ (and (eq_attr "type" "load_byte,load1") ++ (eq_attr "neon_type" "none"))) ++ "cortex_a7_ex1") ++ ++(define_insn_reservation "cortex_a7_store1" 0 ++ (and (eq_attr "tune" "cortexa7") ++ (and (eq_attr "type" "store1") ++ (eq_attr "neon_type" "none"))) ++ "cortex_a7_ex1") ++ ++(define_insn_reservation "cortex_a7_load2" 2 ++ (and (eq_attr "tune" "cortexa7") ++ (and (eq_attr "type" "load2") ++ (eq_attr "neon_type" "none"))) ++ "cortex_a7_both") ++ ++(define_insn_reservation "cortex_a7_store2" 0 ++ (and (eq_attr "tune" "cortexa7") ++ (and (eq_attr "type" "store2") ++ (eq_attr "neon_type" "none"))) ++ "cortex_a7_both") ++ ++(define_insn_reservation "cortex_a7_load3" 3 ++ (and (eq_attr "tune" "cortexa7") ++ (and (eq_attr "type" "load3") ++ (eq_attr "neon_type" "none"))) ++ "cortex_a7_both, cortex_a7_ex1") ++ ++(define_insn_reservation "cortex_a7_store3" 0 ++ (and (eq_attr "tune" "cortexa7") ++ (and (eq_attr "type" "store4") ++ (eq_attr "neon_type" "none"))) ++ "cortex_a7_both, cortex_a7_ex1") ++ ++(define_insn_reservation "cortex_a7_load4" 3 ++ (and (eq_attr "tune" "cortexa7") ++ (and (eq_attr "type" "load4") ++ (eq_attr "neon_type" "none"))) ++ "cortex_a7_both, cortex_a7_both") ++ ++(define_insn_reservation "cortex_a7_store4" 0 ++ (and (eq_attr "tune" "cortexa7") ++ (and (eq_attr "type" "store3") ++ (eq_attr "neon_type" "none"))) ++ "cortex_a7_both, cortex_a7_both") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; Floating-point arithmetic. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; Neon integer, neon floating point, and single-precision floating ++;; point instructions of the same type have the same timing ++;; characteristics, but neon instructions cannot dual-issue. ++ ++(define_insn_reservation "cortex_a7_fpalu" 4 ++ (and (eq_attr "tune" "cortexa7") ++ (and (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys,\ ++ f_cvt, fcmps, fcmpd") ++ (eq_attr "neon_type" "none"))) ++ "cortex_a7_ex1+cortex_a7_fpadd_pipe") ++ ++;; For fconsts and fconstd, 8-bit immediate data is passed directly from ++;; f1 to f3 (which I think reduces the latency by one cycle). ++ ++(define_insn_reservation "cortex_a7_fconst" 3 ++ (and (eq_attr "tune" "cortexa7") ++ (and (eq_attr "type" "fconsts,fconstd") ++ (eq_attr "neon_type" "none"))) ++ "cortex_a7_ex1+cortex_a7_fpadd_pipe") ++ ++;; We should try not to attempt to issue a single-precision multiplication in ++;; the middle of a double-precision multiplication operation (the usage of ++;; cortex_a7_fpmul_pipe). ++ ++(define_insn_reservation "cortex_a7_fpmuls" 4 ++ (and (eq_attr "tune" "cortexa7") ++ (and (eq_attr "type" "fmuls") ++ (eq_attr "neon_type" "none"))) ++ "cortex_a7_ex1+cortex_a7_fpmul_pipe") ++ ++(define_insn_reservation "cortex_a7_neon_mul" 4 ++ (and (eq_attr "tune" "cortexa7") ++ (eq_attr "neon_type" ++ "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ neon_mul_qqq_8_16_32_ddd_32,\ ++ neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,\ ++ neon_mul_ddd_16_scalar_32_16_long_scalar,\ ++ neon_mul_qqd_32_scalar,\ ++ neon_fp_vmul_ddd,\ ++ neon_fp_vmul_qqd")) ++ "(cortex_a7_both+cortex_a7_fpmul_pipe)*2") ++ ++(define_insn_reservation "cortex_a7_fpmacs" 8 ++ (and (eq_attr "tune" "cortexa7") ++ (and (eq_attr "type" "fmacs,ffmas") ++ (eq_attr "neon_type" "none"))) ++ "cortex_a7_ex1+cortex_a7_fpmul_pipe") ++ ++(define_insn_reservation "cortex_a7_neon_mla" 8 ++ (and (eq_attr "tune" "cortexa7") ++ (eq_attr "neon_type" ++ "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ neon_mla_qqq_8_16,\ ++ neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,\ ++ neon_mla_qqq_32_qqd_32_scalar,\ ++ neon_mla_ddd_16_scalar_qdd_32_16_long_scalar,\ ++ neon_fp_vmla_ddd,\ ++ neon_fp_vmla_qqq,\ ++ neon_fp_vmla_ddd_scalar,\ ++ neon_fp_vmla_qqq_scalar")) ++ "cortex_a7_both+cortex_a7_fpmul_pipe") ++ ++(define_bypass 4 "cortex_a7_fpmacs,cortex_a7_neon_mla" ++ "cortex_a7_fpmacs,cortex_a7_neon_mla" ++ "arm_mac_accumulator_is_result") ++ ++;; Non-multiply instructions can issue between two cycles of a ++;; double-precision multiply. ++ ++(define_insn_reservation "cortex_a7_fpmuld" 7 ++ (and (eq_attr "tune" "cortexa7") ++ (and (eq_attr "type" "fmuld") ++ (eq_attr "neon_type" "none"))) ++ "cortex_a7_ex1+cortex_a7_fpmul_pipe, cortex_a7_fpmul_pipe*3") ++ ++(define_insn_reservation "cortex_a7_fpmacd" 11 ++ (and (eq_attr "tune" "cortexa7") ++ (and (eq_attr "type" "fmacd") ++ (eq_attr "neon_type" "none"))) ++ "cortex_a7_ex1+cortex_a7_fpmul_pipe, cortex_a7_fpmul_pipe*3") ++ ++(define_insn_reservation "cortex_a7_fpfmad" 8 ++ (and (eq_attr "tune" "cortexa7") ++ (and (eq_attr "type" "ffmad") ++ (eq_attr "neon_type" "none"))) ++ "cortex_a7_ex1+cortex_a7_fpmul_pipe, cortex_a7_fpmul_pipe*4") ++ ++(define_bypass 7 "cortex_a7_fpmacd" ++ "cortex_a7_fpmacd,cortex_a7_fpfmad" ++ "arm_mac_accumulator_is_result") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; Floating-point divide/square root instructions. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++(define_insn_reservation "cortex_a7_fdivs" 16 ++ (and (eq_attr "tune" "cortexa7") ++ (and (eq_attr "type" "fdivs") ++ (eq_attr "neon_type" "none"))) ++ "cortex_a7_ex1+cortex_a7_fp_div_sqrt, cortex_a7_fp_div_sqrt * 13") ++ ++(define_insn_reservation "cortex_a7_fdivd" 31 ++ (and (eq_attr "tune" "cortexa7") ++ (and (eq_attr "type" "fdivd") ++ (eq_attr "neon_type" "none"))) ++ "cortex_a7_ex1+cortex_a7_fp_div_sqrt, cortex_a7_fp_div_sqrt * 28") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; VFP to/from core transfers. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++;; Core-to-VFP transfers. ++ ++(define_insn_reservation "cortex_a7_r2f" 4 ++ (and (eq_attr "tune" "cortexa7") ++ (and (eq_attr "type" "r_2_f") ++ (eq_attr "neon_type" "none"))) ++ "cortex_a7_both") ++ ++(define_insn_reservation "cortex_a7_f2r" 2 ++ (and (eq_attr "tune" "cortexa7") ++ (and (eq_attr "type" "f_2_r") ++ (eq_attr "neon_type" "none"))) ++ "cortex_a7_ex1") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; VFP flag transfer. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++;; Fuxne: The flag forwarding from fmstat to the second instruction is ++;; not modeled at present. ++ ++(define_insn_reservation "cortex_a7_f_flags" 4 ++ (and (eq_attr "tune" "cortexa7") ++ (and (eq_attr "type" "f_flag") ++ (eq_attr "neon_type" "none"))) ++ "cortex_a7_ex1") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; VFP load/store. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++(define_insn_reservation "cortex_a7_f_loads" 4 ++ (and (eq_attr "tune" "cortexa7") ++ (and (eq_attr "type" "f_loads") ++ (eq_attr "neon_type" "none"))) ++ "cortex_a7_ex1") ++ ++(define_insn_reservation "cortex_a7_f_loadd" 4 ++ (and (eq_attr "tune" "cortexa7") ++ (and (eq_attr "type" "f_loadd") ++ (eq_attr "neon_type" "none"))) ++ "cortex_a7_both") ++ ++(define_insn_reservation "cortex_a7_f_stores" 0 ++ (and (eq_attr "tune" "cortexa7") ++ (and (eq_attr "type" "f_stores") ++ (eq_attr "neon_type" "none"))) ++ "cortex_a7_ex1") ++ ++(define_insn_reservation "cortex_a7_f_stored" 0 ++ (and (eq_attr "tune" "cortexa7") ++ (and (eq_attr "type" "f_stored") ++ (eq_attr "neon_type" "none"))) ++ "cortex_a7_both") ++ ++;; Load-to-use for floating-point values has a penalty of one cycle, ++;; i.e. a latency of two. ++ ++(define_bypass 2 "cortex_a7_f_loads, cortex_a7_f_loadd" ++ "cortex_a7_fpalu,\ ++ cortex_a7_fpmuls,cortex_a7_fpmacs,\ ++ cortex_a7_fpmuld,cortex_a7_fpmacd, cortex_a7_fpfmad,\ ++ cortex_a7_fdivs, cortex_a7_fdivd,\ ++ cortex_a7_f2r") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; NEON ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++;; Simple modeling for all neon instructions not covered earlier. ++ ++(define_insn_reservation "cortex_a7_neon" 4 ++ (and (eq_attr "tune" "cortexa7") ++ (eq_attr "neon_type" ++ "!none,\ ++ neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ neon_mul_qqq_8_16_32_ddd_32,\ ++ neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,\ ++ neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ neon_mla_qqq_8_16,\ ++ neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,\ ++ neon_mla_qqq_32_qqd_32_scalar,\ ++ neon_mul_ddd_16_scalar_32_16_long_scalar,\ ++ neon_mul_qqd_32_scalar,\ ++ neon_mla_ddd_16_scalar_qdd_32_16_long_scalar,\ ++ neon_fp_vmul_ddd,\ ++ neon_fp_vmul_qqd,\ ++ neon_fp_vmla_ddd,\ ++ neon_fp_vmla_qqq,\ ++ neon_fp_vmla_ddd_scalar,\ ++ neon_fp_vmla_qqq_scalar")) ++ "cortex_a7_both*2") +--- a/src/gcc/config/arm/cortex-a8.md ++++ b/src/gcc/config/arm/cortex-a8.md +@@ -85,7 +85,7 @@ + ;; (source read in E2 and destination available at the end of that cycle). + (define_insn_reservation "cortex_a8_alu" 2 + (and (eq_attr "tune" "cortexa8") +- (ior (and (and (eq_attr "type" "alu") ++ (ior (and (and (eq_attr "type" "alu_reg,simple_alu_imm") + (eq_attr "neon_type" "none")) + (not (eq_attr "insn" "mov,mvn"))) + (eq_attr "insn" "clz"))) +@@ -93,7 +93,7 @@ + + (define_insn_reservation "cortex_a8_alu_shift" 2 + (and (eq_attr "tune" "cortexa8") +- (and (eq_attr "type" "alu_shift") ++ (and (eq_attr "type" "simple_alu_shift,alu_shift") + (not (eq_attr "insn" "mov,mvn")))) + "cortex_a8_default") + +@@ -107,7 +107,7 @@ + + (define_insn_reservation "cortex_a8_mov" 1 + (and (eq_attr "tune" "cortexa8") +- (and (eq_attr "type" "alu,alu_shift,alu_shift_reg") ++ (and (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,alu_shift,alu_shift_reg") + (eq_attr "insn" "mov,mvn"))) + "cortex_a8_default") + +--- a/src/gcc/config/arm/cortex-a8-neon.md ++++ b/src/gcc/config/arm/cortex-a8-neon.md +@@ -149,12 +149,12 @@ + + (define_insn_reservation "cortex_a8_vfp_macs" 21 + (and (eq_attr "tune" "cortexa8") +- (eq_attr "type" "fmacs")) ++ (eq_attr "type" "fmacs,ffmas")) + "cortex_a8_vfp,cortex_a8_vfplite*20") + + (define_insn_reservation "cortex_a8_vfp_macd" 26 + (and (eq_attr "tune" "cortexa8") +- (eq_attr "type" "fmacd")) ++ (eq_attr "type" "fmacd,ffmad")) + "cortex_a8_vfp,cortex_a8_vfplite*25") + + (define_insn_reservation "cortex_a8_vfp_divs" 37 +--- a/src/gcc/config/arm/cortex-a9.md ++++ b/src/gcc/config/arm/cortex-a9.md +@@ -80,9 +80,9 @@ + ;; which can go down E2 without any problem. + (define_insn_reservation "cortex_a9_dp" 2 + (and (eq_attr "tune" "cortexa9") +- (ior (and (eq_attr "type" "alu") ++ (ior (and (eq_attr "type" "alu_reg,simple_alu_imm") + (eq_attr "neon_type" "none")) +- (and (and (eq_attr "type" "alu_shift_reg, alu_shift") ++ (and (and (eq_attr "type" "alu_shift_reg, simple_alu_shift,alu_shift") + (eq_attr "insn" "mov")) + (eq_attr "neon_type" "none")))) + "cortex_a9_p0_default|cortex_a9_p1_default") +@@ -90,7 +90,7 @@ + ;; An instruction using the shifter will go down E1. + (define_insn_reservation "cortex_a9_dp_shift" 3 + (and (eq_attr "tune" "cortexa9") +- (and (eq_attr "type" "alu_shift_reg, alu_shift") ++ (and (eq_attr "type" "alu_shift_reg, simple_alu_shift,alu_shift") + (not (eq_attr "insn" "mov")))) + "cortex_a9_p0_shift | cortex_a9_p1_shift") + +@@ -203,7 +203,7 @@ + ;; Pipeline Instruction Classification. + ;; FPS - fcpys, ffariths, ffarithd,r_2_f,f_2_r + ;; FP_ADD - fadds, faddd, fcmps (1) +-;; FPMUL - fmul{s,d}, fmac{s,d} ++;; FPMUL - fmul{s,d}, fmac{s,d}, ffma{s,d} + ;; FPDIV - fdiv{s,d} + (define_cpu_unit "ca9fps" "cortex_a9") + (define_cpu_unit "ca9fp_add1, ca9fp_add2, ca9fp_add3, ca9fp_add4" "cortex_a9") +@@ -253,12 +253,12 @@ + + (define_insn_reservation "cortex_a9_fmacs" 8 + (and (eq_attr "tune" "cortexa9") +- (eq_attr "type" "fmacs")) ++ (eq_attr "type" "fmacs,ffmas")) + "ca9fmuls, ca9fp_add") + + (define_insn_reservation "cortex_a9_fmacd" 9 + (and (eq_attr "tune" "cortexa9") +- (eq_attr "type" "fmacd")) ++ (eq_attr "type" "fmacd,ffmad")) + "ca9fmuld, ca9fp_add") + + ;; Division pipeline description. +--- a/src/gcc/config/arm/cortex-m4-fpu.md ++++ b/src/gcc/config/arm/cortex-m4-fpu.md +@@ -46,7 +46,7 @@ + + (define_insn_reservation "cortex_m4_fmacs" 4 + (and (eq_attr "tune" "cortexm4") +- (eq_attr "type" "fmacs")) ++ (eq_attr "type" "fmacs,ffmas")) + "cortex_m4_ex_v*3") + + (define_insn_reservation "cortex_m4_ffariths" 1 +--- a/src/gcc/config/arm/cortex-m4.md ++++ b/src/gcc/config/arm/cortex-m4.md +@@ -31,7 +31,7 @@ + ;; ALU and multiply is one cycle. + (define_insn_reservation "cortex_m4_alu" 1 + (and (eq_attr "tune" "cortexm4") +- (eq_attr "type" "alu,alu_shift,alu_shift_reg,mult")) ++ (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,alu_shift,alu_shift_reg,mult")) + "cortex_m4_ex") + + ;; Byte, half-word and word load is two cycles. +--- a/src/gcc/config/arm/cortex-r4f.md ++++ b/src/gcc/config/arm/cortex-r4f.md +@@ -63,7 +63,7 @@ + + (define_insn_reservation "cortex_r4_fmacs" 6 + (and (eq_attr "tune_cortexr4" "yes") +- (eq_attr "type" "fmacs")) ++ (eq_attr "type" "fmacs,ffmas")) + "(cortex_r4_issue_a+cortex_r4_v1)|(cortex_r4_issue_b+cortex_r4_vmla)") + + (define_insn_reservation "cortex_r4_fdivs" 17 +@@ -119,7 +119,7 @@ + + (define_insn_reservation "cortex_r4_fmacd" 20 + (and (eq_attr "tune_cortexr4" "yes") +- (eq_attr "type" "fmacd")) ++ (eq_attr "type" "fmacd,ffmad")) + "cortex_r4_single_issue*13") + + (define_insn_reservation "cortex_r4_farith" 10 +--- a/src/gcc/config/arm/cortex-r4.md ++++ b/src/gcc/config/arm/cortex-r4.md +@@ -78,19 +78,19 @@ + ;; for the purposes of the dual-issue constraints above. + (define_insn_reservation "cortex_r4_alu" 2 + (and (eq_attr "tune_cortexr4" "yes") +- (and (eq_attr "type" "alu") ++ (and (eq_attr "type" "alu_reg,simple_alu_imm") + (not (eq_attr "insn" "mov")))) + "cortex_r4_alu") + + (define_insn_reservation "cortex_r4_mov" 2 + (and (eq_attr "tune_cortexr4" "yes") +- (and (eq_attr "type" "alu") ++ (and (eq_attr "type" "alu_reg,simple_alu_imm") + (eq_attr "insn" "mov"))) + "cortex_r4_mov") + + (define_insn_reservation "cortex_r4_alu_shift" 2 + (and (eq_attr "tune_cortexr4" "yes") +- (eq_attr "type" "alu_shift")) ++ (eq_attr "type" "simple_alu_shift,alu_shift")) + "cortex_r4_alu") + + (define_insn_reservation "cortex_r4_alu_shift_reg" 2 +--- a/src/gcc/config/arm/driver-arm.c ++++ b/src/gcc/config/arm/driver-arm.c +@@ -37,6 +37,7 @@ + {"0xb56", "armv6t2", "arm1156t2-s"}, + {"0xb76", "armv6zk", "arm1176jz-s"}, + {"0xc05", "armv7-a", "cortex-a5"}, ++ {"0xc07", "armv7-a", "cortex-a7"}, + {"0xc08", "armv7-a", "cortex-a8"}, + {"0xc09", "armv7-a", "cortex-a9"}, + {"0xc0f", "armv7-a", "cortex-a15"}, +--- a/src/gcc/config/arm/fa526.md ++++ b/src/gcc/config/arm/fa526.md +@@ -62,12 +62,12 @@ + ;; ALU operations + (define_insn_reservation "526_alu_op" 1 + (and (eq_attr "tune" "fa526") +- (eq_attr "type" "alu")) ++ (eq_attr "type" "alu_reg,simple_alu_imm")) + "fa526_core") + + (define_insn_reservation "526_alu_shift_op" 2 + (and (eq_attr "tune" "fa526") +- (eq_attr "type" "alu_shift,alu_shift_reg")) ++ (eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg")) + "fa526_core") + + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +--- a/src/gcc/config/arm/fa606te.md ++++ b/src/gcc/config/arm/fa606te.md +@@ -62,7 +62,7 @@ + ;; ALU operations + (define_insn_reservation "606te_alu_op" 1 + (and (eq_attr "tune" "fa606te") +- (eq_attr "type" "alu,alu_shift,alu_shift_reg")) ++ (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,alu_shift,alu_shift_reg")) + "fa606te_core") + + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +--- a/src/gcc/config/arm/fa626te.md ++++ b/src/gcc/config/arm/fa626te.md +@@ -68,12 +68,12 @@ + ;; ALU operations + (define_insn_reservation "626te_alu_op" 1 + (and (eq_attr "tune" "fa626,fa626te") +- (eq_attr "type" "alu")) ++ (eq_attr "type" "alu_reg,simple_alu_imm")) + "fa626te_core") + + (define_insn_reservation "626te_alu_shift_op" 2 + (and (eq_attr "tune" "fa626,fa626te") +- (eq_attr "type" "alu_shift,alu_shift_reg")) ++ (eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg")) + "fa626te_core") + + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +--- a/src/gcc/config/arm/fa726te.md ++++ b/src/gcc/config/arm/fa726te.md +@@ -85,7 +85,7 @@ + ;; Other ALU instructions 2 cycles. + (define_insn_reservation "726te_alu_op" 1 + (and (eq_attr "tune" "fa726te") +- (and (eq_attr "type" "alu") ++ (and (eq_attr "type" "alu_reg,simple_alu_imm") + (not (eq_attr "insn" "mov,mvn")))) + "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)") + +@@ -95,7 +95,7 @@ + ;; it takes 3 cycles. + (define_insn_reservation "726te_alu_shift_op" 3 + (and (eq_attr "tune" "fa726te") +- (and (eq_attr "type" "alu_shift") ++ (and (eq_attr "type" "simple_alu_shift,alu_shift") + (not (eq_attr "insn" "mov,mvn")))) + "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)") + +--- a/src/gcc/config/arm/fmp626.md ++++ b/src/gcc/config/arm/fmp626.md +@@ -63,12 +63,12 @@ + ;; ALU operations + (define_insn_reservation "mp626_alu_op" 1 + (and (eq_attr "tune" "fmp626") +- (eq_attr "type" "alu")) ++ (eq_attr "type" "alu_reg,simple_alu_imm")) + "fmp626_core") + + (define_insn_reservation "mp626_alu_shift_op" 2 + (and (eq_attr "tune" "fmp626") +- (eq_attr "type" "alu_shift,alu_shift_reg")) ++ (eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg")) + "fmp626_core") + + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +--- a/src/gcc/config/arm/iterators.md ++++ b/src/gcc/config/arm/iterators.md +@@ -42,6 +42,9 @@ + ;; A list of the 32bit and 64bit integer modes + (define_mode_iterator SIDI [SI DI]) + ++;; A list of modes which the VFP unit can handle ++(define_mode_iterator SDF [(SF "TARGET_VFP") (DF "TARGET_VFP_DOUBLE")]) ++ + ;; Integer element sizes implemented by IWMMXT. + (define_mode_iterator VMMX [V2SI V4HI V8QI]) + +@@ -183,6 +186,9 @@ + ;; A list of widening operators + (define_code_iterator SE [sign_extend zero_extend]) + ++;; Right shifts ++(define_code_iterator rshifts [ashiftrt lshiftrt]) ++ + ;;---------------------------------------------------------------------------- + ;; Mode attributes + ;;---------------------------------------------------------------------------- +@@ -243,7 +249,8 @@ + (V4HI "P") (V8HI "q") + (V2SI "P") (V4SI "q") + (V2SF "P") (V4SF "q") +- (DI "P") (V2DI "q")]) ++ (DI "P") (V2DI "q") ++ (SF "") (DF "P")]) + + ;; Wider modes with the same number of elements. + (define_mode_attr V_widen [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI")]) +@@ -301,7 +308,8 @@ + (V4HI "i16") (V8HI "i16") + (V2SI "i32") (V4SI "i32") + (DI "i64") (V2DI "i64") +- (V2SF "f32") (V4SF "f32")]) ++ (V2SF "f32") (V4SF "f32") ++ (SF "f32") (DF "f64")]) + + ;; Same, but for operations which work on signed values. + (define_mode_attr V_s_elem [(V8QI "s8") (V16QI "s8") +@@ -409,8 +417,8 @@ + (define_mode_attr qhs_extenddi_op [(SI "s_register_operand") + (HI "nonimmediate_operand") + (QI "arm_reg_or_extendqisi_mem_op")]) +-(define_mode_attr qhs_extenddi_cstr [(SI "r") (HI "rm") (QI "rUq")]) +-(define_mode_attr qhs_zextenddi_cstr [(SI "r") (HI "rm") (QI "rm")]) ++(define_mode_attr qhs_extenddi_cstr [(SI "r,0,r,r") (HI "r,0,rm,rm") (QI "r,0,rUq,rm")]) ++(define_mode_attr qhs_zextenddi_cstr [(SI "r,0,r") (HI "r,0,rm") (QI "r,0,rm")]) + + ;; Mode attributes used for fixed-point support. + (define_mode_attr qaddsub_suf [(V4UQQ "8") (V2UHQ "16") (UQQ "8") (UHQ "16") +@@ -421,6 +429,10 @@ + ;; Mode attribute for vshll. + (define_mode_attr V_innermode [(V8QI "QI") (V4HI "HI") (V2SI "SI")]) + ++;; Mode attributes used for fused-multiply-accumulate VFP support ++(define_mode_attr F_constraint [(SF "t") (DF "w")]) ++(define_mode_attr F_fma_type [(SF "s") (DF "d")]) ++ + ;;---------------------------------------------------------------------------- + ;; Code attributes + ;;---------------------------------------------------------------------------- +@@ -438,3 +450,8 @@ + + ;; Assembler mnemonics for signedness of widening operations. + (define_code_attr US [(sign_extend "s") (zero_extend "u")]) ++ ++;; Right shifts ++(define_code_attr shift [(ashiftrt "ashr") (lshiftrt "lshr")]) ++(define_code_attr shifttype [(ashiftrt "signed") (lshiftrt "unsigned")]) ++ --- a/src/gcc/config/arm/linux-eabi.h +++ b/src/gcc/config/arm/linux-eabi.h @@ -32,7 +32,8 @@ @@ -49035,9 +55620,68 @@ /* At this point, bpabi.h will have clobbered LINK_SPEC. We want to use the GNU/Linux version, not the generic BPABI version. */ +--- a/src/gcc/config/arm/neon-docgen.ml ++++ b/src/gcc/config/arm/neon-docgen.ml +@@ -103,6 +103,8 @@ + "Multiplication", single_opcode Vmul; + "Multiply-accumulate", single_opcode Vmla; + "Multiply-subtract", single_opcode Vmls; ++ "Fused-multiply-accumulate", single_opcode Vfma; ++ "Fused-multiply-subtract", single_opcode Vfms; + "Subtraction", single_opcode Vsub; + "Comparison (equal-to)", single_opcode Vceq; + "Comparison (greater-than-or-equal-to)", single_opcode Vcge; +--- a/src/gcc/config/arm/neon-gen.ml ++++ b/src/gcc/config/arm/neon-gen.ml +@@ -239,6 +239,24 @@ + and srcmode = mode_of_elt src shape in + string_of_mode dstmode ^ string_of_mode srcmode + ++let print_feature_test_start features = ++ try ++ match List.find (fun feature -> ++ match feature with Requires_feature _ -> true ++ | _ -> false) ++ features with ++ Requires_feature feature -> ++ Format.printf "#ifdef __ARM_FEATURE_%s@\n" feature ++ | _ -> assert false ++ with Not_found -> assert true ++ ++let print_feature_test_end features = ++ let feature = ++ List.exists (function Requires_feature x -> true ++ | _ -> false) features in ++ if feature then Format.printf "#endif@\n" ++ ++ + let print_variant opcode features shape name (ctype, asmtype, elttype) = + let bits = infoword_value elttype features in + let modesuf = mode_suffix elttype shape in +@@ -252,7 +270,11 @@ + let rdecls, stmts = return ctype return_by_ptr builtin in + let body = pdecls @ rdecls @ stmts + and fnname = (intrinsic_name name) ^ "_" ^ (string_of_elt elttype) in +- print_function ctype fnname body ++ begin ++ print_feature_test_start features; ++ print_function ctype fnname body; ++ print_feature_test_end features; ++ end + + (* When this function processes the element types in the ops table, it rewrites + them in a list of tuples (a,b,c): --- a/src/gcc/config/arm/neon.md +++ b/src/gcc/config/arm/neon.md -@@ -156,10 +156,10 @@ +@@ -23,6 +23,7 @@ + (define_c_enum "unspec" [ + UNSPEC_ASHIFT_SIGNED + UNSPEC_ASHIFT_UNSIGNED ++ UNSPEC_LOAD_COUNT + UNSPEC_VABD + UNSPEC_VABDL + UNSPEC_VADD +@@ -156,10 +157,10 @@ (define_attr "vqh_mnem" "vadd,vmin,vmax" (const_string "vadd")) (define_insn "*neon_mov" @@ -49052,7 +55696,7 @@ "TARGET_NEON && (register_operand (operands[0], mode) || register_operand (operands[1], mode))" -@@ -177,20 +177,15 @@ +@@ -177,20 +178,15 @@ if (width == 0) return "vmov.f32\t%P0, %1 @ "; else @@ -49075,7 +55719,25 @@ case 2: gcc_unreachable (); case 4: return "vmov\t%Q0, %R0, %P1 @ "; case 5: return "vmov\t%P0, %Q1, %R1 @ "; -@@ -422,30 +417,33 @@ +@@ -198,7 +194,7 @@ + } + } + [(set_attr "neon_type" "neon_int_1,*,neon_vmov,*,neon_mrrc,neon_mcr_2_mcrr,*,*,*") +- (set_attr "type" "*,f_stored,*,f_loadd,*,*,alu,load2,store2") ++ (set_attr "type" "*,f_stored,*,f_loadd,*,*,alu_reg,load2,store2") + (set_attr "insn" "*,*,*,*,*,*,mov,*,*") + (set_attr "length" "4,4,4,4,4,4,8,8,8") + (set_attr "pool_range" "*,*,*,1020,*,*,*,1020,*") +@@ -243,7 +239,7 @@ + } + [(set_attr "neon_type" "neon_int_1,neon_stm_2,neon_vmov,neon_ldm_2,\ + neon_mrrc,neon_mcr_2_mcrr,*,*,*") +- (set_attr "type" "*,*,*,*,*,*,alu,load4,store4") ++ (set_attr "type" "*,*,*,*,*,*,alu_reg,load4,store4") + (set_attr "insn" "*,*,*,*,*,*,mov,*,*") + (set_attr "length" "4,8,4,8,8,8,16,8,16") + (set_attr "pool_range" "*,*,*,1020,*,*,*,1020,*") +@@ -422,30 +418,33 @@ [(set_attr "neon_type" "neon_vld1_1_2_regs")]) (define_insn "vec_set_internal" @@ -49120,7 +55782,7 @@ "TARGET_NEON" { HOST_WIDE_INT elem = ffs ((int) INTVAL (operands[2])) - 1; -@@ -460,18 +458,21 @@ +@@ -460,18 +459,21 @@ operands[0] = gen_rtx_REG (mode, regno + hi); operands[2] = GEN_INT (elt); @@ -49148,7 +55810,7 @@ "TARGET_NEON" { HOST_WIDE_INT elem = ffs ((int) INTVAL (operands[2])) - 1; -@@ -479,9 +480,12 @@ +@@ -479,9 +481,12 @@ operands[0] = gen_rtx_REG (DImode, regno); @@ -49163,7 +55825,7 @@ ) (define_expand "vec_set" -@@ -497,10 +501,10 @@ +@@ -497,10 +502,10 @@ }) (define_insn "vec_extract" @@ -49177,7 +55839,7 @@ "TARGET_NEON" { if (BYTES_BIG_ENDIAN) -@@ -509,16 +513,20 @@ +@@ -509,16 +514,20 @@ elt = GET_MODE_NUNITS (mode) - 1 - elt; operands[2] = GEN_INT (elt); } @@ -49203,7 +55865,7 @@ "TARGET_NEON" { int half_elts = GET_MODE_NUNITS (mode) / 2; -@@ -532,25 +540,31 @@ +@@ -532,25 +541,31 @@ operands[1] = gen_rtx_REG (mode, regno + hi); operands[2] = GEN_INT (elt); @@ -49242,7 +55904,7 @@ ) (define_expand "vec_init" -@@ -582,9 +596,9 @@ +@@ -582,9 +597,9 @@ ) (define_insn "adddi3_neon" @@ -49255,7 +55917,7 @@ (clobber (reg:CC CC_REGNUM))] "TARGET_NEON" { -@@ -594,13 +608,16 @@ +@@ -594,13 +609,16 @@ case 3: return "vadd.i64\t%P0, %P1, %P2"; case 1: return "#"; case 2: return "#"; @@ -49272,11 +55934,111 @@ + [(set_attr "neon_type" "neon_int_1,*,*,neon_int_1,*,*,*") + (set_attr "conds" "*,clob,clob,*,clob,clob,clob") + (set_attr "length" "*,8,8,*,8,8,8") -+ (set_attr "arch" "nota8,*,*,onlya8,*,*,*")] ++ (set_attr "arch" "neon_for_64bits,*,*,avoid_neon_for_64bits,*,*,*")] ) (define_insn "*sub3_neon" -@@ -920,6 +937,45 @@ +@@ -637,7 +655,7 @@ + [(set_attr "neon_type" "neon_int_2,*,*,*,neon_int_2") + (set_attr "conds" "*,clob,clob,clob,*") + (set_attr "length" "*,8,8,8,*") +- (set_attr "arch" "nota8,*,*,*,onlya8")] ++ (set_attr "arch" "neon_for_64bits,*,*,*,avoid_neon_for_64bits")] + ) + + (define_insn "*mul3_neon" +@@ -705,6 +723,63 @@ + (const_string "neon_mla_qqq_32_qqd_32_scalar")))))] + ) + ++;; Fused multiply-accumulate ++;; We define each insn twice here: ++;; 1: with flag_unsafe_math_optimizations for the widening multiply phase ++;; to be able to use when converting to FMA. ++;; 2: without flag_unsafe_math_optimizations for the intrinsics to use. ++(define_insn "fma4" ++ [(set (match_operand:VCVTF 0 "register_operand" "=w") ++ (fma:VCVTF (match_operand:VCVTF 1 "register_operand" "w") ++ (match_operand:VCVTF 2 "register_operand" "w") ++ (match_operand:VCVTF 3 "register_operand" "0")))] ++ "TARGET_NEON && TARGET_FMA && flag_unsafe_math_optimizations" ++ "vfma%?.\\t%0, %1, %2" ++ [(set (attr "neon_type") ++ (if_then_else (match_test "") ++ (const_string "neon_fp_vmla_ddd") ++ (const_string "neon_fp_vmla_qqq")))] ++) ++ ++(define_insn "fma4_intrinsic" ++ [(set (match_operand:VCVTF 0 "register_operand" "=w") ++ (fma:VCVTF (match_operand:VCVTF 1 "register_operand" "w") ++ (match_operand:VCVTF 2 "register_operand" "w") ++ (match_operand:VCVTF 3 "register_operand" "0")))] ++ "TARGET_NEON && TARGET_FMA" ++ "vfma%?.\\t%0, %1, %2" ++ [(set (attr "neon_type") ++ (if_then_else (match_test "") ++ (const_string "neon_fp_vmla_ddd") ++ (const_string "neon_fp_vmla_qqq")))] ++) ++ ++(define_insn "*fmsub4" ++ [(set (match_operand:VCVTF 0 "register_operand" "=w") ++ (fma:VCVTF (neg:VCVTF (match_operand:VCVTF 1 "register_operand" "w")) ++ (match_operand:VCVTF 2 "register_operand" "w") ++ (match_operand:VCVTF 3 "register_operand" "0")))] ++ "TARGET_NEON && TARGET_FMA && flag_unsafe_math_optimizations" ++ "vfms%?.\\t%0, %1, %2" ++ [(set (attr "neon_type") ++ (if_then_else (match_test "") ++ (const_string "neon_fp_vmla_ddd") ++ (const_string "neon_fp_vmla_qqq")))] ++) ++ ++(define_insn "fmsub4_intrinsic" ++ [(set (match_operand:VCVTF 0 "register_operand" "=w") ++ (fma:VCVTF (neg:VCVTF (match_operand:VCVTF 1 "register_operand" "w")) ++ (match_operand:VCVTF 2 "register_operand" "w") ++ (match_operand:VCVTF 3 "register_operand" "0")))] ++ "TARGET_NEON && TARGET_FMA" ++ "vfms%?.\\t%0, %1, %2" ++ [(set (attr "neon_type") ++ (if_then_else (match_test "") ++ (const_string "neon_fp_vmla_ddd") ++ (const_string "neon_fp_vmla_qqq")))] ++) ++ + (define_insn "ior3" + [(set (match_operand:VDQ 0 "s_register_operand" "=w,w") + (ior:VDQ (match_operand:VDQ 1 "s_register_operand" "w,0") +@@ -742,7 +817,7 @@ + } + [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*,neon_int_1,neon_int_1") + (set_attr "length" "*,*,8,8,*,*") +- (set_attr "arch" "nota8,nota8,*,*,onlya8,onlya8")] ++ (set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")] + ) + + ;; The concrete forms of the Neon immediate-logic instructions are vbic and +@@ -787,7 +862,7 @@ + } + [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*,neon_int_1,neon_int_1") + (set_attr "length" "*,*,8,8,*,*") +- (set_attr "arch" "nota8,nota8,*,*,onlya8,onlya8")] ++ (set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")] + ) + + (define_insn "orn3_neon" +@@ -883,7 +958,7 @@ + veor\t%P0, %P1, %P2" + [(set_attr "neon_type" "neon_int_1,*,*,neon_int_1") + (set_attr "length" "*,8,8,*") +- (set_attr "arch" "nota8,*,*,onlya8")] ++ (set_attr "arch" "neon_for_64bits,*,*,avoid_neon_for_64bits")] + ) + + (define_insn "one_cmpl2" +@@ -920,6 +995,45 @@ (const_string "neon_int_3")))] ) @@ -49322,7 +56084,230 @@ (define_insn "*umin3_neon" [(set (match_operand:VDQIW 0 "s_register_operand" "=w") (umin:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w") -@@ -2108,7 +2164,7 @@ +@@ -1088,6 +1202,189 @@ + DONE; + }) + ++;; 64-bit shifts ++ ++;; This pattern loads a 32-bit shift count into a 64-bit NEON register, ++;; leaving the upper half uninitalized. This is OK since the shift ++;; instruction only looks at the low 8 bits anyway. To avoid confusing ++;; data flow analysis however, we pretent the full register is set ++;; using an unspec. ++(define_insn "neon_load_count" ++ [(set (match_operand:DI 0 "s_register_operand" "=w,w") ++ (unspec:DI [(match_operand:SI 1 "nonimmediate_operand" "Um,r")] ++ UNSPEC_LOAD_COUNT))] ++ "TARGET_NEON" ++ "@ ++ vld1.32\t{%P0[0]}, %A1 ++ vmov.32\t%P0[0], %1" ++ [(set_attr "neon_type" "neon_vld1_vld2_lane,neon_mcr")] ++) ++ ++(define_insn "ashldi3_neon_noclobber" ++ [(set (match_operand:DI 0 "s_register_operand" "=w,w") ++ (ashift:DI (match_operand:DI 1 "s_register_operand" " w,w") ++ (match_operand:DI 2 "reg_or_int_operand" " i,w")))] ++ "TARGET_NEON && reload_completed ++ && (!CONST_INT_P (operands[2]) ++ || (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 64))" ++ "@ ++ vshl.u64\t%P0, %P1, %2 ++ vshl.u64\t%P0, %P1, %P2" ++ [(set_attr "neon_type" "neon_vshl_ddd,neon_vshl_ddd")] ++) ++ ++(define_insn_and_split "ashldi3_neon" ++ [(set (match_operand:DI 0 "s_register_operand" "= w, w,?&r,?r, ?w,w") ++ (ashift:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, r, 0w,w") ++ (match_operand:SI 2 "general_operand" "rUm, i, r, i,rUm,i"))) ++ (clobber (match_scratch:SI 3 "= X, X,?&r, X, X,X")) ++ (clobber (match_scratch:SI 4 "= X, X,?&r, X, X,X")) ++ (clobber (match_scratch:DI 5 "=&w, X, X, X, &w,X")) ++ (clobber (reg:CC_C CC_REGNUM))] ++ "TARGET_NEON" ++ "#" ++ "TARGET_NEON && reload_completed" ++ [(const_int 0)] ++ " ++ { ++ if (IS_VFP_REGNUM (REGNO (operands[0]))) ++ { ++ if (CONST_INT_P (operands[2])) ++ { ++ if (INTVAL (operands[2]) < 1) ++ { ++ emit_insn (gen_movdi (operands[0], operands[1])); ++ DONE; ++ } ++ else if (INTVAL (operands[2]) > 63) ++ operands[2] = gen_rtx_CONST_INT (VOIDmode, 63); ++ } ++ else ++ { ++ emit_insn (gen_neon_load_count (operands[5], operands[2])); ++ operands[2] = operands[5]; ++ } ++ ++ /* Ditch the unnecessary clobbers. */ ++ emit_insn (gen_ashldi3_neon_noclobber (operands[0], operands[1], ++ operands[2])); ++ } ++ else ++ { ++ if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1) ++ /* This clobbers CC. */ ++ emit_insn (gen_arm_ashldi3_1bit (operands[0], operands[1])); ++ else ++ arm_emit_coreregs_64bit_shift (ASHIFT, operands[0], operands[1], ++ operands[2], operands[3], operands[4]); ++ } ++ DONE; ++ }" ++ [(set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits") ++ (set_attr "opt" "*,*,speed,speed,*,*")] ++) ++ ++; The shift amount needs to be negated for right-shifts ++(define_insn "signed_shift_di3_neon" ++ [(set (match_operand:DI 0 "s_register_operand" "=w") ++ (unspec:DI [(match_operand:DI 1 "s_register_operand" " w") ++ (match_operand:DI 2 "s_register_operand" " w")] ++ UNSPEC_ASHIFT_SIGNED))] ++ "TARGET_NEON && reload_completed" ++ "vshl.s64\t%P0, %P1, %P2" ++ [(set_attr "neon_type" "neon_vshl_ddd")] ++) ++ ++; The shift amount needs to be negated for right-shifts ++(define_insn "unsigned_shift_di3_neon" ++ [(set (match_operand:DI 0 "s_register_operand" "=w") ++ (unspec:DI [(match_operand:DI 1 "s_register_operand" " w") ++ (match_operand:DI 2 "s_register_operand" " w")] ++ UNSPEC_ASHIFT_UNSIGNED))] ++ "TARGET_NEON && reload_completed" ++ "vshl.u64\t%P0, %P1, %P2" ++ [(set_attr "neon_type" "neon_vshl_ddd")] ++) ++ ++(define_insn "ashrdi3_neon_imm_noclobber" ++ [(set (match_operand:DI 0 "s_register_operand" "=w") ++ (ashiftrt:DI (match_operand:DI 1 "s_register_operand" " w") ++ (match_operand:DI 2 "const_int_operand" " i")))] ++ "TARGET_NEON && reload_completed ++ && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 64" ++ "vshr.s64\t%P0, %P1, %2" ++ [(set_attr "neon_type" "neon_vshl_ddd")] ++) ++ ++(define_insn "lshrdi3_neon_imm_noclobber" ++ [(set (match_operand:DI 0 "s_register_operand" "=w") ++ (lshiftrt:DI (match_operand:DI 1 "s_register_operand" " w") ++ (match_operand:DI 2 "const_int_operand" " i")))] ++ "TARGET_NEON && reload_completed ++ && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 64" ++ "vshr.u64\t%P0, %P1, %2" ++ [(set_attr "neon_type" "neon_vshl_ddd")] ++) ++ ++;; ashrdi3_neon ++;; lshrdi3_neon ++(define_insn_and_split "di3_neon" ++ [(set (match_operand:DI 0 "s_register_operand" "= w, w,?&r,?r,?w,?w") ++ (rshifts:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, r,0w, w") ++ (match_operand:SI 2 "reg_or_int_operand" " r, i, r, i, r, i"))) ++ (clobber (match_scratch:SI 3 "=2r, X, &r, X,2r, X")) ++ (clobber (match_scratch:SI 4 "= X, X, &r, X, X, X")) ++ (clobber (match_scratch:DI 5 "=&w, X, X, X,&w, X")) ++ (clobber (reg:CC CC_REGNUM))] ++ "TARGET_NEON" ++ "#" ++ "TARGET_NEON && reload_completed" ++ [(const_int 0)] ++ " ++ { ++ if (IS_VFP_REGNUM (REGNO (operands[0]))) ++ { ++ if (CONST_INT_P (operands[2])) ++ { ++ if (INTVAL (operands[2]) < 1) ++ { ++ emit_insn (gen_movdi (operands[0], operands[1])); ++ DONE; ++ } ++ else if (INTVAL (operands[2]) > 64) ++ operands[2] = gen_rtx_CONST_INT (VOIDmode, 64); ++ ++ /* Ditch the unnecessary clobbers. */ ++ emit_insn (gen_di3_neon_imm_noclobber (operands[0], ++ operands[1], ++ operands[2])); ++ } ++ else ++ { ++ /* We must use a negative left-shift. */ ++ emit_insn (gen_negsi2 (operands[3], operands[2])); ++ emit_insn (gen_neon_load_count (operands[5], operands[3])); ++ emit_insn (gen__shift_di3_neon (operands[0], operands[1], ++ operands[5])); ++ } ++ } ++ else ++ { ++ if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1) ++ /* This clobbers CC. */ ++ emit_insn (gen_arm_di3_1bit (operands[0], operands[1])); ++ else ++ /* This clobbers CC (ASHIFTRT by register only). */ ++ arm_emit_coreregs_64bit_shift (, operands[0], operands[1], ++ operands[2], operands[3], operands[4]); ++ } ++ ++ DONE; ++ }" ++ [(set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits") ++ (set_attr "opt" "*,*,speed,speed,*,*")] ++) ++ + ;; Widening operations + + (define_insn "widen_ssum3" +@@ -1843,6 +2140,32 @@ + DONE; + }) + ++(define_expand "neon_vfma" ++ [(match_operand:VCVTF 0 "s_register_operand") ++ (match_operand:VCVTF 1 "s_register_operand") ++ (match_operand:VCVTF 2 "s_register_operand") ++ (match_operand:VCVTF 3 "s_register_operand") ++ (match_operand:SI 4 "immediate_operand")] ++ "TARGET_NEON && TARGET_FMA" ++{ ++ emit_insn (gen_fma4_intrinsic (operands[0], operands[2], operands[3], ++ operands[1])); ++ DONE; ++}) ++ ++(define_expand "neon_vfms" ++ [(match_operand:VCVTF 0 "s_register_operand") ++ (match_operand:VCVTF 1 "s_register_operand") ++ (match_operand:VCVTF 2 "s_register_operand") ++ (match_operand:VCVTF 3 "s_register_operand") ++ (match_operand:SI 4 "immediate_operand")] ++ "TARGET_NEON && TARGET_FMA" ++{ ++ emit_insn (gen_fmsub4_intrinsic (operands[0], operands[2], operands[3], ++ operands[1])); ++ DONE; ++}) ++ + ; Used for intrinsics when flag_unsafe_math_optimizations is false. + + (define_insn "neon_vmla_unspec" +@@ -2108,7 +2431,7 @@ [(set (match_operand: 0 "s_register_operand" "=w,w") (unspec: [(match_operand:VDQW 1 "s_register_operand" "w,w") @@ -49331,7 +56316,7 @@ (match_operand:SI 3 "immediate_operand" "i,i")] UNSPEC_VCEQ))] "TARGET_NEON" -@@ -2127,7 +2183,7 @@ +@@ -2127,7 +2450,7 @@ [(set (match_operand: 0 "s_register_operand" "=w,w") (unspec: [(match_operand:VDQW 1 "s_register_operand" "w,w") @@ -49340,7 +56325,7 @@ (match_operand:SI 3 "immediate_operand" "i,i")] UNSPEC_VCGE))] "TARGET_NEON" -@@ -2158,7 +2214,7 @@ +@@ -2158,7 +2481,7 @@ [(set (match_operand: 0 "s_register_operand" "=w,w") (unspec: [(match_operand:VDQW 1 "s_register_operand" "w,w") @@ -49349,7 +56334,7 @@ (match_operand:SI 3 "immediate_operand" "i,i")] UNSPEC_VCGT))] "TARGET_NEON" -@@ -2192,7 +2248,7 @@ +@@ -2192,7 +2515,7 @@ [(set (match_operand: 0 "s_register_operand" "=w") (unspec: [(match_operand:VDQW 1 "s_register_operand" "w") @@ -49358,7 +56343,7 @@ (match_operand:SI 3 "immediate_operand" "i")] UNSPEC_VCLE))] "TARGET_NEON" -@@ -2209,7 +2265,7 @@ +@@ -2209,7 +2532,7 @@ [(set (match_operand: 0 "s_register_operand" "=w") (unspec: [(match_operand:VDQW 1 "s_register_operand" "w") @@ -49367,7 +56352,7 @@ (match_operand:SI 3 "immediate_operand" "i")] UNSPEC_VCLT))] "TARGET_NEON" -@@ -2710,14 +2766,24 @@ +@@ -2710,14 +3033,24 @@ }) (define_expand "neon_vget_lanev2di" @@ -49398,7 +56383,7 @@ DONE; }) -@@ -4367,9 +4433,10 @@ +@@ -4367,9 +4700,10 @@ (define_insn "neon_vst1_lane" [(set (match_operand: 0 "neon_struct_operand" "=Um") @@ -49412,7 +56397,7 @@ "TARGET_NEON" { HOST_WIDE_INT lane = INTVAL (operands[2]); -@@ -4388,9 +4455,10 @@ +@@ -4388,9 +4722,10 @@ (define_insn "neon_vst1_lane" [(set (match_operand: 0 "neon_struct_operand" "=Um") @@ -49426,19 +56411,109 @@ "TARGET_NEON" { HOST_WIDE_INT lane = INTVAL (operands[2]); +@@ -5666,3 +6001,65 @@ + (const_string "neon_fp_vadd_qqq_vabs_qq")) + (const_string "neon_int_5")))] + ) ++ ++;; Copy from core-to-neon regs, then extend, not vice-versa ++ ++(define_split ++ [(set (match_operand:DI 0 "s_register_operand" "") ++ (sign_extend:DI (match_operand:SI 1 "s_register_operand" "")))] ++ "TARGET_NEON && reload_completed && IS_VFP_REGNUM (REGNO (operands[0]))" ++ [(set (match_dup 2) (vec_duplicate:V2SI (match_dup 1))) ++ (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 32)))] ++ { ++ operands[2] = gen_rtx_REG (V2SImode, REGNO (operands[0])); ++ }) ++ ++(define_split ++ [(set (match_operand:DI 0 "s_register_operand" "") ++ (sign_extend:DI (match_operand:HI 1 "s_register_operand" "")))] ++ "TARGET_NEON && reload_completed && IS_VFP_REGNUM (REGNO (operands[0]))" ++ [(set (match_dup 2) (vec_duplicate:V4HI (match_dup 1))) ++ (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 48)))] ++ { ++ operands[2] = gen_rtx_REG (V4HImode, REGNO (operands[0])); ++ }) ++ ++(define_split ++ [(set (match_operand:DI 0 "s_register_operand" "") ++ (sign_extend:DI (match_operand:QI 1 "s_register_operand" "")))] ++ "TARGET_NEON && reload_completed && IS_VFP_REGNUM (REGNO (operands[0]))" ++ [(set (match_dup 2) (vec_duplicate:V8QI (match_dup 1))) ++ (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))] ++ { ++ operands[2] = gen_rtx_REG (V8QImode, REGNO (operands[0])); ++ }) ++ ++(define_split ++ [(set (match_operand:DI 0 "s_register_operand" "") ++ (zero_extend:DI (match_operand:SI 1 "s_register_operand" "")))] ++ "TARGET_NEON && reload_completed && IS_VFP_REGNUM (REGNO (operands[0]))" ++ [(set (match_dup 2) (vec_duplicate:V2SI (match_dup 1))) ++ (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 32)))] ++ { ++ operands[2] = gen_rtx_REG (V2SImode, REGNO (operands[0])); ++ }) ++ ++(define_split ++ [(set (match_operand:DI 0 "s_register_operand" "") ++ (zero_extend:DI (match_operand:HI 1 "s_register_operand" "")))] ++ "TARGET_NEON && reload_completed && IS_VFP_REGNUM (REGNO (operands[0]))" ++ [(set (match_dup 2) (vec_duplicate:V4HI (match_dup 1))) ++ (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 48)))] ++ { ++ operands[2] = gen_rtx_REG (V4HImode, REGNO (operands[0])); ++ }) ++ ++(define_split ++ [(set (match_operand:DI 0 "s_register_operand" "") ++ (zero_extend:DI (match_operand:QI 1 "s_register_operand" "")))] ++ "TARGET_NEON && reload_completed && IS_VFP_REGNUM (REGNO (operands[0]))" ++ [(set (match_dup 2) (vec_duplicate:V8QI (match_dup 1))) ++ (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))] ++ { ++ operands[2] = gen_rtx_REG (V8QImode, REGNO (operands[0])); ++ }) --- a/src/gcc/config/arm/neon.ml +++ b/src/gcc/config/arm/neon.ml -@@ -234,7 +234,8 @@ +@@ -102,6 +102,8 @@ + | Vmul + | Vmla + | Vmls ++ | Vfma ++ | Vfms + | Vsub + | Vceq + | Vcge +@@ -234,7 +236,10 @@ cases. The function supplied must return the integer to be written into the testcase for the argument number (0-based) supplied to it. *) | Const_valuator of (int -> int) - | Fixed_return_reg + | Fixed_vector_reg + | Fixed_core_reg ++ (* Mark that the intrinsic requires __ARM_FEATURE_string to be defined. *) ++ | Requires_feature of string exception MixedMode of elts * elts -@@ -999,7 +1000,8 @@ +@@ -760,6 +765,12 @@ + Vmls, [], Long, "vmlsl", elts_same_io, su_8_32; + Vmls, [Saturating; Doubling], Long, "vqdmlsl", elts_same_io, [S16; S32]; + ++ (* Fused-multiply-accumulate. *) ++ Vfma, [Requires_feature "FMA"], All (3, Dreg), "vfma", elts_same_io, [F32]; ++ Vfma, [Requires_feature "FMA"], All (3, Qreg), "vfmaQ", elts_same_io, [F32]; ++ Vfms, [Requires_feature "FMA"], All (3, Dreg), "vfms", elts_same_io, [F32]; ++ Vfms, [Requires_feature "FMA"], All (3, Qreg), "vfmsQ", elts_same_io, [F32]; ++ + (* Subtraction. *) + Vsub, [], All (3, Dreg), "vsub", sign_invar_2, F32 :: su_8_32; + Vsub, [No_op], All (3, Dreg), "vsub", sign_invar_2, [S64; U64]; +@@ -999,7 +1010,8 @@ Vget_lane, [InfoWord; Disassembles_as [Use_operands [| Corereg; Corereg; Dreg |]]; @@ -49448,7 +56523,7 @@ Use_operands [| Corereg; Qreg; Immed |], "vgetQ_lane", notype_2, [S64; U64]; -@@ -1115,7 +1117,7 @@ +@@ -1115,7 +1127,7 @@ notype_1, pf_su_8_64; Vget_low, [Instruction_name ["vmov"]; Disassembles_as [Use_operands [| Dreg; Dreg |]]; @@ -49459,7 +56534,25 @@ Vget_low, [No_op], --- a/src/gcc/config/arm/neon-testgen.ml +++ b/src/gcc/config/arm/neon-testgen.ml -@@ -79,9 +79,12 @@ +@@ -46,13 +46,14 @@ + failwith ("Could not create test source file " ^ name ^ ": " ^ str) + + (* Emit prologue code to a test source file. *) +-let emit_prologue chan test_name = ++let emit_prologue chan test_name effective_target = + Printf.fprintf chan "/* Test the `%s' ARM Neon intrinsic. */\n" test_name; + Printf.fprintf chan "/* This file was autogenerated by neon-testgen. */\n\n"; + Printf.fprintf chan "/* { dg-do assemble } */\n"; +- Printf.fprintf chan "/* { dg-require-effective-target arm_neon_ok } */\n"; ++ Printf.fprintf chan "/* { dg-require-effective-target %s_ok } */\n" ++ effective_target; + Printf.fprintf chan "/* { dg-options \"-save-temps -O0\" } */\n"; +- Printf.fprintf chan "/* { dg-add-options arm_neon } */\n"; ++ Printf.fprintf chan "/* { dg-add-options %s } */\n" effective_target; + Printf.fprintf chan "\n#include \"arm_neon.h\"\n\n"; + Printf.fprintf chan "void test_%s (void)\n{\n" test_name + +@@ -79,9 +80,12 @@ (* The intrinsic returns a value. We need to do explict register allocation for vget_low tests or they fail because of copy elimination. *) @@ -49473,6 +56566,36 @@ else Printf.fprintf chan " %s out_%s;\n" return_ty return_ty); emit ()) +@@ -153,6 +157,17 @@ + then (Const :: flags, String.sub ty 6 ((String.length ty) - 6)) + else (flags, ty)) tys' + ++(* Work out what the effective target should be. *) ++let effective_target features = ++ try ++ match List.find (fun feature -> ++ match feature with Requires_feature _ -> true ++ | _ -> false) ++ features with ++ Requires_feature "FMA" -> "arm_neonv2" ++ | _ -> assert false ++ with Not_found -> "arm_neon" ++ + (* Given an intrinsic shape, produce a regexp that will match + the right-hand sides of instructions generated by an intrinsic of + that shape. *) +@@ -260,8 +275,10 @@ + "!?\\(\\[ \t\\]+@\\[a-zA-Z0-9 \\]+\\)?\\n") + (analyze_all_shapes features shape analyze_shape) + in ++ let effective_target = effective_target features ++ in + (* Emit file and function prologues. *) +- emit_prologue chan test_name; ++ emit_prologue chan test_name effective_target; + (* Emit local variable declarations. *) + emit_automatics chan c_types features; + Printf.fprintf chan "\n"; --- a/src/gcc/config/arm/predicates.md +++ b/src/gcc/config/arm/predicates.md @@ -89,6 +89,15 @@ @@ -49538,9 +56661,82 @@ ;; Predicates for named expanders that overlap multiple ISAs. (define_predicate "cmpdi_operand" +--- a/src/gcc/config/arm/t-arm ++++ b/src/gcc/config/arm/t-arm +@@ -33,6 +33,7 @@ + $(srcdir)/config/arm/constraints.md \ + $(srcdir)/config/arm/cortex-a15.md \ + $(srcdir)/config/arm/cortex-a5.md \ ++ $(srcdir)/config/arm/cortex-a7.md \ + $(srcdir)/config/arm/cortex-a8.md \ + $(srcdir)/config/arm/cortex-a8-neon.md \ + $(srcdir)/config/arm/cortex-a9.md \ --- a/src/gcc/config/arm/thumb2.md +++ b/src/gcc/config/arm/thumb2.md -@@ -677,27 +677,6 @@ +@@ -1,5 +1,5 @@ + ;; ARM Thumb-2 Machine Description +-;; Copyright (C) 2007, 2008, 2010 Free Software Foundation, Inc. ++;; Copyright (C) 2007, 2008, 2010, 2012 Free Software Foundation, Inc. + ;; Written by CodeSourcery, LLC. + ;; + ;; This file is part of GCC. +@@ -141,7 +141,8 @@ + eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31" + [(set_attr "conds" "clob,*") + (set_attr "shift" "1") +- ;; predicable can't be set based on the variant, so left as no ++ (set_attr "predicable" "no, yes") ++ (set_attr "ce_count" "2") + (set_attr "length" "10,8")] + ) + +@@ -155,7 +156,8 @@ + eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31" + [(set_attr "conds" "clob,*") + (set_attr "shift" "1") +- ;; predicable can't be set based on the variant, so left as no ++ (set_attr "predicable" "no, yes") ++ (set_attr "ce_count" "2") + (set_attr "length" "10,8")] + ) + +@@ -180,7 +182,7 @@ + ldr%?\\t%0, %1 + str%?\\t%1, %0 + str%?\\t%1, %0" +- [(set_attr "type" "*,*,*,*,load1,load1,store1,store1") ++ [(set_attr "type" "*,*,simple_alu_imm,*,load1,load1,store1,store1") + (set_attr "predicable" "yes") + (set_attr "pool_range" "*,*,*,*,1020,4096,*,*") + (set_attr "neg_pool_range" "*,*,*,*,0,0,*,*")] +@@ -568,7 +570,7 @@ + "@ + sxtb%?\\t%0, %1 + ldr%(sb%)\\t%0, %1" +- [(set_attr "type" "alu_shift,load_byte") ++ [(set_attr "type" "simple_alu_shift,load_byte") + (set_attr "predicable" "yes") + (set_attr "pool_range" "*,4096") + (set_attr "neg_pool_range" "*,250")] +@@ -581,7 +583,7 @@ + "@ + uxth%?\\t%0, %1 + ldr%(h%)\\t%0, %1" +- [(set_attr "type" "alu_shift,load_byte") ++ [(set_attr "type" "simple_alu_shift,load_byte") + (set_attr "predicable" "yes") + (set_attr "pool_range" "*,4096") + (set_attr "neg_pool_range" "*,250")] +@@ -594,7 +596,7 @@ + "@ + uxtb%(%)\\t%0, %1 + ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2" +- [(set_attr "type" "alu_shift,load_byte") ++ [(set_attr "type" "simple_alu_shift,load_byte") + (set_attr "predicable" "yes") + (set_attr "pool_range" "*,4096") + (set_attr "neg_pool_range" "*,250")] +@@ -677,27 +679,6 @@ (set_attr "length" "2")] ) @@ -49568,7 +56764,7 @@ (define_insn "*thumb2_shiftsi3_short" [(set (match_operand:SI 0 "low_register_operand" "=l,l") (match_operator:SI 3 "shift_operator" -@@ -716,20 +695,6 @@ +@@ -716,20 +697,6 @@ (const_string "alu_shift_reg")))] ) @@ -49589,7 +56785,7 @@ (define_insn "*thumb2_mov_shortim" [(set (match_operand:QHSI 0 "low_register_operand" "=l") (match_operand:QHSI 1 "const_int_operand" "I")) -@@ -740,24 +705,6 @@ +@@ -740,24 +707,6 @@ (set_attr "length" "2")] ) @@ -49614,10 +56810,24 @@ (define_insn "*thumb2_addsi_short" [(set (match_operand:SI 0 "low_register_operand" "=l,l") (plus:SI (match_operand:SI 1 "low_register_operand" "l,0") -@@ -869,35 +816,6 @@ - (set_attr "length" "2,4")] - ) - +@@ -848,8 +797,8 @@ + (define_insn "*thumb2_addsi3_compare0_scratch" + [(set (reg:CC_NOOV CC_REGNUM) + (compare:CC_NOOV +- (plus:SI (match_operand:SI 0 "s_register_operand" "l, r") +- (match_operand:SI 1 "arm_add_operand" "lPv,rIL")) ++ (plus:SI (match_operand:SI 0 "s_register_operand" "l,l, r,r") ++ (match_operand:SI 1 "arm_add_operand" "Pv,l,IL,r")) + (const_int 0)))] + "TARGET_THUMB2" + "* +@@ -866,36 +815,8 @@ + return \"cmn\\t%0, %1\"; + " + [(set_attr "conds" "set") +- (set_attr "length" "2,4")] +-) +- -;; 16-bit encodings of "muls" and "mul". We only use these when -;; optimizing for size since "muls" is slow on all known -;; implementations and since "mul" will be generated by @@ -49645,12 +56855,12 @@ - (mult:SI (match_dup 0) (match_dup 1))) - (clobber (reg:CC CC_REGNUM))])] - "" --) -- ++ (set_attr "length" "2,2,4,4") ++ (set_attr "type" "simple_alu_imm,*,simple_alu_imm,*")] + ) + (define_insn "*thumb2_mulsi_short" - [(set (match_operand:SI 0 "low_register_operand" "=l") - (mult:SI (match_operand:SI 1 "low_register_operand" "%0") -@@ -980,19 +898,6 @@ +@@ -980,19 +901,6 @@ (const_int 8)))] ) @@ -49670,7 +56880,7 @@ (define_insn "*thumb2_one_cmplsi2_short" [(set (match_operand:SI 0 "low_register_operand" "=l") (not:SI (match_operand:SI 1 "low_register_operand" "l"))) -@@ -1003,19 +908,6 @@ +@@ -1003,19 +911,6 @@ (set_attr "length" "2")] ) @@ -49690,17 +56900,45 @@ (define_insn "*thumb2_negsi2_short" [(set (match_operand:SI 0 "low_register_operand" "=l") (neg:SI (match_operand:SI 1 "low_register_operand" "l"))) +--- a/src/gcc/config/arm/vfp11.md ++++ b/src/gcc/config/arm/vfp11.md +@@ -56,12 +56,12 @@ + + (define_insn_reservation "vfp_farith" 8 + (and (eq_attr "generic_vfp" "yes") +- (eq_attr "type" "fadds,faddd,fconsts,fconstd,f_cvt,fmuls,fmacs")) ++ (eq_attr "type" "fadds,faddd,fconsts,fconstd,f_cvt,fmuls,fmacs,ffmas")) + "fmac") + + (define_insn_reservation "vfp_fmul" 9 + (and (eq_attr "generic_vfp" "yes") +- (eq_attr "type" "fmuld,fmacd")) ++ (eq_attr "type" "fmuld,fmacd,ffmad")) + "fmac*2") + + (define_insn_reservation "vfp_fdivs" 19 --- a/src/gcc/config/arm/vfp.md +++ b/src/gcc/config/arm/vfp.md -@@ -83,6 +83,7 @@ +@@ -38,6 +38,8 @@ + ;; fmuld Double precision multiply. + ;; fmacs Single precision multiply-accumulate. + ;; fmacd Double precision multiply-accumulate. ++;; ffmas Single precision fused multiply-accumulate. ++;; ffmad Double precision fused multiply-accumulate. + ;; fdivs Single precision sqrt or division. + ;; fdivd Double precision sqrt or division. + ;; f_flag fmstat operation +@@ -82,7 +84,8 @@ + } " [(set_attr "predicable" "yes") - (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores") +- (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores") ++ (set_attr "type" "*,*,simple_alu_imm,simple_alu_imm,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores") + (set_attr "neon_type" "*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*") (set_attr "insn" "mov,mov,mvn,mov,*,*,*,*,*,*,*") (set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*") (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")] -@@ -125,6 +126,7 @@ +@@ -125,6 +128,7 @@ " [(set_attr "predicable" "yes") (set_attr "type" "*,*,*,*,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores") @@ -49708,7 +56946,7 @@ (set_attr "insn" "mov,mov,mvn,mov,*,*,*,*,*,*,*,*,*") (set_attr "pool_range" "*,*,*,*,1020,4096,*,*,*,*,*,1020,*") (set_attr "neg_pool_range" "*,*,*,*, 0, 0,*,*,*,*,*,1008,*")] -@@ -138,7 +140,9 @@ +@@ -138,7 +142,9 @@ (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,r,r,w,w,Uvi,w"))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune != cortexa8 && ( register_operand (operands[0], DImode) @@ -49719,7 +56957,7 @@ "* switch (which_alternative) { -@@ -187,7 +191,8 @@ +@@ -187,7 +193,8 @@ (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,r,r,w,w,Uvi,w"))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune == cortexa8 && ( register_operand (operands[0], DImode) @@ -49729,7 +56967,7 @@ "* switch (which_alternative) { -@@ -213,6 +218,7 @@ +@@ -213,6 +220,7 @@ } " [(set_attr "type" "*,*,*,*,load2,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored") @@ -49737,7 +56975,7 @@ (set (attr "length") (cond [(eq_attr "alternative" "1") (const_int 8) (eq_attr "alternative" "2") (const_int 12) (eq_attr "alternative" "3") (const_int 16) -@@ -371,6 +377,7 @@ +@@ -371,6 +379,7 @@ [(set_attr "predicable" "yes") (set_attr "type" "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*") @@ -49745,7 +56983,7 @@ (set_attr "insn" "*,*,*,*,*,*,*,*,mov") (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*") (set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")] -@@ -408,6 +415,7 @@ +@@ -408,6 +417,7 @@ [(set_attr "predicable" "yes") (set_attr "type" "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*") @@ -49753,7 +56991,7 @@ (set_attr "insn" "*,*,*,*,*,*,*,*,mov") (set_attr "pool_range" "*,*,*,1020,*,4092,*,*,*") (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")] -@@ -451,6 +459,7 @@ +@@ -451,6 +461,7 @@ " [(set_attr "type" "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*") @@ -49761,7 +56999,7 @@ (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8) (eq_attr "alternative" "7") (if_then_else -@@ -494,6 +503,7 @@ +@@ -494,6 +505,7 @@ " [(set_attr "type" "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*") @@ -49769,7 +57007,7 @@ (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8) (eq_attr "alternative" "7") (if_then_else -@@ -528,7 +538,8 @@ +@@ -528,7 +540,8 @@ fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1" [(set_attr "conds" "use") (set_attr "length" "4,4,8,4,4,8,4,4,8") @@ -49779,7 +57017,7 @@ ) (define_insn "*thumb2_movsfcc_vfp" -@@ -551,7 +562,8 @@ +@@ -551,7 +564,8 @@ ite\\t%D3\;fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1" [(set_attr "conds" "use") (set_attr "length" "6,6,10,6,6,10,6,6,10") @@ -49789,7 +57027,7 @@ ) (define_insn "*movdfcc_vfp" -@@ -574,7 +586,8 @@ +@@ -574,7 +588,8 @@ fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1" [(set_attr "conds" "use") (set_attr "length" "4,4,8,4,4,8,4,4,8") @@ -49799,7 +57037,7 @@ ) (define_insn "*thumb2_movdfcc_vfp" -@@ -597,7 +610,8 @@ +@@ -597,7 +612,8 @@ ite\\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1" [(set_attr "conds" "use") (set_attr "length" "6,6,10,6,6,10,6,6,10") @@ -49809,1046 +57047,60 @@ ) ---- a/src/gcc/config/avr/avr.c -+++ b/src/gcc/config/avr/avr.c -@@ -6978,9 +6978,6 @@ - - if (reason) - { -- avr_edump ("%?: %s, %d, %d\n", -- avr_addrspace[as].name, -- avr_addrspace[as].segment, avr_current_device->n_flash); - if (avr_addrspace[as].segment >= avr_current_device->n_flash) - { - if (TYPE_P (node)) ---- a/src/gcc/config/avr/rtems.h -+++ b/src/gcc/config/avr/rtems.h -@@ -23,6 +23,5 @@ - #define TARGET_OS_CPP_BUILTINS() \ - do { \ - builtin_define ("__rtems__"); \ -- builtin_define ("__USE_INIT_FINI__"); \ - builtin_assert ("system=rtems"); \ - } while (0) ---- a/src/gcc/config/i386/driver-i386.c -+++ b/src/gcc/config/i386/driver-i386.c -@@ -398,6 +398,7 @@ - unsigned int has_fma = 0, has_fma4 = 0, has_xop = 0; - unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0; - unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0; -+ unsigned int has_osxsave = 0; - - bool arch; - -@@ -439,6 +440,7 @@ - has_sse4_1 = ecx & bit_SSE4_1; - has_sse4_2 = ecx & bit_SSE4_2; - has_avx = ecx & bit_AVX; -+ has_osxsave = ecx & bit_OSXSAVE; - has_cmpxchg16b = ecx & bit_CMPXCHG16B; - has_movbe = ecx & bit_MOVBE; - has_popcnt = ecx & bit_POPCNT; -@@ -464,6 +466,27 @@ - has_fsgsbase = ebx & bit_FSGSBASE; - } +@@ -886,6 +902,54 @@ + (set_attr "type" "fmacd")] + ) -+ /* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv. */ -+#define XCR_XFEATURE_ENABLED_MASK 0x0 -+#define XSTATE_FP 0x1 -+#define XSTATE_SSE 0x2 -+#define XSTATE_YMM 0x4 -+ if (has_osxsave) -+ asm (".byte 0x0f; .byte 0x01; .byte 0xd0" -+ : "=a" (eax), "=d" (edx) -+ : "c" (XCR_XFEATURE_ENABLED_MASK)); -+ -+ /* Check if SSE and YMM states are supported. */ -+ if (!has_osxsave -+ || (eax & (XSTATE_SSE | XSTATE_YMM)) != (XSTATE_SSE | XSTATE_YMM)) -+ { -+ has_avx = 0; -+ has_avx2 = 0; -+ has_fma = 0; -+ has_fma4 = 0; -+ has_xop = 0; -+ } ++;; Fused-multiply-accumulate + - /* Check cpuid level of extended features. */ - __cpuid (0x80000000, ext_level, ebx, ecx, edx); - ---- a/src/gcc/config/i386/fmaintrin.h -+++ b/src/gcc/config/i386/fmaintrin.h -@@ -1,4 +1,4 @@ --/* Copyright (C) 2011 Free Software Foundation, Inc. -+/* Copyright (C) 2011, 2012 Free Software Foundation, Inc. - - This file is part of GCC. - -@@ -164,7 +164,7 @@ - __attribute__((__gnu_inline__, __always_inline__, __artificial__)) - _mm_fnmadd_sd (__m128d __A, __m128d __B, __m128d __C) - { -- return (__m128d)__builtin_ia32_vfmaddsd3 (-(__v2df)__A, (__v2df)__B, -+ return (__m128d)__builtin_ia32_vfmaddsd3 ((__v2df)__A, -(__v2df)__B, - (__v2df)__C); - } - -@@ -172,7 +172,7 @@ - __attribute__((__gnu_inline__, __always_inline__, __artificial__)) - _mm_fnmadd_ss (__m128 __A, __m128 __B, __m128 __C) - { -- return (__m128)__builtin_ia32_vfmaddss3 (-(__v4sf)__A, (__v4sf)__B, -+ return (__m128)__builtin_ia32_vfmaddss3 ((__v4sf)__A, -(__v4sf)__B, - (__v4sf)__C); - } - -@@ -212,7 +212,7 @@ - __attribute__((__gnu_inline__, __always_inline__, __artificial__)) - _mm_fnmsub_sd (__m128d __A, __m128d __B, __m128d __C) - { -- return (__m128d)__builtin_ia32_vfmaddsd3 (-(__v2df)__A, (__v2df)__B, -+ return (__m128d)__builtin_ia32_vfmaddsd3 ((__v2df)__A, -(__v2df)__B, - -(__v2df)__C); - } - -@@ -220,7 +220,7 @@ - __attribute__((__gnu_inline__, __always_inline__, __artificial__)) - _mm_fnmsub_ss (__m128 __A, __m128 __B, __m128 __C) - { -- return (__m128)__builtin_ia32_vfmaddss3 (-(__v4sf)__A, (__v4sf)__B, -+ return (__m128)__builtin_ia32_vfmaddss3 ((__v4sf)__A, -(__v4sf)__B, - -(__v4sf)__C); - } - ---- a/src/gcc/config/i386/i386.c -+++ b/src/gcc/config/i386/i386.c -@@ -10339,7 +10339,7 @@ - rtx eax = gen_rtx_REG (Pmode, AX_REG); - rtx r10 = NULL; - rtx (*adjust_stack_insn)(rtx, rtx, rtx); -- -+ const bool sp_is_cfa_reg = (m->fs.cfa_reg == stack_pointer_rtx); - bool eax_live = false; - bool r10_live = false; - -@@ -10348,16 +10348,31 @@ - if (!TARGET_64BIT_MS_ABI) - eax_live = ix86_eax_live_at_start_p (); - -+ /* Note that SEH directives need to continue tracking the stack -+ pointer even after the frame pointer has been set up. */ - if (eax_live) - { -- emit_insn (gen_push (eax)); -+ insn = emit_insn (gen_push (eax)); - allocate -= UNITS_PER_WORD; -+ if (sp_is_cfa_reg || TARGET_SEH) -+ { -+ if (sp_is_cfa_reg) -+ m->fs.cfa_offset += UNITS_PER_WORD; -+ RTX_FRAME_RELATED_P (insn) = 1; -+ } - } -+ - if (r10_live) - { - r10 = gen_rtx_REG (Pmode, R10_REG); -- emit_insn (gen_push (r10)); -+ insn = emit_insn (gen_push (r10)); - allocate -= UNITS_PER_WORD; -+ if (sp_is_cfa_reg || TARGET_SEH) -+ { -+ if (sp_is_cfa_reg) -+ m->fs.cfa_offset += UNITS_PER_WORD; -+ RTX_FRAME_RELATED_P (insn) = 1; -+ } - } - - emit_move_insn (eax, GEN_INT (allocate)); -@@ -10371,13 +10386,10 @@ - insn = emit_insn (adjust_stack_insn (stack_pointer_rtx, - stack_pointer_rtx, eax)); - -- /* Note that SEH directives need to continue tracking the stack -- pointer even after the frame pointer has been set up. */ -- if (m->fs.cfa_reg == stack_pointer_rtx || TARGET_SEH) -+ if (sp_is_cfa_reg || TARGET_SEH) - { -- if (m->fs.cfa_reg == stack_pointer_rtx) -+ if (sp_is_cfa_reg) - m->fs.cfa_offset += allocate; -- - RTX_FRAME_RELATED_P (insn) = 1; - add_reg_note (insn, REG_FRAME_RELATED_EXPR, - gen_rtx_SET (VOIDmode, stack_pointer_rtx, -@@ -11402,10 +11414,6 @@ - if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) - return false; - -- /* simplify_subreg does not handle stack pointer. */ -- if (REGNO (op) == STACK_POINTER_REGNUM) -- return false; -- - /* Allow only SUBREGs of non-eliminable hard registers. */ - return register_no_elim_operand (op, mode); - } -@@ -13680,15 +13688,9 @@ - print_reg (rtx x, int code, FILE *file) - { - const char *reg; -+ unsigned int regno; - bool duplicated = code == 'd' && TARGET_AVX; - -- gcc_assert (x == pc_rtx -- || (REGNO (x) != ARG_POINTER_REGNUM -- && REGNO (x) != FRAME_POINTER_REGNUM -- && REGNO (x) != FLAGS_REG -- && REGNO (x) != FPSR_REG -- && REGNO (x) != FPCR_REG)); -- - if (ASSEMBLER_DIALECT == ASM_ATT) - putc ('%', file); - -@@ -13699,6 +13701,13 @@ - return; - } - -+ regno = true_regnum (x); -+ gcc_assert (regno != ARG_POINTER_REGNUM -+ && regno != FRAME_POINTER_REGNUM -+ && regno != FLAGS_REG -+ && regno != FPSR_REG -+ && regno != FPCR_REG); -+ - if (code == 'w' || MMX_REG_P (x)) - code = 2; - else if (code == 'b') -@@ -13720,11 +13729,11 @@ - - /* Irritatingly, AMD extended registers use different naming convention - from the normal registers: "r%d[bwd]" */ -- if (REX_INT_REG_P (x)) -+ if (REX_INT_REGNO_P (regno)) - { - gcc_assert (TARGET_64BIT); - putc ('r', file); -- fprint_ul (file, REGNO (x) - FIRST_REX_INT_REG + 8); -+ fprint_ul (file, regno - FIRST_REX_INT_REG + 8); - switch (code) - { - case 0: -@@ -13768,24 +13777,24 @@ - case 16: - case 2: - normal: -- reg = hi_reg_name[REGNO (x)]; -+ reg = hi_reg_name[regno]; - break; - case 1: -- if (REGNO (x) >= ARRAY_SIZE (qi_reg_name)) -+ if (regno >= ARRAY_SIZE (qi_reg_name)) - goto normal; -- reg = qi_reg_name[REGNO (x)]; -+ reg = qi_reg_name[regno]; - break; - case 0: -- if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name)) -+ if (regno >= ARRAY_SIZE (qi_high_reg_name)) - goto normal; -- reg = qi_high_reg_name[REGNO (x)]; -+ reg = qi_high_reg_name[regno]; - break; - case 32: - if (SSE_REG_P (x)) - { - gcc_assert (!duplicated); - putc ('y', file); -- fputs (hi_reg_name[REGNO (x)] + 1, file); -+ fputs (hi_reg_name[regno] + 1, file); - return; - } - break; -@@ -14560,22 +14569,6 @@ - - gcc_assert (ok); - -- if (parts.base && GET_CODE (parts.base) == SUBREG) -- { -- rtx tmp = SUBREG_REG (parts.base); -- parts.base = simplify_subreg (GET_MODE (parts.base), -- tmp, GET_MODE (tmp), 0); -- gcc_assert (parts.base != NULL_RTX); -- } -- -- if (parts.index && GET_CODE (parts.index) == SUBREG) -- { -- rtx tmp = SUBREG_REG (parts.index); -- parts.index = simplify_subreg (GET_MODE (parts.index), -- tmp, GET_MODE (tmp), 0); -- gcc_assert (parts.index != NULL_RTX); -- } -- - base = parts.base; - index = parts.index; - disp = parts.disp; -@@ -14628,19 +14621,24 @@ - else - { - /* Print SImode register names to force addr32 prefix. */ -- if (GET_CODE (addr) == SUBREG) -- { -- gcc_assert (TARGET_64BIT); -- gcc_assert (GET_MODE (addr) == SImode); -- gcc_assert (GET_MODE (SUBREG_REG (addr)) == DImode); -- gcc_assert (!code); -- code = 'l'; -- } -- else if (GET_CODE (addr) == ZERO_EXTEND -- || GET_CODE (addr) == AND) -+ if (SImode_address_operand (addr, VOIDmode)) - { -+#ifdef ENABLE_CHECKING - gcc_assert (TARGET_64BIT); -- gcc_assert (GET_MODE (addr) == DImode); -+ switch (GET_CODE (addr)) -+ { -+ case SUBREG: -+ gcc_assert (GET_MODE (addr) == SImode); -+ gcc_assert (GET_MODE (SUBREG_REG (addr)) == DImode); -+ break; -+ case ZERO_EXTEND: -+ case AND: -+ gcc_assert (GET_MODE (addr) == DImode); -+ break; -+ default: -+ gcc_unreachable (); -+ } -+#endif - gcc_assert (!code); - code = 'l'; - } -@@ -15708,7 +15706,8 @@ - { - rtx m; - rtx (*extract) (rtx, rtx, rtx); -- rtx (*move_unaligned) (rtx, rtx); -+ rtx (*load_unaligned) (rtx, rtx); -+ rtx (*store_unaligned) (rtx, rtx); - enum machine_mode mode; - - switch (GET_MODE (op0)) -@@ -15717,39 +15716,52 @@ - gcc_unreachable (); - case V32QImode: - extract = gen_avx_vextractf128v32qi; -- move_unaligned = gen_avx_movdqu256; -+ load_unaligned = gen_avx_loaddqu256; -+ store_unaligned = gen_avx_storedqu256; - mode = V16QImode; - break; - case V8SFmode: - extract = gen_avx_vextractf128v8sf; -- move_unaligned = gen_avx_movups256; -+ load_unaligned = gen_avx_loadups256; -+ store_unaligned = gen_avx_storeups256; - mode = V4SFmode; - break; - case V4DFmode: - extract = gen_avx_vextractf128v4df; -- move_unaligned = gen_avx_movupd256; -+ load_unaligned = gen_avx_loadupd256; -+ store_unaligned = gen_avx_storeupd256; - mode = V2DFmode; - break; - } - -- if (MEM_P (op1) && TARGET_AVX256_SPLIT_UNALIGNED_LOAD) -+ if (MEM_P (op1)) - { -- rtx r = gen_reg_rtx (mode); -- m = adjust_address (op1, mode, 0); -- emit_move_insn (r, m); -- m = adjust_address (op1, mode, 16); -- r = gen_rtx_VEC_CONCAT (GET_MODE (op0), r, m); -- emit_move_insn (op0, r); -+ if (TARGET_AVX256_SPLIT_UNALIGNED_LOAD) -+ { -+ rtx r = gen_reg_rtx (mode); -+ m = adjust_address (op1, mode, 0); -+ emit_move_insn (r, m); -+ m = adjust_address (op1, mode, 16); -+ r = gen_rtx_VEC_CONCAT (GET_MODE (op0), r, m); -+ emit_move_insn (op0, r); -+ } -+ else -+ emit_insn (load_unaligned (op0, op1)); - } -- else if (MEM_P (op0) && TARGET_AVX256_SPLIT_UNALIGNED_STORE) -+ else if (MEM_P (op0)) - { -- m = adjust_address (op0, mode, 0); -- emit_insn (extract (m, op1, const0_rtx)); -- m = adjust_address (op0, mode, 16); -- emit_insn (extract (m, op1, const1_rtx)); -+ if (TARGET_AVX256_SPLIT_UNALIGNED_STORE) -+ { -+ m = adjust_address (op0, mode, 0); -+ emit_insn (extract (m, op1, const0_rtx)); -+ m = adjust_address (op0, mode, 16); -+ emit_insn (extract (m, op1, const1_rtx)); -+ } -+ else -+ emit_insn (store_unaligned (op0, op1)); - } - else -- emit_insn (move_unaligned (op0, op1)); -+ gcc_unreachable (); - } - - /* Implement the movmisalign patterns for SSE. Non-SSE modes go -@@ -15808,6 +15820,7 @@ - ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[]) - { - rtx op0, op1, m; -+ rtx (*move_unaligned) (rtx, rtx); - - op0 = operands[0]; - op1 = operands[1]; -@@ -15824,14 +15837,28 @@ - /* If we're optimizing for size, movups is the smallest. */ - if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL) - { -+ if (MEM_P (op1)) -+ move_unaligned = gen_sse_loadups; -+ else if (MEM_P (op0)) -+ move_unaligned = gen_sse_storeups; -+ else -+ gcc_unreachable (); -+ - op0 = gen_lowpart (V4SFmode, op0); - op1 = gen_lowpart (V4SFmode, op1); -- emit_insn (gen_sse_movups (op0, op1)); -+ emit_insn (move_unaligned (op0, op1)); - return; - } -+ if (MEM_P (op1)) -+ move_unaligned = gen_sse2_loaddqu; -+ else if (MEM_P (op0)) -+ move_unaligned = gen_sse2_storedqu; -+ else -+ gcc_unreachable (); -+ - op0 = gen_lowpart (V16QImode, op0); - op1 = gen_lowpart (V16QImode, op1); -- emit_insn (gen_sse2_movdqu (op0, op1)); -+ emit_insn (move_unaligned (op0, op1)); - break; - case 32: - op0 = gen_lowpart (V32QImode, op0); -@@ -15849,7 +15876,14 @@ - switch (mode) - { - case V4SFmode: -- emit_insn (gen_sse_movups (op0, op1)); -+ if (MEM_P (op1)) -+ move_unaligned = gen_sse_loadups; -+ else if (MEM_P (op0)) -+ move_unaligned = gen_sse_storeups; -+ else -+ gcc_unreachable (); -+ -+ emit_insn (move_unaligned (op0, op1)); - break; - case V8SFmode: - ix86_avx256_split_vector_move_misalign (op0, op1); -@@ -15857,12 +15891,26 @@ - case V2DFmode: - if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL) - { -+ if (MEM_P (op1)) -+ move_unaligned = gen_sse_loadups; -+ else if (MEM_P (op0)) -+ move_unaligned = gen_sse_storeups; -+ else -+ gcc_unreachable (); ++(define_insn "fma4" ++ [(set (match_operand:SDF 0 "register_operand" "=") ++ (fma:SDF (match_operand:SDF 1 "register_operand" "") ++ (match_operand:SDF 2 "register_operand" "") ++ (match_operand:SDF 3 "register_operand" "0")))] ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA" ++ "vfma%?.\\t%0, %1, %2" ++ [(set_attr "predicable" "yes") ++ (set_attr "type" "ffma")] ++) + - op0 = gen_lowpart (V4SFmode, op0); - op1 = gen_lowpart (V4SFmode, op1); -- emit_insn (gen_sse_movups (op0, op1)); -+ emit_insn (move_unaligned (op0, op1)); - return; - } -- emit_insn (gen_sse2_movupd (op0, op1)); -+ if (MEM_P (op1)) -+ move_unaligned = gen_sse2_loadupd; -+ else if (MEM_P (op0)) -+ move_unaligned = gen_sse2_storeupd; -+ else -+ gcc_unreachable (); ++(define_insn "*fmsub4" ++ [(set (match_operand:SDF 0 "register_operand" "=") ++ (fma:SDF (neg:SDF (match_operand:SDF 1 "register_operand" ++ "")) ++ (match_operand:SDF 2 "register_operand" "") ++ (match_operand:SDF 3 "register_operand" "0")))] ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA" ++ "vfms%?.\\t%0, %1, %2" ++ [(set_attr "predicable" "yes") ++ (set_attr "type" "ffma")] ++) + -+ emit_insn (move_unaligned (op0, op1)); - break; - case V4DFmode: - ix86_avx256_split_vector_move_misalign (op0, op1); -@@ -15887,7 +15935,7 @@ - { - op0 = gen_lowpart (V4SFmode, op0); - op1 = gen_lowpart (V4SFmode, op1); -- emit_insn (gen_sse_movups (op0, op1)); -+ emit_insn (gen_sse_loadups (op0, op1)); - return; - } - -@@ -15898,7 +15946,7 @@ - { - op0 = gen_lowpart (V16QImode, op0); - op1 = gen_lowpart (V16QImode, op1); -- emit_insn (gen_sse2_movdqu (op0, op1)); -+ emit_insn (gen_sse2_loaddqu (op0, op1)); - return; - } - -@@ -15910,7 +15958,7 @@ - { - op0 = gen_lowpart (V2DFmode, op0); - op1 = gen_lowpart (V2DFmode, op1); -- emit_insn (gen_sse2_movupd (op0, op1)); -+ emit_insn (gen_sse2_loadupd (op0, op1)); - return; - } - -@@ -15945,7 +15993,7 @@ - { - op0 = gen_lowpart (V4SFmode, op0); - op1 = gen_lowpart (V4SFmode, op1); -- emit_insn (gen_sse_movups (op0, op1)); -+ emit_insn (gen_sse_loadups (op0, op1)); - return; - } - -@@ -15970,7 +16018,7 @@ - { - op0 = gen_lowpart (V4SFmode, op0); - op1 = gen_lowpart (V4SFmode, op1); -- emit_insn (gen_sse_movups (op0, op1)); -+ emit_insn (gen_sse_storeups (op0, op1)); - return; - } - -@@ -15981,7 +16029,7 @@ - { - op0 = gen_lowpart (V16QImode, op0); - op1 = gen_lowpart (V16QImode, op1); -- emit_insn (gen_sse2_movdqu (op0, op1)); -+ emit_insn (gen_sse2_storedqu (op0, op1)); - return; - } - -@@ -15991,7 +16039,7 @@ - { - op0 = gen_lowpart (V2DFmode, op0); - op1 = gen_lowpart (V2DFmode, op1); -- emit_insn (gen_sse2_movupd (op0, op1)); -+ emit_insn (gen_sse2_storeupd (op0, op1)); - } - else - { -@@ -16009,7 +16057,7 @@ - if (TARGET_SSE_UNALIGNED_STORE_OPTIMAL) - { - op0 = gen_lowpart (V4SFmode, op0); -- emit_insn (gen_sse_movups (op0, op1)); -+ emit_insn (gen_sse_storeups (op0, op1)); - } - else - { -@@ -23308,10 +23356,10 @@ - - /* Calculate the length of the memory address in the instruction encoding. - Includes addr32 prefix, does not include the one-byte modrm, opcode, -- or other prefixes. */ -+ or other prefixes. We never generate addr32 prefix for LEA insn. */ - - int --memory_address_length (rtx addr) -+memory_address_length (rtx addr, bool lea) - { - struct ix86_address parts; - rtx base, index, disp; -@@ -23327,18 +23375,26 @@ - ok = ix86_decompose_address (addr, &parts); - gcc_assert (ok); - -- if (parts.base && GET_CODE (parts.base) == SUBREG) -- parts.base = SUBREG_REG (parts.base); -- if (parts.index && GET_CODE (parts.index) == SUBREG) -- parts.index = SUBREG_REG (parts.index); -+ len = (parts.seg == SEG_DEFAULT) ? 0 : 1; -+ -+ /* If this is not LEA instruction, add the length of addr32 prefix. */ -+ if (TARGET_64BIT && !lea -+ && (SImode_address_operand (addr, VOIDmode) -+ || (parts.base && GET_MODE (parts.base) == SImode) -+ || (parts.index && GET_MODE (parts.index) == SImode))) -+ len++; - - base = parts.base; - index = parts.index; - disp = parts.disp; - -- /* Add length of addr32 prefix. */ -- len = (GET_CODE (addr) == ZERO_EXTEND -- || GET_CODE (addr) == AND); -+ if (base && GET_CODE (base) == SUBREG) -+ base = SUBREG_REG (base); -+ if (index && GET_CODE (index) == SUBREG) -+ index = SUBREG_REG (index); ++(define_insn "*fnmsub4" ++ [(set (match_operand:SDF 0 "register_operand" "=") ++ (fma:SDF (match_operand:SDF 1 "register_operand" "") ++ (match_operand:SDF 2 "register_operand" "") ++ (neg:SDF (match_operand:SDF 3 "register_operand" "0"))))] ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA" ++ "vfnms%?.\\t%0, %1, %2" ++ [(set_attr "predicable" "yes") ++ (set_attr "type" "ffma")] ++) + -+ gcc_assert (base == NULL_RTX || REG_P (base)); -+ gcc_assert (index == NULL_RTX || REG_P (index)); - - /* Rule of thumb: - - esp as the base always wants an index, -@@ -23352,14 +23408,13 @@ - /* esp (for its index) and ebp (for its displacement) need - the two-byte modrm form. Similarly for r12 and r13 in 64-bit - code. */ -- if (REG_P (addr) -- && (addr == arg_pointer_rtx -- || addr == frame_pointer_rtx -- || REGNO (addr) == SP_REG -- || REGNO (addr) == BP_REG -- || REGNO (addr) == R12_REG -- || REGNO (addr) == R13_REG)) -- len = 1; -+ if (base == arg_pointer_rtx -+ || base == frame_pointer_rtx -+ || REGNO (base) == SP_REG -+ || REGNO (base) == BP_REG -+ || REGNO (base) == R12_REG -+ || REGNO (base) == R13_REG) -+ len++; - } - - /* Direct Addressing. In 64-bit mode mod 00 r/m 5 -@@ -23369,7 +23424,7 @@ - by UNSPEC. */ - else if (disp && !base && !index) - { -- len = 4; -+ len += 4; - if (TARGET_64BIT) - { - rtx symbol = disp; -@@ -23387,43 +23442,30 @@ - || (XINT (symbol, 1) != UNSPEC_GOTPCREL - && XINT (symbol, 1) != UNSPEC_PCREL - && XINT (symbol, 1) != UNSPEC_GOTNTPOFF))) -- len += 1; -+ len++; - } - } -- - else - { - /* Find the length of the displacement constant. */ - if (disp) - { - if (base && satisfies_constraint_K (disp)) -- len = 1; -+ len += 1; - else -- len = 4; -+ len += 4; - } - /* ebp always wants a displacement. Similarly r13. */ -- else if (base && REG_P (base) -- && (REGNO (base) == BP_REG || REGNO (base) == R13_REG)) -- len = 1; -+ else if (base && (REGNO (base) == BP_REG || REGNO (base) == R13_REG)) -+ len++; - - /* An index requires the two-byte modrm form.... */ - if (index - /* ...like esp (or r12), which always wants an index. */ - || base == arg_pointer_rtx - || base == frame_pointer_rtx -- || (base && REG_P (base) -- && (REGNO (base) == SP_REG || REGNO (base) == R12_REG))) -- len += 1; -- } -- -- switch (parts.seg) -- { -- case SEG_FS: -- case SEG_GS: -- len += 1; -- break; -- default: -- break; -+ || (base && (REGNO (base) == SP_REG || REGNO (base) == R12_REG))) -+ len++; - } - - return len; -@@ -23477,7 +23519,8 @@ - case MODE_SI: - len = 4; - break; -- /* Immediates for DImode instructions are encoded as 32bit sign extended values. */ -+ /* Immediates for DImode instructions are encoded -+ as 32bit sign extended values. */ - case MODE_DI: - len = 4; - break; -@@ -23487,6 +23530,7 @@ - } - return len; - } ++(define_insn "*fnmadd4" ++ [(set (match_operand:SDF 0 "register_operand" "=") ++ (fma:SDF (neg:SDF (match_operand:SDF 1 "register_operand" ++ "")) ++ (match_operand:SDF 2 "register_operand" "") ++ (neg:SDF (match_operand:SDF 3 "register_operand" "0"))))] ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA" ++ "vfnma%?.\\t%0, %1, %2" ++ [(set_attr "predicable" "yes") ++ (set_attr "type" "ffma")] ++) + - /* Compute default value for "length_address" attribute. */ - int - ix86_attr_length_address_default (rtx insn) -@@ -23503,15 +23547,8 @@ - gcc_assert (GET_CODE (set) == SET); - - addr = SET_SRC (set); -- if (TARGET_64BIT && get_attr_mode (insn) == MODE_SI) -- { -- if (GET_CODE (addr) == ZERO_EXTEND) -- addr = XEXP (addr, 0); -- if (GET_CODE (addr) == SUBREG) -- addr = SUBREG_REG (addr); -- } - -- return memory_address_length (addr); -+ return memory_address_length (addr, true); - } - - extract_insn_cached (insn); -@@ -23533,7 +23570,7 @@ - if (*constraints == 'X') - continue; - } -- return memory_address_length (XEXP (recog_data.operand[i], 0)); -+ return memory_address_length (XEXP (recog_data.operand[i], 0), false); - } - return 0; - } -@@ -25999,9 +26036,9 @@ - { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID }, - - /* SSE */ -- { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF }, -+ { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF }, - { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF }, -- { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT }, -+ { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT }, - - { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF }, - { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF }, -@@ -26015,14 +26052,14 @@ - /* SSE2 */ - { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID }, - { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID }, -- { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF }, -- { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI }, -+ { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF }, -+ { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI }, - { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF }, - { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI }, - { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT }, - { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG }, -- { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE }, -- { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR }, -+ { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE }, -+ { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR }, - - { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE }, - { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE }, -@@ -26047,12 +26084,12 @@ - { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF }, - { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF }, - -- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE }, -- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT }, -- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF }, -- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF }, -- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR }, -- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI }, -+ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE }, -+ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT }, -+ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF }, -+ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF }, -+ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR }, -+ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI }, - { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR }, - - { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI }, ---- a/src/gcc/config/i386/i386.md -+++ b/src/gcc/config/i386/i386.md -@@ -5401,18 +5401,9 @@ - { - rtx addr = operands[1]; - -- if (GET_CODE (addr) == SUBREG) -+ if (SImode_address_operand (addr, VOIDmode)) - { - gcc_assert (TARGET_64BIT); -- gcc_assert (mode == SImode); -- gcc_assert (GET_MODE (SUBREG_REG (addr)) == DImode); -- return "lea{l}\t{%E1, %0|%0, %E1}"; -- } -- else if (GET_CODE (addr) == ZERO_EXTEND -- || GET_CODE (addr) == AND) -- { -- gcc_assert (TARGET_64BIT); -- gcc_assert (mode == DImode); - return "lea{l}\t{%E1, %k0|%k0, %E1}"; - } - else -@@ -5425,7 +5416,11 @@ - DONE; - } - [(set_attr "type" "lea") -- (set_attr "mode" "")]) -+ (set (attr "mode") -+ (if_then_else -+ (match_operand 1 "SImode_address_operand") -+ (const_string "SI") -+ (const_string "")))]) - - ;; Add instructions - -@@ -17700,7 +17695,7 @@ - [(set_attr "type" "sse") - (set_attr "atom_sse_attr" "prefetch") - (set (attr "length_address") -- (symbol_ref "memory_address_length (operands[0])")) -+ (symbol_ref "memory_address_length (operands[0], false)")) - (set_attr "memory" "none")]) - - (define_insn "*prefetch_3dnow" -@@ -17716,7 +17711,7 @@ - } - [(set_attr "type" "mmx") - (set (attr "length_address") -- (symbol_ref "memory_address_length (operands[0])")) -+ (symbol_ref "memory_address_length (operands[0], false)")) - (set_attr "memory" "none")]) - - (define_expand "stack_protect_set" ---- a/src/gcc/config/i386/i386-protos.h -+++ b/src/gcc/config/i386/i386-protos.h -@@ -270,7 +270,7 @@ - }; - - extern int ix86_decompose_address (rtx, struct ix86_address *); --extern int memory_address_length (rtx addr); -+extern int memory_address_length (rtx, bool); - extern void x86_output_aligned_bss (FILE *, tree, const char *, - unsigned HOST_WIDE_INT, int); - extern void x86_elf_aligned_common (FILE *, const char *, ---- a/src/gcc/config/i386/predicates.md -+++ b/src/gcc/config/i386/predicates.md -@@ -822,6 +822,10 @@ - return parts.seg == SEG_DEFAULT; - }) - -+;; Return true for RTX codes that force SImode address. -+(define_predicate "SImode_address_operand" -+ (match_code "subreg,zero_extend,and")) -+ - ;; Return true if op if a valid base register, displacement or - ;; sum of base register and displacement for VSIB addressing. - (define_predicate "vsib_address_operand" -@@ -991,7 +995,7 @@ - ;; by the modRM array. - (define_predicate "long_memory_operand" - (and (match_operand 0 "memory_operand") -- (match_test "memory_address_length (op)"))) -+ (match_test "memory_address_length (op, false)"))) - - ;; Return true if OP is a comparison operator that can be issued by fcmov. - (define_predicate "fcmov_comparison_operator" ---- a/src/gcc/config/i386/sse.md -+++ b/src/gcc/config/i386/sse.md -@@ -21,7 +21,8 @@ - (define_c_enum "unspec" [ - ;; SSE - UNSPEC_MOVNT -- UNSPEC_MOVU -+ UNSPEC_LOADU -+ UNSPEC_STOREU - - ;; SSE3 - UNSPEC_LDDQU -@@ -580,23 +581,51 @@ - DONE; - }) --(define_insn "_movu" -- [(set (match_operand:VF 0 "nonimmediate_operand" "=x,m") -+(define_insn "_loadu" -+ [(set (match_operand:VF 0 "register_operand" "=x") -+ (unspec:VF -+ [(match_operand:VF 1 "memory_operand" "m")] -+ UNSPEC_LOADU))] -+ "TARGET_SSE" -+ "%vmovu\t{%1, %0|%0, %1}" -+ [(set_attr "type" "ssemov") -+ (set_attr "movu" "1") -+ (set_attr "prefix" "maybe_vex") -+ (set_attr "mode" "")]) -+ -+(define_insn "_storeu" -+ [(set (match_operand:VF 0 "memory_operand" "=m") - (unspec:VF -- [(match_operand:VF 1 "nonimmediate_operand" "xm,x")] -- UNSPEC_MOVU))] -- "TARGET_SSE && !(MEM_P (operands[0]) && MEM_P (operands[1]))" -+ [(match_operand:VF 1 "register_operand" "x")] -+ UNSPEC_STOREU))] -+ "TARGET_SSE" - "%vmovu\t{%1, %0|%0, %1}" - [(set_attr "type" "ssemov") - (set_attr "movu" "1") - (set_attr "prefix" "maybe_vex") - (set_attr "mode" "")]) - --(define_insn "_movdqu" -- [(set (match_operand:VI1 0 "nonimmediate_operand" "=x,m") -- (unspec:VI1 [(match_operand:VI1 1 "nonimmediate_operand" "xm,x")] -- UNSPEC_MOVU))] -- "TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))" -+(define_insn "_loaddqu" -+ [(set (match_operand:VI1 0 "register_operand" "=x") -+ (unspec:VI1 [(match_operand:VI1 1 "memory_operand" "m")] -+ UNSPEC_LOADU))] -+ "TARGET_SSE2" -+ "%vmovdqu\t{%1, %0|%0, %1}" -+ [(set_attr "type" "ssemov") -+ (set_attr "movu" "1") -+ (set (attr "prefix_data16") -+ (if_then_else -+ (match_test "TARGET_AVX") -+ (const_string "*") -+ (const_string "1"))) -+ (set_attr "prefix" "maybe_vex") -+ (set_attr "mode" "")]) -+ -+(define_insn "_storedqu" -+ [(set (match_operand:VI1 0 "memory_operand" "=m") -+ (unspec:VI1 [(match_operand:VI1 1 "register_operand" "x")] -+ UNSPEC_STOREU))] -+ "TARGET_SSE2" - "%vmovdqu\t{%1, %0|%0, %1}" - [(set_attr "type" "ssemov") - (set_attr "movu" "1") -@@ -1873,79 +1902,75 @@ - (match_operand:VF_128 1 "nonimmediate_operand") - (match_operand:VF_128 2 "nonimmediate_operand") - (match_operand:VF_128 3 "nonimmediate_operand")) -- (match_dup 0) -+ (match_dup 1) - (const_int 1)))] - "TARGET_FMA") - - (define_insn "*fmai_fmadd_" -- [(set (match_operand:VF_128 0 "register_operand" "=x,x,x") -+ [(set (match_operand:VF_128 0 "register_operand" "=x,x") - (vec_merge:VF_128 - (fma:VF_128 -- (match_operand:VF_128 1 "nonimmediate_operand" "%0, 0,x") -- (match_operand:VF_128 2 "nonimmediate_operand" "xm, x,xm") -- (match_operand:VF_128 3 "nonimmediate_operand" " x,xm,0")) -- (match_dup 0) -+ (match_operand:VF_128 1 "nonimmediate_operand" " 0, 0") -+ (match_operand:VF_128 2 "nonimmediate_operand" "xm, x") -+ (match_operand:VF_128 3 "nonimmediate_operand" " x,xm")) -+ (match_dup 1) - (const_int 1)))] - "TARGET_FMA" - "@ - vfmadd132\t{%2, %3, %0|%0, %3, %2} -- vfmadd213\t{%3, %2, %0|%0, %2, %3} -- vfmadd231\t{%2, %1, %0|%0, %1, %2}" -+ vfmadd213\t{%3, %2, %0|%0, %2, %3}" - [(set_attr "type" "ssemuladd") - (set_attr "mode" "")]) - - (define_insn "*fmai_fmsub_" -- [(set (match_operand:VF_128 0 "register_operand" "=x,x,x") -+ [(set (match_operand:VF_128 0 "register_operand" "=x,x") - (vec_merge:VF_128 - (fma:VF_128 -- (match_operand:VF_128 1 "nonimmediate_operand" "%0, 0,x") -- (match_operand:VF_128 2 "nonimmediate_operand" "xm, x,xm") -+ (match_operand:VF_128 1 "nonimmediate_operand" " 0, 0") -+ (match_operand:VF_128 2 "nonimmediate_operand" "xm, x") - (neg:VF_128 -- (match_operand:VF_128 3 "nonimmediate_operand" " x,xm,0"))) -- (match_dup 0) -+ (match_operand:VF_128 3 "nonimmediate_operand" " x,xm"))) -+ (match_dup 1) - (const_int 1)))] - "TARGET_FMA" - "@ - vfmsub132\t{%2, %3, %0|%0, %3, %2} -- vfmsub213\t{%3, %2, %0|%0, %2, %3} -- vfmsub231\t{%2, %1, %0|%0, %1, %2}" -+ vfmsub213\t{%3, %2, %0|%0, %2, %3}" - [(set_attr "type" "ssemuladd") - (set_attr "mode" "")]) - - (define_insn "*fmai_fnmadd_" -- [(set (match_operand:VF_128 0 "register_operand" "=x,x,x") -+ [(set (match_operand:VF_128 0 "register_operand" "=x,x") - (vec_merge:VF_128 - (fma:VF_128 - (neg:VF_128 -- (match_operand:VF_128 1 "nonimmediate_operand" "%0, 0,x")) -- (match_operand:VF_128 2 "nonimmediate_operand" "xm, x,xm") -- (match_operand:VF_128 3 "nonimmediate_operand" " x,xm,0")) -- (match_dup 0) -+ (match_operand:VF_128 2 "nonimmediate_operand" "xm, x")) -+ (match_operand:VF_128 1 "nonimmediate_operand" " 0, 0") -+ (match_operand:VF_128 3 "nonimmediate_operand" " x,xm")) -+ (match_dup 1) - (const_int 1)))] - "TARGET_FMA" - "@ - vfnmadd132\t{%2, %3, %0|%0, %3, %2} -- vfnmadd213\t{%3, %2, %0|%0, %2, %3} -- vfnmadd231\t{%2, %1, %0|%0, %1, %2}" -+ vfnmadd213\t{%3, %2, %0|%0, %2, %3}" - [(set_attr "type" "ssemuladd") - (set_attr "mode" "")]) - - (define_insn "*fmai_fnmsub_" -- [(set (match_operand:VF_128 0 "register_operand" "=x,x,x") -+ [(set (match_operand:VF_128 0 "register_operand" "=x,x") - (vec_merge:VF_128 - (fma:VF_128 - (neg:VF_128 -- (match_operand:VF_128 1 "nonimmediate_operand" "%0, 0,x")) -- (match_operand:VF_128 2 "nonimmediate_operand" "xm, x,xm") -+ (match_operand:VF_128 2 "nonimmediate_operand" "xm, x")) -+ (match_operand:VF_128 1 "nonimmediate_operand" " 0, 0") - (neg:VF_128 -- (match_operand:VF_128 3 "nonimmediate_operand" " x,xm,0"))) -- (match_dup 0) -+ (match_operand:VF_128 3 "nonimmediate_operand" " x,xm"))) -+ (match_dup 1) - (const_int 1)))] - "TARGET_FMA" - "@ - vfnmsub132\t{%2, %3, %0|%0, %3, %2} -- vfnmsub213\t{%3, %2, %0|%0, %2, %3} -- vfnmsub231\t{%2, %1, %0|%0, %1, %2}" -+ vfnmsub213\t{%3, %2, %0|%0, %2, %3}" - [(set_attr "type" "ssemuladd") - (set_attr "mode" "")]) + ;; Conversion routines --- a/src/gcc/config/m68k/m68k.c +++ b/src/gcc/config/m68k/m68k.c @@ -50861,145 +57113,54 @@ insn_size = sched_ib.filled; } ---- a/src/gcc/config/microblaze/rtems.h -+++ b/src/gcc/config/microblaze/rtems.h -@@ -0,0 +1,25 @@ -+/* Definitions for rtems targeting a microblaze using ELF. -+ Copyright (C) 2012 Free Software Foundation, Inc. -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 3, or (at your option) -+any later version. -+ -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING3. If not see -+. */ -+ -+/* Specify predefined symbols in preprocessor. */ -+ -+#define TARGET_OS_CPP_BUILTINS() do { \ -+ builtin_define( "__rtems__" ); \ -+ builtin_assert( "system=rtems" ); \ -+} while (0) ---- a/src/gcc/config/microblaze/t-rtems -+++ b/src/gcc/config/microblaze/t-rtems -@@ -0,0 +1 @@ -+# Custom multilibs for RTEMS ---- a/src/gcc/config/pa/pa.md -+++ b/src/gcc/config/pa/pa.md -@@ -2881,15 +2881,17 @@ - [(set_attr "type" "store") - (set_attr "length" "4")]) - --(define_insn "" -- [(set (match_operand:HI 0 "register_operand" "=r") -- (plus:HI (match_operand:HI 1 "register_operand" "r") -- (match_operand 2 "const_int_operand" "J")))] -+(define_insn "addhi3" -+ [(set (match_operand:HI 0 "register_operand" "=r,r") -+ (plus:HI (match_operand:HI 1 "register_operand" "%r,r") -+ (match_operand:HI 2 "arith14_operand" "r,J")))] - "" -- "ldo %2(%1),%0" -- [(set_attr "type" "binary") -+ "@ -+ {addl|add,l} %1,%2,%0 -+ ldo %2(%1),%0" -+ [(set_attr "type" "binary,binary") - (set_attr "pa_combine_type" "addmove") -- (set_attr "length" "4")]) -+ (set_attr "length" "4,4")]) - - (define_expand "movqi" - [(set (match_operand:QI 0 "general_operand" "") ---- a/src/gcc/config/rs6000/predicates.md -+++ b/src/gcc/config/rs6000/predicates.md -@@ -891,12 +891,16 @@ +--- a/src/gcc/config/rs6000/rs6000-builtin.def ++++ b/src/gcc/config/rs6000/rs6000-builtin.def +@@ -1430,9 +1430,6 @@ + BU_SPECIAL_X (RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf", RS6000_BTM_FRSQRTES, + RS6000_BTC_FP) + +-BU_SPECIAL_X (RS6000_BUILTIN_BSWAP_HI, "__builtin_bswap16", RS6000_BTM_POWERPC, +- RS6000_BTC_MEM) +- + /* Darwin CfString builtin. */ + BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", RS6000_BTM_POWERPC, + RS6000_BTC_MISC) +--- a/src/gcc/config/rs6000/rs6000.c ++++ b/src/gcc/config/rs6000/rs6000.c +@@ -11388,9 +11388,6 @@ + case RS6000_BUILTIN_RSQRT: + return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2, exp, target); + +- case RS6000_BUILTIN_BSWAP_HI: +- return rs6000_expand_unop_builtin (CODE_FOR_bswaphi2, exp, target); +- + case POWER7_BUILTIN_BPERMD: + return rs6000_expand_binop_builtin (((TARGET_64BIT) + ? CODE_FOR_bpermd_di +@@ -11726,12 +11723,6 @@ + POWER7_BUILTIN_BPERMD, "__builtin_bpermd"); + def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD); + +- /* Don't use builtin_function_type here, as it maps HI/QI to SI. */ +- ftype = build_function_type_list (unsigned_intHI_type_node, +- unsigned_intHI_type_node, +- NULL_TREE); +- def_builtin ("__builtin_bswap16", ftype, RS6000_BUILTIN_BSWAP_HI); +- + #if TARGET_XCOFF + /* AIX libm provides clog as __clog. */ + if ((tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE) +--- a/src/gcc/config/rs6000/rs6000.md ++++ b/src/gcc/config/rs6000/rs6000.md +@@ -2387,7 +2387,7 @@ + (bswap:HI + (match_operand:HI 1 "reg_or_mem_operand" ""))) + (clobber (match_scratch:SI 2 ""))])] +- "" ++ "TARGET_POWERPC" { - if (MEM_P (op)) - { -+ if (! volatile_ok && MEM_VOLATILE_P (op)) -+ return 0; - if (mode == DFmode) - mode = V2DFmode; - else if (mode == DImode) - mode = V2DImode; - else -- gcc_unreachable (); -+ gcc_unreachable (); -+ return memory_address_addr_space_p (mode, XEXP (op, 0), -+ MEM_ADDR_SPACE (op)); - } - return input_operand (op, mode); - }) ---- a/src/gcc/config/s390/s390.c -+++ b/src/gcc/config/s390/s390.c -@@ -1579,6 +1579,7 @@ - break; - case PROCESSOR_2097_Z10: - s390_cost = &z10_cost; -+ break; - case PROCESSOR_2817_Z196: - s390_cost = &z196_cost; - break; ---- a/src/gcc/config/sparc/t-rtems -+++ b/src/gcc/config/sparc/t-rtems -@@ -0,0 +1,22 @@ -+# Copyright (C) 2012 Free Software Foundation, Inc. -+# -+# This file is part of GCC. -+# -+# GCC is free software; you can redistribute it and/or modify -+# it under the terms of the GNU General Public License as published by -+# the Free Software Foundation; either version 3, or (at your option) -+# any later version. -+# -+# GCC is distributed in the hope that it will be useful, -+# but WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+# GNU General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with GCC; see the file COPYING3. If not see -+# . -+# -+ -+MULTILIB_OPTIONS = msoft-float mcpu=v8 -+MULTILIB_DIRNAMES = soft v8 -+MULTILIB_MATCHES = msoft-float=mno-fpu ---- a/src/gcc/config/sparc/t-rtems-64 -+++ b/src/gcc/config/sparc/t-rtems-64 -@@ -0,0 +1,22 @@ -+# Copyright (C) 2012 Free Software Foundation, Inc. -+# -+# This file is part of GCC. -+# -+# GCC is free software; you can redistribute it and/or modify -+# it under the terms of the GNU General Public License as published by -+# the Free Software Foundation; either version 3, or (at your option) -+# any later version. -+# -+# GCC is distributed in the hope that it will be useful, -+# but WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+# GNU General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with GCC; see the file COPYING3. If not see -+# . -+# -+ -+MULTILIB_OPTIONS = msoft-float -+MULTILIB_DIRNAMES = soft -+MULTILIB_MATCHES = msoft-float=mno-fpu + if (!REG_P (operands[0]) && !REG_P (operands[1])) + operands[1] = force_reg (HImode, operands[1]); --- a/src/gcc/config.gcc +++ b/src/gcc/config.gcc @@ -317,6 +317,13 @@ @@ -51016,19 +57177,7 @@ alpha*-*-*) cpu_type=alpha need_64bit_hwint=yes -@@ -692,6 +699,11 @@ - *-*-openbsd2.*|*-*-openbsd3.[012]) - tm_defines="${tm_defines} HAS_LIBC_R=1" ;; - esac -+ case ${target} in -+ *-*-openbsd4.[3-9]|*-*-openbsd[5-9]*) -+ default_use_cxa_atexit=yes -+ ;; -+ esac - ;; - *-*-rtems*) - case ${enable_threads} in -@@ -770,6 +782,27 @@ +@@ -775,6 +782,27 @@ esac case ${target} in @@ -51055,50 +57204,8 @@ + ;; alpha*-*-linux*) tm_file="${tm_file} alpha/elf.h alpha/linux.h alpha/linux-elf.h glibc-stdint.h" - extra_options="${extra_options} alpha/elf.opt" -@@ -1723,6 +1756,14 @@ - c_target_objs="${c_target_objs} microblaze-c.o" - cxx_target_objs="${cxx_target_objs} microblaze-c.o" - ;; -+microblaze*-*-rtems*) -+ tm_file="${tm_file} dbxelf.h" -+ tm_file="${tm_file} microblaze/rtems.h rtems.h newlib-stdint.h" -+ c_target_objs="${c_target_objs} microblaze-c.o" -+ cxx_target_objs="${cxx_target_objs} microblaze-c.o" -+ tmake_file="${tmake_file} microblaze/t-microblaze" -+ tmake_file="${tmake_file} t-rtems microblaze/t-rtems" -+ ;; - microblaze*-*-*) - tm_file="${tm_file} dbxelf.h" - c_target_objs="${c_target_objs} microblaze-c.o" -@@ -1970,7 +2011,7 @@ - tm_file="${tm_file} dbxelf.h elfos.h ${fbsd_tm_file} rs6000/sysv4.h" - extra_options="${extra_options} rs6000/sysv4.opt" - tmake_file="rs6000/t-fprules rs6000/t-ppcos ${tmake_file} rs6000/t-ppccomm" -- case ${host} in -+ case ${target} in - powerpc64*) - tm_file="${tm_file} rs6000/default64.h rs6000/freebsd64.h" - tmake_file="${tmake_file} rs6000/t-freebsd64" -@@ -2404,7 +2445,7 @@ - ;; - sparc-*-rtems*) - tm_file="${tm_file} dbxelf.h elfos.h sparc/sysv4.h sparc/sp-elf.h sparc/rtemself.h rtems.h newlib-stdint.h" -- tmake_file="sparc/t-sparc sparc/t-elf t-rtems" -+ tmake_file="sparc/t-sparc sparc/t-elf sparc/t-rtems t-rtems" - ;; - sparc-*-linux*) - tm_file="${tm_file} dbxelf.h elfos.h sparc/sysv4.h gnu-user.h linux.h glibc-stdint.h sparc/tso.h" -@@ -2457,7 +2498,7 @@ - sparc64-*-rtems*) - tm_file="${tm_file} dbxelf.h elfos.h newlib-stdint.h sparc/sysv4.h sparc/sp64-elf.h sparc/rtemself.h rtems.h" - extra_options="${extra_options}" -- tmake_file="${tmake_file} sparc/t-sparc t-rtems" -+ tmake_file="${tmake_file} sparc/t-sparc sparc/t-rtems-64 t-rtems" - ;; - sparc64-*-linux*) - tm_file="sparc/biarch64.h ${tm_file} dbxelf.h elfos.h sparc/sysv4.h gnu-user.h linux.h glibc-stdint.h sparc/default-64.h sparc/linux64.h sparc/tso.h" -@@ -3024,6 +3065,92 @@ + tmake_file="${tmake_file} alpha/t-linux" +@@ -3042,6 +3070,92 @@ supported_defaults= case "${target}" in @@ -51191,7 +57298,7 @@ alpha*-*-*) supported_defaults="cpu tune" for which in cpu tune; do -@@ -3512,6 +3639,15 @@ +@@ -3530,6 +3644,15 @@ # Set some miscellaneous flags for particular targets. target_cpu_default2= case ${target} in @@ -51209,7 +57316,7 @@ then --- a/src/gcc/configure +++ b/src/gcc/configure -@@ -1655,7 +1655,8 @@ +@@ -1660,7 +1660,8 @@ use sysroot as the system root during the build --with-sysroot[=DIR] search for usr/lib, usr/include, et al, within DIR --with-specs=SPECS add SPECS to driver command-line processing @@ -51219,7 +57326,7 @@ --with-bugurl=URL Direct users to URL to report a bug --with-multilib-list select multilibs (SH and x86-64 only) --with-gnu-ld assume the C compiler uses GNU ld default=no -@@ -7309,7 +7310,7 @@ +@@ -7345,7 +7346,7 @@ *) PKGVERSION="($withval) " ;; esac else @@ -51228,25 +57335,25 @@ fi -@@ -18010,7 +18011,7 @@ +@@ -18046,7 +18047,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF --#line 18013 "configure" -+#line 17974 "configure" +-#line 18049 "configure" ++#line 18050 "configure" #include "confdefs.h" #if HAVE_DLFCN_H -@@ -18116,7 +18117,7 @@ +@@ -18152,7 +18153,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF --#line 18119 "configure" -+#line 18080 "configure" +-#line 18155 "configure" ++#line 18156 "configure" #include "confdefs.h" #if HAVE_DLFCN_H -@@ -23421,6 +23422,19 @@ +@@ -23457,6 +23458,19 @@ tls_first_minor=19 tls_as_opt='--fatal-warnings' ;; @@ -51266,31 +57373,9 @@ powerpc-*-*) conftest_s=' .section ".tdata","awT",@progbits -@@ -26530,7 +26544,9 @@ - $as_echo_n "(cached) " >&6 - else - gcc_cv_ld_no_dot_syms=no -- if test $in_tree_ld = yes ; then -+ if test x"$ld_is_gold" = xyes; then -+ gcc_cv_ld_no_dot_syms=yes -+ elif test $in_tree_ld = yes ; then - if test "$gcc_cv_gld_major_version" -eq 2 -a "$gcc_cv_gld_minor_version" -ge 16 -o "$gcc_cv_gld_major_version" -gt 2; then - gcc_cv_ld_no_dot_syms=yes - fi -@@ -26574,7 +26590,9 @@ - $as_echo_n "(cached) " >&6 - else - gcc_cv_ld_large_toc=no -- if test $in_tree_ld = yes ; then -+ if test x"$ld_is_gold" = xyes; then -+ gcc_cv_ld_large_toc=yes -+ elif test $in_tree_ld = yes ; then - if test "$gcc_cv_gld_major_version" -eq 2 -a "$gcc_cv_gld_minor_version" -ge 21 -o "$gcc_cv_gld_major_version" -gt 2; then - gcc_cv_ld_large_toc=yes - fi --- a/src/gcc/configure.ac +++ b/src/gcc/configure.ac -@@ -803,7 +803,7 @@ +@@ -829,7 +829,7 @@ ) AC_SUBST(CONFIGURE_SPECS) @@ -51299,7 +57384,7 @@ ACX_BUGURL([http://gcc.gnu.org/bugs.html]) # Sanity check enable_languages in case someone does not run the toplevel -@@ -2982,6 +2982,19 @@ +@@ -3008,6 +3008,19 @@ tls_first_minor=19 tls_as_opt='--fatal-warnings' ;; @@ -51319,286 +57404,6 @@ powerpc-*-*) conftest_s=' .section ".tdata","awT",@progbits -@@ -4459,7 +4472,9 @@ - AC_CACHE_CHECK(linker support for omitting dot symbols, - gcc_cv_ld_no_dot_syms, - [gcc_cv_ld_no_dot_syms=no -- if test $in_tree_ld = yes ; then -+ if test x"$ld_is_gold" = xyes; then -+ gcc_cv_ld_no_dot_syms=yes -+ elif test $in_tree_ld = yes ; then - if test "$gcc_cv_gld_major_version" -eq 2 -a "$gcc_cv_gld_minor_version" -ge 16 -o "$gcc_cv_gld_major_version" -gt 2; then - gcc_cv_ld_no_dot_syms=yes - fi -@@ -4496,7 +4511,9 @@ - AC_CACHE_CHECK(linker large toc support, - gcc_cv_ld_large_toc, - [gcc_cv_ld_large_toc=no -- if test $in_tree_ld = yes ; then -+ if test x"$ld_is_gold" = xyes; then -+ gcc_cv_ld_large_toc=yes -+ elif test $in_tree_ld = yes ; then - if test "$gcc_cv_gld_major_version" -eq 2 -a "$gcc_cv_gld_minor_version" -ge 21 -o "$gcc_cv_gld_major_version" -gt 2; then - gcc_cv_ld_large_toc=yes - fi ---- a/src/gcc/cp/ChangeLog -+++ b/src/gcc/cp/ChangeLog -@@ -1,3 +1,30 @@ -+2012-11-05 Jakub Jelinek -+ -+ Backported from mainline -+ 2012-10-23 Jakub Jelinek -+ -+ PR c++/54988 -+ * decl2.c (cplus_decl_attributes): Don't return early -+ if attributes is NULL. -+ -+2012-10-26 Paolo Carlini -+ -+ PR c++/54984 -+ * init.c (build_new): Don't turn a null *init into a pointer to -+ empty vector orig_init. -+ -+2012-10-08 Jakub Jelinek -+ -+ PR c++/54858 -+ * tree.c (cp_tree_equal): Handle FIELD_DECL. -+ -+2012-10-03 Jakub Jelinek -+ -+ PR c++/54777 -+ * semantics.c (cxx_eval_constant_expression) : If -+ not ignoring the second operand, pass the original second operand -+ and not one with stripped nops to cxx_eval_constant_expression. -+ - 2012-09-20 Release Manager - - * GCC 4.7.2 released. ---- a/src/gcc/cp/decl2.c -+++ b/src/gcc/cp/decl2.c -@@ -1302,8 +1302,7 @@ - cplus_decl_attributes (tree *decl, tree attributes, int flags) - { - if (*decl == NULL_TREE || *decl == void_type_node -- || *decl == error_mark_node -- || attributes == NULL_TREE) -+ || *decl == error_mark_node) - return; - - if (processing_template_decl) -@@ -1312,8 +1311,6 @@ - return; - - save_template_attributes (&attributes, decl); -- if (attributes == NULL_TREE) -- return; - } - - cp_check_const_attributes (attributes); ---- a/src/gcc/cp/init.c -+++ b/src/gcc/cp/init.c -@@ -2794,7 +2794,8 @@ - - orig_placement = make_tree_vector_copy (*placement); - orig_nelts = nelts; -- orig_init = make_tree_vector_copy (*init); -+ if (*init) -+ orig_init = make_tree_vector_copy (*init); - - make_args_non_dependent (*placement); - if (nelts) ---- a/src/gcc/cp/semantics.c -+++ b/src/gcc/cp/semantics.c -@@ -7682,6 +7682,7 @@ - /* Check that the LHS is constant and then discard it. */ - cxx_eval_constant_expression (call, op0, allow_non_constant, - false, non_constant_p); -+ op1 = TREE_OPERAND (t, 1); - r = cxx_eval_constant_expression (call, op1, allow_non_constant, - addr, non_constant_p); - } ---- a/src/gcc/cp/tree.c -+++ b/src/gcc/cp/tree.c -@@ -1,7 +1,7 @@ - /* Language-dependent node constructors for parse phase of GNU compiler. - Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, -- 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009, 2010, 2011 -- Free Software Foundation, Inc. -+ 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009, 2010, 2011, -+ 2012 Free Software Foundation, Inc. - Hacked by Michael Tiemann (tiemann@cygnus.com) - - This file is part of GCC. -@@ -2366,6 +2366,7 @@ - - case VAR_DECL: - case CONST_DECL: -+ case FIELD_DECL: - case FUNCTION_DECL: - case TEMPLATE_DECL: - case IDENTIFIER_NODE: ---- a/src/gcc/cse.c -+++ b/src/gcc/cse.c -@@ -2555,7 +2555,7 @@ - Store 1 in DO_NOT_RECORD_P if any subexpression is volatile. - - If HASH_ARG_IN_MEMORY_P is not NULL, store 1 in it if X contains -- a MEM rtx which does not have the RTX_UNCHANGING_P bit set. -+ a MEM rtx which does not have the MEM_READONLY_P flag set. - - Note that cse_insn knows that the hash code of a MEM expression - is just (int) MEM plus the hash code of the address. */ -@@ -2571,7 +2571,7 @@ - /* Hash an rtx X for cse via hash_rtx. - Stores 1 in do_not_record if any subexpression is volatile. - Stores 1 in hash_arg_in_memory if X contains a mem rtx which -- does not have the RTX_UNCHANGING_P bit set. */ -+ does not have the MEM_READONLY_P flag set. */ - - static inline unsigned - canon_hash (rtx x, enum machine_mode mode) ---- a/src/gcc/c-typeck.c -+++ b/src/gcc/c-typeck.c -@@ -3642,7 +3642,13 @@ - "wrong type argument to unary exclamation mark"); - return error_mark_node; - } -- arg = c_objc_common_truthvalue_conversion (location, arg); -+ if (int_operands) -+ { -+ arg = c_objc_common_truthvalue_conversion (location, xarg); -+ arg = remove_c_maybe_const_expr (arg); -+ } -+ else -+ arg = c_objc_common_truthvalue_conversion (location, arg); - ret = invert_truthvalue_loc (location, arg); - /* If the TRUTH_NOT_EXPR has been folded, reset the location. */ - if (EXPR_P (ret) && EXPR_HAS_LOCATION (ret)) -@@ -4862,8 +4868,11 @@ - ret = build_c_cast (loc, type, expr); - if (type_expr) - { -+ bool inner_expr_const = true; -+ ret = c_fully_fold (ret, require_constant_value, &inner_expr_const); - ret = build2 (C_MAYBE_CONST_EXPR, TREE_TYPE (ret), type_expr, ret); -- C_MAYBE_CONST_EXPR_NON_CONST (ret) = !type_expr_const; -+ C_MAYBE_CONST_EXPR_NON_CONST (ret) = !(type_expr_const -+ && inner_expr_const); - SET_EXPR_LOCATION (ret, loc); - } - -@@ -9896,8 +9905,20 @@ - but that does not mean the operands should be - converted to ints! */ - result_type = integer_type_node; -- op0 = c_common_truthvalue_conversion (location, op0); -- op1 = c_common_truthvalue_conversion (location, op1); -+ if (op0_int_operands) -+ { -+ op0 = c_objc_common_truthvalue_conversion (location, orig_op0); -+ op0 = remove_c_maybe_const_expr (op0); -+ } -+ else -+ op0 = c_objc_common_truthvalue_conversion (location, op0); -+ if (op1_int_operands) -+ { -+ op1 = c_objc_common_truthvalue_conversion (location, orig_op1); -+ op1 = remove_c_maybe_const_expr (op1); -+ } -+ else -+ op1 = c_objc_common_truthvalue_conversion (location, op1); - converted = 1; - boolean_op = true; - } -@@ -10609,12 +10630,17 @@ - - int_const = (TREE_CODE (expr) == INTEGER_CST && !TREE_OVERFLOW (expr)); - int_operands = EXPR_INT_CONST_OPERANDS (expr); -- if (int_operands) -- expr = remove_c_maybe_const_expr (expr); -- -- /* ??? Should we also give an error for vectors rather than leaving -- those to give errors later? */ -- expr = c_common_truthvalue_conversion (location, expr); -+ if (int_operands && TREE_CODE (expr) != INTEGER_CST) -+ { -+ expr = remove_c_maybe_const_expr (expr); -+ expr = build2 (NE_EXPR, integer_type_node, expr, -+ convert (TREE_TYPE (expr), integer_zero_node)); -+ expr = note_integer_operands (expr); -+ } -+ else -+ /* ??? Should we also give an error for vectors rather than leaving -+ those to give errors later? */ -+ expr = c_common_truthvalue_conversion (location, expr); - - if (TREE_CODE (expr) == INTEGER_CST && int_operands && !int_const) - { ---- a/src/gcc/DATESTAMP -+++ b/src/gcc/DATESTAMP -@@ -1 +1 @@ --20120920 -+20121106 ---- a/src/gcc/dse.c -+++ b/src/gcc/dse.c -@@ -996,7 +996,32 @@ - insn_info->wild_read = false; - } - --/* Check if EXPR can possibly escape the current function scope. */ -+/* Return whether DECL, a local variable, can possibly escape the current -+ function scope. */ -+ -+static bool -+local_variable_can_escape (tree decl) -+{ -+ if (TREE_ADDRESSABLE (decl)) -+ return true; -+ -+ /* If this is a partitioned variable, we need to consider all the variables -+ in the partition. This is necessary because a store into one of them can -+ be replaced with a store into another and this may not change the outcome -+ of the escape analysis. */ -+ if (cfun->gimple_df->decls_to_pointers != NULL) -+ { -+ void *namep -+ = pointer_map_contains (cfun->gimple_df->decls_to_pointers, decl); -+ if (namep) -+ return TREE_ADDRESSABLE (*(tree *)namep); -+ } -+ -+ return false; -+} -+ -+/* Return whether EXPR can possibly escape the current function scope. */ -+ - static bool - can_escape (tree expr) - { -@@ -1005,7 +1030,11 @@ - return true; - base = get_base_address (expr); - if (DECL_P (base) -- && !may_be_aliased (base)) -+ && !may_be_aliased (base) -+ && !(TREE_CODE (base) == VAR_DECL -+ && !DECL_EXTERNAL (base) -+ && !TREE_STATIC (base) -+ && local_variable_can_escape (base))) - return false; - return true; - } ---- a/src/gcc/dwarf2out.c -+++ b/src/gcc/dwarf2out.c -@@ -8012,6 +8012,8 @@ - return DW_FORM_block1; - case 2: - return DW_FORM_block2; -+ case 4: -+ return DW_FORM_block4; - default: - gcc_unreachable (); - } --- a/src/gcc/flag-types.h +++ b/src/gcc/flag-types.h @@ -106,6 +106,14 @@ @@ -51616,68 +57421,6 @@ /* The algorithm used for the integrated register allocator (IRA). */ enum ira_algorithm { ---- a/src/gcc/fold-const.c -+++ b/src/gcc/fold-const.c -@@ -6781,12 +6781,14 @@ - && TREE_TYPE (TREE_OPERAND (arg1, 0)) == inner_type)) - return NULL_TREE; - -- if ((TYPE_UNSIGNED (inner_type) != TYPE_UNSIGNED (outer_type) -- || POINTER_TYPE_P (inner_type) != POINTER_TYPE_P (outer_type)) -+ if (TYPE_UNSIGNED (inner_type) != TYPE_UNSIGNED (outer_type) - && code != NE_EXPR - && code != EQ_EXPR) - return NULL_TREE; - -+ if (POINTER_TYPE_P (inner_type) != POINTER_TYPE_P (outer_type)) -+ return NULL_TREE; -+ - if (TREE_CODE (arg1) == INTEGER_CST) - arg1 = force_fit_type_double (inner_type, tree_to_double_int (arg1), - 0, TREE_OVERFLOW (arg1)); ---- a/src/gcc/fortran/ChangeLog -+++ b/src/gcc/fortran/ChangeLog -@@ -1,3 +1,9 @@ -+2012-10-14 Janus Weil -+ -+ PR fortran/54784 -+ * trans-stmt.c (gfc_trans_allocate): Correctly determine the reference -+ to the _data component for polymorphic allocation with SOURCE. -+ - 2012-09-20 Release Manager - - * GCC 4.7.2 released. ---- a/src/gcc/fortran/trans-stmt.c -+++ b/src/gcc/fortran/trans-stmt.c -@@ -5087,7 +5087,7 @@ - gfc_actual_arglist *actual; - gfc_expr *ppc; - gfc_code *ppc_code; -- gfc_ref *dataref; -+ gfc_ref *ref, *dataref; - - /* Do a polymorphic deep copy. */ - actual = gfc_get_actual_arglist (); -@@ -5099,13 +5099,15 @@ - actual->next->expr->ts.type = BT_CLASS; - gfc_add_data_component (actual->next->expr); - -- dataref = actual->next->expr->ref; -+ dataref = NULL; - /* Make sure we go up through the reference chain to - the _data reference, where the arrayspec is found. */ -- while (dataref->next && dataref->next->type != REF_ARRAY) -- dataref = dataref->next; -+ for (ref = actual->next->expr->ref; ref; ref = ref->next) -+ if (ref->type == REF_COMPONENT -+ && strcmp (ref->u.c.component->name, "_data") == 0) -+ dataref = ref; - -- if (dataref->u.c.component->as) -+ if (dataref && dataref->u.c.component->as) - { - int dim; - gfc_expr *temp; --- a/src/gcc/fwprop.c +++ b/src/gcc/fwprop.c @@ -664,7 +664,12 @@ @@ -51694,38 +57437,6 @@ flags |= PR_CAN_APPEAR; if (!for_each_rtx (&new_rtx, varying_mem_p, NULL)) flags |= PR_HANDLE_MEM; ---- a/src/gcc/gcc-ar.c -+++ b/src/gcc/gcc-ar.c -@@ -42,6 +42,7 @@ - const char *err_msg; - const char **nargv; - bool is_ar = !strcmp (PERSONALITY, "ar"); -+ int exit_code = FATAL_EXIT_CODE; - - exe_name = PERSONALITY; - #ifdef CROSS_DIRECTORY_STRUCTURE -@@ -96,6 +97,20 @@ - NULL,NULL, &status, &err); - if (err_msg) - fprintf(stderr, "Error running %s: %s\n", exe_name, err_msg); -+ else if (status) -+ { -+ if (WIFSIGNALED (status)) -+ { -+ int sig = WTERMSIG (status); -+ fprintf (stderr, "%s terminated with signal %d [%s]%s\n", -+ exe_name, sig, strsignal(sig), -+ WCOREDUMP(status) ? ", core dumped" : ""); -+ } -+ else if (WIFEXITED (status)) -+ exit_code = WEXITSTATUS (status); -+ } -+ else -+ exit_code = SUCCESS_EXIT_CODE; - -- return err; -+ return exit_code; - } --- a/src/gcc/gengtype-lex.c +++ b/src/gcc/gengtype-lex.c @@ -55,7 +55,6 @@ @@ -51765,8 +57476,8 @@ #define YY_MORE_ADJ 0 #define YY_RESTORE_YY_MORE_OFFSET char *yytext; --#line 1 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 1 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 1 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 1 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" /* -*- indented-text -*- */ /* Process source files and output type information. Copyright (C) 2002, 2003, 2004, 2005, 2007, 2008, 2009, 2010 @@ -51774,8 +57485,8 @@ along with GCC; see the file COPYING3. If not see . */ #define YY_NO_INPUT 1 --#line 25 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 25 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 25 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 25 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" #ifdef GENERATOR_FILE #include "bconfig.h" #else @@ -51801,11 +57512,20 @@ #endif /* Copy whatever the last rule matched to the standard output. */ +@@ -1082,7 +1096,7 @@ + /* This used to be an fputs(), but since the string might contain NUL's, + * we now use fwrite(). + */ +-#define ECHO fwrite( yytext, yyleng, 1, yyout ) ++#define ECHO do { if (fwrite( yytext, yyleng, 1, yyout )) {} } while (0) + #endif + + /* Gets input and stuffs it into "buf". number of characters read, or YY_NULL, @@ -1093,7 +1107,7 @@ if ( YY_CURRENT_BUFFER_LVALUE->yy_is_interactive ) \ { \ int c = '*'; \ -- unsigned n; \ +- int n; \ + size_t n; \ for ( n = 0; n < max_size && \ (c = getc( yyin )) != EOF && c != '\n'; ++n ) \ @@ -51814,8 +57534,8 @@ register char *yy_cp, *yy_bp; register int yy_act; --#line 63 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 63 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 63 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 63 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" /* Do this on entry to yylex(): */ *yylval = 0; @@ -51832,8 +57552,8 @@ (yy_c_buf_p) = yy_cp -= 1; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP --#line 74 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 74 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 74 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 74 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { BEGIN(in_struct); return TYPEDEF; @@ -51841,8 +57561,8 @@ (yy_c_buf_p) = yy_cp -= 1; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP --#line 78 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 78 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 78 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 78 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { BEGIN(in_struct); return STRUCT; @@ -51850,8 +57570,8 @@ (yy_c_buf_p) = yy_cp -= 1; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP --#line 82 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 82 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 82 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 82 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { BEGIN(in_struct); return UNION; @@ -51859,8 +57579,8 @@ (yy_c_buf_p) = yy_cp -= 1; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP --#line 86 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 86 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 86 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 86 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { BEGIN(in_struct); return EXTERN; @@ -51868,8 +57588,8 @@ (yy_c_buf_p) = yy_cp -= 1; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP --#line 90 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 90 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 90 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 90 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { BEGIN(in_struct); return STATIC; @@ -51877,8 +57597,8 @@ (yy_c_buf_p) = yy_cp -= 1; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP --#line 95 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 95 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 95 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 95 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { BEGIN(in_struct); return DEFVEC_OP; @@ -51886,8 +57606,8 @@ (yy_c_buf_p) = yy_cp -= 1; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP --#line 99 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 99 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 99 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 99 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { BEGIN(in_struct); return DEFVEC_I; @@ -51895,8 +57615,8 @@ (yy_c_buf_p) = yy_cp -= 1; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP --#line 103 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 103 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 103 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 103 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { BEGIN(in_struct); return DEFVEC_ALLOC; @@ -51904,22 +57624,22 @@ case 9: YY_RULE_SETUP --#line 111 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 111 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 111 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 111 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { BEGIN(in_struct_comment); } YY_BREAK case 10: /* rule 10 can match eol */ YY_RULE_SETUP --#line 113 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 113 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 113 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 113 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { update_lineno (yytext, yyleng); } YY_BREAK case 11: /* rule 11 can match eol */ YY_RULE_SETUP --#line 114 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 114 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 114 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 114 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { lexer_line.line++; } YY_BREAK case 12: @@ -51927,8 +57647,8 @@ (yy_c_buf_p) = yy_cp = yy_bp + 5; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP --#line 116 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 116 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 116 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 116 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" /* don't care */ YY_BREAK case 13: @@ -51936,8 +57656,8 @@ (yy_c_buf_p) = yy_cp = yy_bp + 3; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP --#line 117 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 117 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 117 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 117 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { return GTY_TOKEN; } YY_BREAK case 14: @@ -51945,8 +57665,8 @@ (yy_c_buf_p) = yy_cp = yy_bp + 3; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP --#line 118 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 118 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 118 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 118 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { return VEC_TOKEN; } YY_BREAK case 15: @@ -51954,8 +57674,8 @@ (yy_c_buf_p) = yy_cp = yy_bp + 5; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP --#line 119 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 119 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 119 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 119 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { return UNION; } YY_BREAK case 16: @@ -51963,8 +57683,8 @@ (yy_c_buf_p) = yy_cp = yy_bp + 6; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP --#line 120 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 120 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 120 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 120 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { return STRUCT; } YY_BREAK case 17: @@ -51972,8 +57692,8 @@ (yy_c_buf_p) = yy_cp = yy_bp + 4; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP --#line 121 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 121 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 121 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 121 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { return ENUM; } YY_BREAK case 18: @@ -51981,8 +57701,8 @@ (yy_c_buf_p) = yy_cp = yy_bp + 9; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP --#line 122 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 122 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 122 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 122 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { return PTR_ALIAS; } YY_BREAK case 19: @@ -51990,14 +57710,14 @@ (yy_c_buf_p) = yy_cp = yy_bp + 10; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP --#line 123 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 123 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 123 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 123 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { return NESTED_PTR; } YY_BREAK case 20: YY_RULE_SETUP --#line 124 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 124 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 124 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 124 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { return NUM; } YY_BREAK case 21: @@ -52005,8 +57725,8 @@ (yy_c_buf_p) = yy_cp -= 1; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP --#line 125 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 125 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 125 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 125 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { *yylval = XDUPVAR (const char, yytext, yyleng, yyleng+1); return PARAM_IS; @@ -52014,13 +57734,13 @@ *yy_cp = (yy_hold_char); /* undo effects of setting up yytext */ (yy_c_buf_p) = yy_cp -= 1; YY_DO_BEFORE_ACTION; /* set up yytext again */ --#line 131 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 131 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 131 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 131 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" case 23: /* rule 23 can match eol */ YY_RULE_SETUP --#line 131 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 131 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 131 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 131 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { size_t len; @@ -52028,8 +57748,8 @@ (yy_c_buf_p) = yy_cp -= 1; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP --#line 143 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 143 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 143 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 143 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { *yylval = XDUPVAR (const char, yytext, yyleng, yyleng+1); return ID; @@ -52037,8 +57757,8 @@ case 25: /* rule 25 can match eol */ YY_RULE_SETUP --#line 148 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 148 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 148 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 148 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { *yylval = XDUPVAR (const char, yytext+1, yyleng-2, yyleng-1); return STRING; @@ -52046,8 +57766,8 @@ case 26: /* rule 26 can match eol */ YY_RULE_SETUP --#line 153 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 153 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 153 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 153 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { *yylval = XDUPVAR (const char, yytext+1, yyleng-2, yyleng-1); return ARRAY; @@ -52055,8 +57775,8 @@ case 27: /* rule 27 can match eol */ YY_RULE_SETUP --#line 157 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 157 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 157 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 157 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { *yylval = XDUPVAR (const char, yytext+1, yyleng-2, yyleng); return CHAR; @@ -52064,28 +57784,28 @@ YY_BREAK case 28: YY_RULE_SETUP --#line 162 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 162 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 162 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 162 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { return ELLIPSIS; } YY_BREAK case 29: YY_RULE_SETUP --#line 163 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 163 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 163 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 163 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { return yytext[0]; } YY_BREAK /* ignore pp-directives */ case 30: /* rule 30 can match eol */ YY_RULE_SETUP --#line 166 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 166 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 166 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 166 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" {lexer_line.line++;} YY_BREAK case 31: YY_RULE_SETUP --#line 168 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 168 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 168 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 168 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { error_at_line (&lexer_line, "unexpected character `%s'", yytext); } @@ -52093,36 +57813,36 @@ case 32: YY_RULE_SETUP --#line 173 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 173 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 173 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 173 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { BEGIN(in_comment); } YY_BREAK case 33: /* rule 33 can match eol */ YY_RULE_SETUP --#line 174 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 174 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 174 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 174 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { lexer_line.line++; } YY_BREAK case 34: --#line 176 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 176 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 176 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 176 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" case 35: /* rule 35 can match eol */ --#line 177 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 177 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 177 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 177 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" case 36: /* rule 36 can match eol */ YY_RULE_SETUP --#line 177 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 177 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 177 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 177 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" /* do nothing */ YY_BREAK case 37: /* rule 37 can match eol */ YY_RULE_SETUP --#line 178 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 178 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 178 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 178 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { update_lineno (yytext, yyleng); } YY_BREAK case 38: @@ -52130,25 +57850,25 @@ (yy_c_buf_p) = yy_cp = yy_bp + 1; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP --#line 179 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 179 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 179 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 179 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" /* do nothing */ YY_BREAK case 39: /* rule 39 can match eol */ YY_RULE_SETUP --#line 182 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 182 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 182 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 182 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { lexer_line.line++; } YY_BREAK case 40: --#line 184 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 184 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 184 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 184 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" case 41: YY_RULE_SETUP --#line 184 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 184 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 184 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 184 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" /* do nothing */ YY_BREAK case 42: @@ -52156,30 +57876,30 @@ (yy_c_buf_p) = yy_cp = yy_bp + 1; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP --#line 185 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 185 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 185 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 185 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" /* do nothing */ YY_BREAK case 43: YY_RULE_SETUP --#line 187 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 187 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 187 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 187 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { BEGIN(INITIAL); } YY_BREAK case 44: YY_RULE_SETUP --#line 188 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 188 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 188 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 188 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { BEGIN(in_struct); } YY_BREAK case 45: --#line 191 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 191 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 191 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 191 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" case 46: YY_RULE_SETUP --#line 191 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 191 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 191 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 191 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" { error_at_line (&lexer_line, "unterminated comment or string; unexpected EOF"); @@ -52187,14 +57907,14 @@ case 47: /* rule 47 can match eol */ YY_RULE_SETUP --#line 196 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 196 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 196 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 196 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" /* do nothing */ YY_BREAK case 48: YY_RULE_SETUP --#line 198 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 198 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 198 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 198 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" YY_FATAL_ERROR( "flex scanner jammed" ); YY_BREAK -#line 1654 "gengtype-lex.c" @@ -52217,25 +57937,18 @@ #define YYTABLES_NAME "yytables" --#line 198 "/d/gcc-4.7.2/gcc-4.7.2/gcc/gengtype-lex.l" -+#line 198 "/work/release/4.7-2012.11/gcc-linaro-4.7-2012.11/gcc/gengtype-lex.l" +-#line 198 "/space/rguenther/gcc-4.7.3/gcc-4.7.3/gcc/gengtype-lex.l" ++#line 198 "/home/doko/gcc-4.7.3-RC-20130411/gcc-4.7.3-RC-20130411/gcc/gengtype-lex.l" --- a/src/gcc/genmultilib +++ b/src/gcc/genmultilib -@@ -1,6 +1,6 @@ - #!/bin/sh - # Generates multilib.h. --# Copyright (C) 1994, 1995, 1996, 1997, 1999, 2002, 2007 -+# Copyright (C) 1994, 1995, 1996, 1997, 1999, 2002, 2007, 2012 - # Free Software Foundation, Inc. - - #This file is part of GCC. -@@ -73,6 +73,17 @@ +@@ -73,7 +73,18 @@ # the os directory names are used exclusively. Use the mapping when # there is no one-to-one equivalence between GCC levels and the OS. +-# The optional eighth argument is the multiarch name. +# The optional eighth argument which intends to reduce the effort to write +# so many MULTILIB_EXCEPTIONS rules. This option defines a series of option +# combinations that we actually required. @@ -52247,10 +57960,11 @@ +# This argument can be used together with MULTILIB_EXCEPTIONS and will take +# effect after the MULTILIB_EXCEPTIONS. + ++# The optional ninth argument is the multiarch name. + # The last option should be "yes" if multilibs are enabled. If it is not # "yes", all GCC multilib dir names will be ".". - -@@ -93,7 +104,7 @@ +@@ -95,7 +106,7 @@ # genmultilib 'm64/m32 mno-app-regs|mcmodel=medany' '64 32 alt' # 'mcmodel?medany=mcmodel?medmid' 'm32/mno-app-regs* m32/mcmodel=*' # '' 'm32/!m64/mno-app-regs m32/!m64/mcmodel=medany' @@ -52259,17 +57973,19 @@ # This produces: # ". !m64 !m32 !mno-app-regs !mcmodel=medany;", # "64:../lib64 m64 !m32 !mno-app-regs !mcmodel=medany;", -@@ -121,7 +132,8 @@ +@@ -123,8 +134,9 @@ extra=$5 exclusions=$6 osdirnames=$7 --enable_multilib=$8 +-multiarch=$8 +-enable_multilib=$9 +multilib_required=$8 -+enable_multilib=$9 ++multiarch=$9 ++enable_multilib=${10} echo "static const char *const multilib_raw[] = {" -@@ -195,6 +207,33 @@ +@@ -198,6 +210,33 @@ combinations=`./tmpmultilib2 ${combinations}` fi @@ -52303,1991 +58019,174 @@ # Construct a sed pattern which will convert option names to directory # names. todirnames= ---- a/src/gcc/gimple-fold.c -+++ b/src/gcc/gimple-fold.c -@@ -115,7 +115,8 @@ - tree - canonicalize_constructor_val (tree cval) - { -- STRIP_USELESS_TYPE_CONVERSION (cval); -+ tree orig_cval = cval; -+ STRIP_NOPS (cval); - if (TREE_CODE (cval) == POINTER_PLUS_EXPR - && TREE_CODE (TREE_OPERAND (cval, 1)) == INTEGER_CST) - { -@@ -146,8 +147,12 @@ - /* Fixup types in global initializers. */ - if (TREE_TYPE (TREE_TYPE (cval)) != TREE_TYPE (TREE_OPERAND (cval, 0))) - cval = build_fold_addr_expr (TREE_OPERAND (cval, 0)); -+ -+ if (!useless_type_conversion_p (TREE_TYPE (orig_cval), TREE_TYPE (cval))) -+ cval = fold_convert (TREE_TYPE (orig_cval), cval); -+ return cval; - } -- return cval; -+ return orig_cval; - } - - /* If SYM is a constant variable with known value, return the value. ---- a/src/gcc/gimple.h -+++ b/src/gcc/gimple.h -@@ -1087,6 +1087,24 @@ - bool in_cleanup_point_expr; - }; +--- a/src/gcc/haifa-sched.c ++++ b/src/gcc/haifa-sched.c +@@ -398,6 +398,14 @@ + /* Create empty basic block after the specified block. */ + basic_block (* sched_create_empty_bb) (basic_block); -+/* Return true if gimplify_one_sizepos doesn't need to gimplify -+ expr (when in TYPE_SIZE{,_UNIT} and similar type/decl size/bitsize -+ fields). */ -+static inline bool -+is_gimple_sizepos (tree expr) ++/* Return the number of cycles until INSN is expected to be ready. ++ Return zero if it already is. */ ++static int ++insn_delay (rtx insn) +{ -+ /* gimplify_one_sizepos doesn't need to do anything if the value isn't there, -+ is constant, or contains A PLACEHOLDER_EXPR. We also don't want to do -+ anything if it's already a VAR_DECL. If it's a VAR_DECL from another -+ function, the gimplifier will want to replace it with a new variable, -+ but that will cause problems if this type is from outside the function. -+ It's OK to have that here. */ -+ return (expr == NULL_TREE -+ || TREE_CONSTANT (expr) -+ || TREE_CODE (expr) == VAR_DECL -+ || CONTAINS_PLACEHOLDER_P (expr)); -+} -+ - extern enum gimplify_status gimplify_expr (tree *, gimple_seq *, gimple_seq *, - bool (*) (tree), fallback_t); - extern void gimplify_type_sizes (tree, gimple_seq *); ---- a/src/gcc/gimplify.c -+++ b/src/gcc/gimplify.c -@@ -119,6 +119,19 @@ - && TREE_CODE (x) != RESULT_DECL) - return; - TREE_ADDRESSABLE (x) = 1; ++ return MAX (INSN_TICK (insn) - clock_var, 0); ++} + -+ /* Also mark the artificial SSA_NAME that points to the partition of X. */ -+ if (TREE_CODE (x) == VAR_DECL -+ && !DECL_EXTERNAL (x) -+ && !TREE_STATIC (x) -+ && cfun->gimple_df != NULL -+ && cfun->gimple_df->decls_to_pointers != NULL) -+ { -+ void *namep -+ = pointer_map_contains (cfun->gimple_df->decls_to_pointers, x); -+ if (namep) -+ TREE_ADDRESSABLE (*(tree *)namep) = 1; -+ } + static int + may_trap_exp (const_rtx x, int is_store) + { +@@ -872,10 +880,10 @@ + + /* Do register pressure sensitive insn scheduling if the flag is set + up. */ +-bool sched_pressure_p; ++enum sched_pressure_algorithm sched_pressure; + + /* Map regno -> its pressure class. The map defined only when +- SCHED_PRESSURE_P is true. */ ++ SCHED_PRESSURE != SCHED_PRESSURE_NONE. */ + enum reg_class *sched_regno_pressure_class; + + /* The current register pressure. Only elements corresponding pressure +@@ -903,10 +911,12 @@ + bitmap_clear (region_ref_regs); } - /* Return a hash value for a formal temporary table entry. */ -@@ -7935,9 +7948,7 @@ - a VAR_DECL. If it's a VAR_DECL from another function, the gimplifier - will want to replace it with a new variable, but that will cause problems - if this type is from outside the function. It's OK to have that here. */ -- if (expr == NULL_TREE || TREE_CONSTANT (expr) -- || TREE_CODE (expr) == VAR_DECL -- || CONTAINS_PLACEHOLDER_P (expr)) -+ if (is_gimple_sizepos (expr)) - return; +-/* Update current register pressure related info after birth (if +- BIRTH_P) or death of register REGNO. */ +-static void +-mark_regno_birth_or_death (int regno, bool birth_p) ++/* PRESSURE[CL] describes the pressure on register class CL. Update it ++ for the birth (if BIRTH_P) or death (if !BIRTH_P) of register REGNO. ++ LIVE tracks the set of live registers; if it is null, assume that ++ every birth or death is genuine. */ ++static inline void ++mark_regno_birth_or_death (bitmap live, int *pressure, int regno, bool birth_p) + { + enum reg_class pressure_class; - type = TREE_TYPE (expr); ---- a/src/gcc/go/ChangeLog -+++ b/src/gcc/go/ChangeLog -@@ -1,3 +1,18 @@ -+2012-10-30 Ian Lance Taylor -+ -+ * lang.opt (-fgo-relative-import-path): New option. -+ * go-lang.c (go_relative_import_path): New static variable. -+ (go_langhook_init): Pass go_relative_import_path to -+ go_create_gogo. -+ (go_langhook_handle_option): Handle -fgo-relative-import-path. -+ * go-c.h (go_create_gogo): Update declaration. -+ * gccgo.texi (Invoking gccgo): Document -+ -fgo-relative-import-path. -+ -+2012-09-20 Ian Lance Taylor -+ -+ * Make-lang.in (go/gogo.o): Depend on filenames.h. -+ - 2012-09-20 Release Manager - - * GCC 4.7.2 released. ---- a/src/gcc/go/gccgo.texi -+++ b/src/gcc/go/gccgo.texi -@@ -184,6 +184,12 @@ - the special treatment of the @code{main} package and permits that - package to be imported like any other. - -+@item -fgo-relative-import-path=@var{dir} -+@cindex @option{-fgo-relative-import-path} -+A relative import is an import that starts with @file{./} or -+@file{../}. If this option is used, @command{gccgo} will use -+@var{dir} as a prefix for the relative import when searching for it. -+ - @item -frequire-return-statement - @itemx -fno-require-return-statement - @cindex @option{-frequire-return-statement} ---- a/src/gcc/go/go-c.h -+++ b/src/gcc/go/go-c.h -@@ -42,7 +42,8 @@ - extern void go_add_search_path (const char*); - - extern void go_create_gogo (int int_type_size, int pointer_size, -- const char* pkgpath, const char *prefix); -+ const char* pkgpath, const char *prefix, -+ const char *relative_import_path); - - extern void go_parse_input_files (const char**, unsigned int, - bool only_check_syntax, ---- a/src/gcc/go/gofrontend/expressions.cc -+++ b/src/gcc/go/gofrontend/expressions.cc -@@ -301,19 +301,25 @@ - // object type: a list of function pointers for each interface - // method. - Named_type* rhs_named_type = rhs_type->named_type(); -+ Struct_type* rhs_struct_type = rhs_type->struct_type(); - bool is_pointer = false; -- if (rhs_named_type == NULL) -+ if (rhs_named_type == NULL && rhs_struct_type == NULL) +@@ -917,17 +927,17 @@ { - rhs_named_type = rhs_type->deref()->named_type(); -+ rhs_struct_type = rhs_type->deref()->struct_type(); - is_pointer = true; + if (birth_p) + { +- bitmap_set_bit (curr_reg_live, regno); +- curr_reg_pressure[pressure_class] +- += (ira_reg_class_max_nregs +- [pressure_class][PSEUDO_REGNO_MODE (regno)]); ++ if (!live || bitmap_set_bit (live, regno)) ++ pressure[pressure_class] ++ += (ira_reg_class_max_nregs ++ [pressure_class][PSEUDO_REGNO_MODE (regno)]); + } + else + { +- bitmap_clear_bit (curr_reg_live, regno); +- curr_reg_pressure[pressure_class] +- -= (ira_reg_class_max_nregs +- [pressure_class][PSEUDO_REGNO_MODE (regno)]); ++ if (!live || bitmap_clear_bit (live, regno)) ++ pressure[pressure_class] ++ -= (ira_reg_class_max_nregs ++ [pressure_class][PSEUDO_REGNO_MODE (regno)]); + } } - tree method_table; -- if (rhs_named_type == NULL) -- method_table = null_pointer_node; -- else -+ if (rhs_named_type != NULL) - method_table = - rhs_named_type->interface_method_table(gogo, lhs_interface_type, - is_pointer); -+ else if (rhs_struct_type != NULL) -+ method_table = -+ rhs_struct_type->interface_method_table(gogo, lhs_interface_type, -+ is_pointer); -+ else -+ method_table = null_pointer_node; - first_field_value = fold_convert_loc(location.gcc_location(), - const_ptr_type_node, method_table); } -@@ -5184,6 +5190,9 @@ - pf != fields->end(); - ++pf, ++field_index) +@@ -936,13 +946,13 @@ { -+ if (Gogo::is_sink_name(pf->field_name())) -+ continue; -+ - if (field_index > 0) + if (birth_p) + { +- bitmap_set_bit (curr_reg_live, regno); +- curr_reg_pressure[pressure_class]++; ++ if (!live || bitmap_set_bit (live, regno)) ++ pressure[pressure_class]++; + } + else { - if (left_temp == NULL) -@@ -5450,7 +5459,8 @@ - && (this->left_->type()->integer_type() == NULL - || (subcontext.type->integer_type() == NULL - && subcontext.type->float_type() == NULL -- && subcontext.type->complex_type() == NULL))) -+ && subcontext.type->complex_type() == NULL -+ && subcontext.type->interface_type() == NULL))) - this->report_error(("invalid context-determined non-integer type " - "for shift operand")); +- bitmap_clear_bit (curr_reg_live, regno); +- curr_reg_pressure[pressure_class]--; ++ if (!live || bitmap_clear_bit (live, regno)) ++ pressure[pressure_class]--; + } + } + } +@@ -960,8 +970,10 @@ + curr_reg_pressure[ira_pressure_classes[i]] = 0; + bitmap_clear (curr_reg_live); + EXECUTE_IF_SET_IN_BITMAP (live, 0, j, bi) +- if (current_nr_blocks == 1 || bitmap_bit_p (region_ref_regs, j)) +- mark_regno_birth_or_death (j, true); ++ if (sched_pressure == SCHED_PRESSURE_MODEL ++ || current_nr_blocks == 1 ++ || bitmap_bit_p (region_ref_regs, j)) ++ mark_regno_birth_or_death (curr_reg_live, curr_reg_pressure, j, true); + } -@@ -6682,38 +6692,6 @@ - this->set_args(new_args); + /* Mark registers in X as mentioned in the current region. */ +@@ -1015,7 +1027,8 @@ + if (regno == INVALID_REGNUM) + break; + if (! bitmap_bit_p (df_get_live_in (bb), regno)) +- mark_regno_birth_or_death (regno, true); ++ mark_regno_birth_or_death (curr_reg_live, curr_reg_pressure, ++ regno, true); + } + #endif + } +@@ -1445,19 +1458,19 @@ + return true; } --// A traversal class which looks for a call expression. -- --class Find_call_expression : public Traverse --{ -- public: -- Find_call_expression() -- : Traverse(traverse_expressions), -- found_(false) -- { } -- -- int -- expression(Expression**); -- -- bool -- found() -- { return this->found_; } -- -- private: -- bool found_; --}; -- --int --Find_call_expression::expression(Expression** pexpr) --{ -- if ((*pexpr)->call_expression() != NULL) -- { -- this->found_ = true; -- return TRAVERSE_EXIT; -- } -- return TRAVERSE_CONTINUE; --} -- - // Lower a builtin call expression. This turns new and make into - // specific expressions. We also convert to a constant if we can. +-/* Compute the number of nondebug forward deps of an insn. */ ++/* Compute the number of nondebug deps in list LIST for INSN. */ + + static int +-dep_list_size (rtx insn) ++dep_list_size (rtx insn, sd_list_types_def list) + { + sd_iterator_def sd_it; + dep_t dep; + int dbgcount = 0, nodbgcount = 0; -@@ -6734,20 +6712,6 @@ + if (!MAY_HAVE_DEBUG_INSNS) +- return sd_lists_size (insn, SD_LIST_FORW); ++ return sd_lists_size (insn, list); - if (this->is_constant()) +- FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep) ++ FOR_EACH_DEP (insn, list, sd_it, dep) { -- // We can only lower len and cap if there are no function calls -- // in the arguments. Otherwise we have to make the call. -- if (this->code_ == BUILTIN_LEN || this->code_ == BUILTIN_CAP) -- { -- Expression* arg = this->one_arg(); -- if (arg != NULL && !arg->is_constant()) -- { -- Find_call_expression find_call; -- Expression::traverse(&arg, &find_call); -- if (find_call.found()) -- return this; -- } -- } -- - Numeric_constant nc; - if (this->numeric_constant_value(&nc)) - return nc.expression(loc); -@@ -7064,8 +7028,42 @@ - return args->front(); + if (DEBUG_INSN_P (DEP_CON (dep))) + dbgcount++; +@@ -1465,7 +1478,7 @@ + nodbgcount++; + } + +- gcc_assert (dbgcount + nodbgcount == sd_lists_size (insn, SD_LIST_FORW)); ++ gcc_assert (dbgcount + nodbgcount == sd_lists_size (insn, list)); + + return nodbgcount; } +@@ -1484,7 +1497,7 @@ + { + int this_priority = -1; --// Return whether this is constant: len of a string, or len or cap of --// a fixed array, or unsafe.Sizeof, unsafe.Offsetof, unsafe.Alignof. -+// A traversal class which looks for a call or receive expression. -+ -+class Find_call_expression : public Traverse -+{ -+ public: -+ Find_call_expression() -+ : Traverse(traverse_expressions), -+ found_(false) -+ { } -+ -+ int -+ expression(Expression**); -+ -+ bool -+ found() -+ { return this->found_; } -+ -+ private: -+ bool found_; -+}; +- if (dep_list_size (insn) == 0) ++ if (dep_list_size (insn, SD_LIST_FORW) == 0) + /* ??? We should set INSN_PRIORITY to insn_cost when and insn has + some forward deps but all of them are ignored by + contributes_to_priority hook. At the moment we set priority of +@@ -1580,6 +1593,22 @@ + qsort (READY, N_READY, sizeof (rtx), rank_for_schedule); } \ + while (0) + ++/* For each pressure class CL, set DEATH[CL] to the number of registers ++ in that class that die in INSN. */ + -+int -+Find_call_expression::expression(Expression** pexpr) ++static void ++calculate_reg_deaths (rtx insn, int *death) +{ -+ if ((*pexpr)->call_expression() != NULL -+ || (*pexpr)->receive_expression() != NULL) -+ { -+ this->found_ = true; -+ return TRAVERSE_EXIT; -+ } -+ return TRAVERSE_CONTINUE; -+} -+ -+// Return whether this is constant: len of a string constant, or len -+// or cap of an array, or unsafe.Sizeof, unsafe.Offsetof, -+// unsafe.Alignof. - - bool - Builtin_call_expression::do_is_constant() const -@@ -7088,6 +7086,17 @@ - && !arg_type->points_to()->is_slice_type()) - arg_type = arg_type->points_to(); - -+ // The len and cap functions are only constant if there are no -+ // function calls or channel operations in the arguments. -+ // Otherwise we have to make the call. -+ if (!arg->is_constant()) -+ { -+ Find_call_expression find_call; -+ Expression::traverse(&arg, &find_call); -+ if (find_call.found()) -+ return false; -+ } -+ - if (arg_type->array_type() != NULL - && arg_type->array_type()->length() != NULL) - return true; -@@ -7474,7 +7483,7 @@ - if (args != NULL && args->size() == 2) - { - Type* t1 = args->front()->type(); -- Type* t2 = args->front()->type(); -+ Type* t2 = args->back()->type(); - if (!t1->is_abstract()) - arg_type = t1; - else if (!t2->is_abstract()) ---- a/src/gcc/go/gofrontend/go.cc -+++ b/src/gcc/go/gofrontend/go.cc -@@ -21,7 +21,7 @@ - GO_EXTERN_C - void - go_create_gogo(int int_type_size, int pointer_size, const char *pkgpath, -- const char *prefix) -+ const char *prefix, const char *relative_import_path) - { - go_assert(::gogo == NULL); - Linemap* linemap = go_get_linemap(); -@@ -32,6 +32,9 @@ - else if (prefix != NULL) - ::gogo->set_prefix(prefix); - -+ if (relative_import_path != NULL) -+ ::gogo->set_relative_import_path(relative_import_path); -+ - // FIXME: This should be in the gcc dependent code. - ::gogo->define_builtin_function_trees(); - } ---- a/src/gcc/go/gofrontend/gogo.cc -+++ b/src/gcc/go/gofrontend/gogo.cc -@@ -6,6 +6,8 @@ - - #include "go-system.h" - -+#include "filenames.h" -+ - #include "go-c.h" - #include "go-dump.h" - #include "lex.h" -@@ -42,6 +44,7 @@ - pkgpath_set_(false), - pkgpath_from_option_(false), - prefix_from_option_(false), -+ relative_import_path_(), - verify_types_(), - interface_types_(), - specific_type_functions_(), -@@ -385,6 +388,57 @@ - bool is_local_name_exported, - Location location) - { -+ if (filename.empty()) -+ { -+ error_at(location, "import path is empty"); -+ return; -+ } -+ -+ const char *pf = filename.data(); -+ const char *pend = pf + filename.length(); -+ while (pf < pend) -+ { -+ unsigned int c; -+ int adv = Lex::fetch_char(pf, &c); -+ if (adv == 0) -+ { -+ error_at(location, "import path contains invalid UTF-8 sequence"); -+ return; -+ } -+ if (c == '\0') -+ { -+ error_at(location, "import path contains NUL"); -+ return; -+ } -+ if (c < 0x20 || c == 0x7f) -+ { -+ error_at(location, "import path contains control character"); -+ return; -+ } -+ if (c == '\\') -+ { -+ error_at(location, "import path contains backslash; use slash"); -+ return; -+ } -+ if (Lex::is_unicode_space(c)) -+ { -+ error_at(location, "import path contains space character"); -+ return; -+ } -+ if (c < 0x7f && strchr("!\"#$%&'()*,:;<=>?[]^`{|}", c) != NULL) -+ { -+ error_at(location, "import path contains invalid character '%c'", c); -+ return; -+ } -+ pf += adv; -+ } -+ -+ if (IS_ABSOLUTE_PATH(filename.c_str())) -+ { -+ error_at(location, "import path cannot be absolute path"); -+ return; -+ } -+ - if (filename == "unsafe") - { - this->import_unsafe(local_name, is_local_name_exported, location); -@@ -424,7 +478,8 @@ - return; - } - -- Import::Stream* stream = Import::open_package(filename, location); -+ Import::Stream* stream = Import::open_package(filename, location, -+ this->relative_import_path_); - if (stream == NULL) - { - error_at(location, "import file %qs not found", filename.c_str()); -@@ -1003,7 +1058,15 @@ - Named_object* no = this->current_bindings()->add_type(name, NULL, type, - location); - if (!this->in_global_scope() && no->is_type()) -- no->type_value()->set_in_function(this->functions_.back().function); -+ { -+ Named_object* f = this->functions_.back().function; -+ unsigned int index; -+ if (f->is_function()) -+ index = f->func_value()->new_local_type_index(); -+ else -+ index = 0; -+ no->type_value()->set_in_function(f, index); -+ } - } - - // Add a named type. -@@ -1025,7 +1088,12 @@ - if (!this->in_global_scope() && no->is_type_declaration()) - { - Named_object* f = this->functions_.back().function; -- no->type_declaration_value()->set_in_function(f); -+ unsigned int index; -+ if (f->is_function()) -+ index = f->func_value()->new_local_type_index(); -+ else -+ index = 0; -+ no->type_declaration_value()->set_in_function(f, index); - } - return no; - } -@@ -2806,7 +2874,8 @@ - Build_method_tables::type(Type* type) - { - Named_type* nt = type->named_type(); -- if (nt != NULL) -+ Struct_type* st = type->struct_type(); -+ if (nt != NULL || st != NULL) - { - for (std::vector::const_iterator p = - this->interfaces_.begin(); -@@ -2816,10 +2885,23 @@ - // We ask whether a pointer to the named type implements the - // interface, because a pointer can implement more methods - // than a value. -- if ((*p)->implements_interface(Type::make_pointer_type(nt), NULL)) -+ if (nt != NULL) -+ { -+ if ((*p)->implements_interface(Type::make_pointer_type(nt), -+ NULL)) -+ { -+ nt->interface_method_table(this->gogo_, *p, false); -+ nt->interface_method_table(this->gogo_, *p, true); -+ } -+ } -+ else - { -- nt->interface_method_table(this->gogo_, *p, false); -- nt->interface_method_table(this->gogo_, *p, true); -+ if ((*p)->implements_interface(Type::make_pointer_type(st), -+ NULL)) -+ { -+ st->interface_method_table(this->gogo_, *p, false); -+ st->interface_method_table(this->gogo_, *p, true); -+ } - } - } - } -@@ -2989,9 +3071,10 @@ - Function::Function(Function_type* type, Function* enclosing, Block* block, - Location location) - : type_(type), enclosing_(enclosing), results_(NULL), -- closure_var_(NULL), block_(block), location_(location), fndecl_(NULL), -- defer_stack_(NULL), results_are_named_(false), calls_recover_(false), -- is_recover_thunk_(false), has_recover_thunk_(false) -+ closure_var_(NULL), block_(block), location_(location), labels_(), -+ local_type_count_(0), fndecl_(NULL), defer_stack_(NULL), -+ results_are_named_(false), calls_recover_(false), is_recover_thunk_(false), -+ has_recover_thunk_(false) - { - } - -@@ -4157,7 +4240,7 @@ - else if (type->is_call_multiple_result_type()) - { - error_at(this->location_, -- "single variable set to multiple value function call"); -+ "single variable set to multiple-value function call"); - type = Type::make_error_type(); - } - -@@ -4599,9 +4682,10 @@ - go_assert(this->classification_ == NAMED_OBJECT_TYPE_DECLARATION); - Type_declaration* td = this->u_.type_declaration; - td->define_methods(named_type); -- Named_object* in_function = td->in_function(); -+ unsigned int index; -+ Named_object* in_function = td->in_function(&index); - if (in_function != NULL) -- named_type->set_in_function(in_function); -+ named_type->set_in_function(in_function, index); - delete td; - this->classification_ = NAMED_OBJECT_TYPE; - this->u_.type_value = named_type; ---- a/src/gcc/go/gofrontend/gogo.h -+++ b/src/gcc/go/gofrontend/gogo.h -@@ -206,6 +206,17 @@ - pkgpath_from_option() const - { return this->pkgpath_from_option_; } - -+ // Return the relative import path as set from the command line. -+ // Returns an empty string if it was not set. -+ const std::string& -+ relative_import_path() const -+ { return this->relative_import_path_; } -+ -+ // Set the relative import path from a command line option. -+ void -+ set_relative_import_path(const std::string& s) -+ {this->relative_import_path_ = s; } -+ - // Return the priority to use for the package we are compiling. - // This is two more than the largest priority of any package we - // import. -@@ -574,7 +585,7 @@ - // Build an interface method table for a type: a list of function - // pointers, one for each interface method. This returns a decl. - tree -- interface_method_table_for_type(const Interface_type*, Named_type*, -+ interface_method_table_for_type(const Interface_type*, Type*, - bool is_pointer); - - // Return a tree which allocate SIZE bytes to hold values of type -@@ -732,6 +743,9 @@ - bool pkgpath_from_option_; - // Whether an explicit prefix was set by -fgo-prefix. - bool prefix_from_option_; -+ // The relative import path, from the -fgo-relative-import-path -+ // option. -+ std::string relative_import_path_; - // A list of types to verify. - std::vector verify_types_; - // A list of interface types defined while parsing. -@@ -963,6 +977,11 @@ - void - check_labels() const; - -+ // Note that a new local type has been added. Return its index. -+ unsigned int -+ new_local_type_index() -+ { return this->local_type_count_++; } -+ - // Whether this function calls the predeclared recover function. - bool - calls_recover() const -@@ -1084,6 +1103,8 @@ - Location location_; - // Labels defined or referenced in the function. - Labels labels_; -+ // The number of local types defined in this function. -+ unsigned int local_type_count_; - // The function decl. - tree fndecl_; - // The defer stack variable. A pointer to this variable is used to -@@ -1638,8 +1659,8 @@ - { - public: - Type_declaration(Location location) -- : location_(location), in_function_(NULL), methods_(), -- issued_warning_(false) -+ : location_(location), in_function_(NULL), in_function_index_(0), -+ methods_(), issued_warning_(false) - { } - - // Return the location. -@@ -1650,13 +1671,19 @@ - // Return the function in which this type is declared. This will - // return NULL for a type declared in global scope. - Named_object* -- in_function() -- { return this->in_function_; } -+ in_function(unsigned int* pindex) -+ { -+ *pindex = this->in_function_index_; -+ return this->in_function_; -+ } - - // Set the function in which this type is declared. - void -- set_in_function(Named_object* f) -- { this->in_function_ = f; } -+ set_in_function(Named_object* f, unsigned int index) -+ { -+ this->in_function_ = f; -+ this->in_function_index_ = index; -+ } - - // Add a method to this type. This is used when methods are defined - // before the type. -@@ -1689,6 +1716,8 @@ - // If this type is declared in a function, a pointer back to the - // function in which it is defined. - Named_object* in_function_; -+ // The index of this type in IN_FUNCTION_. -+ unsigned int in_function_index_; - // Methods defined before the type is defined. - Methods methods_; - // True if we have issued a warning about a use of this type ---- a/src/gcc/go/gofrontend/gogo-tree.cc -+++ b/src/gcc/go/gofrontend/gogo-tree.cc -@@ -1002,9 +1002,19 @@ - } - if (this->is_type()) - { -- const Named_object* in_function = this->type_value()->in_function(); -+ unsigned int index; -+ const Named_object* in_function = this->type_value()->in_function(&index); - if (in_function != NULL) -- decl_name += '$' + Gogo::unpack_hidden_name(in_function->name()); -+ { -+ decl_name += '$' + Gogo::unpack_hidden_name(in_function->name()); -+ if (index > 0) -+ { -+ char buf[30]; -+ snprintf(buf, sizeof buf, "%u", index); -+ decl_name += '$'; -+ decl_name += buf; -+ } -+ } - } - return get_identifier_from_string(decl_name); - } -@@ -2133,8 +2143,7 @@ - - tree - Gogo::interface_method_table_for_type(const Interface_type* interface, -- Named_type* type, -- bool is_pointer) -+ Type* type, bool is_pointer) - { - const Typed_identifier_list* interface_methods = interface->methods(); - go_assert(!interface_methods->empty()); -@@ -2163,7 +2172,9 @@ - // interface. If the interface has hidden methods, and the named - // type is defined in a different package, then the interface - // conversion table will be defined by that other package. -- if (has_hidden_methods && type->named_object()->package() != NULL) -+ if (has_hidden_methods -+ && type->named_type() != NULL -+ && type->named_type()->named_object()->package() != NULL) - { - tree array_type = build_array_type(const_ptr_type_node, NULL); - tree decl = build_decl(BUILTINS_LOCATION, VAR_DECL, id, array_type); -@@ -2191,13 +2202,20 @@ - Linemap::predeclared_location()); - elt->value = fold_convert(const_ptr_type_node, tdp); - -+ Named_type* nt = type->named_type(); -+ Struct_type* st = type->struct_type(); -+ go_assert(nt != NULL || st != NULL); - size_t i = 1; - for (Typed_identifier_list::const_iterator p = interface_methods->begin(); - p != interface_methods->end(); - ++p, ++i) - { - bool is_ambiguous; -- Method* m = type->method_function(p->name(), &is_ambiguous); -+ Method* m; -+ if (nt != NULL) -+ m = nt->method_function(p->name(), &is_ambiguous); -+ else -+ m = st->method_function(p->name(), &is_ambiguous); - go_assert(m != NULL); - - Named_object* no = m->named_object(); ---- a/src/gcc/go/gofrontend/import.cc -+++ b/src/gcc/go/gofrontend/import.cc -@@ -41,6 +41,9 @@ - // When FILENAME is not an absolute path and does not start with ./ or - // ../, we use the search path provided by -I and -L options. - -+// When FILENAME does start with ./ or ../, we use -+// RELATIVE_IMPORT_PATH as a prefix. -+ - // When FILENAME does not exist, we try modifying FILENAME to find the - // file. We use the first of these which exists: - // * We append ".gox". -@@ -55,19 +58,35 @@ - // later in the search path. - - Import::Stream* --Import::open_package(const std::string& filename, Location location) -+Import::open_package(const std::string& filename, Location location, -+ const std::string& relative_import_path) - { - bool is_local; - if (IS_ABSOLUTE_PATH(filename)) - is_local = true; -- else if (filename[0] == '.' && IS_DIR_SEPARATOR(filename[1])) -+ else if (filename[0] == '.' -+ && (filename[1] == '\0' || IS_DIR_SEPARATOR(filename[1]))) - is_local = true; - else if (filename[0] == '.' - && filename[1] == '.' -- && IS_DIR_SEPARATOR(filename[2])) -+ && (filename[2] == '\0' || IS_DIR_SEPARATOR(filename[2]))) - is_local = true; - else - is_local = false; -+ -+ std::string fn = filename; -+ if (is_local && !IS_ABSOLUTE_PATH(filename) && !relative_import_path.empty()) -+ { -+ if (fn == ".") -+ { -+ // A special case. -+ fn = relative_import_path; -+ } -+ else -+ fn = relative_import_path + '/' + fn; -+ is_local = false; -+ } -+ - if (!is_local) - { - for (std::vector::const_iterator p = search_path.begin(); -@@ -77,14 +96,14 @@ - std::string indir = *p; - if (!indir.empty() && indir[indir.size() - 1] != '/') - indir += '/'; -- indir += filename; -+ indir += fn; - Stream* s = Import::try_package_in_directory(indir, location); - if (s != NULL) - return s; - } - } - -- Stream* s = Import::try_package_in_directory(filename, location); -+ Stream* s = Import::try_package_in_directory(fn, location); - if (s != NULL) - return s; - ---- a/src/gcc/go/gofrontend/import.h -+++ b/src/gcc/go/gofrontend/import.h -@@ -124,8 +124,10 @@ - // Find import data. This searches the file system for FILENAME and - // returns a pointer to a Stream object to read the data that it - // exports. LOCATION is the location of the import statement. -+ // RELATIVE_IMPORT_PATH is used as a prefix for a relative import. - static Stream* -- open_package(const std::string& filename, Location location); -+ open_package(const std::string& filename, Location location, -+ const std::string& relative_import_path); - - // Constructor. - Import(Stream*, Location); ---- a/src/gcc/go/gofrontend/lex.cc -+++ b/src/gcc/go/gofrontend/lex.cc -@@ -722,7 +722,16 @@ - unsigned int ci; - bool issued_error; - this->lineoff_ = p - this->linebuf_; -- this->advance_one_utf8_char(p, &ci, &issued_error); -+ const char *pnext = this->advance_one_utf8_char(p, &ci, -+ &issued_error); -+ -+ // Ignore byte order mark at start of file. -+ if (ci == 0xfeff) -+ { -+ p = pnext; -+ break; -+ } -+ - if (Lex::is_unicode_letter(ci)) - return this->gather_identifier(); - -@@ -831,6 +840,14 @@ - *issued_error = true; - return p + 1; - } -+ -+ // Warn about byte order mark, except at start of file. -+ if (*value == 0xfeff && (this->lineno_ != 1 || this->lineoff_ != 0)) -+ { -+ error_at(this->location(), "Unicode (UTF-8) BOM in middle of file"); -+ *issued_error = true; -+ } -+ - return p + adv; - } - -@@ -1295,6 +1312,12 @@ - // Turn it into the "replacement character". - v = 0xfffd; - } -+ if (v >= 0xd800 && v < 0xe000) -+ { -+ warning_at(location, 0, -+ "unicode code point 0x%x is invalid surrogate pair", v); -+ v = 0xfffd; -+ } - if (v <= 0xffff) - { - buf[0] = 0xe0 + (v >> 12); -@@ -1705,6 +1728,27 @@ - unsigned int stride; - }; - -+// A table of whitespace characters--Unicode code points classified as -+// "Space", "C" locale whitespace characters, the "next line" control -+// character (0085), the line separator (2028), the paragraph -+// separator (2029), and the "zero-width non-break space" (feff). -+ -+static const Unicode_range unicode_space[] = -+{ -+ { 0x0009, 0x000d, 1 }, -+ { 0x0020, 0x0020, 1 }, -+ { 0x0085, 0x0085, 1 }, -+ { 0x00a0, 0x00a0, 1 }, -+ { 0x1680, 0x1680, 1 }, -+ { 0x180e, 0x180e, 1 }, -+ { 0x2000, 0x200a, 1 }, -+ { 0x2028, 0x2029, 1 }, -+ { 0x202f, 0x202f, 1 }, -+ { 0x205f, 0x205f, 1 }, -+ { 0x3000, 0x3000, 1 }, -+ { 0xfeff, 0xfeff, 1 }, -+}; -+ - // A table of Unicode digits--Unicode code points classified as - // "Digit". - -@@ -2294,6 +2338,15 @@ - } - } - -+// Return whether C is a space character. -+ -+bool -+Lex::is_unicode_space(unsigned int c) -+{ -+ return Lex::is_in_unicode_range(c, unicode_space, -+ ARRAY_SIZE(unicode_space)); -+} -+ - // Return whether C is a Unicode digit--a Unicode code point - // classified as "Digit". - ---- a/src/gcc/go/gofrontend/lex.h -+++ b/src/gcc/go/gofrontend/lex.h -@@ -375,6 +375,10 @@ - static int - fetch_char(const char* str, unsigned int *value); - -+ // Return whether C is a Unicode or "C" locale space character. -+ static bool -+ is_unicode_space(unsigned int c); -+ - private: - ssize_t - get_line(); ---- a/src/gcc/go/gofrontend/parse.cc -+++ b/src/gcc/go/gofrontend/parse.cc -@@ -1631,12 +1631,16 @@ - - // Note that INIT was already parsed with the old name bindings, so - // we don't have to worry that it will accidentally refer to the -- // newly declared variables. -+ // newly declared variables. But we do have to worry about a mix of -+ // newly declared variables and old variables if the old variables -+ // appear in the initializations. - - Expression_list::const_iterator pexpr; - if (init != NULL) - pexpr = init->begin(); - bool any_new = false; -+ Expression_list* vars = new Expression_list(); -+ Expression_list* vals = new Expression_list(); - for (Typed_identifier_list::const_iterator p = til->begin(); - p != til->end(); - ++p) -@@ -1644,7 +1648,7 @@ - if (init != NULL) - go_assert(pexpr != init->end()); - this->init_var(*p, type, init == NULL ? NULL : *pexpr, is_coloneq, -- false, &any_new); -+ false, &any_new, vars, vals); - if (init != NULL) - ++pexpr; - } -@@ -1652,6 +1656,7 @@ - go_assert(pexpr == init->end()); - if (is_coloneq && !any_new) - error_at(location, "variables redeclared but no variable is new"); -+ this->finish_init_vars(vars, vals, location); - } - - // See if we need to initialize a list of variables from a function -@@ -1674,13 +1679,15 @@ - Named_object* first_var = NULL; - unsigned int index = 0; - bool any_new = false; -+ Expression_list* ivars = new Expression_list(); -+ Expression_list* ivals = new Expression_list(); - for (Typed_identifier_list::const_iterator pv = vars->begin(); - pv != vars->end(); - ++pv, ++index) - { - Expression* init = Expression::make_call_result(call, index); - Named_object* no = this->init_var(*pv, type, init, is_coloneq, false, -- &any_new); -+ &any_new, ivars, ivals); - - if (this->gogo_->in_global_scope() && no->is_variable()) - { -@@ -1700,6 +1707,8 @@ - if (is_coloneq && !any_new) - error_at(location, "variables redeclared but no variable is new"); - -+ this->finish_init_vars(ivars, ivals, location); -+ - return true; - } - -@@ -1725,7 +1734,7 @@ - Typed_identifier_list::const_iterator p = vars->begin(); - Expression* init = type == NULL ? index : NULL; - Named_object* val_no = this->init_var(*p, type, init, is_coloneq, -- type == NULL, &any_new); -+ type == NULL, &any_new, NULL, NULL); - if (type == NULL && any_new && val_no->is_variable()) - val_no->var_value()->set_type_from_init_tuple(); - Expression* val_var = Expression::make_var_reference(val_no, location); -@@ -1735,7 +1744,7 @@ - if (var_type == NULL) - var_type = Type::lookup_bool_type(); - Named_object* no = this->init_var(*p, var_type, NULL, is_coloneq, false, -- &any_new); -+ &any_new, NULL, NULL); - Expression* present_var = Expression::make_var_reference(no, location); - - if (is_coloneq && !any_new) -@@ -1790,7 +1799,7 @@ - Typed_identifier_list::const_iterator p = vars->begin(); - Expression* init = type == NULL ? receive : NULL; - Named_object* val_no = this->init_var(*p, type, init, is_coloneq, -- type == NULL, &any_new); -+ type == NULL, &any_new, NULL, NULL); - if (type == NULL && any_new && val_no->is_variable()) - val_no->var_value()->set_type_from_init_tuple(); - Expression* val_var = Expression::make_var_reference(val_no, location); -@@ -1800,7 +1809,7 @@ - if (var_type == NULL) - var_type = Type::lookup_bool_type(); - Named_object* no = this->init_var(*p, var_type, NULL, is_coloneq, false, -- &any_new); -+ &any_new, NULL, NULL); - Expression* received_var = Expression::make_var_reference(no, location); - - if (is_coloneq && !any_new) -@@ -1857,7 +1866,7 @@ - if (var_type == NULL) - var_type = type_guard->type(); - Named_object* val_no = this->init_var(*p, var_type, NULL, is_coloneq, false, -- &any_new); -+ &any_new, NULL, NULL); - Expression* val_var = Expression::make_var_reference(val_no, location); - - ++p; -@@ -1865,7 +1874,7 @@ - if (var_type == NULL) - var_type = Type::lookup_bool_type(); - Named_object* no = this->init_var(*p, var_type, NULL, is_coloneq, false, -- &any_new); -+ &any_new, NULL, NULL); - Expression* ok_var = Expression::make_var_reference(no, location); - - Expression* texpr = type_guard->expr(); -@@ -1904,7 +1913,8 @@ - - Named_object* - Parse::init_var(const Typed_identifier& tid, Type* type, Expression* init, -- bool is_coloneq, bool type_from_init, bool* is_new) -+ bool is_coloneq, bool type_from_init, bool* is_new, -+ Expression_list* vars, Expression_list* vals) - { - Location location = tid.location(); - -@@ -1946,9 +1956,9 @@ - // like v, ok := x.(int). - if (!type_from_init && init != NULL) - { -- Expression *v = Expression::make_var_reference(no, location); -- Statement *s = Statement::make_assignment(v, init, location); -- this->gogo_->add_statement(s); -+ go_assert(vars != NULL && vals != NULL); -+ vars->push_back(Expression::make_var_reference(no, location)); -+ vals->push_back(init); - } - return no; - } -@@ -1983,6 +1993,36 @@ - return this->gogo_->add_variable(buf, var); - } - -+// Finish the variable initialization by executing any assignments to -+// existing variables when using :=. These must be done as a tuple -+// assignment in case of something like n, a, b := 1, b, a. -+ -+void -+Parse::finish_init_vars(Expression_list* vars, Expression_list* vals, -+ Location location) -+{ -+ if (vars->empty()) -+ { -+ delete vars; -+ delete vals; -+ } -+ else if (vars->size() == 1) -+ { -+ go_assert(!this->gogo_->in_global_scope()); -+ this->gogo_->add_statement(Statement::make_assignment(vars->front(), -+ vals->front(), -+ location)); -+ delete vars; -+ delete vals; -+ } -+ else -+ { -+ go_assert(!this->gogo_->in_global_scope()); -+ this->gogo_->add_statement(Statement::make_tuple_assignment(vars, vals, -+ location)); -+ } -+} -+ - // SimpleVarDecl = identifier ":=" Expression . - - // We've already seen the identifier. -@@ -2723,7 +2763,11 @@ - } - else - { -- error_at(this->location(), "expected %<,%> or %<}%>"); -+ if (token->is_op(OPERATOR_SEMICOLON)) -+ error_at(this->location(), -+ "need trailing comma before newline in composite literal"); -+ else -+ error_at(this->location(), "expected %<,%> or %<}%>"); - - this->gogo_->mark_locals_used(); - int depth = 0; -@@ -3311,6 +3355,61 @@ - bool* is_type_switch) - { - const Token* token = this->peek_token(); -+ -+ // There is a complex parse for <- chan. The choices are -+ // Convert x to type <- chan int: -+ // (<- chan int)(x) -+ // Receive from (x converted to type chan <- chan int): -+ // (<- chan <- chan int (x)) -+ // Convert x to type <- chan (<- chan int). -+ // (<- chan <- chan int)(x) -+ if (token->is_op(OPERATOR_CHANOP)) -+ { -+ Location location = token->location(); -+ if (this->advance_token()->is_keyword(KEYWORD_CHAN)) -+ { -+ Expression* expr = this->primary_expr(false, may_be_composite_lit, -+ NULL); -+ if (expr->is_error_expression()) -+ return expr; -+ else if (!expr->is_type_expression()) -+ return Expression::make_receive(expr, location); -+ else -+ { -+ if (expr->type()->is_error_type()) -+ return expr; -+ -+ // We picked up "chan TYPE", but it is not a type -+ // conversion. -+ Channel_type* ct = expr->type()->channel_type(); -+ if (ct == NULL) -+ { -+ // This is probably impossible. -+ error_at(location, "expected channel type"); -+ return Expression::make_error(location); -+ } -+ else if (ct->may_receive()) -+ { -+ // <- chan TYPE. -+ Type* t = Type::make_channel_type(false, true, -+ ct->element_type()); -+ return Expression::make_type(t, location); -+ } -+ else -+ { -+ // <- chan <- TYPE. Because we skipped the leading -+ // <-, we parsed this as chan <- TYPE. With the -+ // leading <-, we parse it as <- chan (<- TYPE). -+ Type *t = this->reassociate_chan_direction(ct, location); -+ return Expression::make_type(t, location); -+ } -+ } -+ } -+ -+ this->unget_token(Token::make_operator_token(OPERATOR_CHANOP, location)); -+ token = this->peek_token(); -+ } -+ - if (token->is_op(OPERATOR_PLUS) - || token->is_op(OPERATOR_MINUS) - || token->is_op(OPERATOR_NOT) -@@ -3323,14 +3422,6 @@ - Operator op = token->op(); - this->advance_token(); - -- if (op == OPERATOR_CHANOP -- && this->peek_token()->is_keyword(KEYWORD_CHAN)) -- { -- // This is "<- chan" which must be the start of a type. -- this->unget_token(Token::make_operator_token(op, location)); -- return Expression::make_type(this->type(), location); -- } -- - Expression* expr = this->unary_expr(false, may_be_composite_lit, NULL); - if (expr->is_error_expression()) - ; -@@ -3350,6 +3441,32 @@ - is_type_switch); - } - -+// This is called for the obscure case of -+// (<- chan <- chan int)(x) -+// In unary_expr we remove the leading <- and parse the remainder, -+// which gives us -+// chan <- (chan int) -+// When we add the leading <- back in, we really want -+// <- chan (<- chan int) -+// This means that we need to reassociate. -+ -+Type* -+Parse::reassociate_chan_direction(Channel_type *ct, Location location) -+{ -+ Channel_type* ele = ct->element_type()->channel_type(); -+ if (ele == NULL) -+ { -+ error_at(location, "parse error"); -+ return Type::make_error_type(); -+ } -+ Type* sub = ele; -+ if (ele->may_send()) -+ sub = Type::make_channel_type(false, true, ele->element_type()); -+ else -+ sub = this->reassociate_chan_direction(ele, location); -+ return Type::make_channel_type(false, true, sub); -+} -+ - // Statement = - // Declaration | LabeledStmt | SimpleStmt | - // GoStmt | ReturnStmt | BreakStmt | ContinueStmt | GotoStmt | -@@ -5036,7 +5153,8 @@ - bool any_new = false; - - const Typed_identifier* pti = &til->front(); -- Named_object* no = this->init_var(*pti, NULL, expr, true, true, &any_new); -+ Named_object* no = this->init_var(*pti, NULL, expr, true, true, &any_new, -+ NULL, NULL); - if (any_new && no->is_variable()) - no->var_value()->set_type_from_range_index(); - p_range_clause->index = Expression::make_var_reference(no, location); -@@ -5047,7 +5165,7 @@ - { - pti = &til->back(); - bool is_new = false; -- no = this->init_var(*pti, NULL, expr, true, true, &is_new); -+ no = this->init_var(*pti, NULL, expr, true, true, &is_new, NULL, NULL); - if (is_new && no->is_variable()) - no->var_value()->set_type_from_range_value(); - if (is_new) -@@ -5337,7 +5455,8 @@ - - if (!token->is_string()) - { -- error_at(this->location(), "missing import package name"); -+ error_at(this->location(), "import statement not a string"); -+ this->advance_token(); - return; - } - ---- a/src/gcc/go/gofrontend/parse.h -+++ b/src/gcc/go/gofrontend/parse.h -@@ -14,6 +14,7 @@ - class Type; - class Typed_identifier; - class Typed_identifier_list; -+class Channel_type; - class Function_type; - class Block; - class Expression; -@@ -205,8 +206,11 @@ - Expression*, bool is_coloneq, - Location); - Named_object* init_var(const Typed_identifier&, Type*, Expression*, -- bool is_coloneq, bool type_from_init, bool* is_new); -+ bool is_coloneq, bool type_from_init, bool* is_new, -+ Expression_list* vars, Expression_list* vals); - Named_object* create_dummy_global(Type*, Expression*, Location); -+ void finish_init_vars(Expression_list* vars, Expression_list* vals, -+ Location); - void simple_var_decl_or_assignment(const std::string&, Location, - bool may_be_composite_lit, - Range_clause*, Type_switch*); -@@ -229,6 +233,7 @@ - bool expression_may_start_here(); - Expression* unary_expr(bool may_be_sink, bool may_be_composite_lit, - bool* is_type_switch); -+ Type* reassociate_chan_direction(Channel_type*, Location); - Expression* qualified_expr(Expression*, Location); - Expression* id_to_expression(const std::string&, Location); - void statement(Label*); ---- a/src/gcc/go/gofrontend/statements.cc -+++ b/src/gcc/go/gofrontend/statements.cc -@@ -3313,16 +3313,10 @@ - p != this->cases_->end(); - ++p) - { -- Expression* this_cond; -- if (val_temp == NULL) -- this_cond = *p; -- else -- { -- Expression* ref = Expression::make_temporary_reference(val_temp, -- loc); -- this_cond = Expression::make_binary(OPERATOR_EQEQ, ref, *p, loc); -- } -- -+ Expression* ref = Expression::make_temporary_reference(val_temp, -+ loc); -+ Expression* this_cond = Expression::make_binary(OPERATOR_EQEQ, ref, -+ *p, loc); - if (cond == NULL) - cond = this_cond; - else -@@ -3846,6 +3840,16 @@ - return new Constant_switch_statement(this->val_, this->clauses_, - this->break_label_, loc); - -+ if (this->val_ != NULL -+ && !this->val_->type()->is_comparable() -+ && !Type::are_compatible_for_comparison(true, this->val_->type(), -+ Type::make_nil_type(), NULL)) -+ { -+ error_at(this->val_->location(), -+ "cannot switch on value whose type that may not be compared"); -+ return Statement::make_error_statement(loc); -+ } -+ - Block* b = new Block(enclosing, loc); - - if (this->clauses_->empty()) -@@ -3856,15 +3860,12 @@ - return Statement::make_statement(val, true); - } - -- Temporary_statement* val_temp; -- if (this->val_ == NULL) -- val_temp = NULL; -- else -- { -- // var val_temp VAL_TYPE = VAL -- val_temp = Statement::make_temporary(NULL, this->val_, loc); -- b->add_statement(val_temp); -- } -+ // var val_temp VAL_TYPE = VAL -+ Expression* val = this->val_; -+ if (val == NULL) -+ val = Expression::make_boolean(true, loc); -+ Temporary_statement* val_temp = Statement::make_temporary(NULL, val, loc); -+ b->add_statement(val_temp); - - this->clauses_->lower(b, val_temp, this->break_label()); - ---- a/src/gcc/go/gofrontend/types.cc -+++ b/src/gcc/go/gofrontend/types.cc -@@ -430,7 +430,7 @@ - - case TYPE_CALL_MULTIPLE_RESULT: - if (reason != NULL) -- *reason = "invalid use of multiple value function call"; -+ *reason = "invalid use of multiple-value function call"; - return false; - - default: -@@ -588,6 +588,9 @@ - p != fields->end(); - ++p) - { -+ if (Gogo::is_sink_name(p->field_name())) -+ continue; -+ - if (!p->type()->is_comparable()) - { - if (reason != NULL) -@@ -633,8 +636,8 @@ - if (rhs->is_call_multiple_result_type()) - { - if (reason != NULL) -- reason->assign(_("multiple value function call in " -- "single value context")); -+ reason->assign(_("multiple-value function call in " -+ "single-value context")); - return false; - } - } -@@ -1295,7 +1298,8 @@ - return "__go_td_" + this->mangled_name(gogo); - - Named_object* no = nt->named_object(); -- const Named_object* in_function = nt->in_function(); -+ unsigned int index; -+ const Named_object* in_function = nt->in_function(&index); - std::string ret = "__go_tdn_"; - if (nt->is_builtin()) - go_assert(in_function == NULL); -@@ -1310,6 +1314,13 @@ - { - ret.append(Gogo::unpack_hidden_name(in_function->name())); - ret.append(1, '.'); -+ if (index > 0) -+ { -+ char buf[30]; -+ snprintf(buf, sizeof buf, "%u", index); -+ ret.append(buf); -+ ret.append(1, '.'); -+ } - } - } - -@@ -1746,9 +1757,19 @@ - { - // This name is already hidden or not as appropriate. - base_name = name->name(); -- const Named_object* in_function = name->in_function(); -+ unsigned int index; -+ const Named_object* in_function = name->in_function(&index); - if (in_function != NULL) -- base_name += '$' + Gogo::unpack_hidden_name(in_function->name()); -+ { -+ base_name += '$' + Gogo::unpack_hidden_name(in_function->name()); -+ if (index > 0) -+ { -+ char buf[30]; -+ snprintf(buf, sizeof buf, "%u", index); -+ base_name += '$'; -+ base_name += buf; -+ } -+ } - } - std::string hash_name = base_name + "$hash"; - std::string equal_name = base_name + "$equal"; -@@ -1989,10 +2010,19 @@ - ? gogo->pkgpath() - : package->pkgpath()); - n.assign(pkgpath); -- if (name->in_function() != NULL) -+ unsigned int index; -+ const Named_object* in_function = name->in_function(&index); -+ if (in_function != NULL) - { - n.append(1, '.'); -- n.append(Gogo::unpack_hidden_name(name->in_function()->name())); -+ n.append(Gogo::unpack_hidden_name(in_function->name())); -+ if (index > 0) -+ { -+ char buf[30]; -+ snprintf(buf, sizeof buf, "%u", index); -+ n.append(1, '.'); -+ n.append(buf); -+ } - } - s = Expression::make_string(n, bloc); - vals->push_back(Expression::make_unary(OPERATOR_AND, s, bloc)); -@@ -4276,6 +4306,9 @@ - pf != fields->end(); - ++pf) - { -+ if (Gogo::is_sink_name(pf->field_name())) -+ return false; -+ - if (!pf->type()->compare_is_identity(gogo)) - return false; - -@@ -4530,6 +4563,20 @@ - return Type::method_function(this->all_methods_, name, is_ambiguous); - } - -+// Return a pointer to the interface method table for this type for -+// the interface INTERFACE. IS_POINTER is true if this is for a -+// pointer to THIS. -+ -+tree -+Struct_type::interface_method_table(Gogo* gogo, -+ const Interface_type* interface, -+ bool is_pointer) -+{ -+ return Type::interface_method_table(gogo, this, interface, is_pointer, -+ &this->interface_method_tables_, -+ &this->pointer_interface_method_tables_); -+} -+ - // Convert struct fields to the backend representation. This is not - // declared in types.h so that types.h doesn't have to #include - // backend.h. -@@ -4749,6 +4796,9 @@ - pf != fields->end(); - ++pf) - { -+ if (Gogo::is_sink_name(pf->field_name())) -+ continue; -+ - if (first) - first = false; - else -@@ -4840,6 +4890,9 @@ - pf != fields->end(); - ++pf, ++field_index) - { -+ if (Gogo::is_sink_name(pf->field_name())) -+ continue; -+ - // Compare one field in both P1 and P2. - Expression* f1 = Expression::make_temporary_reference(p1, bloc); - f1 = Expression::make_unary(OPERATOR_MULT, f1, bloc); -@@ -4875,14 +4928,15 @@ - void - Struct_type::do_reflection(Gogo* gogo, std::string* ret) const - { -- ret->append("struct { "); -+ ret->append("struct {"); - - for (Struct_field_list::const_iterator p = this->fields_->begin(); - p != this->fields_->end(); - ++p) - { - if (p != this->fields_->begin()) -- ret->append("; "); -+ ret->push_back(';'); -+ ret->push_back(' '); - if (p->is_anonymous()) - ret->push_back('?'); - else -@@ -4915,7 +4969,10 @@ - } - } - -- ret->append(" }"); -+ if (!this->fields_->empty()) -+ ret->push_back(' '); -+ -+ ret->push_back('}'); - } - - // Mangled name. -@@ -6815,7 +6872,8 @@ - std::string n = Gogo::message_name(p->name()); - size_t len = 100 + n.length(); - char* buf = new char[len]; -- snprintf(buf, len, _("method %s%s%s requires a pointer"), -+ snprintf(buf, len, -+ _("method %s%s%s requires a pointer receiver"), - open_quote, n.c_str(), close_quote); - reason->assign(buf); - delete[] buf; -@@ -7151,7 +7209,17 @@ - { - if (!p->name().empty()) - { -- std::string n = Gogo::unpack_hidden_name(p->name()); -+ std::string n; -+ if (!Gogo::is_hidden_name(p->name())) -+ n = p->name(); -+ else -+ { -+ n = "."; -+ std::string pkgpath = Gogo::hidden_name_pkgpath(p->name()); -+ n.append(Gogo::pkgpath_for_symbol(pkgpath)); -+ n.append(1, '.'); -+ n.append(Gogo::unpack_hidden_name(p->name())); -+ } - char buf[20]; - snprintf(buf, sizeof buf, "%u_", - static_cast(n.length())); -@@ -7704,32 +7772,9 @@ - Named_type::interface_method_table(Gogo* gogo, const Interface_type* interface, - bool is_pointer) - { -- go_assert(!interface->is_empty()); -- -- Interface_method_tables** pimt = (is_pointer -- ? &this->interface_method_tables_ -- : &this->pointer_interface_method_tables_); -- -- if (*pimt == NULL) -- *pimt = new Interface_method_tables(5); -- -- std::pair val(interface, NULL_TREE); -- std::pair ins = (*pimt)->insert(val); -- -- if (ins.second) -- { -- // This is a new entry in the hash table. -- go_assert(ins.first->second == NULL_TREE); -- ins.first->second = gogo->interface_method_table_for_type(interface, -- this, -- is_pointer); -- } -- -- tree decl = ins.first->second; -- if (decl == error_mark_node) -- return error_mark_node; -- go_assert(decl != NULL_TREE && TREE_CODE(decl) == VAR_DECL); -- return build_fold_addr_expr(decl); -+ return Type::interface_method_table(gogo, this, interface, is_pointer, -+ &this->interface_method_tables_, -+ &this->pointer_interface_method_tables_); - } - - // Return whether a named type has any hidden fields. -@@ -8358,8 +8403,17 @@ - } - if (this->in_function_ != NULL) - { -+ ret->push_back('\t'); - ret->append(Gogo::unpack_hidden_name(this->in_function_->name())); - ret->push_back('$'); -+ if (this->in_function_index_ > 0) -+ { -+ char buf[30]; -+ snprintf(buf, sizeof buf, "%u", this->in_function_index_); -+ ret->append(buf); -+ ret->push_back('$'); -+ } -+ ret->push_back('\t'); - } - ret->append(Gogo::unpack_hidden_name(this->named_object_->name())); - } -@@ -8389,6 +8443,13 @@ - { - name.append(Gogo::unpack_hidden_name(this->in_function_->name())); - name.append(1, '$'); -+ if (this->in_function_index_ > 0) -+ { -+ char buf[30]; -+ snprintf(buf, sizeof buf, "%u", this->in_function_index_); -+ name.append(buf); -+ name.append(1, '$'); -+ } - } - } - name.append(Gogo::unpack_hidden_name(no->name())); -@@ -8899,6 +8960,42 @@ - return m; - } - -+// Return a pointer to the interface method table for TYPE for the -+// interface INTERFACE. -+ -+tree -+Type::interface_method_table(Gogo* gogo, Type* type, -+ const Interface_type *interface, -+ bool is_pointer, -+ Interface_method_tables** method_tables, -+ Interface_method_tables** pointer_tables) -+{ -+ go_assert(!interface->is_empty()); -+ -+ Interface_method_tables** pimt = is_pointer ? method_tables : pointer_tables; -+ -+ if (*pimt == NULL) -+ *pimt = new Interface_method_tables(5); -+ -+ std::pair val(interface, NULL_TREE); -+ std::pair ins = (*pimt)->insert(val); -+ -+ if (ins.second) -+ { -+ // This is a new entry in the hash table. -+ go_assert(ins.first->second == NULL_TREE); -+ ins.first->second = gogo->interface_method_table_for_type(interface, -+ type, -+ is_pointer); -+ } -+ -+ tree decl = ins.first->second; -+ if (decl == error_mark_node) -+ return error_mark_node; -+ go_assert(decl != NULL_TREE && TREE_CODE(decl) == VAR_DECL); -+ return build_fold_addr_expr(decl); -+} -+ - // Look for field or method NAME for TYPE. Return an Expression for - // the field or method bound to EXPR. If there is no such field or - // method, give an appropriate error and return an error expression. -@@ -8990,7 +9087,7 @@ - Gogo::message_name(name).c_str(), ambig1.c_str(), - ambig2.c_str()); - else if (found_pointer_method) -- error_at(location, "method requires a pointer"); -+ error_at(location, "method requires a pointer receiver"); - else if (nt == NULL && st == NULL && it == NULL) - error_at(location, - ("reference to field %qs in object which " ---- a/src/gcc/go/gofrontend/types.h -+++ b/src/gcc/go/gofrontend/types.h -@@ -983,6 +983,19 @@ - method_function(const Methods*, const std::string& name, - bool* is_ambiguous); - -+ // A mapping from interfaces to the associated interface method -+ // tables for this type. This maps to a decl. -+ typedef Unordered_map_hash(const Interface_type*, tree, Type_hash_identical, -+ Type_identical) Interface_method_tables; -+ -+ // Return a pointer to the interface method table for TYPE for the -+ // interface INTERFACE. -+ static tree -+ interface_method_table(Gogo* gogo, Type* type, -+ const Interface_type *interface, bool is_pointer, -+ Interface_method_tables** method_tables, -+ Interface_method_tables** pointer_tables); -+ - // Return a composite literal for the type descriptor entry for a - // type. - static Expression* -@@ -1994,7 +2007,8 @@ - public: - Struct_type(Struct_field_list* fields, Location location) - : Type(TYPE_STRUCT), -- fields_(fields), location_(location), all_methods_(NULL) -+ fields_(fields), location_(location), all_methods_(NULL), -+ interface_method_tables_(NULL), pointer_interface_method_tables_(NULL) - { } - - // Return the field NAME. This only looks at local fields, not at -@@ -2076,6 +2090,14 @@ - Method* - method_function(const std::string& name, bool* is_ambiguous) const; - -+ // Return a pointer to the interface method table for this type for -+ // the interface INTERFACE. If IS_POINTER is true, set the type -+ // descriptor to a pointer to this type, otherwise set it to this -+ // type. -+ tree -+ interface_method_table(Gogo*, const Interface_type* interface, -+ bool is_pointer); -+ - // Traverse just the field types of a struct type. - int - traverse_field_types(Traverse* traverse) -@@ -2156,6 +2178,13 @@ - Location location_; - // If this struct is unnamed, a list of methods. - Methods* all_methods_; -+ // A mapping from interfaces to the associated interface method -+ // tables for this type. Only used if this struct is unnamed. -+ Interface_method_tables* interface_method_tables_; -+ // A mapping from interfaces to the associated interface method -+ // tables for pointers to this type. Only used if this struct is -+ // unnamed. -+ Interface_method_tables* pointer_interface_method_tables_; - }; - - // The type of an array. -@@ -2623,8 +2652,8 @@ - public: - Named_type(Named_object* named_object, Type* type, Location location) - : Type(TYPE_NAMED), -- named_object_(named_object), in_function_(NULL), type_(type), -- local_methods_(NULL), all_methods_(NULL), -+ named_object_(named_object), in_function_(NULL), in_function_index_(0), -+ type_(type), local_methods_(NULL), all_methods_(NULL), - interface_method_tables_(NULL), pointer_interface_method_tables_(NULL), - location_(location), named_btype_(NULL), dependencies_(), - is_visible_(true), is_error_(false), is_placeholder_(false), -@@ -2651,13 +2680,19 @@ - // Return the function in which this type is defined. This will - // return NULL for a type defined in global scope. - const Named_object* -- in_function() const -- { return this->in_function_; } -+ in_function(unsigned int *pindex) const -+ { -+ *pindex = this->in_function_index_; -+ return this->in_function_; -+ } - - // Set the function in which this type is defined. - void -- set_in_function(Named_object* f) -- { this->in_function_ = f; } -+ set_in_function(Named_object* f, unsigned int index) -+ { -+ this->in_function_ = f; -+ this->in_function_index_ = index; -+ } - - // Return the name of the type. - const std::string& -@@ -2855,16 +2890,13 @@ - void - create_placeholder(Gogo*); - -- // A mapping from interfaces to the associated interface method -- // tables for this type. This maps to a decl. -- typedef Unordered_map_hash(const Interface_type*, tree, Type_hash_identical, -- Type_identical) Interface_method_tables; -- - // A pointer back to the Named_object for this type. - Named_object* named_object_; - // If this type is defined in a function, a pointer back to the - // function in which it is defined. - Named_object* in_function_; -+ // The index of this type in IN_FUNCTION_. -+ unsigned int in_function_index_; - // The actual type. - Type* type_; - // The list of methods defined for this type. Any named type can ---- a/src/gcc/go/go-lang.c -+++ b/src/gcc/go/go-lang.c -@@ -85,6 +85,7 @@ - - static const char *go_pkgpath = NULL; - static const char *go_prefix = NULL; -+static const char *go_relative_import_path = NULL; - - /* Language hooks. */ - -@@ -101,7 +102,8 @@ - to, e.g., unsigned_char_type_node) but before calling - build_common_builtin_nodes (because it calls, indirectly, - go_type_for_size). */ -- go_create_gogo (INT_TYPE_SIZE, POINTER_SIZE, go_pkgpath, go_prefix); -+ go_create_gogo (INT_TYPE_SIZE, POINTER_SIZE, go_pkgpath, go_prefix, -+ go_relative_import_path); - - build_common_builtin_nodes (); - -@@ -240,6 +242,10 @@ - go_prefix = arg; - break; - -+ case OPT_fgo_relative_import_path_: -+ go_relative_import_path = arg; -+ break; -+ - default: - /* Just return 1 to indicate that the option is valid. */ - break; ---- a/src/gcc/go/lang.opt -+++ b/src/gcc/go/lang.opt -@@ -61,6 +61,10 @@ - Go Joined RejectNegative - -fgo-prefix= Set package-specific prefix for exported Go names - -+fgo-relative-import-path= -+Go Joined RejectNegative -+-fgo-relative-import-path= Treat a relative import as relative to path -+ - frequire-return-statement - Go Var(go_require_return_statement) Init(1) Warning - Functions which return values must end with return statements ---- a/src/gcc/go/Make-lang.in -+++ b/src/gcc/go/Make-lang.in -@@ -289,10 +289,11 @@ - convert.h output.h $(DIAGNOSTIC_H) $(GO_TYPES_H) \ - $(GO_EXPRESSIONS_H) $(GO_STATEMENTS_H) $(GO_RUNTIME_H) \ - go/gofrontend/backend.h $(GO_GOGO_H) --go/gogo.o: go/gofrontend/gogo.cc $(GO_SYSTEM_H) $(GO_C_H) \ -- go/gofrontend/go-dump.h $(GO_LEX_H) $(GO_TYPES_H) $(GO_STATEMENTS_H) \ -- $(GO_EXPRESSIONS_H) go/gofrontend/dataflow.h $(GO_RUNTIME_H) \ -- $(GO_IMPORT_H) $(GO_EXPORT_H) go/gofrontend/backend.h $(GO_GOGO_H) -+go/gogo.o: go/gofrontend/gogo.cc $(GO_SYSTEM_H) \ -+ $(srcdir)/../include/filenames.h $(GO_C_H) go/gofrontend/go-dump.h \ -+ $(GO_LEX_H) $(GO_TYPES_H) $(GO_STATEMENTS_H) $(GO_EXPRESSIONS_H) \ -+ go/gofrontend/dataflow.h $(GO_RUNTIME_H) $(GO_IMPORT_H) \ -+ $(GO_EXPORT_H) go/gofrontend/backend.h $(GO_GOGO_H) - go/import.o: go/gofrontend/import.cc $(GO_SYSTEM_H) \ - $(srcdir)/../include/filenames.h $(srcdir)/../include/simple-object.h \ - $(GO_C_H) $(GO_GOGO_H) $(GO_LEX_H) $(GO_TYPES_H) $(GO_EXPORT_H) \ ---- a/src/gcc/haifa-sched.c -+++ b/src/gcc/haifa-sched.c -@@ -398,6 +398,14 @@ - /* Create empty basic block after the specified block. */ - basic_block (* sched_create_empty_bb) (basic_block); - -+/* Return the number of cycles until INSN is expected to be ready. -+ Return zero if it already is. */ -+static int -+insn_delay (rtx insn) -+{ -+ return MAX (INSN_TICK (insn) - clock_var, 0); -+} -+ - static int - may_trap_exp (const_rtx x, int is_store) - { -@@ -872,10 +880,10 @@ - - /* Do register pressure sensitive insn scheduling if the flag is set - up. */ --bool sched_pressure_p; -+enum sched_pressure_algorithm sched_pressure; - - /* Map regno -> its pressure class. The map defined only when -- SCHED_PRESSURE_P is true. */ -+ SCHED_PRESSURE != SCHED_PRESSURE_NONE. */ - enum reg_class *sched_regno_pressure_class; - - /* The current register pressure. Only elements corresponding pressure -@@ -903,10 +911,12 @@ - bitmap_clear (region_ref_regs); - } - --/* Update current register pressure related info after birth (if -- BIRTH_P) or death of register REGNO. */ --static void --mark_regno_birth_or_death (int regno, bool birth_p) -+/* PRESSURE[CL] describes the pressure on register class CL. Update it -+ for the birth (if BIRTH_P) or death (if !BIRTH_P) of register REGNO. -+ LIVE tracks the set of live registers; if it is null, assume that -+ every birth or death is genuine. */ -+static inline void -+mark_regno_birth_or_death (bitmap live, int *pressure, int regno, bool birth_p) - { - enum reg_class pressure_class; - -@@ -917,17 +927,17 @@ - { - if (birth_p) - { -- bitmap_set_bit (curr_reg_live, regno); -- curr_reg_pressure[pressure_class] -- += (ira_reg_class_max_nregs -- [pressure_class][PSEUDO_REGNO_MODE (regno)]); -+ if (!live || bitmap_set_bit (live, regno)) -+ pressure[pressure_class] -+ += (ira_reg_class_max_nregs -+ [pressure_class][PSEUDO_REGNO_MODE (regno)]); - } - else - { -- bitmap_clear_bit (curr_reg_live, regno); -- curr_reg_pressure[pressure_class] -- -= (ira_reg_class_max_nregs -- [pressure_class][PSEUDO_REGNO_MODE (regno)]); -+ if (!live || bitmap_clear_bit (live, regno)) -+ pressure[pressure_class] -+ -= (ira_reg_class_max_nregs -+ [pressure_class][PSEUDO_REGNO_MODE (regno)]); - } - } - } -@@ -936,13 +946,13 @@ - { - if (birth_p) - { -- bitmap_set_bit (curr_reg_live, regno); -- curr_reg_pressure[pressure_class]++; -+ if (!live || bitmap_set_bit (live, regno)) -+ pressure[pressure_class]++; - } - else - { -- bitmap_clear_bit (curr_reg_live, regno); -- curr_reg_pressure[pressure_class]--; -+ if (!live || bitmap_clear_bit (live, regno)) -+ pressure[pressure_class]--; - } - } - } -@@ -960,8 +970,10 @@ - curr_reg_pressure[ira_pressure_classes[i]] = 0; - bitmap_clear (curr_reg_live); - EXECUTE_IF_SET_IN_BITMAP (live, 0, j, bi) -- if (current_nr_blocks == 1 || bitmap_bit_p (region_ref_regs, j)) -- mark_regno_birth_or_death (j, true); -+ if (sched_pressure == SCHED_PRESSURE_MODEL -+ || current_nr_blocks == 1 -+ || bitmap_bit_p (region_ref_regs, j)) -+ mark_regno_birth_or_death (curr_reg_live, curr_reg_pressure, j, true); - } - - /* Mark registers in X as mentioned in the current region. */ -@@ -1015,7 +1027,8 @@ - if (regno == INVALID_REGNUM) - break; - if (! bitmap_bit_p (df_get_live_in (bb), regno)) -- mark_regno_birth_or_death (regno, true); -+ mark_regno_birth_or_death (curr_reg_live, curr_reg_pressure, -+ regno, true); - } - #endif - } -@@ -1445,19 +1458,19 @@ - return true; - } - --/* Compute the number of nondebug forward deps of an insn. */ -+/* Compute the number of nondebug deps in list LIST for INSN. */ - - static int --dep_list_size (rtx insn) -+dep_list_size (rtx insn, sd_list_types_def list) - { - sd_iterator_def sd_it; - dep_t dep; - int dbgcount = 0, nodbgcount = 0; - - if (!MAY_HAVE_DEBUG_INSNS) -- return sd_lists_size (insn, SD_LIST_FORW); -+ return sd_lists_size (insn, list); - -- FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep) -+ FOR_EACH_DEP (insn, list, sd_it, dep) - { - if (DEBUG_INSN_P (DEP_CON (dep))) - dbgcount++; -@@ -1465,7 +1478,7 @@ - nodbgcount++; - } - -- gcc_assert (dbgcount + nodbgcount == sd_lists_size (insn, SD_LIST_FORW)); -+ gcc_assert (dbgcount + nodbgcount == sd_lists_size (insn, list)); - - return nodbgcount; - } -@@ -1484,7 +1497,7 @@ - { - int this_priority = -1; - -- if (dep_list_size (insn) == 0) -+ if (dep_list_size (insn, SD_LIST_FORW) == 0) - /* ??? We should set INSN_PRIORITY to insn_cost when and insn has - some forward deps but all of them are ignored by - contributes_to_priority hook. At the moment we set priority of -@@ -1580,6 +1593,22 @@ - qsort (READY, N_READY, sizeof (rtx), rank_for_schedule); } \ - while (0) - -+/* For each pressure class CL, set DEATH[CL] to the number of registers -+ in that class that die in INSN. */ -+ -+static void -+calculate_reg_deaths (rtx insn, int *death) -+{ -+ int i; -+ struct reg_use_data *use; ++ int i; ++ struct reg_use_data *use; + + for (i = 0; i < ira_pressure_classes_num; i++) + death[ira_pressure_classes[i]] = 0; @@ -56003,7 +59902,7 @@ } free (curr_state); -@@ -5244,7 +6696,7 @@ +@@ -5247,7 +6699,7 @@ INSN_TICK (next) = tick; delay = tick - clock_var; @@ -56012,7 +59911,7 @@ delay = QUEUE_READY; change_queue_index (next, delay); -@@ -6499,7 +7951,7 @@ +@@ -6502,7 +7954,7 @@ if (insn == jump) break; @@ -56021,7 +59920,7 @@ { dep_def _new_dep, *new_dep = &_new_dep; -@@ -6640,6 +8092,7 @@ +@@ -6643,6 +8095,7 @@ FOR_EACH_VEC_ELT (haifa_insn_data_def, h_i_d, i, data) { @@ -56029,7 +59928,7 @@ free (data->reg_pressure); for (use = data->reg_use_list; use != NULL; use = next) { -@@ -6670,7 +8123,7 @@ +@@ -6673,7 +8126,7 @@ /* Extend dependency caches by one element. */ extend_dependency_caches (1, false); } @@ -56040,339 +59939,224 @@ --- a/src/gcc/ifcvt.c +++ b/src/gcc/ifcvt.c -@@ -44,6 +44,7 @@ - #include "tree-pass.h" - #include "df.h" - #include "vec.h" -+#include "pointer-set.h" - #include "vecprim.h" - #include "dbgcnt.h" - -@@ -2689,12 +2690,14 @@ - - /* Check whether a block is suitable for conditional move conversion. - Every insn must be a simple set of a register to a constant or a -- register. For each assignment, store the value in the array VALS, -- indexed by register number, then store the register number in -- REGS. COND is the condition we will test. */ -+ register. For each assignment, store the value in the pointer map -+ VALS, keyed indexed by register pointer, then store the register -+ pointer in REGS. COND is the condition we will test. */ - - static int --check_cond_move_block (basic_block bb, rtx *vals, VEC (int, heap) **regs, -+check_cond_move_block (basic_block bb, -+ struct pointer_map_t *vals, -+ VEC (rtx, heap) **regs, - rtx cond) +@@ -2496,6 +2496,12 @@ + || ! noce_operand_ok (SET_SRC (set_b)) + || reg_overlap_mentioned_p (x, SET_SRC (set_b)) + || modified_between_p (SET_SRC (set_b), insn_b, jump) ++ /* Avoid extending the lifetime of hard registers on small ++ register class machines. */ ++ || (REG_P (SET_SRC (set_b)) ++ && HARD_REGISTER_P (SET_SRC (set_b)) ++ && targetm.small_register_classes_for_mode_p ++ (GET_MODE (SET_SRC (set_b)))) + /* Likewise with X. In particular this can happen when + noce_get_condition looks farther back in the instruction + stream than one might expect. */ +--- a/src/gcc/LINARO-VERSION ++++ b/src/gcc/LINARO-VERSION +@@ -0,0 +1 @@ ++4.7-2013.04-1~dev +--- a/src/gcc/lower-subreg.c ++++ b/src/gcc/lower-subreg.c +@@ -233,9 +233,9 @@ { - rtx insn; -@@ -2708,6 +2711,7 @@ - FOR_BB_INSNS (bb, insn) - { - rtx set, dest, src; -+ void **slot; + /* Not a simple move from one location to another. */ + NOT_SIMPLE_MOVE, +- /* A simple move from one pseudo-register to another. */ +- SIMPLE_PSEUDO_REG_MOVE, +- /* A simple move involving a non-pseudo-register. */ ++ /* A simple move we want to decompose. */ ++ DECOMPOSABLE_SIMPLE_MOVE, ++ /* Any other simple move. */ + SIMPLE_MOVE + }; - if (!NONDEBUG_INSN_P (insn) || JUMP_P (insn)) - continue; -@@ -2734,14 +2738,14 @@ - /* Don't try to handle this if the source register was - modified earlier in the block. */ - if ((REG_P (src) -- && vals[REGNO (src)] != NULL) -+ && pointer_map_contains (vals, src)) - || (GET_CODE (src) == SUBREG && REG_P (SUBREG_REG (src)) -- && vals[REGNO (SUBREG_REG (src))] != NULL)) -+ && pointer_map_contains (vals, SUBREG_REG (src)))) - return FALSE; - - /* Don't try to handle this if the destination register was - modified earlier in the block. */ -- if (vals[REGNO (dest)] != NULL) -+ if (pointer_map_contains (vals, dest)) - return FALSE; - - /* Don't try to handle this if the condition uses the -@@ -2755,17 +2759,18 @@ - && modified_between_p (src, insn, NEXT_INSN (BB_END (bb)))) - return FALSE; - -- vals[REGNO (dest)] = src; -+ slot = pointer_map_insert (vals, (void *) dest); -+ *slot = (void *) src; +@@ -311,7 +311,7 @@ -- VEC_safe_push (int, heap, *regs, REGNO (dest)); -+ VEC_safe_push (rtx, heap, *regs, dest); - } + If this is not a simple copy from one location to another, + then we can not decompose this register. If this is a simple +- copy from one pseudo-register to another, and the mode is right ++ copy we want to decompose, and the mode is right, + then we mark the register as decomposable. + Otherwise we don't say anything about this register -- + it could be decomposed, but whether that would be +@@ -330,7 +330,7 @@ + case NOT_SIMPLE_MOVE: + bitmap_set_bit (non_decomposable_context, regno); + break; +- case SIMPLE_PSEUDO_REG_MOVE: ++ case DECOMPOSABLE_SIMPLE_MOVE: + if (MODES_TIEABLE_P (GET_MODE (x), word_mode)) + bitmap_set_bit (decomposable_context, regno); + break; +@@ -346,7 +346,7 @@ + enum classify_move_insn cmi_mem = NOT_SIMPLE_MOVE; - return TRUE; - } + /* Any registers used in a MEM do not participate in a +- SIMPLE_MOVE or SIMPLE_PSEUDO_REG_MOVE. Do our own recursion ++ SIMPLE_MOVE or DECOMPOSABLE_SIMPLE_MOVE. Do our own recursion + here, and return -1 to block the parent's recursion. */ + for_each_rtx (&XEXP (x, 0), find_decomposable_subregs, &cmi_mem); + return -1; +@@ -1074,11 +1074,11 @@ + } + + /* Look for registers which are always accessed via word-sized SUBREGs +- or via copies. Decompose these registers into several word-sized +- pseudo-registers. */ ++ or -if DECOMPOSE_COPIES is true- via copies. Decompose these ++ registers into several word-sized pseudo-registers. */ - /* Given a basic block BB suitable for conditional move conversion, -- a condition COND, and arrays THEN_VALS and ELSE_VALS containing the -- register values depending on COND, emit the insns in the block as -+ a condition COND, and pointer maps THEN_VALS and ELSE_VALS containing -+ the register values depending on COND, emit the insns in the block as - conditional moves. If ELSE_BLOCK is true, THEN_BB was already - processed. The caller has started a sequence for the conversion. - Return true if successful, false if something goes wrong. */ -@@ -2773,7 +2778,8 @@ - static bool - cond_move_convert_if_block (struct noce_if_info *if_infop, - basic_block bb, rtx cond, -- rtx *then_vals, rtx *else_vals, -+ struct pointer_map_t *then_vals, -+ struct pointer_map_t *else_vals, - bool else_block_p) + static void +-decompose_multiword_subregs (void) ++decompose_multiword_subregs (bool decompose_copies) { - enum rtx_code code; -@@ -2786,7 +2792,7 @@ - FOR_BB_INSNS (bb, insn) - { - rtx set, target, dest, t, e; -- unsigned int regno; -+ void **then_slot, **else_slot; - - /* ??? Maybe emit conditional debug insn? */ - if (!NONDEBUG_INSN_P (insn) || JUMP_P (insn)) -@@ -2795,10 +2801,11 @@ - gcc_assert (set && REG_P (SET_DEST (set))); - - dest = SET_DEST (set); -- regno = REGNO (dest); - -- t = then_vals[regno]; -- e = else_vals[regno]; -+ then_slot = pointer_map_contains (then_vals, dest); -+ else_slot = pointer_map_contains (else_vals, dest); -+ t = then_slot ? (rtx) *then_slot : NULL_RTX; -+ e = else_slot ? (rtx) *else_slot : NULL_RTX; - - if (else_block_p) - { -@@ -2842,31 +2849,25 @@ - rtx jump = if_info->jump; - rtx cond = if_info->cond; - rtx seq, loc_insn; -- int max_reg, size, c, reg; -- rtx *then_vals; -- rtx *else_vals; -- VEC (int, heap) *then_regs = NULL; -- VEC (int, heap) *else_regs = NULL; -+ rtx reg; -+ int c; -+ struct pointer_map_t *then_vals; -+ struct pointer_map_t *else_vals; -+ VEC (rtx, heap) *then_regs = NULL; -+ VEC (rtx, heap) *else_regs = NULL; - unsigned int i; -+ int success_p = FALSE; - - /* Build a mapping for each block to the value used for each - register. */ -- max_reg = max_reg_num (); -- size = (max_reg + 1) * sizeof (rtx); -- then_vals = (rtx *) alloca (size); -- else_vals = (rtx *) alloca (size); -- memset (then_vals, 0, size); -- memset (else_vals, 0, size); -+ then_vals = pointer_map_create (); -+ else_vals = pointer_map_create (); - - /* Make sure the blocks are suitable. */ - if (!check_cond_move_block (then_bb, then_vals, &then_regs, cond) - || (else_bb - && !check_cond_move_block (else_bb, else_vals, &else_regs, cond))) -- { -- VEC_free (int, heap, then_regs); -- VEC_free (int, heap, else_regs); -- return FALSE; -- } -+ goto done; - - /* Make sure the blocks can be used together. If the same register - is set in both blocks, and is not set to a constant in both -@@ -2875,41 +2876,38 @@ - source register does not change after the assignment. Also count - the number of registers set in only one of the blocks. */ - c = 0; -- FOR_EACH_VEC_ELT (int, then_regs, i, reg) -+ FOR_EACH_VEC_ELT (rtx, then_regs, i, reg) - { -- if (!then_vals[reg] && !else_vals[reg]) -- continue; -+ void **then_slot = pointer_map_contains (then_vals, reg); -+ void **else_slot = pointer_map_contains (else_vals, reg); - -- if (!else_vals[reg]) -+ gcc_checking_assert (then_slot); -+ if (!else_slot) - ++c; - else - { -- if (!CONSTANT_P (then_vals[reg]) -- && !CONSTANT_P (else_vals[reg]) -- && !rtx_equal_p (then_vals[reg], else_vals[reg])) -- { -- VEC_free (int, heap, then_regs); -- VEC_free (int, heap, else_regs); -- return FALSE; -- } -+ rtx then_val = (rtx) *then_slot; -+ rtx else_val = (rtx) *else_slot; -+ if (!CONSTANT_P (then_val) && !CONSTANT_P (else_val) -+ && !rtx_equal_p (then_val, else_val)) -+ goto done; - } - } - - /* Finish off c for MAX_CONDITIONAL_EXECUTE. */ -- FOR_EACH_VEC_ELT (int, else_regs, i, reg) -- if (!then_vals[reg]) -- ++c; -+ FOR_EACH_VEC_ELT (rtx, else_regs, i, reg) -+ { -+ gcc_checking_assert (pointer_map_contains (else_vals, reg)); -+ if (!pointer_map_contains (then_vals, reg)) -+ ++c; -+ } - - /* Make sure it is reasonable to convert this block. What matters - is the number of assignments currently made in only one of the - branches, since if we convert we are going to always execute - them. */ - if (c > MAX_CONDITIONAL_EXECUTE) -- { -- VEC_free (int, heap, then_regs); -- VEC_free (int, heap, else_regs); -- return FALSE; -- } -+ goto done; - - /* Try to emit the conditional moves. First do the then block, - then do anything left in the else blocks. */ -@@ -2921,17 +2919,11 @@ - then_vals, else_vals, true))) - { - end_sequence (); -- VEC_free (int, heap, then_regs); -- VEC_free (int, heap, else_regs); -- return FALSE; -+ goto done; - } - seq = end_ifcvt_sequence (if_info); - if (!seq) -- { -- VEC_free (int, heap, then_regs); -- VEC_free (int, heap, else_regs); -- return FALSE; -- } -+ goto done; - - loc_insn = first_active_insn (then_bb); - if (!loc_insn) -@@ -2962,9 +2954,14 @@ - - num_updated_if_blocks++; - -- VEC_free (int, heap, then_regs); -- VEC_free (int, heap, else_regs); -- return TRUE; -+ success_p = TRUE; -+ -+done: -+ pointer_map_destroy (then_vals); -+ pointer_map_destroy (else_vals); -+ VEC_free (rtx, heap, then_regs); -+ VEC_free (rtx, heap, else_regs); -+ return success_p; + unsigned int max; + basic_block bb; +@@ -1149,8 +1149,15 @@ + cmi = NOT_SIMPLE_MOVE; + else + { ++ /* We mark pseudo-to-pseudo copies as decomposable during the ++ second pass only. The first pass is so early that there is ++ good chance such moves will be optimized away completely by ++ subsequent optimizations anyway. ++ ++ However, we call find_pseudo_copy even during the first pass ++ so as to properly set up the reg_copy_graph. */ + if (find_pseudo_copy (set)) +- cmi = SIMPLE_PSEUDO_REG_MOVE; ++ cmi = decompose_copies? DECOMPOSABLE_SIMPLE_MOVE : SIMPLE_MOVE; + else + cmi = SIMPLE_MOVE; + } +@@ -1351,7 +1358,7 @@ + static unsigned int + rest_of_handle_lower_subreg (void) + { +- decompose_multiword_subregs (); ++ decompose_multiword_subregs (false); + return 0; } - ---- a/src/gcc/ira-int.h -+++ b/src/gcc/ira-int.h -@@ -1138,8 +1138,13 @@ - ira_allocno_object_iter_cond (ira_allocno_object_iterator *i, ira_allocno_t a, - ira_object_t *o) +@@ -1360,7 +1367,7 @@ + static unsigned int + rest_of_handle_lower_subreg2 (void) { -- *o = ALLOCNO_OBJECT (a, i->n); -- return i->n++ < ALLOCNO_NUM_OBJECTS (a); -+ int n = i->n++; -+ if (n < ALLOCNO_NUM_OBJECTS (a)) -+ { -+ *o = ALLOCNO_OBJECT (a, n); -+ return true; -+ } -+ return false; +- decompose_multiword_subregs (); ++ decompose_multiword_subregs (true); + return 0; } - /* Loop over all objects associated with allocno A. In each ---- a/src/gcc/LINARO-VERSION -+++ b/src/gcc/LINARO-VERSION -@@ -0,0 +1 @@ -+4.7-2012.11 ---- a/src/gcc/lto/ChangeLog -+++ b/src/gcc/lto/ChangeLog -@@ -1,3 +1,12 @@ -+2012-09-20 Richard Guenther -+ -+ Backport from mainline -+ 2012-09-11 Jan Hubicka -+ -+ PR lto/54312 -+ * lto.c (uniquify_nodes): Remove quadratic loop checking if the -+ type is variant leader. -+ - 2012-09-20 Release Manager - - * GCC 4.7.2 released. ---- a/src/gcc/lto/lto.c -+++ b/src/gcc/lto/lto.c -@@ -761,6 +761,7 @@ - variant list state before fixup is broken. */ - tree tem, mv; - -+#ifdef ENABLE_CHECKING - /* Remove us from our main variant list if we are not the - variant leader. */ - if (TYPE_MAIN_VARIANT (t) != t) -@@ -768,10 +769,9 @@ - tem = TYPE_MAIN_VARIANT (t); - while (tem && TYPE_NEXT_VARIANT (tem) != t) - tem = TYPE_NEXT_VARIANT (tem); -- if (tem) -- TYPE_NEXT_VARIANT (tem) = TYPE_NEXT_VARIANT (t); -- TYPE_NEXT_VARIANT (t) = NULL_TREE; -+ gcc_assert (!tem && !TYPE_NEXT_VARIANT (t)); - } -+#endif - - /* Query our new main variant. */ - mv = GIMPLE_REGISTER_TYPE (TYPE_MAIN_VARIANT (t)); --- a/src/gcc/Makefile.in +++ b/src/gcc/Makefile.in -@@ -1833,10 +1833,11 @@ +@@ -1848,11 +1848,12 @@ "$(MULTILIB_EXTRA_OPTS)" \ "$(MULTILIB_EXCLUSIONS)" \ "$(MULTILIB_OSDIRNAMES)" \ + "$(MULTILIB_REQUIRED)" \ + "$(MULTIARCH_DIRNAME)" \ "@enable_multilib@" \ > tmp-mlib.h; \ else \ -- $(SHELL) $(srcdir)/genmultilib '' '' '' '' '' '' '' no \ -+ $(SHELL) $(srcdir)/genmultilib '' '' '' '' '' '' '' '' no\ +- $(SHELL) $(srcdir)/genmultilib '' '' '' '' '' '' '' "$(MULTIARCH_DIRNAME)" no \ ++ $(SHELL) $(srcdir)/genmultilib '' '' '' '' '' '' '' '' "$(MULTIARCH_DIRNAME)" no \ > tmp-mlib.h; \ fi $(SHELL) $(srcdir)/../move-if-change tmp-mlib.h multilib.h -@@ -3417,7 +3418,7 @@ - ifcvt.o : ifcvt.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(RTL_H) \ - $(REGS_H) $(DIAGNOSTIC_CORE_H) $(FLAGS_H) insn-config.h $(FUNCTION_H) $(RECOG_H) \ - $(TARGET_H) $(BASIC_BLOCK_H) $(EXPR_H) output.h $(EXCEPT_H) $(TM_P_H) \ -- $(OPTABS_H) $(CFGLOOP_H) hard-reg-set.h $(TIMEVAR_H) \ -+ $(OPTABS_H) $(CFGLOOP_H) hard-reg-set.h pointer-set.h $(TIMEVAR_H) \ - $(TREE_PASS_H) $(DF_H) $(DBGCNT_H) - params.o : params.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(COMMON_TARGET_H) \ - $(PARAMS_H) $(DIAGNOSTIC_CORE_H) +@@ -3904,7 +3905,7 @@ + $(SYSTEM_H) coretypes.h $(GTM_H) errors.h $(READ_MD_H) gensupport.h + build/gengenrtl.o : gengenrtl.c $(BCONFIG_H) $(SYSTEM_H) rtl.def + gengtype-lex.o build/gengtype-lex.o : gengtype-lex.c gengtype.h $(SYSTEM_H) +-gengtype-lex.o: $(CONFIG_H) ++gengtype-lex.o: $(CONFIG_H) $(BCONFIG_H) + build/gengtype-lex.o: $(BCONFIG_H) + gengtype-parse.o build/gengtype-parse.o : gengtype-parse.c gengtype.h \ + $(SYSTEM_H) +--- a/src/gcc/optabs.c ++++ b/src/gcc/optabs.c +@@ -3028,6 +3028,47 @@ + /* Widening (or narrowing) bswap needs special treatment. */ + if (unoptab == bswap_optab) + { ++ /* HImode is special because in this mode BSWAP is equivalent to ROTATE ++ or ROTATERT. First try these directly; if this fails, then try the ++ obvious pair of shifts with allowed widening, as this will probably ++ be always more efficient than the other fallback methods. */ ++ if (mode == HImode) ++ { ++ rtx last, temp1, temp2; ++ ++ if (optab_handler (rotl_optab, mode) != CODE_FOR_nothing) ++ { ++ temp = expand_binop (mode, rotl_optab, op0, GEN_INT (8), target, ++ unsignedp, OPTAB_DIRECT); ++ if (temp) ++ return temp; ++ } ++ ++ if (optab_handler (rotr_optab, mode) != CODE_FOR_nothing) ++ { ++ temp = expand_binop (mode, rotr_optab, op0, GEN_INT (8), target, ++ unsignedp, OPTAB_DIRECT); ++ if (temp) ++ return temp; ++ } ++ ++ last = get_last_insn (); ++ ++ temp1 = expand_binop (mode, ashl_optab, op0, GEN_INT (8), NULL_RTX, ++ unsignedp, OPTAB_WIDEN); ++ temp2 = expand_binop (mode, lshr_optab, op0, GEN_INT (8), NULL_RTX, ++ unsignedp, OPTAB_WIDEN); ++ if (temp1 && temp2) ++ { ++ temp = expand_binop (mode, ior_optab, temp1, temp2, target, ++ unsignedp, OPTAB_WIDEN); ++ if (temp) ++ return temp; ++ } ++ ++ delete_insns_since (last); ++ } ++ + temp = widen_bswap (mode, op0, target); + if (temp) + return temp; +@@ -3219,10 +3260,10 @@ + /* For certain operations, we need not actually extend + the narrow operand, as long as we will truncate the + results to the same narrowness. */ +- + xop0 = widen_operand (xop0, wider_mode, mode, unsignedp, + (unoptab == neg_optab +- || unoptab == one_cmpl_optab) ++ || unoptab == one_cmpl_optab ++ || unoptab == bswap_optab) + && mclass == MODE_INT); + + temp = expand_unop (wider_mode, unoptab, xop0, NULL_RTX, +@@ -3237,6 +3278,20 @@ + - GET_MODE_PRECISION (mode)), + target, true, OPTAB_DIRECT); + ++ /* Likewise for bswap. */ ++ if (unoptab == bswap_optab && temp != 0) ++ { ++ gcc_assert (GET_MODE_PRECISION (wider_mode) ++ == GET_MODE_BITSIZE (wider_mode) ++ && GET_MODE_PRECISION (mode) ++ == GET_MODE_BITSIZE (mode)); ++ ++ temp = expand_shift (RSHIFT_EXPR, wider_mode, temp, ++ GET_MODE_BITSIZE (wider_mode) ++ - GET_MODE_BITSIZE (mode), ++ NULL_RTX, true); ++ } ++ + if (temp) + { + if (mclass != MODE_INT) --- a/src/gcc/opts.c +++ b/src/gcc/opts.c @@ -499,6 +499,7 @@ @@ -56383,226607 +60167,6 @@ /* -Ofast adds optimizations to -O3. */ { OPT_LEVELS_FAST, OPT_ffast_math, NULL, 1 }, -Binary files gcc-4.7.2/gcc/po/be.gmo and gcc-linaro-4.7-2012.11/gcc/po/be.gmo differ ---- a/src/gcc/po/be.po -+++ b/src/gcc/po/be.po -@@ -6,7 +6,7 @@ - msgstr "" - "Project-Id-Version: gcc 3.1\n" - "Report-Msgid-Bugs-To: http://gcc.gnu.org/bugs.html\n" --"POT-Creation-Date: 2012-06-13 21:42+0000\n" -+"POT-Creation-Date: 2012-09-19 14:50+0000\n" - "PO-Revision-Date: 2002-05-17 15:54+0200\n" - "Last-Translator: Ales Nyakhaychyk \n" - "Language-Team: Belarusian \n" -@@ -24,7 +24,7 @@ - msgid "({anonymous})" - msgstr "" - --#: c-parser.c:946 cp/parser.c:22268 -+#: c-parser.c:946 cp/parser.c:22263 - #, gcc-internal-format - msgid "expected end of line" - msgstr "" -@@ -34,8 +34,8 @@ - #: c-parser.c:7308 c-parser.c:7343 c-parser.c:7374 c-parser.c:7421 - #: c-parser.c:7602 c-parser.c:8369 c-parser.c:8439 c-parser.c:8482 - #: c-parser.c:9760 c-parser.c:9775 c-parser.c:9784 c-parser.c:9929 --#: c-parser.c:9968 c-parser.c:2500 c-parser.c:7595 cp/parser.c:21791 --#: cp/parser.c:22214 -+#: c-parser.c:9968 c-parser.c:2500 c-parser.c:7595 cp/parser.c:21786 -+#: cp/parser.c:22209 - #, gcc-internal-format - msgid "expected %<;%>" - msgstr "" -@@ -47,13 +47,13 @@ - #: c-parser.c:6703 c-parser.c:6727 c-parser.c:7893 c-parser.c:7965 - #: c-parser.c:8791 c-parser.c:8812 c-parser.c:8862 c-parser.c:9015 - #: c-parser.c:9094 c-parser.c:9178 c-parser.c:9892 c-parser.c:10716 --#: c-parser.c:8935 c-parser.c:8960 cp/parser.c:22217 -+#: c-parser.c:8935 c-parser.c:8960 cp/parser.c:22212 - #, gcc-internal-format - msgid "expected %<(%>" - msgstr "" - - #: c-parser.c:1845 c-parser.c:6389 c-parser.c:6427 c-parser.c:6555 --#: cp/parser.c:21789 cp/parser.c:22232 -+#: cp/parser.c:21784 cp/parser.c:22227 - #, gcc-internal-format - msgid "expected %<,%>" - msgstr "" -@@ -69,14 +69,14 @@ - #: c-parser.c:7687 c-parser.c:7708 c-parser.c:7916 c-parser.c:7969 - #: c-parser.c:8341 c-parser.c:8794 c-parser.c:8815 c-parser.c:8893 - #: c-parser.c:9022 c-parser.c:9159 c-parser.c:9242 c-parser.c:9820 --#: c-parser.c:9937 c-parser.c:9979 c-parser.c:10725 cp/parser.c:22262 -+#: c-parser.c:9937 c-parser.c:9979 c-parser.c:10725 cp/parser.c:22257 - #, gcc-internal-format - msgid "expected %<)%>" - msgstr "" - - #: c-parser.c:3095 c-parser.c:3904 c-parser.c:3938 c-parser.c:5224 - #: c-parser.c:6491 c-parser.c:6760 c-parser.c:6866 c-parser.c:10628 --#: c-parser.c:10630 cp/parser.c:22226 -+#: c-parser.c:10630 cp/parser.c:22221 - #, gcc-internal-format - msgid "expected %<]%>" - msgstr "" -@@ -85,25 +85,25 @@ - msgid "expected %<;%>, %<,%> or %<)%>" - msgstr "" - --#: c-parser.c:3767 c-parser.c:9776 cp/parser.c:22220 cp/parser.c:24037 -+#: c-parser.c:3767 c-parser.c:9776 cp/parser.c:22215 cp/parser.c:24032 - #, gcc-internal-format - msgid "expected %<}%>" - msgstr "" - - #: c-parser.c:4057 c-parser.c:7936 c-parser.c:10222 c-parser.c:2318 --#: c-parser.c:2521 c-parser.c:7490 cp/parser.c:14425 cp/parser.c:22223 -+#: c-parser.c:2521 c-parser.c:7490 cp/parser.c:14425 cp/parser.c:22218 - #, gcc-internal-format - msgid "expected %<{%>" - msgstr "" - - #: c-parser.c:4276 c-parser.c:4285 c-parser.c:5128 c-parser.c:5469 - #: c-parser.c:7701 c-parser.c:8076 c-parser.c:8133 c-parser.c:9148 --#: cp/parser.c:22256 cp/parser.c:23258 -+#: cp/parser.c:22251 cp/parser.c:23253 - #, gcc-internal-format - msgid "expected %<:%>" - msgstr "" - --#: c-parser.c:4824 cp/parser.c:22150 -+#: c-parser.c:4824 cp/parser.c:22145 - #, gcc-internal-format - msgid "expected %" - msgstr "" -@@ -112,34 +112,34 @@ - msgid "expected %<.%>" - msgstr "" - --#: c-parser.c:7161 c-parser.c:7193 c-parser.c:7433 cp/parser.c:23821 --#: cp/parser.c:23895 -+#: c-parser.c:7161 c-parser.c:7193 c-parser.c:7433 cp/parser.c:23816 -+#: cp/parser.c:23890 - #, gcc-internal-format - msgid "expected %<@end%>" - msgstr "" - --#: c-parser.c:7850 cp/parser.c:22241 -+#: c-parser.c:7850 cp/parser.c:22236 - #, gcc-internal-format - msgid "expected %<>%>" - msgstr "" - --#: c-parser.c:9246 cp/parser.c:22265 -+#: c-parser.c:9246 cp/parser.c:22260 - #, gcc-internal-format - msgid "expected %<,%> or %<)%>" - msgstr "" - - #: c-parser.c:9499 c-parser.c:9530 c-parser.c:9766 c-parser.c:9918 --#: c-parser.c:3961 cp/parser.c:22244 -+#: c-parser.c:3961 cp/parser.c:22239 - #, gcc-internal-format - msgid "expected %<=%>" - msgstr "" - --#: c-parser.c:10279 c-parser.c:10269 cp/parser.c:26674 -+#: c-parser.c:10279 c-parser.c:10269 cp/parser.c:26669 - #, gcc-internal-format - msgid "expected %<#pragma omp section%> or %<}%>" - msgstr "" - --#: c-parser.c:10616 cp/parser.c:22229 -+#: c-parser.c:10616 cp/parser.c:22224 - #, gcc-internal-format - msgid "expected %<[%>" - msgstr "" -@@ -316,12 +316,12 @@ - #. TARGET_PRINT_OPERAND must handle them. - #. We can't handle floating point constants; - #. PRINT_OPERAND must handle them. --#: final.c:3615 config/i386/i386.c:13086 config/pdp11/pdp11.c:1689 -+#: final.c:3615 config/i386/i386.c:13180 config/pdp11/pdp11.c:1689 - #, c-format - msgid "floating constant misused" - msgstr "" - --#: final.c:3673 config/i386/i386.c:13184 config/pdp11/pdp11.c:1730 -+#: final.c:3673 config/i386/i386.c:13278 config/pdp11/pdp11.c:1730 - #, c-format - msgid "invalid expression as operand" - msgstr "" -@@ -1395,20 +1395,20 @@ - msgid "insn does not satisfy its constraints:" - msgstr "" - --#: targhooks.c:1404 -+#: targhooks.c:1411 - #, c-format - msgid "created and used with differing settings of '%s'" - msgstr "" - --#: targhooks.c:1406 -+#: targhooks.c:1413 - msgid "out of memory" - msgstr "" - --#: targhooks.c:1421 -+#: targhooks.c:1428 - msgid "created and used with different settings of -fpic" - msgstr "" - --#: targhooks.c:1423 -+#: targhooks.c:1430 - msgid "created and used with different settings of -fpie" - msgstr "" - -@@ -2028,195 +2028,195 @@ - msgid "The maximum number of RTL nodes that can be recorded as combiner's last value" - msgstr "" - --#: params.def:644 -+#: params.def:645 - msgid "The upper bound for sharing integer constants" - msgstr "" - --#: params.def:663 -+#: params.def:664 - msgid "Minimum number of virtual mappings to consider switching to full virtual renames" - msgstr "" - --#: params.def:668 -+#: params.def:669 - msgid "Ratio between virtual mappings and virtual symbols to do full virtual renames" - msgstr "" - --#: params.def:673 -+#: params.def:674 - msgid "The lower bound for a buffer to be considered for stack smashing protection" - msgstr "" - --#: params.def:691 -+#: params.def:692 - msgid "Maximum number of statements allowed in a block that needs to be duplicated when threading jumps" - msgstr "" - --#: params.def:700 -+#: params.def:701 - msgid "Maximum number of fields in a structure before pointer analysis treats the structure as a single variable" - msgstr "" - --#: params.def:705 -+#: params.def:706 - msgid "The maximum number of instructions ready to be issued to be considered by the scheduler during the first scheduling pass" - msgstr "" - --#: params.def:711 -+#: params.def:712 - msgid "Maximum number of active local stores in RTL dead store elimination" - msgstr "" - --#: params.def:721 -+#: params.def:722 - msgid "The number of insns executed before prefetch is completed" - msgstr "" - --#: params.def:728 -+#: params.def:729 - msgid "The number of prefetches that can run at the same time" - msgstr "" - --#: params.def:735 -+#: params.def:736 - msgid "The size of L1 cache" - msgstr "" - --#: params.def:742 -+#: params.def:743 - msgid "The size of L1 cache line" - msgstr "" - --#: params.def:749 -+#: params.def:750 - msgid "The size of L2 cache" - msgstr "" - --#: params.def:760 -+#: params.def:761 - msgid "Whether to use canonical types" - msgstr "" - --#: params.def:765 -+#: params.def:766 - msgid "Maximum length of partial antic set when performing tree pre optimization" - msgstr "" - --#: params.def:775 -+#: params.def:776 - msgid "Maximum size of a SCC before SCCVN stops processing a function" - msgstr "" - --#: params.def:780 -+#: params.def:781 - msgid "Max loops number for regional RA" - msgstr "" - --#: params.def:785 -+#: params.def:786 - msgid "Max size of conflict table in MB" - msgstr "" - --#: params.def:790 -+#: params.def:791 - msgid "The number of registers in each class kept unused by loop invariant motion" - msgstr "" - --#: params.def:798 -+#: params.def:799 - msgid "The maximum ratio between array size and switch branches for a switch conversion to take place" - msgstr "" - --#: params.def:806 -+#: params.def:807 - msgid "size of tiles for loop blocking" - msgstr "" - --#: params.def:813 -+#: params.def:814 - msgid "maximum number of parameters in a SCoP" - msgstr "" - --#: params.def:820 -+#: params.def:821 - msgid "maximum number of basic blocks per function to be analyzed by Graphite" - msgstr "" - --#: params.def:826 -+#: params.def:827 - msgid "Maximum number of datarefs in loop for building loop data dependencies" - msgstr "" - --#: params.def:833 -+#: params.def:834 - msgid "Max basic blocks number in loop for loop invariant motion" - msgstr "" - --#: params.def:839 -+#: params.def:840 - msgid "Maximum number of instructions in basic block to be considered for SLP vectorization" - msgstr "" - --#: params.def:844 -+#: params.def:845 - msgid "Min. ratio of insns to prefetches to enable prefetching for a loop with an unknown trip count" - msgstr "" - --#: params.def:850 -+#: params.def:851 - msgid "Min. ratio of insns to mem ops to enable prefetching in a loop" - msgstr "" - --#: params.def:857 -+#: params.def:858 - msgid "Max. size of var tracking hash tables" - msgstr "" - --#: params.def:865 -+#: params.def:866 - msgid "Max. recursion depth for expanding var tracking expressions" - msgstr "" - --#: params.def:872 -+#: params.def:873 - msgid "The minimum UID to be used for a nondebug insn" - msgstr "" - --#: params.def:877 -+#: params.def:878 - msgid "Maximum allowed growth of size of new parameters ipa-sra replaces a pointer to an aggregate with" - msgstr "" - --#: params.def:883 -+#: params.def:884 - msgid "Size in bytes after which thread-local aggregates should be instrumented with the logging functions instead of save/restore pairs" - msgstr "" - --#: params.def:890 -+#: params.def:891 - msgid "Maximum size of a list of values associated with each parameter for interprocedural constant propagation" - msgstr "" - --#: params.def:896 -+#: params.def:897 - msgid "Threshold ipa-cp opportunity evaluation that is still considered beneficial to clone." - msgstr "" - --#: params.def:904 -+#: params.def:905 - msgid "Number of partitions the program should be split to" - msgstr "" - --#: params.def:909 -+#: params.def:910 - msgid "Minimal size of a partition for LTO (in estimated instructions)" - msgstr "" - --#: params.def:916 -+#: params.def:917 - msgid "Maximum number of namespaces to search for alternatives when name lookup fails" - msgstr "" - --#: params.def:923 -+#: params.def:924 - msgid "Maximum number of conditional store pairs that can be sunk" - msgstr "" - --#: params.def:931 -+#: params.def:932 - msgid "The smallest number of different values for which it is best to use a jump-table instead of a tree of conditional branches, if 0, use the default for the machine" - msgstr "" - --#: params.def:939 -+#: params.def:940 - msgid "Allow new data races on loads to be introduced" - msgstr "" - --#: params.def:944 -+#: params.def:945 - msgid "Allow new data races on stores to be introduced" - msgstr "" - --#: params.def:949 -+#: params.def:950 - msgid "Allow new data races on packed data loads to be introduced" - msgstr "" - --#: params.def:954 -+#: params.def:955 - msgid "Allow new data races on packed data stores to be introduced" - msgstr "" - --#: params.def:960 -+#: params.def:961 - msgid "Set the maximum number of instructions executed in parallel in reassociated tree. If 0, use the target dependent heuristic." - msgstr "" - --#: params.def:966 -+#: params.def:967 - msgid "Maximum amount of similar bbs to compare a bb with" - msgstr "" - --#: params.def:971 -+#: params.def:972 - msgid "Maximum amount of iterations of the pass over a function" - msgstr "" - --#: params.def:978 -+#: params.def:979 - msgid "Maximum number of strings for which strlen optimization pass will track string lengths" - msgstr "" - -@@ -2589,18 +2589,18 @@ - msgstr "нерэчаіснае значэньне %%r" - - #: config/alpha/alpha.c:5103 config/ia64/ia64.c:5249 --#: config/rs6000/rs6000.c:15018 config/xtensa/xtensa.c:2350 -+#: config/rs6000/rs6000.c:15017 config/xtensa/xtensa.c:2350 - #, c-format - msgid "invalid %%R value" - msgstr "нерэчаіснае значэньне %%R" - --#: config/alpha/alpha.c:5109 config/rs6000/rs6000.c:14937 -+#: config/alpha/alpha.c:5109 config/rs6000/rs6000.c:14936 - #: config/xtensa/xtensa.c:2317 - #, c-format - msgid "invalid %%N value" - msgstr "нерэчаіснае значэньне %%N" - --#: config/alpha/alpha.c:5117 config/rs6000/rs6000.c:14965 -+#: config/alpha/alpha.c:5117 config/rs6000/rs6000.c:14964 - #, c-format - msgid "invalid %%P value" - msgstr "нерэчаіснае значэньне %%P" -@@ -2615,12 +2615,12 @@ - msgid "invalid %%L value" - msgstr "нерэчаіснае значэньне %%L" - --#: config/alpha/alpha.c:5172 config/rs6000/rs6000.c:14919 -+#: config/alpha/alpha.c:5172 config/rs6000/rs6000.c:14918 - #, c-format - msgid "invalid %%m value" - msgstr "нерэчаіснае значэньне %%m" - --#: config/alpha/alpha.c:5180 config/rs6000/rs6000.c:14927 -+#: config/alpha/alpha.c:5180 config/rs6000/rs6000.c:14926 - #, c-format - msgid "invalid %%M value" - msgstr "нерэчаіснае значэньне %%M" -@@ -2631,7 +2631,7 @@ - msgstr "нерэчаіснае значэньне %%U" - - #: config/alpha/alpha.c:5232 config/alpha/alpha.c:5243 --#: config/rs6000/rs6000.c:15026 -+#: config/rs6000/rs6000.c:15025 - #, c-format - msgid "invalid %%s value" - msgstr "нерэчаіснае значэньне %%v" -@@ -2641,7 +2641,7 @@ - msgid "invalid %%C value" - msgstr "нерэчаіснае значэньне %%C" - --#: config/alpha/alpha.c:5291 config/rs6000/rs6000.c:14784 -+#: config/alpha/alpha.c:5291 config/rs6000/rs6000.c:14783 - #, c-format - msgid "invalid %%E value" - msgstr "нерэчаіснае значэньне %%E" -@@ -2652,39 +2652,39 @@ - msgstr "" - - #: config/alpha/alpha.c:5325 config/cr16/cr16.c:1537 --#: config/rs6000/rs6000.c:15375 config/spu/spu.c:1744 -+#: config/rs6000/rs6000.c:15374 config/spu/spu.c:1744 - #, c-format - msgid "invalid %%xn code" - msgstr "нерэчаіснае значэньне %%xn" - --#: config/arm/arm.c:17116 config/arm/arm.c:17134 -+#: config/arm/arm.c:17120 config/arm/arm.c:17138 - #, fuzzy, c-format - msgid "predicated Thumb instruction" - msgstr "нявернае выкарыстанне \"restict\"" - --#: config/arm/arm.c:17122 -+#: config/arm/arm.c:17126 - #, c-format - msgid "predicated instruction in conditional sequence" - msgstr "" - --#: config/arm/arm.c:17253 -+#: config/arm/arm.c:17257 - #, fuzzy, c-format - msgid "Unsupported operand for code '%c'" - msgstr "Нерэчаісны выбар \"%s\"" - --#: config/arm/arm.c:17301 -+#: config/arm/arm.c:17305 - #, fuzzy, c-format - #| msgid "invalid %%f operand" - msgid "invalid shift operand" - msgstr "нерэчаісны %%f аперанд" - --#: config/arm/arm.c:17358 config/arm/arm.c:17380 config/arm/arm.c:17390 --#: config/arm/arm.c:17400 config/arm/arm.c:17410 config/arm/arm.c:17449 --#: config/arm/arm.c:17467 config/arm/arm.c:17502 config/arm/arm.c:17521 --#: config/arm/arm.c:17536 config/arm/arm.c:17563 config/arm/arm.c:17570 --#: config/arm/arm.c:17588 config/arm/arm.c:17595 config/arm/arm.c:17603 --#: config/arm/arm.c:17624 config/arm/arm.c:17631 config/arm/arm.c:17756 --#: config/arm/arm.c:17763 config/arm/arm.c:17786 config/arm/arm.c:17793 -+#: config/arm/arm.c:17362 config/arm/arm.c:17384 config/arm/arm.c:17394 -+#: config/arm/arm.c:17404 config/arm/arm.c:17414 config/arm/arm.c:17453 -+#: config/arm/arm.c:17471 config/arm/arm.c:17506 config/arm/arm.c:17525 -+#: config/arm/arm.c:17540 config/arm/arm.c:17567 config/arm/arm.c:17574 -+#: config/arm/arm.c:17592 config/arm/arm.c:17599 config/arm/arm.c:17607 -+#: config/arm/arm.c:17628 config/arm/arm.c:17635 config/arm/arm.c:17760 -+#: config/arm/arm.c:17767 config/arm/arm.c:17790 config/arm/arm.c:17797 - #: config/bfin/bfin.c:1436 config/bfin/bfin.c:1443 config/bfin/bfin.c:1450 - #: config/bfin/bfin.c:1457 config/bfin/bfin.c:1466 config/bfin/bfin.c:1473 - #: config/bfin/bfin.c:1480 config/bfin/bfin.c:1487 -@@ -2692,83 +2692,83 @@ - msgid "invalid operand for code '%c'" - msgstr "Нерэчаісны выбар \"%s\"" - --#: config/arm/arm.c:17462 -+#: config/arm/arm.c:17466 - #, c-format - msgid "instruction never executed" - msgstr "" - --#: config/arm/arm.c:17805 -+#: config/arm/arm.c:17809 - #, fuzzy, c-format - msgid "missing operand" - msgstr "прапушчан ініцыялізатар" - --#: config/arm/arm.c:20407 -+#: config/arm/arm.c:20411 - #, fuzzy - msgid "function parameters cannot have __fp16 type" - msgstr "віртуальныя функцыі не могуць быць сяброўскімі" - --#: config/arm/arm.c:20417 -+#: config/arm/arm.c:20421 - #, fuzzy - #| msgid "function does not return string type" - msgid "functions cannot return __fp16 type" - msgstr "функцыя не вяртае тып string" - --#: config/avr/avr.c:1806 -+#: config/avr/avr.c:1816 - #, c-format - msgid "address operand requires constraint for X, Y, or Z register" - msgstr "" - --#: config/avr/avr.c:1959 -+#: config/avr/avr.c:1969 - msgid "operands to %T/%t must be reg + const_int:" - msgstr "" - --#: config/avr/avr.c:1997 config/avr/avr.c:2052 -+#: config/avr/avr.c:2007 config/avr/avr.c:2062 - msgid "bad address, not an I/O address:" - msgstr "" - --#: config/avr/avr.c:2006 -+#: config/avr/avr.c:2016 - msgid "bad address, not a constant:" - msgstr "" - --#: config/avr/avr.c:2024 -+#: config/avr/avr.c:2034 - msgid "bad address, not (reg+disp):" - msgstr "" - --#: config/avr/avr.c:2031 -+#: config/avr/avr.c:2041 - msgid "bad address, not post_inc or pre_dec:" - msgstr "" - --#: config/avr/avr.c:2042 -+#: config/avr/avr.c:2052 - msgid "internal compiler error. Bad address:" - msgstr "" - --#: config/avr/avr.c:2072 -+#: config/avr/avr.c:2082 - msgid "internal compiler error. Unknown mode:" - msgstr "" - --#: config/avr/avr.c:2871 config/avr/avr.c:3444 config/avr/avr.c:3730 -+#: config/avr/avr.c:2881 config/avr/avr.c:3454 config/avr/avr.c:3740 - #, fuzzy - msgid "invalid insn:" - msgstr "Нерэчаісны выбар %s" - --#: config/avr/avr.c:2900 config/avr/avr.c:2975 config/avr/avr.c:3018 --#: config/avr/avr.c:3037 config/avr/avr.c:3128 config/avr/avr.c:3297 --#: config/avr/avr.c:3507 config/avr/avr.c:3623 config/avr/avr.c:3759 --#: config/avr/avr.c:3850 config/avr/avr.c:3972 -+#: config/avr/avr.c:2910 config/avr/avr.c:2985 config/avr/avr.c:3028 -+#: config/avr/avr.c:3047 config/avr/avr.c:3138 config/avr/avr.c:3307 -+#: config/avr/avr.c:3517 config/avr/avr.c:3633 config/avr/avr.c:3769 -+#: config/avr/avr.c:3860 config/avr/avr.c:3982 - msgid "incorrect insn:" - msgstr "" - --#: config/avr/avr.c:3052 config/avr/avr.c:3213 config/avr/avr.c:3368 --#: config/avr/avr.c:3576 config/avr/avr.c:3669 config/avr/avr.c:3906 --#: config/avr/avr.c:4027 -+#: config/avr/avr.c:3062 config/avr/avr.c:3223 config/avr/avr.c:3378 -+#: config/avr/avr.c:3586 config/avr/avr.c:3679 config/avr/avr.c:3916 -+#: config/avr/avr.c:4037 - msgid "unknown move insn:" - msgstr "" - --#: config/avr/avr.c:4441 -+#: config/avr/avr.c:4451 - msgid "bad shift insn:" - msgstr "" - --#: config/avr/avr.c:4549 config/avr/avr.c:5030 config/avr/avr.c:5445 -+#: config/avr/avr.c:4559 config/avr/avr.c:5040 config/avr/avr.c:5455 - msgid "internal compiler error. Incorrect shift:" - msgstr "" - -@@ -2785,7 +2785,7 @@ - - #: config/cris/cris.c:579 config/moxie/moxie.c:111 final.c:3129 final.c:3131 - #: fold-const.c:287 gcc.c:4609 gcc.c:4623 loop-iv.c:2968 loop-iv.c:2977 --#: rtl-error.c:103 toplev.c:346 tree-ssa-loop-niter.c:1917 tree-vrp.c:6046 -+#: rtl-error.c:103 toplev.c:346 tree-ssa-loop-niter.c:1917 tree-vrp.c:6018 - #: cp/typeck.c:5347 java/expr.c:390 lto/lto-object.c:184 lto/lto-object.c:282 - #: lto/lto-object.c:339 lto/lto-object.c:363 - #, gcc-internal-format, gfc-internal-format -@@ -3018,73 +3018,73 @@ - msgid "bad output_condmove_single operand" - msgstr "" - --#: config/i386/i386.c:13178 -+#: config/i386/i386.c:13272 - #, c-format - msgid "invalid UNSPEC as operand" - msgstr "" - --#: config/i386/i386.c:13801 -+#: config/i386/i386.c:13896 - #, c-format - msgid "'%%&' used without any local dynamic TLS references" - msgstr "" - --#: config/i386/i386.c:13892 config/i386/i386.c:13967 -+#: config/i386/i386.c:13994 config/i386/i386.c:14069 - #, fuzzy, c-format - msgid "invalid operand size for operand code '%c'" - msgstr "Нерэчаісны выбар \"%s\"" - --#: config/i386/i386.c:13962 -+#: config/i386/i386.c:14064 - #, fuzzy, c-format - msgid "invalid operand type used with operand code '%c'" - msgstr "Нерэчаісны выбар \"%s\"" - --#: config/i386/i386.c:14043 config/i386/i386.c:14083 -+#: config/i386/i386.c:14145 config/i386/i386.c:14185 - #, c-format - msgid "operand is not a condition code, invalid operand code 'D'" - msgstr "" - --#: config/i386/i386.c:14109 -+#: config/i386/i386.c:14211 - #, c-format - msgid "operand is neither a constant nor a condition code, invalid operand code 'C'" - msgstr "" - --#: config/i386/i386.c:14119 -+#: config/i386/i386.c:14221 - #, c-format - msgid "operand is neither a constant nor a condition code, invalid operand code 'F'" - msgstr "" - --#: config/i386/i386.c:14137 -+#: config/i386/i386.c:14239 - #, c-format - msgid "operand is neither a constant nor a condition code, invalid operand code 'c'" - msgstr "" - --#: config/i386/i386.c:14147 -+#: config/i386/i386.c:14249 - #, c-format - msgid "operand is neither a constant nor a condition code, invalid operand code 'f'" - msgstr "" - --#: config/i386/i386.c:14162 -+#: config/i386/i386.c:14264 - #, c-format - msgid "operand is not an offsettable memory reference, invalid operand code 'H'" - msgstr "" - --#: config/i386/i386.c:14257 -+#: config/i386/i386.c:14359 - #, c-format - msgid "operand is not a condition code, invalid operand code 'Y'" - msgstr "" - --#: config/i386/i386.c:14287 -+#: config/i386/i386.c:14389 - #, fuzzy, c-format - msgid "invalid operand code '%c'" - msgstr "Нерэчаісны выбар \"%s\"" - --#: config/i386/i386.c:14342 -+#: config/i386/i386.c:14444 - #, fuzzy, c-format - #| msgid "invalid %%c operand" - msgid "invalid constraints for operand" - msgstr "нерэчаісны %%c аперанд" - --#: config/i386/i386.c:23356 -+#: config/i386/i386.c:23485 - #, fuzzy - msgid "unknown insn mode" - msgstr "невядомы рэжым машыны \"%s\"" -@@ -3141,13 +3141,13 @@ - msgid "invalid operation on %<__fpreg%>" - msgstr "нерэчаісны %%-код" - --#: config/iq2000/iq2000.c:3130 config/tilegx/tilegx.c:5131 -+#: config/iq2000/iq2000.c:3130 config/tilegx/tilegx.c:5133 - #: config/tilepro/tilepro.c:4696 - #, fuzzy, c-format - msgid "invalid %%P operand" - msgstr "нерэчаісны %%-код" - --#: config/iq2000/iq2000.c:3138 config/rs6000/rs6000.c:14955 -+#: config/iq2000/iq2000.c:3138 config/rs6000/rs6000.c:14954 - #, c-format - msgid "invalid %%p value" - msgstr "" -@@ -3228,7 +3228,7 @@ - msgstr "" - - #: config/m32r/m32r.c:2321 config/m32r/m32r.c:2335 --#: config/rs6000/rs6000.c:24534 -+#: config/rs6000/rs6000.c:24557 - msgid "bad address" - msgstr "дрэнны адрас" - -@@ -3369,119 +3369,119 @@ - msgid "Try running '%s' in the shell to raise its limit.\n" - msgstr "" - --#: config/rs6000/rs6000.c:2758 -+#: config/rs6000/rs6000.c:2757 - #, fuzzy - #| msgid "Use hardware floating point" - msgid "-mvsx requires hardware floating point" - msgstr "Выкарыстоўваць апаратную \"плаваючую кропку\"" - --#: config/rs6000/rs6000.c:2763 -+#: config/rs6000/rs6000.c:2762 - msgid "-mvsx and -mpaired are incompatible" - msgstr "" - --#: config/rs6000/rs6000.c:2768 -+#: config/rs6000/rs6000.c:2767 - msgid "-mvsx used with little endian code" - msgstr "" - --#: config/rs6000/rs6000.c:2770 -+#: config/rs6000/rs6000.c:2769 - msgid "-mvsx needs indexed addressing" - msgstr "" - --#: config/rs6000/rs6000.c:2774 -+#: config/rs6000/rs6000.c:2773 - msgid "-mvsx and -mno-altivec are incompatible" - msgstr "" - --#: config/rs6000/rs6000.c:2776 -+#: config/rs6000/rs6000.c:2775 - msgid "-mno-altivec disables vsx" - msgstr "" - --#: config/rs6000/rs6000.c:7324 -+#: config/rs6000/rs6000.c:7323 - msgid "bad move" - msgstr "" - --#: config/rs6000/rs6000.c:14765 -+#: config/rs6000/rs6000.c:14764 - #, fuzzy, c-format - #| msgid "invalid %%Q value" - msgid "invalid %%c value" - msgstr "дрэннае %%Q значэнне" - --#: config/rs6000/rs6000.c:14793 -+#: config/rs6000/rs6000.c:14792 - #, c-format - msgid "invalid %%f value" - msgstr "" - --#: config/rs6000/rs6000.c:14802 -+#: config/rs6000/rs6000.c:14801 - #, c-format - msgid "invalid %%F value" - msgstr "" - --#: config/rs6000/rs6000.c:14811 -+#: config/rs6000/rs6000.c:14810 - #, c-format - msgid "invalid %%G value" - msgstr "" - --#: config/rs6000/rs6000.c:14846 -+#: config/rs6000/rs6000.c:14845 - #, c-format - msgid "invalid %%j code" - msgstr "" - --#: config/rs6000/rs6000.c:14856 -+#: config/rs6000/rs6000.c:14855 - #, c-format - msgid "invalid %%J code" - msgstr "" - --#: config/rs6000/rs6000.c:14866 -+#: config/rs6000/rs6000.c:14865 - #, c-format - msgid "invalid %%k value" - msgstr "" - --#: config/rs6000/rs6000.c:14881 config/xtensa/xtensa.c:2336 -+#: config/rs6000/rs6000.c:14880 config/xtensa/xtensa.c:2336 - #, c-format - msgid "invalid %%K value" - msgstr "" - --#: config/rs6000/rs6000.c:14945 -+#: config/rs6000/rs6000.c:14944 - #, c-format - msgid "invalid %%O value" - msgstr "нерэчаіснае значэньне %%O" - --#: config/rs6000/rs6000.c:14992 -+#: config/rs6000/rs6000.c:14991 - #, c-format - msgid "invalid %%q value" - msgstr "" - --#: config/rs6000/rs6000.c:15036 -+#: config/rs6000/rs6000.c:15035 - #, c-format - msgid "invalid %%S value" - msgstr "" - --#: config/rs6000/rs6000.c:15076 -+#: config/rs6000/rs6000.c:15075 - #, c-format - msgid "invalid %%T value" - msgstr "" - --#: config/rs6000/rs6000.c:15086 -+#: config/rs6000/rs6000.c:15085 - #, c-format - msgid "invalid %%u value" - msgstr "" - --#: config/rs6000/rs6000.c:15095 config/xtensa/xtensa.c:2306 -+#: config/rs6000/rs6000.c:15094 config/xtensa/xtensa.c:2306 - #, c-format - msgid "invalid %%v value" - msgstr "" - --#: config/rs6000/rs6000.c:15177 config/xtensa/xtensa.c:2357 -+#: config/rs6000/rs6000.c:15176 config/xtensa/xtensa.c:2357 - #, fuzzy, c-format - #| msgid "invalid %%x/X value" - msgid "invalid %%x value" - msgstr "нерэчаіснае значэньне %%x/X" - --#: config/rs6000/rs6000.c:15323 -+#: config/rs6000/rs6000.c:15322 - #, fuzzy, c-format - msgid "invalid %%y value, try using the 'Z' constraint" - msgstr "нявернае выкарыстанне \"restict\"" - --#: config/rs6000/rs6000.c:26944 -+#: config/rs6000/rs6000.c:26967 - #, fuzzy - #| msgid "too few arguments to function" - msgid "AltiVec argument passed to unprototyped function" -@@ -3572,25 +3572,25 @@ - msgid "invalid operand for code: '%c'" - msgstr "Нерэчаісны выбар \"%s\"" - --#: config/sh/sh.c:1031 -+#: config/sh/sh.c:1024 - #, fuzzy, c-format - msgid "invalid operand to %%R" - msgstr "нерэчаісны %%-код" - --#: config/sh/sh.c:1058 -+#: config/sh/sh.c:1051 - #, fuzzy, c-format - msgid "invalid operand to %%S" - msgstr "нерэчаісны %%-код" - --#: config/sh/sh.c:9154 -+#: config/sh/sh.c:9157 - msgid "created and used with different architectures / ABIs" - msgstr "" - --#: config/sh/sh.c:9156 -+#: config/sh/sh.c:9159 - msgid "created and used with different ABIs" - msgstr "" - --#: config/sh/sh.c:9158 -+#: config/sh/sh.c:9161 - msgid "created and used with different endianness" - msgstr "" - -@@ -3609,13 +3609,13 @@ - msgid "invalid %%B operand" - msgstr "нерэчаісны %%B аперанд" - --#: config/sparc/sparc.c:8247 config/tilegx/tilegx.c:4934 -+#: config/sparc/sparc.c:8247 config/tilegx/tilegx.c:4936 - #: config/tilepro/tilepro.c:4499 - #, c-format - msgid "invalid %%C operand" - msgstr "нерэчаісны %%C аперанд" - --#: config/sparc/sparc.c:8264 config/tilegx/tilegx.c:4967 -+#: config/sparc/sparc.c:8264 config/tilegx/tilegx.c:4969 - #, c-format - msgid "invalid %%D operand" - msgstr "нерэчаісны %%D аперанд" -@@ -3660,58 +3660,58 @@ - msgid "xstormy16_print_operand: unknown code" - msgstr "" - --#: config/tilegx/tilegx.c:4919 config/tilepro/tilepro.c:4484 -+#: config/tilegx/tilegx.c:4921 config/tilepro/tilepro.c:4484 - #, c-format - msgid "invalid %%c operand" - msgstr "нерэчаісны %%c аперанд" - --#: config/tilegx/tilegx.c:4950 -+#: config/tilegx/tilegx.c:4952 - #, c-format - msgid "invalid %%d operand" - msgstr "нерэчаісны %%d аперанд" - --#: config/tilegx/tilegx.c:5033 -+#: config/tilegx/tilegx.c:5035 - #, fuzzy, c-format - msgid "invalid %%H specifier" - msgstr "нерэчаісны %%-код" - --#: config/tilegx/tilegx.c:5069 config/tilepro/tilepro.c:4513 -+#: config/tilegx/tilegx.c:5071 config/tilepro/tilepro.c:4513 - #, fuzzy, c-format - msgid "invalid %%h operand" - msgstr "нерэчаісны %%-код" - --#: config/tilegx/tilegx.c:5081 config/tilepro/tilepro.c:4577 -+#: config/tilegx/tilegx.c:5083 config/tilepro/tilepro.c:4577 - #, fuzzy, c-format - msgid "invalid %%I operand" - msgstr "нерэчаісны %%-код" - --#: config/tilegx/tilegx.c:5095 config/tilepro/tilepro.c:4591 -+#: config/tilegx/tilegx.c:5097 config/tilepro/tilepro.c:4591 - #, fuzzy, c-format - msgid "invalid %%i operand" - msgstr "нерэчаісны %%-код" - --#: config/tilegx/tilegx.c:5118 config/tilepro/tilepro.c:4614 -+#: config/tilegx/tilegx.c:5120 config/tilepro/tilepro.c:4614 - #, fuzzy, c-format - msgid "invalid %%j operand" - msgstr "нерэчаісны %%-код" - --#: config/tilegx/tilegx.c:5149 -+#: config/tilegx/tilegx.c:5151 - #, fuzzy, c-format - #| msgid "invalid %%c operand" - msgid "invalid %%%c operand" - msgstr "нерэчаісны %%c аперанд" - --#: config/tilegx/tilegx.c:5164 config/tilepro/tilepro.c:4728 -+#: config/tilegx/tilegx.c:5166 config/tilepro/tilepro.c:4728 - #, fuzzy, c-format - msgid "invalid %%N operand" - msgstr "нерэчаісны %%-код" - --#: config/tilegx/tilegx.c:5208 -+#: config/tilegx/tilegx.c:5210 - #, fuzzy, c-format - msgid "invalid operand for 'r' specifier" - msgstr "нерэчаісны %%-код" - --#: config/tilegx/tilegx.c:5233 config/tilepro/tilepro.c:4810 -+#: config/tilegx/tilegx.c:5235 config/tilepro/tilepro.c:4810 - #, c-format - msgid "unable to print out operand yet; code == %d (%c)" - msgstr "" -@@ -4049,7 +4049,7 @@ - msgid "candidates are:" - msgstr "" - --#: cp/pt.c:17843 cp/call.c:3289 -+#: cp/pt.c:17869 cp/call.c:3289 - #, gcc-internal-format - msgid "candidate is:" - msgid_plural "candidates are:" -@@ -4434,11 +4434,11 @@ - msgid "implied END DO" - msgstr "" - --#: fortran/parse.c:1475 fortran/resolve.c:9395 -+#: fortran/parse.c:1475 fortran/resolve.c:9397 - msgid "assignment" - msgstr "" - --#: fortran/parse.c:1478 fortran/resolve.c:9434 fortran/resolve.c:9437 -+#: fortran/parse.c:1478 fortran/resolve.c:9436 fortran/resolve.c:9439 - msgid "pointer assignment" - msgstr "" - -@@ -4446,125 +4446,125 @@ - msgid "simple IF" - msgstr "" - --#: fortran/resolve.c:533 -+#: fortran/resolve.c:535 - msgid "module procedure" - msgstr "" - --#: fortran/resolve.c:534 -+#: fortran/resolve.c:536 - #, fuzzy - #| msgid "In function" - msgid "internal function" - msgstr "У функцыі" - --#: fortran/resolve.c:1973 -+#: fortran/resolve.c:1975 - msgid "elemental procedure" - msgstr "" - --#: fortran/resolve.c:3798 -+#: fortran/resolve.c:3800 - #, c-format - msgid "Invalid context for NULL() pointer at %%L" - msgstr "" - --#: fortran/resolve.c:3814 -+#: fortran/resolve.c:3816 - #, c-format - msgid "Operand of unary numeric operator '%s' at %%L is %s" - msgstr "" - --#: fortran/resolve.c:3830 -+#: fortran/resolve.c:3832 - #, c-format - msgid "Operands of binary numeric operator '%s' at %%L are %s/%s" - msgstr "" - --#: fortran/resolve.c:3845 -+#: fortran/resolve.c:3847 - #, c-format - msgid "Operands of string concatenation operator at %%L are %s/%s" - msgstr "" - --#: fortran/resolve.c:3864 -+#: fortran/resolve.c:3866 - #, c-format - msgid "Operands of logical operator '%s' at %%L are %s/%s" - msgstr "" - --#: fortran/resolve.c:3878 -+#: fortran/resolve.c:3880 - #, c-format - msgid "Operand of .not. operator at %%L is %s" - msgstr "" - --#: fortran/resolve.c:3892 -+#: fortran/resolve.c:3894 - msgid "COMPLEX quantities cannot be compared at %L" - msgstr "" - --#: fortran/resolve.c:3921 -+#: fortran/resolve.c:3923 - #, c-format - msgid "Logicals at %%L must be compared with %s instead of %s" - msgstr "" - --#: fortran/resolve.c:3927 -+#: fortran/resolve.c:3929 - #, c-format - msgid "Operands of comparison operator '%s' at %%L are %s/%s" - msgstr "" - --#: fortran/resolve.c:3935 -+#: fortran/resolve.c:3937 - #, c-format - msgid "Unknown operator '%s' at %%L" - msgstr "" - --#: fortran/resolve.c:3937 -+#: fortran/resolve.c:3939 - #, c-format - msgid "Operand of user operator '%s' at %%L is %s" - msgstr "" - --#: fortran/resolve.c:3941 -+#: fortran/resolve.c:3943 - #, c-format - msgid "Operands of user operator '%s' at %%L are %s/%s" - msgstr "" - --#: fortran/resolve.c:4029 -+#: fortran/resolve.c:4031 - #, c-format - msgid "Inconsistent ranks for operator at %%L and %%L" - msgstr "" - --#: fortran/resolve.c:6401 -+#: fortran/resolve.c:6403 - msgid "Loop variable" - msgstr "" - --#: fortran/resolve.c:6405 -+#: fortran/resolve.c:6407 - msgid "iterator variable" - msgstr "" - --#: fortran/resolve.c:6410 -+#: fortran/resolve.c:6412 - msgid "Start expression in DO loop" - msgstr "" - --#: fortran/resolve.c:6414 -+#: fortran/resolve.c:6416 - msgid "End expression in DO loop" - msgstr "" - --#: fortran/resolve.c:6418 -+#: fortran/resolve.c:6420 - msgid "Step expression in DO loop" - msgstr "" - --#: fortran/resolve.c:6674 fortran/resolve.c:6677 -+#: fortran/resolve.c:6676 fortran/resolve.c:6679 - msgid "DEALLOCATE object" - msgstr "" - --#: fortran/resolve.c:7019 fortran/resolve.c:7021 -+#: fortran/resolve.c:7021 fortran/resolve.c:7023 - msgid "ALLOCATE object" - msgstr "" - --#: fortran/resolve.c:7201 fortran/resolve.c:8434 -+#: fortran/resolve.c:7203 fortran/resolve.c:8436 - msgid "STAT variable" - msgstr "" - --#: fortran/resolve.c:7244 fortran/resolve.c:8446 -+#: fortran/resolve.c:7246 fortran/resolve.c:8448 - msgid "ERRMSG variable" - msgstr "" - --#: fortran/resolve.c:8312 -+#: fortran/resolve.c:8314 - msgid "item in READ" - msgstr "" - --#: fortran/resolve.c:8458 -+#: fortran/resolve.c:8460 - msgid "ACQUIRED_LOCK variable" - msgstr "" - -@@ -4573,7 +4573,7 @@ - msgid "Different CHARACTER lengths (%ld/%ld) in array constructor" - msgstr "" - --#: fortran/trans-array.c:5070 -+#: fortran/trans-array.c:5064 - msgid "Integer overflow when calculating the amount of memory to allocate" - msgstr "" - -@@ -4898,6 +4898,18 @@ - msgid "cannot use mshared and static together" - msgstr "" - -+#: java/lang-specs.h:33 -+msgid "-fjni and -femit-class-files are incompatible" -+msgstr "" -+ -+#: java/lang-specs.h:34 -+msgid "-fjni and -femit-class-file are incompatible" -+msgstr "" -+ -+#: java/lang-specs.h:35 java/lang-specs.h:36 -+msgid "-femit-class-file should used along with -fsyntax-only" -+msgstr "" -+ - #: config/i386/mingw-w64.h:83 config/i386/mingw32.h:116 - #: config/i386/cygwin.h:114 - msgid "shared and mdll are not compatible" -@@ -4991,26 +5003,10 @@ - msgid "objc-cpp-output is deprecated; please use objective-c-cpp-output instead" - msgstr "" - --#: config/vax/netbsd-elf.h:51 --msgid "the -shared option is not currently supported for VAX ELF" --msgstr "" -- - #: fortran/lang-specs.h:55 fortran/lang-specs.h:69 - msgid "gfortran does not support -E without -cpp" - msgstr "" - --#: java/lang-specs.h:33 --msgid "-fjni and -femit-class-files are incompatible" --msgstr "" -- --#: java/lang-specs.h:34 --msgid "-fjni and -femit-class-file are incompatible" --msgstr "" -- --#: java/lang-specs.h:35 java/lang-specs.h:36 --msgid "-femit-class-file should used along with -fsyntax-only" --msgstr "" -- - #: config/sh/sh.h:430 config/sh/sh.h:433 - #, fuzzy - #| msgid "%s does not support %s" -@@ -5025,6 +5021,10 @@ - msgid "objc++-cpp-output is deprecated; please use objective-c++-cpp-output instead" - msgstr "" - -+#: config/vax/netbsd-elf.h:51 -+msgid "the -shared option is not currently supported for VAX ELF" -+msgstr "" -+ - #: config/vax/vax.h:50 config/vax/vax.h:51 - #, fuzzy - msgid "profiling not supported with -mg" -@@ -7841,7 +7841,7 @@ - msgstr "" - - #: config/sh/sh.opt:274 --msgid "Increase the IEEE compliance for floating-point code" -+msgid "Increase the IEEE compliance for floating-point comparisons" - msgstr "" - - #: config/sh/sh.opt:278 -@@ -12247,256 +12247,252 @@ - msgid "Create a position independent executable" - msgstr "" - --#: go/gofrontend/expressions.cc:853 -+#: go/gofrontend/expressions.cc:855 - #, fuzzy - #| msgid "invalid use of `%D'" - msgid "invalid use of type" - msgstr "нерэчаіснае выкарыстаньне `%D'" - --#: go/gofrontend/expressions.cc:2533 go/gofrontend/expressions.cc:2599 --#: go/gofrontend/expressions.cc:2615 -+#: go/gofrontend/expressions.cc:2535 go/gofrontend/expressions.cc:2601 -+#: go/gofrontend/expressions.cc:2617 - msgid "constant refers to itself" - msgstr "" - --#: go/gofrontend/expressions.cc:3900 -+#: go/gofrontend/expressions.cc:3902 - msgid "expected numeric type" - msgstr "" - --#: go/gofrontend/expressions.cc:3905 -+#: go/gofrontend/expressions.cc:3907 - msgid "expected boolean type" - msgstr "" - --#: go/gofrontend/expressions.cc:3911 -+#: go/gofrontend/expressions.cc:3913 - msgid "expected integer or boolean type" - msgstr "" - --#: go/gofrontend/expressions.cc:3918 -+#: go/gofrontend/expressions.cc:3920 - #, fuzzy - msgid "invalid operand for unary %<&%>" - msgstr "нерэчаісны %%-код" - --#: go/gofrontend/expressions.cc:3927 -+#: go/gofrontend/expressions.cc:3929 - msgid "expected pointer" - msgstr "" - --#: go/gofrontend/expressions.cc:5588 go/gofrontend/expressions.cc:5606 -+#: go/gofrontend/expressions.cc:5599 go/gofrontend/expressions.cc:5617 - msgid "incompatible types in binary expression" - msgstr "" - --#: go/gofrontend/expressions.cc:5620 -+#: go/gofrontend/expressions.cc:5631 - #, fuzzy - msgid "shift of non-integer operand" - msgstr "памер масіва \"%s\" адмоўны" - --#: go/gofrontend/expressions.cc:5625 go/gofrontend/expressions.cc:5633 -+#: go/gofrontend/expressions.cc:5636 go/gofrontend/expressions.cc:5644 - msgid "shift count not unsigned integer" - msgstr "" - --#: go/gofrontend/expressions.cc:5638 -+#: go/gofrontend/expressions.cc:5649 - msgid "negative shift count" - msgstr "" - --#: go/gofrontend/expressions.cc:6431 -+#: go/gofrontend/expressions.cc:6448 - #, fuzzy - #| msgid "cannot find method" - msgid "object is not a method" - msgstr "немагчыма знайсьці мэтад" - --#: go/gofrontend/expressions.cc:6440 -+#: go/gofrontend/expressions.cc:6457 - msgid "method type does not match object type" - msgstr "" - --#: go/gofrontend/expressions.cc:6714 -+#: go/gofrontend/expressions.cc:6731 - msgid "invalid use of %<...%> with builtin function" - msgstr "" - --#: go/gofrontend/expressions.cc:6748 go/gofrontend/expressions.cc:6805 --#: go/gofrontend/expressions.cc:6850 go/gofrontend/expressions.cc:7539 --#: go/gofrontend/expressions.cc:7686 go/gofrontend/expressions.cc:7729 --#: go/gofrontend/expressions.cc:7785 go/gofrontend/expressions.cc:8967 --#: go/gofrontend/expressions.cc:8986 -+#: go/gofrontend/expressions.cc:6765 go/gofrontend/expressions.cc:6822 -+#: go/gofrontend/expressions.cc:6867 go/gofrontend/expressions.cc:7556 -+#: go/gofrontend/expressions.cc:7703 go/gofrontend/expressions.cc:7746 -+#: go/gofrontend/expressions.cc:7802 go/gofrontend/expressions.cc:8984 -+#: go/gofrontend/expressions.cc:9003 - #, fuzzy - #| msgid "no arguments" - msgid "not enough arguments" - msgstr "няма аргументаў" - --#: go/gofrontend/expressions.cc:6750 go/gofrontend/expressions.cc:6807 --#: go/gofrontend/expressions.cc:7544 go/gofrontend/expressions.cc:7669 --#: go/gofrontend/expressions.cc:7691 go/gofrontend/expressions.cc:7734 --#: go/gofrontend/expressions.cc:7787 go/gofrontend/expressions.cc:8662 --#: go/gofrontend/expressions.cc:8972 go/gofrontend/expressions.cc:8993 -+#: go/gofrontend/expressions.cc:6767 go/gofrontend/expressions.cc:6824 -+#: go/gofrontend/expressions.cc:7561 go/gofrontend/expressions.cc:7686 -+#: go/gofrontend/expressions.cc:7708 go/gofrontend/expressions.cc:7751 -+#: go/gofrontend/expressions.cc:7804 go/gofrontend/expressions.cc:8679 -+#: go/gofrontend/expressions.cc:8989 go/gofrontend/expressions.cc:9010 - #, fuzzy - #| msgid "too many arguments to function" - msgid "too many arguments" - msgstr "вельмі шмат аргументаў у функцыі" - --#: go/gofrontend/expressions.cc:6809 -+#: go/gofrontend/expressions.cc:6826 - #, fuzzy - msgid "argument 1 must be a map" - msgstr "першым аргументам \"%s\" павінен быць \"int\"" - --#: go/gofrontend/expressions.cc:6876 -+#: go/gofrontend/expressions.cc:6893 - #, fuzzy - msgid "invalid type for make function" - msgstr "Нерэчаісны выбар \"%s\"" - --#: go/gofrontend/expressions.cc:6890 -+#: go/gofrontend/expressions.cc:6907 - msgid "length required when allocating a slice" - msgstr "" - --#: go/gofrontend/expressions.cc:6904 -+#: go/gofrontend/expressions.cc:6921 - msgid "bad size for make" - msgstr "" - --#: go/gofrontend/expressions.cc:6919 -+#: go/gofrontend/expressions.cc:6936 - msgid "bad capacity when making slice" - msgstr "" - --#: go/gofrontend/expressions.cc:6930 -+#: go/gofrontend/expressions.cc:6947 - #, fuzzy - #| msgid "too many arguments to function" - msgid "too many arguments to make" - msgstr "вельмі шмат аргументаў у функцыі" - --#: go/gofrontend/expressions.cc:7588 -+#: go/gofrontend/expressions.cc:7605 - #, fuzzy - msgid "argument must be array or slice or channel" - msgstr "першым аргументам \"%s\" павінен быць \"int\"" - --#: go/gofrontend/expressions.cc:7598 -+#: go/gofrontend/expressions.cc:7615 - msgid "argument must be string or array or slice or map or channel" - msgstr "" - --#: go/gofrontend/expressions.cc:7644 -+#: go/gofrontend/expressions.cc:7661 - #, fuzzy - #| msgid "too few arguments to function" - msgid "unsupported argument type to builtin function" - msgstr "не хапае аргументаў у функцыі" - --#: go/gofrontend/expressions.cc:7655 -+#: go/gofrontend/expressions.cc:7672 - #, fuzzy - msgid "argument must be channel" - msgstr "першым аргументам \"%s\" павінен быць \"int\"" - --#: go/gofrontend/expressions.cc:7657 -+#: go/gofrontend/expressions.cc:7674 - msgid "cannot close receive-only channel" - msgstr "" - --#: go/gofrontend/expressions.cc:7677 -+#: go/gofrontend/expressions.cc:7694 - #, fuzzy - msgid "argument must be a field reference" - msgstr "першым аргументам \"%s\" павінен быць \"int\"" - --#: go/gofrontend/expressions.cc:7704 -+#: go/gofrontend/expressions.cc:7721 - #, fuzzy - msgid "left argument must be a slice" - msgstr "першым аргументам \"%s\" павінен быць \"int\"" - --#: go/gofrontend/expressions.cc:7712 -+#: go/gofrontend/expressions.cc:7729 - msgid "element types must be the same" - msgstr "" - --#: go/gofrontend/expressions.cc:7717 -+#: go/gofrontend/expressions.cc:7734 - #, fuzzy - #| msgid "first argument of `%s' should be `int'" - msgid "first argument must be []byte" - msgstr "першым аргументам \"%s\" павінен быць \"int\"" - --#: go/gofrontend/expressions.cc:7720 -+#: go/gofrontend/expressions.cc:7737 - msgid "second argument must be slice or string" - msgstr "" - --#: go/gofrontend/expressions.cc:7761 -+#: go/gofrontend/expressions.cc:7778 - #, fuzzy - #| msgid "bit-field `%s' has invalid type" - msgid "argument 2 has invalid type" - msgstr "бітавае поле \"%s\" мае нерэчаісны тып" - --#: go/gofrontend/expressions.cc:7777 -+#: go/gofrontend/expressions.cc:7794 - #, fuzzy - msgid "argument must have complex type" - msgstr "\"%s\" мае незавершаны тып" - --#: go/gofrontend/expressions.cc:7795 -+#: go/gofrontend/expressions.cc:7812 - msgid "complex arguments must have identical types" - msgstr "" - --#: go/gofrontend/expressions.cc:7797 -+#: go/gofrontend/expressions.cc:7814 - msgid "complex arguments must have floating-point type" - msgstr "" - --#: go/gofrontend/expressions.cc:8666 -+#: go/gofrontend/expressions.cc:8683 - #, fuzzy - msgid "invalid use of %<...%> with non-slice" - msgstr "нявернае выкарыстанне \"restict\"" - --#: go/gofrontend/expressions.cc:8920 go/gofrontend/expressions.cc:9361 -+#: go/gofrontend/expressions.cc:8937 go/gofrontend/expressions.cc:9378 - #, fuzzy - #| msgid "In function" - msgid "expected function" - msgstr "У функцыі" - --#: go/gofrontend/expressions.cc:8939 -+#: go/gofrontend/expressions.cc:8956 - msgid "incompatible type for receiver" - msgstr "" - --#: go/gofrontend/expressions.cc:8957 -+#: go/gofrontend/expressions.cc:8974 - msgid "invalid use of %<...%> calling non-variadic function" - msgstr "" - --#: go/gofrontend/expressions.cc:9370 go/gofrontend/expressions.cc:9384 -+#: go/gofrontend/expressions.cc:9387 go/gofrontend/expressions.cc:9401 - msgid "number of results does not match number of values" - msgstr "" - --#: go/gofrontend/expressions.cc:9688 go/gofrontend/expressions.cc:10110 -+#: go/gofrontend/expressions.cc:9705 go/gofrontend/expressions.cc:10127 - msgid "index must be integer" - msgstr "" - --#: go/gofrontend/expressions.cc:9694 go/gofrontend/expressions.cc:10114 -+#: go/gofrontend/expressions.cc:9711 go/gofrontend/expressions.cc:10131 - msgid "slice end must be integer" - msgstr "" - --#: go/gofrontend/expressions.cc:9751 -+#: go/gofrontend/expressions.cc:9768 - msgid "slice of unaddressable value" - msgstr "" - --#: go/gofrontend/expressions.cc:10344 -+#: go/gofrontend/expressions.cc:10361 - msgid "incompatible type for map index" - msgstr "" - --#: go/gofrontend/expressions.cc:10692 -+#: go/gofrontend/expressions.cc:10709 - msgid "expected interface or pointer to interface" - msgstr "" - --#: go/gofrontend/expressions.cc:11260 -+#: go/gofrontend/expressions.cc:11277 - #, fuzzy - #| msgid "too many arguments to function" - msgid "too many expressions for struct" - msgstr "вельмі шмат аргументаў у функцыі" - --#: go/gofrontend/expressions.cc:11273 -+#: go/gofrontend/expressions.cc:11290 - #, fuzzy - #| msgid "too few arguments to function" - msgid "too few expressions for struct" - msgstr "не хапае аргументаў у функцыі" - --#: go/gofrontend/expressions.cc:12933 go/gofrontend/expressions.cc:12941 --msgid "invalid unsafe.Pointer conversion" --msgstr "" -- --#: go/gofrontend/expressions.cc:12946 go/gofrontend/statements.cc:1539 -+#: go/gofrontend/expressions.cc:12945 go/gofrontend/statements.cc:1539 - msgid "type assertion only valid for interface types" - msgstr "" - --#: go/gofrontend/expressions.cc:12958 -+#: go/gofrontend/expressions.cc:12957 - msgid "impossible type assertion: type does not implement interface" - msgstr "" - --#: go/gofrontend/expressions.cc:13142 go/gofrontend/statements.cc:1387 -+#: go/gofrontend/expressions.cc:13128 go/gofrontend/statements.cc:1387 - msgid "expected channel" - msgstr "" - --#: go/gofrontend/expressions.cc:13147 go/gofrontend/statements.cc:1392 -+#: go/gofrontend/expressions.cc:13133 go/gofrontend/statements.cc:1392 - msgid "invalid receive on send-only channel" - msgstr "" - -@@ -12534,19 +12530,23 @@ - msgid "expected boolean expression" - msgstr "" - --#: go/gofrontend/statements.cc:4334 -+#: go/gofrontend/statements.cc:4198 -+msgid "cannot type switch on non-interface value" -+msgstr "" -+ -+#: go/gofrontend/statements.cc:4320 - msgid "incompatible types in send" - msgstr "" - --#: go/gofrontend/statements.cc:4339 -+#: go/gofrontend/statements.cc:4325 - msgid "invalid send on receive-only channel" - msgstr "" - --#: go/gofrontend/statements.cc:5226 -+#: go/gofrontend/statements.cc:5212 - msgid "too many variables for range clause with channel" - msgstr "" - --#: go/gofrontend/statements.cc:5233 -+#: go/gofrontend/statements.cc:5219 - msgid "range clause must have array, slice, string, map, or channel type" - msgstr "" - -@@ -12842,7 +12842,7 @@ - - #. All valid uses of __builtin_va_arg_pack () are removed during - #. inlining. --#: builtins.c:6023 expr.c:9964 -+#: builtins.c:6023 expr.c:9965 - #, gcc-internal-format - msgid "%Kinvalid use of %<__builtin_va_arg_pack ()%>" - msgstr "" -@@ -12942,13 +12942,13 @@ - #. an unprototyped function, it is compile-time undefined; - #. making it a constraint in that case was rejected in - #. DR#252. --#: c-convert.c:101 c-typeck.c:1992 c-typeck.c:5332 c-typeck.c:10590 -+#: c-convert.c:103 c-typeck.c:1992 c-typeck.c:5332 c-typeck.c:10596 - #: cp/typeck.c:1849 cp/typeck.c:6722 cp/typeck.c:7420 fortran/convert.c:88 - #, gcc-internal-format - msgid "void value not ignored as it ought to be" - msgstr "" - --#: c-convert.c:181 fortran/convert.c:122 java/typeck.c:150 -+#: c-convert.c:182 fortran/convert.c:122 java/typeck.c:150 - #, gcc-internal-format - msgid "conversion to non-scalar type requested" - msgstr "" -@@ -13333,7 +13333,7 @@ - msgid "%qE defined as wrong kind of tag" - msgstr "" - --#: c-decl.c:3674 c-typeck.c:11016 c-family/c-common.c:4164 -+#: c-decl.c:3674 c-typeck.c:11022 c-family/c-common.c:4164 - #, fuzzy, gcc-internal-format - #| msgid "invalid use of `restrict'" - msgid "invalid use of %" -@@ -13466,7 +13466,7 @@ - msgid "variable %qD has initializer but incomplete type" - msgstr "\"%s\" мае незавершаны тып" - --#: c-decl.c:4138 cp/decl.c:4430 cp/decl.c:12670 -+#: c-decl.c:4138 cp/decl.c:4430 cp/decl.c:12687 - #, fuzzy, gcc-internal-format - msgid "inline function %q+D given attribute noinline" - msgstr "няма папярэдняга аб'яўлення для \"%s\"" -@@ -13476,7 +13476,7 @@ - msgid "uninitialized const member in %qT is invalid in C++" - msgstr "" - --#: c-decl.c:4191 cp/init.c:2115 cp/init.c:2130 -+#: c-decl.c:4191 cp/init.c:2117 cp/init.c:2132 - #, fuzzy, gcc-internal-format - msgid "%qD should be initialized" - msgstr "параметр \"%s\" ініцыялізаваны" -@@ -14404,7 +14404,7 @@ - msgid "argument %qD doesn%'t match prototype" - msgstr "" - --#: c-decl.c:8380 cp/decl.c:13528 -+#: c-decl.c:8380 cp/decl.c:13545 - #, gcc-internal-format - msgid "no return statement in function returning non-void" - msgstr "" -@@ -14621,7 +14621,7 @@ - msgid "unknown type name %qE" - msgstr "невядомая назва рэгістра: %s" - --#: c-parser.c:1486 c-parser.c:8568 cp/parser.c:27380 -+#: c-parser.c:1486 c-parser.c:8568 cp/parser.c:27375 - #, fuzzy, gcc-internal-format - #| msgid "empty declaration" - msgid "expected declaration specifiers" -@@ -14632,7 +14632,7 @@ - msgid "expected %<;%>, identifier or %<(%>" - msgstr "" - --#: c-parser.c:1529 cp/parser.c:23810 cp/parser.c:23884 -+#: c-parser.c:1529 cp/parser.c:23805 cp/parser.c:23879 - #, fuzzy, gcc-internal-format - msgid "prefix attributes are ignored for methods" - msgstr "\"%s\" атрыбут ігнарыруецца" -@@ -14683,7 +14683,7 @@ - msgid "ISO C90 does not support %<_Static_assert%>" - msgstr "ISO C89 не падтрымлівае комлексныя тыпы" - --#: c-parser.c:1862 c-parser.c:3383 c-parser.c:8623 cp/parser.c:27251 -+#: c-parser.c:1862 c-parser.c:3383 c-parser.c:8623 cp/parser.c:27246 - #, gcc-internal-format - msgid "expected string literal" - msgstr "" -@@ -14715,8 +14715,8 @@ - #: c-parser.c:7360 c-parser.c:7368 c-parser.c:7397 c-parser.c:7410 - #: c-parser.c:7715 c-parser.c:7839 c-parser.c:8266 c-parser.c:8301 - #: c-parser.c:8354 c-parser.c:8407 c-parser.c:8423 c-parser.c:8469 --#: c-parser.c:8748 c-parser.c:9823 c-parser.c:10626 cp/parser.c:22271 --#: cp/parser.c:24654 cp/parser.c:24684 cp/parser.c:24754 cp/parser.c:26971 -+#: c-parser.c:8748 c-parser.c:9823 c-parser.c:10626 cp/parser.c:22266 -+#: cp/parser.c:24649 cp/parser.c:24679 cp/parser.c:24749 cp/parser.c:26966 - #, gcc-internal-format - msgid "expected identifier" - msgstr "" -@@ -15060,78 +15060,78 @@ - msgid "no type or storage class may be specified here," - msgstr "" - --#: c-parser.c:8270 c-parser.c:8327 cp/parser.c:24714 -+#: c-parser.c:8270 c-parser.c:8327 cp/parser.c:24709 - #, gcc-internal-format - msgid "unknown property attribute" - msgstr "" - --#: c-parser.c:8291 cp/parser.c:24674 -+#: c-parser.c:8291 cp/parser.c:24669 - #, gcc-internal-format - msgid "missing %<=%> (after % attribute)" - msgstr "" - --#: c-parser.c:8294 cp/parser.c:24677 -+#: c-parser.c:8294 cp/parser.c:24672 - #, gcc-internal-format - msgid "missing %<=%> (after % attribute)" - msgstr "" - --#: c-parser.c:8308 cp/parser.c:24692 -+#: c-parser.c:8308 cp/parser.c:24687 - #, gcc-internal-format - msgid "the % attribute may only be specified once" - msgstr "" - --#: c-parser.c:8313 cp/parser.c:24698 -+#: c-parser.c:8313 cp/parser.c:24693 - #, gcc-internal-format - msgid "setter name must terminate with %<:%>" - msgstr "" - --#: c-parser.c:8320 cp/parser.c:24706 -+#: c-parser.c:8320 cp/parser.c:24701 - #, gcc-internal-format - msgid "the % attribute may only be specified once" - msgstr "" - --#: c-parser.c:8506 cp/parser.c:27295 -+#: c-parser.c:8506 cp/parser.c:27290 - #, gcc-internal-format - msgid "%<#pragma omp barrier%> may only be used in compound statements" - msgstr "" - --#: c-parser.c:8517 cp/parser.c:27310 -+#: c-parser.c:8517 cp/parser.c:27305 - #, gcc-internal-format - msgid "%<#pragma omp flush%> may only be used in compound statements" - msgstr "" - --#: c-parser.c:8528 cp/parser.c:27326 -+#: c-parser.c:8528 cp/parser.c:27321 - #, gcc-internal-format - msgid "%<#pragma omp taskwait%> may only be used in compound statements" - msgstr "" - --#: c-parser.c:8539 cp/parser.c:27342 -+#: c-parser.c:8539 cp/parser.c:27337 - #, gcc-internal-format - msgid "%<#pragma omp taskyield%> may only be used in compound statements" - msgstr "" - --#: c-parser.c:8552 cp/parser.c:27370 -+#: c-parser.c:8552 cp/parser.c:27365 - #, gcc-internal-format - msgid "%<#pragma omp section%> may only be used in %<#pragma omp sections%> construct" - msgstr "" - --#: c-parser.c:8558 cp/parser.c:27285 -+#: c-parser.c:8558 cp/parser.c:27280 - #, gcc-internal-format - msgid "%<#pragma GCC pch_preprocess%> must be first" - msgstr "" - --#: c-parser.c:8723 cp/parser.c:24962 -+#: c-parser.c:8723 cp/parser.c:24957 - #, fuzzy, gcc-internal-format - #| msgid "too many input files" - msgid "too many %qs clauses" - msgstr "вельмі шмат уваходзячых файлаў" - --#: c-parser.c:8825 cp/parser.c:25077 -+#: c-parser.c:8825 cp/parser.c:25072 - #, gcc-internal-format - msgid "collapse argument needs positive constant integer expression" - msgstr "" - --#: c-parser.c:8891 cp/parser.c:25128 -+#: c-parser.c:8891 cp/parser.c:25123 - #, gcc-internal-format - msgid "expected % or %" - msgstr "" -@@ -15146,44 +15146,44 @@ - msgid "% value must be positive" - msgstr "" - --#: c-parser.c:9142 cp/parser.c:25347 -+#: c-parser.c:9142 cp/parser.c:25342 - #, gcc-internal-format - msgid "expected %<+%>, %<*%>, %<-%>, %<&%>, %<^%>, %<|%>, %<&&%>, %<||%>, % or %" - msgstr "" - --#: c-parser.c:9231 cp/parser.c:25432 -+#: c-parser.c:9231 cp/parser.c:25427 - #, gcc-internal-format - msgid "schedule % does not take a % parameter" - msgstr "" - --#: c-parser.c:9235 cp/parser.c:25435 -+#: c-parser.c:9235 cp/parser.c:25430 - #, gcc-internal-format - msgid "schedule % does not take a % parameter" - msgstr "" - --#: c-parser.c:9253 cp/parser.c:25451 -+#: c-parser.c:9253 cp/parser.c:25446 - #, fuzzy, gcc-internal-format - #| msgid "invalid %%-code" - msgid "invalid schedule kind" - msgstr "нерэчаісны %%-код" - --#: c-parser.c:9381 cp/parser.c:25583 -+#: c-parser.c:9381 cp/parser.c:25578 - #, gcc-internal-format - msgid "expected %<#pragma omp%> clause" - msgstr "" - --#: c-parser.c:9390 cp/parser.c:25592 -+#: c-parser.c:9390 cp/parser.c:25587 - #, fuzzy, gcc-internal-format - #| msgid "complex invalid for `%s'" - msgid "%qs is not valid for %qs" - msgstr "complex нерэчаісны для \"%s\"" - --#: c-parser.c:9682 cp/parser.c:25876 -+#: c-parser.c:9682 cp/parser.c:25871 - #, gcc-internal-format - msgid "invalid form of %<#pragma omp atomic%>" - msgstr "" - --#: c-parser.c:9722 c-parser.c:9740 cp/parser.c:25907 cp/parser.c:25924 -+#: c-parser.c:9722 c-parser.c:9740 cp/parser.c:25902 cp/parser.c:25919 - #, gcc-internal-format - msgid "invalid operator for %<#pragma omp atomic%>" - msgstr "" -@@ -15193,7 +15193,7 @@ - msgid "expected %<(%> or end of line" - msgstr "" - --#: c-parser.c:9882 cp/parser.c:26195 -+#: c-parser.c:9882 cp/parser.c:26190 - #, fuzzy, gcc-internal-format - msgid "for statement expected" - msgstr "вельмі шмат аргументаў у функцыі" -@@ -15208,12 +15208,12 @@ - msgid "not enough perfectly nested loops" - msgstr "" - --#: c-parser.c:10069 cp/parser.c:26537 -+#: c-parser.c:10069 cp/parser.c:26532 - #, gcc-internal-format - msgid "collapsed loops not perfectly nested" - msgstr "" - --#: c-parser.c:10107 cp/parser.c:26380 cp/parser.c:26418 cp/pt.c:12728 -+#: c-parser.c:10107 cp/parser.c:26375 cp/parser.c:26413 cp/pt.c:12754 - #, gcc-internal-format - msgid "iteration variable %qD should not be firstprivate" - msgstr "" -@@ -15238,27 +15238,27 @@ - msgid "% %qE has incomplete type" - msgstr "\"%s\" мае незавершаны тып" - --#: c-parser.c:10773 cp/parser.c:27181 -+#: c-parser.c:10773 cp/parser.c:27176 - #, gcc-internal-format - msgid "%<__transaction_cancel%> without transactional memory support enabled" - msgstr "" - --#: c-parser.c:10779 cp/parser.c:27187 -+#: c-parser.c:10779 cp/parser.c:27182 - #, gcc-internal-format - msgid "%<__transaction_cancel%> within a %<__transaction_relaxed%>" - msgstr "" - --#: c-parser.c:10788 cp/parser.c:27196 -+#: c-parser.c:10788 cp/parser.c:27191 - #, gcc-internal-format - msgid "outer %<__transaction_cancel%> not within outer %<__transaction_atomic%>" - msgstr "" - --#: c-parser.c:10790 cp/parser.c:27199 -+#: c-parser.c:10790 cp/parser.c:27194 - #, gcc-internal-format - msgid " or a % function" - msgstr "" - --#: c-parser.c:10796 cp/parser.c:27205 -+#: c-parser.c:10796 cp/parser.c:27200 - #, gcc-internal-format - msgid "%<__transaction_cancel%> not within %<__transaction_atomic%>" - msgstr "" -@@ -16045,7 +16045,7 @@ - msgid "initialization of a flexible array member" - msgstr "" - --#: c-typeck.c:6164 cp/typeck2.c:890 -+#: c-typeck.c:6164 cp/typeck2.c:893 - #, gcc-internal-format - msgid "char-array initialized from wide string" - msgstr "" -@@ -16253,223 +16253,223 @@ - msgid "ISO C forbids % with expression, in function returning void" - msgstr "" - --#: c-typeck.c:8825 -+#: c-typeck.c:8831 - #, gcc-internal-format - msgid "function returns address of local variable" - msgstr "" - --#: c-typeck.c:8898 cp/semantics.c:1045 -+#: c-typeck.c:8904 cp/semantics.c:1045 - #, gcc-internal-format - msgid "switch quantity not an integer" - msgstr "" - --#: c-typeck.c:8911 -+#: c-typeck.c:8917 - #, gcc-internal-format - msgid "% switch expression not converted to % in ISO C" - msgstr "" - --#: c-typeck.c:8947 c-typeck.c:8955 -+#: c-typeck.c:8953 c-typeck.c:8961 - #, fuzzy, gcc-internal-format - msgid "case label is not an integer constant expression" - msgstr "памер масіва \"%s\" адмоўны" - --#: c-typeck.c:8961 cp/parser.c:8827 -+#: c-typeck.c:8967 cp/parser.c:8827 - #, gcc-internal-format - msgid "case label not within a switch statement" - msgstr "" - --#: c-typeck.c:8963 -+#: c-typeck.c:8969 - #, gcc-internal-format - msgid "% label not within a switch statement" - msgstr "" - --#: c-typeck.c:9046 cp/parser.c:9127 -+#: c-typeck.c:9052 cp/parser.c:9127 - #, gcc-internal-format - msgid "suggest explicit braces to avoid ambiguous %" - msgstr "" - --#: c-typeck.c:9155 cp/parser.c:9854 -+#: c-typeck.c:9161 cp/parser.c:9854 - #, gcc-internal-format - msgid "break statement not within loop or switch" - msgstr "" - --#: c-typeck.c:9157 cp/parser.c:9875 -+#: c-typeck.c:9163 cp/parser.c:9875 - #, gcc-internal-format - msgid "continue statement not within a loop" - msgstr "" - --#: c-typeck.c:9162 cp/parser.c:9865 -+#: c-typeck.c:9168 cp/parser.c:9865 - #, gcc-internal-format - msgid "break statement used with OpenMP for loop" - msgstr "" - --#: c-typeck.c:9188 cp/cp-gimplify.c:402 -+#: c-typeck.c:9194 cp/cp-gimplify.c:402 - #, gcc-internal-format - msgid "statement with no effect" - msgstr "" - --#: c-typeck.c:9214 -+#: c-typeck.c:9220 - #, gcc-internal-format - msgid "expression statement has incomplete type" - msgstr "" - --#: c-typeck.c:9473 c-typeck.c:9508 c-typeck.c:9522 -+#: c-typeck.c:9479 c-typeck.c:9514 c-typeck.c:9528 - #, gcc-internal-format - msgid "conversion of scalar to vector involves truncation" - msgstr "" - --#: c-typeck.c:9950 cp/typeck.c:3939 -+#: c-typeck.c:9956 cp/typeck.c:3939 - #, gcc-internal-format - msgid "right shift count is negative" - msgstr "" - --#: c-typeck.c:9961 cp/typeck.c:3946 -+#: c-typeck.c:9967 cp/typeck.c:3946 - #, gcc-internal-format - msgid "right shift count >= width of type" - msgstr "" - --#: c-typeck.c:10002 cp/typeck.c:3968 -+#: c-typeck.c:10008 cp/typeck.c:3968 - #, gcc-internal-format - msgid "left shift count is negative" - msgstr "" - --#: c-typeck.c:10009 cp/typeck.c:3974 -+#: c-typeck.c:10015 cp/typeck.c:3974 - #, gcc-internal-format - msgid "left shift count >= width of type" - msgstr "" - --#: c-typeck.c:10032 c-typeck.c:10169 -+#: c-typeck.c:10038 c-typeck.c:10175 - #, gcc-internal-format - msgid "comparing vectors with different element types" - msgstr "" - --#: c-typeck.c:10039 c-typeck.c:10176 -+#: c-typeck.c:10045 c-typeck.c:10182 - #, gcc-internal-format - msgid "comparing vectors with different number of elements" - msgstr "" - --#: c-typeck.c:10055 cp/typeck.c:4020 -+#: c-typeck.c:10061 cp/typeck.c:4020 - #, gcc-internal-format - msgid "comparing floating point with == or != is unsafe" - msgstr "" - --#: c-typeck.c:10072 c-typeck.c:10092 -+#: c-typeck.c:10078 c-typeck.c:10098 - #, gcc-internal-format - msgid "the comparison will always evaluate as % for the address of %qD will never be NULL" - msgstr "" - --#: c-typeck.c:10078 c-typeck.c:10098 -+#: c-typeck.c:10084 c-typeck.c:10104 - #, gcc-internal-format - msgid "the comparison will always evaluate as % for the address of %qD will never be NULL" - msgstr "" - --#: c-typeck.c:10119 c-typeck.c:10219 -+#: c-typeck.c:10125 c-typeck.c:10225 - #, gcc-internal-format - msgid "comparison of pointers to disjoint address spaces" - msgstr "" - --#: c-typeck.c:10126 c-typeck.c:10132 -+#: c-typeck.c:10132 c-typeck.c:10138 - #, fuzzy, gcc-internal-format - msgid "ISO C forbids comparison of % with function pointer" - msgstr "ISO C не дазваляе дэкларацыі метак (label)" - --#: c-typeck.c:10139 c-typeck.c:10229 -+#: c-typeck.c:10145 c-typeck.c:10235 - #, gcc-internal-format - msgid "comparison of distinct pointer types lacks a cast" - msgstr "" - --#: c-typeck.c:10151 c-typeck.c:10156 c-typeck.c:10255 c-typeck.c:10260 -+#: c-typeck.c:10157 c-typeck.c:10162 c-typeck.c:10261 c-typeck.c:10266 - #, gcc-internal-format - msgid "comparison between pointer and integer" - msgstr "" - --#: c-typeck.c:10207 -+#: c-typeck.c:10213 - #, gcc-internal-format - msgid "comparison of complete and incomplete pointers" - msgstr "" - --#: c-typeck.c:10209 -+#: c-typeck.c:10215 - #, gcc-internal-format - msgid "ISO C forbids ordered comparisons of pointers to functions" - msgstr "" - --#: c-typeck.c:10214 -+#: c-typeck.c:10220 - #, gcc-internal-format - msgid "ordered comparison of pointer with null pointer" - msgstr "" - --#: c-typeck.c:10237 c-typeck.c:10240 c-typeck.c:10247 c-typeck.c:10250 -+#: c-typeck.c:10243 c-typeck.c:10246 c-typeck.c:10253 c-typeck.c:10256 - #: cp/typeck.c:4271 cp/typeck.c:4278 - #, gcc-internal-format - msgid "ordered comparison of pointer with integer zero" - msgstr "" - --#: c-typeck.c:10294 cp/typeck.c:4350 -+#: c-typeck.c:10300 cp/typeck.c:4350 - #, gcc-internal-format - msgid "implicit conversion from %qT to %qT to match other operand of binary expression" - msgstr "" - --#: c-typeck.c:10578 -+#: c-typeck.c:10584 - #, gcc-internal-format - msgid "used array that cannot be converted to pointer where scalar is required" - msgstr "" - --#: c-typeck.c:10582 -+#: c-typeck.c:10588 - #, gcc-internal-format - msgid "used struct type value where scalar is required" - msgstr "" - --#: c-typeck.c:10586 -+#: c-typeck.c:10592 - #, gcc-internal-format - msgid "used union type value where scalar is required" - msgstr "" - --#: c-typeck.c:10597 -+#: c-typeck.c:10603 - #, gcc-internal-format - msgid "used vector type where scalar is required" - msgstr "" - --#: c-typeck.c:10751 cp/semantics.c:4202 -+#: c-typeck.c:10757 cp/semantics.c:4202 - #, gcc-internal-format - msgid "%qE has invalid type for %" - msgstr "" - --#: c-typeck.c:10788 cp/semantics.c:4217 -+#: c-typeck.c:10794 cp/semantics.c:4217 - #, gcc-internal-format - msgid "%qE has invalid type for %" - msgstr "" - --#: c-typeck.c:10805 cp/semantics.c:4227 -+#: c-typeck.c:10811 cp/semantics.c:4227 - #, gcc-internal-format - msgid "%qE must be % for %" - msgstr "" - --#: c-typeck.c:10815 cp/semantics.c:3995 -+#: c-typeck.c:10821 cp/semantics.c:3995 - #, gcc-internal-format - msgid "%qE is not a variable in clause %qs" - msgstr "" - --#: c-typeck.c:10823 c-typeck.c:10845 c-typeck.c:10867 -+#: c-typeck.c:10829 c-typeck.c:10851 c-typeck.c:10873 - #, gcc-internal-format - msgid "%qE appears more than once in data clauses" - msgstr "" - --#: c-typeck.c:10838 cp/semantics.c:4018 -+#: c-typeck.c:10844 cp/semantics.c:4018 - #, gcc-internal-format - msgid "%qE is not a variable in clause %" - msgstr "" - --#: c-typeck.c:10860 cp/semantics.c:4040 -+#: c-typeck.c:10866 cp/semantics.c:4040 - #, gcc-internal-format - msgid "%qE is not a variable in clause %" - msgstr "" - --#: c-typeck.c:10928 cp/semantics.c:4273 -+#: c-typeck.c:10934 cp/semantics.c:4273 - #, gcc-internal-format - msgid "%qE is predetermined %qs for %qs" - msgstr "" - --#: c-typeck.c:11030 -+#: c-typeck.c:11036 - #, gcc-internal-format - msgid "C++ requires promoted type, not enum type, in %" - msgstr "" -@@ -17522,7 +17522,7 @@ - msgid "multiple EH personalities are supported only with assemblers supporting .cfi_personality directive" - msgstr "" - --#: dwarf2out.c:10710 -+#: dwarf2out.c:10713 - #, gcc-internal-format, gfc-internal-format - msgid "non-delegitimized UNSPEC %s (%d) found in variable location" - msgstr "" -@@ -17643,12 +17643,12 @@ - msgid "local frame unavailable (naked function?)" - msgstr "" - --#: expr.c:9971 -+#: expr.c:9972 - #, gcc-internal-format - msgid "%Kcall to %qs declared with attribute error: %s" - msgstr "" - --#: expr.c:9978 -+#: expr.c:9979 - #, gcc-internal-format - msgid "%Kcall to %qs declared with attribute warning: %s" - msgstr "" -@@ -17735,28 +17735,28 @@ - msgid "total size of local objects too large" - msgstr "памер масіва \"%s\" вельмі вялікі" - --#: function.c:1732 gimplify.c:5163 -+#: function.c:1732 gimplify.c:5164 - #, fuzzy, gcc-internal-format - #| msgid "impossible operator '%s'" - msgid "impossible constraint in %" - msgstr "немагчымы апэратар '%s'" - --#: function.c:3959 -+#: function.c:3974 - #, gcc-internal-format - msgid "variable %q+D might be clobbered by % or %" - msgstr "" - --#: function.c:3980 -+#: function.c:3995 - #, gcc-internal-format - msgid "argument %q+D might be clobbered by % or %" - msgstr "" - --#: function.c:4502 -+#: function.c:4517 - #, gcc-internal-format - msgid "function returns an aggregate" - msgstr "" - --#: function.c:4896 -+#: function.c:4911 - #, fuzzy, gcc-internal-format - #| msgid "unused parameter `%s'" - msgid "unused parameter %q+D" -@@ -18201,62 +18201,62 @@ - msgid "using result of function returning %" - msgstr "" - --#: gimplify.c:5048 -+#: gimplify.c:5049 - #, gcc-internal-format, gfc-internal-format - msgid "invalid lvalue in asm output %d" - msgstr "" - --#: gimplify.c:5164 -+#: gimplify.c:5165 - #, gcc-internal-format, gfc-internal-format - msgid "non-memory input %d must stay in memory" - msgstr "" - --#: gimplify.c:5186 -+#: gimplify.c:5187 - #, gcc-internal-format, gfc-internal-format - msgid "memory input %d is not directly addressable" - msgstr "" - --#: gimplify.c:5681 -+#: gimplify.c:5682 - #, gcc-internal-format - msgid "threadprivate variable %qE used in untied task" - msgstr "" - --#: gimplify.c:5683 gimplify.c:5745 -+#: gimplify.c:5684 gimplify.c:5746 - #, gcc-internal-format - msgid "enclosing task" - msgstr "" - --#: gimplify.c:5742 -+#: gimplify.c:5743 - #, gcc-internal-format - msgid "%qE not specified in enclosing parallel" - msgstr "" - --#: gimplify.c:5747 -+#: gimplify.c:5748 - #, gcc-internal-format - msgid "enclosing parallel" - msgstr "" - --#: gimplify.c:5852 -+#: gimplify.c:5853 - #, gcc-internal-format - msgid "iteration variable %qE should be private" - msgstr "" - --#: gimplify.c:5866 -+#: gimplify.c:5867 - #, gcc-internal-format - msgid "iteration variable %qE should not be firstprivate" - msgstr "" - --#: gimplify.c:5869 -+#: gimplify.c:5870 - #, gcc-internal-format - msgid "iteration variable %qE should not be reduction" - msgstr "" - --#: gimplify.c:6032 -+#: gimplify.c:6033 - #, gcc-internal-format - msgid "%s variable %qE is private in outer context" - msgstr "" - --#: gimplify.c:7794 -+#: gimplify.c:7795 - #, gcc-internal-format - msgid "gimplification failed" - msgstr "" -@@ -18471,48 +18471,48 @@ - msgid "function %qD redeclared as variable" - msgstr "віртуальныя функцыі не могуць быць сяброўскімі" - --#: omp-low.c:1846 -+#: omp-low.c:1847 - #, gcc-internal-format - msgid "barrier region may not be closely nested inside of work-sharing, critical, ordered, master or explicit task region" - msgstr "" - --#: omp-low.c:1851 -+#: omp-low.c:1853 - #, gcc-internal-format - msgid "work-sharing region may not be closely nested inside of work-sharing, critical, ordered, master or explicit task region" - msgstr "" - --#: omp-low.c:1869 -+#: omp-low.c:1872 - #, gcc-internal-format - msgid "master region may not be closely nested inside of work-sharing or explicit task region" - msgstr "" - --#: omp-low.c:1884 -+#: omp-low.c:1888 - #, gcc-internal-format - msgid "ordered region may not be closely nested inside of critical or explicit task region" - msgstr "" - --#: omp-low.c:1890 -+#: omp-low.c:1896 - #, gcc-internal-format - msgid "ordered region must be closely nested inside a loop region with an ordered clause" - msgstr "" - --#: omp-low.c:1905 -+#: omp-low.c:1914 - #, gcc-internal-format - msgid "critical region may not be nested inside a critical region with the same name" - msgstr "" - --#: omp-low.c:7024 cp/decl.c:2885 cp/parser.c:9862 cp/parser.c:9882 -+#: omp-low.c:7034 cp/decl.c:2885 cp/parser.c:9862 cp/parser.c:9882 - #, gcc-internal-format - msgid "invalid exit from OpenMP structured block" - msgstr "" - --#: omp-low.c:7026 omp-low.c:7031 -+#: omp-low.c:7036 omp-low.c:7041 - #, gcc-internal-format - msgid "invalid entry to OpenMP structured block" - msgstr "" - - #. Otherwise, be vague and lazy, but efficient. --#: omp-low.c:7034 -+#: omp-low.c:7044 - #, gcc-internal-format - msgid "invalid branch to/from an OpenMP structured block" - msgstr "" -@@ -18610,12 +18610,12 @@ - msgid "section anchors must be disabled when toplevel reorder is disabled" - msgstr "" - --#: opts.c:721 config/darwin.c:3002 config/sh/sh.c:809 -+#: opts.c:721 config/darwin.c:3002 config/sh/sh.c:797 - #, gcc-internal-format - msgid "-freorder-blocks-and-partition does not work with exceptions on this architecture" - msgstr "" - --#: opts.c:736 config/sh/sh.c:817 -+#: opts.c:736 config/sh/sh.c:805 - #, gcc-internal-format - msgid "-freorder-blocks-and-partition does not support unwind info on this architecture" - msgstr "" -@@ -18989,8 +18989,8 @@ - msgstr "Клас \"%s\" ужо існуе" - - #: reginfo.c:864 config/ia64/ia64.c:5753 config/ia64/ia64.c:5760 --#: config/pa/pa.c:427 config/pa/pa.c:434 config/sh/sh.c:8761 --#: config/sh/sh.c:8768 config/spu/spu.c:5198 config/spu/spu.c:5205 -+#: config/pa/pa.c:427 config/pa/pa.c:434 config/sh/sh.c:8764 -+#: config/sh/sh.c:8771 config/spu/spu.c:5198 config/spu/spu.c:5205 - #, gcc-internal-format, gfc-internal-format - msgid "unknown register name: %s" - msgstr "невядомая назва рэгістра: %s" -@@ -19299,7 +19299,7 @@ - msgid "packed attribute is unnecessary" - msgstr "" - --#: stor-layout.c:2244 -+#: stor-layout.c:2252 - #, gcc-internal-format - msgid "alignment of array elements is greater than element size" - msgstr "" -@@ -19319,12 +19319,12 @@ - msgid "nested function trampolines not supported on this target" - msgstr "атрыбуты секцыі не падтрымліваюцца для гэтай мэты" - --#: targhooks.c:1154 -+#: targhooks.c:1161 - #, fuzzy, gcc-internal-format - msgid "target attribute is not supported on this machine" - msgstr "атрыбуты секцыі не падтрымліваюцца для гэтай мэты" - --#: targhooks.c:1164 -+#: targhooks.c:1171 - #, fuzzy, gcc-internal-format - msgid "#pragma GCC target is not supported for this machine" - msgstr "атрыбуты секцыі не падтрымліваюцца для гэтай мэты" -@@ -19520,7 +19520,7 @@ - msgid "% function call not within outer transaction or %" - msgstr "" - --#: trans-mem.c:664 trans-mem.c:4194 -+#: trans-mem.c:664 trans-mem.c:4192 - #, gcc-internal-format - msgid "unsafe function call %qD within atomic transaction" - msgstr "" -@@ -19535,7 +19535,7 @@ - msgid "unsafe indirect function call within atomic transaction" - msgstr "" - --#: trans-mem.c:682 trans-mem.c:4127 -+#: trans-mem.c:682 trans-mem.c:4125 - #, gcc-internal-format - msgid "unsafe function call %qD within % function" - msgstr "" -@@ -19550,7 +19550,7 @@ - msgid "unsafe indirect function call within % function" - msgstr "" - --#: trans-mem.c:707 trans-mem.c:4166 -+#: trans-mem.c:707 trans-mem.c:4164 - #, fuzzy, gcc-internal-format - msgid "asm not allowed in atomic transaction" - msgstr "\"%s\" - гэта не пачатак дэкларацыі" -@@ -19585,7 +19585,7 @@ - msgid "outer transaction in % function" - msgstr "" - --#: trans-mem.c:3792 -+#: trans-mem.c:3790 - #, gcc-internal-format - msgid "%Kasm not allowed in % function" - msgstr "" -@@ -20218,117 +20218,117 @@ - msgid "ignoring unknown option %q.*s in %<-fdump-%s%>" - msgstr "" - --#: tree-eh.c:4320 -+#: tree-eh.c:4319 - #, gcc-internal-format, gfc-internal-format - msgid "BB %i has multiple EH edges" - msgstr "" - --#: tree-eh.c:4332 -+#: tree-eh.c:4331 - #, gcc-internal-format, gfc-internal-format - msgid "BB %i can not throw but has an EH edge" - msgstr "" - --#: tree-eh.c:4340 -+#: tree-eh.c:4339 - #, gcc-internal-format, gfc-internal-format - msgid "BB %i last statement has incorrectly set lp" - msgstr "" - --#: tree-eh.c:4346 -+#: tree-eh.c:4345 - #, gcc-internal-format, gfc-internal-format - msgid "BB %i is missing an EH edge" - msgstr "" - --#: tree-eh.c:4352 -+#: tree-eh.c:4351 - #, gcc-internal-format, gfc-internal-format - msgid "Incorrect EH edge %i->%i" - msgstr "" - --#: tree-eh.c:4386 tree-eh.c:4405 -+#: tree-eh.c:4385 tree-eh.c:4404 - #, gcc-internal-format, gfc-internal-format - msgid "BB %i is missing an edge" - msgstr "" - --#: tree-eh.c:4422 -+#: tree-eh.c:4421 - #, gcc-internal-format, gfc-internal-format - msgid "BB %i too many fallthru edges" - msgstr "" - --#: tree-eh.c:4431 -+#: tree-eh.c:4430 - #, gcc-internal-format, gfc-internal-format - msgid "BB %i has incorrect edge" - msgstr "" - --#: tree-eh.c:4437 -+#: tree-eh.c:4436 - #, gcc-internal-format, gfc-internal-format - msgid "BB %i has incorrect fallthru edge" - msgstr "" - --#: tree-inline.c:3040 -+#: tree-inline.c:3041 - #, gcc-internal-format - msgid "function %q+F can never be copied because it receives a non-local goto" - msgstr "" - --#: tree-inline.c:3054 -+#: tree-inline.c:3055 - #, gcc-internal-format - msgid "function %q+F can never be copied because it saves address of local label in a static variable" - msgstr "" - --#: tree-inline.c:3094 -+#: tree-inline.c:3095 - #, gcc-internal-format - msgid "function %q+F can never be inlined because it uses alloca (override using the always_inline attribute)" - msgstr "" - --#: tree-inline.c:3108 -+#: tree-inline.c:3109 - #, gcc-internal-format - msgid "function %q+F can never be inlined because it uses setjmp" - msgstr "" - --#: tree-inline.c:3122 -+#: tree-inline.c:3123 - #, gcc-internal-format - msgid "function %q+F can never be inlined because it uses variable argument lists" - msgstr "" - --#: tree-inline.c:3134 -+#: tree-inline.c:3135 - #, gcc-internal-format - msgid "function %q+F can never be inlined because it uses setjmp-longjmp exception handling" - msgstr "" - --#: tree-inline.c:3142 -+#: tree-inline.c:3143 - #, gcc-internal-format - msgid "function %q+F can never be inlined because it uses non-local goto" - msgstr "" - --#: tree-inline.c:3154 -+#: tree-inline.c:3155 - #, gcc-internal-format - msgid "function %q+F can never be inlined because it uses __builtin_return or __builtin_apply_args" - msgstr "" - --#: tree-inline.c:3174 -+#: tree-inline.c:3175 - #, gcc-internal-format - msgid "function %q+F can never be inlined because it contains a computed goto" - msgstr "" - --#: tree-inline.c:3254 -+#: tree-inline.c:3255 - #, gcc-internal-format - msgid "function %q+F can never be inlined because it is suppressed using -fno-inline" - msgstr "" - --#: tree-inline.c:3262 -+#: tree-inline.c:3263 - #, gcc-internal-format - msgid "function %q+F can never be inlined because it uses attributes conflicting with inlining" - msgstr "" - --#: tree-inline.c:3843 -+#: tree-inline.c:3844 - #, gcc-internal-format - msgid "inlining failed in call to always_inline %q+F: %s" - msgstr "" - --#: tree-inline.c:3845 tree-inline.c:3860 -+#: tree-inline.c:3846 tree-inline.c:3861 - #, gcc-internal-format - msgid "called from here" - msgstr "выклікана адсюль" - --#: tree-inline.c:3858 -+#: tree-inline.c:3859 - #, gcc-internal-format - msgid "inlining failed in call to %q+F: %s" - msgstr "" -@@ -20367,7 +20367,7 @@ - msgstr "памер вяртаемага значэння \"%s\" больш чым %d байт" - - #: tree-outof-ssa.c:784 tree-outof-ssa.c:841 tree-ssa-coalesce.c:951 --#: tree-ssa-coalesce.c:966 tree-ssa-coalesce.c:1188 tree-ssa-live.c:1340 -+#: tree-ssa-coalesce.c:966 tree-ssa-coalesce.c:1188 tree-ssa-live.c:1337 - #, gcc-internal-format - msgid "SSA corruption" - msgstr "" -@@ -20610,72 +20610,72 @@ - msgid "vector shuffling operation will be expanded piecewise" - msgstr "" - --#: tree-vrp.c:5300 -+#: tree-vrp.c:5272 - #, gcc-internal-format - msgid "array subscript is outside array bounds" - msgstr "" - --#: tree-vrp.c:5312 tree-vrp.c:5399 -+#: tree-vrp.c:5284 tree-vrp.c:5371 - #, gcc-internal-format - msgid "array subscript is above array bounds" - msgstr "" - --#: tree-vrp.c:5319 tree-vrp.c:5387 -+#: tree-vrp.c:5291 tree-vrp.c:5359 - #, gcc-internal-format - msgid "array subscript is below array bounds" - msgstr "" - --#: tree-vrp.c:6028 -+#: tree-vrp.c:6000 - #, gcc-internal-format - msgid "assuming signed overflow does not occur when simplifying conditional to constant" - msgstr "" - --#: tree-vrp.c:6034 -+#: tree-vrp.c:6006 - #, gcc-internal-format - msgid "assuming signed overflow does not occur when simplifying conditional" - msgstr "" - --#: tree-vrp.c:6078 -+#: tree-vrp.c:6050 - #, gcc-internal-format - msgid "comparison always false due to limited range of data type" - msgstr "" - --#: tree-vrp.c:6080 -+#: tree-vrp.c:6052 - #, gcc-internal-format - msgid "comparison always true due to limited range of data type" - msgstr "" - --#: tree-vrp.c:6871 -+#: tree-vrp.c:6847 - #, gcc-internal-format - msgid "assuming signed overflow does not occur when simplifying % or %<%%%> to %<>>%> or %<&%>" - msgstr "" - --#: tree-vrp.c:6953 -+#: tree-vrp.c:6929 - #, gcc-internal-format - msgid "assuming signed overflow does not occur when simplifying % to % or %<-X%>" - msgstr "" - --#: tree.c:4235 -+#: tree.c:4236 - #, gcc-internal-format - msgid "ignoring attributes applied to %qT after definition" - msgstr "" - --#: tree.c:5460 -+#: tree.c:5475 - #, gcc-internal-format - msgid "%q+D already declared with dllexport attribute: dllimport ignored" - msgstr "" - --#: tree.c:5472 -+#: tree.c:5487 - #, gcc-internal-format - msgid "%q+D redeclared without dllimport attribute after being referenced with dll linkage" - msgstr "" - --#: tree.c:5487 -+#: tree.c:5502 - #, gcc-internal-format - msgid "%q+D redeclared without dllimport attribute: previous dllimport ignored" - msgstr "" - --#: tree.c:5530 tree.c:5542 tree.c:5552 c-family/c-common.c:5865 -+#: tree.c:5545 tree.c:5557 tree.c:5567 c-family/c-common.c:5865 - #: c-family/c-common.c:5884 c-family/c-common.c:5902 c-family/c-common.c:5930 - #: c-family/c-common.c:5957 c-family/c-common.c:5983 c-family/c-common.c:6002 - #: c-family/c-common.c:6019 c-family/c-common.c:6043 c-family/c-common.c:6066 -@@ -20689,142 +20689,142 @@ - #: c-family/c-common.c:7523 c-family/c-common.c:7544 c-family/c-common.c:7656 - #: c-family/c-common.c:7680 c-family/c-common.c:7971 c-family/c-common.c:7994 - #: c-family/c-common.c:8033 c-family/c-common.c:8111 c-family/c-common.c:8260 --#: config/darwin.c:1942 config/arm/arm.c:5007 config/arm/arm.c:5035 --#: config/arm/arm.c:5052 config/avr/avr.c:6763 config/h8300/h8300.c:5418 --#: config/h8300/h8300.c:5442 config/i386/i386.c:4939 config/i386/i386.c:31897 --#: config/ia64/ia64.c:734 config/rs6000/rs6000.c:24321 config/spu/spu.c:4035 --#: ada/gcc-interface/utils.c:5505 lto/lto-lang.c:215 -+#: config/darwin.c:1942 config/arm/arm.c:5011 config/arm/arm.c:5039 -+#: config/arm/arm.c:5056 config/avr/avr.c:6773 config/h8300/h8300.c:5418 -+#: config/h8300/h8300.c:5442 config/i386/i386.c:4946 config/i386/i386.c:32027 -+#: config/ia64/ia64.c:734 config/rs6000/rs6000.c:24344 config/spu/spu.c:4035 -+#: ada/gcc-interface/utils.c:5496 lto/lto-lang.c:215 - #, fuzzy, gcc-internal-format - #| msgid "`%s' attribute ignored" - msgid "%qE attribute ignored" - msgstr "\"%s\" атрыбут ігнарыруецца" - --#: tree.c:5570 -+#: tree.c:5585 - #, gcc-internal-format - msgid "inline function %q+D declared as dllimport: attribute ignored" - msgstr "" - --#: tree.c:5578 -+#: tree.c:5593 - #, gcc-internal-format - msgid "function %q+D definition is marked dllimport" - msgstr "" - --#: tree.c:5586 -+#: tree.c:5601 - #, gcc-internal-format - msgid "variable %q+D definition is marked dllimport" - msgstr "" - --#: tree.c:5614 -+#: tree.c:5629 - #, gcc-internal-format - msgid "external linkage required for symbol %q+D because of %qE attribute" - msgstr "" - --#: tree.c:5628 -+#: tree.c:5643 - #, gcc-internal-format - msgid "%qE implies default visibility, but %qD has already been declared with a different visibility" - msgstr "" - --#: tree.c:7378 -+#: tree.c:7394 - #, gcc-internal-format - msgid "arrays of functions are not meaningful" - msgstr "" - --#: tree.c:7545 -+#: tree.c:7561 - #, gcc-internal-format - msgid "function return type cannot be function" - msgstr "" - --#: tree.c:8844 tree.c:8929 tree.c:8990 -+#: tree.c:8860 tree.c:8945 tree.c:9006 - #, gcc-internal-format, gfc-internal-format - msgid "tree check: %s, have %s in %s, at %s:%d" - msgstr "" - --#: tree.c:8881 -+#: tree.c:8897 - #, gcc-internal-format, gfc-internal-format - msgid "tree check: expected none of %s, have %s in %s, at %s:%d" - msgstr "" - --#: tree.c:8894 -+#: tree.c:8910 - #, gcc-internal-format - msgid "tree check: expected class %qs, have %qs (%s) in %s, at %s:%d" - msgstr "" - --#: tree.c:8943 -+#: tree.c:8959 - #, gcc-internal-format - msgid "tree check: did not expect class %qs, have %qs (%s) in %s, at %s:%d" - msgstr "" - --#: tree.c:8956 -+#: tree.c:8972 - #, gcc-internal-format, gfc-internal-format - msgid "tree check: expected omp_clause %s, have %s in %s, at %s:%d" - msgstr "" - --#: tree.c:9016 -+#: tree.c:9032 - #, gcc-internal-format - msgid "tree check: expected tree that contains %qs structure, have %qs in %s, at %s:%d" - msgstr "" - --#: tree.c:9030 -+#: tree.c:9046 - #, gcc-internal-format, gfc-internal-format - msgid "tree check: accessed elt %d of tree_vec with %d elts in %s, at %s:%d" - msgstr "" - --#: tree.c:9043 -+#: tree.c:9059 - #, gcc-internal-format, gfc-internal-format - msgid "tree check: accessed operand %d of %s with %d operands in %s, at %s:%d" - msgstr "" - --#: tree.c:9056 -+#: tree.c:9072 - #, gcc-internal-format, gfc-internal-format - msgid "tree check: accessed operand %d of omp_clause %s with %d operands in %s, at %s:%d" - msgstr "" - --#: tree.c:11340 -+#: tree.c:11356 - #, gcc-internal-format - msgid "%qD is deprecated (declared at %s:%d): %s" - msgstr "" - --#: tree.c:11344 -+#: tree.c:11360 - #, gcc-internal-format - msgid "%qD is deprecated (declared at %s:%d)" - msgstr "" - --#: tree.c:11369 -+#: tree.c:11385 - #, gcc-internal-format - msgid "%qE is deprecated (declared at %s:%d): %s" - msgstr "" - --#: tree.c:11373 -+#: tree.c:11389 - #, gcc-internal-format - msgid "%qE is deprecated (declared at %s:%d)" - msgstr "" - --#: tree.c:11380 -+#: tree.c:11396 - #, gcc-internal-format, gfc-internal-format - msgid "type is deprecated (declared at %s:%d): %s" - msgstr "" - --#: tree.c:11384 -+#: tree.c:11400 - #, gcc-internal-format, gfc-internal-format - msgid "type is deprecated (declared at %s:%d)" - msgstr "" - --#: tree.c:11393 -+#: tree.c:11409 - #, gcc-internal-format - msgid "%qE is deprecated: %s" - msgstr "" - --#: tree.c:11396 -+#: tree.c:11412 - #, gcc-internal-format - msgid "%qE is deprecated" - msgstr "" - --#: tree.c:11401 -+#: tree.c:11417 - #, gcc-internal-format, gfc-internal-format - msgid "type is deprecated: %s" - msgstr "" - --#: tree.c:11404 -+#: tree.c:11420 - #, gcc-internal-format - msgid "type is deprecated" - msgstr "" -@@ -21041,12 +21041,12 @@ - msgid "no sclass for %s stab (0x%x)" - msgstr "" - --#: lto-streamer.h:962 -+#: lto-streamer.h:975 - #, gcc-internal-format, gfc-internal-format - msgid "bytecode stream: expected tag %s instead of %s" - msgstr "" - --#: lto-streamer.h:972 -+#: lto-streamer.h:985 - #, gcc-internal-format, gfc-internal-format - msgid "bytecode stream: tag %s is not in the expected range [%s, %s]" - msgstr "" -@@ -21061,8 +21061,8 @@ - msgid "string length %qd is greater than the length %qd ISO C%d compilers are required to support" - msgstr "" - --#: c-family/c-common.c:1494 c-family/c-common.c:1506 cp/semantics.c:6646 --#: cp/semantics.c:8030 -+#: c-family/c-common.c:1494 c-family/c-common.c:1506 cp/semantics.c:6677 -+#: cp/semantics.c:8071 - #, gcc-internal-format - msgid "overflow in constant expression" - msgstr "" -@@ -21698,40 +21698,40 @@ - msgid "invalid vector type for attribute %qE" - msgstr "нявернае выкарыстанне \"restict\"" - --#: c-family/c-common.c:7720 ada/gcc-interface/utils.c:5623 --#: ada/gcc-interface/utils.c:5717 -+#: c-family/c-common.c:7720 ada/gcc-interface/utils.c:5614 -+#: ada/gcc-interface/utils.c:5708 - #, gcc-internal-format - msgid "vector size not an integral multiple of component size" - msgstr "" - --#: c-family/c-common.c:7726 ada/gcc-interface/utils.c:5629 --#: ada/gcc-interface/utils.c:5723 -+#: c-family/c-common.c:7726 ada/gcc-interface/utils.c:5620 -+#: ada/gcc-interface/utils.c:5714 - #, gcc-internal-format - msgid "zero vector size" - msgstr "" - --#: c-family/c-common.c:7734 ada/gcc-interface/utils.c:5637 --#: ada/gcc-interface/utils.c:5730 -+#: c-family/c-common.c:7734 ada/gcc-interface/utils.c:5628 -+#: ada/gcc-interface/utils.c:5721 - #, gcc-internal-format - msgid "number of components of the vector not a power of two" - msgstr "" - --#: c-family/c-common.c:7762 ada/gcc-interface/utils.c:5364 -+#: c-family/c-common.c:7762 ada/gcc-interface/utils.c:5355 - #, gcc-internal-format - msgid "nonnull attribute without arguments on a non-prototype" - msgstr "" - --#: c-family/c-common.c:7776 ada/gcc-interface/utils.c:5378 -+#: c-family/c-common.c:7776 ada/gcc-interface/utils.c:5369 - #, gcc-internal-format, gfc-internal-format - msgid "nonnull argument has invalid operand number (argument %lu)" - msgstr "" - --#: c-family/c-common.c:7798 ada/gcc-interface/utils.c:5400 -+#: c-family/c-common.c:7798 ada/gcc-interface/utils.c:5391 - #, gcc-internal-format, gfc-internal-format - msgid "nonnull argument with out-of-range operand number (argument %lu, operand %lu)" - msgstr "" - --#: c-family/c-common.c:7806 ada/gcc-interface/utils.c:5409 -+#: c-family/c-common.c:7806 ada/gcc-interface/utils.c:5400 - #, gcc-internal-format, gfc-internal-format - msgid "nonnull argument references non-pointer operand (argument %lu, operand %lu)" - msgstr "" -@@ -21773,12 +21773,12 @@ - msgid "%qE attribute only applies to variadic functions" - msgstr "\"%s\" звычайна функцыя" - --#: c-family/c-common.c:8069 ada/gcc-interface/utils.c:5451 -+#: c-family/c-common.c:8069 ada/gcc-interface/utils.c:5442 - #, fuzzy, gcc-internal-format - msgid "requested position is not an integer constant" - msgstr "аргумент `__builtin_args_info' павінен быць канстантай" - --#: c-family/c-common.c:8077 ada/gcc-interface/utils.c:5458 -+#: c-family/c-common.c:8077 ada/gcc-interface/utils.c:5449 - #, gcc-internal-format - msgid "requested position is less than zero" - msgstr "" -@@ -23560,231 +23560,231 @@ - msgstr "" - - #: config/alpha/alpha.c:6576 config/alpha/alpha.c:6579 config/s390/s390.c:9162 --#: config/s390/s390.c:9165 config/tilegx/tilegx.c:3394 -+#: config/s390/s390.c:9165 config/tilegx/tilegx.c:3395 - #: config/tilepro/tilepro.c:3098 - #, gcc-internal-format - msgid "bad builtin fcode" - msgstr "" - --#: config/arm/arm.c:1512 -+#: config/arm/arm.c:1516 - #, gcc-internal-format, gfc-internal-format - msgid "switch -mcpu=%s conflicts with -march=%s switch" - msgstr "" - --#: config/arm/arm.c:1629 -+#: config/arm/arm.c:1633 - #, fuzzy, gcc-internal-format - msgid "target CPU does not support ARM mode" - msgstr "ISO C не падтрымлівае комлексныя цэлалікавыя тыпы" - --#: config/arm/arm.c:1635 -+#: config/arm/arm.c:1639 - #, gcc-internal-format - msgid "target CPU does not support interworking" - msgstr "" - --#: config/arm/arm.c:1641 -+#: config/arm/arm.c:1645 - #, fuzzy, gcc-internal-format - msgid "target CPU does not support THUMB instructions" - msgstr "ISO C не падтрымлівае комлексныя цэлалікавыя тыпы" - --#: config/arm/arm.c:1659 -+#: config/arm/arm.c:1663 - #, gcc-internal-format - msgid "enabling backtrace support is only meaningful when compiling for the Thumb" - msgstr "" - --#: config/arm/arm.c:1662 -+#: config/arm/arm.c:1666 - #, gcc-internal-format - msgid "enabling callee interworking support is only meaningful when compiling for the Thumb" - msgstr "" - --#: config/arm/arm.c:1666 -+#: config/arm/arm.c:1670 - #, gcc-internal-format - msgid "-mapcs-stack-check incompatible with -mno-apcs-frame" - msgstr "" - --#: config/arm/arm.c:1674 -+#: config/arm/arm.c:1678 - #, gcc-internal-format - msgid "-fpic and -mapcs-reent are incompatible" - msgstr "" - --#: config/arm/arm.c:1677 -+#: config/arm/arm.c:1681 - #, gcc-internal-format - msgid "APCS reentrant code not supported. Ignored" - msgstr "" - --#: config/arm/arm.c:1685 -+#: config/arm/arm.c:1689 - #, gcc-internal-format - msgid "-g with -mno-apcs-frame may not give sensible debugging" - msgstr "" - --#: config/arm/arm.c:1688 -+#: config/arm/arm.c:1692 - #, gcc-internal-format - msgid "passing floating point arguments in fp regs not yet supported" - msgstr "" - --#: config/arm/arm.c:1691 -+#: config/arm/arm.c:1695 - #, gcc-internal-format - msgid "% is deprecated and will be removed in a future release" - msgstr "" - --#: config/arm/arm.c:1753 -+#: config/arm/arm.c:1757 - #, gcc-internal-format - msgid "iwmmxt requires an AAPCS compatible ABI for proper operation" - msgstr "" - --#: config/arm/arm.c:1756 -+#: config/arm/arm.c:1760 - #, gcc-internal-format - msgid "iwmmxt abi requires an iwmmxt capable cpu" - msgstr "" - --#: config/arm/arm.c:1804 -+#: config/arm/arm.c:1808 - #, gcc-internal-format - msgid "FPA is unsupported in the AAPCS" - msgstr "" - --#: config/arm/arm.c:1809 -+#: config/arm/arm.c:1813 - #, gcc-internal-format - msgid "AAPCS does not support -mcaller-super-interworking" - msgstr "" - --#: config/arm/arm.c:1812 -+#: config/arm/arm.c:1816 - #, gcc-internal-format - msgid "AAPCS does not support -mcallee-super-interworking" - msgstr "" - --#: config/arm/arm.c:1819 -+#: config/arm/arm.c:1823 - #, fuzzy, gcc-internal-format - #| msgid "Use hardware floating point" - msgid "iWMMXt and hardware floating point" - msgstr "Выкарыстоўваць апаратную \"плаваючую кропку\"" - --#: config/arm/arm.c:1823 -+#: config/arm/arm.c:1827 - #, gcc-internal-format - msgid "Thumb-2 iWMMXt" - msgstr "" - --#: config/arm/arm.c:1827 -+#: config/arm/arm.c:1831 - #, gcc-internal-format - msgid "__fp16 and no ldrh" - msgstr "" - --#: config/arm/arm.c:1847 -+#: config/arm/arm.c:1851 - #, gcc-internal-format - msgid "-mfloat-abi=hard and VFP" - msgstr "" - --#: config/arm/arm.c:1872 -+#: config/arm/arm.c:1876 - #, gcc-internal-format - msgid "can not use -mtp=cp15 with 16-bit Thumb" - msgstr "" - --#: config/arm/arm.c:1888 -+#: config/arm/arm.c:1892 - #, gcc-internal-format - msgid "structure size boundary can only be set to 8, 32 or 64" - msgstr "" - --#: config/arm/arm.c:1890 -+#: config/arm/arm.c:1894 - #, gcc-internal-format - msgid "structure size boundary can only be set to 8 or 32" - msgstr "" - --#: config/arm/arm.c:1898 -+#: config/arm/arm.c:1902 - #, gcc-internal-format - msgid "RTP PIC is incompatible with Thumb" - msgstr "" - --#: config/arm/arm.c:1907 -+#: config/arm/arm.c:1911 - #, gcc-internal-format - msgid "RTP PIC is incompatible with -msingle-pic-base" - msgstr "" - --#: config/arm/arm.c:1919 -+#: config/arm/arm.c:1923 - #, gcc-internal-format - msgid "-mpic-register= is useless without -fpic" - msgstr "" - --#: config/arm/arm.c:1928 -+#: config/arm/arm.c:1932 - #, gcc-internal-format, gfc-internal-format - msgid "unable to use '%s' for PIC register" - msgstr "" - --#: config/arm/arm.c:1960 -+#: config/arm/arm.c:1964 - #, fuzzy, gcc-internal-format - msgid "target CPU does not support unaligned accesses" - msgstr "ISO C не падтрымлівае комлексныя цэлалікавыя тыпы" - --#: config/arm/arm.c:1984 -+#: config/arm/arm.c:1988 - #, fuzzy, gcc-internal-format - msgid "-freorder-blocks-and-partition not supported on this architecture" - msgstr "атрыбуты секцыі не падтрымліваюцца для гэтай мэты" - --#: config/arm/arm.c:4036 -+#: config/arm/arm.c:4040 - #, gcc-internal-format - msgid "non-AAPCS derived PCS variant" - msgstr "" - --#: config/arm/arm.c:4038 -+#: config/arm/arm.c:4042 - #, gcc-internal-format - msgid "variadic functions must use the base AAPCS variant" - msgstr "" - --#: config/arm/arm.c:4057 -+#: config/arm/arm.c:4061 - #, gcc-internal-format - msgid "PCS variant" - msgstr "" - --#: config/arm/arm.c:4252 -+#: config/arm/arm.c:4256 - #, gcc-internal-format - msgid "Thumb-1 hard-float VFP ABI" - msgstr "" - --#: config/arm/arm.c:4975 config/arm/arm.c:4993 config/avr/avr.c:6783 --#: config/avr/avr.c:6799 config/bfin/bfin.c:4636 config/bfin/bfin.c:4697 --#: config/bfin/bfin.c:4726 config/h8300/h8300.c:5394 config/i386/i386.c:4894 --#: config/i386/i386.c:31799 config/i386/i386.c:31850 config/i386/i386.c:31922 -+#: config/arm/arm.c:4979 config/arm/arm.c:4997 config/avr/avr.c:6793 -+#: config/avr/avr.c:6809 config/bfin/bfin.c:4636 config/bfin/bfin.c:4697 -+#: config/bfin/bfin.c:4726 config/h8300/h8300.c:5394 config/i386/i386.c:4901 -+#: config/i386/i386.c:31929 config/i386/i386.c:31980 config/i386/i386.c:32052 - #: config/m68k/m68k.c:725 config/mcore/mcore.c:3076 config/mep/mep.c:4011 - #: config/mep/mep.c:4025 config/mep/mep.c:4099 config/rl78/rl78.c:478 --#: config/rs6000/rs6000.c:24247 config/rx/rx.c:2502 config/sh/sh.c:8902 --#: config/sh/sh.c:8920 config/sh/sh.c:8949 config/sh/sh.c:9031 --#: config/sh/sh.c:9054 config/spu/spu.c:3977 config/stormy16/stormy16.c:2200 -+#: config/rs6000/rs6000.c:24270 config/rx/rx.c:2502 config/sh/sh.c:8905 -+#: config/sh/sh.c:8923 config/sh/sh.c:8952 config/sh/sh.c:9034 -+#: config/sh/sh.c:9057 config/spu/spu.c:3977 config/stormy16/stormy16.c:2200 - #: config/v850/v850.c:2057 - #, fuzzy, gcc-internal-format - msgid "%qE attribute only applies to functions" - msgstr "\"%s\" звычайна функцыя" - --#: config/arm/arm.c:18928 -+#: config/arm/arm.c:18932 - #, gcc-internal-format - msgid "unable to compute real location of stacked parameter" - msgstr "" - --#: config/arm/arm.c:20667 -+#: config/arm/arm.c:20679 - #, fuzzy, gcc-internal-format - #| msgid "argument of `__builtin_args_info' must be constant" - msgid "argument must be a constant" - msgstr "аргумент `__builtin_args_info' павінен быць канстантай" - - #. @@@ better error message --#: config/arm/arm.c:21036 config/arm/arm.c:21073 -+#: config/arm/arm.c:21049 config/arm/arm.c:21086 - #, gcc-internal-format - msgid "selector must be an immediate" - msgstr "" - - #. @@@ better error message --#: config/arm/arm.c:21116 -+#: config/arm/arm.c:21129 - #, gcc-internal-format - msgid "mask must be an immediate" - msgstr "" - --#: config/arm/arm.c:21900 -+#: config/arm/arm.c:21913 - #, gcc-internal-format - msgid "no low registers available for popping high registers" - msgstr "" - --#: config/arm/arm.c:22125 -+#: config/arm/arm.c:22138 - #, gcc-internal-format - msgid "interrupt Service Routines cannot be coded in Thumb mode" - msgstr "" - --#: config/arm/arm.c:24411 -+#: config/arm/arm.c:24424 - #, gcc-internal-format - msgid "the mangling of % has changed in GCC 4.4" - msgstr "" -@@ -23826,87 +23826,87 @@ - msgid "%qs appears to be a misspelled %s handler" - msgstr "" - --#: config/avr/avr.c:733 -+#: config/avr/avr.c:743 - #, gcc-internal-format - msgid "'builtin_return_address' contains only 2 bytes of address" - msgstr "" - --#: config/avr/avr.c:1886 -+#: config/avr/avr.c:1896 - #, gcc-internal-format - msgid "pointer offset from symbol maybe incorrect" - msgstr "" - --#: config/avr/avr.c:2009 -+#: config/avr/avr.c:2019 - #, gcc-internal-format - msgid "accessing data memory with program memory address" - msgstr "" - --#: config/avr/avr.c:2058 -+#: config/avr/avr.c:2068 - #, gcc-internal-format - msgid "accessing program memory with data memory address" - msgstr "" - --#: config/avr/avr.c:2464 -+#: config/avr/avr.c:2474 - #, gcc-internal-format, gfc-internal-format - msgid "fixed register %s used to pass parameter to function" - msgstr "" - --#: config/avr/avr.c:2586 -+#: config/avr/avr.c:2596 - #, gcc-internal-format - msgid "writing to address space %qs not supported" - msgstr "" - --#: config/avr/avr.c:6977 -+#: config/avr/avr.c:6987 - #, gcc-internal-format - msgid "%qT uses address space %qs beyond flash of %qs" - msgstr "" - --#: config/avr/avr.c:6980 -+#: config/avr/avr.c:6990 - #, gcc-internal-format - msgid "%s %q+D uses address space %qs beyond flash of %qs" - msgstr "" - --#: config/avr/avr.c:6987 -+#: config/avr/avr.c:6997 - #, gcc-internal-format - msgid "pointer targeting address space %qs must be const in %qT" - msgstr "" - --#: config/avr/avr.c:6990 -+#: config/avr/avr.c:7000 - #, gcc-internal-format - msgid "pointer targeting address space %qs must be const in %s %q+D" - msgstr "" - --#: config/avr/avr.c:7028 -+#: config/avr/avr.c:7038 - #, gcc-internal-format - msgid "variable %q+D located in address space %qs beyond flash of %qs" - msgstr "" - --#: config/avr/avr.c:7044 -+#: config/avr/avr.c:7054 - #, gcc-internal-format - msgid "variable %q+D must be const in order to be put into read-only section by means of %qs" - msgstr "" - --#: config/avr/avr.c:7258 -+#: config/avr/avr.c:7268 - #, gcc-internal-format - msgid "only uninitialized variables can be placed in the .noinit section" - msgstr "" - --#: config/avr/avr.c:7299 -+#: config/avr/avr.c:7309 - #, gcc-internal-format - msgid "uninitialized variable %q+D put into program memory area" - msgstr "" - --#: config/avr/avr.c:7366 -+#: config/avr/avr.c:7376 - #, gcc-internal-format - msgid "MCU %qs supported for assembler only" - msgstr "" - --#: config/avr/avr.c:10628 -+#: config/avr/avr.c:10660 - #, gcc-internal-format, gfc-internal-format - msgid "%s expects a compile time integer constant" - msgstr "" - --#: config/avr/avr.c:10642 -+#: config/avr/avr.c:10674 - #, gcc-internal-format, gfc-internal-format - msgid "%s expects a compile time long integer constant as first argument" - msgstr "" -@@ -24250,412 +24250,412 @@ - msgid "can%'t set position in PCH file: %m" - msgstr "немагчыма зачыніць уваходзячы файл %s" - --#: config/i386/i386.c:3130 config/i386/i386.c:3434 -+#: config/i386/i386.c:3135 config/i386/i386.c:3441 - #, gcc-internal-format, gfc-internal-format - msgid "bad value (%s) for %stune=%s %s" - msgstr "" - --#: config/i386/i386.c:3133 -+#: config/i386/i386.c:3138 - #, gcc-internal-format, gfc-internal-format - msgid "%stune=x86-64%s is deprecated; use %stune=k8%s or %stune=generic%s instead as appropriate" - msgstr "" - - #. rep; movq isn't available in 32-bit code. --#: config/i386/i386.c:3163 -+#: config/i386/i386.c:3168 - #, gcc-internal-format - msgid "-mstringop-strategy=rep_8byte not supported for 32-bit code" - msgstr "" - --#: config/i386/i386.c:3184 config/i386/i386.c:3193 config/i386/i386.c:3205 --#: config/i386/i386.c:3216 config/i386/i386.c:3227 -+#: config/i386/i386.c:3189 config/i386/i386.c:3198 config/i386/i386.c:3210 -+#: config/i386/i386.c:3221 config/i386/i386.c:3232 - #, fuzzy, gcc-internal-format - msgid "code model %qs not supported in the %s bit mode" - msgstr "__buitin_saveregs не падтрымліваецца гэтай мэтай" - --#: config/i386/i386.c:3196 config/i386/i386.c:3208 -+#: config/i386/i386.c:3201 config/i386/i386.c:3213 - #, fuzzy, gcc-internal-format - msgid "code model %qs not supported in x32 mode" - msgstr "-pipe не падтрымліваецца" - --#: config/i386/i386.c:3214 config/i386/i386.c:3223 -+#: config/i386/i386.c:3219 config/i386/i386.c:3228 - #, fuzzy, gcc-internal-format, gfc-internal-format - #| msgid "%s does not support %s" - msgid "code model %s does not support PIC mode" - msgstr "%s не падтрымлівае %s" - --#: config/i386/i386.c:3250 -+#: config/i386/i386.c:3255 - #, fuzzy, gcc-internal-format - msgid "-masm=intel not supported in this configuration" - msgstr "атрыбуты секцыі не падтрымліваюцца для гэтай мэты" - --#: config/i386/i386.c:3254 -+#: config/i386/i386.c:3259 - #, gcc-internal-format, gfc-internal-format - msgid "%i-bit mode not compiled in" - msgstr "" - --#: config/i386/i386.c:3266 config/i386/i386.c:3396 -+#: config/i386/i386.c:3271 config/i386/i386.c:3403 - #, fuzzy, gcc-internal-format - msgid "CPU you selected does not support x86-64 instruction set" - msgstr "ISO C не падтрымлівае комлексныя цэлалікавыя тыпы" - --#: config/i386/i386.c:3366 -+#: config/i386/i386.c:3373 - #, gcc-internal-format, gfc-internal-format - msgid "generic CPU can be used only for %stune=%s %s" - msgstr "" - --#: config/i386/i386.c:3369 -+#: config/i386/i386.c:3376 - #, gcc-internal-format, gfc-internal-format - msgid "bad value (%s) for %sarch=%s %s" - msgstr "" - --#: config/i386/i386.c:3482 -+#: config/i386/i386.c:3489 - #, gcc-internal-format - msgid "-mregparm is ignored in 64-bit mode" - msgstr "" - --#: config/i386/i386.c:3485 -+#: config/i386/i386.c:3492 - #, gcc-internal-format, gfc-internal-format - msgid "-mregparm=%d is not between 0 and %d" - msgstr "" - --#: config/i386/i386.c:3526 -+#: config/i386/i386.c:3533 - #, gcc-internal-format, gfc-internal-format - msgid "%srtd%s is ignored in 64bit mode" - msgstr "" - --#: config/i386/i386.c:3590 -+#: config/i386/i386.c:3597 - #, fuzzy, gcc-internal-format - msgid "-mpreferred-stack-boundary is not supported for this target" - msgstr "атрыбуты секцыі не падтрымліваюцца для гэтай мэты" - --#: config/i386/i386.c:3593 -+#: config/i386/i386.c:3600 - #, gcc-internal-format, gfc-internal-format - msgid "-mpreferred-stack-boundary=%d is not between %d and %d" - msgstr "" - --#: config/i386/i386.c:3614 -+#: config/i386/i386.c:3621 - #, gcc-internal-format, gfc-internal-format - msgid "-mincoming-stack-boundary=%d is not between %d and 12" - msgstr "" - --#: config/i386/i386.c:3628 -+#: config/i386/i386.c:3635 - #, gcc-internal-format, gfc-internal-format - msgid "%ssseregparm%s used without SSE enabled" - msgstr "" - --#: config/i386/i386.c:3636 -+#: config/i386/i386.c:3643 - #, gcc-internal-format - msgid "SSE instruction set disabled, using 387 arithmetics" - msgstr "" - --#: config/i386/i386.c:3641 -+#: config/i386/i386.c:3648 - #, gcc-internal-format - msgid "387 instruction set disabled, using SSE arithmetics" - msgstr "" - --#: config/i386/i386.c:3685 -+#: config/i386/i386.c:3692 - #, gcc-internal-format, gfc-internal-format - msgid "unwind tables currently require either a frame pointer or %saccumulate-outgoing-args%s for correctness" - msgstr "" - --#: config/i386/i386.c:3698 -+#: config/i386/i386.c:3705 - #, gcc-internal-format, gfc-internal-format - msgid "stack probing requires %saccumulate-outgoing-args%s for correctness" - msgstr "" - --#: config/i386/i386.c:3779 -+#: config/i386/i386.c:3786 - #, gcc-internal-format - msgid "-mfentry isn%'t supported for 32-bit in combination with -fpic" - msgstr "" - --#: config/i386/i386.c:3786 -+#: config/i386/i386.c:3793 - #, gcc-internal-format - msgid "-mno-fentry isn%'t compatible with SEH" - msgstr "" - --#: config/i386/i386.c:3856 config/rs6000/rs6000.c:3331 -+#: config/i386/i386.c:3863 config/rs6000/rs6000.c:3330 - #, fuzzy, gcc-internal-format, gfc-internal-format - msgid "unknown option for -mrecip=%s" - msgstr "невядомая назва рэгістра: %s\n" - --#: config/i386/i386.c:4271 config/i386/i386.c:4318 -+#: config/i386/i386.c:4278 config/i386/i386.c:4325 - #, gcc-internal-format, gfc-internal-format - msgid "attribute(target(\"%s\")) is unknown" - msgstr "" - --#: config/i386/i386.c:4299 -+#: config/i386/i386.c:4306 - #, gcc-internal-format, gfc-internal-format - msgid "option(\"%s\") was already specified" - msgstr "" - --#: config/i386/i386.c:4907 config/i386/i386.c:4958 -+#: config/i386/i386.c:4914 config/i386/i386.c:4965 - #, gcc-internal-format - msgid "fastcall and regparm attributes are not compatible" - msgstr "" - --#: config/i386/i386.c:4912 -+#: config/i386/i386.c:4919 - #, gcc-internal-format - msgid "regparam and thiscall attributes are not compatible" - msgstr "" - --#: config/i386/i386.c:4919 config/i386/i386.c:31819 -+#: config/i386/i386.c:4926 config/i386/i386.c:31949 - #, gcc-internal-format - msgid "%qE attribute requires an integer constant argument" - msgstr "" - --#: config/i386/i386.c:4925 -+#: config/i386/i386.c:4932 - #, fuzzy, gcc-internal-format - msgid "argument to %qE attribute larger than %d" - msgstr "памер \"%s\" больш чам %d байт" - --#: config/i386/i386.c:4950 config/i386/i386.c:4993 -+#: config/i386/i386.c:4957 config/i386/i386.c:5000 - #, gcc-internal-format - msgid "fastcall and cdecl attributes are not compatible" - msgstr "" - --#: config/i386/i386.c:4954 -+#: config/i386/i386.c:4961 - #, gcc-internal-format - msgid "fastcall and stdcall attributes are not compatible" - msgstr "" - --#: config/i386/i386.c:4962 config/i386/i386.c:5011 -+#: config/i386/i386.c:4969 config/i386/i386.c:5018 - #, gcc-internal-format - msgid "fastcall and thiscall attributes are not compatible" - msgstr "" - --#: config/i386/i386.c:4972 config/i386/i386.c:4989 -+#: config/i386/i386.c:4979 config/i386/i386.c:4996 - #, gcc-internal-format - msgid "stdcall and cdecl attributes are not compatible" - msgstr "" - --#: config/i386/i386.c:4976 -+#: config/i386/i386.c:4983 - #, gcc-internal-format - msgid "stdcall and fastcall attributes are not compatible" - msgstr "" - --#: config/i386/i386.c:4980 config/i386/i386.c:5007 -+#: config/i386/i386.c:4987 config/i386/i386.c:5014 - #, gcc-internal-format - msgid "stdcall and thiscall attributes are not compatible" - msgstr "" - --#: config/i386/i386.c:4997 config/i386/i386.c:5015 -+#: config/i386/i386.c:5004 config/i386/i386.c:5022 - #, gcc-internal-format - msgid "cdecl and thiscall attributes are not compatible" - msgstr "" - --#: config/i386/i386.c:5003 -+#: config/i386/i386.c:5010 - #, gcc-internal-format - msgid "%qE attribute is used for none class-method" - msgstr "" - --#: config/i386/i386.c:5229 -+#: config/i386/i386.c:5236 - #, gcc-internal-format - msgid "calling %qD with attribute sseregparm without SSE/SSE2 enabled" - msgstr "" - --#: config/i386/i386.c:5232 -+#: config/i386/i386.c:5239 - #, gcc-internal-format - msgid "calling %qT with attribute sseregparm without SSE/SSE2 enabled" - msgstr "" - --#: config/i386/i386.c:5447 -+#: config/i386/i386.c:5454 - #, gcc-internal-format - msgid "ms_hook_prologue is not compatible with nested function" - msgstr "" - --#: config/i386/i386.c:5599 -+#: config/i386/i386.c:5606 - #, gcc-internal-format - msgid "ms_abi attribute requires -maccumulate-outgoing-args or subtarget optimization implying it" - msgstr "" - --#: config/i386/i386.c:5723 -+#: config/i386/i386.c:5730 - #, gcc-internal-format - msgid "AVX vector argument without AVX enabled changes the ABI" - msgstr "" - --#: config/i386/i386.c:5905 -+#: config/i386/i386.c:5912 - #, gcc-internal-format - msgid "the ABI of passing struct with a flexible array member has changed in GCC 4.4" - msgstr "" - --#: config/i386/i386.c:6021 -+#: config/i386/i386.c:6028 - #, gcc-internal-format - msgid "the ABI of passing union with long double has changed in GCC 4.4" - msgstr "" - --#: config/i386/i386.c:6136 -+#: config/i386/i386.c:6143 - #, gcc-internal-format - msgid "the ABI of passing structure with complex float member has changed in GCC 4.4" - msgstr "" - --#: config/i386/i386.c:6282 -+#: config/i386/i386.c:6289 - #, gcc-internal-format - msgid "SSE register return with SSE disabled" - msgstr "" - --#: config/i386/i386.c:6288 -+#: config/i386/i386.c:6295 - #, gcc-internal-format - msgid "SSE register argument with SSE disabled" - msgstr "" - --#: config/i386/i386.c:6304 -+#: config/i386/i386.c:6311 - #, gcc-internal-format - msgid "x87 register return with x87 disabled" - msgstr "" - --#: config/i386/i386.c:6683 -+#: config/i386/i386.c:6690 - #, gcc-internal-format - msgid "SSE vector argument without SSE enabled changes the ABI" - msgstr "" - --#: config/i386/i386.c:6721 -+#: config/i386/i386.c:6728 - #, gcc-internal-format - msgid "MMX vector argument without MMX enabled changes the ABI" - msgstr "" - --#: config/i386/i386.c:7096 -+#: config/i386/i386.c:7103 - #, gcc-internal-format, gfc-internal-format - msgid "The ABI for passing parameters with %d-byte alignment has changed in GCC 4.6" - msgstr "" - --#: config/i386/i386.c:7432 -+#: config/i386/i386.c:7439 - #, gcc-internal-format - msgid "SSE vector return without SSE enabled changes the ABI" - msgstr "" - --#: config/i386/i386.c:7442 -+#: config/i386/i386.c:7449 - #, gcc-internal-format - msgid "MMX vector return without MMX enabled changes the ABI" - msgstr "" - --#: config/i386/i386.c:10028 -+#: config/i386/i386.c:10049 - #, gcc-internal-format - msgid "ms_hook_prologue attribute isn%'t compatible with -mfentry for 32-bit" - msgstr "" - --#: config/i386/i386.c:11025 -+#: config/i386/i386.c:11084 - #, gcc-internal-format - msgid "-fsplit-stack does not support fastcall with nested function" - msgstr "" - --#: config/i386/i386.c:11039 -+#: config/i386/i386.c:11098 - #, gcc-internal-format - msgid "-fsplit-stack does not support 2 register parameters for a nested function" - msgstr "" - - #. FIXME: We could make this work by pushing a register - #. around the addition and comparison. --#: config/i386/i386.c:11050 -+#: config/i386/i386.c:11109 - #, gcc-internal-format - msgid "-fsplit-stack does not support 3 register parameters" - msgstr "" - --#: config/i386/i386.c:13637 -+#: config/i386/i386.c:13731 - #, gcc-internal-format - msgid "extended registers have no high halves" - msgstr "" - --#: config/i386/i386.c:13652 -+#: config/i386/i386.c:13746 - #, gcc-internal-format - msgid "unsupported operand size for extended register" - msgstr "" - --#: config/i386/i386.c:13899 -+#: config/i386/i386.c:14001 - #, gcc-internal-format, gfc-internal-format - msgid "non-integer operand used with operand code '%c'" - msgstr "" - --#: config/i386/i386.c:27790 config/i386/i386.c:28727 -+#: config/i386/i386.c:27920 config/i386/i386.c:28857 - #, fuzzy, gcc-internal-format - msgid "the last argument must be a 2-bit immediate" - msgstr "першым аргументам \"%s\" павінен быць \"int\"" - --#: config/i386/i386.c:28196 -+#: config/i386/i386.c:28326 - #, fuzzy, gcc-internal-format - msgid "the fifth argument must be an 8-bit immediate" - msgstr "першым аргументам \"%s\" павінен быць \"int\"" - --#: config/i386/i386.c:28291 -+#: config/i386/i386.c:28421 - #, fuzzy, gcc-internal-format - msgid "the third argument must be an 8-bit immediate" - msgstr "першым аргументам \"%s\" павінен быць \"int\"" - --#: config/i386/i386.c:28699 -+#: config/i386/i386.c:28829 - #, fuzzy, gcc-internal-format - msgid "the last argument must be an 1-bit immediate" - msgstr "першым аргументам \"%s\" павінен быць \"int\"" - --#: config/i386/i386.c:28718 -+#: config/i386/i386.c:28848 - #, fuzzy, gcc-internal-format - msgid "the last argument must be a 4-bit immediate" - msgstr "першым аргументам \"%s\" павінен быць \"int\"" - --#: config/i386/i386.c:28736 -+#: config/i386/i386.c:28866 - #, fuzzy, gcc-internal-format - msgid "the last argument must be a 1-bit immediate" - msgstr "першым аргументам \"%s\" павінен быць \"int\"" - --#: config/i386/i386.c:28745 -+#: config/i386/i386.c:28875 - #, fuzzy, gcc-internal-format - msgid "the last argument must be a 5-bit immediate" - msgstr "першым аргументам \"%s\" павінен быць \"int\"" - --#: config/i386/i386.c:28754 -+#: config/i386/i386.c:28884 - #, gcc-internal-format - msgid "the next to last argument must be an 8-bit immediate" - msgstr "" - --#: config/i386/i386.c:28758 config/i386/i386.c:28982 -+#: config/i386/i386.c:28888 config/i386/i386.c:29112 - #, fuzzy, gcc-internal-format - msgid "the last argument must be an 8-bit immediate" - msgstr "першым аргументам \"%s\" павінен быць \"int\"" - --#: config/i386/i386.c:28980 -+#: config/i386/i386.c:29110 - #, fuzzy, gcc-internal-format - msgid "the last argument must be a 32-bit immediate" - msgstr "першым аргументам \"%s\" павінен быць \"int\"" - --#: config/i386/i386.c:29048 config/rs6000/rs6000.c:10551 -+#: config/i386/i386.c:29178 config/rs6000/rs6000.c:10550 - #, gcc-internal-format - msgid "selector must be an integer constant in the range 0..%wi" - msgstr "" - --#: config/i386/i386.c:29191 -+#: config/i386/i386.c:29321 - #, gcc-internal-format - msgid "%qE needs unknown isa option" - msgstr "" - --#: config/i386/i386.c:29195 -+#: config/i386/i386.c:29325 - #, fuzzy, gcc-internal-format - msgid "%qE needs isa option %s" - msgstr "Нерэчаісны выбар %s" - --#: config/i386/i386.c:29366 -+#: config/i386/i386.c:29496 - #, fuzzy, gcc-internal-format - msgid "last argument must be an immediate" - msgstr "першым аргументам \"%s\" павінен быць \"int\"" - --#: config/i386/i386.c:29560 -+#: config/i386/i386.c:29690 - #, gcc-internal-format - msgid "last argument must be scale 1, 2, 4, 8" - msgstr "" - --#: config/i386/i386.c:31806 -+#: config/i386/i386.c:31936 - #, fuzzy, gcc-internal-format - msgid "%qE attribute only available for 32-bit" - msgstr "\"%s\" атрыбут ігнарыруецца" - --#: config/i386/i386.c:31827 -+#: config/i386/i386.c:31957 - #, fuzzy, gcc-internal-format - msgid "argument to %qE attribute is neither zero, nor one" - msgstr "аргумент `__builtin_args_info' павінен быць канстантай" - --#: config/i386/i386.c:31861 config/i386/i386.c:31870 -+#: config/i386/i386.c:31991 config/i386/i386.c:32000 - #, gcc-internal-format - msgid "ms_abi and sysv_abi attributes are not compatible" - msgstr "" - --#: config/i386/i386.c:31907 config/rs6000/rs6000.c:24330 -+#: config/i386/i386.c:32037 config/rs6000/rs6000.c:24353 - #, fuzzy, gcc-internal-format - #| msgid "`%s' attribute ignored" - msgid "%qE incompatible attribute ignored" -@@ -24727,13 +24727,13 @@ - msgid "%qE attribute requires a string constant argument" - msgstr "аргумент `__builtin_args_info' павінен быць канстантай" - --#: config/ia64/ia64.c:5741 config/pa/pa.c:415 config/sh/sh.c:8750 -+#: config/ia64/ia64.c:5741 config/pa/pa.c:415 config/sh/sh.c:8753 - #: config/spu/spu.c:5187 - #, gcc-internal-format - msgid "value of -mfixed-range must have form REG1-REG2" - msgstr "" - --#: config/ia64/ia64.c:5768 config/pa/pa.c:442 config/sh/sh.c:8776 -+#: config/ia64/ia64.c:5768 config/pa/pa.c:442 config/sh/sh.c:8779 - #: config/spu/spu.c:5213 - #, gcc-internal-format, gfc-internal-format - msgid "%s-%s is an empty range" -@@ -24807,7 +24807,7 @@ - msgstr "атрыбуты секцыі не падтрымліваюцца для гэтай мэты" - - #. The argument must be a constant integer. --#: config/m32c/m32c.c:3169 config/sh/sh.c:8957 config/sh/sh.c:9063 -+#: config/m32c/m32c.c:3169 config/sh/sh.c:8960 config/sh/sh.c:9066 - #, fuzzy, gcc-internal-format - msgid "%qE attribute argument not an integer constant" - msgstr "аргумент `__builtin_args_info' павінен быць канстантай" -@@ -24864,7 +24864,7 @@ - msgid "interrupt_thread is available only on fido" - msgstr "" - --#: config/m68k/m68k.c:1072 config/rs6000/rs6000.c:18607 -+#: config/m68k/m68k.c:1072 config/rs6000/rs6000.c:18606 - #, gcc-internal-format - msgid "stack limit expression is not supported" - msgstr "" -@@ -25209,63 +25209,63 @@ - msgid "%qs does not support MIPS16 code" - msgstr "%s не падтрымлівае %s" - --#: config/mips/mips.c:15623 -+#: config/mips/mips.c:15629 - #, gcc-internal-format - msgid "MIPS16 PIC for ABIs other than o32 and o64" - msgstr "" - --#: config/mips/mips.c:15626 -+#: config/mips/mips.c:15632 - #, gcc-internal-format - msgid "MIPS16 -mxgot code" - msgstr "" - --#: config/mips/mips.c:15629 -+#: config/mips/mips.c:15635 - #, gcc-internal-format - msgid "hard-float MIPS16 code for ABIs other than o32 and o64" - msgstr "" - --#: config/mips/mips.c:15818 -+#: config/mips/mips.c:15824 - #, gcc-internal-format - msgid "%<-%s%> conflicts with the other architecture options, which specify a %s processor" - msgstr "" - --#: config/mips/mips.c:15828 -+#: config/mips/mips.c:15834 - #, gcc-internal-format - msgid "%<-march=%s%> is not compatible with the selected ABI" - msgstr "" - --#: config/mips/mips.c:15843 -+#: config/mips/mips.c:15849 - #, gcc-internal-format - msgid "%<-mgp64%> used with a 32-bit processor" - msgstr "" - --#: config/mips/mips.c:15845 -+#: config/mips/mips.c:15851 - #, gcc-internal-format - msgid "%<-mgp32%> used with a 64-bit ABI" - msgstr "" - --#: config/mips/mips.c:15847 -+#: config/mips/mips.c:15853 - #, gcc-internal-format - msgid "%<-mgp64%> used with a 32-bit ABI" - msgstr "" - --#: config/mips/mips.c:15863 config/mips/mips.c:15865 config/mips/mips.c:15956 -+#: config/mips/mips.c:15869 config/mips/mips.c:15871 config/mips/mips.c:15962 - #, fuzzy, gcc-internal-format, gfc-internal-format - #| msgid "unsupported version" - msgid "unsupported combination: %s" - msgstr "непадтрымліваемая версія" - --#: config/mips/mips.c:15869 -+#: config/mips/mips.c:15875 - #, gcc-internal-format - msgid "%<-mgp32%> and %<-mfp64%> can only be combined if the target supports the mfhc1 and mthc1 instructions" - msgstr "" - --#: config/mips/mips.c:15872 -+#: config/mips/mips.c:15878 - #, gcc-internal-format - msgid "%<-mgp32%> and %<-mfp64%> can only be combined when using the o32 ABI" - msgstr "" - --#: config/mips/mips.c:15895 config/mips/mips.c:15897 config/mips/mips.c:15910 -+#: config/mips/mips.c:15901 config/mips/mips.c:15903 config/mips/mips.c:15916 - #, gcc-internal-format - msgid "%qs is incompatible with %qs" - msgstr "" -@@ -25275,57 +25275,57 @@ - #. effort to support the combination of 32-bit GOT entries - #. and 64-bit pointers, so we treat the abicalls case as - #. an error. --#: config/mips/mips.c:15904 -+#: config/mips/mips.c:15910 - #, gcc-internal-format - msgid "the combination of %qs and %qs is incompatible with %qs" - msgstr "" - --#: config/mips/mips.c:15950 -+#: config/mips/mips.c:15956 - #, fuzzy, gcc-internal-format - msgid "the %qs architecture does not support branch-likely instructions" - msgstr "ISO C не падтрымлівае комлексныя цэлалікавыя тыпы" - --#: config/mips/mips.c:15990 -+#: config/mips/mips.c:15996 - #, gcc-internal-format - msgid "%<-mno-gpopt%> needs %<-mexplicit-relocs%>" - msgstr "" - --#: config/mips/mips.c:15998 config/mips/mips.c:16001 -+#: config/mips/mips.c:16004 config/mips/mips.c:16007 - #, gcc-internal-format - msgid "cannot use small-data accesses for %qs" - msgstr "" - --#: config/mips/mips.c:16015 -+#: config/mips/mips.c:16021 - #, gcc-internal-format - msgid "%<-mips3d%> requires %<-mpaired-single%>" - msgstr "" - --#: config/mips/mips.c:16024 -+#: config/mips/mips.c:16030 - #, gcc-internal-format - msgid "%qs must be used with %qs" - msgstr "" - --#: config/mips/mips.c:16031 -+#: config/mips/mips.c:16037 - #, fuzzy, gcc-internal-format - msgid "the %qs architecture does not support paired-single instructions" - msgstr "ISO C не падтрымлівае комлексныя цэлалікавыя тыпы" - --#: config/mips/mips.c:16037 -+#: config/mips/mips.c:16043 - #, gcc-internal-format - msgid "%qs requires a target that provides the %qs instruction" - msgstr "" - --#: config/mips/mips.c:16142 -+#: config/mips/mips.c:16148 - #, fuzzy, gcc-internal-format - msgid "%qs requires branch-likely instructions" - msgstr "Не генерыраваць сімвальныя інструкцыі" - --#: config/mips/mips.c:16146 -+#: config/mips/mips.c:16152 - #, fuzzy, gcc-internal-format - msgid "the %qs architecture does not support the synci instruction" - msgstr "ISO C не падтрымлівае комлексныя цэлалікавыя тыпы" - --#: config/mips/mips.c:16596 -+#: config/mips/mips.c:16602 - #, gcc-internal-format - msgid "mips16 function profiling" - msgstr "" -@@ -25610,308 +25610,308 @@ - msgid "invalid parameter combination for AltiVec intrinsic" - msgstr "нявернае выкарыстанне \"restict\"" - --#: config/rs6000/rs6000.c:2436 -+#: config/rs6000/rs6000.c:2435 - #, gcc-internal-format - msgid "-mrecip requires -ffinite-math or -ffast-math" - msgstr "" - --#: config/rs6000/rs6000.c:2438 -+#: config/rs6000/rs6000.c:2437 - #, gcc-internal-format - msgid "-mrecip requires -fno-trapping-math or -ffast-math" - msgstr "" - --#: config/rs6000/rs6000.c:2440 -+#: config/rs6000/rs6000.c:2439 - #, gcc-internal-format - msgid "-mrecip requires -freciprocal-math or -ffast-math" - msgstr "" - --#: config/rs6000/rs6000.c:2535 -+#: config/rs6000/rs6000.c:2534 - #, gcc-internal-format - msgid "-m64 requires PowerPC64 architecture, enabling" - msgstr "" - --#: config/rs6000/rs6000.c:2616 -+#: config/rs6000/rs6000.c:2615 - #, gcc-internal-format - msgid "-malign-power is not supported for 64-bit Darwin; it is incompatible with the installed C and C++ libraries" - msgstr "" - --#: config/rs6000/rs6000.c:2622 -+#: config/rs6000/rs6000.c:2621 - #, gcc-internal-format - msgid "not configured for SPE ABI" - msgstr "" - --#: config/rs6000/rs6000.c:2710 -+#: config/rs6000/rs6000.c:2709 - #, fuzzy, gcc-internal-format - msgid "AltiVec not supported in this target" - msgstr "__buitin_saveregs не падтрымліваецца гэтай мэтай" - --#: config/rs6000/rs6000.c:2712 -+#: config/rs6000/rs6000.c:2711 - #, fuzzy, gcc-internal-format - msgid "SPE not supported in this target" - msgstr "__buitin_saveregs не падтрымліваецца гэтай мэтай" - --#: config/rs6000/rs6000.c:2739 -+#: config/rs6000/rs6000.c:2738 - #, gcc-internal-format - msgid "-mmultiple is not supported on little endian systems" - msgstr "" - --#: config/rs6000/rs6000.c:2746 -+#: config/rs6000/rs6000.c:2745 - #, gcc-internal-format - msgid "-mstring is not supported on little endian systems" - msgstr "" - --#: config/rs6000/rs6000.c:2852 -+#: config/rs6000/rs6000.c:2851 - #, gcc-internal-format, gfc-internal-format - msgid "unknown vectorization library ABI type (%s) for -mveclibabi= switch" - msgstr "" - --#: config/rs6000/rs6000.c:2864 -+#: config/rs6000/rs6000.c:2863 - #, gcc-internal-format - msgid "target attribute or pragma changes long double size" - msgstr "" - --#: config/rs6000/rs6000.c:2885 config/rs6000/rs6000.c:2900 -+#: config/rs6000/rs6000.c:2884 config/rs6000/rs6000.c:2899 - #, gcc-internal-format - msgid "target attribute or pragma changes AltiVec ABI" - msgstr "" - --#: config/rs6000/rs6000.c:2917 -+#: config/rs6000/rs6000.c:2916 - #, gcc-internal-format - msgid "target attribute or pragma changes darwin64 ABI" - msgstr "" - --#: config/rs6000/rs6000.c:2958 -+#: config/rs6000/rs6000.c:2957 - #, gcc-internal-format - msgid "target attribute or pragma changes SPE ABI" - msgstr "" - --#: config/rs6000/rs6000.c:3281 -+#: config/rs6000/rs6000.c:3280 - #, gcc-internal-format - msgid "target attribute or pragma changes single precision floating point" - msgstr "" - --#: config/rs6000/rs6000.c:3284 -+#: config/rs6000/rs6000.c:3283 - #, gcc-internal-format - msgid "target attribute or pragma changes double precision floating point" - msgstr "" - --#: config/rs6000/rs6000.c:7420 -+#: config/rs6000/rs6000.c:7419 - #, gcc-internal-format - msgid "GCC vector returned by reference: non-standard ABI extension with no compatibility guarantee" - msgstr "" - --#: config/rs6000/rs6000.c:7561 -+#: config/rs6000/rs6000.c:7560 - #, gcc-internal-format - msgid "cannot return value in vector register because altivec instructions are disabled, use -maltivec to enable them" - msgstr "" - --#: config/rs6000/rs6000.c:7904 -+#: config/rs6000/rs6000.c:7903 - #, gcc-internal-format - msgid "cannot pass argument in vector register because altivec instructions are disabled, use -maltivec to enable them" - msgstr "" - --#: config/rs6000/rs6000.c:8830 -+#: config/rs6000/rs6000.c:8829 - #, gcc-internal-format - msgid "GCC vector passed by reference: non-standard ABI extension with no compatibility guarantee" - msgstr "" - --#: config/rs6000/rs6000.c:9459 -+#: config/rs6000/rs6000.c:9458 - #, gcc-internal-format, gfc-internal-format - msgid "internal error: builtin function %s already processed" - msgstr "" - --#: config/rs6000/rs6000.c:9832 -+#: config/rs6000/rs6000.c:9831 - #, fuzzy, gcc-internal-format - msgid "argument 1 must be a 5-bit signed literal" - msgstr "першым аргументам \"%s\" павінен быць \"int\"" - --#: config/rs6000/rs6000.c:9935 config/rs6000/rs6000.c:10952 -+#: config/rs6000/rs6000.c:9934 config/rs6000/rs6000.c:10951 - #, fuzzy, gcc-internal-format - msgid "argument 2 must be a 5-bit unsigned literal" - msgstr "першым аргументам \"%s\" павінен быць \"int\"" - --#: config/rs6000/rs6000.c:9974 -+#: config/rs6000/rs6000.c:9973 - #, fuzzy, gcc-internal-format - msgid "argument 1 of __builtin_altivec_predicate must be a constant" - msgstr "аргумент `__builtin_args_info' павінен быць канстантай" - --#: config/rs6000/rs6000.c:10026 -+#: config/rs6000/rs6000.c:10025 - #, fuzzy, gcc-internal-format - msgid "argument 1 of __builtin_altivec_predicate is out of range" - msgstr "аргумент `__builtin_args_info' выйшаў за межы" - --#: config/rs6000/rs6000.c:10283 -+#: config/rs6000/rs6000.c:10282 - #, fuzzy, gcc-internal-format - msgid "argument 3 must be a 4-bit unsigned literal" - msgstr "першым аргументам \"%s\" павінен быць \"int\"" - --#: config/rs6000/rs6000.c:10301 -+#: config/rs6000/rs6000.c:10300 - #, fuzzy, gcc-internal-format - msgid "argument 3 must be a 2-bit unsigned literal" - msgstr "першым аргументам \"%s\" павінен быць \"int\"" - --#: config/rs6000/rs6000.c:10313 -+#: config/rs6000/rs6000.c:10312 - #, fuzzy, gcc-internal-format - msgid "argument 3 must be a 1-bit unsigned literal" - msgstr "першым аргументам \"%s\" павінен быць \"int\"" - --#: config/rs6000/rs6000.c:10496 -+#: config/rs6000/rs6000.c:10495 - #, fuzzy, gcc-internal-format - msgid "argument to %qs must be a 2-bit unsigned literal" - msgstr "першым аргументам \"%s\" павінен быць \"int\"" - --#: config/rs6000/rs6000.c:10637 -+#: config/rs6000/rs6000.c:10636 - #, gcc-internal-format - msgid "unresolved overload for Altivec builtin %qF" - msgstr "" - --#: config/rs6000/rs6000.c:10743 -+#: config/rs6000/rs6000.c:10742 - #, fuzzy, gcc-internal-format - msgid "argument to dss must be a 2-bit unsigned literal" - msgstr "першым аргументам \"%s\" павінен быць \"int\"" - --#: config/rs6000/rs6000.c:11072 -+#: config/rs6000/rs6000.c:11071 - #, fuzzy, gcc-internal-format - msgid "argument 1 of __builtin_paired_predicate must be a constant" - msgstr "аргумент `__builtin_args_info' павінен быць канстантай" - --#: config/rs6000/rs6000.c:11119 -+#: config/rs6000/rs6000.c:11118 - #, fuzzy, gcc-internal-format - msgid "argument 1 of __builtin_paired_predicate is out of range" - msgstr "аргумент `__builtin_args_info' выйшаў за межы" - --#: config/rs6000/rs6000.c:11144 -+#: config/rs6000/rs6000.c:11143 - #, fuzzy, gcc-internal-format - msgid "argument 1 of __builtin_spe_predicate must be a constant" - msgstr "аргумент `__builtin_args_info' павінен быць канстантай" - --#: config/rs6000/rs6000.c:11216 -+#: config/rs6000/rs6000.c:11215 - #, fuzzy, gcc-internal-format - msgid "argument 1 of __builtin_spe_predicate is out of range" - msgstr "аргумент `__builtin_args_info' выйшаў за межы" - --#: config/rs6000/rs6000.c:11298 -+#: config/rs6000/rs6000.c:11297 - #, gcc-internal-format, gfc-internal-format - msgid "Builtin function %s is only valid for the cell processor" - msgstr "" - --#: config/rs6000/rs6000.c:11300 -+#: config/rs6000/rs6000.c:11299 - #, gcc-internal-format, gfc-internal-format - msgid "Builtin function %s requires the -mvsx option" - msgstr "" - --#: config/rs6000/rs6000.c:11302 -+#: config/rs6000/rs6000.c:11301 - #, gcc-internal-format, gfc-internal-format - msgid "Builtin function %s requires the -maltivec option" - msgstr "" - --#: config/rs6000/rs6000.c:11304 -+#: config/rs6000/rs6000.c:11303 - #, gcc-internal-format, gfc-internal-format - msgid "Builtin function %s requires the -mpaired option" - msgstr "" - --#: config/rs6000/rs6000.c:11306 -+#: config/rs6000/rs6000.c:11305 - #, gcc-internal-format, gfc-internal-format - msgid "Builtin function %s requires the -mspe option" - msgstr "" - --#: config/rs6000/rs6000.c:11308 -+#: config/rs6000/rs6000.c:11307 - #, fuzzy, gcc-internal-format, gfc-internal-format - msgid "Builtin function %s is not supported with the current options" - msgstr "атрыбуты секцыі не падтрымліваюцца для гэтай мэты" - --#: config/rs6000/rs6000.c:12568 -+#: config/rs6000/rs6000.c:12567 - #, gcc-internal-format, gfc-internal-format - msgid "internal error: builtin function %s had no type" - msgstr "" - --#: config/rs6000/rs6000.c:12575 -+#: config/rs6000/rs6000.c:12574 - #, gcc-internal-format, gfc-internal-format - msgid "internal error: builtin function %s had an unexpected return type %s" - msgstr "" - --#: config/rs6000/rs6000.c:12591 -+#: config/rs6000/rs6000.c:12590 - #, gcc-internal-format, gfc-internal-format - msgid "internal error: builtin function %s, argument %d had unexpected argument type %s" - msgstr "" - --#: config/rs6000/rs6000.c:18577 -+#: config/rs6000/rs6000.c:18576 - #, fuzzy, gcc-internal-format - #| msgid "%s is too large" - msgid "stack frame too large" - msgstr "%s - вельмі вялікі" - --#: config/rs6000/rs6000.c:22051 -+#: config/rs6000/rs6000.c:22050 - #, gcc-internal-format - msgid "no profiling of 64-bit code for this ABI" - msgstr "" - --#: config/rs6000/rs6000.c:24036 -+#: config/rs6000/rs6000.c:24059 - #, gcc-internal-format - msgid "You cannot take the address of a nested function if you use the -mno-pointers-to-nested-functions option." - msgstr "" - --#: config/rs6000/rs6000.c:24117 -+#: config/rs6000/rs6000.c:24140 - #, gcc-internal-format - msgid "use of % in AltiVec types is invalid" - msgstr "" - --#: config/rs6000/rs6000.c:24119 -+#: config/rs6000/rs6000.c:24142 - #, gcc-internal-format - msgid "use of boolean types in AltiVec types is invalid" - msgstr "" - --#: config/rs6000/rs6000.c:24121 -+#: config/rs6000/rs6000.c:24144 - #, gcc-internal-format - msgid "use of % in AltiVec types is invalid" - msgstr "" - --#: config/rs6000/rs6000.c:24123 -+#: config/rs6000/rs6000.c:24146 - #, gcc-internal-format - msgid "use of decimal floating point types in AltiVec types is invalid" - msgstr "" - --#: config/rs6000/rs6000.c:24129 -+#: config/rs6000/rs6000.c:24152 - #, gcc-internal-format - msgid "use of % in AltiVec types is invalid for 64-bit code without -mvsx" - msgstr "" - --#: config/rs6000/rs6000.c:24132 -+#: config/rs6000/rs6000.c:24155 - #, gcc-internal-format - msgid "use of % in AltiVec types is deprecated; use %" - msgstr "" - --#: config/rs6000/rs6000.c:24137 -+#: config/rs6000/rs6000.c:24160 - #, gcc-internal-format - msgid "use of % in AltiVec types is invalid without -mvsx" - msgstr "" - --#: config/rs6000/rs6000.c:24140 -+#: config/rs6000/rs6000.c:24163 - #, gcc-internal-format - msgid "use of % in AltiVec types is invalid without -mvsx" - msgstr "" - --#: config/rs6000/rs6000.c:26979 -+#: config/rs6000/rs6000.c:27002 - #, gcc-internal-format, gfc-internal-format - msgid "emitting microcode insn %s\t[%s] #%d" - msgstr "" - --#: config/rs6000/rs6000.c:26983 -+#: config/rs6000/rs6000.c:27006 - #, gcc-internal-format, gfc-internal-format - msgid "emitting conditional microcode insn %s\t[%s] #%d" - msgstr "" - --#: config/rs6000/rs6000.c:27207 -+#: config/rs6000/rs6000.c:27230 - #, gcc-internal-format, gfc-internal-format - msgid "invalid cpu \"%s\" for %s\"%s\"%s" - msgstr "" - --#: config/rs6000/rs6000.c:27210 -+#: config/rs6000/rs6000.c:27233 - #, gcc-internal-format, gfc-internal-format - msgid "%s\"%s\"%s is not allowed" - msgstr "" - --#: config/rs6000/rs6000.c:27212 -+#: config/rs6000/rs6000.c:27235 - #, gcc-internal-format, gfc-internal-format - msgid "%s\"%s\"%s is invalid" - msgstr "" -@@ -26147,63 +26147,63 @@ - msgid "%qs uses dynamic stack allocation" - msgstr "" - --#: config/sh/sh.c:775 -+#: config/sh/sh.c:768 - #, gcc-internal-format - msgid "ignoring -fschedule-insns because of exception handling bug" - msgstr "" - --#: config/sh/sh.c:796 -+#: config/sh/sh.c:784 - #, gcc-internal-format - msgid "unwind tables currently require either a frame pointer or -maccumulate-outgoing-args for correctness" - msgstr "" - --#: config/sh/sh.c:7674 -+#: config/sh/sh.c:7677 - #, fuzzy, gcc-internal-format - msgid "__builtin_saveregs not supported by this subtarget" - msgstr "__buitin_saveregs не падтрымліваецца гэтай мэтай" - --#: config/sh/sh.c:8838 -+#: config/sh/sh.c:8841 - #, fuzzy, gcc-internal-format - msgid "%qE attribute only applies to interrupt functions" - msgstr "\"%s\" звычайна функцыя" - --#: config/sh/sh.c:8896 -+#: config/sh/sh.c:8899 - #, fuzzy, gcc-internal-format - msgid "%qE attribute is supported only for SH2A" - msgstr "атрыбуты секцыі не падтрымліваюцца для гэтай мэты" - --#: config/sh/sh.c:8926 -+#: config/sh/sh.c:8929 - #, gcc-internal-format - msgid "attribute interrupt_handler is not compatible with -m5-compact" - msgstr "" - --#: config/sh/sh.c:8943 -+#: config/sh/sh.c:8946 - #, fuzzy, gcc-internal-format - msgid "%qE attribute only applies to SH2A" - msgstr "\"%s\" звычайна функцыя" - --#: config/sh/sh.c:8965 -+#: config/sh/sh.c:8968 - #, gcc-internal-format - msgid "%qE attribute argument should be between 0 to 255" - msgstr "" - - #. The argument must be a constant string. --#: config/sh/sh.c:9038 -+#: config/sh/sh.c:9041 - #, fuzzy, gcc-internal-format - msgid "%qE attribute argument not a string constant" - msgstr "аргумент `__builtin_args_info' павінен быць канстантай" - --#: config/sh/sh.c:11618 -+#: config/sh/sh.c:11621 - #, gcc-internal-format - msgid "r0 needs to be available as a call-clobbered register" - msgstr "" - --#: config/sh/sh.c:11639 -+#: config/sh/sh.c:11642 - #, gcc-internal-format - msgid "need a second call-clobbered general purpose register" - msgstr "" - --#: config/sh/sh.c:11647 -+#: config/sh/sh.c:11650 - #, gcc-internal-format - msgid "need a call-clobbered target register" - msgstr "" -@@ -26327,12 +26327,12 @@ - msgid "__BELOW100__ attribute not allowed with auto storage class" - msgstr "" - --#: config/tilegx/tilegx.c:3397 config/tilepro/tilepro.c:3101 -+#: config/tilegx/tilegx.c:3398 config/tilepro/tilepro.c:3101 - #, gcc-internal-format - msgid "bad builtin icode" - msgstr "" - --#: config/tilegx/tilegx.c:3438 config/tilepro/tilepro.c:3127 -+#: config/tilegx/tilegx.c:3439 config/tilepro/tilepro.c:3127 - #, gcc-internal-format - msgid "operand must be an immediate of the right size" - msgstr "" -@@ -26550,40 +26550,40 @@ - msgid "-fexcess-precision=standard for Ada" - msgstr "" - --#: ada/gcc-interface/utils.c:5312 ada/gcc-interface/utils.c:5487 --#: ada/gcc-interface/utils.c:5529 ada/gcc-interface/utils.c:5583 -+#: ada/gcc-interface/utils.c:5303 ada/gcc-interface/utils.c:5478 -+#: ada/gcc-interface/utils.c:5520 ada/gcc-interface/utils.c:5574 - #, fuzzy, gcc-internal-format - #| msgid "`%s' attribute ignored" - msgid "%qs attribute ignored" - msgstr "\"%s\" атрыбут ігнарыруецца" - --#: ada/gcc-interface/utils.c:5430 -+#: ada/gcc-interface/utils.c:5421 - #, gcc-internal-format - msgid "%qs attribute requires prototypes with named arguments" - msgstr "" - --#: ada/gcc-interface/utils.c:5439 -+#: ada/gcc-interface/utils.c:5430 - #, fuzzy, gcc-internal-format - msgid "%qs attribute only applies to variadic functions" - msgstr "\"%s\" звычайна функцыя" - --#: ada/gcc-interface/utils.c:5510 -+#: ada/gcc-interface/utils.c:5501 - #, fuzzy, gcc-internal-format - #| msgid "`%s' attribute ignored" - msgid "%qE attribute has no effect" - msgstr "\"%s\" атрыбут ігнарыруецца" - --#: ada/gcc-interface/utils.c:5616 -+#: ada/gcc-interface/utils.c:5607 - #, fuzzy, gcc-internal-format - msgid "invalid vector type for attribute %qs" - msgstr "нявернае выкарыстанне \"restict\"" - --#: ada/gcc-interface/utils.c:5679 -+#: ada/gcc-interface/utils.c:5670 - #, fuzzy, gcc-internal-format - msgid "attribute %qs applies to array types only" - msgstr "\"%s\" атрыбут ігнарыруецца" - --#: ada/gcc-interface/utils.c:5706 -+#: ada/gcc-interface/utils.c:5697 - #, fuzzy, gcc-internal-format - msgid "invalid element type for attribute %qs" - msgstr "нявернае выкарыстанне \"restict\"" -@@ -27024,7 +27024,7 @@ - msgid "passing %qT chooses %qT over %qT" - msgstr "" - --#: cp/call.c:8070 cp/name-lookup.c:5495 -+#: cp/call.c:8070 cp/name-lookup.c:5500 - #, gcc-internal-format - msgid " in call to %qD" - msgstr "" -@@ -27086,427 +27086,427 @@ - msgid "invalid initialization of reference of type %qT from expression of type %qT" - msgstr "" - --#: cp/class.c:296 -+#: cp/class.c:297 - #, gcc-internal-format - msgid "cannot convert from base %qT to derived type %qT via virtual base %qT" - msgstr "" - --#: cp/class.c:998 -+#: cp/class.c:999 - #, gcc-internal-format - msgid "Java class %qT cannot have a destructor" - msgstr "" - --#: cp/class.c:1000 -+#: cp/class.c:1001 - #, gcc-internal-format - msgid "Java class %qT cannot have an implicit non-trivial destructor" - msgstr "" - --#: cp/class.c:1103 -+#: cp/class.c:1104 - #, gcc-internal-format - msgid "%q+#D cannot be overloaded" - msgstr "" - --#: cp/class.c:1104 -+#: cp/class.c:1105 - #, gcc-internal-format - msgid "with %q+#D" - msgstr "" - --#: cp/class.c:1173 -+#: cp/class.c:1174 - #, gcc-internal-format - msgid "conflicting access specifications for method %q+D, ignored" - msgstr "" - --#: cp/class.c:1176 -+#: cp/class.c:1177 - #, gcc-internal-format - msgid "conflicting access specifications for field %qE, ignored" - msgstr "" - --#: cp/class.c:1238 cp/class.c:1246 -+#: cp/class.c:1239 cp/class.c:1247 - #, fuzzy, gcc-internal-format - msgid "%q+D invalid in %q#T" - msgstr "Нерэчаісны выбар \"%s\"" - --#: cp/class.c:1239 -+#: cp/class.c:1240 - #, gcc-internal-format - msgid " because of local method %q+#D with same name" - msgstr "" - --#: cp/class.c:1247 -+#: cp/class.c:1248 - #, gcc-internal-format - msgid " because of local member %q+#D with same name" - msgstr "" - --#: cp/class.c:1291 -+#: cp/class.c:1292 - #, gcc-internal-format - msgid "cannot derive from % base %qT in derived type %qT" - msgstr "" - --#: cp/class.c:1303 -+#: cp/class.c:1304 - #, gcc-internal-format - msgid "base class %q#T has a non-virtual destructor" - msgstr "" - --#: cp/class.c:1707 -+#: cp/class.c:1708 - #, gcc-internal-format - msgid "all member functions in class %qT are private" - msgstr "" - --#: cp/class.c:1719 -+#: cp/class.c:1720 - #, gcc-internal-format - msgid "%q#T only defines a private destructor and has no friends" - msgstr "" - --#: cp/class.c:1764 -+#: cp/class.c:1765 - #, gcc-internal-format - msgid "%q#T only defines private constructors and has no friends" - msgstr "" - --#: cp/class.c:2157 -+#: cp/class.c:2158 - #, gcc-internal-format - msgid "no unique final overrider for %qD in %qT" - msgstr "" - --#: cp/class.c:2524 -+#: cp/class.c:2525 - #, gcc-internal-format - msgid "%q+#D marked final, but is not virtual" - msgstr "" - --#: cp/class.c:2526 -+#: cp/class.c:2527 - #, gcc-internal-format - msgid "%q+#D marked override, but does not override" - msgstr "" - - #. Here we know it is a hider, and no overrider exists. --#: cp/class.c:2595 -+#: cp/class.c:2596 - #, gcc-internal-format - msgid "%q+D was hidden" - msgstr "" - --#: cp/class.c:2596 -+#: cp/class.c:2597 - #, gcc-internal-format - msgid " by %q+D" - msgstr "" - --#: cp/class.c:2639 cp/decl2.c:1359 -+#: cp/class.c:2640 cp/decl2.c:1359 - #, gcc-internal-format - msgid "%q+#D invalid; an anonymous union can only have non-static data members" - msgstr "" - --#: cp/class.c:2642 -+#: cp/class.c:2643 - #, gcc-internal-format - msgid "%q+#D invalid; an anonymous struct can only have non-static data members" - msgstr "" - --#: cp/class.c:2650 cp/decl2.c:1365 -+#: cp/class.c:2651 cp/decl2.c:1365 - #, gcc-internal-format - msgid "private member %q+#D in anonymous union" - msgstr "" - --#: cp/class.c:2652 -+#: cp/class.c:2653 - #, gcc-internal-format - msgid "private member %q+#D in anonymous struct" - msgstr "" - --#: cp/class.c:2657 cp/decl2.c:1367 -+#: cp/class.c:2658 cp/decl2.c:1367 - #, gcc-internal-format - msgid "protected member %q+#D in anonymous union" - msgstr "" - --#: cp/class.c:2659 -+#: cp/class.c:2660 - #, gcc-internal-format - msgid "protected member %q+#D in anonymous struct" - msgstr "" - --#: cp/class.c:2887 -+#: cp/class.c:2904 - #, fuzzy, gcc-internal-format - msgid "bit-field %q+#D with non-integral type" - msgstr "бітавае поле \"%s\" мае нерэчаісны тып" - --#: cp/class.c:2903 -+#: cp/class.c:2920 - #, fuzzy, gcc-internal-format - msgid "bit-field %q+D width not an integer constant" - msgstr "бітавае поле \"%s\" мае нерэчаісны тып" - --#: cp/class.c:2908 -+#: cp/class.c:2925 - #, gcc-internal-format - msgid "negative width in bit-field %q+D" - msgstr "" - --#: cp/class.c:2913 -+#: cp/class.c:2930 - #, gcc-internal-format - msgid "zero width for bit-field %q+D" - msgstr "" - --#: cp/class.c:2919 -+#: cp/class.c:2936 - #, gcc-internal-format - msgid "width of %q+D exceeds its type" - msgstr "" - --#: cp/class.c:2923 -+#: cp/class.c:2940 - #, gcc-internal-format - msgid "%q+D is too small to hold all values of %q#T" - msgstr "" - --#: cp/class.c:2982 -+#: cp/class.c:2999 - #, gcc-internal-format - msgid "member %q+#D with constructor not allowed in union" - msgstr "" - --#: cp/class.c:2985 -+#: cp/class.c:3002 - #, gcc-internal-format - msgid "member %q+#D with destructor not allowed in union" - msgstr "" - --#: cp/class.c:2987 -+#: cp/class.c:3004 - #, gcc-internal-format - msgid "member %q+#D with copy assignment operator not allowed in union" - msgstr "" - --#: cp/class.c:2991 -+#: cp/class.c:3008 - #, gcc-internal-format - msgid "unrestricted unions only available with -std=c++11 or -std=gnu++11" - msgstr "" - --#: cp/class.c:3025 -+#: cp/class.c:3042 - #, gcc-internal-format - msgid "multiple fields in union %qT initialized" - msgstr "" - --#: cp/class.c:3109 -+#: cp/class.c:3126 - #, gcc-internal-format - msgid "%q+D may not be static because it is a member of a union" - msgstr "" - --#: cp/class.c:3114 -+#: cp/class.c:3131 - #, gcc-internal-format - msgid "%q+D may not have reference type %qT because it is a member of a union" - msgstr "" - --#: cp/class.c:3125 -+#: cp/class.c:3142 - #, fuzzy, gcc-internal-format - msgid "field %q+D invalidly declared function type" - msgstr "бітавае поле \"%s\" мае нерэчаісны тып" - --#: cp/class.c:3131 -+#: cp/class.c:3148 - #, fuzzy, gcc-internal-format - msgid "field %q+D invalidly declared method type" - msgstr "бітавае поле \"%s\" мае нерэчаісны тып" - --#: cp/class.c:3187 -+#: cp/class.c:3204 - #, gcc-internal-format - msgid "ignoring packed attribute because of unpacked non-POD field %q+#D" - msgstr "" - --#: cp/class.c:3285 -+#: cp/class.c:3302 - #, gcc-internal-format - msgid "field %q+#D with same name as class" - msgstr "" - --#: cp/class.c:3308 -+#: cp/class.c:3325 - #, gcc-internal-format - msgid "%q#T has pointer data members" - msgstr "" - --#: cp/class.c:3313 -+#: cp/class.c:3330 - #, gcc-internal-format - msgid " but does not override %<%T(const %T&)%>" - msgstr "" - --#: cp/class.c:3315 -+#: cp/class.c:3332 - #, gcc-internal-format - msgid " or %" - msgstr "" - --#: cp/class.c:3319 -+#: cp/class.c:3336 - #, gcc-internal-format - msgid " but does not override %" - msgstr "" - --#: cp/class.c:3790 -+#: cp/class.c:3807 - #, gcc-internal-format - msgid "offset of empty base %qT may not be ABI-compliant and maychange in a future version of GCC" - msgstr "" - --#: cp/class.c:3917 -+#: cp/class.c:3934 - #, gcc-internal-format - msgid "class %qT will be considered nearly empty in a future version of GCC" - msgstr "" - --#: cp/class.c:3999 -+#: cp/class.c:4016 - #, fuzzy, gcc-internal-format - msgid "initializer specified for non-virtual method %q+D" - msgstr "не магу ініцыялізаваць сяброўскую функцыю \"%s\"" - --#: cp/class.c:4390 -+#: cp/class.c:4407 - #, gcc-internal-format - msgid "method overrides both % and %qE methods" - msgstr "" - --#: cp/class.c:4411 -+#: cp/class.c:4428 - #, gcc-internal-format - msgid "method declared %qE overriding %qE method" - msgstr "" - --#: cp/class.c:4877 cp/semantics.c:5729 -+#: cp/class.c:4894 cp/semantics.c:5729 - #, gcc-internal-format - msgid "enclosing class of constexpr non-static member function %q+#D is not a literal type" - msgstr "" - --#: cp/class.c:4902 -+#: cp/class.c:4919 - #, gcc-internal-format - msgid "%q+T is not literal because:" - msgstr "" - --#: cp/class.c:4904 -+#: cp/class.c:4921 - #, gcc-internal-format - msgid " %q+T has a non-trivial destructor" - msgstr "" - --#: cp/class.c:4909 -+#: cp/class.c:4926 - #, gcc-internal-format - msgid " %q+T is not an aggregate, does not have a trivial default constructor, and has no constexpr constructor that is not a copy or move constructor" - msgstr "" - --#: cp/class.c:4945 -+#: cp/class.c:4962 - #, gcc-internal-format - msgid " base class %qT of %q+T is non-literal" - msgstr "" - --#: cp/class.c:4959 -+#: cp/class.c:4976 - #, gcc-internal-format - msgid " non-static data member %q+D has non-literal type" - msgstr "" - --#: cp/class.c:5071 -+#: cp/class.c:5089 - #, gcc-internal-format - msgid "non-static reference %q+#D in class without a constructor" - msgstr "" - --#: cp/class.c:5076 -+#: cp/class.c:5094 - #, gcc-internal-format - msgid "non-static const member %q+#D in class without a constructor" - msgstr "" - - #. If the function is defaulted outside the class, we just - #. give the synthesis error. --#: cp/class.c:5102 -+#: cp/class.c:5120 - #, gcc-internal-format - msgid "%q+D declared to take const reference, but implicit declaration would take non-const" - msgstr "" - --#: cp/class.c:5105 -+#: cp/class.c:5123 - #, gcc-internal-format - msgid "%q+D declared to take non-const reference cannot be defaulted in the class body" - msgstr "" - --#: cp/class.c:5329 -+#: cp/class.c:5347 - #, gcc-internal-format - msgid "offset of virtual base %qT is not ABI-compliant and may change in a future version of GCC" - msgstr "" - --#: cp/class.c:5430 -+#: cp/class.c:5448 - #, gcc-internal-format - msgid "direct base %qT inaccessible in %qT due to ambiguity" - msgstr "" - --#: cp/class.c:5442 -+#: cp/class.c:5460 - #, gcc-internal-format - msgid "virtual base %qT inaccessible in %qT due to ambiguity" - msgstr "" - --#: cp/class.c:5628 -+#: cp/class.c:5646 - #, gcc-internal-format - msgid "size assigned to %qT may not be ABI-compliant and may change in a future version of GCC" - msgstr "" - --#: cp/class.c:5668 -+#: cp/class.c:5686 - #, gcc-internal-format - msgid "the offset of %qD may not be ABI-compliant and may change in a future version of GCC" - msgstr "" - --#: cp/class.c:5696 -+#: cp/class.c:5714 - #, gcc-internal-format - msgid "offset of %q+D is not ABI-compliant and may change in a future version of GCC" - msgstr "" - --#: cp/class.c:5706 -+#: cp/class.c:5724 - #, gcc-internal-format - msgid "%q+D contains empty classes which may cause base classes to be placed at different locations in a future version of GCC" - msgstr "" - --#: cp/class.c:5794 -+#: cp/class.c:5812 - #, gcc-internal-format - msgid "layout of classes derived from empty class %qT may change in a future version of GCC" - msgstr "" - --#: cp/class.c:5963 cp/decl.c:11829 cp/parser.c:18586 -+#: cp/class.c:5980 cp/decl.c:11840 cp/parser.c:18573 - #, fuzzy, gcc-internal-format - #| msgid "previous definition of `%#T'" - msgid "redefinition of %q#T" - msgstr "папярэдняе вызначэньне `%#T'" - --#: cp/class.c:6114 -+#: cp/class.c:6123 - #, gcc-internal-format - msgid "%q#T has virtual functions and accessible non-virtual destructor" - msgstr "" - --#: cp/class.c:6140 -+#: cp/class.c:6149 - #, gcc-internal-format - msgid "type transparent class %qT does not have any fields" - msgstr "" - --#: cp/class.c:6146 -+#: cp/class.c:6155 - #, gcc-internal-format - msgid "type transparent class %qT has base classes" - msgstr "" - --#: cp/class.c:6150 -+#: cp/class.c:6159 - #, gcc-internal-format - msgid "type transparent class %qT has virtual functions" - msgstr "" - --#: cp/class.c:6252 -+#: cp/class.c:6300 - #, gcc-internal-format - msgid "trying to finish struct, but kicked out due to previous parse errors" - msgstr "" - --#: cp/class.c:6758 -+#: cp/class.c:6810 - #, fuzzy, gcc-internal-format - #| msgid "language %s not recognized" - msgid "language string %<\"%E\"%> not recognized" - msgstr "мова %s не распазнана" - --#: cp/class.c:6848 -+#: cp/class.c:6900 - #, gcc-internal-format - msgid "cannot resolve overloaded function %qD based on conversion to type %qT" - msgstr "" - --#: cp/class.c:6972 -+#: cp/class.c:7024 - #, gcc-internal-format - msgid "no matches converting function %qD to type %q#T" - msgstr "" - --#: cp/class.c:6995 -+#: cp/class.c:7047 - #, gcc-internal-format - msgid "converting overloaded function %qD to type %q#T is ambiguous" - msgstr "" - --#: cp/class.c:7022 -+#: cp/class.c:7074 - #, fuzzy, gcc-internal-format - msgid "assuming pointer to member %qD" - msgstr "прапушчан ініцыялізатар" - --#: cp/class.c:7025 -+#: cp/class.c:7077 - #, gcc-internal-format - msgid "(a pointer to member can only be formed with %<&%E%>)" - msgstr "" - --#: cp/class.c:7087 cp/class.c:7121 -+#: cp/class.c:7139 cp/class.c:7173 - #, gcc-internal-format - msgid "not enough type information" - msgstr "" - --#: cp/class.c:7104 cp/cvt.c:169 cp/cvt.c:194 cp/cvt.c:244 -+#: cp/class.c:7156 cp/cvt.c:169 cp/cvt.c:194 cp/cvt.c:244 - #, gcc-internal-format - msgid "cannot convert %qE from type %qT to type %qT" - msgstr "" -@@ -27516,13 +27516,13 @@ - #. A name N used in a class S shall refer to the same declaration - #. in its context and when re-evaluated in the completed scope of - #. S. --#: cp/class.c:7415 cp/decl.c:1287 -+#: cp/class.c:7467 cp/decl.c:1287 - #, fuzzy, gcc-internal-format - #| msgid "declaration of `%#D'" - msgid "declaration of %q#D" - msgstr "абвяшчэньне `%#D'" - --#: cp/class.c:7416 -+#: cp/class.c:7468 - #, gcc-internal-format - msgid "changes meaning of %qD from %q+#D" - msgstr "" -@@ -27542,7 +27542,7 @@ - msgid "conversion of %qE from %qT to %qT is ambiguous" - msgstr "" - --#: cp/cvt.c:204 cp/decl.c:10586 cp/typeck.c:4101 -+#: cp/cvt.c:204 cp/decl.c:10584 cp/typeck.c:4101 - #, gcc-internal-format - msgid "zero as null pointer constant" - msgstr "" -@@ -28461,7 +28461,7 @@ - msgid "name used in a GNU-style designated initializer for an array" - msgstr "" - --#: cp/decl.c:4698 cp/typeck2.c:1084 cp/typeck2.c:1189 -+#: cp/decl.c:4698 cp/typeck2.c:1087 cp/typeck2.c:1192 - #, gcc-internal-format - msgid "non-trivial designated initializers not supported" - msgstr "" -@@ -28556,8 +28556,8 @@ - msgid "C99 designator %qE outside aggregate initializer" - msgstr "" - --#: cp/decl.c:5195 cp/decl.c:5380 cp/typeck2.c:1071 cp/typeck2.c:1270 --#: cp/typeck2.c:1299 cp/typeck2.c:1346 -+#: cp/decl.c:5195 cp/decl.c:5380 cp/typeck2.c:1074 cp/typeck2.c:1273 -+#: cp/typeck2.c:1302 cp/typeck2.c:1349 - #, fuzzy, gcc-internal-format - msgid "too many initializers for %qT" - msgstr "не магу ініцыялізаваць сяброўскую функцыю \"%s\"" -@@ -29093,7 +29093,7 @@ - msgid "type %qT is not derived from type %qT" - msgstr "" - --#: cp/decl.c:8519 cp/decl.c:8611 cp/decl.c:8620 cp/decl.c:9963 -+#: cp/decl.c:8519 cp/decl.c:8611 cp/decl.c:8620 cp/decl.c:9961 - #, fuzzy, gcc-internal-format - msgid "declaration of %qD as non-function" - msgstr "няма папярэдняга аб'яўлення для \"%s\"" -@@ -29421,380 +29421,375 @@ - - #: cp/decl.c:9497 - #, gcc-internal-format --msgid "both % and % cannot be used here" --msgstr "" -- --#: cp/decl.c:9499 --#, gcc-internal-format - msgid "both % and % cannot be used here" - msgstr "" - --#: cp/decl.c:9511 -+#: cp/decl.c:9509 - #, gcc-internal-format - msgid "template-id %qD used as a declarator" - msgstr "" - --#: cp/decl.c:9562 -+#: cp/decl.c:9560 - #, gcc-internal-format - msgid "member functions are implicitly friends of their class" - msgstr "" - --#: cp/decl.c:9567 -+#: cp/decl.c:9565 - #, gcc-internal-format - msgid "extra qualification %<%T::%> on member %qs" - msgstr "" - --#: cp/decl.c:9597 -+#: cp/decl.c:9595 - #, gcc-internal-format - msgid "cannot define member function %<%T::%s%> within %<%T%>" - msgstr "" - --#: cp/decl.c:9599 -+#: cp/decl.c:9597 - #, gcc-internal-format - msgid "cannot declare member function %<%T::%s%> within %<%T%>" - msgstr "" - --#: cp/decl.c:9608 -+#: cp/decl.c:9606 - #, gcc-internal-format - msgid "cannot declare member %<%T::%s%> within %qT" - msgstr "" - --#: cp/decl.c:9634 -+#: cp/decl.c:9632 - #, gcc-internal-format - msgid "non-parameter %qs cannot be a parameter pack" - msgstr "" - --#: cp/decl.c:9644 -+#: cp/decl.c:9642 - #, fuzzy, gcc-internal-format - #| msgid "size of array `%s' is too large" - msgid "size of array %qs is too large" - msgstr "памер масіва \"%s\" вельмі вялікі" - --#: cp/decl.c:9655 -+#: cp/decl.c:9653 - #, gcc-internal-format - msgid "data member may not have variably modified type %qT" - msgstr "" - --#: cp/decl.c:9657 -+#: cp/decl.c:9655 - #, gcc-internal-format - msgid "parameter may not have variably modified type %qT" - msgstr "" - - #. [dcl.fct.spec] The explicit specifier shall only be used in - #. declarations of constructors within a class definition. --#: cp/decl.c:9665 -+#: cp/decl.c:9663 - #, gcc-internal-format - msgid "only declarations of constructors can be %" - msgstr "" - --#: cp/decl.c:9673 -+#: cp/decl.c:9671 - #, fuzzy, gcc-internal-format - msgid "non-member %qs cannot be declared %" - msgstr "віртуальныя функцыі не могуць быць сяброўскімі" - --#: cp/decl.c:9678 -+#: cp/decl.c:9676 - #, gcc-internal-format - msgid "non-object member %qs cannot be declared %" - msgstr "" - --#: cp/decl.c:9684 -+#: cp/decl.c:9682 - #, fuzzy, gcc-internal-format - msgid "function %qs cannot be declared %" - msgstr "віртуальныя функцыі не могуць быць сяброўскімі" - --#: cp/decl.c:9689 -+#: cp/decl.c:9687 - #, fuzzy, gcc-internal-format - msgid "static %qs cannot be declared %" - msgstr "віртуальныя функцыі не могуць быць сяброўскімі" - --#: cp/decl.c:9694 -+#: cp/decl.c:9692 - #, fuzzy, gcc-internal-format - msgid "const %qs cannot be declared %" - msgstr "віртуальныя функцыі не могуць быць сяброўскімі" - --#: cp/decl.c:9699 -+#: cp/decl.c:9697 - #, fuzzy, gcc-internal-format - msgid "reference %qs cannot be declared %" - msgstr "віртуальныя функцыі не могуць быць сяброўскімі" - --#: cp/decl.c:9734 -+#: cp/decl.c:9732 - #, gcc-internal-format - msgid "typedef declared %" - msgstr "" - --#: cp/decl.c:9744 -+#: cp/decl.c:9742 - #, gcc-internal-format - msgid "typedef name may not be a nested-name-specifier" - msgstr "" - --#: cp/decl.c:9762 -+#: cp/decl.c:9760 - #, gcc-internal-format - msgid "ISO C++ forbids nested type %qD with same name as enclosing class" - msgstr "" - --#: cp/decl.c:9864 -+#: cp/decl.c:9862 - #, gcc-internal-format - msgid "qualified function types cannot be used to declare static member functions" - msgstr "" - --#: cp/decl.c:9866 -+#: cp/decl.c:9864 - #, fuzzy, gcc-internal-format - msgid "qualified function types cannot be used to declare free functions" - msgstr "віртуальныя функцыі не могуць быць сяброўскімі" - --#: cp/decl.c:9893 -+#: cp/decl.c:9891 - #, gcc-internal-format - msgid "type qualifiers specified for friend class declaration" - msgstr "" - --#: cp/decl.c:9898 -+#: cp/decl.c:9896 - #, fuzzy, gcc-internal-format - msgid "% specified for friend class declaration" - msgstr "паўторнае абвяшчэнне меткі \"%s\"" - --#: cp/decl.c:9906 -+#: cp/decl.c:9904 - #, fuzzy, gcc-internal-format - msgid "template parameters cannot be friends" - msgstr "віртуальныя функцыі не могуць быць сяброўскімі" - --#: cp/decl.c:9908 -+#: cp/decl.c:9906 - #, gcc-internal-format - msgid "friend declaration requires class-key, i.e. %" - msgstr "" - --#: cp/decl.c:9912 -+#: cp/decl.c:9910 - #, gcc-internal-format - msgid "friend declaration requires class-key, i.e. %" - msgstr "" - --#: cp/decl.c:9925 -+#: cp/decl.c:9923 - #, gcc-internal-format - msgid "trying to make class %qT a friend of global scope" - msgstr "" - --#: cp/decl.c:9943 -+#: cp/decl.c:9941 - #, gcc-internal-format - msgid "invalid qualifiers on non-member function type" - msgstr "" - --#: cp/decl.c:9953 -+#: cp/decl.c:9951 - #, gcc-internal-format - msgid "abstract declarator %qT used as declaration" - msgstr "" - --#: cp/decl.c:9982 -+#: cp/decl.c:9980 - #, fuzzy, gcc-internal-format - msgid "cannot use %<::%> in parameter declaration" - msgstr "Не магу знайсці дэкларацыю пратакола для \"%s\"" - --#: cp/decl.c:9986 -+#: cp/decl.c:9984 - #, fuzzy, gcc-internal-format - msgid "parameter declared %" - msgstr "тып параметра \"%s\" не аб'яўлены" - --#: cp/decl.c:10028 -+#: cp/decl.c:10026 - #, gcc-internal-format - msgid "non-static data member declared %" - msgstr "" - - #. Something like struct S { int N::j; }; --#: cp/decl.c:10050 -+#: cp/decl.c:10048 - #, fuzzy, gcc-internal-format - #| msgid "invalid use of `::'" - msgid "invalid use of %<::%>" - msgstr "нерэчаіснае выкарыстаньне `::'" - --#: cp/decl.c:10072 -+#: cp/decl.c:10070 - #, fuzzy, gcc-internal-format - msgid "declaration of function %qD in invalid context" - msgstr "няма папярэдняга аб'яўлення для \"%s\"" - --#: cp/decl.c:10081 -+#: cp/decl.c:10079 - #, fuzzy, gcc-internal-format - msgid "function %qD declared virtual inside a union" - msgstr "\"%s\" не абвешчан (першае выкарыстанне ў гэтай функцыі)" - --#: cp/decl.c:10090 -+#: cp/decl.c:10088 - #, gcc-internal-format - msgid "%qD cannot be declared virtual, since it is always static" - msgstr "" - --#: cp/decl.c:10106 -+#: cp/decl.c:10104 - #, gcc-internal-format - msgid "expected qualified name in friend declaration for destructor %qD" - msgstr "" - --#: cp/decl.c:10113 -+#: cp/decl.c:10111 - #, fuzzy, gcc-internal-format - #| msgid "declaration of template `%#D'" - msgid "declaration of %qD as member of %qT" - msgstr "абвяшчэньне шаблёну `%#D'" - --#: cp/decl.c:10119 -+#: cp/decl.c:10117 - #, gcc-internal-format - msgid "a destructor cannot be %" - msgstr "" - --#: cp/decl.c:10125 -+#: cp/decl.c:10123 - #, gcc-internal-format - msgid "expected qualified name in friend declaration for constructor %qD" - msgstr "" - --#: cp/decl.c:10171 -+#: cp/decl.c:10169 - #, fuzzy, gcc-internal-format - msgid "field %qD has incomplete type" - msgstr "\"%s\" мае незавершаны тып" - --#: cp/decl.c:10173 -+#: cp/decl.c:10171 - #, fuzzy, gcc-internal-format - msgid "name %qT has incomplete type" - msgstr "\"%s\" мае незавершаны тып" - --#: cp/decl.c:10182 -+#: cp/decl.c:10180 - #, fuzzy, gcc-internal-format - #| msgid "declaration of template `%#D'" - msgid " in instantiation of template %qT" - msgstr "абвяшчэньне шаблёну `%#D'" - --#: cp/decl.c:10191 -+#: cp/decl.c:10189 - #, fuzzy, gcc-internal-format - msgid "%qE is neither function nor member function; cannot be declared friend" - msgstr "віртуальныя функцыі не могуць быць сяброўскімі" - --#: cp/decl.c:10243 -+#: cp/decl.c:10241 - #, gcc-internal-format - msgid "constexpr static data member %qD must have an initializer" - msgstr "" - --#: cp/decl.c:10252 -+#: cp/decl.c:10250 - #, gcc-internal-format - msgid "non-static data member %qE declared %" - msgstr "" - --#: cp/decl.c:10302 -+#: cp/decl.c:10300 - #, gcc-internal-format - msgid "storage class % invalid for function %qs" - msgstr "" - --#: cp/decl.c:10304 -+#: cp/decl.c:10302 - #, gcc-internal-format - msgid "storage class % invalid for function %qs" - msgstr "" - --#: cp/decl.c:10306 -+#: cp/decl.c:10304 - #, gcc-internal-format - msgid "storage class %<__thread%> invalid for function %qs" - msgstr "" - --#: cp/decl.c:10309 -+#: cp/decl.c:10307 - #, gcc-internal-format - msgid "virt-specifiers in %qs not allowed outside a class definition" - msgstr "" - --#: cp/decl.c:10320 -+#: cp/decl.c:10318 - #, gcc-internal-format - msgid "% specified invalid for function %qs declared out of global scope" - msgstr "" - --#: cp/decl.c:10324 -+#: cp/decl.c:10322 - #, gcc-internal-format - msgid "% specifier invalid for function %qs declared out of global scope" - msgstr "" - --#: cp/decl.c:10332 -+#: cp/decl.c:10330 - #, gcc-internal-format - msgid "virtual non-class function %qs" - msgstr "" - --#: cp/decl.c:10339 -+#: cp/decl.c:10337 - #, gcc-internal-format - msgid "%qs defined in a non-class scope" - msgstr "" - --#: cp/decl.c:10340 -+#: cp/decl.c:10338 - #, fuzzy, gcc-internal-format - msgid "%qs declared in a non-class scope" - msgstr "\"%s\" не абвешчан (першае выкарыстанне ў гэтай функцыі)" - --#: cp/decl.c:10368 -+#: cp/decl.c:10366 - #, gcc-internal-format - msgid "cannot declare member function %qD to have static linkage" - msgstr "" - - #. FIXME need arm citation --#: cp/decl.c:10375 -+#: cp/decl.c:10373 - #, gcc-internal-format - msgid "cannot declare static function inside another function" - msgstr "" - --#: cp/decl.c:10405 -+#: cp/decl.c:10403 - #, gcc-internal-format - msgid "% may not be used when defining (as opposed to declaring) a static data member" - msgstr "" - --#: cp/decl.c:10412 -+#: cp/decl.c:10410 - #, gcc-internal-format - msgid "static member %qD declared %" - msgstr "" - --#: cp/decl.c:10418 -+#: cp/decl.c:10416 - #, gcc-internal-format - msgid "cannot explicitly declare member %q#D to have extern linkage" - msgstr "" - --#: cp/decl.c:10425 -+#: cp/decl.c:10423 - #, gcc-internal-format - msgid "declaration of constexpr variable %qD is not a definition" - msgstr "" - --#: cp/decl.c:10438 -+#: cp/decl.c:10436 - #, gcc-internal-format - msgid "%qs initialized and declared %" - msgstr "" - --#: cp/decl.c:10442 -+#: cp/decl.c:10440 - #, gcc-internal-format - msgid "%qs has both % and initializer" - msgstr "" - --#: cp/decl.c:10570 -+#: cp/decl.c:10568 - #, fuzzy, gcc-internal-format - #| msgid "default argument for `%#D' has type `%T'" - msgid "default argument for %q#D has type %qT" - msgstr "звычайны аргумэнт для `%#D' мае тып `%T'" - --#: cp/decl.c:10573 -+#: cp/decl.c:10571 - #, fuzzy, gcc-internal-format - #| msgid "default argument for `%#D' has type `%T'" - msgid "default argument for parameter of type %qT has type %qT" - msgstr "звычайны аргумэнт для `%#D' мае тып `%T'" - --#: cp/decl.c:10601 -+#: cp/decl.c:10599 - #, fuzzy, gcc-internal-format - msgid "default argument %qE uses %qD" - msgstr "нехапае аргументаў у функцыі \"%s\"" - --#: cp/decl.c:10603 -+#: cp/decl.c:10601 - #, fuzzy, gcc-internal-format - msgid "default argument %qE uses local variable %qD" - msgstr "нехапае аргументаў у функцыі \"%s\"" - --#: cp/decl.c:10691 -+#: cp/decl.c:10689 - #, fuzzy, gcc-internal-format - msgid "parameter %qD has Java class type" - msgstr "тып параметра \"%s\" не аб'яўлены" - --#: cp/decl.c:10719 -+#: cp/decl.c:10717 - #, fuzzy, gcc-internal-format - msgid "parameter %qD invalidly declared method type" - msgstr "тып параметра \"%s\" не аб'яўлены" - --#: cp/decl.c:10744 -+#: cp/decl.c:10742 - #, gcc-internal-format - msgid "parameter %qD includes pointer to array of unknown bound %qT" - msgstr "" - --#: cp/decl.c:10746 -+#: cp/decl.c:10744 - #, gcc-internal-format - msgid "parameter %qD includes reference to array of unknown bound %qT" - msgstr "" -@@ -29814,170 +29809,170 @@ - #. or implicitly defined), there's no need to worry about their - #. existence. Theoretically, they should never even be - #. instantiated, but that's hard to forestall. --#: cp/decl.c:10987 -+#: cp/decl.c:10998 - #, gcc-internal-format - msgid "invalid constructor; you probably meant %<%T (const %T&)%>" - msgstr "" - --#: cp/decl.c:11109 -+#: cp/decl.c:11120 - #, fuzzy, gcc-internal-format - msgid "%qD may not be declared within a namespace" - msgstr "\"%s\" не абвешчан (першае выкарыстанне ў гэтай функцыі)" - --#: cp/decl.c:11114 -+#: cp/decl.c:11125 - #, fuzzy, gcc-internal-format - msgid "%qD may not be declared as static" - msgstr "\"%s\" не абвешчан (першае выкарыстанне ў гэтай функцыі)" - --#: cp/decl.c:11140 -+#: cp/decl.c:11151 - #, gcc-internal-format - msgid "%qD must be a nonstatic member function" - msgstr "" - --#: cp/decl.c:11149 -+#: cp/decl.c:11160 - #, gcc-internal-format - msgid "%qD must be either a non-static member function or a non-member function" - msgstr "" - --#: cp/decl.c:11171 -+#: cp/decl.c:11182 - #, gcc-internal-format - msgid "%qD must have an argument of class or enumerated type" - msgstr "" - --#: cp/decl.c:11200 -+#: cp/decl.c:11211 - #, gcc-internal-format - msgid "conversion to a reference to void will never use a type conversion operator" - msgstr "" - --#: cp/decl.c:11202 -+#: cp/decl.c:11213 - #, gcc-internal-format - msgid "conversion to void will never use a type conversion operator" - msgstr "" - --#: cp/decl.c:11209 -+#: cp/decl.c:11220 - #, gcc-internal-format - msgid "conversion to a reference to the same type will never use a type conversion operator" - msgstr "" - --#: cp/decl.c:11211 -+#: cp/decl.c:11222 - #, gcc-internal-format - msgid "conversion to the same type will never use a type conversion operator" - msgstr "" - --#: cp/decl.c:11219 -+#: cp/decl.c:11230 - #, gcc-internal-format - msgid "conversion to a reference to a base class will never use a type conversion operator" - msgstr "" - --#: cp/decl.c:11221 -+#: cp/decl.c:11232 - #, gcc-internal-format - msgid "conversion to a base class will never use a type conversion operator" - msgstr "" - - #. 13.4.0.3 --#: cp/decl.c:11230 -+#: cp/decl.c:11241 - #, gcc-internal-format - msgid "ISO C++ prohibits overloading operator ?:" - msgstr "" - --#: cp/decl.c:11235 -+#: cp/decl.c:11246 - #, gcc-internal-format - msgid "%qD must not have variable number of arguments" - msgstr "" - --#: cp/decl.c:11286 -+#: cp/decl.c:11297 - #, gcc-internal-format - msgid "postfix %qD must take % as its argument" - msgstr "" - --#: cp/decl.c:11289 -+#: cp/decl.c:11300 - #, gcc-internal-format - msgid "postfix %qD must take % as its second argument" - msgstr "" - --#: cp/decl.c:11297 -+#: cp/decl.c:11308 - #, gcc-internal-format - msgid "%qD must take either zero or one argument" - msgstr "" - --#: cp/decl.c:11299 -+#: cp/decl.c:11310 - #, gcc-internal-format - msgid "%qD must take either one or two arguments" - msgstr "" - --#: cp/decl.c:11321 -+#: cp/decl.c:11332 - #, gcc-internal-format - msgid "prefix %qD should return %qT" - msgstr "" - --#: cp/decl.c:11327 -+#: cp/decl.c:11338 - #, gcc-internal-format - msgid "postfix %qD should return %qT" - msgstr "" - --#: cp/decl.c:11336 -+#: cp/decl.c:11347 - #, gcc-internal-format - msgid "%qD must take %" - msgstr "" - --#: cp/decl.c:11338 cp/decl.c:11347 -+#: cp/decl.c:11349 cp/decl.c:11358 - #, gcc-internal-format - msgid "%qD must take exactly one argument" - msgstr "" - --#: cp/decl.c:11349 -+#: cp/decl.c:11360 - #, gcc-internal-format - msgid "%qD must take exactly two arguments" - msgstr "" - --#: cp/decl.c:11358 -+#: cp/decl.c:11369 - #, gcc-internal-format - msgid "user-defined %qD always evaluates both arguments" - msgstr "" - --#: cp/decl.c:11372 -+#: cp/decl.c:11383 - #, gcc-internal-format - msgid "%qD should return by value" - msgstr "" - --#: cp/decl.c:11383 cp/decl.c:11388 -+#: cp/decl.c:11394 cp/decl.c:11399 - #, fuzzy, gcc-internal-format - msgid "%qD cannot have default arguments" - msgstr "нехапае аргументаў у функцыі \"%s\"" - --#: cp/decl.c:11449 -+#: cp/decl.c:11460 - #, fuzzy, gcc-internal-format - msgid "using template type parameter %qT after %qs" - msgstr "нявернае выкарыстанне \"restict\"" - --#: cp/decl.c:11471 -+#: cp/decl.c:11482 - #, gcc-internal-format - msgid "using alias template specialization %qT after %qs" - msgstr "" - --#: cp/decl.c:11474 -+#: cp/decl.c:11485 - #, gcc-internal-format - msgid "using typedef-name %qD after %qs" - msgstr "" - --#: cp/decl.c:11476 -+#: cp/decl.c:11487 - #, fuzzy, gcc-internal-format - #| msgid "this is a previous declaration" - msgid "%qD has a previous declaration here" - msgstr "гэта папярэдняе абвяшчэньне" - --#: cp/decl.c:11484 -+#: cp/decl.c:11495 - #, gcc-internal-format - msgid "%qT referred to as %qs" - msgstr "" - --#: cp/decl.c:11485 cp/decl.c:11492 -+#: cp/decl.c:11496 cp/decl.c:11503 - #, fuzzy, gcc-internal-format - #| msgid "this is a previous declaration" - msgid "%q+T has a previous declaration here" - msgstr "гэта папярэдняе абвяшчэньне" - --#: cp/decl.c:11491 -+#: cp/decl.c:11502 - #, gcc-internal-format - msgid "%qT referred to as enum" - msgstr "" -@@ -29989,90 +29984,90 @@ - #. void f(class C); // No template header here - #. - #. then the required template argument is missing. --#: cp/decl.c:11506 -+#: cp/decl.c:11517 - #, fuzzy, gcc-internal-format - msgid "template argument required for %<%s %T%>" - msgstr "параметр \"%s\" ініцыялізаваны" - --#: cp/decl.c:11554 cp/name-lookup.c:3052 -+#: cp/decl.c:11565 cp/name-lookup.c:3057 - #, gcc-internal-format - msgid "%qD has the same name as the class in which it is declared" - msgstr "" - --#: cp/decl.c:11584 cp/name-lookup.c:2551 cp/name-lookup.c:3376 --#: cp/name-lookup.c:3421 cp/parser.c:5060 cp/parser.c:20517 -+#: cp/decl.c:11595 cp/name-lookup.c:2556 cp/name-lookup.c:3381 -+#: cp/name-lookup.c:3426 cp/parser.c:5060 cp/parser.c:20512 - #, fuzzy, gcc-internal-format - msgid "reference to %qD is ambiguous" - msgstr "памер \"%s\" - %d байт" - --#: cp/decl.c:11696 -+#: cp/decl.c:11707 - #, fuzzy, gcc-internal-format - msgid "use of enum %q#D without previous declaration" - msgstr "секцыя \"%s\" канфліктуе з папярэдняй дэкларацыяй" - --#: cp/decl.c:11717 -+#: cp/decl.c:11728 - #, fuzzy, gcc-internal-format - #| msgid "declaration of template `%#D'" - msgid "redeclaration of %qT as a non-template" - msgstr "абвяшчэньне шаблёну `%#D'" - --#: cp/decl.c:11718 -+#: cp/decl.c:11729 - #, fuzzy, gcc-internal-format - #| msgid "previous declaration `%D'" - msgid "previous declaration %q+D" - msgstr "папярэдняе абвяшчэньне `%D'" - --#: cp/decl.c:11852 -+#: cp/decl.c:11863 - #, gcc-internal-format - msgid "derived union %qT invalid" - msgstr "" - --#: cp/decl.c:11861 -+#: cp/decl.c:11872 - #, gcc-internal-format - msgid "Java class %qT cannot have multiple bases" - msgstr "" - --#: cp/decl.c:11872 -+#: cp/decl.c:11883 - #, gcc-internal-format - msgid "Java class %qT cannot have virtual bases" - msgstr "" - --#: cp/decl.c:11892 -+#: cp/decl.c:11903 - #, gcc-internal-format - msgid "base type %qT fails to be a struct or class type" - msgstr "" - --#: cp/decl.c:11925 -+#: cp/decl.c:11936 - #, gcc-internal-format - msgid "recursive type %qT undefined" - msgstr "" - --#: cp/decl.c:11927 -+#: cp/decl.c:11938 - #, fuzzy, gcc-internal-format - msgid "duplicate base type %qT invalid" - msgstr "паўтарэнне \"restrict\"" - --#: cp/decl.c:12051 -+#: cp/decl.c:12062 - #, gcc-internal-format - msgid "scoped/unscoped mismatch in enum %q#T" - msgstr "" - --#: cp/decl.c:12054 cp/decl.c:12062 cp/decl.c:12074 cp/parser.c:14523 -+#: cp/decl.c:12065 cp/decl.c:12073 cp/decl.c:12085 cp/parser.c:14523 - #, gcc-internal-format - msgid "previous definition here" - msgstr "папярэдняе вызначэньне" - --#: cp/decl.c:12059 -+#: cp/decl.c:12070 - #, gcc-internal-format - msgid "underlying type mismatch in enum %q#T" - msgstr "" - --#: cp/decl.c:12071 -+#: cp/decl.c:12082 - #, gcc-internal-format - msgid "different underlying type in enum %q#T" - msgstr "" - --#: cp/decl.c:12138 -+#: cp/decl.c:12149 - #, gcc-internal-format - msgid "underlying type %<%T%> of %<%T%> must be an integral type" - msgstr "" -@@ -30081,75 +30076,75 @@ - #. - #. IF no integral type can represent all the enumerator values, the - #. enumeration is ill-formed. --#: cp/decl.c:12272 -+#: cp/decl.c:12283 - #, gcc-internal-format - msgid "no integral type can represent all of the enumerator values for %qT" - msgstr "" - --#: cp/decl.c:12407 -+#: cp/decl.c:12424 - #, fuzzy, gcc-internal-format - msgid "enumerator value for %qD is not an integer constant" - msgstr "памер масіва \"%s\" адмоўны" - --#: cp/decl.c:12457 -+#: cp/decl.c:12474 - #, gcc-internal-format - msgid "incremented enumerator value is too large for %" - msgstr "" - --#: cp/decl.c:12469 -+#: cp/decl.c:12486 - #, gcc-internal-format - msgid "overflow in enumeration values at %qD" - msgstr "" - --#: cp/decl.c:12489 -+#: cp/decl.c:12506 - #, gcc-internal-format - msgid "enumerator value %E is too large for underlying type %<%T%>" - msgstr "" - --#: cp/decl.c:12586 -+#: cp/decl.c:12603 - #, fuzzy, gcc-internal-format - msgid "return type %q#T is incomplete" - msgstr "вяртаемы тып \"%s\" не \"int\"" - --#: cp/decl.c:12588 -+#: cp/decl.c:12605 - #, gcc-internal-format - msgid "return type has Java class type %q#T" - msgstr "" - --#: cp/decl.c:12712 cp/typeck.c:7909 -+#: cp/decl.c:12729 cp/typeck.c:7909 - #, gcc-internal-format - msgid "% should return a reference to %<*this%>" - msgstr "" - --#: cp/decl.c:12807 -+#: cp/decl.c:12824 - #, fuzzy, gcc-internal-format - #| msgid "no previous declaration for `%s'" - msgid "no previous declaration for %q+D" - msgstr "няма папярэдняга аб'яўлення для \"%s\"" - --#: cp/decl.c:13022 -+#: cp/decl.c:13039 - #, fuzzy, gcc-internal-format - #| msgid "Invalid declaration" - msgid "invalid function declaration" - msgstr "Нерэчаіснае абвяшчэнне" - --#: cp/decl.c:13106 -+#: cp/decl.c:13123 - #, fuzzy, gcc-internal-format - msgid "parameter %qD declared void" - msgstr "тып параметра \"%s\" не аб'яўлены" - --#: cp/decl.c:13559 -+#: cp/decl.c:13576 - #, fuzzy, gcc-internal-format - #| msgid "label `%D' defined but not used" - msgid "parameter %q+D set but not used" - msgstr "адмеціна `%D' вызначана, але не выкарыстоўваецца" - --#: cp/decl.c:13654 -+#: cp/decl.c:13671 - #, fuzzy, gcc-internal-format - msgid "invalid member function declaration" - msgstr "паўторнае абвяшчэнне меткі \"%s\"" - --#: cp/decl.c:13668 -+#: cp/decl.c:13685 - #, fuzzy, gcc-internal-format - msgid "%qD is already defined in class %qT" - msgstr "не знойдзен клас \"%s\"" -@@ -30498,7 +30493,7 @@ - msgid "throwing NULL, which has integral, not pointer type" - msgstr "" - --#: cp/except.c:743 cp/init.c:2308 -+#: cp/except.c:743 cp/init.c:2310 - #, gcc-internal-format - msgid "%qD should never be overloaded" - msgstr "" -@@ -30759,153 +30754,153 @@ - msgid "bad array initializer" - msgstr "нерэчаісны ініцыялізатар" - --#: cp/init.c:1778 cp/semantics.c:2780 -+#: cp/init.c:1780 cp/semantics.c:2780 - #, fuzzy, gcc-internal-format - msgid "%qT is not a class type" - msgstr "\"%s\" мае незавершаны тып" - --#: cp/init.c:1832 -+#: cp/init.c:1834 - #, gcc-internal-format - msgid "incomplete type %qT does not have member %qD" - msgstr "" - --#: cp/init.c:1845 -+#: cp/init.c:1847 - #, fuzzy, gcc-internal-format - msgid "invalid pointer to bit-field %qD" - msgstr "нявернае выкарыстанне \"restict\"" - --#: cp/init.c:1922 -+#: cp/init.c:1924 - #, fuzzy, gcc-internal-format - msgid "invalid use of non-static member function %qD" - msgstr "нявернае выкарыстанне \"restict\"" - --#: cp/init.c:1928 -+#: cp/init.c:1930 - #, fuzzy, gcc-internal-format - msgid "invalid use of non-static data member %qD" - msgstr "нявернае выкарыстанне \"restict\"" - --#: cp/init.c:2110 -+#: cp/init.c:2112 - #, gcc-internal-format - msgid "uninitialized reference member in %q#T using % without new-initializer" - msgstr "" - --#: cp/init.c:2113 -+#: cp/init.c:2115 - #, fuzzy, gcc-internal-format - msgid "uninitialized reference member in %q#T" - msgstr "прапушчан ініцыялізатар" - --#: cp/init.c:2125 -+#: cp/init.c:2127 - #, gcc-internal-format - msgid "uninitialized const member in %q#T using % without new-initializer" - msgstr "" - --#: cp/init.c:2128 -+#: cp/init.c:2130 - #, fuzzy, gcc-internal-format - msgid "uninitialized const member in %q#T" - msgstr "не магу ініцыялізаваць сяброўскую функцыю \"%s\"" - --#: cp/init.c:2225 -+#: cp/init.c:2227 - #, gcc-internal-format - msgid "invalid type % for new" - msgstr "" - --#: cp/init.c:2268 -+#: cp/init.c:2270 - #, fuzzy, gcc-internal-format - msgid "uninitialized const in % of %q#T" - msgstr "не магу ініцыялізаваць сяброўскую функцыю \"%s\"" - --#: cp/init.c:2302 -+#: cp/init.c:2304 - #, gcc-internal-format - msgid "call to Java constructor with %qs undefined" - msgstr "" - --#: cp/init.c:2318 -+#: cp/init.c:2320 - #, gcc-internal-format - msgid "Java class %q#T object allocated using placement new" - msgstr "" - --#: cp/init.c:2348 -+#: cp/init.c:2350 - #, fuzzy, gcc-internal-format - #| msgid "field '%s' not found in class" - msgid "no suitable %qD found in class %qT" - msgstr "поле \"%s\" не знойдзена ў класе" - --#: cp/init.c:2355 cp/search.c:1107 -+#: cp/init.c:2357 cp/search.c:1107 - #, fuzzy, gcc-internal-format - msgid "request for member %qD is ambiguous" - msgstr "памер \"%s\" - %d байт" - --#: cp/init.c:2563 -+#: cp/init.c:2565 - #, gcc-internal-format - msgid "non-constant array size in new, unable to verify length of initializer-list" - msgstr "" - --#: cp/init.c:2574 -+#: cp/init.c:2576 - #, gcc-internal-format - msgid "parenthesized initializer in array new" - msgstr "" - --#: cp/init.c:2808 -+#: cp/init.c:2810 - #, gcc-internal-format - msgid "size in array new must have integral type" - msgstr "" - --#: cp/init.c:2822 -+#: cp/init.c:2824 - #, gcc-internal-format - msgid "new cannot be applied to a reference type" - msgstr "" - --#: cp/init.c:2831 -+#: cp/init.c:2833 - #, gcc-internal-format - msgid "new cannot be applied to a function type" - msgstr "" - --#: cp/init.c:2875 -+#: cp/init.c:2877 - #, gcc-internal-format - msgid "call to Java constructor, while % undefined" - msgstr "" - --#: cp/init.c:2893 -+#: cp/init.c:2895 - #, fuzzy, gcc-internal-format - msgid "can%'t find % in %qT" - msgstr "Не магу знайсці клас \"%s\"" - --#: cp/init.c:3382 -+#: cp/init.c:3384 - #, gcc-internal-format - msgid "initializer ends prematurely" - msgstr "" - --#: cp/init.c:3446 -+#: cp/init.c:3448 - #, gcc-internal-format - msgid "cannot initialize multi-dimensional array with initializer" - msgstr "" - --#: cp/init.c:3620 -+#: cp/init.c:3622 - #, gcc-internal-format - msgid "possible problem detected in invocation of delete operator:" - msgstr "" - --#: cp/init.c:3624 -+#: cp/init.c:3626 - #, gcc-internal-format - msgid "neither the destructor nor the class-specific operator delete will be called, even if they are declared when the class is defined" - msgstr "" - --#: cp/init.c:3640 -+#: cp/init.c:3642 - #, gcc-internal-format - msgid "deleting object of abstract class type %qT which has non-virtual destructor will cause undefined behaviour" - msgstr "" - --#: cp/init.c:3645 -+#: cp/init.c:3647 - #, gcc-internal-format - msgid "deleting object of polymorphic class type %qT which has non-virtual destructor might cause undefined behaviour" - msgstr "" - --#: cp/init.c:3667 -+#: cp/init.c:3669 - #, gcc-internal-format - msgid "unknown array size in delete" - msgstr "" - --#: cp/init.c:3936 -+#: cp/init.c:3938 - #, gcc-internal-format - msgid "type to vector delete is neither pointer or array type" - msgstr "" -@@ -30995,12 +30990,12 @@ - msgid "string literal in function template signature" - msgstr "" - --#: cp/mangle.c:3244 -+#: cp/mangle.c:3249 - #, gcc-internal-format - msgid "the mangled name of %qD will change in a future version of GCC" - msgstr "" - --#: cp/mangle.c:3388 -+#: cp/mangle.c:3393 - #, gcc-internal-format - msgid "-fabi-version=6 (or =0) avoids this error with a change in mangling" - msgstr "" -@@ -31010,12 +31005,12 @@ - msgid "generic thunk code fails for method %q#D which uses %<...%>" - msgstr "" - --#: cp/method.c:664 cp/method.c:1003 -+#: cp/method.c:664 cp/method.c:1002 - #, gcc-internal-format - msgid "non-static const member %q#D, can%'t use default assignment operator" - msgstr "" - --#: cp/method.c:670 cp/method.c:1009 -+#: cp/method.c:670 cp/method.c:1008 - #, gcc-internal-format - msgid "non-static reference member %q#D, can%'t use default assignment operator" - msgstr "" -@@ -31030,98 +31025,98 @@ - msgid "union member %q+D with non-trivial %qD" - msgstr "" - --#: cp/method.c:964 -+#: cp/method.c:963 - #, gcc-internal-format - msgid "defaulted constructor calls non-constexpr %q+D" - msgstr "" - --#: cp/method.c:1025 -+#: cp/method.c:1024 - #, fuzzy, gcc-internal-format - msgid "initializer for %q+#D is invalid" - msgstr "complex нерэчаісны для \"%s\"" - --#: cp/method.c:1048 -+#: cp/method.c:1047 - #, fuzzy, gcc-internal-format - msgid "uninitialized non-static const member %q#D" - msgstr "не магу ініцыялізаваць сяброўскую функцыю \"%s\"" - --#: cp/method.c:1055 -+#: cp/method.c:1054 - #, fuzzy, gcc-internal-format - msgid "uninitialized non-static reference member %q#D" - msgstr "не магу ініцыялізаваць сяброўскую функцыю \"%s\"" - --#: cp/method.c:1071 -+#: cp/method.c:1070 - #, gcc-internal-format - msgid "defaulted default constructor does not initialize %q+#D" - msgstr "" - - #. A trivial constructor doesn't have any NSDMI. --#: cp/method.c:1220 -+#: cp/method.c:1223 - #, gcc-internal-format - msgid "defaulted default constructor does not initialize any non-static data member" - msgstr "" - --#: cp/method.c:1298 -+#: cp/method.c:1304 - #, gcc-internal-format - msgid "%qT has virtual bases, default move assignment operator cannot be generated" - msgstr "" - --#: cp/method.c:1388 -+#: cp/method.c:1395 - #, gcc-internal-format - msgid "a lambda closure type has a deleted default constructor" - msgstr "" - --#: cp/method.c:1391 -+#: cp/method.c:1398 - #, gcc-internal-format - msgid "a lambda closure type has a deleted copy assignment operator" - msgstr "" - --#: cp/method.c:1401 -+#: cp/method.c:1408 - #, gcc-internal-format - msgid "%q+#D is implicitly declared as deleted because %qT declares a move constructor or move assignment operator" - msgstr "" - --#: cp/method.c:1411 -+#: cp/method.c:1418 - #, gcc-internal-format - msgid "%q+#D is implicitly deleted because the default definition would be ill-formed:" - msgstr "" - --#: cp/method.c:1621 -+#: cp/method.c:1630 - #, fuzzy, gcc-internal-format - msgid "defaulted declaration %q+D" - msgstr "пустое абвяшчэнне" - --#: cp/method.c:1623 -+#: cp/method.c:1632 - #, gcc-internal-format - msgid "does not match expected signature %qD" - msgstr "" - --#: cp/method.c:1637 -+#: cp/method.c:1646 - #, gcc-internal-format - msgid "function %q+D defaulted on its first declaration with an exception-specification that differs from the implicit declaration %q#D" - msgstr "" - --#: cp/method.c:1658 -+#: cp/method.c:1667 - #, gcc-internal-format - msgid "explicitly defaulted function %q+D cannot be declared as constexpr because the implicit declaration is not constexpr:" - msgstr "" - --#: cp/method.c:1680 -+#: cp/method.c:1689 - #, fuzzy, gcc-internal-format - msgid "a template cannot be defaulted" - msgstr "віртуальныя функцыі не могуць быць сяброўскімі" - --#: cp/method.c:1708 -+#: cp/method.c:1717 - #, fuzzy, gcc-internal-format - msgid "%qD cannot be defaulted" - msgstr "YYDEBUG не вызначан." - --#: cp/method.c:1717 -+#: cp/method.c:1726 - #, gcc-internal-format - msgid "defaulted function %q+D with default argument" - msgstr "" - --#: cp/method.c:1805 -+#: cp/method.c:1818 - #, gcc-internal-format - msgid "vtable layout for class %qT may not be ABI-compliantand may change in a future version of GCC due to implicit virtual destructor" - msgstr "" -@@ -31261,155 +31256,155 @@ - msgid "%s %s %p %d\n" - msgstr "" - --#: cp/name-lookup.c:2252 -+#: cp/name-lookup.c:2257 - #, fuzzy, gcc-internal-format - msgid "%q#D hides constructor for %q#T" - msgstr "дэструктару неабходны \"%#D\"" - --#: cp/name-lookup.c:2269 -+#: cp/name-lookup.c:2274 - #, fuzzy, gcc-internal-format - msgid "%q#D conflicts with previous using declaration %q#D" - msgstr "секцыя \"%s\" канфліктуе з папярэдняй дэкларацыяй" - --#: cp/name-lookup.c:2292 -+#: cp/name-lookup.c:2297 - #, fuzzy, gcc-internal-format - msgid "previous non-function declaration %q+#D" - msgstr "няма папярэдняга аб'яўлення для \"%s\"" - --#: cp/name-lookup.c:2293 -+#: cp/name-lookup.c:2298 - #, fuzzy, gcc-internal-format - msgid "conflicts with function declaration %q#D" - msgstr "секцыя \"%s\" канфліктуе з папярэдняй дэкларацыяй" - - #. It's a nested name with template parameter dependent scope. - #. This can only be using-declaration for class member. --#: cp/name-lookup.c:2383 cp/name-lookup.c:2408 -+#: cp/name-lookup.c:2388 cp/name-lookup.c:2413 - #, fuzzy, gcc-internal-format - msgid "%qT is not a namespace" - msgstr "\"%s\" мае незавершаны тып" - - #. 7.3.3/5 - #. A using-declaration shall not name a template-id. --#: cp/name-lookup.c:2393 -+#: cp/name-lookup.c:2398 - #, gcc-internal-format - msgid "a using-declaration cannot specify a template-id. Try %" - msgstr "" - --#: cp/name-lookup.c:2400 -+#: cp/name-lookup.c:2405 - #, fuzzy, gcc-internal-format - msgid "namespace %qD not allowed in using-declaration" - msgstr "\"%s\" - гэта не пачатак дэкларацыі" - --#: cp/name-lookup.c:2436 -+#: cp/name-lookup.c:2441 - #, fuzzy, gcc-internal-format - msgid "%qD not declared" - msgstr "YYDEBUG не вызначан." - --#: cp/name-lookup.c:2472 cp/name-lookup.c:2509 cp/name-lookup.c:2543 --#: cp/name-lookup.c:2558 -+#: cp/name-lookup.c:2477 cp/name-lookup.c:2514 cp/name-lookup.c:2548 -+#: cp/name-lookup.c:2563 - #, fuzzy, gcc-internal-format - msgid "%qD is already declared in this scope" - msgstr "\"%s\" не абвешчан (першае выкарыстанне ў гэтай функцыі)" - --#: cp/name-lookup.c:3201 -+#: cp/name-lookup.c:3206 - #, gcc-internal-format - msgid "using-declaration for non-member at class scope" - msgstr "" - --#: cp/name-lookup.c:3208 -+#: cp/name-lookup.c:3213 - #, gcc-internal-format - msgid "%<%T::%D%> names destructor" - msgstr "" - --#: cp/name-lookup.c:3213 -+#: cp/name-lookup.c:3218 - #, gcc-internal-format - msgid "%<%T::%D%> names constructor" - msgstr "" - --#: cp/name-lookup.c:3218 -+#: cp/name-lookup.c:3223 - #, fuzzy, gcc-internal-format - msgid "%<%T::%D%> names constructor in %qT" - msgstr "дэструктару неабходны \"%#D\"" - --#: cp/name-lookup.c:3268 -+#: cp/name-lookup.c:3273 - #, gcc-internal-format - msgid "no members matching %<%T::%D%> in %q#T" - msgstr "" - --#: cp/name-lookup.c:3355 -+#: cp/name-lookup.c:3360 - #, gcc-internal-format - msgid "declaration of %qD not in a namespace surrounding %qD" - msgstr "" - --#: cp/name-lookup.c:3363 -+#: cp/name-lookup.c:3368 - #, fuzzy, gcc-internal-format - msgid "explicit qualification in declaration of %qD" - msgstr "паўторнае абвяшчэнне меткі \"%s\"" - --#: cp/name-lookup.c:3446 -+#: cp/name-lookup.c:3451 - #, gcc-internal-format - msgid "%qD should have been declared inside %qD" - msgstr "" - --#: cp/name-lookup.c:3490 -+#: cp/name-lookup.c:3495 - #, gcc-internal-format - msgid "%qD attribute requires a single NTBS argument" - msgstr "" - --#: cp/name-lookup.c:3497 -+#: cp/name-lookup.c:3502 - #, gcc-internal-format - msgid "%qD attribute is meaningless since members of the anonymous namespace get local symbols" - msgstr "" - --#: cp/name-lookup.c:3505 cp/name-lookup.c:3894 -+#: cp/name-lookup.c:3510 cp/name-lookup.c:3899 - #, fuzzy, gcc-internal-format - #| msgid "`%s' attribute ignored" - msgid "%qD attribute directive ignored" - msgstr "\"%s\" атрыбут ігнарыруецца" - --#: cp/name-lookup.c:3550 -+#: cp/name-lookup.c:3555 - #, fuzzy, gcc-internal-format - msgid "namespace alias %qD not allowed here, assuming %qD" - msgstr "\"%s\" - гэта не пачатак дэкларацыі" - --#: cp/name-lookup.c:3882 -+#: cp/name-lookup.c:3887 - #, gcc-internal-format - msgid "strong using only meaningful at namespace scope" - msgstr "" - --#: cp/name-lookup.c:3886 -+#: cp/name-lookup.c:3891 - #, gcc-internal-format - msgid "current namespace %qD does not enclose strongly used namespace %qD" - msgstr "" - --#: cp/name-lookup.c:4224 -+#: cp/name-lookup.c:4229 - #, gcc-internal-format - msgid "maximum limit of %d namespaces searched for %qE" - msgstr "" - --#: cp/name-lookup.c:4234 -+#: cp/name-lookup.c:4239 - #, gcc-internal-format - msgid "suggested alternative:" - msgid_plural "suggested alternatives:" - msgstr[0] "" - msgstr[1] "" - --#: cp/name-lookup.c:4238 -+#: cp/name-lookup.c:4243 - #, gcc-internal-format - msgid " %qE" - msgstr "" - --#: cp/name-lookup.c:5494 -+#: cp/name-lookup.c:5499 - #, gcc-internal-format - msgid "argument dependent lookup finds %q+D" - msgstr "" - --#: cp/name-lookup.c:5990 -+#: cp/name-lookup.c:5995 - #, gcc-internal-format - msgid "XXX entering pop_everything ()\n" - msgstr "" - --#: cp/name-lookup.c:5999 -+#: cp/name-lookup.c:6004 - #, gcc-internal-format - msgid "XXX leaving pop_everything ()\n" - msgstr "" -@@ -31541,7 +31536,7 @@ - msgid "floating-point literal cannot appear in a constant-expression" - msgstr "" - --#: cp/parser.c:2645 cp/pt.c:13536 -+#: cp/parser.c:2645 cp/pt.c:13562 - #, gcc-internal-format - msgid "a cast to a type other than an integral or enumeration type cannot appear in a constant-expression" - msgstr "" -@@ -31772,7 +31767,7 @@ - msgid "literal operator suffixes not preceded by %<_%> are reserved for future standardization" - msgstr "" - --#: cp/parser.c:4841 cp/parser.c:16238 -+#: cp/parser.c:4841 cp/parser.c:16241 - #, gcc-internal-format - msgid "expected unqualified-id" - msgstr "" -@@ -31967,7 +31962,7 @@ - msgid "compound-statement in constexpr function" - msgstr "вельмі шмат аргументаў у функцыі" - --#: cp/parser.c:9160 cp/parser.c:22274 -+#: cp/parser.c:9160 cp/parser.c:22269 - #, fuzzy, gcc-internal-format - #| msgid "empty body in an else-statement" - msgid "expected selection-statement" -@@ -31998,7 +31993,7 @@ - msgid "inconsistent begin/end types in range-based % statement: %qT and %qT" - msgstr "" - --#: cp/parser.c:9749 cp/parser.c:22277 -+#: cp/parser.c:9749 cp/parser.c:22272 - #, fuzzy, gcc-internal-format - #| msgid "empty body in an else-statement" - msgid "expected iteration-statement" -@@ -32015,12 +32010,12 @@ - msgid "ISO C++ forbids computed gotos" - msgstr "" - --#: cp/parser.c:9931 cp/parser.c:22280 -+#: cp/parser.c:9931 cp/parser.c:22275 - #, gcc-internal-format - msgid "expected jump-statement" - msgstr "" - --#: cp/parser.c:10063 cp/parser.c:18871 -+#: cp/parser.c:10063 cp/parser.c:18866 - #, gcc-internal-format - msgid "extra %<;%>" - msgstr "" -@@ -32057,7 +32052,7 @@ - msgid "class definition may not be declared a friend" - msgstr "віртуальныя функцыі не могуць быць сяброўскімі" - --#: cp/parser.c:10847 cp/parser.c:19243 -+#: cp/parser.c:10847 cp/parser.c:19238 - #, gcc-internal-format - msgid "templates may not be %" - msgstr "" -@@ -32134,12 +32129,12 @@ - msgid "keyword % not implemented, and will be ignored" - msgstr "" - --#: cp/parser.c:12115 cp/parser.c:12213 cp/parser.c:12320 cp/parser.c:17340 -+#: cp/parser.c:12115 cp/parser.c:12213 cp/parser.c:12320 cp/parser.c:17343 - #, fuzzy, gcc-internal-format - msgid "template parameter pack %qD cannot have a default argument" - msgstr "віртуальныя функцыі не могуць быць сяброўскімі" - --#: cp/parser.c:12119 cp/parser.c:17348 -+#: cp/parser.c:12119 cp/parser.c:17351 - #, fuzzy, gcc-internal-format - msgid "template parameter pack cannot have a default argument" - msgstr "віртуальныя функцыі не могуць быць сяброўскімі" -@@ -32154,7 +32149,7 @@ - msgid "expected template-id" - msgstr "" - --#: cp/parser.c:12453 cp/parser.c:22238 -+#: cp/parser.c:12453 cp/parser.c:22233 - #, gcc-internal-format - msgid "expected %<<%>" - msgstr "" -@@ -32282,12 +32277,12 @@ - msgid "cannot add an enumerator list to a template instantiation" - msgstr "" - --#: cp/parser.c:14493 cp/parser.c:18444 -+#: cp/parser.c:14493 cp/parser.c:18431 - #, gcc-internal-format - msgid "declaration of %qD in namespace %qD which does not enclose %qD" - msgstr "" - --#: cp/parser.c:14498 cp/parser.c:18449 -+#: cp/parser.c:14498 cp/parser.c:18436 - #, gcc-internal-format - msgid "declaration of %qD in %qD which does not enclose %qD" - msgstr "" -@@ -32334,75 +32329,75 @@ - msgid "access declarations are deprecated in favour of using-declarations; suggestion: add the % keyword" - msgstr "" - --#: cp/parser.c:15094 -+#: cp/parser.c:15097 - #, gcc-internal-format - msgid "types may not be defined in alias template declarations" - msgstr "" - --#: cp/parser.c:15541 -+#: cp/parser.c:15544 - #, fuzzy, gcc-internal-format - msgid "a function-definition is not allowed here" - msgstr "атрыбуты секцыі не падтрымліваюцца для гэтай мэты" - --#: cp/parser.c:15553 -+#: cp/parser.c:15556 - #, gcc-internal-format - msgid "an asm-specification is not allowed on a function-definition" - msgstr "" - --#: cp/parser.c:15557 -+#: cp/parser.c:15560 - #, fuzzy, gcc-internal-format - msgid "attributes are not allowed on a function-definition" - msgstr "\"%s\" - гэта не пачатак дэкларацыі" - --#: cp/parser.c:15594 -+#: cp/parser.c:15597 - #, gcc-internal-format - msgid "expected constructor, destructor, or type conversion" - msgstr "" - - #. Anything else is an error. --#: cp/parser.c:15629 cp/parser.c:17509 -+#: cp/parser.c:15632 cp/parser.c:17512 - #, fuzzy, gcc-internal-format - #| msgid "invalid initializer" - msgid "expected initializer" - msgstr "нерэчаісны ініцыялізатар" - --#: cp/parser.c:15649 -+#: cp/parser.c:15652 - #, fuzzy, gcc-internal-format - #| msgid "Invalid declaration" - msgid "invalid type in declaration" - msgstr "Нерэчаіснае абвяшчэнне" - --#: cp/parser.c:15725 -+#: cp/parser.c:15728 - #, fuzzy, gcc-internal-format - msgid "initializer provided for function" - msgstr "не магу ініцыялізаваць сяброўскую функцыю \"%s\"" - --#: cp/parser.c:15757 -+#: cp/parser.c:15760 - #, gcc-internal-format - msgid "attributes after parenthesized initializer ignored" - msgstr "" - --#: cp/parser.c:16161 -+#: cp/parser.c:16164 - #, fuzzy, gcc-internal-format - msgid "array bound is not an integer constant" - msgstr "памер масіва \"%s\" адмоўны" - --#: cp/parser.c:16282 -+#: cp/parser.c:16285 - #, gcc-internal-format - msgid "cannot define member of dependent typedef %qT" - msgstr "" - --#: cp/parser.c:16286 -+#: cp/parser.c:16289 - #, fuzzy, gcc-internal-format - msgid "%<%T::%E%> is not a type" - msgstr "\"%s\" мае незавершаны тып" - --#: cp/parser.c:16314 -+#: cp/parser.c:16317 - #, fuzzy, gcc-internal-format - msgid "invalid use of constructor as a template" - msgstr "нявернае выкарыстанне \"restict\"" - --#: cp/parser.c:16316 -+#: cp/parser.c:16319 - #, gcc-internal-format - msgid "use %<%T::%D%> instead of %<%T::%D%> to name the constructor in a qualified name" - msgstr "" -@@ -32411,253 +32406,253 @@ - #. here because we do not have enough - #. information about its original syntactic - #. form. --#: cp/parser.c:16333 -+#: cp/parser.c:16336 - #, gcc-internal-format - msgid "invalid declarator" - msgstr "нерэчаісны абвяшчальнік" - --#: cp/parser.c:16399 -+#: cp/parser.c:16402 - #, fuzzy, gcc-internal-format - #| msgid "empty declaration" - msgid "expected declarator" - msgstr "пустое абвяшчэньне" - --#: cp/parser.c:16494 -+#: cp/parser.c:16497 - #, gcc-internal-format - msgid "%qD is a namespace" - msgstr "" - --#: cp/parser.c:16496 -+#: cp/parser.c:16499 - #, gcc-internal-format - msgid "cannot form pointer to member of non-class %q#T" - msgstr "" - --#: cp/parser.c:16513 -+#: cp/parser.c:16516 - #, gcc-internal-format - msgid "expected ptr-operator" - msgstr "" - --#: cp/parser.c:16572 -+#: cp/parser.c:16575 - #, fuzzy, gcc-internal-format - #| msgid "duplicate `volatile'" - msgid "duplicate cv-qualifier" - msgstr "паўтарэнне \"volatile\"" - --#: cp/parser.c:16630 -+#: cp/parser.c:16633 - #, fuzzy, gcc-internal-format - #| msgid "duplicate `volatile'" - msgid "duplicate virt-specifier" - msgstr "паўтарэнне \"volatile\"" - --#: cp/parser.c:16792 cp/typeck2.c:450 cp/typeck2.c:1670 -+#: cp/parser.c:16795 cp/typeck2.c:450 cp/typeck2.c:1673 - #, fuzzy, gcc-internal-format - #| msgid "invalid use of `%D'" - msgid "invalid use of %" - msgstr "нерэчаіснае выкарыстаньне `%D'" - --#: cp/parser.c:16811 -+#: cp/parser.c:16814 - #, gcc-internal-format - msgid "types may not be defined in template arguments" - msgstr "" - --#: cp/parser.c:16892 -+#: cp/parser.c:16895 - #, gcc-internal-format - msgid "expected type-specifier" - msgstr "" - --#: cp/parser.c:17136 -+#: cp/parser.c:17139 - #, gcc-internal-format - msgid "expected %<,%> or %<...%>" - msgstr "" - --#: cp/parser.c:17193 -+#: cp/parser.c:17196 - #, gcc-internal-format - msgid "types may not be defined in parameter types" - msgstr "" - --#: cp/parser.c:17319 -+#: cp/parser.c:17322 - #, gcc-internal-format - msgid "deprecated use of default argument for parameter of non-function" - msgstr "" - --#: cp/parser.c:17323 -+#: cp/parser.c:17326 - #, gcc-internal-format - msgid "default arguments are only permitted for function parameters" - msgstr "" - --#: cp/parser.c:17342 -+#: cp/parser.c:17345 - #, gcc-internal-format - msgid "parameter pack %qD cannot have a default argument" - msgstr "" - --#: cp/parser.c:17350 -+#: cp/parser.c:17353 - #, gcc-internal-format - msgid "parameter pack cannot have a default argument" - msgstr "" - --#: cp/parser.c:17637 -+#: cp/parser.c:17640 - #, gcc-internal-format - msgid "ISO C++ does not allow designated initializers" - msgstr "" - --#: cp/parser.c:17651 -+#: cp/parser.c:17654 - #, gcc-internal-format - msgid "ISO C++ does not allow C99 designated initializers" - msgstr "" - --#: cp/parser.c:17755 cp/parser.c:17879 -+#: cp/parser.c:17758 cp/parser.c:17882 - #, gcc-internal-format - msgid "expected class-name" - msgstr "" - --#: cp/parser.c:18067 -+#: cp/parser.c:18056 - #, gcc-internal-format - msgid "expected %<;%> after class definition" - msgstr "" - --#: cp/parser.c:18069 -+#: cp/parser.c:18058 - #, gcc-internal-format - msgid "expected %<;%> after struct definition" - msgstr "" - --#: cp/parser.c:18071 -+#: cp/parser.c:18060 - #, gcc-internal-format - msgid "expected %<;%> after union definition" - msgstr "" - --#: cp/parser.c:18392 -+#: cp/parser.c:18379 - #, gcc-internal-format - msgid "expected %<{%> or %<:%>" - msgstr "" - --#: cp/parser.c:18403 -+#: cp/parser.c:18390 - #, fuzzy, gcc-internal-format - #| msgid "cannot find file for class %s" - msgid "cannot specify % for a class" - msgstr "немагчыма знайсьці файл для кляса %s" - --#: cp/parser.c:18411 -+#: cp/parser.c:18398 - #, gcc-internal-format - msgid "global qualification of class name is invalid" - msgstr "" - --#: cp/parser.c:18418 -+#: cp/parser.c:18405 - #, gcc-internal-format - msgid "qualified name does not name a class" - msgstr "" - --#: cp/parser.c:18430 -+#: cp/parser.c:18417 - #, fuzzy, gcc-internal-format - msgid "invalid class name in declaration of %qD" - msgstr "Нерэчаіснае абвяшчэнне" - --#: cp/parser.c:18463 -+#: cp/parser.c:18450 - #, gcc-internal-format - msgid "extra qualification not allowed" - msgstr "" - --#: cp/parser.c:18475 -+#: cp/parser.c:18462 - #, fuzzy, gcc-internal-format - msgid "an explicit specialization must be preceded by %