diff -Nru gcc-4.7-4.7.2/debian/changelog gcc-4.7-4.7.3/debian/changelog --- gcc-4.7-4.7.2/debian/changelog 2013-07-25 18:49:32.000000000 +0000 +++ gcc-4.7-4.7.3/debian/changelog 2013-07-25 18:49:34.000000000 +0000 @@ -1,8 +1,770 @@ -gcc-4.7 (4.7.2-2ubuntu1~precise) precise; urgency=low +gcc-4.7 (4.7.3-2ubuntu1~12.04) precise; urgency=low - * Build for precise + * PPA upload. - -- Michael R. Crusoe Thu, 15 Nov 2012 02:20:58 -0700 + -- Matthias Klose Sun, 21 Apr 2013 19:53:11 +0200 + +gcc-4.7 (4.7.3-2ubuntu1) raring; urgency=low + + * Merge with Debian; remaining changes: + - Build from upstream source. + * Re-enable Linaro changes which were reverted in 4.7.3-1ubuntu1. + + -- Matthias Klose Sun, 21 Apr 2013 19:24:42 +0200 + +gcc-4.7 (4.7.3-2) experimental; urgency=low + + * Update to SVN 20130421 (r198115) from the gcc-4_7-branch. + - Fix PR libstdc++/54847, PR debug/53453, PR target/56890 (sparc), + PR target/55487 (parisc), PR c++/56388, PR fortran/56994, + PR middle-end/56848, PR middle-end/56077, PR tree-optimization/48189. + * Use target specific names for libstdc++ baseline files. LP: #1168267. + * Fix control file for builds without the x32 multilibs + * Ignore the return value for dh_shlibdeps for builds on precise/ARM. + * In gnatlink, pass the options and libraries after objects to the + linker to avoid link failures with --as-needed. Addresses: #680292. + + -- Matthias Klose Sun, 21 Apr 2013 14:54:57 +0200 + +gcc-4.7 (4.7.3-1ubuntu1) raring; urgency=low + + * Merge with Debian; remaining changes: + - Build from upstream source. + * Revert Linaro changes for this upload: + - Revert the partial backport Vectorizer Cost Model for ARM. + * Use target specific names for libstdc++ baseline files. LP: #1168267. + + -- Matthias Klose Fri, 12 Apr 2013 13:17:16 +0200 + +gcc-4.7 (4.7.3-1) experimental; urgency=low + + * GCC 4.7.3 release. + - Fix PR middle-end/56848, reverting the fix for PR middle-end/56077. + * Refresh patches. + * Update the Linaro support to the 4.7-2013.04 release. + - Merges from the arm/aarch64-4.7-branch branch. + - Partial backport Vectorizer Cost Model for ARM. + - Backport "Turn off 64bits ops in Neon" from mainline. + + -- Matthias Klose Thu, 11 Apr 2013 12:19:03 +0200 + +gcc-4.7 (4.7.2-24) experimental; urgency=low + + * Fix PR middle-end/56848, reverting the fix for PR middle-end/56077. + + -- Matthias Klose Fri, 05 Apr 2013 19:56:11 +0200 + +gcc-4.7 (4.7.2-23ubuntu2) raring; urgency=low + + * Fix PR middle-end/56848, reverting the fix for PR middle-end/56077. + LP: #1164886. + + -- Matthias Klose Fri, 05 Apr 2013 12:13:56 +0200 + +gcc-4.7 (4.7.2-23ubuntu2~r197382) raring; urgency=low + + * Merge with Debian; remaining changes: + - Build from upstream source. + + -- Matthias Klose Thu, 04 Apr 2013 13:23:14 +0200 + +gcc-4.7 (4.7.2-23) experimental; urgency=low + + * Update to SVN 20130404 (r197476) from the gcc-4_7-branch (4.7.3 release + candidate 1). + - Fix PR libstdc++/56012, PR libstdc++/56011, PR target/56529 (SH), + PR tree-optimization/55481, PR middle-end/52888, PR target/56351 (ARM), + PR tree-optimization/56443, PR c++/56543, PR lto/50293, PR c++/56614, + PR c++/56403, PR c++/56534, PR ada/52123, PR fortran/56575, + PR fortran/55362, PR libstdc++/56468, PR libstdc++/56002, + PR target/49880 (SH), PR tree-optimization/56608, PR target/56470 (ARM), + PR tree-optimization/56270, PR target/56560 (x86), PR bootstrap/56258, + PR c++/54277, PR c++/56646, PR fortran/56615, PR tree-optimization/56501, + PR tree-optimization/56539, PR debug/56510, PR middle-end/56768, + PR middle-end/45472, PR middle-end/56461, PR middle-end/55889, + PR middle-end/56077, PR debug/56819, PR c++/56794, PR c++/56774, + PR c++/35722, PR fortran/56737, PR fortran/56737, PR fortran/56735, + PR target/56771. + * Fix PR rtl-optimization/56484 (Venkataramanan Kumar, Linaro only). + LP: #1135633. + * Update the Linaro support to the 4.7-2013.03 release. + + -- Matthias Klose Thu, 04 Apr 2013 13:06:02 +0200 + +gcc-4.7 (4.7.2-22ubuntu5) raring; urgency=low + + * Update to SVN 20130328 (r197184) from the gcc-4_7-branch. + - Fix PR libstdc++/56468, PR libstdc++/56002, + PR target/49880 (SH), PR tree-optimization/56608, PR target/56470 (ARM), + PR tree-optimization/56270, PR target/56560 (x86), PR bootstrap/56258, + PR c++/54277, PR c++/56646, PR fortran/56615. + + -- Matthias Klose Thu, 28 Mar 2013 03:30:49 +0100 + +gcc-4.7 (4.7.2-22ubuntu4) raring; urgency=low + + * Update the Linaro support to the 4.7-2013.03 release. + - Aarch64 updates. + + -- Matthias Klose Thu, 14 Mar 2013 20:52:50 -0700 + +gcc-4.7 (4.7.2-22ubuntu3) raring; urgency=low + + * Update to SVN 20130307 (r196523) from the gcc-4_7-branch. + - Fix PR libstdc++/56012, PR libstdc++/56011, PR target/56529 (SH), + PR tree-optimization/55481, PR middle-end/52888, PR target/56351 (ARM), + PR tree-optimization/56443, PR c++/56543, PR lto/50293, PR c++/56614, + PR c++/56403, PR c++/56534, PR ada/52123, PR fortran/56575, + PR fortran/55362. + * Fix PR rtl-optimization/56484 (Venkataramanan Kumar, Linaro only). + LP: #1135633. + + -- Matthias Klose Fri, 08 Mar 2013 00:40:18 +0800 + +gcc-4.7 (4.7.2-22ubuntu2) raring; urgency=low + + * Build arm64 from the Linaro branch again. + + -- Matthias Klose Tue, 26 Feb 2013 07:55:17 +0100 + +gcc-4.7 (4.7.2-22ubuntu1) raring; urgency=low + + * Merge with Debian; remaining changes: + - Build from upstream source. + + -- Matthias Klose Sat, 23 Feb 2013 06:43:05 +0100 + +gcc-4.7 (4.7.2-22) experimental; urgency=low + + * Update to SVN 20130222 (r196236) from the gcc-4_7-branch. + - Fix PR rtl-optimization/56275, PR target/56043, PR c++/56268, + PR c++/56247, PR target/52122, PR c++/56291, PR target/52123, + PR target/52122, PR c++/54276, PR c++/52026, PR c++/55710, PR c++/56135, + PR fortran/53537, PR middle-end/56217, PR libstdc++/55043, + PR other/56245, PR bootstrap/56258, PR tree-optimization/56350, + PR tree-optimization/56381, PR tree-optimization/56250, + PR middle-end/56217, PR tree-optimization/55110, PR c++/40405, + PR c++/56395, PR c++/56241, PR c++/56239, PR c++/56237, PR ada/56271, + PR fortran/56385, PR libfortran/30162. + * Revert the fix for PR optimization/53844. LP: #1123588. + * Update the Linaro support to the 4.7-2013.02 release. + + -- Matthias Klose Sat, 23 Feb 2013 06:28:17 +0100 + +gcc-4.7 (4.7.2-21ubuntu3) raring; urgency=low + + * Update to SVN 20130214 (r196053) from the gcc-4_7-branch. + - Fix PR c++/56291, PR target/52123, PR target/52122. + * Update the Linaro support to the 4.7-2013.02 release. + + -- Matthias Klose Thu, 14 Feb 2013 19:11:22 +0100 + +gcc-4.7 (4.7.2-21ubuntu2) raring; urgency=low + + * Update to SVN 20130212 (r195985) from the gcc-4_7-branch. + - Fix PR rtl-optimization/56275, PR target/56043, PR c++/56268, + PR c++/56247, PR target/52122. + * Revert the fix for PR optimization/53844. LP: #1123588. + + -- Matthias Klose Wed, 13 Feb 2013 01:16:12 +0100 + +gcc-4.7 (4.7.2-21ubuntu1) raring; urgency=low + + * Merge with Debian; remaining changes: + - Build from upstream source. + + -- Matthias Klose Fri, 08 Feb 2013 23:59:10 +0100 + +gcc-4.7 (4.7.2-21) experimental; urgency=low + + * Update to SVN 20130208 (r195898) from the gcc-4_7-branch. + - Fix PR libgomp/51376, PR libgomp/56073, PR libquadmath/56072, + PR other/54620, PR target/39064, PR other/53413, PR other/53285, + PR bootstrap/56227, PR target/53040, PR tree-optimization/55107, + PR tree-optimization/54767, PR tree-optimization/44061, PR lto/55660, + PR middle-end/55890, PR tree-optimization/53844, PR middle-end/55890, + PR tree-optimization/56125, PR tree-optimization/56098, PR target/49069, + PR tree-optimization/56051, PR middle-end/56015, PR target/55940, + PR tree-optimization/55921, PR rtl-optimization/55838, PR c++/54046, + PR middle-end/55094, PR tree-optimization/55236, + PR rtl-optimization/54127, PR c++/54122, PR c++/55652, PR c++/54207, + PR c++/55542, PR c++/54046, PR target/50678, PR fortran/50627, + PR fortran/56054, PR fortran/56052, PR bootstrap/56227, + PR tree-optimization/56051, PR middle-end/56015, PR target/55940, + PR tree-optimization/55921, PR rtl-optimization/55838, PR c++/54046, + PR middle-end/55094, PR tree-optimization/55236, + PR rtl-optimization/54127, PR c++/54122, PR c++/55652, PR c++/54207, + PR c++/55542, PR c++/54046, PR target/50678, PR fortran/50627, + PR fortran/56054, PR fortran/56052, PR bootstrap/56227. + + [ Thibaut Girka ] + * Fix dh_shlibdeps and dh_gencontrol cross-build mangling for + libgfortran-dev packages. + + [ Matthias Klose ] + * Fix dh_shlibdeps calls for the libgo packages. + * Use the CLooG PPL 1.0 backend for graphite. + + -- Matthias Klose Fri, 08 Feb 2013 21:04:54 +0100 + +gcc-4.7 (4.7.2-20ubuntu1) raring; urgency=low + + * Merge with Debian; remaining changes: + - Build from upstream source. + + -- Matthias Klose Wed, 30 Jan 2013 02:46:31 +0100 + +gcc-4.7 (4.7.2-20) experimental; urgency=low + + * Update to SVN 20130130 (r195565) from the gcc-4_7-branch. + - Fix PR libstdc++/56085, PR target/56114, PR target/56028, + PR tree-optimization/55755, PR rtl-optimization/56023, + PR tree-optimization/55264, PR target/55981, PR c++/56104, PR c++/53650, + PR c++/56071, PR c++/56059, PR fortran/56081, PR tree-optimization/56113, + PR target/35294 (ARM). + + [ Matthias Klose ] + * Fix MULTILIB_OS_DIRNAME for the default multilib on x32. + * Bump dependencies on cloog/ppl. + * Add a Build-Using attribute for each binary package, which can be + built from the gcc-4.7-source package (patch derived from a proposal by + Ansgar Burchardt). + - Use it for cross-compiler packages. + - Not yet used when building gcj, gdc or gnat using the gcc-source package. + These packages don't require an exact version of the gcc-source package, + but just a versions which is specifed by the build dependencies. + + [ Thibaut Girka ] + * Fix regexp used to list patched autotools files. + + -- Matthias Klose Wed, 30 Jan 2013 01:04:15 +0100 + +gcc-4.7 (4.7.2-19ubuntu1) raring; urgency=low + + * Merge with Debian; remaining changes: + - Build from upstream source. + + -- Matthias Klose Thu, 17 Jan 2013 21:47:02 +0100 + +gcc-4.7 (4.7.2-19) experimental; urgency=low + + * Update to SVN 20130117 (r195280) from the gcc-4_7-branch. + - Fix PR target/55974 (AVR), PR fortran/55072, PR fortran/55618, + PR libstdc++/52887, PR fortran/55983. + - Backport multiarch patches. + * Update the Linaro support to the 4.7-2013.01 release. + + * Don't call dh_shlibdeps for staged cross builds. These packages + are never shipped, and the information is irrelevant. + * Don't ship libiberty.a in gcc-4.7-hppa64. Closes: #659556. + * Fix dependency on the non-default multilib libc-dev. LP: #1100894. + + -- Matthias Klose Thu, 17 Jan 2013 21:48:29 +0100 + +gcc-4.7 (4.7.2-18ubuntu1) raring; urgency=low + + * Merge with Debian; remaining changes: + - Build from upstream source. + + -- Matthias Klose Fri, 11 Jan 2013 18:31:24 +0100 + +gcc-4.7 (4.7.2-18) experimental; urgency=low + + * Update to SVN 20130111 (r195107) from the gcc-4_7-branch. + - Fix PR c++/55877, PR target/55897, PR target/54461, PR other/55243, + PR target/55712, PR fortran/42769, PR fortran/45836, PR fortran/45900, + PR fortran/55852, PR fortran/55827, PR c++/55893. + * Explicitly search multiarch and multilib system directories when + calling dh_shlibdeps. + * Let gjdoc accept -source 1.5|1.6|1.7. Addresses: #678945. + * Fix build configured with --enable-java-maintainer-mode. + * Don't ship .md5 files in the libstdc++-doc package. + * Always configure --with-system-zlib. + * Search library dependencies in the build-sysroot too. + * Don't complain about missing .substvars files when trying to mangle + these files. + * Add ARM multilib packages to the control file for staged cross builds. + * Fix ARM multilib shlibs dependency generation for cross builds. + + -- Matthias Klose Fri, 11 Jan 2013 17:18:23 +0100 + +gcc-4.7 (4.7.2-17ubuntu2) raring; urgency=low + + * Update to SVN 20130105 (r194933) from the gcc-4_7-branch. + - Fix PR c++/55877. + * Explicitly search multiarch and multilib system directories when + calling dh_shlibdeps. + * Let gjdoc accept -source 1.5|1.6|1.7. Addresses: #678945. + * Fix build configured with --enable-java-maintainer-mode. + * Don't ship .md5 files in the libstdc++-doc package. + * Always configure --with-system-zlib. + + -- Matthias Klose Sat, 05 Jan 2013 20:28:47 +0100 + +gcc-4.7 (4.7.2-17ubuntu1) raring; urgency=low + + * Merge with Debian; remaining changes: + - Build from upstream source. + + -- Matthias Klose Fri, 04 Jan 2013 16:42:31 +0100 + +gcc-4.7 (4.7.2-17) experimental; urgency=low + + * Update to SVN 20130104 (r194901) from the gcc-4_7-branch. + - Fix PR target/53789 (hppa), PR bootstrap/55707, PR c++/55804, + PR tree-optimization/55355, PR c++/55419, PR c++/55753, PR c++/55842, + PR c++/55856, PR c++/54325, PR c++/55032, PR c++/55245, PR c++/55724, + PR ada/53737, PR fortran/54818, PR libfortran/30162. + + [ Matthias Klose ] + * Move .jar symlinks from the -jre-lib into the -jre-headless package. + * Keep the debug link for libstdc++6. Closes: #696854. + * Fix libstdc++ symbols files for sparc 128bit symbols. + * Keep the rt.jar symlink in the gcj-jre-headless package. + + [ Thibaut Girka ] + * Prepare for optional dependencies on the packages built on the + target architecture. + * When using the above, + - use the same settings for gcc_lib_dir, sysroot, header and C++ header + locations as for the native build. + - install libraries into the multiarch directories. + - use cpp-4.x- instead of gcc-4.x-base to collect doc files. + + -- Matthias Klose Fri, 04 Jan 2013 16:24:21 +0100 + +gcc-4.7 (4.7.2-16ubuntu1) raring; urgency=low + + * Fix libc6 multilib dependencies on armhf. + + -- Matthias Klose Tue, 18 Dec 2012 14:10:51 +0100 + +gcc-4.7 (4.7.2-16) experimental; urgency=low + + * Allow building a gcj cross compiler. + * Fix libobjc-dbg dependencies on libgcc-dbg packages. + + -- Matthias Klose Mon, 17 Dec 2012 15:58:31 +0100 + +gcc-4.7 (4.7.2-15ubuntu1) raring; urgency=low + + * Merge with Debian; remaining changes: + - Build from upstream source. + + -- Matthias Klose Mon, 17 Dec 2012 14:57:14 +0100 + +gcc-4.7 (4.7.2-15) experimental; urgency=low + + * Update to SVN 20121217 (r194553) from the gcc-4_7-branch. + - Fix PR libstdc++/55631, PR middle-end/55492, PR target/54121, + PR c++/54883, PR c++/55643, PR target/55673, PR ada/54614, PR ada/53766. + + [ Matthias Klose ] + * Drop build-dependency on libelf. + * Drop the g++-multilib build dependency, use the built compiler to + check which multilib variants can be run. Provide an asm symlink for + the build. + * Stop configuring cross compilers --with-headers --with-libs. + * Always call dh_shlibdeps with -l, pointing to the correct dependency + packages. + * Fix cross build stage1 package installation, only including the target + files in the gcc package. + * Explicitly configure with --enable-multiarch when doing builds + supporting the multiarch layout. + * Only configure --with-sysroot, --with-build-sysroot when values are set. + * Revert: For stage1 builds, include gcc_lib_dir files in the gcc package. + * Allow multilib enabled stage1 and stage2 cross builds. + * libgcc backports from the trunk: + - Always define USE_PT_GNU_EH_FRAME in crtstuff.c for glibc. + - Build static libgcc with hidden visibility even with --disable-shared. + * Don't check glibc version to configure --with-long-double-128. + * Don't auto-detect multilib osdirnames. + * Don't set a LD_LIBRARY_PATH when calling dh_shlibdeps in cross builds. + * Pretend that wheezy has x32 support (sid is now known as wheezy :-/). + + [ Thibaut Girka ] + * Call $(cross_gencontrol) dh_gencontrol bulding libgfortran-dev. + * Set MULTIARCH_DIRNAME for builds configured with --disable-multilib + on mips and s390. + + -- Matthias Klose Mon, 17 Dec 2012 14:12:49 +0100 + +gcc-4.7 (4.7.2-14ubuntu2) raring; urgency=low + + * Update to SVN 20121214 (r194398) from the gcc-4_7-branch. + - Fix PR libstdc++/55631, PR middle-end/55492, PR target/54121, + PR c++/54883, PR c++/55643. + + [ Matthias Klose ] + * Drop build-dependency on libelf. + * Drop the g++-multilib build dependency, use the built compiler to + check which multilib variants can be run. Provide an asm symlink for + the build. + * Stop configuring cross compilers --with-headers --with-libs. + * Always call dh_shlibdeps with -l, pointing to the correct dependency + packages. + * Fix cross build stage1 package installation, only including the target + files in the gcc package. + + [ Thibaut Girka ] + * Call $(cross_gencontrol) dh_gencontrol bulding libgfortran-dev. + * Set MULTIARCH_DIRNAME for builds configured with --disable-multilib + on mips and s390. + + -- Matthias Klose Fri, 14 Dec 2012 14:50:51 +0100 + +gcc-4.7 (4.7.2-14ubuntu1) raring; urgency=low + + * Merge with Debian; remaining changes: + - Build from upstream source. + + -- Matthias Klose Tue, 11 Dec 2012 09:03:32 +0100 + +gcc-4.7 (4.7.2-14) experimental; urgency=low + + * Update to SVN 20121211 (r194382) from the gcc-4_7-branch. + - Fix PR target/55344, PR target/53912. + * Update the Linaro support to a 4.7-2012.12 pre-release. + * Fix spu cross build on powerpc/ppc64. + * Make libgcj packages Multi-Arch: same, append the Debian architecture + name to the gcj java home. + * Don't encode versioned build dependencies on binutils and dpkg-dev in + the control file (makes the package cross-buildable). + * Drop the versioned build dependency on make (>= 3.81). + * Only include gengtype for native builds. Needs upstream changes. + See #645018. + * Build fixes for libstdc++ and libgo, when cross building the native + compiler. + * When cross building the native compiler, configure --with-sysroot=/ + and without --without-ppl. + * Fix package builds with the common libraries provided by a newer + gcc-X.Y package. + * Stop building packages now built from gcc-4.8 in experimental. + + -- Matthias Klose Tue, 11 Dec 2012 08:49:17 +0100 + +gcc-4.7 (4.7.2-13) experimental; urgency=low + + * Update to SVN 20121208 (r194323) from the gcc-4_7-branch. + - Fix PR libstdc++/55503, PR libgcc/48076, PR c/55570, + PR tree-optimization/53663, PR target/53912, PR target/55195, + PR target/55171, PR lto/54795, PR lto/55474, PR rtl-optimization/55489, + PR c++/53137, PR c++/53862, PR c++/53039, PR c++/50852, PR c++/53039, + PR c++/55032, PR c++/54325, PR c++/55058, PR c++/55249, PR c++/54744, + PR c++/54947, PR c++/55015, PR c++/53821, PR c++/55419, PR ada/52110, + bootstrap/55571, PR target/55597. + * Point to gcc's README.Bugs when building gcj packages. Closes: #623987. + * Re-enable the patch to add options -fuse-ld=gold and -fuse-ld=bfd. Keep + -fuse-ld=ld.bfd as an alias. + * For cross builds, don't use the multiarch location for the C++ headers. + * For cross builds, fix multilib inter package dependencies. + * For cross builds, fix libc6 dependencies for non-default multilib packages. + * Aarch64 updates, taken from the Linaro branch. + * Only run the libgo testsuite for flags configured in RUNTESTFLAGS. + * Remove the cross-includes patch, not needed anymore with --with-sysroot=/. + * For cross builds, install into /usr/lib/gcc-cross to avoid file conflicts + with the native compiler for the target architecture. + * For cross builds, don't add /usr/local/include to the standard include + path, however /usr/local/include/ is still on the path. + * For cross builds, provide symbols files based on the symbols files for + the native build. Not picked up by dh_makeshlibs yet. + + -- Matthias Klose Sat, 08 Dec 2012 14:52:45 +0100 + +gcc-4.7 (4.7.2-12ubuntu2) raring; urgency=low + + * Update to SVN 20121205 (r194220) from the gcc-4_7-branch. + - Fix PR libstdc++/55503, PR libgcc/48076, PR c/55570, + PR tree-optimization/53663, PR target/53912, PR target/55195, + PR target/55171, PR lto/54795, PR lto/55474, PR rtl-optimization/55489, + PR c++/53137, PR c++/53862, PR c++/53039, PR c++/50852, PR c++/53039, + PR ada/52110, bootstrap/55571. + * Point to gcc's README.Bugs when building gcj packages. Closes: #623987. + * Re-enable the patch to add options -fuse-ld=gold and -fuse-ld=bfd. Keep + -fuse-ld=ld.bfd as an alias. + * For cross builds, don't use the multiarch location for the C++ headers. + * Split out a gccgo-4.7-doc package. + + -- Matthias Klose Wed, 05 Dec 2012 13:31:27 +0100 + +gcc-4.7 (4.7.2-12ubuntu1) raring; urgency=low + + * Merge with Debian; remaining changes: + - Build from upstream source. + + -- Matthias Klose Tue, 27 Nov 2012 13:38:44 +0100 + +gcc-4.7 (4.7.2-12) experimental; urgency=low + + * Update to SVN 20121127 (r193840) from the gcc-4_7-branch. + - Fix PR middle-end/55331 (ice on valid), PR tree-optimization/54976 (ice + on valid), PR tree-optimization/54894 (ice on valid), + PR middle-end/54735 (ice on valid), PR c++/55446 (wrong code), + PR fortran/55314 (rejects valid). + + [ Matthias Klose ] + * Fix x32 multiarch name (x86_64-linux-gnux32). + * gcc-4.7-base: Add break to gcc-4.4-base (<< 4.4.7). Closes: #690172. + * Add weak __aeabi symbols to the libgcc1 ARM symbol files. Closes: #677139. + * For stage1 builds, include gcc_lib_dir files in the gcc package. + + [ Thibaut Girka ] + * Fix libstdc++ multiarch include path for cross builds. + + -- Matthias Klose Tue, 27 Nov 2012 11:02:10 +0100 + +gcc-4.7 (4.7.2-11ubuntu1) raring; urgency=low + + * Merge with Debian; remaining changes: + - Build from upstream source. + + -- Matthias Klose Sat, 24 Nov 2012 06:09:46 +0100 + +gcc-4.7 (4.7.2-11) experimental; urgency=low + + * Update to SVN 20121124 (r193776) from the gcc-4_7-branch. + - Fix PR libgomp/55411, PR libstdc++/55413, PR middle-end/55142, + PR fortran/55352. + + * Update build-indep dependencies for building the libstdc++ docs. + * Drop the gcc-no-add-needed patch, depend on binutils 2.22 instead. + * Pass --hash-style=gnu instead of --hash-style=both. + * Link using --hash-style=gnu on arm64 by default. + * Split multiarch patches into local and upstreamed parts. + * Fix PR54974: Thumb literal pools don't handle PC rounding (Matthew + Gretton-Dann). LP: #1049614, #1065509. + * Rename the gccgo info to gccgo-4.7 on installation, install into gccgo-4.7. + * Include libquadmath documentation in the gcc-4.7-doc package. + * Don't pretend to understand .d files, no D frontend available for 4.7. + * Fix the multiarch c++ include path for multilib'd targets. LP: #1082344. + * Make explicit --{en,dis}able-multiarch options effecitive (Thorsten Glaser). + + -- Matthias Klose Sat, 24 Nov 2012 03:57:00 +0100 + +gcc-4.7 (4.7.2-10) experimental; urgency=low + + * Update to SVN 20121118 (r193598) from the gcc-4_7-branch. + - Fix PR target/54892 (ARM, LP: #1065122), PR rtl-optimization/54870, + PR rtl-optimization/53701, PR target/53975 (ia64), + PR tree-optimization/54902 (LP: #1065559), PR middle-end/54945, + PR target/55019 (ARM), PR c++/54984, PR target/55175, + PR tree-optimization/53708, PR tree-optimization/54985, + PR libstdc++/55169, PR libstdc++/55047, PR libstdc++/55123, + PR libstdc++/54075, PR libstdc++/28811, PR libstdc++/54482, + PR libstdc++/55028, PR libstdc++/55215, PR middle-end/55219, + PR tree-optimization/54986, PR target/55204, PR debug/54828, + PR tree-optimization/54877, PR c++/54988, PR other/52438, + PR fortran/54917, PR libstdc++/55320, PR libstdc++/53841. + + [ Matthias Klose ] + * Update the Linaro support to the 4.7-2012.11 release. + * Define MULTIARCH_DIRNAME for arm64 (Wookey). + * Let the lib*objc-dev packages depend on the lib*gcc-dev packages. + * Let the libstdc++-dev package depend on the libgcc-dev package. + * Drop the dependency of the libstdc++-dev package on g++, make + libstdc++-dev and libstdc++-pic Multi-Arch: same. Closes: #678623. + * Install override files before calling dh_fixperms. + * Backport the libffi arm64 port. + * Build libx32gcc-dev, libx32objc-dev and libx32gfortran-dev packages. + * Allow conditional building of the x32 multilibs. + * Fix libmudflap build failure for x32 multilibs. + * Fix dependency on glibc for triarch builds. + * Add build-{arch,indep} targets. + * Fix libquadmath x32 multilib builds on kernels which don't support x32. + * Fix location of x32 specific C++ header files. + * Turn on -D_FORTIFY_SOURCE=2 by default for C, C++, ObjC, ObjC++, + only if the optimization level is > 0. + * Keep the host alias when building multilib libraries which need to + be cross-built on some architectures/buildds. + * Update arm64 from the aarch64 branch 20121105. + * Fix PR other/54411, libiberty: objalloc_alloc integer overflows + (CVE-2012-3509). + * Use /usr/include//c++/4.x as the include directory + for host dependent c++ header files. + * Add alternative libelf-dev build dependency. Closes: #690952. + * Always build the aarch64-linux-gnu target from the Linaro branch. + * Add __gnu_* symbols to the libgcc1 symbols file for armel and armhf. + * For powerpcspe prevent floating point register handling when there + are none available (Roland Stigge). Closes: #693328. + * Don't apply hurd-pthread.diff for trunk builds, integrated + upstream (Samuel Thibault). Addresses: #692538. + * Again, suggest graphite runtime dependencies. + * Clean up libstdc++ man pages. Closes: #692445. + + [ Thibaut Girka ] + * Split out lib*gcc-dev packages. + * Split out lib*objc-dev packages. + * Split out lib*gfortran-dev packages. + + [ Daniel Schepler ] + * Add support for x32. Closes: #667005. + * New patch hjl-x32-gcc-4_7-branch.diff to incorporate changes from + that branch, including --with-abi=mx32 option. + * Split out lib*stdc++-dev packages. + + [ Marcin Juszkiewicz ] + * lib*-dev packages for cross builds are not Multi-Arch: same. LP: #1070694. + * Remove conflicts for armhf/armel cross packages. + + -- Matthias Klose Sun, 18 Nov 2012 17:54:15 +0100 + +gcc-4.7 (4.7.2-5ubuntu7) raring; urgency=low + + * Fix thinko in the gcc-multiarch patch; the multiarch related + macros have to be defined in the Makefile before including the + host fragment files. + + -- Matthias Klose Wed, 14 Nov 2012 19:24:11 +0100 + +gcc-4.7 (4.7.2-5ubuntu6) raring; urgency=low + + * Update to SVN 20121113 (r193472) from the gcc-4_7-branch. + * Use /usr/include//c++/4.x as the include directory + for host dependent c++ header files. + * Split out lib*stdc++-dev packages. + * Update to the Linaro 4.7-2012.11 release. + + -- Matthias Klose Wed, 14 Nov 2012 10:34:27 +0100 + +gcc-4.7 (4.7.2-5ubuntu5) raring; urgency=low + + * Update to SVN 20121105 (r193152) from the gcc-4_7-branch. + * Fix typo in control file for arm multilib packages. + + -- Matthias Klose Mon, 05 Nov 2012 14:46:59 +0100 + +gcc-4.7 (4.7.2-5ubuntu4) raring; urgency=low + + * Update to SVN 20121027 (r192873) from the gcc-4_7-branch. + * Build x32 multilibs on amd64 and i386. + * Don't run the libstdc++ tests on armel, timeouts on the buildds. + * lib*-dev packages for cross builds are not Multi-Arch: same. LP: #1070694. + * Turn on -D_FORTIFY_SOURCE=2 by default for C, C++, ObjC, ObjC++, + only if the optimization level is > 0. + + -- Matthias Klose Sat, 27 Oct 2012 14:03:30 +0200 + +gcc-4.7 (4.7.2-5ubuntu3) raring; urgency=low + + * Fix hjl-x32-gcc-4_7-branch.diff. + + -- Matthias Klose Thu, 25 Oct 2012 13:45:40 +0200 + +gcc-4.7 (4.7.2-5ubuntu2) raring; urgency=low + + * Merge with Debian. + + -- Matthias Klose Thu, 25 Oct 2012 13:31:07 +0200 + +gcc-4.7 (4.7.2-5) UNRELEASED; urgency=low + + * Update to SVN 20121118 (r193598) from the gcc-4_7-branch. + - Fix PR target/54892 (ARM, LP: #1065122), PR rtl-optimization/54870, + PR rtl-optimization/53701, PR target/53975 (ia64), + PR tree-optimization/54902 (LP: #1065559), PR middle-end/54945, + PR target/55019 (ARM), PR c++/54984, PR target/55175, + PR tree-optimization/53708, PR tree-optimization/54985, + PR libstdc++/55169, PR libstdc++/55047, PR libstdc++/55123, + PR libstdc++/54075, PR libstdc++/28811, PR libstdc++/54482, + PR libstdc++/55028, PR libstdc++/55215, PR middle-end/55219, + PR tree-optimization/54986, PR target/55204, PR debug/54828, + PR tree-optimization/54877, PR c++/54988, PR other/52438, + PR fortran/54917, PR libstdc++/55320, PR libstdc++/53841. + + [ Matthias Klose ] + * Update the Linaro support to the 4.7-2012.11 release. + * Define MULTIARCH_DIRNAME for arm64 (Wookey). + * Let the lib*objc-dev packages depend on the lib*gcc-dev packages. + * Let the libstdc++-dev package depend on the libgcc-dev package. + * Drop the dependency of the libstdc++-dev package on g++, make + libstdc++-dev and libstdc++-pic Multi-Arch: same. Closes: #678623. + * Install override files before calling dh_fixperms. + * Backport the libffi arm64 port. + * Build libx32gcc-dev, libx32objc-dev and libx32gfortran-dev packages. + * Allow conditional building of the x32 multilibs. + * Fix libmudflap build failure for x32 multilibs. + * Fix dependency on glibc for triarch builds. + * Add build-{arch,indep} targets. + * Fix libquadmath x32 multilib builds on kernels which don't support x32. + * Fix location of x32 specific C++ header files. + * Turn on -D_FORTIFY_SOURCE=2 by default for C, C++, ObjC, ObjC++, + only if the optimization level is > 0. + * Keep the host alias when building multilib libraries which need to + be cross-built on some architectures/buildds. + * Update arm64 from the aarch64 branch 20121105. + * Fix PR other/54411, libiberty: objalloc_alloc integer overflows + (CVE-2012-3509). + * Use /usr/include//c++/4.x as the include directory + for host dependent c++ header files. + * Add alternative libelf-dev build dependency. Closes: #690952. + * Always build the aarch64-linux-gnu target from the Linaro branch. + * Add __gnu_* symbols to the libgcc1 symbols file for armel and armhf. + * For powerpcspe prevent floating point register handling when there + are none available (Roland Stigge). Closes: #693328. + * Don't apply hurd-pthread.diff for trunk builds, integrated + upstream (Samuel Thibault). Addresses: #692538. + * Again, suggest graphite runtime dependencies. + * Clean up libstdc++ man pages. Closes: #692445. + * Update build-indep dependencies for building the libstdc++ docs. + * Drop the gcc-no-add-needed patch, depend on binutils 2.22 instead. + * Pass --hash-style=gnu instead of --hash-style=both. + * Link using --hash-style=gnu on arm64 by default. + + [ Thibaut Girka ] + * Split out lib*gcc-dev packages. + * Split out lib*objc-dev packages. + * Split out lib*gfortran-dev packages. + + [ Daniel Schepler ] + * Add support for x32. Closes: #667005. + * New patch hjl-x32-gcc-4_7-branch.diff to incorporate changes from + that branch, including --with-abi=mx32 option. + * Split out lib*stdc++-dev packages. + + [ Marcin Juszkiewicz ] + * lib*-dev packages for cross builds are not Multi-Arch: same. LP: #1070694. + * Remove conflicts for armhf/armel cross packages. + + -- Matthias Klose Sun, 18 Nov 2012 17:54:15 +0100 + +gcc-4.7 (4.7.2-4ubuntu1) quantal; urgency=low + + * Merge with Debian. + + -- Matthias Klose Wed, 10 Oct 2012 01:16:02 +0200 + +gcc-4.7 (4.7.2-4) unstable; urgency=low + + * Fix PR c++/54858 (ice on valid), taken from the branch. + * Build again Go on armel and armhf. + + -- Matthias Klose Tue, 09 Oct 2012 12:00:59 +0200 + +gcc-4.7 (4.7.2-3) unstable; urgency=low + + * Revert the fix PR c/33763, and just disable the sorry message, + taken from the branch. Closes: #678589. LP: #1062343. + * Update libgo to 1.0.3. + * Go fixes: + - Fix a, b, c := b, a, 1 when a and b already exist. + - Fix some type reflection strings. + - Fix parse of (<- chan <- chan <- int)(x). + - Fix handling of omitted expression in switch. + - Better error for switch on non-comparable type. + * Fix PR debug/53135 (ice on valid), PR target/54703 (x86, wrong code), + PR c++/54777 (c++11, rejects valid), taken from the 4.7 branch. + * gcc-4.7-base: ensure smooth upgrades from squeeze by adding + Breaks: gcj-4.4-base (<< 4.4.6-9~), gnat-4.4-base (<< 4.4.6-3~) + as in gcc-4.4-base (multiarch patches re-worked in 4.6.1-8/4.4.6-9). + Fixes some squeeze->wheezy upgrade paths where apt chooses to hold back + gcc-4.4-base and keep gcj-4.4-base installed instead of upgrading + gcc-4.4-base and removing the obsolete gcj-4.4-base (Andreas Beckmann). + Closes: #677582. + * Add arm64 support, partly based on Wookey's patches (only applied for + arm64). Disabled for arm64 are ssp, gomp, mudflap, boehm-gc, Ada, ObjC, + Obj-C++ and Java). + + -- Matthias Klose Fri, 05 Oct 2012 20:00:30 +0200 gcc-4.7 (4.7.2-2ubuntu1) quantal; urgency=low diff -Nru gcc-4.7-4.7.2/debian/control gcc-4.7-4.7.3/debian/control --- gcc-4.7-4.7.2/debian/control 2013-07-25 18:49:32.000000000 +0000 +++ gcc-4.7-4.7.3/debian/control 2013-07-25 18:49:34.000000000 +0000 @@ -5,8 +5,18 @@ XSBC-Original-Maintainer: Debian GCC Maintainers Uploaders: Matthias Klose Standards-Version: 3.9.3 -Build-Depends: dpkg-dev (>= 1.16.0~ubuntu4), debhelper (>= 5.0.62), g++-multilib [amd64 armel armhf i386 kfreebsd-amd64 mips mipsel powerpc ppc64 s390 s390x sparc], libc6.1-dev (>= 2.13-0ubuntu6) [alpha ia64] | libc0.3-dev (>= 2.13-0ubuntu6) [hurd-i386] | libc0.1-dev (>= 2.13-0ubuntu6) [kfreebsd-i386 kfreebsd-amd64] | libc6-dev (>= 2.13-0ubuntu6), libc6-dev (>= 2.13-31) [armel armhf], libc6-dev-amd64 [i386], libc6-dev-sparc64 [sparc], libc6-dev-s390 [s390x], libc6-dev-s390x [s390], libc6-dev-i386 [amd64], libc6-dev-powerpc [ppc64], libc6-dev-ppc64 [powerpc], libc0.1-dev-i386 [kfreebsd-amd64], lib32gcc1 [amd64 ppc64 kfreebsd-amd64 s390x], lib64gcc1 [i386 powerpc sparc s390], libc6-dev-mips64 [mips mipsel], libc6-dev-mipsn32 [mips mipsel], libc6-dev-armhf [armel], libc6-dev-armel [armhf], m4, libtool, autoconf2.64, automake (>= 1:1.11), automake (<< 1:1.12), libunwind7-dev (>= 0.98.5-6) [ia64], libatomic-ops-dev [ia64], zlib1g-dev, gawk, lzma, xz-utils, patchutils, binutils (>= 2.21.1) | binutils-multiarch (>= 2.21.1), binutils-hppa64 (>= 2.21.1) [hppa], gperf (>= 3.0.1), bison (>= 1:2.3), flex, gettext, texinfo (>= 4.3), locales, procps, sharutils, netbase, binutils-spu (>= 2.21.1) [powerpc ppc64], newlib-spu (>= 1.16.0) [powerpc ppc64], libcloog-ppl-dev (>= 0.15.9-2~), libmpc-dev, libmpfr-dev (>= 3.0.0-9~), libgmp-dev (>= 2:5.0.1~), libelfg0-dev (>= 0.8.12), dejagnu [!m68k !hurd-i386 !hurd-alpha], autogen, realpath (>= 1.9.12), chrpath, lsb-release, make (>= 3.81), quilt -Build-Depends-Indep: doxygen (>= 1.7.2), graphviz (>= 2.2), gsfonts-x11, texlive-latex-base, +Build-Depends: debhelper (>= 5.0.62), + libc6.1-dev (>= 2.13-0ubuntu6) [alpha ia64] | libc0.3-dev (>= 2.13-0ubuntu6) [hurd-i386] | libc0.1-dev (>= 2.13-0ubuntu6) [kfreebsd-i386 kfreebsd-amd64] | libc6-dev (>= 2.13-0ubuntu6) , libc6-dev (>= 2.13-31) [armel armhf], libc6-dev-amd64 [i386 x32], libc6-dev-sparc64 [sparc], libc6-dev-s390 [s390x], libc6-dev-s390x [s390], libc6-dev-i386 [amd64 x32], libc6-dev-powerpc [ppc64], libc6-dev-ppc64 [powerpc], libc0.1-dev-i386 [kfreebsd-amd64], lib32gcc1 [amd64 ppc64 kfreebsd-amd64 s390x x32], lib64gcc1 [i386 powerpc sparc s390 x32], libc6-dev-mips64 [mips mipsel], libc6-dev-mipsn32 [mips mipsel], libc6-dev-armhf [armel], libc6-dev-armel [armhf], + m4, libtool, autoconf2.64, automake (>= 1:1.11), automake (<< 1:1.12), + libunwind7-dev (>= 0.98.5-6) [ia64], libatomic-ops-dev [ia64], + zlib1g-dev, gawk, lzma, xz-utils, patchutils, + binutils-hppa64 (>= 2.22) [hppa], + gperf (>= 3.0.1), bison (>= 1:2.3), flex, gettext, + texinfo (>= 4.3), locales, sharutils, + procps, netbase, binutils-spu (>= 2.22) [powerpc ppc64], newlib-spu (>= 1.16.0) [powerpc ppc64], + libcloog-ppl-dev (>= 0.15.11), libmpc-dev, libmpfr-dev (>= 3.0.0-9~), libgmp-dev (>= 2:5.0.1~), + dejagnu [!m68k !arm !armel !armhf !hurd-i386 !hurd-alpha], autogen, realpath (>= 1.9.12), chrpath, lsb-release, quilt +Build-Depends-Indep: doxygen (>= 1.7.2), graphviz (>= 2.2), ghostscript, texlive-latex-base, xsltproc, libxml2-utils, docbook-xsl-ns, Build-Conflicts: binutils-gold Homepage: http://gcc.gnu.org/ XS-Vcs-Browser: http://svn.debian.org/viewsvn/gcccvs/branches/sid/gcc-4.7/ @@ -19,192 +29,94 @@ Priority: required Depends: ${misc:Depends} Replaces: ${base:Replaces} -Breaks: gcj-4.6-base (<< 4.6.1-4~), gnat-4.6 (<< 4.6.1-5~), dehydra (<= 0.9.hg20110609-2) +Breaks: gcc-4.4-base (<< 4.4.7), gcj-4.4-base (<< 4.4.6-9~), gnat-4.4-base (<< 4.4.6-3~), gcj-4.6-base (<< 4.6.1-4~), gnat-4.6 (<< 4.6.1-5~), dehydra (<= 0.9.hg20110609-2) Description: GCC, the GNU Compiler Collection (base package) This package contains files common to all languages and libraries contained in the GNU Compiler Collection (GCC). -Package: libgcc1 +Package: libgcc-4.7-dev Architecture: any -Section: libs -Priority: required -Depends: gcc-4.7-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Multi-Arch: same -Pre-Depends: multiarch-support -Breaks: ${multiarch:breaks} -Provides: libgcc1-armel [armel], libgcc1-armhf [armhf] -Description: GCC support library - Shared version of the support library, a library of internal subroutines - that GCC uses to overcome shortcomings of particular machines, or - special needs for some languages. - -Package: libgcc1-dbg -Architecture: any -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libgcc1 (= ${gcc:EpochVersion}), ${misc:Depends} -Multi-Arch: same -Provides: libgcc1-dbg-armel [armel], libgcc1-dbg-armhf [armhf] -Description: GCC support library (debug symbols) - Debug symbols for the GCC support library. - -Package: libgcc2 -Architecture: m68k -Section: libs -Priority: required -Depends: gcc-4.7-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Multi-Arch: same -Pre-Depends: multiarch-support -Breaks: ${multiarch:breaks} -Description: GCC support library - Shared version of the support library, a library of internal subroutines - that GCC uses to overcome shortcomings of particular machines, or - special needs for some languages. - -Package: libgcc2-dbg -Architecture: m68k -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libgcc2 (= ${gcc:Version}), ${misc:Depends} -Multi-Arch: same -Description: GCC support library (debug symbols) - Debug symbols for the GCC support library. - -Package: libgcc4 -Architecture: hppa -Multi-Arch: same -Pre-Depends: multiarch-support -Breaks: ${multiarch:breaks} -Section: libs -Priority: required -Depends: gcc-4.7-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Description: GCC support library - Shared version of the support library, a library of internal subroutines - that GCC uses to overcome shortcomings of particular machines, or - special needs for some languages. - -Package: libgcc4-dbg -Architecture: hppa +Section: libdevel +Priority: optional +Recommends: ${dep:libcdev} +Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libgcc}, ${dep:libssp}, ${dep:libgomp}, ${dep:libitm}, ${dep:libqmath}, ${dep:libunwinddev}, ${shlibs:Depends}, ${misc:Depends} +Replaces: gcc-4.7 (<< ${gcc:SplitVersion}) Multi-Arch: same -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libgcc4 (= ${gcc:Version}), ${misc:Depends} -Description: GCC support library (debug symbols) - Debug symbols for the GCC support library. +Description: GCC support library (development files) + This package contains the headers and static library files necessary for + building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. -Package: lib64gcc1 -Architecture: i386 powerpc sparc s390 mips mipsel -Section: libs +Package: lib64gcc-4.7-dev +Architecture: i386 powerpc sparc s390 mips mipsel x32 +Section: libdevel Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${misc:Depends} -Conflicts: libgcc1 (<= 1:3.3-0pre9) -Description: GCC support library (64bit) - Shared version of the support library, a library of internal subroutines - that GCC uses to overcome shortcomings of particular machines, or - special needs for some languages. - -Package: lib64gcc1-dbg -Architecture: i386 powerpc sparc s390 mips mipsel -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib64gcc1 (= ${gcc:EpochVersion}), ${misc:Depends} -Description: GCC support library (debug symbols) - Debug symbols for the GCC support library. - -Package: lib32gcc1 -Architecture: amd64 ppc64 kfreebsd-amd64 s390x -Section: libs -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${misc:Depends} -Conflicts: ${confl:lib32} -Description: GCC support library (32 bit Version) - Shared version of the support library, a library of internal subroutines - that GCC uses to overcome shortcomings of particular machines, or - special needs for some languages. - -Package: lib32gcc1-dbg -Architecture: amd64 ppc64 kfreebsd-amd64 s390x -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib32gcc1 (= ${gcc:EpochVersion}), ${misc:Depends} -Description: GCC support library (debug symbols) - Debug symbols for the GCC support library. +Recommends: ${dep:libcdev} +Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libgccbiarch}, ${dep:libsspbiarch}, ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends} +Replaces: gcc-4.7-multilib (<< ${gcc:SplitVersion}) +Description: GCC support library (64bit development files) + This package contains the headers and static library files necessary for + building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. -Package: libhfgcc1 -Architecture: armel -Section: libs +Package: lib32gcc-4.7-dev +Architecture: amd64 ppc64 kfreebsd-amd64 s390x x32 +Section: libdevel Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${misc:Depends} -Conflicts: libgcc1-armhf [armel] -Description: GCC support library (hard float ABI) - Shared version of the support library, a library of internal subroutines - that GCC uses to overcome shortcomings of particular machines, or - special needs for some languages. +Recommends: ${dep:libcdev} +Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libgccbiarch}, ${dep:libsspbiarch}, ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends} +Replaces: gcc-4.7-multilib (<< ${gcc:SplitVersion}) +Description: GCC support library (32 bit development files) + This package contains the headers and static library files necessary for + building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. -Package: libhfgcc1-dbg +Package: libhfgcc-4.7-dev Architecture: armel -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libhfgcc1 (= ${gcc:EpochVersion}), ${misc:Depends} -Conflicts: libgcc1-dbg-armhf [armel] -Description: GCC support library (debug symbols) - Debug symbols for the GCC support library. - -Package: libsfgcc1 -Architecture: armhf -Section: libs +Section: libdevel Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${misc:Depends} -Conflicts: libgcc1-armel [armhf] -Description: GCC support library (soft float ABI) - Shared version of the support library, a library of internal subroutines - that GCC uses to overcome shortcomings of particular machines, or - special needs for some languages. +Recommends: ${dep:libcdev} +Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libgccbiarch}, ${dep:libsspbiarch}, ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends} +Replaces: gcc-4.7-multilib (<< ${gcc:SplitVersion}) +Description: GCC support library (hard float ABI development files) + This package contains the headers and static library files necessary for + building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. -Package: libsfgcc1-dbg +Package: libsfgcc-4.7-dev Architecture: armhf -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libsfgcc1 (= ${gcc:EpochVersion}), ${misc:Depends} -Conflicts: libgcc1-dbg-armel [armhf] -Description: GCC support library (debug symbols) - Debug symbols for the GCC support library. - -Package: libn32gcc1 -Architecture: mips mipsel -Section: libs +Section: libdevel Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${misc:Depends} -Conflicts: libgcc1 (<= 1:3.3-0pre9) -Description: GCC support library (n32) - Shared version of the support library, a library of internal subroutines - that GCC uses to overcome shortcomings of particular machines, or - special needs for some languages. +Recommends: ${dep:libcdev} +Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libgccbiarch}, ${dep:libsspbiarch}, ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends} +Replaces: gcc-4.7-multilib (<< ${gcc:SplitVersion}) +Description: GCC support library (soft float ABI development files) + This package contains the headers and static library files necessary for + building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. -Package: libn32gcc1-dbg +Package: libn32gcc-4.7-dev Architecture: mips mipsel -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libn32gcc1 (= ${gcc:EpochVersion}), ${misc:Depends} -Description: GCC support library (debug symbols) - Debug symbols for the GCC support library. +Section: libdevel +Priority: optional +Recommends: ${dep:libcdev} +Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libgccbiarch}, ${dep:libsspbiarch}, ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends} +Replaces: gcc-4.7-multilib (<< ${gcc:SplitVersion}) +Description: GCC support library (n32 development files) + This package contains the headers and static library files necessary for + building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. Package: gcc-4.7 Architecture: any Section: devel Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), cpp-4.7 (= ${gcc:Version}), binutils (>= ${binutils:Version}), ${dep:libgcc}, ${dep:libssp}, ${dep:libgomp}, ${dep:libitm}, ${dep:libqmath}, ${dep:libunwinddev}, ${shlibs:Depends}, ${misc:Depends} +Depends: gcc-4.7-base (= ${gcc:Version}), cpp-4.7 (= ${gcc:Version}), binutils (>= ${binutils:Version}), libgcc-4.7-dev (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} Recommends: ${dep:libcdev} -Suggests: ${gcc:multilib}, libmudflap0-4.7-dev (>= ${gcc:Version}), gcc-4.7-doc (>= ${gcc:SoftVersion}), gcc-4.7-locales (>= ${gcc:SoftVersion}), libgcc1-dbg, libgomp1-dbg, libitm1-dbg, libquadmath0-dbg, libmudflap0-dbg, ${dep:libcloog}, ${dep:gold} +Suggests: ${gcc:multilib}, libmudflap0-4.7-dev (>= ${gcc:Version}), gcc-4.7-doc (>= ${gcc:SoftVersion}), gcc-4.7-locales (>= ${gcc:SoftVersion}), libgcc1-dbg (>= ${gcc:EpochVersion}), libgomp1-dbg (>= ${gcc:Version}), libitm1-dbg (>= ${gcc:Version}), libquadmath0-dbg (>= ${gcc:Version}), libmudflap0-dbg (>= ${gcc:Version}), ${dep:libcloog}, ${dep:gold} Provides: c-compiler Description: GNU C compiler This is the GNU C compiler, a fairly portable optimizing compiler for C. Package: gcc-4.7-multilib -Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mipsel powerpc ppc64 s390 s390x sparc +Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mipsel powerpc ppc64 s390 s390x sparc x32 Section: devel Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), gcc-4.7 (= ${gcc:Version}), ${dep:libcbiarchdev}, ${dep:libgccbiarch}, ${dep:libsspbiarch}, ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends} +Depends: gcc-4.7-base (= ${gcc:Version}), gcc-4.7 (= ${gcc:Version}), ${dep:libcbiarchdev}, ${dep:libgccbiarchdev}, ${shlibs:Depends}, ${misc:Depends} Suggests: ${dep:libmudflapbiarch} Description: GNU C compiler (multilib files) This is the GNU C compiler, a fairly portable optimizing compiler for C. @@ -278,545 +190,61 @@ Section: doc Priority: optional Depends: gcc-4.7-base (>= ${gcc:SoftVersion}), dpkg (>= 1.15.4) | install-info, ${misc:Depends} -Description: Documentation for the GNU C preprocessor (cpp) - Documentation for the GNU C preprocessor in info format. - -Package: gcc-4.7-locales -Architecture: all -Section: devel -Priority: optional -Depends: gcc-4.7-base (>= ${gcc:SoftVersion}), cpp-4.7 (>= ${gcc:SoftVersion}), ${misc:Depends} -Recommends: gcc-4.7 (>= ${gcc:SoftVersion}) -Description: GCC, the GNU compiler collection (native language support files) - Native language support for GCC. Lets GCC speak your language, - if translations are available. - . - Please do NOT submit bug reports in other languages than "C". - Always reset your language settings to use the "C" locales. - -Package: g++-4.7 -Architecture: any -Section: devel -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), gcc-4.7 (= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Provides: c++-compiler, c++abi2-dev -Suggests: ${gxx:multilib}, gcc-4.7-doc (>= ${gcc:SoftVersion}), libstdc++6-4.7-dbg -Description: GNU C++ compiler - This is the GNU C++ compiler, a fairly portable optimizing compiler for C++. - -Package: g++-4.7-multilib -Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mipsel powerpc ppc64 s390 s390x sparc -Section: devel -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), g++-4.7 (= ${gcc:Version}), gcc-4.7-multilib (= ${gcc:Version}), ${dep:libcxxbiarch}, ${shlibs:Depends}, ${misc:Depends} -Suggests: ${dep:libcxxbiarchdbg} -Description: GNU C++ compiler (multilib files) - This is the GNU C++ compiler, a fairly portable optimizing compiler for C++. - . - On architectures with multilib support, the package contains files - and dependencies for the non-default multilib architecture(s). - -Package: libmudflap0 -Architecture: any -Multi-Arch: same -Pre-Depends: multiarch-support -Breaks: ${multiarch:breaks} -Provides: libmudflap0-armel [armel], libmudflap0-armhf [armhf] -Section: libs -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Description: GCC mudflap shared support libraries - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libmudflap0-dbg -Architecture: any -Multi-Arch: same -Provides: libmudflap0-dbg-armel [armel], libmudflap0-dbg-armhf [armhf] -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libmudflap0 (= ${gcc:Version}), ${misc:Depends} -Description: GCC mudflap shared support libraries (debug symbols) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: lib32mudflap0 -Architecture: amd64 ppc64 kfreebsd-amd64 s390x -Section: libs -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Replaces: libmudflap0 (<< 4.1) -Conflicts: ${confl:lib32} -Description: GCC mudflap shared support libraries (32bit) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: lib32mudflap0-dbg -Architecture: amd64 ppc64 kfreebsd-amd64 s390x -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib32mudflap0 (= ${gcc:Version}), ${misc:Depends} -Description: GCC mudflap shared support libraries (32 bit debug symbols) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: lib64mudflap0 -Architecture: i386 powerpc sparc s390 mips mipsel -Section: libs -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Replaces: libmudflap0 (<< 4.1) -Description: GCC mudflap shared support libraries (64bit) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: lib64mudflap0-dbg -Architecture: i386 powerpc sparc s390 mips mipsel -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib64mudflap0 (= ${gcc:Version}), ${misc:Depends} -Description: GCC mudflap shared support libraries (64 bit debug symbols) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libn32mudflap0 -Architecture: mips mipsel -Section: libs -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Replaces: libmudflap0 (<< 4.1) -Description: GCC mudflap shared support libraries (n32) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libn32mudflap0-dbg -Architecture: mips mipsel -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libn32mudflap0 (= ${gcc:Version}), ${misc:Depends} -Description: GCC mudflap shared support libraries (n32 debug symbols) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libhfmudflap0 -Architecture: armel -Section: libs -Priority: optional -Conflicts: libmudflap0-armhf [armel] -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Description: GCC mudflap shared support libraries (hard float) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libhfmudflap0-dbg -Architecture: armel -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libhfmudflap0 (= ${gcc:Version}), ${misc:Depends} -Conflicts: libmudflap0-dbg-armhf [armel] -Description: GCC mudflap shared support libraries (hard float debug symbols) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libsfmudflap0 -Architecture: armhf -Section: libs -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: libmudflap0-armel [armhf] -Description: GCC mudflap shared support libraries (soft float) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libsfmudflap0-dbg -Architecture: armhf -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libsfmudflap0 (= ${gcc:Version}), ${misc:Depends} -Conflicts: libmudflap0-dbg-armel [armhf] -Description: GCC mudflap shared support libraries (soft float debug symbols) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libmudflap0-4.7-dev -Architecture: any -Section: libdevel -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), libmudflap0 (>= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends} -Suggests: ${sug:libmudflapdev} -Conflicts: libmudflap0-dev -Description: GCC mudflap support libraries (development files) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - . - This package contains the headers and the static libraries. - -Package: libgomp1 -Section: libs -Architecture: any -Multi-Arch: same -Pre-Depends: multiarch-support -Breaks: ${multiarch:breaks} -Provides: libgomp1-armel [armel], libgomp1-armhf [armhf] -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Description: GCC OpenMP (GOMP) support library - GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers - in the GNU Compiler Collection. - -Package: libgomp1-dbg -Architecture: any -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libgomp1 (= ${gcc:Version}), ${misc:Depends} -Multi-Arch: same -Provides: libgomp1-dbg-armel [armel], libgomp1-dbg-armhf [armhf] -Description: GCC OpenMP (GOMP) support library (debug symbols) - GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers - in the GNU Compiler Collection. - -Package: lib32gomp1 -Section: libs -Architecture: amd64 ppc64 kfreebsd-amd64 s390x -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: ${confl:lib32} -Description: GCC OpenMP (GOMP) support library (32bit) - GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers - in the GNU Compiler Collection. - -Package: lib32gomp1-dbg -Architecture: amd64 ppc64 kfreebsd-amd64 s390x -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib32gomp1 (= ${gcc:Version}), ${misc:Depends} -Description: GCC OpenMP (GOMP) support library (32 bit debug symbols) - GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers - in the GNU Compiler Collection. - -Package: lib64gomp1 -Section: libs -Architecture: i386 powerpc sparc s390 mips mipsel -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Description: GCC OpenMP (GOMP) support library (64bit) - GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers - in the GNU Compiler Collection. - -Package: lib64gomp1-dbg -Architecture: i386 powerpc sparc s390 mips mipsel -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib64gomp1 (= ${gcc:Version}), ${misc:Depends} -Description: GCC OpenMP (GOMP) support library (64bit debug symbols) - GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers - in the GNU Compiler Collection. - -Package: libn32gomp1 -Section: libs -Architecture: mips mipsel -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Description: GCC OpenMP (GOMP) support library (n32) - GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers - in the GNU Compiler Collection. - -Package: libn32gomp1-dbg -Architecture: mips mipsel -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libn32gomp1 (= ${gcc:Version}), ${misc:Depends} -Description: GCC OpenMP (GOMP) support library (n32 debug symbols) - GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers - -Package: libhfgomp1 -Section: libs -Architecture: armel -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: libgomp1-armhf [armel] -Description: GCC OpenMP (GOMP) support library (hard float ABI) - GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers - in the GNU Compiler Collection. - -Package: libhfgomp1-dbg -Architecture: armel -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libhfgomp1 (= ${gcc:Version}), ${misc:Depends} -Conflicts: libgomp1-dbg-armhf [armel] -Description: GCC OpenMP (GOMP) support library (hard float ABI debug symbols) - GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers - -Package: libsfgomp1 -Section: libs -Architecture: armhf -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: libgomp1-armel [armhf] -Description: GCC OpenMP (GOMP) support library (soft float ABI) - GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers - in the GNU Compiler Collection. - -Package: libsfgomp1-dbg -Architecture: armhf -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libsfgomp1 (= ${gcc:Version}), ${misc:Depends} -Conflicts: libgomp1-dbg-armel [armhf] -Description: GCC OpenMP (GOMP) support library (soft float ABI debug symbols) - GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers - -Package: libitm1 -Section: libs -Architecture: any -Multi-Arch: same -Pre-Depends: multiarch-support -Provides: libitm1-armel [armel], libitm1-armhf [armhf] -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Description: GNU Transactional Memory Library - GNU Transactional Memory Library (libitm) provides transaction support for - accesses to the memory of a process, enabling easy-to-use synchronization of - accesses to shared memory by several threads. - -Package: libitm1-dbg -Architecture: any -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libitm1 (= ${gcc:Version}), ${misc:Depends} -Multi-Arch: same -Provides: libitm1-dbg-armel [armel], libitm1-dbg-armhf [armhf] -Description: GNU Transactional Memory Library (debug symbols) - GNU Transactional Memory Library (libitm) provides transaction support for - accesses to the memory of a process, enabling easy-to-use synchronization of - accesses to shared memory by several threads. - -Package: lib32itm1 -Section: libs -Architecture: amd64 ppc64 kfreebsd-amd64 s390x -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: ${confl:lib32} -Description: GNU Transactional Memory Library (32bit) - GNU Transactional Memory Library (libitm) provides transaction support for - accesses to the memory of a process, enabling easy-to-use synchronization of - accesses to shared memory by several threads. - -Package: lib32itm1-dbg -Architecture: amd64 ppc64 kfreebsd-amd64 s390x -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib32itm1 (= ${gcc:Version}), ${misc:Depends} -Description: GNU Transactional Memory Library (32 bit debug symbols) - GNU Transactional Memory Library (libitm) provides transaction support for - accesses to the memory of a process, enabling easy-to-use synchronization of - accesses to shared memory by several threads. - -Package: lib64itm1 -Section: libs -Architecture: i386 powerpc sparc s390 mips mipsel -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Description: GNU Transactional Memory Library (64bit) - GNU Transactional Memory Library (libitm) provides transaction support for - accesses to the memory of a process, enabling easy-to-use synchronization of - accesses to shared memory by several threads. - -Package: lib64itm1-dbg -Architecture: i386 powerpc sparc s390 mips mipsel -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib64itm1 (= ${gcc:Version}), ${misc:Depends} -Description: GNU Transactional Memory Library (64bit debug symbols) - GNU Transactional Memory Library (libitm) provides transaction support for - accesses to the memory of a process, enabling easy-to-use synchronization of - accesses to shared memory by several threads. - -Package: libn32itm1 -Section: libs -Architecture: mips mipsel -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Description: GNU Transactional Memory Library (n32) - GNU Transactional Memory Library (libitm) provides transaction support for - accesses to the memory of a process, enabling easy-to-use synchronization of - accesses to shared memory by several threads. - -Package: libn32itm1-dbg -Architecture: mips mipsel -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libn32itm1 (= ${gcc:Version}), ${misc:Depends} -Description: GNU Transactional Memory Library (n32 debug symbols) - GNU Transactional Memory Library (libitm) provides transaction support for - accesses to the memory of a process, enabling easy-to-use synchronization of - accesses to shared memory by several threads. - -Package: libhfitm1 -Section: libs -Architecture: armel -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: libitm1-armhf [armel] -Description: GNU Transactional Memory Library (hard float ABI) - GNU Transactional Memory Library (libitm) provides transaction support for - accesses to the memory of a process, enabling easy-to-use synchronization of - accesses to shared memory by several threads. - -Package: libhfitm1-dbg -Architecture: armel -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libhfitm1 (= ${gcc:Version}), ${misc:Depends} -Conflicts: libitm1-armel [armhf] -Description: GNU Transactional Memory Library (hard float ABI debug symbols) - GNU Transactional Memory Library (libitm) provides transaction support for - accesses to the memory of a process, enabling easy-to-use synchronization of - accesses to shared memory by several threads. - -Package: libsfitm1 -Section: libs -Architecture: armhf -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Description: GNU Transactional Memory Library (soft float ABI) - GNU Transactional Memory Library (libitm) provides transaction support for - accesses to the memory of a process, enabling easy-to-use synchronization of - accesses to shared memory by several threads. - -Package: libsfitm1-dbg -Architecture: armhf -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libsfitm1 (= ${gcc:Version}), ${misc:Depends} -Description: GNU Transactional Memory Library (soft float ABI debug symbols) - GNU Transactional Memory Library (libitm) provides transaction support for - accesses to the memory of a process, enabling easy-to-use synchronization of - accesses to shared memory by several threads. - -Package: libquadmath0 -Section: libs -Architecture: any -Multi-Arch: same -Pre-Depends: multiarch-support -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Description: GCC Quad-Precision Math Library - A library, which provides quad-precision mathematical functions on targets - supporting the __float128 datatype. The library is used to provide on such - targets the REAL(16) type in the GNU Fortran compiler. - -Package: libquadmath0-dbg -Architecture: any -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libquadmath0 (= ${gcc:Version}), ${misc:Depends} -Multi-Arch: same -Description: GCC Quad-Precision Math Library (debug symbols) - A library, which provides quad-precision mathematical functions on targets - supporting the __float128 datatype. - -Package: lib32quadmath0 -Section: libs -Architecture: amd64 ppc64 kfreebsd-amd64 s390x -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: ${confl:lib32} -Description: GCC Quad-Precision Math Library (32bit) - A library, which provides quad-precision mathematical functions on targets - supporting the __float128 datatype. The library is used to provide on such - targets the REAL(16) type in the GNU Fortran compiler. - -Package: lib32quadmath0-dbg -Architecture: amd64 ppc64 kfreebsd-amd64 s390x -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib32quadmath0 (= ${gcc:Version}), ${misc:Depends} -Description: GCC Quad-Precision Math Library (32 bit debug symbols) - A library, which provides quad-precision mathematical functions on targets - supporting the __float128 datatype. - -Package: lib64quadmath0 -Section: libs -Architecture: i386 powerpc sparc s390 mips mipsel -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Description: GCC Quad-Precision Math Library (64bit) - A library, which provides quad-precision mathematical functions on targets - supporting the __float128 datatype. The library is used to provide on such - targets the REAL(16) type in the GNU Fortran compiler. - -Package: lib64quadmath0-dbg -Architecture: i386 powerpc sparc s390 mips mipsel -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib64quadmath0 (= ${gcc:Version}), ${misc:Depends} -Description: GCC Quad-Precision Math Library (64bit debug symbols) - A library, which provides quad-precision mathematical functions on targets - supporting the __float128 datatype. - -Package: libn32quadmath0 -Section: libs -Architecture: mips mipsel -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Description: GCC Quad-Precision Math Library (n32) - A library, which provides quad-precision mathematical functions on targets - supporting the __float128 datatype. The library is used to provide on such - targets the REAL(16) type in the GNU Fortran compiler. - -Package: libn32quadmath0-dbg -Architecture: mips mipsel -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libn32quadmath0 (= ${gcc:Version}), ${misc:Depends} -Description: GCC Quad-Precision Math Library (n32 debug symbols) - A library, which provides quad-precision mathematical functions on targets - supporting the __float128 datatype. +Description: Documentation for the GNU C preprocessor (cpp) + Documentation for the GNU C preprocessor in info format. -Package: libhfquadmath0 -Section: libs -Architecture: armel +Package: gcc-4.7-locales +Architecture: all +Section: devel Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Description: GCC Quad-Precision Math Library (hard float ABI) - A library, which provides quad-precision mathematical functions on targets - supporting the __float128 datatype. The library is used to provide on such - targets the REAL(16) type in the GNU Fortran compiler. +Depends: gcc-4.7-base (>= ${gcc:SoftVersion}), cpp-4.7 (>= ${gcc:SoftVersion}), ${misc:Depends} +Recommends: gcc-4.7 (>= ${gcc:SoftVersion}) +Description: GCC, the GNU compiler collection (native language support files) + Native language support for GCC. Lets GCC speak your language, + if translations are available. + . + Please do NOT submit bug reports in other languages than "C". + Always reset your language settings to use the "C" locales. -Package: libhfquadmath0-dbg -Architecture: armel -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libhfquadmath0 (= ${gcc:Version}), ${misc:Depends} -Description: GCC Quad-Precision Math Library (hard float ABI debug symbols) - A library, which provides quad-precision mathematical functions on targets - supporting the __float128 datatype. +Package: g++-4.7 +Architecture: any +Section: devel +Priority: optional +Depends: gcc-4.7-base (= ${gcc:Version}), gcc-4.7 (= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Provides: c++-compiler, c++abi2-dev +Suggests: ${gxx:multilib}, gcc-4.7-doc (>= ${gcc:SoftVersion}), libstdc++6-4.7-dbg (>= ${gcc:Version}) +Description: GNU C++ compiler + This is the GNU C++ compiler, a fairly portable optimizing compiler for C++. -Package: libsfquadmath0 -Section: libs -Architecture: armhf +Package: g++-4.7-multilib +Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mipsel powerpc ppc64 s390 s390x sparc x32 +Section: devel Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Description: GCC Quad-Precision Math Library (soft float ABI) - A library, which provides quad-precision mathematical functions on targets - supporting the __float128 datatype. The library is used to provide on such - targets the REAL(16) type in the GNU Fortran compiler. +Depends: gcc-4.7-base (= ${gcc:Version}), g++-4.7 (= ${gcc:Version}), gcc-4.7-multilib (= ${gcc:Version}), ${dep:libcxxbiarchdev}, ${shlibs:Depends}, ${misc:Depends} +Suggests: ${dep:libcxxbiarchdbg} +Description: GNU C++ compiler (multilib files) + This is the GNU C++ compiler, a fairly portable optimizing compiler for C++. + . + On architectures with multilib support, the package contains files + and dependencies for the non-default multilib architecture(s). -Package: libsfquadmath0-dbg -Architecture: armhf -Section: debug -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libsfquadmath0 (= ${gcc:Version}), ${misc:Depends} -Description: GCC Quad-Precision Math Library (hard float ABI debug symbols) - A library, which provides quad-precision mathematical functions on targets - supporting the __float128 datatype. +Package: libmudflap0-4.7-dev +Architecture: any +Section: libdevel +Priority: optional +Depends: gcc-4.7-base (= ${gcc:Version}), libmudflap0 (>= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends} +Suggests: ${sug:libmudflapdev} +Conflicts: libmudflap0-dev +Description: GCC mudflap support libraries (development files) + The libmudflap libraries are used by GCC for instrumenting pointer and array + dereferencing operations. + . + This package contains the headers and the static libraries. Package: gobjc++-4.7 Architecture: any Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), gobjc-4.7 (= ${gcc:Version}), g++-4.7 (= ${gcc:Version}), ${shlibs:Depends}, libobjc4 (>= ${gcc:Version}), ${misc:Depends} +Depends: gcc-4.7-base (= ${gcc:Version}), gobjc-4.7 (= ${gcc:Version}), g++-4.7 (= ${gcc:Version}), ${shlibs:Depends}, libobjc-4.7-dev (= ${gcc:Version}), ${misc:Depends} Suggests: ${gobjcxx:multilib}, gcc-4.7-doc (>= ${gcc:SoftVersion}) Provides: objc++-compiler Description: GNU Objective-C++ compiler @@ -825,7 +253,7 @@ gcc backend to generate optimized code. Package: gobjc++-4.7-multilib -Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mipsel powerpc ppc64 s390 s390x sparc +Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mipsel powerpc ppc64 s390 s390x sparc x32 Section: devel Priority: optional Depends: gcc-4.7-base (= ${gcc:Version}), gobjc++-4.7 (= ${gcc:Version}), g++-4.7-multilib (= ${gcc:Version}), gobjc-4.7-multilib (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} @@ -839,8 +267,8 @@ Package: gobjc-4.7 Architecture: any Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), gcc-4.7 (= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, libobjc4 (>= ${gcc:Version}), ${misc:Depends} -Suggests: ${gobjc:multilib}, gcc-4.7-doc (>= ${gcc:SoftVersion}), libobjc4-dbg +Depends: gcc-4.7-base (= ${gcc:Version}), gcc-4.7 (= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, libobjc-4.7-dev (= ${gcc:Version}), ${misc:Depends} +Suggests: ${gobjc:multilib}, gcc-4.7-doc (>= ${gcc:SoftVersion}), libobjc4-dbg (>= ${gcc:Version}) Provides: objc-compiler Description: GNU Objective-C compiler This is the GNU Objective-C compiler, which compiles @@ -848,10 +276,10 @@ gcc backend to generate optimized code. Package: gobjc-4.7-multilib -Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mipsel powerpc ppc64 s390 s390x sparc +Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mipsel powerpc ppc64 s390 s390x sparc x32 Section: devel Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), gobjc-4.7 (= ${gcc:Version}), gcc-4.7-multilib (= ${gcc:Version}), ${dep:libobjcbiarch}, ${shlibs:Depends}, ${misc:Depends} +Depends: gcc-4.7-base (= ${gcc:Version}), gobjc-4.7 (= ${gcc:Version}), gcc-4.7-multilib (= ${gcc:Version}), ${dep:libobjcbiarchdev}, ${shlibs:Depends}, ${misc:Depends} Description: GNU Objective-C compiler (multilib files) This is the GNU Objective-C compiler, which compiles Objective-C on platforms supported by the gcc compiler. @@ -859,129 +287,83 @@ On architectures with multilib support, the package contains files and dependencies for the non-default multilib architecture(s). -Package: libobjc4 -Section: libs +Package: libobjc-4.7-dev Architecture: any -Multi-Arch: same -Pre-Depends: multiarch-support -Provides: libobjc4-armel [armel], libobjc4-armhf [armhf] +Section: libdevel Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Description: Runtime library for GNU Objective-C applications - Library needed for GNU ObjC applications linked against the shared library. - -Package: libobjc4-dbg -Section: debug -Architecture: any +Depends: gcc-4.7-base (= ${gcc:Version}), libgcc-4.7-dev (= ${gcc:Version}), libobjc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Replaces: gobjc-4.7 (<< ${gcc:SplitVersion}) Multi-Arch: same -Provides: libobjc4-dbg-armel [armel], libobjc4-dbg-armhf [armhf] -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libobjc4 (= ${gcc:Version}), libgcc1-dbg, ${misc:Depends} -Description: Runtime library for GNU Objective-C applications (debug symbols) - Library needed for GNU ObjC applications linked against the shared library. +Description: Runtime library for GNU Objective-C applications (development files) + This package contains the headers and static library files needed to build + GNU ObjC applications. -Package: lib64objc4 -Section: libs -Architecture: i386 powerpc sparc s390 mips mipsel +Package: lib64objc-4.7-dev +Architecture: i386 powerpc sparc s390 mips mipsel x32 +Section: libdevel Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Description: Runtime library for GNU Objective-C applications (64bit) - Library needed for GNU ObjC applications linked against the shared library. - -Package: lib64objc4-dbg -Section: debug -Architecture: i386 powerpc sparc s390 mips mipsel -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib64objc4 (= ${gcc:Version}), lib64gcc1-dbg, ${misc:Depends} -Description: Runtime library for GNU Objective-C applications (64 bit debug symbols) - Library needed for GNU ObjC applications linked against the shared library. +Depends: gcc-4.7-base (= ${gcc:Version}), lib64gcc-4.7-dev (= ${gcc:Version}), lib64objc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Replaces: gobjc-4.7-multilib (<< ${gcc:SplitVersion}) +Description: Runtime library for GNU Objective-C applications (64bit development files) + This package contains the headers and static library files needed to build + GNU ObjC applications. -Package: lib32objc4 -Section: libs -Architecture: amd64 ppc64 kfreebsd-amd64 s390x +Package: lib32objc-4.7-dev +Architecture: amd64 ppc64 kfreebsd-amd64 s390x x32 +Section: libdevel Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: ${confl:lib32} -Description: Runtime library for GNU Objective-C applications (32bit) - Library needed for GNU ObjC applications linked against the shared library. +Depends: gcc-4.7-base (= ${gcc:Version}), lib32gcc-4.7-dev (= ${gcc:Version}), lib32objc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Replaces: gobjc-4.7-multilib (<< ${gcc:SplitVersion}) +Description: Runtime library for GNU Objective-C applications (32bit development files) + This package contains the headers and static library files needed to build + GNU ObjC applications. -Package: lib32objc4-dbg -Section: debug -Architecture: amd64 ppc64 kfreebsd-amd64 s390x -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib32objc4 (= ${gcc:Version}), lib32gcc1-dbg, ${misc:Depends} -Description: Runtime library for GNU Objective-C applications (32 bit debug symbols) - Library needed for GNU ObjC applications linked against the shared library. - -Package: libn32objc4 -Section: libs +Package: libn32objc-4.7-dev Architecture: mips mipsel +Section: libdevel Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Description: Runtime library for GNU Objective-C applications (n32) - Library needed for GNU ObjC applications linked against the shared library. - -Package: libn32objc4-dbg -Section: debug -Architecture: mips mipsel -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libn32objc4 (= ${gcc:Version}), libn32gcc1-dbg, ${misc:Depends} -Description: Runtime library for GNU Objective-C applications (n32 debug symbols) - Library needed for GNU ObjC applications linked against the shared library. +Depends: gcc-4.7-base (= ${gcc:Version}), libn32gcc-4.7-dev (= ${gcc:Version}), libn32objc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Replaces: gobjc-4.7-multilib (<< ${gcc:SplitVersion}) +Description: Runtime library for GNU Objective-C applications (n32 development files) + This package contains the headers and static library files needed to build + GNU ObjC applications. -Package: libhfobjc4 -Section: libs +Package: libhfobjc-4.7-dev Architecture: armel +Section: libdevel Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: libobjc4-armhf [armel] -Description: Runtime library for GNU Objective-C applications (hard float ABI) - Library needed for GNU ObjC applications linked against the shared library. - -Package: libhfobjc4-dbg -Section: debug -Architecture: armel -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libhfobjc4 (= ${gcc:Version}), libhfgcc1-dbg, ${misc:Depends} -Conflicts: libobjc4-dbg-armhf [armel] -Description: Runtime library for GNU Objective-C applications (hard float ABI debug symbols) - Library needed for GNU ObjC applications linked against the shared library. +Depends: gcc-4.7-base (= ${gcc:Version}), libhfgcc-4.7-dev (= ${gcc:Version}), libhfobjc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Replaces: gobjc-4.7-multilib (<< ${gcc:SplitVersion}) +Description: Runtime library for GNU Objective-C applications (hard float ABI development files) + This package contains the headers and static library files needed to build + GNU ObjC applications. -Package: libsfobjc4 -Section: libs +Package: libsfobjc-4.7-dev Architecture: armhf +Section: libdevel Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: libobjc4-armel [armhf] -Description: Runtime library for GNU Objective-C applications (soft float ABI) - Library needed for GNU ObjC applications linked against the shared library. - -Package: libsfobjc4-dbg -Section: debug -Architecture: armhf -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libsfobjc4 (= ${gcc:Version}), libsfgcc1-dbg, ${misc:Depends} -Conflicts: libobjc4-dbg-armel [armhf] -Description: Runtime library for GNU Objective-C applications (soft float ABI debug symbols) - Library needed for GNU ObjC applications linked against the shared library. +Depends: gcc-4.7-base (= ${gcc:Version}), libsfgcc-4.7-dev (= ${gcc:Version}), libsfobjc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Replaces: gobjc-4.7-multilib (<< ${gcc:SplitVersion}) +Description: Runtime library for GNU Objective-C applications (soft float development files) + This package contains the headers and static library files needed to build + GNU ObjC applications. Package: gfortran-4.7 Architecture: any Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), gcc-4.7 (= ${gcc:Version}), libgfortran3 (>= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends} +Depends: gcc-4.7-base (= ${gcc:Version}), gcc-4.7 (= ${gcc:Version}), libgfortran-4.7-dev (= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends} Provides: fortran95-compiler -Suggests: ${gfortran:multilib}, gfortran-4.7-doc, libgfortran3-dbg -Replaces: libgfortran3-dev +Suggests: ${gfortran:multilib}, gfortran-4.7-doc, libgfortran3-dbg (>= ${gcc:Version}) Description: GNU Fortran compiler This is the GNU Fortran compiler, which compiles Fortran on platforms supported by the gcc compiler. It uses the gcc backend to generate optimized code. Package: gfortran-4.7-multilib -Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mipsel powerpc ppc64 s390 s390x sparc +Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mipsel powerpc ppc64 s390 s390x sparc x32 Section: devel Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), gfortran-4.7 (= ${gcc:Version}), gcc-4.7-multilib (= ${gcc:Version}), ${dep:libgfortranbiarch}, ${shlibs:Depends}, ${misc:Depends} +Depends: gcc-4.7-base (= ${gcc:Version}), gfortran-4.7 (= ${gcc:Version}), gcc-4.7-multilib (= ${gcc:Version}), ${dep:libgfortranbiarchdev}, ${shlibs:Depends}, ${misc:Depends} Description: GNU Fortran compiler (multilib files) This is the GNU Fortran compiler, which compiles Fortran on platforms supported by the gcc compiler. @@ -997,137 +379,86 @@ Description: Documentation for the GNU Fortran compiler (gfortran) Documentation for the GNU Fortran compiler in info format. -Package: libgfortran3 -Section: libs +Package: libgfortran-4.7-dev Architecture: any -Multi-Arch: same -Pre-Depends: multiarch-support -Breaks: ${multiarch:breaks} -Provides: libgfortran3-armel [armel], libgfortran3-armhf [armhf] +Section: libdevel Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Description: Runtime library for GNU Fortran applications - Library needed for GNU Fortran applications linked against the - shared library. - -Package: libgfortran3-dbg -Section: debug -Architecture: any -Multi-Arch: same -Provides: libgfortran3-dbg-armel [armel], libgfortran3-dbg-armhf [armhf] -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libgfortran3 (= ${gcc:Version}), ${misc:Depends} -Description: Runtime library for GNU Fortran applications (debug symbols) - Library needed for GNU Fortran applications linked against the - shared library. +Depends: gcc-4.7-base (= ${gcc:Version}), libgfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Replaces: gfortran-4.7 (<< ${gcc:SplitVersion}) +Breaks: gfortran-4.7 (<< ${gcc:SplitVersion}) +Multi-Arch: same +Description: Runtime library for GNU Fortran applications (development files) + This package contains the headers and static library files needed to build + GNU Fortran applications. -Package: lib64gfortran3 -Section: libs -Architecture: i386 powerpc sparc s390 mips mipsel +Package: lib64gfortran-4.7-dev +Architecture: i386 powerpc sparc s390 mips mipsel x32 +Section: libdevel Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Description: Runtime library for GNU Fortran applications (64bit) - Library needed for GNU Fortran applications linked against the - shared library. +Depends: gcc-4.7-base (= ${gcc:Version}), lib64gfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Replaces: gfortran-4.7-multilib (<< ${gcc:SplitVersion}) +Breaks: gfortran-4.7-multilib (<< ${gcc:SplitVersion}) +Description: Runtime library for GNU Fortran applications (64bit development files) + This package contains the headers and static library files needed to build + GNU Fortran applications. -Package: lib64gfortran3-dbg -Section: debug -Architecture: i386 powerpc sparc s390 mips mipsel -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib64gfortran3 (= ${gcc:Version}), ${misc:Depends} -Description: Runtime library for GNU Fortran applications (64bit debug symbols) - Library needed for GNU Fortran applications linked against the - shared library. - -Package: lib32gfortran3 -Section: libs -Architecture: amd64 ppc64 kfreebsd-amd64 s390x +Package: lib32gfortran-4.7-dev +Architecture: amd64 ppc64 kfreebsd-amd64 s390x x32 +Section: libdevel Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: ${confl:lib32} -Description: Runtime library for GNU Fortran applications (32bit) - Library needed for GNU Fortran applications linked against the - shared library. - -Package: lib32gfortran3-dbg -Section: debug -Architecture: amd64 ppc64 kfreebsd-amd64 s390x -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib32gfortran3 (= ${gcc:Version}), ${misc:Depends} -Description: Runtime library for GNU Fortran applications (32 bit debug symbols) - Library needed for GNU Fortran applications linked against the - shared library. +Depends: gcc-4.7-base (= ${gcc:Version}), lib32gfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Replaces: gfortran-4.7-multilib (<< ${gcc:SplitVersion}) +Breaks: gfortran-4.7-multilib (<< ${gcc:SplitVersion}) +Description: Runtime library for GNU Fortran applications (32bit development files) + This package contains the headers and static library files needed to build + GNU Fortran applications. -Package: libn32gfortran3 -Section: libs +Package: libn32gfortran-4.7-dev Architecture: mips mipsel +Section: libdevel Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Description: Runtime library for GNU Fortran applications (n32) - Library needed for GNU Fortran applications linked against the - shared library. - -Package: libn32gfortran3-dbg -Section: debug -Architecture: mips mipsel -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libn32gfortran3 (= ${gcc:Version}), ${misc:Depends} -Description: Runtime library for GNU Fortran applications (n32 debug symbols) - Library needed for GNU Fortran applications linked against the - shared library. +Depends: gcc-4.7-base (= ${gcc:Version}), libn32gfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Replaces: gfortran-4.7-multilib (<< ${gcc:SplitVersion}) +Breaks: gfortran-4.7-multilib (<< ${gcc:SplitVersion}) +Description: Runtime library for GNU Fortran applications (n32 development files) + This package contains the headers and static library files needed to build + GNU Fortran applications. -Package: libhfgfortran3 -Section: libs +Package: libhfgfortran-4.7-dev Architecture: armel +Section: libdevel Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: libgfortran3-armhf [armel] -Description: Runtime library for GNU Fortran applications (hard float ABI) - Library needed for GNU Fortran applications linked against the - shared library. - -Package: libhfgfortran3-dbg -Section: debug -Architecture: armel -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libhfgfortran3 (= ${gcc:Version}), ${misc:Depends} -Conflicts: libgfortran3-dbg-armhf [armel] -Description: Runtime library for GNU Fortran applications (hard float ABI debug symbols) - Library needed for GNU Fortran applications linked against the - shared library. +Depends: gcc-4.7-base (= ${gcc:Version}), libhfgfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Replaces: gfortran-4.7-multilib (<< ${gcc:SplitVersion}) +Breaks: gfortran-4.7-multilib (<< ${gcc:SplitVersion}) +Description: Runtime library for GNU Fortran applications (hard float ABI development files) + This package contains the headers and static library files needed to build + GNU Fortran applications. -Package: libsfgfortran3 -Section: libs +Package: libsfgfortran-4.7-dev Architecture: armhf +Section: libdevel Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: libgfortran3-armel [armhf] -Description: Runtime library for GNU Fortran applications (soft float ABI) - Library needed for GNU Fortran applications linked against the - shared library. - -Package: libsfgfortran3-dbg -Section: debug -Architecture: armhf -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libsfgfortran3 (= ${gcc:Version}), ${misc:Depends} -Conflicts: libgfortran3-dbg-armel [armhf] -Description: Runtime library for GNU Fortran applications (hard float ABI debug symbols) - Library needed for GNU Fortran applications linked against the - shared library. +Depends: gcc-4.7-base (= ${gcc:Version}), libsfgfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Replaces: gfortran-4.7-multilib (<< ${gcc:SplitVersion}) +Breaks: gfortran-4.7-multilib (<< ${gcc:SplitVersion}) +Description: Runtime library for GNU Fortran applications (soft float ABI development files) + This package contains the headers and static library files needed to build + GNU Fortran applications. Package: gccgo-4.7 Architecture: any Priority: optional Depends: gcc-4.7-base (= ${gcc:Version}), gcc-4.7 (= ${gcc:Version}), libgo0 (>= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends} Provides: go-compiler -Suggests: ${go:multilib}, gccgo-4.7-doc, libgo0-dbg +Suggests: ${go:multilib}, gccgo-4.7-doc, libgo0-dbg (>= ${gcc:Version}) +Replaces: gcc-4.7-doc (<< 4.7.2-11) Description: GNU Go compiler This is the GNU Go compiler, which compiles Go on platforms supported by the gcc compiler. It uses the gcc backend to generate optimized code. Package: gccgo-4.7-multilib -Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mipsel powerpc ppc64 s390 s390x sparc +Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mipsel powerpc ppc64 s390 s390x sparc x32 Section: devel Priority: optional Depends: gcc-4.7-base (= ${gcc:Version}), gccgo-4.7 (= ${gcc:Version}), gcc-4.7-multilib (= ${gcc:Version}), ${dep:libgobiarch}, ${shlibs:Depends}, ${misc:Depends} @@ -1172,7 +503,7 @@ Package: lib64go0 Section: libs -Architecture: i386 powerpc sparc s390 mips mipsel +Architecture: i386 powerpc sparc s390 mips mipsel x32 Priority: optional Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Description: Runtime library for GNU Go applications (64bit) @@ -1181,7 +512,7 @@ Package: lib64go0-dbg Section: debug -Architecture: i386 powerpc sparc s390 mips mipsel +Architecture: i386 powerpc sparc s390 mips mipsel x32 Priority: extra Depends: gcc-4.7-base (= ${gcc:Version}), lib64go0 (= ${gcc:Version}), ${misc:Depends} Description: Runtime library for GNU Go applications (64bit debug symbols) @@ -1190,7 +521,7 @@ Package: lib32go0 Section: libs -Architecture: amd64 ppc64 kfreebsd-amd64 s390x +Architecture: amd64 ppc64 kfreebsd-amd64 s390x x32 Priority: optional Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Conflicts: ${confl:lib32} @@ -1200,7 +531,7 @@ Package: lib32go0-dbg Section: debug -Architecture: amd64 ppc64 kfreebsd-amd64 s390x +Architecture: amd64 ppc64 kfreebsd-amd64 s390x x32 Priority: extra Depends: gcc-4.7-base (= ${gcc:Version}), lib32go0 (= ${gcc:Version}), ${misc:Depends} Description: Runtime library for GNU Go applications (32 bit debug symbols) @@ -1225,94 +556,14 @@ Library needed for GNU Go applications linked against the shared library. -Package: libstdc++6 -Architecture: any -Section: libs -Priority: important -Depends: gcc-4.7-base (= ${gcc:Version}), ${dep:libc}, ${shlibs:Depends}, ${misc:Depends} -Multi-Arch: same -Pre-Depends: multiarch-support -Breaks: ${multiarch:breaks} -Provides: libstdc++6-armel [armel], libstdc++6-armhf [armhf] -Conflicts: scim (<< 1.4.2-1) -Description: GNU Standard C++ Library v3 - This package contains an additional runtime library for C++ programs - built with the GNU compiler. - . - libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which - was included up to g++-2.95. The first version of libstdc++-v3 appeared - in g++-3.0. - -Package: lib32stdc++6 -Architecture: amd64 ppc64 kfreebsd-amd64 s390x -Section: libs -Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib32gcc1, ${shlibs:Depends}, ${misc:Depends} -Conflicts: ${confl:lib32} -Description: GNU Standard C++ Library v3 (32 bit Version) - This package contains an additional runtime library for C++ programs - built with the GNU compiler. - -Package: lib64stdc++6 -Architecture: i386 powerpc sparc s390 mips mipsel -Section: libs -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${shlibs:Depends}, lib64gcc1, ${misc:Depends} -Description: GNU Standard C++ Library v3 (64bit) - This package contains an additional runtime library for C++ programs - built with the GNU compiler. - . - libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which - was included up to g++-2.95. The first version of libstdc++-v3 appeared - in g++-3.0. - -Package: libn32stdc++6 -Architecture: mips mipsel -Section: libs -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${shlibs:Depends}, libn32gcc1, ${misc:Depends} -Description: GNU Standard C++ Library v3 (n32) - This package contains an additional runtime library for C++ programs - built with the GNU compiler. - . - libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which - was included up to g++-2.95. The first version of libstdc++-v3 appeared - in g++-3.0. - -Package: libhfstdc++6 -Architecture: armel -Section: libs -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${shlibs:Depends}, libhfgcc1, ${misc:Depends} -Conflicts: libstdc++6-armhf [armel] -Description: GNU Standard C++ Library v3 (hard float ABI) - This package contains an additional runtime library for C++ programs - built with the GNU compiler. - . - libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which - was included up to g++-2.95. The first version of libstdc++-v3 appeared - in g++-3.0. - -Package: libsfstdc++6 -Architecture: armhf -Section: libs -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), ${shlibs:Depends}, libsfgcc1, ${misc:Depends} -Conflicts: libstdc++6-armel [armhf] -Description: GNU Standard C++ Library v3 (soft float ABI) - This package contains an additional runtime library for C++ programs - built with the GNU compiler. - . - libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which - was included up to g++-2.95. The first version of libstdc++-v3 appeared - in g++-3.0. - Package: libstdc++6-4.7-dev Architecture: any +Multi-Arch: same Section: libdevel Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), g++-4.7 (= ${gcc:Version}), libstdc++6 (>= ${gcc:Version}), ${dep:libcdev}, ${misc:Depends} +Depends: gcc-4.7-base (= ${gcc:Version}), libgcc-4.7-dev (= ${gcc:Version}), libstdc++6 (>= ${gcc:Version}), ${dep:libcdev}, ${misc:Depends} Conflicts: libg++27-dev, libg++272-dev (<< 2.7.2.8-1), libstdc++2.8-dev, libg++2.8-dev, libstdc++2.9-dev, libstdc++2.9-glibc2.1-dev, libstdc++2.10-dev (<< 1:2.95.3-2), libstdc++3.0-dev +Replaces: g++-4.7 (<< ${gcc:SplitVersion}) Suggests: libstdc++6-4.7-doc Provides: libstdc++-dev Description: GNU Standard C++ Library v3 (development files) @@ -1325,6 +576,7 @@ Package: libstdc++6-4.7-pic Architecture: any +Multi-Arch: same Section: libdevel Priority: extra Depends: gcc-4.7-base (= ${gcc:Version}), libstdc++6 (>= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), ${misc:Depends} @@ -1338,7 +590,7 @@ Architecture: any Section: debug Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libstdc++6 (>= ${gcc:Version}), libgcc1-dbg, ${shlibs:Depends}, ${misc:Depends} +Depends: gcc-4.7-base (= ${gcc:Version}), libstdc++6 (>= ${gcc:Version}), libgcc1-dbg (>= ${gcc:EpochVersion}), ${shlibs:Depends}, ${misc:Depends} Multi-Arch: same Provides: libstdc++6-4.7-dbg-armel [armel], libstdc++6-4.7-dbg-armhf [armhf] Recommends: libstdc++6-4.7-dev (= ${gcc:Version}) @@ -1347,51 +599,126 @@ This package contains the shared library of libstdc++ compiled with debugging symbols. +Package: lib32stdc++6-4.7-dev +Architecture: amd64 ppc64 kfreebsd-amd64 s390x x32 +Section: libdevel +Priority: optional +Depends: gcc-4.7-base (= ${gcc:Version}), lib32gcc-4.7-dev (= ${gcc:Version}), lib32stdc++6 (>= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), ${misc:Depends} +Replaces: libstdc++6-4.7-dev (<< ${gcc:SplitVersion}), g++-4.7-multilib (<< ${gcc:SplitVersion}) +Breaks: libstdc++6-4.7-dev (<< ${gcc:SplitVersion}), g++-4.7-multilib (<< ${gcc:SplitVersion}) +Description: GNU Standard C++ Library v3 (development files) + This package contains the headers and static library files necessary for + building C++ programs which use libstdc++. + . + libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which + was included up to g++-2.95. The first version of libstdc++-v3 appeared + in g++-3.0. + Package: lib32stdc++6-4.7-dbg -Architecture: amd64 ppc64 kfreebsd-amd64 s390x +Architecture: amd64 ppc64 kfreebsd-amd64 s390x x32 Section: debug Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib32stdc++6 (>= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), lib32gcc1-dbg, ${shlibs:Depends}, ${misc:Depends} +Depends: gcc-4.7-base (= ${gcc:Version}), lib32stdc++6 (>= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), lib32gcc1-dbg (>= ${gcc:EpochVersion}), ${shlibs:Depends}, ${misc:Depends} Conflicts: lib32stdc++6-dbg, lib32stdc++6-4.0-dbg, lib32stdc++6-4.1-dbg, lib32stdc++6-4.2-dbg, lib32stdc++6-4.3-dbg, lib32stdc++6-4.4-dbg, lib32stdc++6-4.5-dbg, lib32stdc++6-4.6-dbg Description: GNU Standard C++ Library v3 (debugging files) This package contains the shared library of libstdc++ compiled with debugging symbols. +Package: lib64stdc++6-4.7-dev +Architecture: i386 powerpc sparc s390 mips mipsel x32 +Section: libdevel +Priority: optional +Depends: gcc-4.7-base (= ${gcc:Version}), lib64gcc-4.7-dev (= ${gcc:Version}), lib64stdc++6 (>= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), ${misc:Depends} +Replaces: libstdc++6-4.7-dev (<< ${gcc:SplitVersion}), g++-4.7-multilib (<< ${gcc:SplitVersion}) +Breaks: libstdc++6-4.7-dev (<< ${gcc:SplitVersion}), g++-4.7-multilib (<< ${gcc:SplitVersion}) +Description: GNU Standard C++ Library v3 (development files) + This package contains the headers and static library files necessary for + building C++ programs which use libstdc++. + . + libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which + was included up to g++-2.95. The first version of libstdc++-v3 appeared + in g++-3.0. + Package: lib64stdc++6-4.7-dbg -Architecture: i386 powerpc sparc s390 mips mipsel +Architecture: i386 powerpc sparc s390 mips mipsel x32 Section: debug Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), lib64stdc++6 (>= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), lib64gcc1-dbg, ${shlibs:Depends}, ${misc:Depends} +Depends: gcc-4.7-base (= ${gcc:Version}), lib64stdc++6 (>= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), lib64gcc1-dbg (>= ${gcc:EpochVersion}), ${shlibs:Depends}, ${misc:Depends} Conflicts: lib64stdc++6-dbg, lib64stdc++6-4.0-dbg, lib64stdc++6-4.1-dbg, lib64stdc++6-4.2-dbg, lib64stdc++6-4.3-dbg, lib64stdc++6-4.4-dbg, lib64stdc++6-4.5-dbg, lib64stdc++6-4.6-dbg Description: GNU Standard C++ Library v3 (debugging files) This package contains the shared library of libstdc++ compiled with debugging symbols. +Package: libn32stdc++6-4.7-dev +Architecture: mips mipsel +Section: libdevel +Priority: optional +Depends: gcc-4.7-base (= ${gcc:Version}), libn32gcc-4.7-dev (= ${gcc:Version}), libn32stdc++6 (>= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), ${misc:Depends} +Replaces: libstdc++6-4.7-dev (<< ${gcc:SplitVersion}), g++-4.7-multilib (<< ${gcc:SplitVersion}) +Breaks: libstdc++6-4.7-dev (<< ${gcc:SplitVersion}), g++-4.7-multilib (<< ${gcc:SplitVersion}) +Description: GNU Standard C++ Library v3 (development files) + This package contains the headers and static library files necessary for + building C++ programs which use libstdc++. + . + libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which + was included up to g++-2.95. The first version of libstdc++-v3 appeared + in g++-3.0. + Package: libn32stdc++6-4.7-dbg Architecture: mips mipsel Section: debug Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libn32stdc++6 (>= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), libn32gcc1-dbg, ${shlibs:Depends}, ${misc:Depends} +Depends: gcc-4.7-base (= ${gcc:Version}), libn32stdc++6 (>= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), libn32gcc1-dbg (>= ${gcc:EpochVersion}), ${shlibs:Depends}, ${misc:Depends} Conflicts: libn32stdc++6-dbg, libn32stdc++6-4.0-dbg, libn32stdc++6-4.1-dbg, libn32stdc++6-4.2-dbg, libn32stdc++6-4.3-dbg, libn32stdc++6-4.4-dbg, libn32stdc++6-4.5-dbg, libn32stdc++6-4.6-dbg Description: GNU Standard C++ Library v3 (debugging files) This package contains the shared library of libstdc++ compiled with debugging symbols. +Package: libhfstdc++6-4.7-dev +Architecture: armel +Section: libdevel +Priority: optional +Depends: gcc-4.7-base (= ${gcc:Version}), libhfgcc-4.7-dev (= ${gcc:Version}), libstdc++6 (>= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), ${misc:Depends} +Replaces: libstdc++6-4.7-dev (<< ${gcc:SplitVersion}), g++-4.7-multilib (<< ${gcc:SplitVersion}) +Breaks: libstdc++6-4.7-dev (<< ${gcc:SplitVersion}), g++-4.7-multilib (<< ${gcc:SplitVersion}) +Description: GNU Standard C++ Library v3 (development files) + This package contains the headers and static library files necessary for + building C++ programs which use libstdc++. + . + libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which + was included up to g++-2.95. The first version of libstdc++-v3 appeared + in g++-3.0. + Package: libhfstdc++6-4.7-dbg Architecture: armel Section: debug Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libhfstdc++6 (>= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), libhfgcc1-dbg, ${shlibs:Depends}, ${misc:Depends} +Depends: gcc-4.7-base (= ${gcc:Version}), libhfstdc++6 (>= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), libhfgcc1-dbg (>= ${gcc:EpochVersion}), ${shlibs:Depends}, ${misc:Depends} Conflicts: libhfstdc++6-dbg, libhfstdc++6-4.3-dbg, libhfstdc++6-4.4-dbg, libhfstdc++6-4.5-dbg, libhfstdc++6-4.6-dbg, libstdc++6-armhf [armel] Description: GNU Standard C++ Library v3 (debugging files) This package contains the shared library of libstdc++ compiled with debugging symbols. +Package: libsfstdc++6-4.7-dev +Architecture: armhf +Section: libdevel +Priority: optional +Depends: gcc-4.7-base (= ${gcc:Version}), libsfgcc-4.7-dev (= ${gcc:Version}), libsfstdc++6 (>= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), ${misc:Depends} +Replaces: libstdc++6-4.7-dev (<< ${gcc:SplitVersion}), g++-4.7-multilib (<< ${gcc:SplitVersion}) +Breaks: libstdc++6-4.7-dev (<< ${gcc:SplitVersion}), g++-4.7-multilib (<< ${gcc:SplitVersion}) +Description: GNU Standard C++ Library v3 (development files) + This package contains the headers and static library files necessary for + building C++ programs which use libstdc++. + . + libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which + was included up to g++-2.95. The first version of libstdc++-v3 appeared + in g++-3.0. + Package: libsfstdc++6-4.7-dbg Architecture: armhf Section: debug Priority: extra -Depends: gcc-4.7-base (= ${gcc:Version}), libsfstdc++6 (>= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), libsfgcc1-dbg, ${shlibs:Depends}, ${misc:Depends} +Depends: gcc-4.7-base (= ${gcc:Version}), libsfstdc++6 (>= ${gcc:Version}), libstdc++6-4.7-dev (= ${gcc:Version}), libsfgcc1-dbg (>= ${gcc:EpochVersion}), ${shlibs:Depends}, ${misc:Depends} Conflicts: libsfstdc++6-dbg, libsfstdc++6-4.3-dbg, libsfstdc++6-4.4-dbg, libsfstdc++6-4.5-dbg, libsfstdc++6-4.6-dbg, libstdc++6-armel [armhf] Description: GNU Standard C++ Library v3 (debugging files) This package contains the shared library of libstdc++ compiled with @@ -1420,20 +747,6 @@ These are versions of basic static libraries such as libgcc.a compiled with the -msoft-float option, for CPUs without a floating-point unit. -Package: fixincludes -Architecture: any -Priority: optional -Depends: gcc-4.7-base (= ${gcc:Version}), gcc-4.7 (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Description: Fix non-ANSI header files - FixIncludes was created to fix non-ANSI system header files. Many - system manufacturers supply proprietary headers that are not ANSI compliant. - The GNU compilers cannot compile non-ANSI headers. Consequently, the - FixIncludes shell script was written to fix the header files. - . - Not all packages with header files are installed on the system, when the - package is built, so we make fixincludes available at build time of other - packages, such that checking tools like lintian can make use of it. - Package: gcc-4.7-doc Architecture: all Section: doc diff -Nru gcc-4.7-4.7.2/debian/control.m4 gcc-4.7-4.7.3/debian/control.m4 --- gcc-4.7-4.7.2/debian/control.m4 2013-07-25 18:49:32.000000000 +0000 +++ gcc-4.7-4.7.3/debian/control.m4 2013-07-25 18:49:34.000000000 +0000 @@ -20,6 +20,14 @@ define(`ifenabled', `ifelse(index(enabled_languages, `$1'), -1, `dnl', `$2')') +define(`CROSS_ARCH', ifdef(`CROSS_ARCH', CROSS_ARCH, `all')) +define(`libdep', `lib$2$1`'LS`'AQ (ifelse(`$3',`',`>=',`$3') ifelse(`$4',`',`${gcc:Version}',`$4'))') +define(`libdevdep', `lib$2$1`'LS`'AQ (ifelse(`$3',`',`=',`$3') ifelse(`$4',`',`${gcc:Version}',`$4'))') +define(`libdbgdep', `lib$2$1`'LS`'AQ (ifelse(`$3',`',`>=',`$3') ifelse(`$4',`',`${gcc:Version}',`$4'))') + +define(`BUILT_USING', ifelse(add_built_using,yes,`Built-Using: ${Built-Using} +')) + divert`'dnl dnl -------------------------------------------------------------------------- Source: SRCNAME @@ -44,9 +52,26 @@ ')dnl SRCNAME Standards-Version: 3.9.3 ifdef(`TARGET',`dnl cross -Build-Depends: DPKG_BUILD_DEP debhelper (>= 5.0.62), LIBC_BUILD_DEP, LIBC_BIARCH_BUILD_DEP LIBUNWIND_BUILD_DEP LIBATOMIC_OPS_BUILD_DEP AUTOGEN_BUILD_DEP AUTO_BUILD_DEP SOURCE_BUILD_DEP CROSS_BUILD_DEP CLOOG_BUILD_DEP MPC_BUILD_DEP MPFR_BUILD_DEP GMP_BUILD_DEP ELF_BUILD_DEP, zlib1g-dev, gawk, lzma, xz-utils, patchutils, BINUTILS_BUILD_DEP, bison (>= 1:2.3), flex, realpath (>= 1.9.12), lsb-release, make (>= 3.81), quilt +Build-Depends: DPKG_BUILD_DEP debhelper (>= 5.0.62), + LIBC_BUILD_DEP, LIBC_BIARCH_BUILD_DEP + LIBUNWIND_BUILD_DEP LIBATOMIC_OPS_BUILD_DEP AUTOGEN_BUILD_DEP AUTO_BUILD_DEP + SOURCE_BUILD_DEP CROSS_BUILD_DEP + CLOOG_BUILD_DEP MPC_BUILD_DEP MPFR_BUILD_DEP GMP_BUILD_DEP, + zlib1g-dev, gawk, lzma, xz-utils, patchutils, + BINUTILS_BUILD_DEP, + bison (>= 1:2.3), flex, realpath (>= 1.9.12), lsb-release, quilt ',`dnl native -Build-Depends: DPKG_BUILD_DEP debhelper (>= 5.0.62), GCC_MULTILIB_BUILD_DEP LIBC_BUILD_DEP, LIBC_BIARCH_BUILD_DEP AUTO_BUILD_DEP AUTOGEN_BUILD_DEP libunwind7-dev (>= 0.98.5-6) [ia64], libatomic-ops-dev [ia64], zlib1g-dev, gawk, lzma, xz-utils, patchutils, BINUTILS_BUILD_DEP, binutils-hppa64 (>= BINUTILSV) [hppa], gperf (>= 3.0.1), bison (>= 1:2.3), flex, gettext, texinfo (>= 4.3), FORTRAN_BUILD_DEP locales, procps, sharutils, JAVA_BUILD_DEP GNAT_BUILD_DEP GO_BUILD_DEP GDC_BUILD_DEP SPU_BUILD_DEP CLOOG_BUILD_DEP MPC_BUILD_DEP MPFR_BUILD_DEP GMP_BUILD_DEP ELF_BUILD_DEP CHECK_BUILD_DEP realpath (>= 1.9.12), chrpath, lsb-release, make (>= 3.81), quilt +Build-Depends: debhelper (>= 5.0.62), + LIBC_BUILD_DEP, LIBC_BIARCH_BUILD_DEP + AUTO_BUILD_DEP AUTOGEN_BUILD_DEP + libunwind7-dev (>= 0.98.5-6) [ia64], libatomic-ops-dev [ia64], + zlib1g-dev, gawk, lzma, xz-utils, patchutils, + binutils-hppa64 (>= BINUTILSV) [hppa], + gperf (>= 3.0.1), bison (>= 1:2.3), flex, gettext, + texinfo (>= 4.3), locales, sharutils, + procps, FORTRAN_BUILD_DEP JAVA_BUILD_DEP GNAT_BUILD_DEP GO_BUILD_DEP GDC_BUILD_DEP SPU_BUILD_DEP + CLOOG_BUILD_DEP MPC_BUILD_DEP MPFR_BUILD_DEP GMP_BUILD_DEP + CHECK_BUILD_DEP realpath (>= 1.9.12), chrpath, lsb-release, quilt Build-Depends-Indep: LIBSTDCXX_BUILD_INDEP JAVA_BUILD_INDEP ')dnl Build-Conflicts: binutils-gold @@ -105,7 +130,7 @@ Priority: PRI(required) Depends: ${misc:Depends} Replaces: ${base:Replaces} -Breaks: gcj-4.6-base (<< 4.6.1-4~), gnat-4.6 (<< 4.6.1-5~), dehydra (<= 0.9.hg20110609-2) +Breaks: gcc-4.4-base (<< 4.4.7), gcj-4.4-base (<< 4.4.6-9~), gnat-4.4-base (<< 4.4.6-3~), gcj-4.6-base (<< 4.6.1-4~), gnat-4.6 (<< 4.6.1-5~), dehydra (<= 0.9.hg20110609-2) Description: GCC, the GNU Compiler Collection (base package) This package contains files common to all languages and libraries contained in the GNU Compiler Collection (GCC). @@ -129,20 +154,46 @@ Section: devel Priority: PRI(extra) Depends: ${misc:Depends} +BUILT_USING`'dnl Description: GCC, the GNU Compiler Collection (base package) This package contains files common to all languages and libraries contained in the GNU Compiler Collection (GCC). ')`'dnl ifenabled(`java',` +ifdef(`TARGET', `', ` +ifenabled(`gcjbase',` Package: gcj`'PV-base Architecture: any +ifdef(`MULTIARCH', `Multi-Arch: same +')`'dnl Section: libs Priority: PRI(optional) Depends: ${misc:Depends} +BUILT_USING`'dnl +Description: GCC, the GNU Compiler Collection (gcj base package) + This package contains files common to all java related packages + built from the GNU Compiler Collection (GCC). +')`'dnl gccbase +')`'dnl native + +ifenabled(`gcjxbase',` +dnl override default base package dependencies to cross version +dnl This creates a toolchain that doesnt depend on the system -base packages +define(`BASETARGET', `PV`'TS') +define(`BASEDEP', `gcj`'BASETARGET-base (= ${gcc:Version})') +define(`SOFTBASEDEP', `gcj`'BASETARGET-base (>= ${gcc:SoftVersion})') + +Package: gcj`'BASETARGET-base +Architecture: any +Section: devel +Priority: PRI(extra) +Depends: ${misc:Depends} +BUILT_USING`'dnl Description: GCC, the GNU Compiler Collection (gcj base package) This package contains files common to all java related packages built from the GNU Compiler Collection (GCC). +')`'dnl ')`'dnl java ifenabled(`ada',` @@ -152,6 +203,7 @@ Priority: PRI(optional) Depends: ${misc:Depends} Breaks: gcc-4.6 (<< 4.6.1-8~) +BUILT_USING`'dnl Description: GNU Ada compiler (common files) GNAT is a compiler for the Ada programming language. It produces optimized code on platforms supported by the GNU Compiler Collection (GCC). @@ -161,7 +213,7 @@ ifenabled(`libgcc',` Package: libgcc1`'LS -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',required) Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} @@ -170,6 +222,7 @@ Pre-Depends: multiarch-support Breaks: ${multiarch:breaks} ')`Provides: libgcc1-armel [armel], libgcc1-armhf [armhf]') +BUILT_USING`'dnl Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') Shared version of the support library, a library of internal subroutines that GCC uses to overcome shortcomings of particular machines, or @@ -181,15 +234,16 @@ ')`'dnl Package: libgcc1-dbg`'LS -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') Section: debug Priority: extra -Depends: BASEDEP, libgcc1`'LS (= ${gcc:EpochVersion}), ${misc:Depends} +Depends: BASEDEP, libdep(gcc1,,=,${gcc:EpochVersion}), ${misc:Depends} ifdef(`TARGET',`',`dnl ifdef(`MULTIARCH',`Multi-Arch: same ')dnl Provides: libgcc1-dbg-armel [armel], libgcc1-dbg-armhf [armhf] ')dnl +BUILT_USING`'dnl Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `') Debug symbols for the GCC support library. ifdef(`TARGET', `dnl @@ -199,7 +253,7 @@ ')`'dnl Package: libgcc2`'LS -Architecture: ifdef(`TARGET',`all',`m68k') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`m68k') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',required) Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} @@ -208,6 +262,7 @@ Pre-Depends: multiarch-support Breaks: ${multiarch:breaks} '))`'dnl +BUILT_USING`'dnl Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') Shared version of the support library, a library of internal subroutines that GCC uses to overcome shortcomings of particular machines, or @@ -219,12 +274,13 @@ ')`'dnl Package: libgcc2-dbg`'LS -Architecture: ifdef(`TARGET',`all',`m68k') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`m68k') Section: debug Priority: extra -Depends: BASEDEP, libgcc2`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(gcc2,,=,${gcc:EpochVersion}), ${misc:Depends} ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same '))`'dnl +BUILT_USING`'dnl Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `') Debug symbols for the GCC support library. ifdef(`TARGET', `dnl @@ -234,9 +290,25 @@ ')`'dnl ')`'dnl libgcc +ifenabled(`cdev',` +Package: libgcc`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') +Section: libdevel +Priority: optional +Recommends: ${dep:libcdev} +Depends: BASEDEP, ${dep:libgcc}, ${dep:libssp}, ${dep:libgomp}, ${dep:libitm}, ${dep:libqmath}, ${dep:libunwinddev}, ${shlibs:Depends}, ${misc:Depends} +Replaces: gcc`'PV (<< ${gcc:SplitVersion}) +ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same +'))`'dnl +BUILT_USING`'dnl +Description: GCC support library (development files) + This package contains the headers and static library files necessary for + building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. +')`'dnl cdev + ifenabled(`lib4gcc',` Package: libgcc4`'LS -Architecture: ifdef(`TARGET',`all',`hppa') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`hppa') ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same Pre-Depends: multiarch-support Breaks: ${multiarch:breaks} @@ -244,6 +316,7 @@ Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',required) Depends: ifdef(`STANDALONEJAVA',`gcj`'PV-base (>= ${gcj:Version})',`BASEDEP'), ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') Shared version of the support library, a library of internal subroutines that GCC uses to overcome shortcomings of particular machines, or @@ -255,12 +328,13 @@ ')`'dnl Package: libgcc4-dbg`'LS -Architecture: ifdef(`TARGET',`all',`hppa') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`hppa') ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same '))`'dnl Section: debug Priority: extra -Depends: BASEDEP, libgcc4`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(gcc4,,=,${gcc:EpochVersion}), ${misc:Depends} +BUILT_USING`'dnl Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `') Debug symbols for the GCC support library. ifdef(`TARGET', `dnl @@ -272,13 +346,14 @@ ifenabled(`lib64gcc',` Package: lib64gcc1`'LS -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${dep:libcbiarch}, ${misc:Depends} ifdef(`TARGET',`Provides: lib64gcc1-TARGET-dcv1 ',`')`'dnl Conflicts: libgcc`'GCC_SO`'LS (<= 1:3.3-0pre9) +BUILT_USING`'dnl Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') (64bit) Shared version of the support library, a library of internal subroutines that GCC uses to overcome shortcomings of particular machines, or @@ -290,10 +365,11 @@ ')`'dnl Package: lib64gcc1-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Section: debug Priority: extra -Depends: BASEDEP, lib64gcc1`'LS (= ${gcc:EpochVersion}), ${misc:Depends} +Depends: BASEDEP, libdep(gcc1,64,=,${gcc:EpochVersion}), ${misc:Depends} +BUILT_USING`'dnl Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `') Debug symbols for the GCC support library. ifdef(`TARGET', `dnl @@ -303,15 +379,30 @@ ')`'dnl ')`'dnl lib64gcc +ifenabled(`cdev',` +Package: lib64gcc`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') +Section: libdevel +Priority: optional +Recommends: ${dep:libcdev} +Depends: BASEDEP, ${dep:libgccbiarch}, ${dep:libsspbiarch}, ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends} +Replaces: gcc`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: GCC support library (64bit development files) + This package contains the headers and static library files necessary for + building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. +')`'dnl cdev + ifenabled(`lib32gcc',` Package: lib32gcc1`'LS -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: extra Depends: BASEDEP, ${dep:libcbiarch}, ${misc:Depends} Conflicts: ${confl:lib32} ifdef(`TARGET',`Provides: lib32gcc1-TARGET-dcv1 ',`')`'dnl +BUILT_USING`'dnl Description: GCC support library (32 bit Version) Shared version of the support library, a library of internal subroutines that GCC uses to overcome shortcomings of particular machines, or @@ -323,10 +414,11 @@ ')`'dnl Package: lib32gcc1-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Section: debug Priority: extra -Depends: BASEDEP, lib32gcc1`'LS (= ${gcc:EpochVersion}), ${misc:Depends} +Depends: BASEDEP, libdep(gcc1,32,=,${gcc:EpochVersion}), ${misc:Depends} +BUILT_USING`'dnl Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `') Debug symbols for the GCC support library. ifdef(`TARGET', `dnl @@ -336,12 +428,27 @@ ')`'dnl ')`'dnl lib32gcc1 +ifenabled(`cdev',` +Package: lib32gcc`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') +Section: libdevel +Priority: optional +Recommends: ${dep:libcdev} +Depends: BASEDEP, ${dep:libgccbiarch}, ${dep:libsspbiarch}, ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends} +Replaces: gcc`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: GCC support library (32 bit development files) + This package contains the headers and static library files necessary for + building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. +')`'dnl cdev + ifenabled(`libneongcc',` Package: libgcc1-neon`'LS Architecture: NEON_ARCHS Section: libs Priority: extra Depends: BASEDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC support library [neon optimized] Shared version of the support library, a library of internal subroutines that GCC uses to overcome shortcomings of particular machines, or @@ -353,13 +460,14 @@ ifenabled(`libhfgcc',` Package: libhfgcc1`'LS -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${dep:libcbiarch}, ${misc:Depends} ifdef(`TARGET',`Provides: libhfgcc1-TARGET-dcv1 ',`Conflicts: libgcc1-armhf [biarchhf_archs] ')`'dnl +BUILT_USING`'dnl Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') (hard float ABI) Shared version of the support library, a library of internal subroutines that GCC uses to overcome shortcomings of particular machines, or @@ -371,11 +479,12 @@ ')`'dnl Package: libhfgcc1-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Section: debug Priority: extra -Depends: BASEDEP, libhfgcc1`'LS (= ${gcc:EpochVersion}), ${misc:Depends} -Conflicts: libgcc1-dbg-armhf [biarchhf_archs] +Depends: BASEDEP, libdep(gcc1,hf,=,${gcc:EpochVersion}), ${misc:Depends} +ifdef(`TARGET',`dnl',`Conflicts: libgcc1-dbg-armhf [biarchhf_archs]') +BUILT_USING`'dnl Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `') Debug symbols for the GCC support library. ifdef(`TARGET', `dnl @@ -385,15 +494,32 @@ ')`'dnl ')`'dnl libhfgcc +ifenabled(`cdev',` +ifenabled(`armml',` +Package: libhfgcc`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') +Section: libdevel +Priority: optional +Recommends: ${dep:libcdev} +Depends: BASEDEP, ${dep:libgccbiarch}, ${dep:libsspbiarch}, ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends} +Replaces: gcc`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: GCC support library (hard float ABI development files) + This package contains the headers and static library files necessary for + building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. +')`'dnl armml +')`'dnl cdev + ifenabled(`libsfgcc',` Package: libsfgcc1`'LS -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${dep:libcbiarch}, ${misc:Depends} ifdef(`TARGET',`Provides: libsfgcc1-TARGET-dcv1 ',`Conflicts: libgcc1-armel [biarchsf_archs] ')`'dnl +BUILT_USING`'dnl Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') (soft float ABI) Shared version of the support library, a library of internal subroutines that GCC uses to overcome shortcomings of particular machines, or @@ -405,11 +531,12 @@ ')`'dnl Package: libsfgcc1-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Section: debug Priority: extra -Depends: BASEDEP, libsfgcc1`'LS (= ${gcc:EpochVersion}), ${misc:Depends} -Conflicts: libgcc1-dbg-armel [biarchsf_archs] +Depends: BASEDEP, libdep(gcc1,sf,=,${gcc:EpochVersion}), ${misc:Depends} +ifdef(`TARGET',`dnl',`Conflicts: libgcc1-dbg-armel [biarchsf_archs]') +BUILT_USING`'dnl Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `') Debug symbols for the GCC support library. ifdef(`TARGET', `dnl @@ -419,15 +546,32 @@ ')`'dnl ')`'dnl libsfgcc +ifenabled(`cdev',` +ifenabled(`armml',` +Package: libsfgcc`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') +Section: libdevel +Priority: optional +Recommends: ${dep:libcdev} +Depends: BASEDEP, ${dep:libgccbiarch}, ${dep:libsspbiarch}, ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends} +Replaces: gcc`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: GCC support library (soft float ABI development files) + This package contains the headers and static library files necessary for + building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. +')`'dnl armml +')`'dnl cdev + ifenabled(`libn32gcc',` Package: libn32gcc1`'LS -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${dep:libcbiarch}, ${misc:Depends} ifdef(`TARGET',`Provides: libn32gcc1-TARGET-dcv1 ',`')`'dnl Conflicts: libgcc`'GCC_SO`'LS (<= 1:3.3-0pre9) +BUILT_USING`'dnl Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') (n32) Shared version of the support library, a library of internal subroutines that GCC uses to overcome shortcomings of particular machines, or @@ -439,10 +583,11 @@ ')`'dnl Package: libn32gcc1-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Section: debug Priority: extra -Depends: BASEDEP, libn32gcc1`'LS (= ${gcc:EpochVersion}), ${misc:Depends} +Depends: BASEDEP, libdep(gcc1,n32,=,${gcc:EpochVersion}), ${misc:Depends} +BUILT_USING`'dnl Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `') Debug symbols for the GCC support library. ifdef(`TARGET', `dnl @@ -452,6 +597,68 @@ ')`'dnl ')`'dnl libn32gcc +ifenabled(`cdev',` +Package: libn32gcc`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') +Section: libdevel +Priority: optional +Recommends: ${dep:libcdev} +Depends: BASEDEP, ${dep:libgccbiarch}, ${dep:libsspbiarch}, ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends} +Replaces: gcc`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: GCC support library (n32 development files) + This package contains the headers and static library files necessary for + building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. +')`'dnl cdev + +ifenabled(`libx32gcc',` +Package: libx32gcc1`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') +Section: ifdef(`TARGET',`devel',`libs') +Priority: ifdef(`TARGET',`extra',PRI(optional)) +Depends: BASEDEP, ${dep:libcbiarch}, ${misc:Depends} +ifdef(`TARGET',`Provides: libx32gcc1-TARGET-dcv1 +',`')`'dnl +BUILT_USING`'dnl +Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') (x32) + Shared version of the support library, a library of internal subroutines + that GCC uses to overcome shortcomings of particular machines, or + special needs for some languages. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl + +Package: libx32gcc1-dbg`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') +Section: debug +Priority: extra +Depends: BASEDEP, libdep(gcc1,x32,=,${gcc:EpochVersion}), ${misc:Depends} +BUILT_USING`'dnl +Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `') + Debug symbols for the GCC support library. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl + +ifenabled(`cdev',` +Package: libx32gcc`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') +Section: libdevel +Priority: optional +Recommends: ${dep:libcdev} +Depends: BASEDEP, ${dep:libgccbiarch}, ${dep:libsspbiarch}, ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends} +Replaces: gcc`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: GCC support library (x32 development files) + This package contains the headers and static library files necessary for + building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. +')`'dnl cdev +')`'dnl libx32gcc + ifdef(`TARGET', `', ` ifenabled(`libgmath',` Package: libgccmath`'GCCMATH_SO`'LS @@ -462,6 +669,7 @@ Section: libs Priority: PRI(optional) Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC math support library Support library for GCC. @@ -470,6 +678,7 @@ Section: libs Priority: PRI(optional) Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC math support library (32bit) Support library for GCC. @@ -478,6 +687,7 @@ Section: libs Priority: PRI(optional) Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC math support library (64bit) Support library for GCC. ')`'dnl @@ -488,10 +698,11 @@ Architecture: any Section: devel Priority: ifdef(`TARGET',`extra',`PRI(optional)') -Depends: BASEDEP, cpp`'PV`'TS (= ${gcc:Version}), binutils`'TS (>= ${binutils:Version}), ${dep:libgcc}, ${dep:libssp}, ${dep:libgomp}, ${dep:libitm}, ${dep:libqmath}, ${dep:libunwinddev}, ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, cpp`'PV`'TS (= ${gcc:Version}), binutils`'TS (>= ${binutils:Version}), libdevdep(gcc`'PV-dev,,=), ${shlibs:Depends}, ${misc:Depends} Recommends: ${dep:libcdev} -Suggests: ${gcc:multilib}, libmudflap`'MF_SO`'PV-dev`'LS (>= ${gcc:Version}), gcc`'PV-doc (>= ${gcc:SoftVersion}), gcc`'PV-locales (>= ${gcc:SoftVersion}), libgcc`'GCC_SO-dbg`'LS, libgomp`'GOMP_SO-dbg`'LS, libitm`'ITM_SO-dbg`'LS, libquadmath`'QMATH_SO-dbg`'LS, libmudflap`'MF_SO-dbg`'LS, ${dep:libcloog}, ${dep:gold} +Suggests: ${gcc:multilib}, libdevdep(mudflap`'MF_SO`'PV-dev,,>=,${gcc:Version}), gcc`'PV-doc (>= ${gcc:SoftVersion}), gcc`'PV-locales (>= ${gcc:SoftVersion}), libdbgdep(gcc`'GCC_SO-dbg,,>=,${gcc:EpochVersion}), libdbgdep(gomp`'GOMP_SO-dbg), libdbgdep(itm`'ITM_SO-dbg), libdbgdep(quadmath`'QMATH_SO-dbg,), libdbgdep(mudflap`'MF_SO-dbg,), ${dep:libcloog}, ${dep:gold} Provides: c-compiler`'TS +BUILT_USING`'dnl Description: GNU C compiler`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `') This is the GNU C compiler, a fairly portable optimizing compiler for C. ifdef(`TARGET', `dnl @@ -504,8 +715,9 @@ Architecture: ifdef(`TARGET',`any',MULTILIB_ARCHS) Section: devel Priority: ifdef(`TARGET',`extra',`PRI(optional)') -Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), ${dep:libcbiarchdev}, ${dep:libgccbiarch}, ${dep:libsspbiarch}, ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), ${dep:libcbiarchdev}, ${dep:libgccbiarchdev}, ${shlibs:Depends}, ${misc:Depends} Suggests: ${dep:libmudflapbiarch} +BUILT_USING`'dnl Description: GNU C compiler (multilib files)`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `') This is the GNU C compiler, a fairly portable optimizing compiler for C. . @@ -519,6 +731,7 @@ Section: devel Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), GMP_BUILD_DEP ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: Files for GNU GCC plugin development. This package contains (header) files for GNU GCC plugin development. It is only used for the development of GCC plugins, but not needed to run @@ -533,6 +746,7 @@ Priority: PRI(optional) Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} Conflicts: gcc-3.3-hppa64 (<= 1:3.3.4-5), gcc-3.4-hppa64 (<= 3.4.1-3) +BUILT_USING`'dnl Description: GNU C compiler (cross compiler for hppa64) This is the GNU C compiler, a fairly portable optimizing compiler for C. @@ -543,6 +757,7 @@ Priority: PRI(optional) Depends: BASEDEP, binutils-spu (>= 2.18.1~cvs20080103-3), newlib-spu, ${shlibs:Depends}, ${misc:Depends} Provides: spu-gcc +BUILT_USING`'dnl Description: SPU cross-compiler (preprocessor and C compiler) GNU Compiler Collection for the Cell Broadband Engine SPU (preprocessor and C compiler). @@ -553,6 +768,7 @@ Priority: PRI(optional) Depends: BASEDEP, gcc`'PV-spu (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} Provides: spu-g++ +BUILT_USING`'dnl Description: SPU cross-compiler (C++ compiler) GNU Compiler Collection for the Cell Broadband Engine SPU (C++ compiler). @@ -562,6 +778,7 @@ Priority: PRI(optional) Depends: BASEDEP, gcc`'PV-spu (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} Provides: spu-gfortran +BUILT_USING`'dnl Description: SPU cross-compiler (Fortran compiler) GNU Compiler Collection for the Cell Broadband Engine SPU (Fortran compiler). @@ -576,6 +793,7 @@ Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} Suggests: gcc`'PV-locales (>= ${gcc:SoftVersion}) Replaces: gcc-4.6 (<< 4.6.1-9) +BUILT_USING`'dnl Description: GNU C preprocessor A macro processor that is used automatically by the GNU C compiler to transform programs before actual compilation. @@ -621,9 +839,10 @@ Architecture: any Section: devel Priority: ifdef(`TARGET',`extra',`PRI(optional)') -Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), libstdc++CXX_SO`'PV-dev`'LS (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), libdevdep(stdc++CXX_SO`'PV-dev,,=,${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} Provides: c++-compiler`'TS`'ifdef(`TARGET)',`',`, c++abi2-dev') -Suggests: ${gxx:multilib}, gcc`'PV-doc (>= ${gcc:SoftVersion}), libstdc++CXX_SO`'PV-dbg`'LS +Suggests: ${gxx:multilib}, gcc`'PV-doc (>= ${gcc:SoftVersion}), libdbgdep(stdc++CXX_SO`'PV-dbg,) +BUILT_USING`'dnl Description: GNU C++ compiler`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `') This is the GNU C++ compiler, a fairly portable optimizing compiler for C++. ifdef(`TARGET', `dnl @@ -636,8 +855,9 @@ Architecture: ifdef(`TARGET',`any',MULTILIB_ARCHS) Section: devel Priority: ifdef(`TARGET',`extra',`PRI(optional)') -Depends: BASEDEP, g++`'PV`'TS (= ${gcc:Version}), gcc`'PV-multilib`'TS (= ${gcc:Version}), ${dep:libcxxbiarch}, ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, g++`'PV`'TS (= ${gcc:Version}), gcc`'PV-multilib`'TS (= ${gcc:Version}), ${dep:libcxxbiarchdev}, ${shlibs:Depends}, ${misc:Depends} Suggests: ${dep:libcxxbiarchdbg} +BUILT_USING`'dnl Description: GNU C++ compiler (multilib files)`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `') This is the GNU C++ compiler, a fairly portable optimizing compiler for C++. . @@ -650,7 +870,7 @@ ifenabled(`mudflap',` ifenabled(`libmudf',` Package: libmudflap`'MF_SO`'LS -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') ifdef(`TARGET',`dnl',ifdef(`MULTIARCH', `Multi-Arch: same Pre-Depends: multiarch-support Breaks: ${multiarch:breaks} @@ -658,96 +878,129 @@ Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC mudflap shared support libraries The libmudflap libraries are used by GCC for instrumenting pointer and array dereferencing operations. Package: libmudflap`'MF_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') ifdef(`TARGET',`dnl',ifdef(`MULTIARCH', `Multi-Arch: same ')`Provides: libmudflap'MF_SO`-dbg-armel [armel], libmudflap'MF_SO`-dbg-armhf [armhf]') Section: debug Priority: extra -Depends: BASEDEP, libmudflap`'MF_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(mudflap`'MF_SO,,=), ${misc:Depends} +BUILT_USING`'dnl Description: GCC mudflap shared support libraries (debug symbols) The libmudflap libraries are used by GCC for instrumenting pointer and array dereferencing operations. Package: lib32mudflap`'MF_SO`'LS -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Replaces: libmudflap0 (<< 4.1) Conflicts: ${confl:lib32} +BUILT_USING`'dnl Description: GCC mudflap shared support libraries (32bit) The libmudflap libraries are used by GCC for instrumenting pointer and array dereferencing operations. Package: lib32mudflap`'MF_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Section: debug Priority: extra -Depends: BASEDEP, lib32mudflap`'MF_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(mudflap`'MF_SO,32,=), ${misc:Depends} +BUILT_USING`'dnl Description: GCC mudflap shared support libraries (32 bit debug symbols) The libmudflap libraries are used by GCC for instrumenting pointer and array dereferencing operations. Package: lib64mudflap`'MF_SO`'LS -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Replaces: libmudflap0 (<< 4.1) +BUILT_USING`'dnl Description: GCC mudflap shared support libraries (64bit) The libmudflap libraries are used by GCC for instrumenting pointer and array dereferencing operations. Package: lib64mudflap`'MF_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Section: debug Priority: extra -Depends: BASEDEP, lib64mudflap`'MF_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(mudflap`'MF_SO,64,=), ${misc:Depends} +BUILT_USING`'dnl Description: GCC mudflap shared support libraries (64 bit debug symbols) The libmudflap libraries are used by GCC for instrumenting pointer and array dereferencing operations. Package: libn32mudflap`'MF_SO`'LS -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Replaces: libmudflap0 (<< 4.1) +BUILT_USING`'dnl Description: GCC mudflap shared support libraries (n32) The libmudflap libraries are used by GCC for instrumenting pointer and array dereferencing operations. Package: libn32mudflap`'MF_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Section: debug Priority: extra -Depends: BASEDEP, libn32mudflap`'MF_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(mudflap`'MF_SO,n32,=), ${misc:Depends} +BUILT_USING`'dnl Description: GCC mudflap shared support libraries (n32 debug symbols) The libmudflap libraries are used by GCC for instrumenting pointer and array dereferencing operations. +ifenabled(`libx32mudflap',` +Package: libx32mudflap`'MF_SO`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') +Section: ifdef(`TARGET',`devel',`libs') +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +Replaces: libmudflap0 (<< 4.1) +BUILT_USING`'dnl +Description: GCC mudflap shared support libraries (x32) + The libmudflap libraries are used by GCC for instrumenting pointer and array + dereferencing operations. + +Package: libx32mudflap`'MF_SO-dbg`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') +Section: debug +Priority: extra +Depends: BASEDEP, libdep(mudflap`'MF_SO,x32,=), ${misc:Depends} +BUILT_USING`'dnl +Description: GCC mudflap shared support libraries (x32 debug symbols) + The libmudflap libraries are used by GCC for instrumenting pointer and array + dereferencing operations. +')`'dnl libx32mudflap + ifenabled(`libhfmudflap',` Package: libhfmudflap`'MF_SO`'LS -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') -Conflicts: libmudflap`'MF_SO`'-armhf [biarchhf_archs] +ifdef(`TARGET',`dnl',`Conflicts: libmudflap`'MF_SO`'-armhf [biarchhf_archs]') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC mudflap shared support libraries (hard float) The libmudflap libraries are used by GCC for instrumenting pointer and array dereferencing operations. Package: libhfmudflap`'MF_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Section: debug Priority: extra -Depends: BASEDEP, libhfmudflap`'MF_SO`'LS (= ${gcc:Version}), ${misc:Depends} -Conflicts: libmudflap`'MF_SO`'-dbg-armhf [biarchhf_archs] +Depends: BASEDEP, libdep(mudflap`'MF_SO,hf,=), ${misc:Depends} +ifdef(`TARGET',`dnl',`Conflicts: libmudflap`'MF_SO`'-dbg-armhf [biarchhf_archs]') +BUILT_USING`'dnl Description: GCC mudflap shared support libraries (hard float debug symbols) The libmudflap libraries are used by GCC for instrumenting pointer and array dereferencing operations. @@ -755,21 +1008,23 @@ ifenabled(`libsfmudflap',` Package: libsfmudflap`'MF_SO`'LS -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: libmudflap`'MF_SO`'-armel [biarchsf_archs] +ifdef(`TARGET',`dnl',`Conflicts: libmudflap`'MF_SO`'-armel [biarchsf_archs]') +BUILT_USING`'dnl Description: GCC mudflap shared support libraries (soft float) The libmudflap libraries are used by GCC for instrumenting pointer and array dereferencing operations. Package: libsfmudflap`'MF_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Section: debug Priority: extra -Depends: BASEDEP, libsfmudflap`'MF_SO`'LS (= ${gcc:Version}), ${misc:Depends} -Conflicts: libmudflap`'MF_SO`'-dbg-armel [biarchsf_archs] +Depends: BASEDEP, libdep(mudflap`'MF_SO,sf,=), ${misc:Depends} +ifdef(`TARGET',`dnl',`Conflicts: libmudflap`'MF_SO`'-dbg-armel [biarchsf_archs]') +BUILT_USING`'dnl Description: GCC mudflap shared support libraries (soft float debug symbols) The libmudflap libraries are used by GCC for instrumenting pointer and array dereferencing operations. @@ -777,12 +1032,13 @@ ')`'dnl libmudf Package: libmudflap`'MF_SO`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') Section: ifdef(`TARGET',`devel',`libdevel') Priority: ifdef(`TARGET',`extra',`PRI(optional)') -Depends: BASEDEP, libmudflap`'MF_SO`'LS (>= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, libdevdep(mudflap`'MF_SO,,>=,${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends} Suggests: ${sug:libmudflapdev} Conflicts: libmudflap0-dev +BUILT_USING`'dnl Description: GCC mudflap support libraries (development files) The libmudflap libraries are used by GCC for instrumenting pointer and array dereferencing operations. @@ -800,6 +1056,7 @@ Section: libs Priority: PRI(optional) Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC stack smashing protection library GCC can now emit code for protecting applications from stack-smashing attacks. The protection is realized by buffer overflow detection and reordering of @@ -812,6 +1069,7 @@ Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Replaces: libssp0 (<< 4.1) Conflicts: ${confl:lib32} +BUILT_USING`'dnl Description: GCC stack smashing protection library (32bit) GCC can now emit code for protecting applications from stack-smashing attacks. The protection is realized by buffer overflow detection and reordering of @@ -823,6 +1081,7 @@ Priority: PRI(optional) Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Replaces: libssp0 (<< 4.1) +BUILT_USING`'dnl Description: GCC stack smashing protection library (64bit) GCC can now emit code for protecting applications from stack-smashing attacks. The protection is realized by buffer overflow detection and reordering of @@ -834,16 +1093,30 @@ Priority: PRI(optional) Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Replaces: libssp0 (<< 4.1) +BUILT_USING`'dnl Description: GCC stack smashing protection library (n32) GCC can now emit code for protecting applications from stack-smashing attacks. The protection is realized by buffer overflow detection and reordering of stack variables to avoid pointer corruption. +Package: libx32ssp`'SSP_SO`'LS +Architecture: biarchx32_archs +Section: libs +Priority: PRI(optional) +Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +Replaces: libssp0 (<< 4.1) +BUILT_USING`'dnl +Description: GCC stack smashing protection library (x32) + GCC can now emit code for protecting applications from stack-smashing attacks. + The protection is realized by buffer overflow detection and reordering of + stack variables to avoid pointer corruption. + Package: libhfssp`'SSP_SO`'LS Architecture: biarchhf_archs Section: libs Priority: PRI(optional) Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC stack smashing protection library (hard float ABI) GCC can now emit code for protecting applications from stack-smashing attacks. The protection is realized by buffer overflow detection and reordering of @@ -854,6 +1127,7 @@ Section: libs Priority: PRI(optional) Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC stack smashing protection library (soft float ABI) GCC can now emit code for protecting applications from stack-smashing attacks. The protection is realized by buffer overflow detection and reordering of @@ -864,99 +1138,130 @@ ifenabled(`libgomp',` Package: libgomp`'GOMP_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') ifdef(`TARGET',`dnl',ifdef(`MULTIARCH', `Multi-Arch: same Pre-Depends: multiarch-support Breaks: ${multiarch:breaks} ')`Provides: libgomp'GOMP_SO`-armel [armel], libgomp'GOMP_SO`-armhf [armhf]') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC OpenMP (GOMP) support library GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers in the GNU Compiler Collection. Package: libgomp`'GOMP_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') Section: debug Priority: extra -Depends: BASEDEP, libgomp`'GOMP_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(gomp`'GOMP_SO,,=), ${misc:Depends} ifdef(`TARGET',`dnl',ifdef(`MULTIARCH', `Multi-Arch: same ')`Provides: libgomp'GOMP_SO`-dbg-armel [armel], libgomp'GOMP_SO`-dbg-armhf [armhf]') +BUILT_USING`'dnl Description: GCC OpenMP (GOMP) support library (debug symbols) GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers in the GNU Compiler Collection. Package: lib32gomp`'GOMP_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Conflicts: ${confl:lib32} +BUILT_USING`'dnl Description: GCC OpenMP (GOMP) support library (32bit) GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers in the GNU Compiler Collection. Package: lib32gomp`'GOMP_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Section: debug Priority: extra -Depends: BASEDEP, lib32gomp`'GOMP_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(gomp`'GOMP_SO,32,=), ${misc:Depends} +BUILT_USING`'dnl Description: GCC OpenMP (GOMP) support library (32 bit debug symbols) GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers in the GNU Compiler Collection. Package: lib64gomp`'GOMP_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC OpenMP (GOMP) support library (64bit) GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers in the GNU Compiler Collection. Package: lib64gomp`'GOMP_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Section: debug Priority: extra -Depends: BASEDEP, lib64gomp`'GOMP_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(gomp`'GOMP_SO,64,=), ${misc:Depends} +BUILT_USING`'dnl Description: GCC OpenMP (GOMP) support library (64bit debug symbols) GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers in the GNU Compiler Collection. Package: libn32gomp`'GOMP_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC OpenMP (GOMP) support library (n32) GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers in the GNU Compiler Collection. Package: libn32gomp`'GOMP_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Section: debug Priority: extra -Depends: BASEDEP, libn32gomp`'GOMP_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(gomp`'GOMP_SO,n32,=), ${misc:Depends} +BUILT_USING`'dnl Description: GCC OpenMP (GOMP) support library (n32 debug symbols) GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers +ifenabled(`libx32gomp',` +Package: libx32gomp`'GOMP_SO`'LS +Section: ifdef(`TARGET',`devel',`libs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl +Description: GCC OpenMP (GOMP) support library (x32) + GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers + in the GNU Compiler Collection. + +Package: libx32gomp`'GOMP_SO-dbg`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') +Section: debug +Priority: extra +Depends: BASEDEP, libdep(gomp`'GOMP_SO,x32,=), ${misc:Depends} +BUILT_USING`'dnl +Description: GCC OpenMP (GOMP) support library (x32 debug symbols) + GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers +')`'dnl libx32gomp + ifenabled(`libhfgomp',` Package: libhfgomp`'GOMP_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: libgomp'GOMP_SO`-armhf [biarchhf_archs] +ifdef(`TARGET',`dnl',`Conflicts: libgomp'GOMP_SO`-armhf [biarchhf_archs]') +BUILT_USING`'dnl Description: GCC OpenMP (GOMP) support library (hard float ABI) GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers in the GNU Compiler Collection. Package: libhfgomp`'GOMP_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Section: debug Priority: extra -Depends: BASEDEP, libhfgomp`'GOMP_SO`'LS (= ${gcc:Version}), ${misc:Depends} -Conflicts: libgomp'GOMP_SO`-dbg-armhf [biarchhf_archs] +Depends: BASEDEP, libdep(gomp`'GOMP_SO,hf,=), ${misc:Depends} +ifdef(`TARGET',`dnl',`Conflicts: libgomp'GOMP_SO`-dbg-armhf [biarchhf_archs]') +BUILT_USING`'dnl Description: GCC OpenMP (GOMP) support library (hard float ABI debug symbols) GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers ')`'dnl libhfgomp @@ -964,20 +1269,22 @@ ifenabled(`libsfgomp',` Package: libsfgomp`'GOMP_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: libgomp'GOMP_SO`-armel [biarchsf_archs] +ifdef(`TARGET',`dnl',`Conflicts: libgomp'GOMP_SO`-armel [biarchsf_archs]') +BUILT_USING`'dnl Description: GCC OpenMP (GOMP) support library (soft float ABI) GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers in the GNU Compiler Collection. Package: libsfgomp`'GOMP_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Section: debug Priority: extra -Depends: BASEDEP, libsfgomp`'GOMP_SO`'LS (= ${gcc:Version}), ${misc:Depends} -Conflicts: libgomp'GOMP_SO`-dbg-armel [biarchsf_archs] +Depends: BASEDEP, libdep(gomp`'GOMP_SO,sf,=), ${misc:Depends} +ifdef(`TARGET',`dnl',`Conflicts: libgomp'GOMP_SO`-dbg-armel [biarchsf_archs]') +BUILT_USING`'dnl Description: GCC OpenMP (GOMP) support library (soft float ABI debug symbols) GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers ')`'dnl libsfgomp @@ -988,6 +1295,7 @@ Section: libs Priority: extra Depends: BASEDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC OpenMP (GOMP) support library [neon optimized] GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers in the GNU Compiler Collection. @@ -1000,24 +1308,26 @@ ifenabled(`libitm',` Package: libitm`'ITM_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') ifdef(`TARGET',`dnl',ifdef(`MULTIARCH', `Multi-Arch: same Pre-Depends: multiarch-support ')`Provides: libitm'ITM_SO`-armel [armel], libitm'ITM_SO`-armhf [armhf]') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GNU Transactional Memory Library GNU Transactional Memory Library (libitm) provides transaction support for accesses to the memory of a process, enabling easy-to-use synchronization of accesses to shared memory by several threads. Package: libitm`'ITM_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') Section: debug Priority: extra -Depends: BASEDEP, libitm`'ITM_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(itm`'ITM_SO,,=), ${misc:Depends} ifdef(`TARGET',`dnl',ifdef(`MULTIARCH', `Multi-Arch: same ')`Provides: libitm'ITM_SO`-dbg-armel [armel], libitm'ITM_SO`-dbg-armhf [armhf]') +BUILT_USING`'dnl Description: GNU Transactional Memory Library (debug symbols) GNU Transactional Memory Library (libitm) provides transaction support for accesses to the memory of a process, enabling easy-to-use synchronization of @@ -1025,20 +1335,22 @@ Package: lib32itm`'ITM_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Conflicts: ${confl:lib32} +BUILT_USING`'dnl Description: GNU Transactional Memory Library (32bit) GNU Transactional Memory Library (libitm) provides transaction support for accesses to the memory of a process, enabling easy-to-use synchronization of accesses to shared memory by several threads. Package: lib32itm`'ITM_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Section: debug Priority: extra -Depends: BASEDEP, lib32itm`'ITM_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(itm`'ITM_SO,32,=), ${misc:Depends} +BUILT_USING`'dnl Description: GNU Transactional Memory Library (32 bit debug symbols) GNU Transactional Memory Library (libitm) provides transaction support for accesses to the memory of a process, enabling easy-to-use synchronization of @@ -1046,19 +1358,21 @@ Package: lib64itm`'ITM_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GNU Transactional Memory Library (64bit) GNU Transactional Memory Library (libitm) provides transaction support for accesses to the memory of a process, enabling easy-to-use synchronization of accesses to shared memory by several threads. Package: lib64itm`'ITM_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Section: debug Priority: extra -Depends: BASEDEP, lib64itm`'ITM_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(itm`'ITM_SO,64,=), ${misc:Depends} +BUILT_USING`'dnl Description: GNU Transactional Memory Library (64bit debug symbols) GNU Transactional Memory Library (libitm) provides transaction support for accesses to the memory of a process, enabling easy-to-use synchronization of @@ -1066,42 +1380,70 @@ Package: libn32itm`'ITM_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GNU Transactional Memory Library (n32) GNU Transactional Memory Library (libitm) provides transaction support for accesses to the memory of a process, enabling easy-to-use synchronization of accesses to shared memory by several threads. Package: libn32itm`'ITM_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Section: debug Priority: extra -Depends: BASEDEP, libn32itm`'ITM_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(itm`'ITM_SO,n32,=), ${misc:Depends} +BUILT_USING`'dnl Description: GNU Transactional Memory Library (n32 debug symbols) GNU Transactional Memory Library (libitm) provides transaction support for accesses to the memory of a process, enabling easy-to-use synchronization of accesses to shared memory by several threads. +ifenabled(`libx32itm',` +Package: libx32itm`'ITM_SO`'LS +Section: ifdef(`TARGET',`devel',`libs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl +Description: GNU Transactional Memory Library (x32) + This manual documents the usage and internals of libitm. It provides + transaction support for accesses to the memory of a process, enabling + easy-to-use synchronization of accesses to shared memory by several threads. + +Package: libx32itm`'ITM_SO-dbg`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') +Section: debug +Priority: extra +Depends: BASEDEP, libdep(itm`'ITM_SO,x32,=), ${misc:Depends} +BUILT_USING`'dnl +Description: GNU Transactional Memory Library (x32 debug symbols) + This manual documents the usage and internals of libitm. It provides + transaction support for accesses to the memory of a process, enabling + easy-to-use synchronization of accesses to shared memory by several threads. +')`'dnl libx32itm + ifenabled(`libhfitm',` Package: libhfitm`'ITM_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: libitm'ITM_SO`-armhf [biarchhf_archs] +ifdef(`TARGET',`dnl',`Conflicts: libitm'ITM_SO`-armhf [biarchhf_archs]') +BUILT_USING`'dnl Description: GNU Transactional Memory Library (hard float ABI) GNU Transactional Memory Library (libitm) provides transaction support for accesses to the memory of a process, enabling easy-to-use synchronization of accesses to shared memory by several threads. Package: libhfitm`'ITM_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Section: debug Priority: extra -Depends: BASEDEP, libhfitm`'ITM_SO`'LS (= ${gcc:Version}), ${misc:Depends} -Conflicts: libitm'ITM_SO`-armel [biarchsf_archs] +Depends: BASEDEP, libdep(itm`'ITM_SO,hf,=), ${misc:Depends} +ifdef(`TARGET',`dnl',`Conflicts: libitm'ITM_SO`-armel [biarchsf_archs]') +BUILT_USING`'dnl Description: GNU Transactional Memory Library (hard float ABI debug symbols) GNU Transactional Memory Library (libitm) provides transaction support for accesses to the memory of a process, enabling easy-to-use synchronization of @@ -1111,19 +1453,21 @@ ifenabled(`libsfitm',` Package: libsfitm`'ITM_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GNU Transactional Memory Library (soft float ABI) GNU Transactional Memory Library (libitm) provides transaction support for accesses to the memory of a process, enabling easy-to-use synchronization of accesses to shared memory by several threads. Package: libsfitm`'ITM_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Section: debug Priority: extra -Depends: BASEDEP, libsfitm`'ITM_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(itm`'ITM_SO,sf,=), ${misc:Depends} +BUILT_USING`'dnl Description: GNU Transactional Memory Library (soft float ABI debug symbols) GNU Transactional Memory Library (libitm) provides transaction support for accesses to the memory of a process, enabling easy-to-use synchronization of @@ -1136,6 +1480,7 @@ Section: libs Priority: extra Depends: BASEDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GNU Transactional Memory Library [neon optimized] GNU Transactional Memory Library (libitm) provides transaction support for accesses to the memory of a process, enabling easy-to-use synchronization of @@ -1149,102 +1494,135 @@ ifenabled(`libqmath',` Package: libquadmath`'QMATH_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') ifdef(`TARGET',`dnl',ifdef(`MULTIARCH', `Multi-Arch: same Pre-Depends: multiarch-support '))`'dnl Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC Quad-Precision Math Library A library, which provides quad-precision mathematical functions on targets supporting the __float128 datatype. The library is used to provide on such targets the REAL(16) type in the GNU Fortran compiler. Package: libquadmath`'QMATH_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') Section: debug Priority: extra -Depends: BASEDEP, libquadmath`'QMATH_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(quadmath`'QMATH_SO,,=), ${misc:Depends} ifdef(`TARGET',`dnl',ifdef(`MULTIARCH', `Multi-Arch: same '))`'dnl +BUILT_USING`'dnl Description: GCC Quad-Precision Math Library (debug symbols) A library, which provides quad-precision mathematical functions on targets supporting the __float128 datatype. Package: lib32quadmath`'QMATH_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Conflicts: ${confl:lib32} +BUILT_USING`'dnl Description: GCC Quad-Precision Math Library (32bit) A library, which provides quad-precision mathematical functions on targets supporting the __float128 datatype. The library is used to provide on such targets the REAL(16) type in the GNU Fortran compiler. Package: lib32quadmath`'QMATH_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Section: debug Priority: extra -Depends: BASEDEP, lib32quadmath`'QMATH_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(quadmath`'QMATH_SO,32,=), ${misc:Depends} +BUILT_USING`'dnl Description: GCC Quad-Precision Math Library (32 bit debug symbols) A library, which provides quad-precision mathematical functions on targets supporting the __float128 datatype. Package: lib64quadmath`'QMATH_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC Quad-Precision Math Library (64bit) A library, which provides quad-precision mathematical functions on targets supporting the __float128 datatype. The library is used to provide on such targets the REAL(16) type in the GNU Fortran compiler. Package: lib64quadmath`'QMATH_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Section: debug Priority: extra -Depends: BASEDEP, lib64quadmath`'QMATH_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(quadmath`'QMATH_SO,64,=), ${misc:Depends} +BUILT_USING`'dnl Description: GCC Quad-Precision Math Library (64bit debug symbols) A library, which provides quad-precision mathematical functions on targets supporting the __float128 datatype. Package: libn32quadmath`'QMATH_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC Quad-Precision Math Library (n32) A library, which provides quad-precision mathematical functions on targets supporting the __float128 datatype. The library is used to provide on such targets the REAL(16) type in the GNU Fortran compiler. Package: libn32quadmath`'QMATH_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Section: debug Priority: extra -Depends: BASEDEP, libn32quadmath`'QMATH_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(quadmath`'QMATH_SO,n32,=), ${misc:Depends} +BUILT_USING`'dnl Description: GCC Quad-Precision Math Library (n32 debug symbols) A library, which provides quad-precision mathematical functions on targets supporting the __float128 datatype. +ifenabled(`libx32qmath',` +Package: libx32quadmath`'QMATH_SO`'LS +Section: ifdef(`TARGET',`devel',`libs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl +Description: GCC Quad-Precision Math Library (x32) + A library, which provides quad-precision mathematical functions on targets + supporting the __float128 datatype. The library is used to provide on such + targets the REAL(16) type in the GNU Fortran compiler. + +Package: libx32quadmath`'QMATH_SO-dbg`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') +Section: debug +Priority: extra +Depends: BASEDEP, libdep(quadmath`'QMATH_SO,x32,=), ${misc:Depends} +BUILT_USING`'dnl +Description: GCC Quad-Precision Math Library (x32 debug symbols) + A library, which provides quad-precision mathematical functions on targets + supporting the __float128 datatype. +')`'dnl libx32qmath + ifenabled(`libhfqmath',` Package: libhfquadmath`'QMATH_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC Quad-Precision Math Library (hard float ABI) A library, which provides quad-precision mathematical functions on targets supporting the __float128 datatype. The library is used to provide on such targets the REAL(16) type in the GNU Fortran compiler. Package: libhfquadmath`'QMATH_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Section: debug Priority: extra -Depends: BASEDEP, libhfquadmath`'QMATH_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(quadmath`'QMATH_SO,hf,=), ${misc:Depends} +BUILT_USING`'dnl Description: GCC Quad-Precision Math Library (hard float ABI debug symbols) A library, which provides quad-precision mathematical functions on targets supporting the __float128 datatype. @@ -1253,19 +1631,21 @@ ifenabled(`libsfqmath',` Package: libsfquadmath`'QMATH_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GCC Quad-Precision Math Library (soft float ABI) A library, which provides quad-precision mathematical functions on targets supporting the __float128 datatype. The library is used to provide on such targets the REAL(16) type in the GNU Fortran compiler. Package: libsfquadmath`'QMATH_SO-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Section: debug Priority: extra -Depends: BASEDEP, libsfquadmath`'QMATH_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(quadmath`'QMATH_SO,sf,=), ${misc:Depends} +BUILT_USING`'dnl Description: GCC Quad-Precision Math Library (hard float ABI debug symbols) A library, which provides quad-precision mathematical functions on targets supporting the __float128 datatype. @@ -1277,9 +1657,10 @@ Package: gobjc++`'PV`'TS Architecture: any Priority: ifdef(`TARGET',`extra',`PRI(optional)') -Depends: BASEDEP, gobjc`'PV`'TS (= ${gcc:Version}), g++`'PV`'TS (= ${gcc:Version}), ${shlibs:Depends}, libobjc`'OBJC_SO`'LS (>= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, gobjc`'PV`'TS (= ${gcc:Version}), g++`'PV`'TS (= ${gcc:Version}), ${shlibs:Depends}, libdevdep(objc`'PV-dev,,=), ${misc:Depends} Suggests: ${gobjcxx:multilib}, gcc`'PV-doc (>= ${gcc:SoftVersion}) Provides: objc++-compiler`'TS +BUILT_USING`'dnl Description: GNU Objective-C++ compiler This is the GNU Objective-C++ compiler, which compiles Objective-C++ on platforms supported by the gcc compiler. It uses the @@ -1292,6 +1673,7 @@ Section: devel Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, gobjc++`'PV`'TS (= ${gcc:Version}), g++`'PV-multilib`'TS (= ${gcc:Version}), gobjc`'PV-multilib`'TS (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GNU Objective-C++ compiler (multilib files) This is the GNU Objective-C++ compiler, which compiles Objective-C++ on platforms supported by the gcc compiler. @@ -1306,10 +1688,11 @@ Package: gobjc`'PV`'TS Architecture: any Priority: ifdef(`TARGET',`extra',`PRI(optional)') -Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, libobjc`'OBJC_SO`'LS (>= ${gcc:Version}), ${misc:Depends} -Suggests: ${gobjc:multilib}, gcc`'PV-doc (>= ${gcc:SoftVersion}), libobjc`'OBJC_SO-dbg`'LS +Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, libdevdep(objc`'PV-dev,,=), ${misc:Depends} +Suggests: ${gobjc:multilib}, gcc`'PV-doc (>= ${gcc:SoftVersion}), libdbgdep(objc`'OBJC_SO-dbg,) Provides: objc-compiler`'TS ifdef(`__sparc__',`Conflicts: gcc`'PV-sparc64', `dnl') +BUILT_USING`'dnl Description: GNU Objective-C compiler This is the GNU Objective-C compiler, which compiles Objective-C on platforms supported by the gcc compiler. It uses the @@ -1320,7 +1703,8 @@ Architecture: ifdef(`TARGET',`any',MULTILIB_ARCHS) Section: devel Priority: ifdef(`TARGET',`extra',`PRI(optional)') -Depends: BASEDEP, gobjc`'PV`'TS (= ${gcc:Version}), gcc`'PV-multilib`'TS (= ${gcc:Version}), ${dep:libobjcbiarch}, ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, gobjc`'PV`'TS (= ${gcc:Version}), gcc`'PV-multilib`'TS (= ${gcc:Version}), ${dep:libobjcbiarchdev}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GNU Objective-C compiler (multilib files)`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `') This is the GNU Objective-C compiler, which compiles Objective-C on platforms supported by the gcc compiler. @@ -1328,28 +1712,114 @@ On architectures with multilib support, the package contains files and dependencies for the non-default multilib architecture(s). ')`'dnl multilib + +Package: libobjc`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') +Section: libdevel +Priority: optional +Depends: BASEDEP, libdevdep(gcc`'PV-dev,,=), libdep(objc`'OBJC_SO,,>=), ${shlibs:Depends}, ${misc:Depends} +Replaces: gobjc`'PV (<< ${gcc:SplitVersion}) +ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same +'))`'dnl +BUILT_USING`'dnl +Description: Runtime library for GNU Objective-C applications (development files) + This package contains the headers and static library files needed to build + GNU ObjC applications. + +Package: lib64objc`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') +Section: libdevel +Priority: optional +Depends: BASEDEP, libdevdep(gcc`'PV-dev,64,=), libdep(objc`'OBJC_SO,64,>=), ${shlibs:Depends}, ${misc:Depends} +Replaces: gobjc`'PV-multilib (<< ${gcc:SplitVersion}) +Description: Runtime library for GNU Objective-C applications (64bit development files) + This package contains the headers and static library files needed to build + GNU ObjC applications. + +Package: lib32objc`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') +Section: libdevel +Priority: optional +Depends: BASEDEP, libdevdep(gcc`'PV-dev,32,=), libdep(objc`'OBJC_SO,32,>=), ${shlibs:Depends}, ${misc:Depends} +Replaces: gobjc`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: Runtime library for GNU Objective-C applications (32bit development files) + This package contains the headers and static library files needed to build + GNU ObjC applications. + +Package: libn32objc`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') +Section: libdevel +Priority: optional +Depends: BASEDEP, libdevdep(gcc`'PV-dev,n32,=), libdep(objc`'OBJC_SO,n32,>=), ${shlibs:Depends}, ${misc:Depends} +Replaces: gobjc`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: Runtime library for GNU Objective-C applications (n32 development files) + This package contains the headers and static library files needed to build + GNU ObjC applications. + +ifenabled(`libx32objc',` +Package: libx32objc`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') +Section: libdevel +Priority: optional +Depends: BASEDEP, libdevdep(gcc`'PV-dev,x32,=), libdep(objc`'OBJC_SO,x32,>=), ${shlibs:Depends}, ${misc:Depends} +Replaces: gobjc`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: Runtime library for GNU Objective-C applications (x32 development files) + This package contains the headers and static library files needed to build + GNU ObjC applications. +')`'dnl libx32objc + +ifenabled(`armml',` +Package: libhfobjc`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') +Section: libdevel +Priority: optional +Depends: BASEDEP, libdevdep(gcc`'PV-dev,hf,=), libdep(objc`'OBJC_SO,hf,>=), ${shlibs:Depends}, ${misc:Depends} +Replaces: gobjc`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: Runtime library for GNU Objective-C applications (hard float ABI development files) + This package contains the headers and static library files needed to build + GNU ObjC applications. +')`'dnl armml + +ifenabled(`armml',` +Package: libsfobjc`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') +Section: libdevel +Priority: optional +Depends: BASEDEP, libdevdep(gcc`'PV-dev,sf,=), libdep(objc`'OBJC_SO,sf,>=), ${shlibs:Depends}, ${misc:Depends} +Replaces: gobjc`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: Runtime library for GNU Objective-C applications (soft float development files) + This package contains the headers and static library files needed to build + GNU ObjC applications. +')`'dnl armml ')`'dnl objcdev ifenabled(`libobjc',` Package: libobjc`'OBJC_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') ifdef(`TARGET',`dnl',ifdef(`MULTIARCH', `Multi-Arch: same Pre-Depends: multiarch-support ifelse(OBJC_SO,`2',`Breaks: ${multiarch:breaks} ',`')')`Provides: libobjc'OBJC_SO`-armel [armel], libobjc'OBJC_SO`-armhf [armhf]') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Objective-C applications Library needed for GNU ObjC applications linked against the shared library. Package: libobjc`'OBJC_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') ifdef(`TARGET',`dnl',ifdef(`MULTIARCH', `Multi-Arch: same ')`Provides: libobjc'OBJC_SO`-dbg-armel [armel], libobjc'OBJC_SO`-dbg-armhf [armhf]') Priority: extra -Depends: BASEDEP, libobjc`'OBJC_SO`'LS (= ${gcc:Version}), libgcc`'GCC_SO-dbg`'LS, ${misc:Depends} +Depends: BASEDEP, libdep(objc`'OBJC_SO,,=), libdbgdep(gcc`'GCC_SO-dbg,,>=,${gcc:EpochVersion}), ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Objective-C applications (debug symbols) Library needed for GNU ObjC applications linked against the shared library. ')`'dnl libobjc @@ -1357,17 +1827,19 @@ ifenabled(`lib64objc',` Package: lib64objc`'OBJC_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Objective-C applications (64bit) Library needed for GNU ObjC applications linked against the shared library. Package: lib64objc`'OBJC_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Priority: extra -Depends: BASEDEP, lib64objc`'OBJC_SO`'LS (= ${gcc:Version}), lib64gcc`'GCC_SO-dbg`'LS, ${misc:Depends} +Depends: BASEDEP, libdep(objc`'OBJC_SO,64,=), libdbgdep(gcc`'GCC_SO-dbg,64,>=,${gcc:EpochVersion}), ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Objective-C applications (64 bit debug symbols) Library needed for GNU ObjC applications linked against the shared library. ')`'dnl lib64objc @@ -1375,18 +1847,20 @@ ifenabled(`lib32objc',` Package: lib32objc`'OBJC_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Conflicts: ${confl:lib32} +BUILT_USING`'dnl Description: Runtime library for GNU Objective-C applications (32bit) Library needed for GNU ObjC applications linked against the shared library. Package: lib32objc`'OBJC_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Priority: extra -Depends: BASEDEP, lib32objc`'OBJC_SO`'LS (= ${gcc:Version}), lib32gcc`'GCC_SO-dbg`'LS, ${misc:Depends} +Depends: BASEDEP, libdep(objc`'OBJC_SO,32,=), libdbgdep(gcc`'GCC_SO-dbg,32,>=,${gcc:EpochVersion}), ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Objective-C applications (32 bit debug symbols) Library needed for GNU ObjC applications linked against the shared library. ')`'dnl lib32objc @@ -1394,37 +1868,61 @@ ifenabled(`libn32objc',` Package: libn32objc`'OBJC_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Objective-C applications (n32) Library needed for GNU ObjC applications linked against the shared library. Package: libn32objc`'OBJC_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Priority: extra -Depends: BASEDEP, libn32objc`'OBJC_SO`'LS (= ${gcc:Version}), libn32gcc`'GCC_SO-dbg`'LS, ${misc:Depends} +Depends: BASEDEP, libdep(objc`'OBJC_SO,n32,=), libdbgdep(gcc`'GCC_SO-dbg,n32,>=,${gcc:EpochVersion}), ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Objective-C applications (n32 debug symbols) Library needed for GNU ObjC applications linked against the shared library. ')`'dnl libn32objc +ifenabled(`libx32objc',` +Package: libx32objc`'OBJC_SO`'LS +Section: ifdef(`TARGET',`devel',`libs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl +Description: Runtime library for GNU Objective-C applications (x32) + Library needed for GNU ObjC applications linked against the shared library. + +Package: libx32objc`'OBJC_SO-dbg`'LS +Section: debug +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') +Priority: extra +Depends: BASEDEP, libdep(objc`'OBJC_SO,x32,=), libdbgdep(gcc`'GCC_SO-dbg,x32,>=,${gcc:EpochVersion}), ${misc:Depends} +BUILT_USING`'dnl +Description: Runtime library for GNU Objective-C applications (x32 debug symbols) + Library needed for GNU ObjC applications linked against the shared library. +')`'dnl libx32objc + ifenabled(`libhfobjc',` Package: libhfobjc`'OBJC_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: libobjc'OBJC_SO`-armhf [biarchhf_archs] +ifdef(`TARGET',`dnl',`Conflicts: libobjc'OBJC_SO`-armhf [biarchhf_archs]') +BUILT_USING`'dnl Description: Runtime library for GNU Objective-C applications (hard float ABI) Library needed for GNU ObjC applications linked against the shared library. Package: libhfobjc`'OBJC_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Priority: extra -Depends: BASEDEP, libhfobjc`'OBJC_SO`'LS (= ${gcc:Version}), libhfgcc`'GCC_SO-dbg`'LS, ${misc:Depends} -Conflicts: libobjc'OBJC_SO`-dbg-armhf [biarchhf_archs] +Depends: BASEDEP, libdep(objc`'OBJC_SO,hf,=), libdbgdep(gcc`'GCC_SO-dbg,hf,>=,${gcc:EpochVersion}), ${misc:Depends} +ifdef(`TARGET',`dnl',`Conflicts: libobjc'OBJC_SO`-dbg-armhf [biarchhf_archs]') +BUILT_USING`'dnl Description: Runtime library for GNU Objective-C applications (hard float ABI debug symbols) Library needed for GNU ObjC applications linked against the shared library. ')`'dnl libhfobjc @@ -1432,19 +1930,21 @@ ifenabled(`libsfobjc',` Package: libsfobjc`'OBJC_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: libobjc'OBJC_SO`-armel [biarchsf_archs] +ifdef(`TARGET',`dnl',`Conflicts: libobjc'OBJC_SO`-armel [biarchsf_archs]') +BUILT_USING`'dnl Description: Runtime library for GNU Objective-C applications (soft float ABI) Library needed for GNU ObjC applications linked against the shared library. Package: libsfobjc`'OBJC_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Priority: extra -Depends: BASEDEP, libsfobjc`'OBJC_SO`'LS (= ${gcc:Version}), libsfgcc`'GCC_SO-dbg`'LS, ${misc:Depends} -Conflicts: libobjc'OBJC_SO`-dbg-armel [biarchsf_archs] +Depends: BASEDEP, libdep(objc`'OBJC_SO,sf,=), libdbgdep(gcc`'GCC_SO-dbg,sf,>=,${gcc:EpochVersion}), ${misc:Depends} +ifdef(`TARGET',`dnl',`Conflicts: libobjc'OBJC_SO`-dbg-armel [biarchsf_archs]') +BUILT_USING`'dnl Description: Runtime library for GNU Objective-C applications (soft float ABI debug symbols) Library needed for GNU ObjC applications linked against the shared library. ')`'dnl libsfobjc @@ -1455,6 +1955,7 @@ Architecture: NEON_ARCHS Priority: PRI(optional) Depends: BASEDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Objective-C applications [NEON version] Library needed for GNU ObjC applications linked against the shared library. . @@ -1468,10 +1969,10 @@ Package: gfortran`'PV`'TS Architecture: any Priority: ifdef(`TARGET',`extra',`PRI(optional)') -Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), libgfortran`'FORTRAN_SO`'LS (>= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), libdevdep(gfortran`'PV-dev,,=), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends} Provides: fortran95-compiler -Suggests: ${gfortran:multilib}, gfortran`'PV-doc, libgfortran`'FORTRAN_SO-dbg`'LS -Replaces: libgfortran`'FORTRAN_SO-dev +Suggests: ${gfortran:multilib}, gfortran`'PV-doc, libdbgdep(gfortran`'FORTRAN_SO-dbg,) +BUILT_USING`'dnl Description: GNU Fortran compiler This is the GNU Fortran compiler, which compiles Fortran on platforms supported by the gcc compiler. It uses the @@ -1482,7 +1983,8 @@ Architecture: ifdef(`TARGET',`any',MULTILIB_ARCHS) Section: devel Priority: ifdef(`TARGET',`extra',`PRI(optional)') -Depends: BASEDEP, gfortran`'PV`'TS (= ${gcc:Version}), gcc`'PV-multilib`'TS (= ${gcc:Version}), ${dep:libgfortranbiarch}, ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, gfortran`'PV`'TS (= ${gcc:Version}), gcc`'PV-multilib`'TS (= ${gcc:Version}), ${dep:libgfortranbiarchdev}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GNU Fortran compiler (multilib files)`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `') This is the GNU Fortran compiler, which compiles Fortran on platforms supported by the gcc compiler. @@ -1500,29 +2002,123 @@ Description: Documentation for the GNU Fortran compiler (gfortran) Documentation for the GNU Fortran compiler in info `format'. ')`'dnl gfdldoc + +Package: libgfortran`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') +Section: ifdef(`TARGET',`devel',`libdevel') +Priority: optional +Depends: BASEDEP, libdep(gfortran`'FORTRAN_SO,), ${shlibs:Depends}, ${misc:Depends} +Replaces: gfortran`'PV (<< ${gcc:SplitVersion}) +Breaks: gfortran`'PV (<< ${gcc:SplitVersion}) +ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same +'))`'dnl +BUILT_USING`'dnl +Description: Runtime library for GNU Fortran applications (development files) + This package contains the headers and static library files needed to build + GNU Fortran applications. + +Package: lib64gfortran`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') +Section: libdevel +Priority: optional +Depends: BASEDEP, libdep(gfortran`'FORTRAN_SO,64,>=), ${shlibs:Depends}, ${misc:Depends} +Replaces: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) +Breaks: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: Runtime library for GNU Fortran applications (64bit development files) + This package contains the headers and static library files needed to build + GNU Fortran applications. + +Package: lib32gfortran`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') +Section: libdevel +Priority: optional +Depends: BASEDEP, libdep(gfortran`'FORTRAN_SO,32,>=), ${shlibs:Depends}, ${misc:Depends} +Replaces: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) +Breaks: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: Runtime library for GNU Fortran applications (32bit development files) + This package contains the headers and static library files needed to build + GNU Fortran applications. + +Package: libn32gfortran`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') +Section: libdevel +Priority: optional +Depends: BASEDEP, libdep(gfortran`'FORTRAN_SO,n32,>=), ${shlibs:Depends}, ${misc:Depends} +Replaces: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) +Breaks: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: Runtime library for GNU Fortran applications (n32 development files) + This package contains the headers and static library files needed to build + GNU Fortran applications. + +ifenabled(`libx32gfortran',` +Package: libx32gfortran`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') +Section: libdevel +Priority: optional +Depends: BASEDEP, libdep(gfortran`'FORTRAN_SO,x32,>=), ${shlibs:Depends}, ${misc:Depends} +Replaces: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) +Breaks: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: Runtime library for GNU Fortran applications (x32 development files) + This package contains the headers and static library files needed to build + GNU Fortran applications. +')`'dnl libx32gfortran + +ifenabled(`armml',` +Package: libhfgfortran`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') +Section: libdevel +Priority: optional +Depends: BASEDEP, libdep(gfortran`'FORTRAN_SO,hf,>=), ${shlibs:Depends}, ${misc:Depends} +Replaces: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) +Breaks: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: Runtime library for GNU Fortran applications (hard float ABI development files) + This package contains the headers and static library files needed to build + GNU Fortran applications. +')`'dnl armml + +ifenabled(`armml',` +Package: libsfgfortran`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') +Section: libdevel +Priority: optional +Depends: BASEDEP, libdep(gfortran`'FORTRAN_SO,sf,>=), ${shlibs:Depends}, ${misc:Depends} +Replaces: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) +Breaks: gfortran`'PV-multilib (<< ${gcc:SplitVersion}) +BUILT_USING`'dnl +Description: Runtime library for GNU Fortran applications (soft float ABI development files) + This package contains the headers and static library files needed to build + GNU Fortran applications. +')`'dnl armml ')`'dnl fdev ifenabled(`libgfortran',` Package: libgfortran`'FORTRAN_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') ifdef(`TARGET',`dnl',ifdef(`MULTIARCH', `Multi-Arch: same Pre-Depends: multiarch-support Breaks: ${multiarch:breaks} ')`Provides: libgfortran'FORTRAN_SO`-armel [armel], libgfortran'FORTRAN_SO`-armhf [armhf]') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Fortran applications Library needed for GNU Fortran applications linked against the shared library. Package: libgfortran`'FORTRAN_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') ifdef(`TARGET',`dnl',ifdef(`MULTIARCH', `Multi-Arch: same ')`Provides: libgfortran'FORTRAN_SO`-dbg-armel [armel], libgfortran'FORTRAN_SO`-dbg-armhf [armhf]') Priority: extra -Depends: BASEDEP, libgfortran`'FORTRAN_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(gfortran`'FORTRAN_SO,,=), ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Fortran applications (debug symbols) Library needed for GNU Fortran applications linked against the shared library. @@ -1531,18 +2127,20 @@ ifenabled(`lib64gfortran',` Package: lib64gfortran`'FORTRAN_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Fortran applications (64bit) Library needed for GNU Fortran applications linked against the shared library. Package: lib64gfortran`'FORTRAN_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Priority: extra -Depends: BASEDEP, lib64gfortran`'FORTRAN_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(gfortran`'FORTRAN_SO,64,=), ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Fortran applications (64bit debug symbols) Library needed for GNU Fortran applications linked against the shared library. @@ -1551,19 +2149,21 @@ ifenabled(`lib32gfortran',` Package: lib32gfortran`'FORTRAN_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Conflicts: ${confl:lib32} +BUILT_USING`'dnl Description: Runtime library for GNU Fortran applications (32bit) Library needed for GNU Fortran applications linked against the shared library. Package: lib32gfortran`'FORTRAN_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Priority: extra -Depends: BASEDEP, lib32gfortran`'FORTRAN_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(gfortran`'FORTRAN_SO,32,=), ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Fortran applications (32 bit debug symbols) Library needed for GNU Fortran applications linked against the shared library. @@ -1572,40 +2172,66 @@ ifenabled(`libn32gfortran',` Package: libn32gfortran`'FORTRAN_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Fortran applications (n32) Library needed for GNU Fortran applications linked against the shared library. Package: libn32gfortran`'FORTRAN_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Priority: extra -Depends: BASEDEP, libn32gfortran`'FORTRAN_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(gfortran`'FORTRAN_SO,n32,=), ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Fortran applications (n32 debug symbols) Library needed for GNU Fortran applications linked against the shared library. ')`'dnl libn32gfortran +ifenabled(`libx32gfortran',` +Package: libx32gfortran`'FORTRAN_SO`'LS +Section: ifdef(`TARGET',`devel',`libs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') +Priority: ifdef(`TARGET',`extra',PRI(optional)) +Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl +Description: Runtime library for GNU Fortran applications (x32) + Library needed for GNU Fortran applications linked against the + shared library. + +Package: libx32gfortran`'FORTRAN_SO-dbg`'LS +Section: debug +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') +Priority: extra +Depends: BASEDEP, libdep(gfortran`'FORTRAN_SO,x32,=), ${misc:Depends} +BUILT_USING`'dnl +Description: Runtime library for GNU Fortran applications (x32 debug symbols) + Library needed for GNU Fortran applications linked against the + shared library. +')`'dnl libx32gfortran + ifenabled(`libhfgfortran',` Package: libhfgfortran`'FORTRAN_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: libgfortran'FORTRAN_SO`-armhf [biarchhf_archs] +ifdef(`TARGET',`dnl',`Conflicts: libgfortran'FORTRAN_SO`-armhf [biarchhf_archs]') +BUILT_USING`'dnl Description: Runtime library for GNU Fortran applications (hard float ABI) Library needed for GNU Fortran applications linked against the shared library. Package: libhfgfortran`'FORTRAN_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Priority: extra -Depends: BASEDEP, libhfgfortran`'FORTRAN_SO`'LS (= ${gcc:Version}), ${misc:Depends} -Conflicts: libgfortran'FORTRAN_SO`-dbg-armhf [biarchhf_archs] +Depends: BASEDEP, libdep(gfortran`'FORTRAN_SO,hf,=), ${misc:Depends} +ifdef(`TARGET',`dnl',`Conflicts: libgfortran'FORTRAN_SO`-dbg-armhf [biarchhf_archs]') +BUILT_USING`'dnl Description: Runtime library for GNU Fortran applications (hard float ABI debug symbols) Library needed for GNU Fortran applications linked against the shared library. @@ -1614,20 +2240,22 @@ ifenabled(`libsfgfortran',` Package: libsfgfortran`'FORTRAN_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: libgfortran'FORTRAN_SO`-armel [biarchsf_archs] +ifdef(`TARGET',`dnl',`Conflicts: libgfortran'FORTRAN_SO`-armel [biarchsf_archs]') +BUILT_USING`'dnl Description: Runtime library for GNU Fortran applications (soft float ABI) Library needed for GNU Fortran applications linked against the shared library. Package: libsfgfortran`'FORTRAN_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Priority: extra -Depends: BASEDEP, libsfgfortran`'FORTRAN_SO`'LS (= ${gcc:Version}), ${misc:Depends} -Conflicts: libgfortran'FORTRAN_SO`-dbg-armel [biarchsf_archs] +Depends: BASEDEP, libdep(gfortran`'FORTRAN_SO,sf,=), ${misc:Depends} +ifdef(`TARGET',`dnl',`Conflicts: libgfortran'FORTRAN_SO`-dbg-armel [biarchsf_archs]') +BUILT_USING`'dnl Description: Runtime library for GNU Fortran applications (hard float ABI debug symbols) Library needed for GNU Fortran applications linked against the shared library. @@ -1643,6 +2271,7 @@ ')`'dnl Priority: extra Depends: BASEDEP, libgcc1-neon`'LS, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Fortran applications [NEON version] Library needed for GNU Fortran applications linked against the shared library. @@ -1657,9 +2286,11 @@ Package: gccgo`'PV`'TS Architecture: any Priority: ifdef(`TARGET',`extra',`PRI(optional)') -Depends: BASEDEP, ifdef(`STANDALONEGO',,`gcc`'PV`'TS (= ${gcc:Version}), ')libgo`'GO_SO`'LS (>= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, ifdef(`STANDALONEGO',,`gcc`'PV`'TS (= ${gcc:Version}), ')libdep(go`'GO_SO`',,>=), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends} Provides: go-compiler -Suggests: ${go:multilib}, gccgo`'PV-doc, libgo`'GO_SO-dbg`'LS +Suggests: ${go:multilib}, gccgo`'PV-doc, libdbgdep(go`'GO_SO-dbg,) +Replaces: gcc-4.7-doc (<< 4.7.2-11) +BUILT_USING`'dnl Description: GNU Go compiler This is the GNU Go compiler, which compiles Go on platforms supported by the gcc compiler. It uses the gcc backend to generate optimized code. @@ -1671,6 +2302,7 @@ Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, gccgo`'PV`'TS (= ${gcc:Version}), ifdef(`STANDALONEGO',,`gcc`'PV-multilib`'TS (= ${gcc:Version}), ')${dep:libgobiarch}, ${shlibs:Depends}, ${misc:Depends} Suggests: ${dep:libgobiarchdbg} +BUILT_USING`'dnl Description: GNU Go compiler (multilib files)`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `') This is the GNU Go compiler, which compiles Go on platforms supported by the gcc compiler. @@ -1685,6 +2317,7 @@ Section: doc Priority: PRI(optional) Depends: gcc`'PV-base (>= ${gcc:SoftVersion}), dpkg (>= 1.15.4) | install-info, ${misc:Depends} +BUILT_USING`'dnl Description: Documentation for the GNU Go compiler (gccgo) Documentation for the GNU Go compiler in info `format'. ')`'dnl gfdldoc @@ -1693,102 +2326,133 @@ ifenabled(`libggo',` Package: libgo`'GO_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') ifdef(`TARGET',`dnl',ifdef(`MULTIARCH', `Multi-Arch: same Pre-Depends: multiarch-support ')`Provides: libgo'GO_SO`-armel [armel], libgo'GO_SO`-armhf [armhf]') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Go applications Library needed for GNU Go applications linked against the shared library. Package: libgo`'GO_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') ifdef(`TARGET',`dnl',ifdef(`MULTIARCH', `Multi-Arch: same ')`Provides: libgo'GO_SO`-dbg-armel [armel], libgo'GO_SO`-dbg-armhf [armhf]') Priority: extra -Depends: BASEDEP, libgo`'GO_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(go`'GO_SO,,=), ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Go applications (debug symbols) Library needed for GNU Go applications linked against the shared library. ')`'dnl libgo -ifenabled(`lib64go',` +ifenabled(`lib64ggo',` Package: lib64go`'GO_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Go applications (64bit) Library needed for GNU Go applications linked against the shared library. Package: lib64go`'GO_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Priority: extra -Depends: BASEDEP, lib64go`'GO_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(go`'GO_SO,64,=), ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Go applications (64bit debug symbols) Library needed for GNU Go applications linked against the shared library. ')`'dnl lib64go -ifenabled(`lib32go',` +ifenabled(`lib32ggo',` Package: lib32go`'GO_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Conflicts: ${confl:lib32} +BUILT_USING`'dnl Description: Runtime library for GNU Go applications (32bit) Library needed for GNU Go applications linked against the shared library. Package: lib32go`'GO_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Priority: extra -Depends: BASEDEP, lib32go`'GO_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(go`'GO_SO,32,=), ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Go applications (32 bit debug symbols) Library needed for GNU Go applications linked against the shared library. ')`'dnl lib32go -ifenabled(`libn32go',` +ifenabled(`libn32ggo',` Package: libn32go`'GO_SO`'LS Section: ifdef(`TARGET',`devel',`libs') -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Priority: ifdef(`TARGET',`extra',PRI(optional)) Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Go applications (n32) Library needed for GNU Go applications linked against the shared library. Package: libn32go`'GO_SO-dbg`'LS Section: debug -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Priority: extra -Depends: BASEDEP, libn32go`'GO_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(go`'GO_SO,n32,=), ${misc:Depends} +BUILT_USING`'dnl Description: Runtime library for GNU Go applications (n32 debug symbols) Library needed for GNU Go applications linked against the shared library. ')`'dnl libn32go + +ifenabled(`libx32ggo',` +Package: libx32go`'GO_SO`'LS +Section: ifdef(`TARGET',`devel',`libs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') +Priority: ifdef(`TARGET',`extra',PRI(optional)) +Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl +Description: Runtime library for GNU Go applications (x32) + Library needed for GNU Go applications linked against the + shared library. + +Package: libx32go`'GO_SO-dbg`'LS +Section: debug +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') +Priority: extra +Depends: BASEDEP, libdep(go`'GO_SO,x32,=), ${misc:Depends} +BUILT_USING`'dnl +Description: Runtime library for GNU Go applications (x32 debug symbols) + Library needed for GNU Go applications linked against the + shared library. +')`'dnl libx32go ')`'dnl ggo ifenabled(`java',` ifenabled(`gcj',` -Package: gcj`'PV-jdk +Package: gcj`'PV-jdk`'TS Section: java Architecture: any -Priority: PRI(optional) -Depends: gcj`'PV-base (= ${gcj:Version}), ${dep:gcj}, ${dep:libcdev}, gcj`'PV-jre (= ${gcj:Version}), libgcj`'GCJ_SO-dev (= ${gcj:Version}), gcj`'PV-jre-lib (>= ${gcj:SoftVersion}), ${dep:ecj}, fastjar, libgcj-bc, java-common, libantlr-java, ${shlibs:Depends}, dpkg (>= 1.15.4) | install-info, ${misc:Depends} +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, ${dep:gcj}, ${dep:libcdev}, gcj`'PV-jre`'TS (= ${gcj:Version}), libdevdep(gcj`'GCJ_SO-dev,,=,${gcj:Version}), ${dep:ecj}, fastjar, libgcj-bc`'LS, java-common, libantlr-java, ${shlibs:Depends}, dpkg (>= 1.15.4) | install-info, ${misc:Depends} Recommends: libecj-java-gcj -Suggests: gcj`'PV-source (>= ${gcj:SoftVersion}), libgcj`'GCJ_SO-dbg +Suggests: gcj`'PV-source (>= ${gcj:SoftVersion}), libdbgdep(gcj`'GCJ_SO-dbg,) Provides: java-compiler, java-sdk, java2-sdk, java5-sdk Conflicts: gcj-4.4, cpp-4.1 (<< 4.1.1), gcc-4.1 (<< 4.1.1) Replaces: libgcj11 (<< 4.5-20100101-1) +BUILT_USING`'dnl Description: gcj and classpath development tools for Java(TM) GCJ is a front end to the GCC compiler which can natively compile both Java(tm) source and bytecode files. The compiler can also generate class @@ -1805,21 +2469,24 @@ Section: java Architecture: all Priority: PRI(optional) -Depends: gcj`'PV-base (>= ${gcj:SoftVersion}), ${misc:Depends} +Depends: BASEDEP, ${misc:Depends} Conflicts: classpath (<= 0.04-4) Replaces: java-gcj-compat (<< 1.0.65-3), java-gcj-compat-dev (<< 1.0.65-3) +BUILT_USING`'dnl Description: Java runtime library (common files) This package contains files shared by classpath and libgcj libraries. ')`'dnl libgcjcommon -Package: gcj`'PV-jre-headless -Priority: optional +Package: gcj`'PV-jre-headless`'TS +Priority: ifdef(`TARGET',`extra',`PRI(optional)') Section: java Architecture: any -Depends: gcj`'PV-base (= ${gcj:Version}), libgcj`'LIBGCJ_EXT (= ${gcj:Version}), ${dep:prctl}, ${shlibs:Depends}, ${misc:Depends} -Suggests: fastjar, gcj`'PV-jdk (= ${gcj:Version}), libgcj`'LIBGCJ_EXT-awt (= ${gcj:Version}) +Depends: BASEDEP, gcj`'PV-jre-lib`'TS (>= ${gcj:SoftVersion}), libdep(gcj`'LIBGCJ_EXT,,=,${gcj:Version}), ${dep:prctl}, ${shlibs:Depends}, ${misc:Depends} +Suggests: fastjar, gcj`'PV-jdk`'TS (= ${gcj:Version}), libdep(gcj`'LIBGCJ_EXT-awt,,=,${gcj:Version}) Conflicts: gij-4.4, java-gcj-compat (<< 1.0.76-4) +Replaces: gcj-4.7-jre-lib`'TS (<< 4.7.2-10) Provides: java5-runtime-headless, java2-runtime-headless, java1-runtime-headless, java-runtime-headless +BUILT_USING`'dnl Description: Java runtime environment using GIJ/classpath (headless version) GIJ is a Java bytecode interpreter, not limited to interpreting bytecode. It includes a class loader which can dynamically load shared objects, so @@ -1830,12 +2497,13 @@ It is meant to provide a Java-RTE-like interface to the GIJ/GCJ tool set, limited to the headless tools and libraries. -Package: gcj`'PV-jre +Package: gcj`'PV-jre`'TS Section: java Architecture: any -Priority: PRI(optional) -Depends: gcj`'PV-base (= ${gcj:Version}), gcj`'PV-jre-headless (= ${gcj:Version}), libgcj`'LIBGCJ_EXT-awt (= ${gcj:Version}), ${shlibs:Depends}, ${misc:Depends} +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, gcj`'PV-jre-headless`'TS (= ${gcj:Version}), libdep(gcj`'LIBGCJ_EXT-awt,,=,${gcj:Version}), ${shlibs:Depends}, ${misc:Depends} Provides: java5-runtime, java2-runtime, java1-runtime, java-runtime +BUILT_USING`'dnl Description: Java runtime environment using GIJ/classpath GIJ is a Java bytecode interpreter, not limited to interpreting bytecode. It includes a class loader which can dynamically load shared objects, so @@ -1845,16 +2513,18 @@ The package contains as well a collection of wrapper scripts and symlinks. It is meant to provide a Java-RTE-like interface to the GIJ/GCJ tool set. -Package: libgcj`'LIBGCJ_EXT +Package: libgcj`'LIBGCJ_EXT`'LS Section: libs Architecture: any Priority: PRI(optional) ifdef(`MULTIARCH', `Pre-Depends: multiarch-support +Multi-Arch: same ')`'dnl -Depends: gcj`'PV-base (>= ${gcj:Version}), libgcj-common (>= 1:4.1.1-21), ${shlibs:Depends}, ${misc:Depends} -Recommends: gcj`'PV-jre-lib (>= ${gcj:SoftVersion}) -Suggests: libgcj`'GCJ_SO-dbg, libgcj`'LIBGCJ_EXT-awt (= ${gcj:Version}) +Depends: SOFTBASEDEP, libgcj-common (>= 1:4.1.1-21), ${shlibs:Depends}, ${misc:Depends} +Recommends: gcj`'PV-jre-lib`'TS (>= ${gcj:SoftVersion}) +Suggests: libdbgdep(gcj`'GCJ_SO-dbg,), libdep(gcj`'LIBGCJ_EXT-awt,,=,${gcj:Version}) Replaces: gij-4.4 (<< 4.4.0-1) +BUILT_USING`'dnl Description: Java runtime library for use with gcj This is the runtime that goes along with the gcj front end to gcc. libgcj includes parts of the Java Class Libraries, plus glue to @@ -1863,11 +2533,12 @@ To show file names and line numbers in stack traces, the packages libgcj`'GCJ_SO-dbg and binutils are required. -Package: gcj`'PV-jre-lib +Package: gcj`'PV-jre-lib`'TS Section: java Architecture: all Priority: PRI(optional) -Depends: gcj`'PV-base (>= ${gcj:SoftVersion}), libgcj`'LIBGCJ_EXT (>= ${gcj:SoftVersion}), ${misc:Depends} +Depends: SOFTBASEDEP, libdep(gcj`'LIBGCJ_EXT,,>=,${gcj:SoftVersion}), ${misc:Depends} +BUILT_USING`'dnl Description: Java runtime library for use with gcj (jar files) This is the jar file that goes along with the gcj front end to gcc. @@ -1877,8 +2548,10 @@ Architecture: any Priority: PRI(optional) ifdef(`MULTIARCH', `Pre-Depends: multiarch-support +Multi-Arch: same ')`'dnl -Depends: gcj`'PV-base (>= ${gcj:Version}), libgcj`'LIBGCJ_EXT (>= ${gcj:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(gcj`'LIBGCJ_EXT,,>=,${gcj:Version}), ${misc:Depends} +BUILT_USING`'dnl Description: Link time only library for use with gcj A fake library that is used at link time only. It ensures that binaries built with the BC-ABI link against a constant SONAME. @@ -1886,40 +2559,46 @@ libgcj.so changes. ')`'dnl gcjbc -Package: libgcj`'LIBGCJ_EXT-awt +Package: libgcj`'LIBGCJ_EXT-awt`'LS Section: libs Architecture: any Priority: PRI(optional) ifdef(`MULTIARCH', `Pre-Depends: multiarch-support +Multi-Arch: same ')`'dnl -Depends: gcj`'PV-base (>= ${gcj:Version}), libgcj`'LIBGCJ_EXT (= ${gcj:Version}), ${shlibs:Depends}, ${misc:Depends} +Depends: SOFTBASEDEP, libdep(gcj`'LIBGCJ_EXT,,=,${gcj:Version}), ${shlibs:Depends}, ${misc:Depends} Suggests: ${pkg:gcjqt} +BUILT_USING`'dnl Description: AWT peer runtime libraries for use with gcj These are runtime libraries holding the AWT peer implementations for libgcj (currently the GTK+ based peer library is required, the QT bases library is not built). ifenabled(`gtkpeer',` -Package: libgcj`'GCJ_SO-awt-gtk +Package: libgcj`'GCJ_SO-awt-gtk`'LS Section: libs Architecture: any Priority: PRI(optional) ifdef(`MULTIARCH', `Pre-Depends: multiarch-support +Multi-Arch: same ')`'dnl -Depends: gcj`'PV-base (= ${gcj:Version}), libgcj`'LIBGCJ_EXT-awt (= ${gcj:Version}), ${shlibs:Depends}, ${misc:Depends} +Depends: SOFTBASEDEP, libgcj`'LIBGCJ_EXT-awt`'LS (= ${gcj:Version}), ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: AWT GTK+ peer runtime library for use with libgcj This is the runtime library holding the GTK+ based AWT peer implementation for libgcj. ')`'dnl gtkpeer ifenabled(`qtpeer',` -Package: libgcj`'GCJ_SO-awt-qt +Package: libgcj`'GCJ_SO-awt-qt`'LS Section: libs Architecture: any Priority: PRI(optional) ifdef(`MULTIARCH', `Pre-Depends: multiarch-support +Multi-Arch: same ')`'dnl -Depends: gcj`'PV-base (= ${gcj:Version}), libgcj`'LIBGCJ_EXT-awt (= ${gcj:Version}), ${shlibs:Depends}, ${misc:Depends} +Depends: SOFTBASEDEP, libdep(gcj`'LIBGCJ_EXT-awt,,=,${gcj:Version}), ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: AWT QT peer runtime library for use with libgcj This is the runtime library holding the QT based AWT peer implementation for libgcj. @@ -1927,39 +2606,47 @@ ')`'dnl libgcj ifenabled(`libgcjdev',` -Package: libgcj`'GCJ_SO-dev +Package: libgcj`'GCJ_SO-dev`'LS Section: libdevel Architecture: any +ifdef(`MULTIARCH', `Multi-Arch: same +')`'dnl Priority: PRI(optional) -Depends: gcj`'PV-base (= ${gcj:Version}), gcj`'PV-jdk (= ${gcj:Version}), gcj`'PV-jre-lib (>= ${gcj:SoftVersion}), libgcj`'LIBGCJ_EXT-awt (= ${gcj:Version}), libgcj-bc, ${pkg:gcjgtk}, ${pkg:gcjqt}, zlib1g-dev, ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, gcj`'PV-jdk`'TS (= ${gcj:Version}), gcj`'PV-jre-lib`'TS (>= ${gcj:SoftVersion}), libdep(gcj`'LIBGCJ_EXT-awt,,=,${gcj:Version}), libgcj-bc`'LS, ${pkg:gcjgtk}, ${pkg:gcjqt}, zlib1g-dev, ${shlibs:Depends}, ${misc:Depends} Suggests: libgcj-doc +BUILT_USING`'dnl Description: Java development headers for use with gcj These are the development headers that go along with the gcj front end to gcc. libgcj includes parts of the Java Class Libraries, plus glue to connect the libraries to the compiler and the underlying OS. -Package: libgcj`'GCJ_SO-dbg +Package: libgcj`'GCJ_SO-dbg`'LS Section: debug Architecture: any Priority: extra ifdef(`MULTIARCH', `Pre-Depends: multiarch-support +Multi-Arch: same ')`'dnl -Depends: gcj`'PV-base (= ${gcj:Version}), libgcj`'LIBGCJ_EXT (= ${gcj:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(gcj`'LIBGCJ_EXT,,=,${gcj:Version}), ${misc:Depends} Recommends: binutils, libc6-dbg | libc-dbg +BUILT_USING`'dnl Description: Debugging symbols for libraries provided in libgcj`'GCJ_SO-dev The package provides debugging symbols for the libraries provided in libgcj`'GCJ_SO-dev. . binutils is required to show file names and line numbers in stack traces. +ifenabled(`gcjsrc',` Package: gcj`'PV-source Section: java Architecture: all Priority: PRI(optional) Depends: gcj`'PV-base (>= ${gcj:SoftVersion}), gcj`'PV-jdk (>= ${gcj:SoftVersion}), ${misc:Depends} +BUILT_USING`'dnl Description: GCJ java sources for use in IDEs like eclipse and netbeans These are the java source files packaged as a zip file for use in development environments like eclipse and netbeans. +')`'dnl ifenabled(`gcjdoc',` Package: libgcj-doc @@ -1969,6 +2656,7 @@ Depends: gcj`'PV-base (>= ${gcj:SoftVersion}), ${misc:Depends} Enhances: libgcj`'GCJ_SO-dev Provides: classpath-doc +BUILT_USING`'dnl Description: libgcj API documentation and example programs Autogenerated documentation describing the API of the libgcj library. Sources and precompiled example programs from the classpath library. @@ -1979,7 +2667,7 @@ ifenabled(`c++',` ifenabled(`libcxx',` Package: libstdc++CXX_SO`'LS -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',PRI(important)) Depends: BASEDEP, ${dep:libc}, ${shlibs:Depends}, ${misc:Depends} @@ -1989,6 +2677,7 @@ Breaks: ${multiarch:breaks} ')`Provides: libstdc++'CXX_SO`-armel [armel], libstdc++'CXX_SO`-armhf [armhf]') Conflicts: scim (<< 1.4.2-1) +BUILT_USING`'dnl Description: GNU Standard C++ Library v3`'ifdef(`TARGET)',` (TARGET)', `') This package contains an additional runtime library for C++ programs built with the GNU compiler. @@ -2005,13 +2694,14 @@ ifenabled(`lib32cxx',` Package: lib32stdc++CXX_SO`'LS -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: extra -Depends: BASEDEP, lib32gcc1`'LS, ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, libdep(gcc1,32), ${shlibs:Depends}, ${misc:Depends} Conflicts: ${confl:lib32} ifdef(`TARGET',`Provides: lib32stdc++CXX_SO-TARGET-dcv1 ',`')`'dnl +BUILT_USING`'dnl Description: GNU Standard C++ Library v3 (32 bit Version) This package contains an additional runtime library for C++ programs built with the GNU compiler. @@ -2024,12 +2714,13 @@ ifenabled(`lib64cxx',` Package: lib64stdc++CXX_SO`'LS -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',PRI(optional)) -Depends: BASEDEP, ${shlibs:Depends}, lib64gcc1`'LS, ${misc:Depends} +Depends: BASEDEP, libdep(gcc1,64), ${shlibs:Depends}, ${misc:Depends} ifdef(`TARGET',`Provides: lib64stdc++CXX_SO-TARGET-dcv1 ',`')`'dnl +BUILT_USING`'dnl Description: GNU Standard C++ Library v3`'ifdef(`TARGET)',` (TARGET)', `') (64bit) This package contains an additional runtime library for C++ programs built with the GNU compiler. @@ -2046,12 +2737,13 @@ ifenabled(`libn32cxx',` Package: libn32stdc++CXX_SO`'LS -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',PRI(optional)) -Depends: BASEDEP, ${shlibs:Depends}, libn32gcc1`'LS, ${misc:Depends} +Depends: BASEDEP, libdep(gcc1,n32), ${shlibs:Depends}, ${misc:Depends} ifdef(`TARGET',`Provides: libn32stdc++CXX_SO-TARGET-dcv1 ',`')`'dnl +BUILT_USING`'dnl Description: GNU Standard C++ Library v3`'ifdef(`TARGET)',` (TARGET)', `') (n32) This package contains an additional runtime library for C++ programs built with the GNU compiler. @@ -2066,15 +2758,39 @@ ')`'dnl ')`'dnl libn32cxx +ifenabled(`libx32cxx',` +Package: libx32stdc++CXX_SO`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') +Section: ifdef(`TARGET',`devel',`libs') +Priority: ifdef(`TARGET',`extra',PRI(optional)) +Depends: BASEDEP, libdep(gcc1,x32), ${shlibs:Depends}, ${misc:Depends} +ifdef(`TARGET',`Provides: libx32stdc++CXX_SO-TARGET-dcv1 +',`')`'dnl +BUILT_USING`'dnl +Description: GNU Standard C++ Library v3`'ifdef(`TARGET)',` (TARGET)', `') (x32) + This package contains an additional runtime library for C++ programs + built with the GNU compiler. + . + libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which + was included up to g++-2.95. The first version of libstdc++-v3 appeared + in g++-3.0. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl +')`'dnl libx32cxx + ifenabled(`libhfcxx',` Package: libhfstdc++CXX_SO`'LS -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',PRI(optional)) -Depends: BASEDEP, ${shlibs:Depends}, libhfgcc1`'LS, ${misc:Depends} +Depends: BASEDEP, libdep(gcc1,hf), ${shlibs:Depends}, ${misc:Depends} ifdef(`TARGET',`Provides: libhfstdc++CXX_SO-TARGET-dcv1 ',`')`'dnl -Conflicts: libstdc++'CXX_SO`-armhf [biarchhf_archs] +ifdef(`TARGET',`dnl',`Conflicts: libstdc++'CXX_SO`-armhf [biarchhf_archs]') +BUILT_USING`'dnl Description: GNU Standard C++ Library v3`'ifdef(`TARGET)',` (TARGET)', `') (hard float ABI) This package contains an additional runtime library for C++ programs built with the GNU compiler. @@ -2091,13 +2807,14 @@ ifenabled(`libsfcxx',` Package: libsfstdc++CXX_SO`'LS -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Section: ifdef(`TARGET',`devel',`libs') Priority: ifdef(`TARGET',`extra',PRI(optional)) -Depends: BASEDEP, ${shlibs:Depends}, libsfgcc1`'LS, ${misc:Depends} +Depends: BASEDEP, libdep(gcc1,sf), ${shlibs:Depends}, ${misc:Depends} ifdef(`TARGET',`Provides: libsfstdc++CXX_SO-TARGET-dcv1 ',`')`'dnl -Conflicts: libstdc++'CXX_SO`-armel [biarchsf_archs] +ifdef(`TARGET',`dnl',`Conflicts: libstdc++'CXX_SO`-armel [biarchsf_archs]') +BUILT_USING`'dnl Description: GNU Standard C++ Library v3`'ifdef(`TARGET)',` (TARGET)', `') (soft float ABI) This package contains an additional runtime library for C++ programs built with the GNU compiler. @@ -2118,6 +2835,7 @@ Section: libs Priority: extra Depends: BASEDEP, libc6-neon`'LS, libgcc1-neon`'LS, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: GNU Standard C++ Library v3 [NEON version] This package contains an additional runtime library for C++ programs built with the GNU compiler. @@ -2128,15 +2846,19 @@ ifenabled(`c++dev',` Package: libstdc++CXX_SO`'PV-dev`'LS -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') +ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same +'))`'dnl Section: ifdef(`TARGET',`devel',`libdevel') Priority: ifdef(`TARGET',`extra',PRI(optional)) -Depends: BASEDEP, g++`'PV`'TS (= ${gcc:Version}), libstdc++CXX_SO`'LS (>= ${gcc:Version}), ${dep:libcdev}, ${misc:Depends} +Depends: BASEDEP, libdevdep(gcc`'PV-dev,,=), libdep(stdc++CXX_SO,,>=), ${dep:libcdev}, ${misc:Depends} ifdef(`TARGET',`',`dnl native Conflicts: libg++27-dev, libg++272-dev (<< 2.7.2.8-1), libstdc++2.8-dev, libg++2.8-dev, libstdc++2.9-dev, libstdc++2.9-glibc2.1-dev, libstdc++2.10-dev (<< 1:2.95.3-2), libstdc++3.0-dev +Replaces: g++`'PV (<< ${gcc:SplitVersion}) Suggests: libstdc++CXX_SO`'PV-doc ')`'dnl native Provides: libstdc++-dev`'LS`'ifdef(`TARGET',`, libstdc++-dev-TARGET-dcv1, libstdc++CXX_SO-dev-TARGET-dcv1') +BUILT_USING`'dnl Description: GNU Standard C++ Library v3 (development files)`'ifdef(`TARGET)',` (TARGET)', `') This package contains the headers and static library files necessary for building C++ programs which use libstdc++. @@ -2151,12 +2873,15 @@ ')`'dnl Package: libstdc++CXX_SO`'PV-pic`'LS -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') +ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same +'))`'dnl Section: ifdef(`TARGET',`devel',`libdevel') Priority: extra -Depends: BASEDEP, libstdc++CXX_SO`'LS (>= ${gcc:Version}), libstdc++CXX_SO`'PV-dev`'LS (= ${gcc:Version}), ${misc:Depends} +Depends: BASEDEP, libdep(stdc++CXX_SO,,>=), libdevdep(stdc++CXX_SO`'PV-dev,,=), ${misc:Depends} ifdef(`TARGET',`Provides: libstdc++CXX_SO-pic-TARGET-dcv1 ',`')`'dnl +BUILT_USING`'dnl Description: GNU Standard C++ Library v3 (shared library subset kit)`'ifdef(`TARGET)',` (TARGET)', `') This is used to develop subsets of the libstdc++ shared libraries for use on custom installation floppies and in embedded systems. @@ -2169,16 +2894,17 @@ ')`'dnl Package: libstdc++CXX_SO`'PV-dbg`'LS -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') Section: debug Priority: extra -Depends: BASEDEP, libstdc++CXX_SO`'LS (>= ${gcc:Version}), libgcc`'GCC_SO-dbg`'LS, ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, libdep(stdc++CXX_SO,,>=), libdbgdep(gcc`'GCC_SO-dbg,,>=,${gcc:EpochVersion}), ${shlibs:Depends}, ${misc:Depends} ifdef(`TARGET',`Provides: libstdc++CXX_SO-dbg-TARGET-dcv1',`dnl ifdef(`MULTIARCH', `Multi-Arch: same',`dnl') Provides: libstdc++'CXX_SO`'PV`-dbg-armel [armel], libstdc++'CXX_SO`'PV`-dbg-armhf [armhf]dnl ') -Recommends: libstdc++CXX_SO`'PV-dev`'LS (= ${gcc:Version}) +Recommends: libdevdep(stdc++CXX_SO`'PV-dev,,=) Conflicts: libstdc++5-dbg`'LS, libstdc++5-3.3-dbg`'LS, libstdc++6-dbg`'LS, libstdc++6-4.0-dbg`'LS, libstdc++6-4.1-dbg`'LS, libstdc++6-4.2-dbg`'LS, libstdc++6-4.3-dbg`'LS, libstdc++6-4.4-dbg`'LS, libstdc++6-4.5-dbg`'LS, libstdc++6-4.6-dbg`'LS +BUILT_USING`'dnl Description: GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `') This package contains the shared library of libstdc++ compiled with debugging symbols. @@ -2188,14 +2914,38 @@ environment. ')`'dnl +Package: lib32stdc++CXX_SO`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') +Section: ifdef(`TARGET',`devel',`libdevel') +Priority: ifdef(`TARGET',`extra',PRI(optional)) +Depends: BASEDEP, libdevdep(gcc`'PV-dev,32,=), libdep(stdc++CXX_SO,32,>=), libdevdep(stdc++CXX_SO`'PV-dev,,=), ${misc:Depends} +ifdef(`TARGET',`',`dnl native +Replaces: libstdc++CXX_SO`'PV-dev (<< ${gcc:SplitVersion}), g++`'PV-multilib (<< ${gcc:SplitVersion}) +Breaks: libstdc++CXX_SO`'PV-dev (<< ${gcc:SplitVersion}), g++`'PV-multilib (<< ${gcc:SplitVersion}) +')`'dnl native +BUILT_USING`'dnl +Description: GNU Standard C++ Library v3 (development files)`'ifdef(`TARGET',` (TARGET)', `') + This package contains the headers and static library files necessary for + building C++ programs which use libstdc++. + . + libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which + was included up to g++-2.95. The first version of libstdc++-v3 appeared + in g++-3.0. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl + Package: lib32stdc++CXX_SO`'PV-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') Section: debug Priority: extra -Depends: BASEDEP, lib32stdc++CXX_SO`'LS (>= ${gcc:Version}), libstdc++CXX_SO`'PV-dev`'LS (= ${gcc:Version}), lib32gcc`'GCC_SO-dbg`'LS, ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, libdep(stdc++CXX_SO,32,>=), libdevdep(stdc++CXX_SO`'PV-dev,,=), libdbgdep(gcc`'GCC_SO-dbg,32,>=,${gcc:EpochVersion}), ${shlibs:Depends}, ${misc:Depends} ifdef(`TARGET',`Provides: lib32stdc++CXX_SO-dbg-TARGET-dcv1 ',`')`'dnl Conflicts: lib32stdc++6-dbg`'LS, lib32stdc++6-4.0-dbg`'LS, lib32stdc++6-4.1-dbg`'LS, lib32stdc++6-4.2-dbg`'LS, lib32stdc++6-4.3-dbg`'LS, lib32stdc++6-4.4-dbg`'LS, lib32stdc++6-4.5-dbg`'LS, lib32stdc++6-4.6-dbg`'LS +BUILT_USING`'dnl Description: GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `') This package contains the shared library of libstdc++ compiled with debugging symbols. @@ -2205,14 +2955,38 @@ environment. ')`'dnl +Package: lib64stdc++CXX_SO`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') +Section: ifdef(`TARGET',`devel',`libdevel') +Priority: ifdef(`TARGET',`extra',PRI(optional)) +Depends: BASEDEP, libdevdep(gcc`'PV-dev,64,=), libdep(stdc++CXX_SO,64,>=), libdevdep(stdc++CXX_SO`'PV-dev,,=), ${misc:Depends} +ifdef(`TARGET',`',`dnl native +Replaces: libstdc++CXX_SO`'PV-dev (<< ${gcc:SplitVersion}), g++`'PV-multilib (<< ${gcc:SplitVersion}) +Breaks: libstdc++CXX_SO`'PV-dev (<< ${gcc:SplitVersion}), g++`'PV-multilib (<< ${gcc:SplitVersion}) +')`'dnl native +BUILT_USING`'dnl +Description: GNU Standard C++ Library v3 (development files)`'ifdef(`TARGET',` (TARGET)', `') + This package contains the headers and static library files necessary for + building C++ programs which use libstdc++. + . + libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which + was included up to g++-2.95. The first version of libstdc++-v3 appeared + in g++-3.0. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl + Package: lib64stdc++CXX_SO`'PV-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') Section: debug Priority: extra -Depends: BASEDEP, lib64stdc++CXX_SO`'LS (>= ${gcc:Version}), libstdc++CXX_SO`'PV-dev`'LS (= ${gcc:Version}), lib64gcc`'GCC_SO-dbg`'LS, ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, libdep(stdc++CXX_SO,64,>=), libdevdep(stdc++CXX_SO`'PV-dev,,=), libdbgdep(gcc`'GCC_SO-dbg,64,>=,${gcc:EpochVersion}), ${shlibs:Depends}, ${misc:Depends} ifdef(`TARGET',`Provides: lib64stdc++CXX_SO-dbg-TARGET-dcv1 ',`')`'dnl Conflicts: lib64stdc++6-dbg`'LS, lib64stdc++6-4.0-dbg`'LS, lib64stdc++6-4.1-dbg`'LS, lib64stdc++6-4.2-dbg`'LS, lib64stdc++6-4.3-dbg`'LS, lib64stdc++6-4.4-dbg`'LS, lib64stdc++6-4.5-dbg`'LS, lib64stdc++6-4.6-dbg`'LS +BUILT_USING`'dnl Description: GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `') This package contains the shared library of libstdc++ compiled with debugging symbols. @@ -2222,14 +2996,38 @@ environment. ')`'dnl +Package: libn32stdc++CXX_SO`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') +Section: ifdef(`TARGET',`devel',`libdevel') +Priority: ifdef(`TARGET',`extra',PRI(optional)) +Depends: BASEDEP, libdevdep(gcc`'PV-dev,n32,=), libdep(stdc++CXX_SO,n32,>=), libdevdep(stdc++CXX_SO`'PV-dev,,=), ${misc:Depends} +ifdef(`TARGET',`',`dnl native +Replaces: libstdc++CXX_SO`'PV-dev (<< ${gcc:SplitVersion}), g++`'PV-multilib (<< ${gcc:SplitVersion}) +Breaks: libstdc++CXX_SO`'PV-dev (<< ${gcc:SplitVersion}), g++`'PV-multilib (<< ${gcc:SplitVersion}) +')`'dnl native +BUILT_USING`'dnl +Description: GNU Standard C++ Library v3 (development files)`'ifdef(`TARGET',` (TARGET)', `') + This package contains the headers and static library files necessary for + building C++ programs which use libstdc++. + . + libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which + was included up to g++-2.95. The first version of libstdc++-v3 appeared + in g++-3.0. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl + Package: libn32stdc++CXX_SO`'PV-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') Section: debug Priority: extra -Depends: BASEDEP, libn32stdc++CXX_SO`'LS (>= ${gcc:Version}), libstdc++CXX_SO`'PV-dev`'LS (= ${gcc:Version}), libn32gcc`'GCC_SO-dbg`'LS, ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, libdep(stdc++CXX_SO,n32,>=), libdevdep(stdc++CXX_SO`'PV-dev,,=), libdbgdep(gcc`'GCC_SO-dbg,n32,>=,${gcc:EpochVersion}), ${shlibs:Depends}, ${misc:Depends} ifdef(`TARGET',`Provides: libn32stdc++CXX_SO-dbg-TARGET-dcv1 ',`')`'dnl Conflicts: libn32stdc++6-dbg`'LS, libn32stdc++6-4.0-dbg`'LS, libn32stdc++6-4.1-dbg`'LS, libn32stdc++6-4.2-dbg`'LS, libn32stdc++6-4.3-dbg`'LS, libn32stdc++6-4.4-dbg`'LS, libn32stdc++6-4.5-dbg`'LS, libn32stdc++6-4.6-dbg`'LS +BUILT_USING`'dnl Description: GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `') This package contains the shared library of libstdc++ compiled with debugging symbols. @@ -2239,15 +3037,82 @@ environment. ')`'dnl +ifenabled(`libx32dbgcxx',` +Package: libx32stdc++CXX_SO`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') +Section: ifdef(`TARGET',`devel',`libdevel') +Priority: ifdef(`TARGET',`extra',PRI(optional)) +Depends: BASEDEP, libdevdep(gcc`'PV-dev,x32,=), libdep(stdc++CXX_SO,x32,>=), libdevdep(stdc++CXX_SO`'PV-dev,,=), ${misc:Depends} +ifdef(`TARGET',`',`dnl native +Replaces: libstdc++CXX_SO`'PV-dev (<< ${gcc:SplitVersion}), g++`'PV-multilib (<< ${gcc:SplitVersion}) +Breaks: libstdc++CXX_SO`'PV-dev (<< ${gcc:SplitVersion}), g++`'PV-multilib (<< ${gcc:SplitVersion}) +')`'dnl native +BUILT_USING`'dnl +Description: GNU Standard C++ Library v3 (development files)`'ifdef(`TARGET',` (TARGET)', `') + This package contains the headers and static library files necessary for + building C++ programs which use libstdc++. + . + libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which + was included up to g++-2.95. The first version of libstdc++-v3 appeared + in g++-3.0. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl + +Package: libx32stdc++CXX_SO`'PV-dbg`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') +Section: debug +Priority: extra +Depends: BASEDEP, libdep(stdc++CXX_SO,x32,>=), libdevdep(stdc++CXX_SO`'PV-dev,,=), libdbgdep(gcc`'GCC_SO-dbg,x32,>=,${gcc:EpochVersion}), ${shlibs:Depends}, ${misc:Depends} +ifdef(`TARGET',`Provides: libx32stdc++CXX_SO-dbg-TARGET-dcv1 +',`')`'dnl +Conflicts: libx32stdc++6-dbg`'LS, libx32stdc++6-4.0-dbg`'LS, libx32stdc++6-4.1-dbg`'LS, libx32stdc++6-4.2-dbg`'LS, libx32stdc++6-4.3-dbg`'LS, libx32stdc++6-4.4-dbg`'LS, libx32stdc++6-4.5-dbg`'LS, libx32stdc++6-4.6-dbg`'LS +BUILT_USING`'dnl +Description: GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `') + This package contains the shared library of libstdc++ compiled with + debugging symbols. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl +')`'dnl libx32dbgcxx + ifenabled(`libhfdbgcxx',` +Package: libhfstdc++CXX_SO`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') +Section: ifdef(`TARGET',`devel',`libdevel') +Priority: ifdef(`TARGET',`extra',PRI(optional)) +Depends: BASEDEP, libdevdep(gcc`'PV-dev,hf,=), libdep(stdc++CXX_SO,,>=), libdevdep(stdc++CXX_SO`'PV-dev,,=), ${misc:Depends} +ifdef(`TARGET',`',`dnl native +Replaces: libstdc++CXX_SO`'PV-dev (<< ${gcc:SplitVersion}), g++`'PV-multilib (<< ${gcc:SplitVersion}) +Breaks: libstdc++CXX_SO`'PV-dev (<< ${gcc:SplitVersion}), g++`'PV-multilib (<< ${gcc:SplitVersion}) +')`'dnl native +BUILT_USING`'dnl +Description: GNU Standard C++ Library v3 (development files)`'ifdef(`TARGET',` (TARGET)', `') + This package contains the headers and static library files necessary for + building C++ programs which use libstdc++. + . + libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which + was included up to g++-2.95. The first version of libstdc++-v3 appeared + in g++-3.0. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl + Package: libhfstdc++CXX_SO`'PV-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchhf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') Section: debug Priority: extra -Depends: BASEDEP, libhfstdc++CXX_SO`'LS (>= ${gcc:Version}), libstdc++CXX_SO`'PV-dev`'LS (= ${gcc:Version}), libhfgcc`'GCC_SO-dbg`'LS, ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, libdep(stdc++CXX_SO,hf,>=), libdevdep(stdc++CXX_SO`'PV-dev,,=), libdbgdep(gcc`'GCC_SO-dbg,hf,>=,${gcc:EpochVersion}), ${shlibs:Depends}, ${misc:Depends} ifdef(`TARGET',`Provides: libhfstdc++CXX_SO-dbg-TARGET-dcv1 ',`')`'dnl -Conflicts: libhfstdc++6-dbg`'LS, libhfstdc++6-4.3-dbg`'LS, libhfstdc++6-4.4-dbg`'LS, libhfstdc++6-4.5-dbg`'LS, libhfstdc++6-4.6-dbg`'LS, libstdc++'CXX_SO`-armhf [biarchhf_archs] +ifdef(`TARGET',`dnl',`Conflicts: libhfstdc++6-dbg`'LS, libhfstdc++6-4.3-dbg`'LS, libhfstdc++6-4.4-dbg`'LS, libhfstdc++6-4.5-dbg`'LS, libhfstdc++6-4.6-dbg`'LS, libstdc++'CXX_SO`-armhf [biarchhf_archs]') +BUILT_USING`'dnl Description: GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `') This package contains the shared library of libstdc++ compiled with debugging symbols. @@ -2259,14 +3124,38 @@ ')`'dnl libhfdbgcxx ifenabled(`libsfdbgcxx',` +Package: libsfstdc++CXX_SO`'PV-dev`'LS +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') +Section: ifdef(`TARGET',`devel',`libdevel') +Priority: ifdef(`TARGET',`extra',PRI(optional)) +Depends: BASEDEP, libdevdep(gcc`'PV-dev,sf,=), libdep(stdc++CXX_SO,sf,>=), libdevdep(stdc++CXX_SO`'PV-dev,,=), ${misc:Depends} +ifdef(`TARGET',`',`dnl native +Replaces: libstdc++CXX_SO`'PV-dev (<< ${gcc:SplitVersion}), g++`'PV-multilib (<< ${gcc:SplitVersion}) +Breaks: libstdc++CXX_SO`'PV-dev (<< ${gcc:SplitVersion}), g++`'PV-multilib (<< ${gcc:SplitVersion}) +')`'dnl native +BUILT_USING`'dnl +Description: GNU Standard C++ Library v3 (development files)`'ifdef(`TARGET',` (TARGET)', `') + This package contains the headers and static library files necessary for + building C++ programs which use libstdc++. + . + libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which + was included up to g++-2.95. The first version of libstdc++-v3 appeared + in g++-3.0. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl + Package: libsfstdc++CXX_SO`'PV-dbg`'LS -Architecture: ifdef(`TARGET',`all',`biarchsf_archs') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') Section: debug Priority: extra -Depends: BASEDEP, libsfstdc++CXX_SO`'LS (>= ${gcc:Version}), libstdc++CXX_SO`'PV-dev`'LS (= ${gcc:Version}), libsfgcc`'GCC_SO-dbg`'LS, ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, libdep(stdc++CXX_SO,sf,>=), libdevdep(stdc++CXX_SO`'PV-dev,,=), libdbgdep(gcc`'GCC_SO-dbg,sf,>=,${gcc:EpochVersion}), ${shlibs:Depends}, ${misc:Depends} ifdef(`TARGET',`Provides: libsfstdc++CXX_SO-dbg-TARGET-dcv1 ',`')`'dnl -Conflicts: libsfstdc++6-dbg`'LS, libsfstdc++6-4.3-dbg`'LS, libsfstdc++6-4.4-dbg`'LS, libsfstdc++6-4.5-dbg`'LS, libsfstdc++6-4.6-dbg`'LS, libstdc++'CXX_SO`-armel [biarchsf_archs] +ifdef(`TARGET',`dnl',`Conflicts: libsfstdc++6-dbg`'LS, libsfstdc++6-4.3-dbg`'LS, libsfstdc++6-4.4-dbg`'LS, libsfstdc++6-4.5-dbg`'LS, libsfstdc++6-4.6-dbg`'LS, libstdc++'CXX_SO`-armel [biarchsf_archs]') +BUILT_USING`'dnl Description: GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `') This package contains the shared library of libstdc++ compiled with debugging symbols. @@ -2305,6 +3194,7 @@ Suggests: gnat`'PV-doc, ada-reference-manual-html, ada-reference-manual-info, ada-reference-manual-pdf, ada-reference-manual-text, gnat`'-GNAT_V-sjlj Provides: ada-compiler Conflicts: gnat (<< 4.1), gnat-3.1, gnat-3.2, gnat-3.3, gnat-3.4, gnat-3.5, gnat-4.0, gnat-4.1, gnat-4.2, gnat-4.3, gnat-4.4, gnat-4.6 +BUILT_USING`'dnl Description: GNU Ada compiler GNAT is a compiler for the Ada programming language. It produces optimized code on platforms supported by the GNU Compiler Collection (GCC). @@ -2318,6 +3208,7 @@ ifdef(`MULTIARCH', `Pre-Depends: multiarch-support ')`'dnl Depends: gnat`'PV-base (= ${gnat:Version}), gnat`'-GNAT_V (= ${gnat:Version}), ${misc:Depends} +BUILT_USING`'dnl Description: GNU Ada compiler (setjump/longjump runtime library) GNAT is a compiler for the Ada programming language. It produces optimized code on platforms supported by the GNU Compiler Collection (GCC). @@ -2335,6 +3226,7 @@ '))`'dnl Priority: PRI(optional) Depends: gnat`'PV-base (= ${gnat:Version}), ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: runtime for applications compiled with GNAT (shared library) GNAT is a compiler for the Ada programming language. It produces optimized code on platforms supported by the GNU Compiler Collection (GCC). @@ -2352,6 +3244,7 @@ '))`'dnl Priority: extra Depends: gnat`'PV-base (= ${gnat:Version}), libgnat`'-GNAT_V (= ${gnat:Version}), ${misc:Depends} +BUILT_USING`'dnl Description: runtime for applications compiled with GNAT (debugging symbols) GNAT is a compiler for the Ada programming language. It produces optimized code on platforms supported by the GNU Compiler Collection (GCC). @@ -2368,6 +3261,7 @@ Depends: gnat`'PV-base (= ${gnat:Version}), gnat`'PV (= ${gnat:Version}), ada-compiler, libgnatvsn`'GNAT_V (= ${gnat:Version}), ${misc:Depends} Conflicts: libgnatvsn-dev (<< `'GNAT_V), libgnatvsn4.1-dev, libgnatvsn4.3-dev, libgnatvsn4.4-dev, libgnatvsn4.5-dev, libgnatvsn4.6-dev +BUILT_USING`'dnl Description: GNU Ada compiler selected components (development files) GNAT is a compiler for the Ada programming language. It produces optimized code on platforms supported by the GNU Compiler Collection (GCC). @@ -2386,6 +3280,7 @@ Priority: PRI(optional) Section: libs Depends: gnat`'PV-base (= ${gnat:Version}), libgnat`'-GNAT_V (= ${gnat:Version}), ${misc:Depends} +BUILT_USING`'dnl Description: GNU Ada compiler selected components (shared library) GNAT is a compiler for the Ada programming language. It produces optimized code on platforms supported by the GNU Compiler Collection (GCC). @@ -2405,6 +3300,7 @@ Section: debug Depends: gnat`'PV-base (= ${gnat:Version}), libgnatvsn`'GNAT_V (= ${gnat:Version}), ${misc:Depends} Suggests: gnat, ada-compiler +BUILT_USING`'dnl Description: GNU Ada compiler selected components (debugging symbols) GNAT is a compiler for the Ada programming language. It produces optimized code on platforms supported by the GNU Compiler Collection (GCC). @@ -2422,6 +3318,7 @@ Depends: gnat`'PV-base (= ${gnat:Version}), gnat`'PV (= ${gnat:Version}), ada-compiler, libgnatprj`'GNAT_V (= ${gnat:Version}), libgnatvsn`'GNAT_V-dev (= ${gnat:Version}), ${misc:Depends} Conflicts: libgnatprj-dev (<< `'GNAT_V), libgnatprj4.1-dev, libgnatprj4.3-dev, libgnatprj4.4-dev, libgnatprj4.5-dev, libgnatprj4.6-dev +BUILT_USING`'dnl Description: GNU Ada compiler Project Manager (development files) GNAT is a compiler for the Ada programming language. It produces optimized code on platforms supported by the GNU Compiler Collection (GCC). @@ -2443,6 +3340,7 @@ Priority: PRI(optional) Section: libs Depends: gnat`'PV-base (= ${gnat:Version}), libgnat`'-GNAT_V (= ${gnat:Version}), libgnatvsn`'GNAT_V (= ${gnat:Version}), ${misc:Depends} +BUILT_USING`'dnl Description: GNU Ada compiler Project Manager (shared library) GNAT is a compiler for the Ada programming language. It produces optimized code on platforms supported by the GNU Compiler Collection (GCC). @@ -2465,6 +3363,7 @@ Section: debug Depends: gnat`'PV-base (= ${gnat:Version}), libgnatprj`'GNAT_V (= ${gnat:Version}), ${misc:Depends} Suggests: gnat, ada-compiler +BUILT_USING`'dnl Description: GNU Ada compiler Project Manager (debugging symbols) GNAT is a compiler for the Ada programming language. It produces optimized code on platforms supported by the GNU Compiler Collection (GCC). @@ -2485,6 +3384,7 @@ Architecture: biarch64_archs Priority: PRI(optional) Depends: gnat`'PV-base (= ${gnat:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: runtime for applications compiled with GNAT (64 bits shared library) GNAT is a compiler for the Ada programming language. It produces optimized code on platforms supported by the GNU Compiler Collection (GCC). @@ -2503,6 +3403,7 @@ Depends: dpkg (>= 1.15.4) | install-info, ${misc:Depends} Suggests: gnat`'PV Conflicts: gnat-4.1-doc, gnat-4.2-doc, gnat-4.3-doc, gnat-4.4-doc, gnat-4.6-doc +BUILT_USING`'dnl Description: GNU Ada compiler (documentation) GNAT is a compiler for the Ada programming language. It produces optimized code on platforms supported by the GNU Compiler Collection (GCC). @@ -2521,6 +3422,7 @@ Depends: SOFTBASEDEP, g++`'PV (>= ${gcc:SoftVersion}), libphobos`'PHOBOS_V`'PV-dev (= ${gdc:Version}) [libphobos_no_archs], ${shlibs:Depends}, ${misc:Depends} Provides: gdc, d-compiler, d-v2-compiler Replaces: gdc (<< 4.4.6-5) +BUILT_USING`'dnl Description: GNU D compiler (version 2), based on the GCC backend This is the GNU D compiler, which compiles D on platforms supported by gcc. It uses the gcc backend to generate optimised code. @@ -2534,6 +3436,7 @@ Priority: PRI(optional) Depends: gdc`'PV`'TS (= ${gdc:Version}), zlib1g-dev, ${shlibs:Depends}, ${misc:Depends} Provides: libphobos`'PHOBOS_V`'TS-dev +BUILT_USING`'dnl Description: Phobos D standard library This is the Phobos standard library that comes with the D2 compiler. . @@ -2541,10 +3444,11 @@ Package: libphobos`'PHOBOS_V`'PV`'TS-dbg Section: debug -Architecture: ifdef(`TARGET',`all',`any') +Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') Priority: extra Depends: gdc`'PV`'TS (= ${gdc:Version}), libphobos`'PHOBOS_V`'PV-dev (= ${gdc:Version}), ${misc:Depends} Provides: libphobos`'PHOBOS_V`'TS-dbg +BUILT_USING`'dnl Description: The Phobos D standard library (debug symbols) This is the Phobos standard library that comes with the D2 compiler. . @@ -2559,6 +3463,7 @@ Priority: PRI(optional) Depends: BASEDEP, ifenabled(`cdev',`gcc`'PV (= ${gcc:Version}),') ${shlibs:Depends}, ${misc:Depends} Conflicts: gcc-4.4-soft-float, gcc-4.5-soft-float, gcc-4.6-soft-float +BUILT_USING`'dnl Description: GCC soft-floating-point gcc libraries (ARM) These are versions of basic static libraries such as libgcc.a compiled with the -msoft-float option, for CPUs without a floating-point unit. @@ -2570,6 +3475,7 @@ Architecture: any Priority: PRI(optional) Depends: BASEDEP, gcc`'PV (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +BUILT_USING`'dnl Description: Fix non-ANSI header files FixIncludes was created to fix non-ANSI system header files. Many system manufacturers supply proprietary headers that are not ANSI compliant. @@ -2604,6 +3510,7 @@ Priority: PRI(optional) Depends: BASEDEP, ${shlibs:Depends}ifenabled(`cdev',`, gcc`'PV (= ${gcc:Version})'), ${misc:Depends} Conflicts: gcc-3.2-nof +BUILT_USING`'dnl Description: GCC no-floating-point gcc libraries (powerpc) These are versions of basic static libraries such as libgcc.a compiled with the -msoft-float option, for CPUs without a floating-point unit. diff -Nru gcc-4.7-4.7.2/debian/gcc-BV-doc.doc-base.itm gcc-4.7-4.7.3/debian/gcc-BV-doc.doc-base.itm --- gcc-4.7-4.7.2/debian/gcc-BV-doc.doc-base.itm 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/gcc-BV-doc.doc-base.itm 2013-07-25 18:49:34.000000000 +0000 @@ -0,0 +1,16 @@ +Document: gcc-@BV@-itm +Title: The GNU Transactional Memory Library (for GCC @BV@) +Author: Various +Abstract: This manual documents the usage and internals of libitm, + the GNU Transactional Memory Library. It provides transaction support + for accesses to a process' memory, enabling easy-to-use synchronization + of accesses to shared memory by several threads. +Section: Programming + +Format: html +Index: /usr/share/doc/gcc-@BV@-base/libitm.html +Files: /usr/share/doc/gcc-@BV@-base/libitm.html + +Format: info +Index: /usr/share/info/libitm-@BV@.info.gz +Files: /usr/share/info/libitm-@BV@* diff -Nru gcc-4.7-4.7.2/debian/gcc-BV-doc.doc-base.qmath gcc-4.7-4.7.3/debian/gcc-BV-doc.doc-base.qmath --- gcc-4.7-4.7.2/debian/gcc-BV-doc.doc-base.qmath 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/gcc-BV-doc.doc-base.qmath 2013-07-25 18:49:34.000000000 +0000 @@ -0,0 +1,14 @@ +Document: gcc-@BV@-qmath +Title: The GCC Quad-Precision Math Library (for GCC @BV@) +Author: Various +Abstract: This manual documents the usage of libquadmath, the GCC + Quad-Precision Math Library Application Programming Interface (API). +Section: Programming + +Format: html +Index: /usr/share/doc/gcc-@BV@-base/libquadmath.html +Files: /usr/share/doc/gcc-@BV@-base/libquadmath.html + +Format: info +Index: /usr/share/info/libquadmath-@BV@.info.gz +Files: /usr/share/info/libquadmath-@BV@* diff -Nru gcc-4.7-4.7.2/debian/gccgo-BV-doc.doc-base gcc-4.7-4.7.3/debian/gccgo-BV-doc.doc-base --- gcc-4.7-4.7.2/debian/gccgo-BV-doc.doc-base 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/gccgo-BV-doc.doc-base 2013-07-25 18:49:34.000000000 +0000 @@ -0,0 +1,17 @@ +Document: gccgo-@BV@ +Title: The GNU Go compiler (version @BV@) +Author: Various +Abstract: This manual describes how to use gccgo, the GNU compiler for + the Go programming language. This manual is specifically about + gccgo. For more information about the Go programming + language in general, including language specifications and standard + package documentation, see http://golang.org/. +Section: Programming + +Format: html +Index: /usr/share/doc/gcc-@BV@-base/gccgo.html +Files: /usr/share/doc/gcc-@BV@-base/gccgo.html + +Format: info +Index: /usr/share/info/gccgo-@BV@.info.gz +Files: /usr/share/info/gccgo-@BV@* diff -Nru gcc-4.7-4.7.2/debian/gcj-BV-jre-headless.overrides gcc-4.7-4.7.3/debian/gcj-BV-jre-headless.overrides --- gcc-4.7-4.7.2/debian/gcj-BV-jre-headless.overrides 2013-07-25 18:49:32.000000000 +0000 +++ gcc-4.7-4.7.3/debian/gcj-BV-jre-headless.overrides 2013-07-25 18:49:34.000000000 +0000 @@ -1,2 +1,5 @@ # pick up the exact version, in case another gcj version is installed gcj-@BV@-jre-headless binary: binary-or-shlib-defines-rpath + +# don't strip the binaries, keep the libgcj13-dbg package Multi-Arch: same +gcj-@BV@-jre-headless binary: unstripped-binary-or-object diff -Nru gcc-4.7-4.7.2/debian/lib64stdc++6.symbols.sparc gcc-4.7-4.7.3/debian/lib64stdc++6.symbols.sparc --- gcc-4.7-4.7.2/debian/lib64stdc++6.symbols.sparc 2013-07-25 18:49:32.000000000 +0000 +++ gcc-4.7-4.7.3/debian/lib64stdc++6.symbols.sparc 2013-07-25 18:49:34.000000000 +0000 @@ -1,5 +1,6 @@ libstdc++.so.6 lib64stdc++6 #MINVER# #include "libstdc++6.symbols.64bit" +#include "libstdc++6.symbols.128bit" #include "libstdc++6.symbols.excprop" _ZN9__gnu_cxx12__atomic_addEPVli@GLIBCXX_3.4 4.1.1 _ZN9__gnu_cxx18__exchange_and_addEPVli@GLIBCXX_3.4 4.1.1 diff -Nru gcc-4.7-4.7.2/debian/libgcc1.symbols.aeabi gcc-4.7-4.7.3/debian/libgcc1.symbols.aeabi --- gcc-4.7-4.7.2/debian/libgcc1.symbols.aeabi 2013-07-25 18:49:32.000000000 +0000 +++ gcc-4.7-4.7.3/debian/libgcc1.symbols.aeabi 2013-07-25 18:49:34.000000000 +0000 @@ -61,6 +61,8 @@ __aeabi_ulcmp@GCC_3.5 1:4.4.0 __aeabi_uldivmod@GCC_3.5 1:4.4.0 __aeabi_unwind_cpp_pr0@GCC_3.5 1:4.4.0 + __aeabi_unwind_cpp_pr1@GCC_3.5 1:4.4.0 + __aeabi_unwind_cpp_pr2@GCC_3.5 1:4.4.0 __aeabi_uread4@GCC_3.5 1:4.4.0 __aeabi_uread8@GCC_3.5 1:4.4.0 __aeabi_uwrite4@GCC_3.5 1:4.4.0 diff -Nru gcc-4.7-4.7.2/debian/libgcc1.symbols.armel gcc-4.7-4.7.3/debian/libgcc1.symbols.armel --- gcc-4.7-4.7.2/debian/libgcc1.symbols.armel 2013-07-25 18:49:32.000000000 +0000 +++ gcc-4.7-4.7.3/debian/libgcc1.symbols.armel 2013-07-25 18:49:34.000000000 +0000 @@ -78,7 +78,987 @@ __gcc_personality_v0@GCC_3.3.1 1:4.3.0 __gedf2@GCC_3.0 1:4.3.0 __gesf2@GCC_3.0 1:4.3.0 + __gnu_addda3@GCC_4.3.0 1:4.3.0 + __gnu_adddq3@GCC_4.3.0 1:4.3.0 + __gnu_addha3@GCC_4.3.0 1:4.3.0 + __gnu_addhq3@GCC_4.3.0 1:4.3.0 + __gnu_addqq3@GCC_4.3.0 1:4.3.0 + __gnu_addsa3@GCC_4.3.0 1:4.3.0 + __gnu_addsq3@GCC_4.3.0 1:4.3.0 + __gnu_adduda3@GCC_4.3.0 1:4.3.0 + __gnu_addudq3@GCC_4.3.0 1:4.3.0 + __gnu_adduha3@GCC_4.3.0 1:4.3.0 + __gnu_adduhq3@GCC_4.3.0 1:4.3.0 + __gnu_adduqq3@GCC_4.3.0 1:4.3.0 + __gnu_addusa3@GCC_4.3.0 1:4.3.0 + __gnu_addusq3@GCC_4.3.0 1:4.3.0 + __gnu_ashlda3@GCC_4.3.0 1:4.3.0 + __gnu_ashldq3@GCC_4.3.0 1:4.3.0 + __gnu_ashlha3@GCC_4.3.0 1:4.3.0 + __gnu_ashlhq3@GCC_4.3.0 1:4.3.0 + __gnu_ashlqq3@GCC_4.3.0 1:4.3.0 + __gnu_ashlsa3@GCC_4.3.0 1:4.3.0 + __gnu_ashlsq3@GCC_4.3.0 1:4.3.0 + __gnu_ashluda3@GCC_4.3.0 1:4.3.0 + __gnu_ashludq3@GCC_4.3.0 1:4.3.0 + __gnu_ashluha3@GCC_4.3.0 1:4.3.0 + __gnu_ashluhq3@GCC_4.3.0 1:4.3.0 + __gnu_ashluqq3@GCC_4.3.0 1:4.3.0 + __gnu_ashlusa3@GCC_4.3.0 1:4.3.0 + __gnu_ashlusq3@GCC_4.3.0 1:4.3.0 + __gnu_ashrda3@GCC_4.3.0 1:4.3.0 + __gnu_ashrdq3@GCC_4.3.0 1:4.3.0 + __gnu_ashrha3@GCC_4.3.0 1:4.3.0 + __gnu_ashrhq3@GCC_4.3.0 1:4.3.0 + __gnu_ashrqq3@GCC_4.3.0 1:4.3.0 + __gnu_ashrsa3@GCC_4.3.0 1:4.3.0 + __gnu_ashrsq3@GCC_4.3.0 1:4.3.0 + __gnu_cmpda2@GCC_4.3.0 1:4.3.0 + __gnu_cmpdq2@GCC_4.3.0 1:4.3.0 + __gnu_cmpha2@GCC_4.3.0 1:4.3.0 + __gnu_cmphq2@GCC_4.3.0 1:4.3.0 + __gnu_cmpqq2@GCC_4.3.0 1:4.3.0 + __gnu_cmpsa2@GCC_4.3.0 1:4.3.0 + __gnu_cmpsq2@GCC_4.3.0 1:4.3.0 + __gnu_cmpuda2@GCC_4.3.0 1:4.3.0 + __gnu_cmpudq2@GCC_4.3.0 1:4.3.0 + __gnu_cmpuha2@GCC_4.3.0 1:4.3.0 + __gnu_cmpuhq2@GCC_4.3.0 1:4.3.0 + __gnu_cmpuqq2@GCC_4.3.0 1:4.3.0 + __gnu_cmpusa2@GCC_4.3.0 1:4.3.0 + __gnu_cmpusq2@GCC_4.3.0 1:4.3.0 + __gnu_divda3@GCC_4.3.0 1:4.3.0 + __gnu_divdq3@GCC_4.3.0 1:4.3.0 + __gnu_divha3@GCC_4.3.0 1:4.3.0 + __gnu_divhq3@GCC_4.3.0 1:4.3.0 + __gnu_divqq3@GCC_4.3.0 1:4.3.0 + __gnu_divsa3@GCC_4.3.0 1:4.3.0 + __gnu_divsq3@GCC_4.3.0 1:4.3.0 + __gnu_fractdadf@GCC_4.3.0 1:4.3.0 + __gnu_fractdadi@GCC_4.3.0 1:4.3.0 + __gnu_fractdadq@GCC_4.3.0 1:4.3.0 + __gnu_fractdaha2@GCC_4.3.0 1:4.3.0 + __gnu_fractdahi@GCC_4.3.0 1:4.3.0 + __gnu_fractdahq@GCC_4.3.0 1:4.3.0 + __gnu_fractdaqi@GCC_4.3.0 1:4.3.0 + __gnu_fractdaqq@GCC_4.3.0 1:4.3.0 + __gnu_fractdasa2@GCC_4.3.0 1:4.3.0 + __gnu_fractdasf@GCC_4.3.0 1:4.3.0 + __gnu_fractdasi@GCC_4.3.0 1:4.3.0 + __gnu_fractdasq@GCC_4.3.0 1:4.3.0 + __gnu_fractdauda@GCC_4.3.0 1:4.3.0 + __gnu_fractdaudq@GCC_4.3.0 1:4.3.0 + __gnu_fractdauha@GCC_4.3.0 1:4.3.0 + __gnu_fractdauhq@GCC_4.3.0 1:4.3.0 + __gnu_fractdauqq@GCC_4.3.0 1:4.3.0 + __gnu_fractdausa@GCC_4.3.0 1:4.3.0 + __gnu_fractdausq@GCC_4.3.0 1:4.3.0 + __gnu_fractdfda@GCC_4.3.0 1:4.3.0 + __gnu_fractdfdq@GCC_4.3.0 1:4.3.0 + __gnu_fractdfha@GCC_4.3.0 1:4.3.0 + __gnu_fractdfhq@GCC_4.3.0 1:4.3.0 + __gnu_fractdfqq@GCC_4.3.0 1:4.3.0 + __gnu_fractdfsa@GCC_4.3.0 1:4.3.0 + __gnu_fractdfsq@GCC_4.3.0 1:4.3.0 + __gnu_fractdfuda@GCC_4.3.0 1:4.3.0 + __gnu_fractdfudq@GCC_4.3.0 1:4.3.0 + __gnu_fractdfuha@GCC_4.3.0 1:4.3.0 + __gnu_fractdfuhq@GCC_4.3.0 1:4.3.0 + __gnu_fractdfuqq@GCC_4.3.0 1:4.3.0 + __gnu_fractdfusa@GCC_4.3.0 1:4.3.0 + __gnu_fractdfusq@GCC_4.3.0 1:4.3.0 + __gnu_fractdida@GCC_4.3.0 1:4.3.0 + __gnu_fractdidq@GCC_4.3.0 1:4.3.0 + __gnu_fractdiha@GCC_4.3.0 1:4.3.0 + __gnu_fractdihq@GCC_4.3.0 1:4.3.0 + __gnu_fractdiqq@GCC_4.3.0 1:4.3.0 + __gnu_fractdisa@GCC_4.3.0 1:4.3.0 + __gnu_fractdisq@GCC_4.3.0 1:4.3.0 + __gnu_fractdiuda@GCC_4.3.0 1:4.3.0 + __gnu_fractdiudq@GCC_4.3.0 1:4.3.0 + __gnu_fractdiuha@GCC_4.3.0 1:4.3.0 + __gnu_fractdiuhq@GCC_4.3.0 1:4.3.0 + __gnu_fractdiuqq@GCC_4.3.0 1:4.3.0 + __gnu_fractdiusa@GCC_4.3.0 1:4.3.0 + __gnu_fractdiusq@GCC_4.3.0 1:4.3.0 + __gnu_fractdqda@GCC_4.3.0 1:4.3.0 + __gnu_fractdqdf@GCC_4.3.0 1:4.3.0 + __gnu_fractdqdi@GCC_4.3.0 1:4.3.0 + __gnu_fractdqha@GCC_4.3.0 1:4.3.0 + __gnu_fractdqhi@GCC_4.3.0 1:4.3.0 + __gnu_fractdqhq2@GCC_4.3.0 1:4.3.0 + __gnu_fractdqqi@GCC_4.3.0 1:4.3.0 + __gnu_fractdqqq2@GCC_4.3.0 1:4.3.0 + __gnu_fractdqsa@GCC_4.3.0 1:4.3.0 + __gnu_fractdqsf@GCC_4.3.0 1:4.3.0 + __gnu_fractdqsi@GCC_4.3.0 1:4.3.0 + __gnu_fractdqsq2@GCC_4.3.0 1:4.3.0 + __gnu_fractdquda@GCC_4.3.0 1:4.3.0 + __gnu_fractdqudq@GCC_4.3.0 1:4.3.0 + __gnu_fractdquha@GCC_4.3.0 1:4.3.0 + __gnu_fractdquhq@GCC_4.3.0 1:4.3.0 + __gnu_fractdquqq@GCC_4.3.0 1:4.3.0 + __gnu_fractdqusa@GCC_4.3.0 1:4.3.0 + __gnu_fractdqusq@GCC_4.3.0 1:4.3.0 + __gnu_fracthada2@GCC_4.3.0 1:4.3.0 + __gnu_fracthadf@GCC_4.3.0 1:4.3.0 + __gnu_fracthadi@GCC_4.3.0 1:4.3.0 + __gnu_fracthadq@GCC_4.3.0 1:4.3.0 + __gnu_fracthahi@GCC_4.3.0 1:4.3.0 + __gnu_fracthahq@GCC_4.3.0 1:4.3.0 + __gnu_fracthaqi@GCC_4.3.0 1:4.3.0 + __gnu_fracthaqq@GCC_4.3.0 1:4.3.0 + __gnu_fracthasa2@GCC_4.3.0 1:4.3.0 + __gnu_fracthasf@GCC_4.3.0 1:4.3.0 + __gnu_fracthasi@GCC_4.3.0 1:4.3.0 + __gnu_fracthasq@GCC_4.3.0 1:4.3.0 + __gnu_fracthauda@GCC_4.3.0 1:4.3.0 + __gnu_fracthaudq@GCC_4.3.0 1:4.3.0 + __gnu_fracthauha@GCC_4.3.0 1:4.3.0 + __gnu_fracthauhq@GCC_4.3.0 1:4.3.0 + __gnu_fracthauqq@GCC_4.3.0 1:4.3.0 + __gnu_fracthausa@GCC_4.3.0 1:4.3.0 + __gnu_fracthausq@GCC_4.3.0 1:4.3.0 + __gnu_fracthida@GCC_4.3.0 1:4.3.0 + __gnu_fracthidq@GCC_4.3.0 1:4.3.0 + __gnu_fracthiha@GCC_4.3.0 1:4.3.0 + __gnu_fracthihq@GCC_4.3.0 1:4.3.0 + __gnu_fracthiqq@GCC_4.3.0 1:4.3.0 + __gnu_fracthisa@GCC_4.3.0 1:4.3.0 + __gnu_fracthisq@GCC_4.3.0 1:4.3.0 + __gnu_fracthiuda@GCC_4.3.0 1:4.3.0 + __gnu_fracthiudq@GCC_4.3.0 1:4.3.0 + __gnu_fracthiuha@GCC_4.3.0 1:4.3.0 + __gnu_fracthiuhq@GCC_4.3.0 1:4.3.0 + __gnu_fracthiuqq@GCC_4.3.0 1:4.3.0 + __gnu_fracthiusa@GCC_4.3.0 1:4.3.0 + __gnu_fracthiusq@GCC_4.3.0 1:4.3.0 + __gnu_fracthqda@GCC_4.3.0 1:4.3.0 + __gnu_fracthqdf@GCC_4.3.0 1:4.3.0 + __gnu_fracthqdi@GCC_4.3.0 1:4.3.0 + __gnu_fracthqdq2@GCC_4.3.0 1:4.3.0 + __gnu_fracthqha@GCC_4.3.0 1:4.3.0 + __gnu_fracthqhi@GCC_4.3.0 1:4.3.0 + __gnu_fracthqqi@GCC_4.3.0 1:4.3.0 + __gnu_fracthqqq2@GCC_4.3.0 1:4.3.0 + __gnu_fracthqsa@GCC_4.3.0 1:4.3.0 + __gnu_fracthqsf@GCC_4.3.0 1:4.3.0 + __gnu_fracthqsi@GCC_4.3.0 1:4.3.0 + __gnu_fracthqsq2@GCC_4.3.0 1:4.3.0 + __gnu_fracthquda@GCC_4.3.0 1:4.3.0 + __gnu_fracthqudq@GCC_4.3.0 1:4.3.0 + __gnu_fracthquha@GCC_4.3.0 1:4.3.0 + __gnu_fracthquhq@GCC_4.3.0 1:4.3.0 + __gnu_fracthquqq@GCC_4.3.0 1:4.3.0 + __gnu_fracthqusa@GCC_4.3.0 1:4.3.0 + __gnu_fracthqusq@GCC_4.3.0 1:4.3.0 + __gnu_fractqida@GCC_4.3.0 1:4.3.0 + __gnu_fractqidq@GCC_4.3.0 1:4.3.0 + __gnu_fractqiha@GCC_4.3.0 1:4.3.0 + __gnu_fractqihq@GCC_4.3.0 1:4.3.0 + __gnu_fractqiqq@GCC_4.3.0 1:4.3.0 + __gnu_fractqisa@GCC_4.3.0 1:4.3.0 + __gnu_fractqisq@GCC_4.3.0 1:4.3.0 + __gnu_fractqiuda@GCC_4.3.0 1:4.3.0 + __gnu_fractqiudq@GCC_4.3.0 1:4.3.0 + __gnu_fractqiuha@GCC_4.3.0 1:4.3.0 + __gnu_fractqiuhq@GCC_4.3.0 1:4.3.0 + __gnu_fractqiuqq@GCC_4.3.0 1:4.3.0 + __gnu_fractqiusa@GCC_4.3.0 1:4.3.0 + __gnu_fractqiusq@GCC_4.3.0 1:4.3.0 + __gnu_fractqqda@GCC_4.3.0 1:4.3.0 + __gnu_fractqqdf@GCC_4.3.0 1:4.3.0 + __gnu_fractqqdi@GCC_4.3.0 1:4.3.0 + __gnu_fractqqdq2@GCC_4.3.0 1:4.3.0 + __gnu_fractqqha@GCC_4.3.0 1:4.3.0 + __gnu_fractqqhi@GCC_4.3.0 1:4.3.0 + __gnu_fractqqhq2@GCC_4.3.0 1:4.3.0 + __gnu_fractqqqi@GCC_4.3.0 1:4.3.0 + __gnu_fractqqsa@GCC_4.3.0 1:4.3.0 + __gnu_fractqqsf@GCC_4.3.0 1:4.3.0 + __gnu_fractqqsi@GCC_4.3.0 1:4.3.0 + __gnu_fractqqsq2@GCC_4.3.0 1:4.3.0 + __gnu_fractqquda@GCC_4.3.0 1:4.3.0 + __gnu_fractqqudq@GCC_4.3.0 1:4.3.0 + __gnu_fractqquha@GCC_4.3.0 1:4.3.0 + __gnu_fractqquhq@GCC_4.3.0 1:4.3.0 + __gnu_fractqquqq@GCC_4.3.0 1:4.3.0 + __gnu_fractqqusa@GCC_4.3.0 1:4.3.0 + __gnu_fractqqusq@GCC_4.3.0 1:4.3.0 + __gnu_fractsada2@GCC_4.3.0 1:4.3.0 + __gnu_fractsadf@GCC_4.3.0 1:4.3.0 + __gnu_fractsadi@GCC_4.3.0 1:4.3.0 + __gnu_fractsadq@GCC_4.3.0 1:4.3.0 + __gnu_fractsaha2@GCC_4.3.0 1:4.3.0 + __gnu_fractsahi@GCC_4.3.0 1:4.3.0 + __gnu_fractsahq@GCC_4.3.0 1:4.3.0 + __gnu_fractsaqi@GCC_4.3.0 1:4.3.0 + __gnu_fractsaqq@GCC_4.3.0 1:4.3.0 + __gnu_fractsasf@GCC_4.3.0 1:4.3.0 + __gnu_fractsasi@GCC_4.3.0 1:4.3.0 + __gnu_fractsasq@GCC_4.3.0 1:4.3.0 + __gnu_fractsauda@GCC_4.3.0 1:4.3.0 + __gnu_fractsaudq@GCC_4.3.0 1:4.3.0 + __gnu_fractsauha@GCC_4.3.0 1:4.3.0 + __gnu_fractsauhq@GCC_4.3.0 1:4.3.0 + __gnu_fractsauqq@GCC_4.3.0 1:4.3.0 + __gnu_fractsausa@GCC_4.3.0 1:4.3.0 + __gnu_fractsausq@GCC_4.3.0 1:4.3.0 + __gnu_fractsfda@GCC_4.3.0 1:4.3.0 + __gnu_fractsfdq@GCC_4.3.0 1:4.3.0 + __gnu_fractsfha@GCC_4.3.0 1:4.3.0 + __gnu_fractsfhq@GCC_4.3.0 1:4.3.0 + __gnu_fractsfqq@GCC_4.3.0 1:4.3.0 + __gnu_fractsfsa@GCC_4.3.0 1:4.3.0 + __gnu_fractsfsq@GCC_4.3.0 1:4.3.0 + __gnu_fractsfuda@GCC_4.3.0 1:4.3.0 + __gnu_fractsfudq@GCC_4.3.0 1:4.3.0 + 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__gnu_satfractqiha@GCC_4.3.0 1:4.3.0 + __gnu_satfractqihq@GCC_4.3.0 1:4.3.0 + __gnu_satfractqiqq@GCC_4.3.0 1:4.3.0 + __gnu_satfractqisa@GCC_4.3.0 1:4.3.0 + __gnu_satfractqisq@GCC_4.3.0 1:4.3.0 + __gnu_satfractqiuda@GCC_4.3.0 1:4.3.0 + __gnu_satfractqiudq@GCC_4.3.0 1:4.3.0 + __gnu_satfractqiuha@GCC_4.3.0 1:4.3.0 + __gnu_satfractqiuhq@GCC_4.3.0 1:4.3.0 + __gnu_satfractqiuqq@GCC_4.3.0 1:4.3.0 + __gnu_satfractqiusa@GCC_4.3.0 1:4.3.0 + __gnu_satfractqiusq@GCC_4.3.0 1:4.3.0 + __gnu_satfractqqda@GCC_4.3.0 1:4.3.0 + __gnu_satfractqqdq2@GCC_4.3.0 1:4.3.0 + __gnu_satfractqqha@GCC_4.3.0 1:4.3.0 + __gnu_satfractqqhq2@GCC_4.3.0 1:4.3.0 + __gnu_satfractqqsa@GCC_4.3.0 1:4.3.0 + __gnu_satfractqqsq2@GCC_4.3.0 1:4.3.0 + __gnu_satfractqquda@GCC_4.3.0 1:4.3.0 + __gnu_satfractqqudq@GCC_4.3.0 1:4.3.0 + __gnu_satfractqquha@GCC_4.3.0 1:4.3.0 + __gnu_satfractqquhq@GCC_4.3.0 1:4.3.0 + __gnu_satfractqquqq@GCC_4.3.0 1:4.3.0 + __gnu_satfractqqusa@GCC_4.3.0 1:4.3.0 + __gnu_satfractqqusq@GCC_4.3.0 1:4.3.0 + __gnu_satfractsada2@GCC_4.3.0 1:4.3.0 + __gnu_satfractsadq@GCC_4.3.0 1:4.3.0 + __gnu_satfractsaha2@GCC_4.3.0 1:4.3.0 + __gnu_satfractsahq@GCC_4.3.0 1:4.3.0 + __gnu_satfractsaqq@GCC_4.3.0 1:4.3.0 + __gnu_satfractsasq@GCC_4.3.0 1:4.3.0 + __gnu_satfractsauda@GCC_4.3.0 1:4.3.0 + __gnu_satfractsaudq@GCC_4.3.0 1:4.3.0 + __gnu_satfractsauha@GCC_4.3.0 1:4.3.0 + __gnu_satfractsauhq@GCC_4.3.0 1:4.3.0 + __gnu_satfractsauqq@GCC_4.3.0 1:4.3.0 + __gnu_satfractsausa@GCC_4.3.0 1:4.3.0 + __gnu_satfractsausq@GCC_4.3.0 1:4.3.0 + __gnu_satfractsfda@GCC_4.3.0 1:4.3.0 + __gnu_satfractsfdq@GCC_4.3.0 1:4.3.0 + __gnu_satfractsfha@GCC_4.3.0 1:4.3.0 + __gnu_satfractsfhq@GCC_4.3.0 1:4.3.0 + __gnu_satfractsfqq@GCC_4.3.0 1:4.3.0 + __gnu_satfractsfsa@GCC_4.3.0 1:4.3.0 + __gnu_satfractsfsq@GCC_4.3.0 1:4.3.0 + __gnu_satfractsfuda@GCC_4.3.0 1:4.3.0 + __gnu_satfractsfudq@GCC_4.3.0 1:4.3.0 + __gnu_satfractsfuha@GCC_4.3.0 1:4.3.0 + __gnu_satfractsfuhq@GCC_4.3.0 1:4.3.0 + __gnu_satfractsfuqq@GCC_4.3.0 1:4.3.0 + __gnu_satfractsfusa@GCC_4.3.0 1:4.3.0 + __gnu_satfractsfusq@GCC_4.3.0 1:4.3.0 + __gnu_satfractsida@GCC_4.3.0 1:4.3.0 + __gnu_satfractsidq@GCC_4.3.0 1:4.3.0 + __gnu_satfractsiha@GCC_4.3.0 1:4.3.0 + __gnu_satfractsihq@GCC_4.3.0 1:4.3.0 + __gnu_satfractsiqq@GCC_4.3.0 1:4.3.0 + __gnu_satfractsisa@GCC_4.3.0 1:4.3.0 + __gnu_satfractsisq@GCC_4.3.0 1:4.3.0 + __gnu_satfractsiuda@GCC_4.3.0 1:4.3.0 + __gnu_satfractsiudq@GCC_4.3.0 1:4.3.0 + __gnu_satfractsiuha@GCC_4.3.0 1:4.3.0 + __gnu_satfractsiuhq@GCC_4.3.0 1:4.3.0 + __gnu_satfractsiuqq@GCC_4.3.0 1:4.3.0 + __gnu_satfractsiusa@GCC_4.3.0 1:4.3.0 + __gnu_satfractsiusq@GCC_4.3.0 1:4.3.0 + __gnu_satfractsqda@GCC_4.3.0 1:4.3.0 + __gnu_satfractsqdq2@GCC_4.3.0 1:4.3.0 + __gnu_satfractsqha@GCC_4.3.0 1:4.3.0 + __gnu_satfractsqhq2@GCC_4.3.0 1:4.3.0 + __gnu_satfractsqqq2@GCC_4.3.0 1:4.3.0 + __gnu_satfractsqsa@GCC_4.3.0 1:4.3.0 + __gnu_satfractsquda@GCC_4.3.0 1:4.3.0 + __gnu_satfractsqudq@GCC_4.3.0 1:4.3.0 + __gnu_satfractsquha@GCC_4.3.0 1:4.3.0 + __gnu_satfractsquhq@GCC_4.3.0 1:4.3.0 + __gnu_satfractsquqq@GCC_4.3.0 1:4.3.0 + __gnu_satfractsqusa@GCC_4.3.0 1:4.3.0 + __gnu_satfractsqusq@GCC_4.3.0 1:4.3.0 + __gnu_satfractudada@GCC_4.3.0 1:4.3.0 + __gnu_satfractudadq@GCC_4.3.0 1:4.3.0 + __gnu_satfractudaha@GCC_4.3.0 1:4.3.0 + __gnu_satfractudahq@GCC_4.3.0 1:4.3.0 + __gnu_satfractudaqq@GCC_4.3.0 1:4.3.0 + __gnu_satfractudasa@GCC_4.3.0 1:4.3.0 + __gnu_satfractudasq@GCC_4.3.0 1:4.3.0 + __gnu_satfractudaudq@GCC_4.3.0 1:4.3.0 + __gnu_satfractudauha2@GCC_4.3.0 1:4.3.0 + __gnu_satfractudauhq@GCC_4.3.0 1:4.3.0 + __gnu_satfractudauqq@GCC_4.3.0 1:4.3.0 + __gnu_satfractudausa2@GCC_4.3.0 1:4.3.0 + __gnu_satfractudausq@GCC_4.3.0 1:4.3.0 + __gnu_satfractudqda@GCC_4.3.0 1:4.3.0 + __gnu_satfractudqdq@GCC_4.3.0 1:4.3.0 + __gnu_satfractudqha@GCC_4.3.0 1:4.3.0 + __gnu_satfractudqhq@GCC_4.3.0 1:4.3.0 + __gnu_satfractudqqq@GCC_4.3.0 1:4.3.0 + __gnu_satfractudqsa@GCC_4.3.0 1:4.3.0 + __gnu_satfractudqsq@GCC_4.3.0 1:4.3.0 + __gnu_satfractudquda@GCC_4.3.0 1:4.3.0 + __gnu_satfractudquha@GCC_4.3.0 1:4.3.0 + __gnu_satfractudquhq2@GCC_4.3.0 1:4.3.0 + __gnu_satfractudquqq2@GCC_4.3.0 1:4.3.0 + __gnu_satfractudqusa@GCC_4.3.0 1:4.3.0 + __gnu_satfractudqusq2@GCC_4.3.0 1:4.3.0 + __gnu_satfractuhada@GCC_4.3.0 1:4.3.0 + __gnu_satfractuhadq@GCC_4.3.0 1:4.3.0 + __gnu_satfractuhaha@GCC_4.3.0 1:4.3.0 + __gnu_satfractuhahq@GCC_4.3.0 1:4.3.0 + __gnu_satfractuhaqq@GCC_4.3.0 1:4.3.0 + __gnu_satfractuhasa@GCC_4.3.0 1:4.3.0 + __gnu_satfractuhasq@GCC_4.3.0 1:4.3.0 + __gnu_satfractuhauda2@GCC_4.3.0 1:4.3.0 + __gnu_satfractuhaudq@GCC_4.3.0 1:4.3.0 + __gnu_satfractuhauhq@GCC_4.3.0 1:4.3.0 + __gnu_satfractuhauqq@GCC_4.3.0 1:4.3.0 + __gnu_satfractuhausa2@GCC_4.3.0 1:4.3.0 + __gnu_satfractuhausq@GCC_4.3.0 1:4.3.0 + __gnu_satfractuhqda@GCC_4.3.0 1:4.3.0 + __gnu_satfractuhqdq@GCC_4.3.0 1:4.3.0 + __gnu_satfractuhqha@GCC_4.3.0 1:4.3.0 + __gnu_satfractuhqhq@GCC_4.3.0 1:4.3.0 + __gnu_satfractuhqqq@GCC_4.3.0 1:4.3.0 + __gnu_satfractuhqsa@GCC_4.3.0 1:4.3.0 + __gnu_satfractuhqsq@GCC_4.3.0 1:4.3.0 + __gnu_satfractuhquda@GCC_4.3.0 1:4.3.0 + __gnu_satfractuhqudq2@GCC_4.3.0 1:4.3.0 + __gnu_satfractuhquha@GCC_4.3.0 1:4.3.0 + __gnu_satfractuhquqq2@GCC_4.3.0 1:4.3.0 + __gnu_satfractuhqusa@GCC_4.3.0 1:4.3.0 + __gnu_satfractuhqusq2@GCC_4.3.0 1:4.3.0 + __gnu_satfractunsdida@GCC_4.3.0 1:4.3.0 + __gnu_satfractunsdidq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunsdiha@GCC_4.3.0 1:4.3.0 + __gnu_satfractunsdihq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunsdiqq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunsdisa@GCC_4.3.0 1:4.3.0 + __gnu_satfractunsdisq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunsdiuda@GCC_4.3.0 1:4.3.0 + __gnu_satfractunsdiudq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunsdiuha@GCC_4.3.0 1:4.3.0 + __gnu_satfractunsdiuhq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunsdiuqq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunsdiusa@GCC_4.3.0 1:4.3.0 + __gnu_satfractunsdiusq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunshida@GCC_4.3.0 1:4.3.0 + __gnu_satfractunshidq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunshiha@GCC_4.3.0 1:4.3.0 + __gnu_satfractunshihq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunshiqq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunshisa@GCC_4.3.0 1:4.3.0 + __gnu_satfractunshisq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunshiuda@GCC_4.3.0 1:4.3.0 + __gnu_satfractunshiudq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunshiuha@GCC_4.3.0 1:4.3.0 + __gnu_satfractunshiuhq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunshiuqq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunshiusa@GCC_4.3.0 1:4.3.0 + __gnu_satfractunshiusq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunsqida@GCC_4.3.0 1:4.3.0 + __gnu_satfractunsqidq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunsqiha@GCC_4.3.0 1:4.3.0 + __gnu_satfractunsqihq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunsqiqq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunsqisa@GCC_4.3.0 1:4.3.0 + __gnu_satfractunsqisq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunsqiuda@GCC_4.3.0 1:4.3.0 + __gnu_satfractunsqiudq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunsqiuha@GCC_4.3.0 1:4.3.0 + __gnu_satfractunsqiuhq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunsqiuqq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunsqiusa@GCC_4.3.0 1:4.3.0 + __gnu_satfractunsqiusq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunssida@GCC_4.3.0 1:4.3.0 + __gnu_satfractunssidq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunssiha@GCC_4.3.0 1:4.3.0 + __gnu_satfractunssihq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunssiqq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunssisa@GCC_4.3.0 1:4.3.0 + __gnu_satfractunssisq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunssiuda@GCC_4.3.0 1:4.3.0 + __gnu_satfractunssiudq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunssiuha@GCC_4.3.0 1:4.3.0 + __gnu_satfractunssiuhq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunssiuqq@GCC_4.3.0 1:4.3.0 + __gnu_satfractunssiusa@GCC_4.3.0 1:4.3.0 + __gnu_satfractunssiusq@GCC_4.3.0 1:4.3.0 + __gnu_satfractuqqda@GCC_4.3.0 1:4.3.0 + __gnu_satfractuqqdq@GCC_4.3.0 1:4.3.0 + __gnu_satfractuqqha@GCC_4.3.0 1:4.3.0 + __gnu_satfractuqqhq@GCC_4.3.0 1:4.3.0 + __gnu_satfractuqqqq@GCC_4.3.0 1:4.3.0 + __gnu_satfractuqqsa@GCC_4.3.0 1:4.3.0 + __gnu_satfractuqqsq@GCC_4.3.0 1:4.3.0 + __gnu_satfractuqquda@GCC_4.3.0 1:4.3.0 + __gnu_satfractuqqudq2@GCC_4.3.0 1:4.3.0 + __gnu_satfractuqquha@GCC_4.3.0 1:4.3.0 + __gnu_satfractuqquhq2@GCC_4.3.0 1:4.3.0 + __gnu_satfractuqqusa@GCC_4.3.0 1:4.3.0 + __gnu_satfractuqqusq2@GCC_4.3.0 1:4.3.0 + __gnu_satfractusada@GCC_4.3.0 1:4.3.0 + __gnu_satfractusadq@GCC_4.3.0 1:4.3.0 + __gnu_satfractusaha@GCC_4.3.0 1:4.3.0 + __gnu_satfractusahq@GCC_4.3.0 1:4.3.0 + __gnu_satfractusaqq@GCC_4.3.0 1:4.3.0 + __gnu_satfractusasa@GCC_4.3.0 1:4.3.0 + __gnu_satfractusasq@GCC_4.3.0 1:4.3.0 + __gnu_satfractusauda2@GCC_4.3.0 1:4.3.0 + __gnu_satfractusaudq@GCC_4.3.0 1:4.3.0 + __gnu_satfractusauha2@GCC_4.3.0 1:4.3.0 + __gnu_satfractusauhq@GCC_4.3.0 1:4.3.0 + __gnu_satfractusauqq@GCC_4.3.0 1:4.3.0 + __gnu_satfractusausq@GCC_4.3.0 1:4.3.0 + __gnu_satfractusqda@GCC_4.3.0 1:4.3.0 + __gnu_satfractusqdq@GCC_4.3.0 1:4.3.0 + __gnu_satfractusqha@GCC_4.3.0 1:4.3.0 + __gnu_satfractusqhq@GCC_4.3.0 1:4.3.0 + __gnu_satfractusqqq@GCC_4.3.0 1:4.3.0 + __gnu_satfractusqsa@GCC_4.3.0 1:4.3.0 + __gnu_satfractusqsq@GCC_4.3.0 1:4.3.0 + __gnu_satfractusquda@GCC_4.3.0 1:4.3.0 + __gnu_satfractusqudq2@GCC_4.3.0 1:4.3.0 + __gnu_satfractusquha@GCC_4.3.0 1:4.3.0 + __gnu_satfractusquhq2@GCC_4.3.0 1:4.3.0 + __gnu_satfractusquqq2@GCC_4.3.0 1:4.3.0 + __gnu_satfractusqusa@GCC_4.3.0 1:4.3.0 + __gnu_ssaddda3@GCC_4.3.0 1:4.3.0 + __gnu_ssadddq3@GCC_4.3.0 1:4.3.0 + __gnu_ssaddha3@GCC_4.3.0 1:4.3.0 + __gnu_ssaddhq3@GCC_4.3.0 1:4.3.0 + __gnu_ssaddqq3@GCC_4.3.0 1:4.3.0 + __gnu_ssaddsa3@GCC_4.3.0 1:4.3.0 + __gnu_ssaddsq3@GCC_4.3.0 1:4.3.0 + __gnu_ssashlda3@GCC_4.3.0 1:4.3.0 + __gnu_ssashldq3@GCC_4.3.0 1:4.3.0 + __gnu_ssashlha3@GCC_4.3.0 1:4.3.0 + __gnu_ssashlhq3@GCC_4.3.0 1:4.3.0 + __gnu_ssashlqq3@GCC_4.3.0 1:4.3.0 + __gnu_ssashlsa3@GCC_4.3.0 1:4.3.0 + __gnu_ssashlsq3@GCC_4.3.0 1:4.3.0 + __gnu_ssdivda3@GCC_4.3.0 1:4.3.0 + __gnu_ssdivdq3@GCC_4.3.0 1:4.3.0 + __gnu_ssdivha3@GCC_4.3.0 1:4.3.0 + __gnu_ssdivhq3@GCC_4.3.0 1:4.3.0 + __gnu_ssdivqq3@GCC_4.3.0 1:4.3.0 + __gnu_ssdivsa3@GCC_4.3.0 1:4.3.0 + __gnu_ssdivsq3@GCC_4.3.0 1:4.3.0 + __gnu_ssmulda3@GCC_4.3.0 1:4.3.0 + __gnu_ssmuldq3@GCC_4.3.0 1:4.3.0 + __gnu_ssmulha3@GCC_4.3.0 1:4.3.0 + __gnu_ssmulhq3@GCC_4.3.0 1:4.3.0 + __gnu_ssmulqq3@GCC_4.3.0 1:4.3.0 + __gnu_ssmulsa3@GCC_4.3.0 1:4.3.0 + __gnu_ssmulsq3@GCC_4.3.0 1:4.3.0 + __gnu_ssnegda2@GCC_4.3.0 1:4.3.0 + __gnu_ssnegdq2@GCC_4.3.0 1:4.3.0 + __gnu_ssnegha2@GCC_4.3.0 1:4.3.0 + __gnu_ssneghq2@GCC_4.3.0 1:4.3.0 + __gnu_ssnegqq2@GCC_4.3.0 1:4.3.0 + __gnu_ssnegsa2@GCC_4.3.0 1:4.3.0 + __gnu_ssnegsq2@GCC_4.3.0 1:4.3.0 + __gnu_sssubda3@GCC_4.3.0 1:4.3.0 + __gnu_sssubdq3@GCC_4.3.0 1:4.3.0 + __gnu_sssubha3@GCC_4.3.0 1:4.3.0 + __gnu_sssubhq3@GCC_4.3.0 1:4.3.0 + __gnu_sssubqq3@GCC_4.3.0 1:4.3.0 + __gnu_sssubsa3@GCC_4.3.0 1:4.3.0 + __gnu_sssubsq3@GCC_4.3.0 1:4.3.0 + __gnu_subda3@GCC_4.3.0 1:4.3.0 + __gnu_subdq3@GCC_4.3.0 1:4.3.0 + __gnu_subha3@GCC_4.3.0 1:4.3.0 + __gnu_subhq3@GCC_4.3.0 1:4.3.0 + __gnu_subqq3@GCC_4.3.0 1:4.3.0 + __gnu_subsa3@GCC_4.3.0 1:4.3.0 + __gnu_subsq3@GCC_4.3.0 1:4.3.0 + __gnu_subuda3@GCC_4.3.0 1:4.3.0 + __gnu_subudq3@GCC_4.3.0 1:4.3.0 + __gnu_subuha3@GCC_4.3.0 1:4.3.0 + __gnu_subuhq3@GCC_4.3.0 1:4.3.0 + __gnu_subuqq3@GCC_4.3.0 1:4.3.0 + __gnu_subusa3@GCC_4.3.0 1:4.3.0 + __gnu_subusq3@GCC_4.3.0 1:4.3.0 + __gnu_udivuda3@GCC_4.3.0 1:4.3.0 + __gnu_udivudq3@GCC_4.3.0 1:4.3.0 + __gnu_udivuha3@GCC_4.3.0 1:4.3.0 + __gnu_udivuhq3@GCC_4.3.0 1:4.3.0 + __gnu_udivuqq3@GCC_4.3.0 1:4.3.0 + __gnu_udivusa3@GCC_4.3.0 1:4.3.0 + __gnu_udivusq3@GCC_4.3.0 1:4.3.0 __gnu_unwind_frame@GCC_3.5 1:4.3.0 + __gnu_usadduda3@GCC_4.3.0 1:4.3.0 + __gnu_usaddudq3@GCC_4.3.0 1:4.3.0 + __gnu_usadduha3@GCC_4.3.0 1:4.3.0 + __gnu_usadduhq3@GCC_4.3.0 1:4.3.0 + __gnu_usadduqq3@GCC_4.3.0 1:4.3.0 + __gnu_usaddusa3@GCC_4.3.0 1:4.3.0 + __gnu_usaddusq3@GCC_4.3.0 1:4.3.0 + __gnu_usashluda3@GCC_4.3.0 1:4.3.0 + __gnu_usashludq3@GCC_4.3.0 1:4.3.0 + __gnu_usashluha3@GCC_4.3.0 1:4.3.0 + __gnu_usashluhq3@GCC_4.3.0 1:4.3.0 + __gnu_usashluqq3@GCC_4.3.0 1:4.3.0 + __gnu_usashlusa3@GCC_4.3.0 1:4.3.0 + __gnu_usashlusq3@GCC_4.3.0 1:4.3.0 + __gnu_usdivuda3@GCC_4.3.0 1:4.3.0 + __gnu_usdivudq3@GCC_4.3.0 1:4.3.0 + __gnu_usdivuha3@GCC_4.3.0 1:4.3.0 + __gnu_usdivuhq3@GCC_4.3.0 1:4.3.0 + __gnu_usdivuqq3@GCC_4.3.0 1:4.3.0 + __gnu_usdivusa3@GCC_4.3.0 1:4.3.0 + __gnu_usdivusq3@GCC_4.3.0 1:4.3.0 + __gnu_usmuluda3@GCC_4.3.0 1:4.3.0 + __gnu_usmuludq3@GCC_4.3.0 1:4.3.0 + __gnu_usmuluha3@GCC_4.3.0 1:4.3.0 + __gnu_usmuluhq3@GCC_4.3.0 1:4.3.0 + __gnu_usmuluqq3@GCC_4.3.0 1:4.3.0 + __gnu_usmulusa3@GCC_4.3.0 1:4.3.0 + __gnu_usmulusq3@GCC_4.3.0 1:4.3.0 + __gnu_usneguda2@GCC_4.3.0 1:4.3.0 + __gnu_usnegudq2@GCC_4.3.0 1:4.3.0 + __gnu_usneguha2@GCC_4.3.0 1:4.3.0 + __gnu_usneguhq2@GCC_4.3.0 1:4.3.0 + __gnu_usneguqq2@GCC_4.3.0 1:4.3.0 + __gnu_usnegusa2@GCC_4.3.0 1:4.3.0 + __gnu_usnegusq2@GCC_4.3.0 1:4.3.0 + __gnu_ussubuda3@GCC_4.3.0 1:4.3.0 + __gnu_ussubudq3@GCC_4.3.0 1:4.3.0 + __gnu_ussubuha3@GCC_4.3.0 1:4.3.0 + __gnu_ussubuhq3@GCC_4.3.0 1:4.3.0 + __gnu_ussubuqq3@GCC_4.3.0 1:4.3.0 + __gnu_ussubusa3@GCC_4.3.0 1:4.3.0 + __gnu_ussubusq3@GCC_4.3.0 1:4.3.0 __gtdf2@GCC_3.0 1:4.3.0 __gtsf2@GCC_3.0 1:4.3.0 __ledf2@GCC_3.0 1:4.3.0 diff -Nru gcc-4.7-4.7.2/debian/libstdc++6.symbols.sparc gcc-4.7-4.7.3/debian/libstdc++6.symbols.sparc --- gcc-4.7-4.7.2/debian/libstdc++6.symbols.sparc 2013-07-25 18:49:32.000000000 +0000 +++ gcc-4.7-4.7.3/debian/libstdc++6.symbols.sparc 2013-07-25 18:49:34.000000000 +0000 @@ -4,6 +4,5 @@ __gxx_personality_v0@CXXABI_1.3 4.1.1 #include "libstdc++6.symbols.glibcxxmath" #include "libstdc++6.symbols.ldbl.32bit" -#include "libstdc++6.symbols.128bit" _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2 _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2 diff -Nru gcc-4.7-4.7.2/debian/libstdc++6.symbols.sparc64 gcc-4.7-4.7.3/debian/libstdc++6.symbols.sparc64 --- gcc-4.7-4.7.2/debian/libstdc++6.symbols.sparc64 2013-07-25 18:49:32.000000000 +0000 +++ gcc-4.7-4.7.3/debian/libstdc++6.symbols.sparc64 2013-07-25 18:49:34.000000000 +0000 @@ -1,6 +1,7 @@ libstdc++.so.6 libstdc++6 #MINVER# #include "libstdc++6.symbols.64bit" #include "libstdc++6.symbols.excprop" +#include "libstdc++6.symbols.128bit" _ZN9__gnu_cxx12__atomic_addEPVli@GLIBCXX_3.4 4.1.1 _ZN9__gnu_cxx18__exchange_and_addEPVli@GLIBCXX_3.4 4.1.1 # FIXME: Currently no ldbl symbols in the 64bit libstdc++ on sparc. diff -Nru gcc-4.7-4.7.2/debian/libx32gfortran3.overrides gcc-4.7-4.7.3/debian/libx32gfortran3.overrides --- gcc-4.7-4.7.2/debian/libx32gfortran3.overrides 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/libx32gfortran3.overrides 2013-07-25 18:49:34.000000000 +0000 @@ -0,0 +1,2 @@ +# automake gets it wrong for the multilib build +libx32gfortran3 binary: binary-or-shlib-defines-rpath diff -Nru gcc-4.7-4.7.2/debian/patches/aarch64-branch.diff gcc-4.7-4.7.3/debian/patches/aarch64-branch.diff --- gcc-4.7-4.7.2/debian/patches/aarch64-branch.diff 2013-07-25 18:49:32.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/aarch64-branch.diff 1970-01-01 00:00:00.000000000 +0000 @@ -1,54878 +0,0 @@ -# DP: updates from the 4.7 aarch64 branch upto 20120920 (r191561). - -last_updated() -{ - cat > ${dir}LAST_UPDATED < -+ Jim MacArthur -+ Marcus Shawcroft -+ Nigel Stephens -+ Ramana Radhakrishnan -+ Richard Earnshaw -+ Sofiane Naci -+ Stephen Thomas -+ Tejas Belagod -+ Yufeng Zhang -+ -+ * configure.tgt: Add AArch64. -Index: libstdc++-v3/configure.host -=================================================================== ---- a/src/libstdc++-v3/configure.host (.../gcc-4_7-branch) -+++ b/src/libstdc++-v3/configure.host (.../ARM/aarch64-4.7-branch) -@@ -94,6 +94,9 @@ - # variants into the established source config/cpu/* sub-directories. - # THIS TABLE IS SORTED. KEEP IT THAT WAY. - case "${host_cpu}" in -+ aarch64*) -+ try_cpu=aarch64 -+ ;; - alpha*) - try_cpu=alpha - ;; -Index: libstdc++-v3/config/cpu/aarch64/cxxabi_tweaks.h -=================================================================== ---- a/src/libstdc++-v3/config/cpu/aarch64/cxxabi_tweaks.h (.../gcc-4_7-branch) -+++ b/src/libstdc++-v3/config/cpu/aarch64/cxxabi_tweaks.h (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,60 @@ -+// Control various target specific ABI tweaks. AArch64 version. -+ -+// Copyright (C) 2004, 2006, 2008, 2009, 2011, 2012 -+// Free Software Foundation, Inc. -+// -+// This file is part of the GNU ISO C++ Library. This library is free -+// software; you can redistribute it and/or modify it under the -+// terms of the GNU General Public License as published by the -+// Free Software Foundation; either version 3, or (at your option) -+// any later version. -+ -+// This library is distributed in the hope that it will be useful, -+// but WITHOUT ANY WARRANTY; without even the implied warranty of -+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+// GNU General Public License for more details. -+ -+// Under Section 7 of GPL version 3, you are granted additional -+// permissions described in the GCC Runtime Library Exception, version -+// 3.1, as published by the Free Software Foundation. -+ -+// You should have received a copy of the GNU General Public License and -+// a copy of the GCC Runtime Library Exception along with this program; -+// see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -+// . -+ -+/** @file cxxabi_tweaks.h -+ * The header provides an CPU-variable interface to the C++ ABI. -+ */ -+ -+#ifndef _CXXABI_TWEAKS_H -+#define _CXXABI_TWEAKS_H 1 -+ -+#ifdef __cplusplus -+namespace __cxxabiv1 -+{ -+ extern "C" -+ { -+#endif -+ -+ // The AArch64 ABI uses the least significant bit of a 64-bit -+ // guard variable. -+#define _GLIBCXX_GUARD_TEST(x) ((*(x) & 1) != 0) -+#define _GLIBCXX_GUARD_SET(x) *(x) = 1 -+#define _GLIBCXX_GUARD_BIT 1 -+#define _GLIBCXX_GUARD_PENDING_BIT __guard_test_bit (1, 1) -+#define _GLIBCXX_GUARD_WAITING_BIT __guard_test_bit (2, 1) -+ __extension__ typedef int __guard __attribute__((mode (__DI__))); -+ -+ // __cxa_vec_ctor has void return type. -+ typedef void __cxa_vec_ctor_return_type; -+#define _GLIBCXX_CXA_VEC_CTOR_RETURN(x) return -+ // Constructors and destructors do not return a value. -+ typedef void __cxa_cdtor_return_type; -+ -+#ifdef __cplusplus -+ } -+} // namespace __cxxabiv1 -+#endif -+ -+#endif - -Property changes on: libstdc++-v3/config/cpu/aarch64/cxxabi_tweaks.h -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: libstdc++-v3/ChangeLog.aarch64 -=================================================================== ---- a/src/libstdc++-v3/ChangeLog.aarch64 (.../gcc-4_7-branch) -+++ b/src/libstdc++-v3/ChangeLog.aarch64 (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,4 @@ -+2012-05-25 Yufeng Zhang -+ -+ * config/cpu/aarch64/cxxabi_tweaks.h: New file. -+ * configure.host: Enable aarch64. -Index: libgcc/config.host -=================================================================== ---- a/src/libgcc/config.host (.../gcc-4_7-branch) -+++ b/src/libgcc/config.host (.../ARM/aarch64-4.7-branch) -@@ -83,6 +83,9 @@ - cpu_type=m32c - tmake_file=t-fdpbit - ;; -+aarch64*-*-*) -+ cpu_type=aarch64 -+ ;; - alpha*-*-*) - cpu_type=alpha - ;; -@@ -279,6 +282,16 @@ - esac - - case ${host} in -+aarch64*-*-elf) -+ extra_parts="$extra_parts crtbegin.o crtend.o crti.o crtn.o" -+ tmake_file="${tmake_file} ${cpu_type}/t-aarch64" -+ tmake_file="${tmake_file} ${cpu_type}/t-softfp t-softfp" -+ ;; -+aarch64*-*-linux*) -+ md_unwind_header=aarch64/linux-unwind.h -+ tmake_file="${tmake_file} ${cpu_type}/t-aarch64" -+ tmake_file="${tmake_file} ${cpu_type}/t-softfp t-softfp" -+ ;; - alpha*-*-linux*) - tmake_file="${tmake_file} alpha/t-alpha alpha/t-ieee t-crtfm alpha/t-linux" - extra_parts="$extra_parts crtfastmath.o" -Index: libgcc/config/aarch64/sfp-machine.h -=================================================================== ---- a/src/libgcc/config/aarch64/sfp-machine.h (.../gcc-4_7-branch) -+++ b/src/libgcc/config/aarch64/sfp-machine.h (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,153 @@ -+/* Machine description for AArch64 architecture. -+ Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. -+ Contributed by ARM Ltd. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3, or (at your option) -+ any later version. -+ -+ GCC is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+#define _FP_W_TYPE_SIZE 64 -+#define _FP_W_TYPE unsigned long -+#define _FP_WS_TYPE signed long -+#define _FP_I_TYPE int -+ -+typedef int TItype __attribute__ ((mode (TI))); -+typedef unsigned int UTItype __attribute__ ((mode (TI))); -+#define TI_BITS (__CHAR_BIT__ * (int)sizeof(TItype)) -+ -+/* The type of the result of a floating point comparison. This must -+ match __libgcc_cmp_return__ in GCC for the target. */ -+typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__))); -+#define CMPtype __gcc_CMPtype -+ -+#define _FP_MUL_MEAT_Q(R,X,Y) \ -+ _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm) -+ -+#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_2_udiv(Q,R,X,Y) -+ -+#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1) -+#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1) -+#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1 -+#define _FP_NANSIGN_S 0 -+#define _FP_NANSIGN_D 0 -+#define _FP_NANSIGN_Q 0 -+ -+#define _FP_KEEPNANFRACP 1 -+ -+/* This appears to be in line with the VFP conventions in the v7-a -+ ARM-ARM. Need to check with the v8 version. */ -+#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \ -+ do { \ -+ if ((_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs) \ -+ && !(_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs)) \ -+ { \ -+ R##_s = Y##_s; \ -+ _FP_FRAC_COPY_##wc(R,Y); \ -+ } \ -+ else \ -+ { \ -+ R##_s = X##_s; \ -+ _FP_FRAC_COPY_##wc(R,X); \ -+ } \ -+ R##_c = FP_CLS_NAN; \ -+ } while (0) -+ -+#define FP_EX_INVALID 0x01 -+#define FP_EX_DIVZERO 0x02 -+#define FP_EX_OVERFLOW 0x04 -+#define FP_EX_UNDERFLOW 0x08 -+#define FP_EX_INEXACT 0x10 -+ -+#define FP_HANDLE_EXCEPTIONS \ -+ do { \ -+ const float fp_max = __FLT_MAX__; \ -+ const float fp_min = __FLT_MIN__; \ -+ const float fp_1e32 = 1.0e32f; \ -+ const float fp_zero = 0.0; \ -+ const float fp_one = 1.0; \ -+ unsigned fpsr; \ -+ if (_fex & FP_EX_INVALID) \ -+ { \ -+ __asm__ __volatile__ ("fdiv\ts0, %s0, %s0" \ -+ : \ -+ : "w" (fp_zero) \ -+ : "s0"); \ -+ __asm__ __volatile__ ("mrs\t%0, fpsr" : "=r" (fpsr)); \ -+ } \ -+ if (_fex & FP_EX_DIVZERO) \ -+ { \ -+ __asm__ __volatile__ ("fdiv\ts0, %s0, %s1" \ -+ : \ -+ : "w" (fp_one), "w" (fp_zero) \ -+ : "s0"); \ -+ __asm__ __volatile__ ("mrs\t%0, fpsr" : "=r" (fpsr)); \ -+ } \ -+ if (_fex & FP_EX_OVERFLOW) \ -+ { \ -+ __asm__ __volatile__ ("fadd\ts0, %s0, %s1" \ -+ : \ -+ : "w" (fp_max), "w" (fp_1e32) \ -+ : "s0"); \ -+ __asm__ __volatile__ ("mrs\t%0, fpsr" : "=r" (fpsr)); \ -+ } \ -+ if (_fex & FP_EX_UNDERFLOW) \ -+ { \ -+ __asm__ __volatile__ ("fmul\ts0, %s0, %s0" \ -+ : \ -+ : "w" (fp_min) \ -+ : "s0"); \ -+ __asm__ __volatile__ ("mrs\t%0, fpsr" : "=r" (fpsr)); \ -+ } \ -+ if (_fex & FP_EX_INEXACT) \ -+ { \ -+ __asm__ __volatile__ ("fsub\ts0, %s0, %s1" \ -+ : \ -+ : "w" (fp_max), "w" (fp_one) \ -+ : "s0"); \ -+ __asm__ __volatile__ ("mrs\t%0, fpsr" : "=r" (fpsr)); \ -+ } \ -+ } while (0) -+ -+ -+#define FP_RND_NEAREST 0 -+#define FP_RND_ZERO 0xc00000 -+#define FP_RND_PINF 0x400000 -+#define FP_RND_MINF 0x800000 -+ -+#define _FP_DECL_EX \ -+ unsigned long int _fpcr __attribute__ ((unused)) = FP_RND_NEAREST -+ -+#define FP_INIT_ROUNDMODE \ -+ do { \ -+ __asm__ __volatile__ ("mrs %0, fpcr" \ -+ : "=r" (_fpcr)); \ -+ } while (0) -+ -+#define FP_ROUNDMODE (_fpcr & 0xc00000) -+ -+#define __LITTLE_ENDIAN 1234 -+#define __BIG_ENDIAN 4321 -+ -+#if defined __AARCH64EB__ -+# define __BYTE_ORDER __BIG_ENDIAN -+#else -+# define __BYTE_ORDER __LITTLE_ENDIAN -+#endif -+ -+ -+/* Define ALIASNAME as a strong alias for NAME. */ -+# define strong_alias(name, aliasname) _strong_alias(name, aliasname) -+# define _strong_alias(name, aliasname) \ -+ extern __typeof (name) aliasname __attribute__ ((alias (#name))); - -Property changes on: libgcc/config/aarch64/sfp-machine.h -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: libgcc/config/aarch64/crti.S -=================================================================== ---- a/src/libgcc/config/aarch64/crti.S (.../gcc-4_7-branch) -+++ b/src/libgcc/config/aarch64/crti.S (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,68 @@ -+# Machine description for AArch64 architecture. -+# Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. -+# Contributed by ARM Ltd. -+# -+# This file is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License as published by the -+# Free Software Foundation; either version 3, or (at your option) any -+# later version. -+# -+# This file is distributed in the hope that it will be useful, but -+# WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+# General Public License for more details. -+# -+# Under Section 7 of GPL version 3, you are granted additional -+# permissions described in the GCC Runtime Library Exception, version -+# 3.1, as published by the Free Software Foundation. -+# -+# You should have received a copy of the GNU General Public License and -+# a copy of the GCC Runtime Library Exception along with this program; -+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -+# . -+ -+/* An executable stack is *not* required for these functions. */ -+#if defined(__ELF__) && defined(__linux__) -+.section .note.GNU-stack,"",%progbits -+.previous -+#endif -+ -+# This file creates a stack frame for the contents of the .fini and -+# .init sections. Users may put any desired instructions in those -+# sections. -+ -+#ifdef __ELF__ -+#define TYPE(x) .type x,function -+#else -+#define TYPE(x) -+#endif -+ -+ # Note - this macro is complemented by the FUNC_END macro -+ # in crtn.S. If you change this macro you must also change -+ # that macro match. -+.macro FUNC_START -+ # Create a stack frame and save any call-preserved registers -+ stp x29, x30, [sp, #-16]! -+ stp x27, x28, [sp, #-16]! -+ stp x25, x26, [sp, #-16]! -+ stp x23, x24, [sp, #-16]! -+ stp x21, x22, [sp, #-16]! -+ stp x19, x20, [sp, #-16]! -+.endm -+ -+ .section ".init" -+ .align 2 -+ .global _init -+ TYPE(_init) -+_init: -+ FUNC_START -+ -+ -+ .section ".fini" -+ .align 2 -+ .global _fini -+ TYPE(_fini) -+_fini: -+ FUNC_START -+ -+# end of crti.S - -Property changes on: libgcc/config/aarch64/crti.S -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: libgcc/config/aarch64/t-softfp -=================================================================== ---- a/src/libgcc/config/aarch64/t-softfp (.../gcc-4_7-branch) -+++ b/src/libgcc/config/aarch64/t-softfp (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,7 @@ -+softfp_float_modes := tf -+softfp_int_modes := si di ti -+softfp_extensions := sftf dftf -+softfp_truncations := tfsf tfdf -+softfp_exclude_libgcc2 := n -+ -+TARGET_LIBGCC2_CFLAGS += -Wno-missing-prototypes -Index: libgcc/config/aarch64/crtn.S -=================================================================== ---- a/src/libgcc/config/aarch64/crtn.S (.../gcc-4_7-branch) -+++ b/src/libgcc/config/aarch64/crtn.S (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,61 @@ -+# Machine description for AArch64 architecture. -+# Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. -+# Contributed by ARM Ltd. -+# -+# This file is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License as published by the -+# Free Software Foundation; either version 3, or (at your option) any -+# later version. -+# -+# This file is distributed in the hope that it will be useful, but -+# WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+# General Public License for more details. -+# -+# Under Section 7 of GPL version 3, you are granted additional -+# permissions described in the GCC Runtime Library Exception, version -+# 3.1, as published by the Free Software Foundation. -+# -+# You should have received a copy of the GNU General Public License and -+# a copy of the GCC Runtime Library Exception along with this program; -+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -+# . -+ -+/* An executable stack is *not* required for these functions. */ -+#if defined(__ELF__) && defined(__linux__) -+.section .note.GNU-stack,"",%progbits -+.previous -+#endif -+ -+# This file just makes sure that the .fini and .init sections do in -+# fact return. Users may put any desired instructions in those sections. -+# This file is the last thing linked into any executable. -+ -+ # Note - this macro is complemented by the FUNC_START macro -+ # in crti.S. If you change this macro you must also change -+ # that macro match. -+ # -+ # Note - we do not try any fancy optimizations of the return -+ # sequences here, it is just not worth it. Instead keep things -+ # simple. Restore all the save resgisters, including the link -+ # register and then perform the correct function return instruction. -+.macro FUNC_END -+ ldp x19, x20, [sp], #16 -+ ldp x21, x22, [sp], #16 -+ ldp x23, x24, [sp], #16 -+ ldp x25, x26, [sp], #16 -+ ldp x27, x28, [sp], #16 -+ ldp x29, x30, [sp], #16 -+ ret -+.endm -+ -+ -+ .section ".init" -+ ;; -+ FUNC_END -+ -+ .section ".fini" -+ ;; -+ FUNC_END -+ -+# end of crtn.S - -Property changes on: libgcc/config/aarch64/crtn.S -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: libgcc/config/aarch64/linux-unwind.h -=================================================================== ---- a/src/libgcc/config/aarch64/linux-unwind.h (.../gcc-4_7-branch) -+++ b/src/libgcc/config/aarch64/linux-unwind.h (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,143 @@ -+/* Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. -+ Contributed by ARM Ltd. -+ -+ This file is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published by the -+ Free Software Foundation; either version 3, or (at your option) any -+ later version. -+ -+ This file is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ Under Section 7 of GPL version 3, you are granted additional -+ permissions described in the GCC Runtime Library Exception, version -+ 3.1, as published by the Free Software Foundation. -+ -+ You should have received a copy of the GNU General Public License and -+ a copy of the GCC Runtime Library Exception along with this program; -+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -+ . */ -+ -+#ifndef inhibit_libc -+ -+#include -+#include -+ -+#define MD_FALLBACK_FRAME_STATE_FOR aarch64_fallback_frame_state -+ -+static _Unwind_Reason_Code -+aarch64_fallback_frame_state (struct _Unwind_Context *context, -+ _Unwind_FrameState * fs) -+{ -+ /* The kernel creates an rt_sigframe on the stack immediately prior -+ to delivering a signal. -+ -+ This structure must have the same shape as the linux kernel -+ equivalent. */ -+ struct rt_sigframe -+ { -+ siginfo_t info; -+ struct ucontext uc; -+ }; -+ -+ struct rt_sigframe *rt_; -+ _Unwind_Ptr new_cfa; -+ unsigned *pc = context->ra; -+ struct sigcontext *sc; -+ struct _aarch64_ctx *extension_marker; -+ int i; -+ -+ /* A signal frame will have a return address pointing to -+ __default_sa_restorer. This code is hardwired as: -+ -+ 0xd2801168 movz x8, #0x8b -+ 0xd4000001 svc 0x0 -+ */ -+ if (pc[0] != 0xd2801168 || pc[1] != 0xd4000001) -+ { -+ return _URC_END_OF_STACK; -+ } -+ -+ rt_ = context->cfa; -+ sc = &rt_->uc.uc_mcontext; -+ -+/* This define duplicates the definition in aarch64.md */ -+#define SP_REGNUM 31 -+ -+ new_cfa = (_Unwind_Ptr) sc; -+ fs->regs.cfa_how = CFA_REG_OFFSET; -+ fs->regs.cfa_reg = STACK_POINTER_REGNUM; -+ fs->regs.cfa_offset = new_cfa - (_Unwind_Ptr) context->cfa; -+ -+ for (i = 0; i < AARCH64_DWARF_NUMBER_R; i++) -+ { -+ fs->regs.reg[AARCH64_DWARF_R0 + i].how = REG_SAVED_OFFSET; -+ fs->regs.reg[AARCH64_DWARF_R0 + i].loc.offset = -+ (_Unwind_Ptr) & (sc->regs[i]) - new_cfa; -+ } -+ -+ /* The core context may be extended with an arbitrary set of -+ additional contexts appended sequentially. Each additional -+ context contains a magic identifier and size in bytes. The size -+ field can be used to skip over unrecognized context extensions. -+ The end of the context sequence is marked by a context with magic -+ 0 or size 0. */ -+ for (extension_marker = (struct _aarch64_ctx *) &sc->__reserved; -+ extension_marker->magic; -+ extension_marker = (struct _aarch64_ctx *) -+ ((unsigned char *) extension_marker + extension_marker->size)) -+ { -+ if (extension_marker->magic == FPSIMD_MAGIC) -+ { -+ struct fpsimd_context *ctx = -+ (struct fpsimd_context *) extension_marker; -+ int i; -+ -+ for (i = 0; i < AARCH64_DWARF_NUMBER_V; i++) -+ { -+ _Unwind_Sword offset; -+ -+ fs->regs.reg[AARCH64_DWARF_V0 + i].how = REG_SAVED_OFFSET; -+ -+ /* sigcontext contains 32 128bit registers for V0 to -+ V31. The kernel will have saved the contents of the -+ V registers. We want to unwind the callee save D -+ registers. Each D register comprises the least -+ significant half of the corresponding V register. We -+ need to offset into the saved V register dependent on -+ our endianness to find the saved D register. */ -+ -+ offset = (_Unwind_Ptr) & (ctx->vregs[i]) - new_cfa; -+ -+ /* The endianness adjustment code below expects that a -+ saved V register is 16 bytes. */ -+ gcc_assert (sizeof (ctx->vregs[0]) == 16); -+#if defined (__AARCH64EB__) -+ offset = offset + 8; -+#endif -+ fs->regs.reg[AARCH64_DWARF_V0 + i].loc.offset = offset; -+ } -+ } -+ else -+ { -+ /* There is context provided that we do not recognize! */ -+ } -+ } -+ -+ fs->regs.reg[31].how = REG_SAVED_OFFSET; -+ fs->regs.reg[31].loc.offset = (_Unwind_Ptr) & (sc->sp) - new_cfa; -+ -+ fs->signal_frame = 1; -+ -+ fs->regs.reg[DWARF_ALT_FRAME_RETURN_COLUMN].how = REG_SAVED_VAL_OFFSET; -+ fs->regs.reg[DWARF_ALT_FRAME_RETURN_COLUMN].loc.offset = -+ (_Unwind_Ptr) (sc->pc) - new_cfa; -+ -+ fs->retaddr_column = DWARF_ALT_FRAME_RETURN_COLUMN; -+ -+ return _URC_NO_REASON; -+} -+ -+#endif - -Property changes on: libgcc/config/aarch64/linux-unwind.h -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: libgcc/config/aarch64/t-aarch64 -=================================================================== ---- a/src/libgcc/config/aarch64/t-aarch64 (.../gcc-4_7-branch) -+++ b/src/libgcc/config/aarch64/t-aarch64 (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,21 @@ -+# Machine description for AArch64 architecture. -+# Copyright (C) 2012 Free Software Foundation, Inc. -+# Contributed by ARM Ltd. -+# -+# This file is part of GCC. -+# -+# GCC is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License as published by -+# the Free Software Foundation; either version 3, or (at your option) -+# any later version. -+# -+# GCC is distributed in the hope that it will be useful, but -+# WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+# General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with GCC; see the file COPYING3. If not see -+# . -+ -+LIB2ADD += $(srcdir)/config/aarch64/sync-cache.c -Index: libgcc/config/aarch64/sync-cache.c -=================================================================== ---- a/src/libgcc/config/aarch64/sync-cache.c (.../gcc-4_7-branch) -+++ b/src/libgcc/config/aarch64/sync-cache.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,57 @@ -+/* Machine description for AArch64 architecture. -+ Copyright (C) 2012 Free Software Foundation, Inc. -+ Contributed by ARM Ltd. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3, or (at your option) -+ any later version. -+ -+ GCC is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+void -+__aarch64_sync_cache_range (const void *base, const void *end) -+{ -+ unsigned icache_lsize; -+ unsigned dcache_lsize; -+ static unsigned int cache_info = 0; -+ const char *address; -+ -+ if (! cache_info) -+ /* CTR_EL0 [3:0] contains log2 of icache line size in words. -+ CTR_EL0 [19:16] contains log2 of dcache line size in words. */ -+ asm volatile ("mrs\t%0, ctr_el0":"=r" (cache_info)); -+ -+ icache_lsize = 4 << (cache_info & 0xF); -+ dcache_lsize = 4 << ((cache_info >> 16) & 0xF); -+ -+ /* Loop over the address range, clearing one cache line at once. -+ Data cache must be flushed to unification first to make sure the -+ instruction cache fetches the updated data. 'end' is exclusive, -+ as per the GNU definition of __clear_cache. */ -+ -+ for (address = base; address < (const char *) end; address += dcache_lsize) -+ asm volatile ("dc\tcvau, %0" -+ : -+ : "r" (address) -+ : "memory"); -+ -+ asm volatile ("dsb\tish" : : : "memory"); -+ -+ for (address = base; address < (const char *) end; address += icache_lsize) -+ asm volatile ("ic\tivau, %0" -+ : -+ : "r" (address) -+ : "memory"); -+ -+ asm volatile ("dsb\tish; isb" : : : "memory"); -+} - -Property changes on: libgcc/config/aarch64/sync-cache.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: libgcc/ChangeLog.aarch64 -=================================================================== ---- a/src/libgcc/ChangeLog.aarch64 (.../gcc-4_7-branch) -+++ b/src/libgcc/ChangeLog.aarch64 (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,56 @@ -+2012-09-06 Marcus Shawcroft -+ -+ * config/aarch64/sfp-machine.h (FP_EX_INVALID, FP_EX_DIVZERO) -+ (FP_EX_OVERFLOW, FP_EX_UNDERFLOW, FP_EX_INEXACT) -+ (FP_HANDLE_EXCEPTIONS, FP_RND_NEAREST, FP_RND_ZERO, FP_RND_PINF) -+ (FP_RND_MINF, _FP_DECL_EX, FP_INIT_FOUNDMODE, FP_ROUNDMODE): New. -+ -+2012-09-03 Marcus Shawcroft -+ -+ * config/aarch64/sync-cache.c (__aarch64_sync_cache_range): Cache -+ the ctr_el0 register. -+ -+2012-09-03 Marcus Shawcroft -+ -+ * config/aarch64/sync-cache.c (__aarch64_sync_cache_range): Lift -+ declarations to top of function. Update comment. Correct -+ icache_linesize and dcache_linesize calculation. -+ -+2012-07-17 Marcus Shawcroft -+ -+ * config/aarch64/sfp-machine.h (__ARM_EABI__): Remove. -+ -+2012-06-08 Jim MacArthur -+ -+ * config.host -+ (aarch64*-*-elf): Remove t-softfp-sfdf and t-softfp-excl. -+ (aarch64*-*-linux*): Likewise. -+ -+2012-06-08 Jim MacArthur -+ -+ * config.host -+ (aarch64*-*-elf): Add t-aarch64. -+ (aarch64*-*-linux*): Add t-aarch64, remove t-linux. -+ * config/aarch64/lib1funcs.S: Delete. -+ * config/aarch64/sync-cache.c: New file. -+ * config/aarch64/t-aarch64: New file. -+ * config/aarch64/t-linux: Delete. -+ -+2012-06-08 Jim MacArthur -+ -+ * config/aarch64/t-aarch64: Delete. -+ * config.host (aarch64*-*-elf): Remove reference to t-aarch64. -+ -+2012-05-25 Ian Bolton -+ Jim MacArthur -+ Marcus Shawcroft -+ Nigel Stephens -+ Ramana Radhakrishnan -+ Richard Earnshaw -+ Sofiane Naci -+ Stephen Thomas -+ Tejas Belagod -+ Yufeng Zhang -+ -+ * configure.ac: Enable AArch64. -+ * configure: Regenerate. -Index: config.guess -=================================================================== ---- a/src/config.guess (.../gcc-4_7-branch) -+++ b/src/config.guess (.../ARM/aarch64-4.7-branch) -@@ -2,9 +2,9 @@ - # Attempt to guess a canonical system name. - # Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - # 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, --# 2011 Free Software Foundation, Inc. -+# 2011, 2012 Free Software Foundation, Inc. - --timestamp='2011-06-03' -+timestamp='2012-08-14' - - # This file is free software; you can redistribute it and/or modify it - # under the terms of the GNU General Public License as published by -@@ -17,9 +17,7 @@ - # General Public License for more details. - # - # You should have received a copy of the GNU General Public License --# along with this program; if not, write to the Free Software --# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA --# 02110-1301, USA. -+# along with this program; if not, see . - # - # As a special exception to the GNU General Public License, if you - # distribute this file as part of a program that contains a -@@ -57,8 +55,8 @@ - - Originally written by Per Bothner. - Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, --2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 Free --Software Foundation, Inc. -+2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012 -+Free Software Foundation, Inc. - - This is free software; see the source for copying conditions. There is NO - warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." -@@ -145,7 +143,7 @@ - case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in - *:NetBSD:*:*) - # NetBSD (nbsd) targets should (where applicable) match one or -- # more of the tupples: *-*-netbsdelf*, *-*-netbsdaout*, -+ # more of the tuples: *-*-netbsdelf*, *-*-netbsdaout*, - # *-*-netbsdecoff* and *-*-netbsd*. For targets that recently - # switched to ELF, *-*-netbsd* would select the old - # object file format. This provides both forward -@@ -202,6 +200,10 @@ - # CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM is used. - echo "${machine}-${os}${release}" - exit ;; -+ *:Bitrig:*:*) -+ UNAME_MACHINE_ARCH=`arch | sed 's/Bitrig.//'` -+ echo ${UNAME_MACHINE_ARCH}-unknown-bitrig${UNAME_RELEASE} -+ exit ;; - *:OpenBSD:*:*) - UNAME_MACHINE_ARCH=`arch | sed 's/OpenBSD.//'` - echo ${UNAME_MACHINE_ARCH}-unknown-openbsd${UNAME_RELEASE} -@@ -792,21 +794,26 @@ - echo ${UNAME_MACHINE}-unknown-bsdi${UNAME_RELEASE} - exit ;; - *:FreeBSD:*:*) -- case ${UNAME_MACHINE} in -- pc98) -- echo i386-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; -+ UNAME_PROCESSOR=`/usr/bin/uname -p` -+ case ${UNAME_PROCESSOR} in - amd64) - echo x86_64-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; - *) -- echo ${UNAME_MACHINE}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; -+ echo ${UNAME_PROCESSOR}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; - esac - exit ;; - i*:CYGWIN*:*) - echo ${UNAME_MACHINE}-pc-cygwin - exit ;; -+ *:MINGW64*:*) -+ echo ${UNAME_MACHINE}-pc-mingw64 -+ exit ;; - *:MINGW*:*) - echo ${UNAME_MACHINE}-pc-mingw32 - exit ;; -+ i*:MSYS*:*) -+ echo ${UNAME_MACHINE}-pc-msys -+ exit ;; - i*:windows32*:*) - # uname -m includes "-pc" on this system. - echo ${UNAME_MACHINE}-mingw32 -@@ -861,6 +868,13 @@ - i*86:Minix:*:*) - echo ${UNAME_MACHINE}-pc-minix - exit ;; -+ aarch64:Linux:*:*) -+ echo ${UNAME_MACHINE}-unknown-linux-gnu -+ exit ;; -+ aarch64_be:Linux:*:*) -+ UNAME_MACHINE=aarch64_be -+ echo ${UNAME_MACHINE}-unknown-linux-gnu -+ exit ;; - alpha:Linux:*:*) - case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in - EV5) UNAME_MACHINE=alphaev5 ;; -@@ -895,14 +909,17 @@ - echo ${UNAME_MACHINE}-unknown-linux-gnu - exit ;; - cris:Linux:*:*) -- echo cris-axis-linux-gnu -+ echo ${UNAME_MACHINE}-axis-linux-gnu - exit ;; - crisv32:Linux:*:*) -- echo crisv32-axis-linux-gnu -+ echo ${UNAME_MACHINE}-axis-linux-gnu - exit ;; - frv:Linux:*:*) -- echo frv-unknown-linux-gnu -+ echo ${UNAME_MACHINE}-unknown-linux-gnu - exit ;; -+ hexagon:Linux:*:*) -+ echo ${UNAME_MACHINE}-unknown-linux-gnu -+ exit ;; - i*86:Linux:*:*) - LIBC=gnu - eval $set_cc_for_build -@@ -943,7 +960,7 @@ - test x"${CPU}" != x && { echo "${CPU}-unknown-linux-gnu"; exit; } - ;; - or32:Linux:*:*) -- echo or32-unknown-linux-gnu -+ echo ${UNAME_MACHINE}-unknown-linux-gnu - exit ;; - padre:Linux:*:*) - echo sparc-unknown-linux-gnu -@@ -984,7 +1001,7 @@ - echo ${UNAME_MACHINE}-dec-linux-gnu - exit ;; - x86_64:Linux:*:*) -- echo x86_64-unknown-linux-gnu -+ echo ${UNAME_MACHINE}-unknown-linux-gnu - exit ;; - xtensa*:Linux:*:*) - echo ${UNAME_MACHINE}-unknown-linux-gnu -@@ -1191,6 +1208,9 @@ - BePC:Haiku:*:*) # Haiku running on Intel PC compatible. - echo i586-pc-haiku - exit ;; -+ x86_64:Haiku:*:*) -+ echo x86_64-unknown-haiku -+ exit ;; - SX-4:SUPER-UX:*:*) - echo sx4-nec-superux${UNAME_RELEASE} - exit ;; -@@ -1246,7 +1266,7 @@ - NEO-?:NONSTOP_KERNEL:*:*) - echo neo-tandem-nsk${UNAME_RELEASE} - exit ;; -- NSE-?:NONSTOP_KERNEL:*:*) -+ NSE-*:NONSTOP_KERNEL:*:*) - echo nse-tandem-nsk${UNAME_RELEASE} - exit ;; - NSR-?:NONSTOP_KERNEL:*:*) -@@ -1315,11 +1335,11 @@ - i*86:AROS:*:*) - echo ${UNAME_MACHINE}-pc-aros - exit ;; -+ x86_64:VMkernel:*:*) -+ echo ${UNAME_MACHINE}-unknown-esx -+ exit ;; - esac - --#echo '(No uname command or uname output not recognized.)' 1>&2 --#echo "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" 1>&2 -- - eval $set_cc_for_build - cat >$dummy.c < -+ -+ * config/aarch64/aarch64.h: Define CTZ_DEFINED_VALUE_AT_ZERO. -+ * config/aarch64/aarch64.md (clrsb2): New pattern. -+ * config/aarch64/aarch64.md (rbit2): New pattern. -+ * config/aarch64/aarch64.md (ctz2): New pattern. -+ -+2012-09-18 Marcus Shawcroft -+ -+ * config/aarch64/aarch64-linux.h (MULTIARCH_TUPLE): Remove. -+ (STANDARD_STARTFILE_PREFIX_1): Likewise. -+ (STANDARD_STARTFILE_PREFIX_2): Likewise. -+ -+2012-09-17 Ian Bolton -+ -+ * config/aarch64/aarch64.md (csinc3): Turn into named -+ pattern. -+ * config/aarch64/aarch64.md (ffs2): New pattern. -+ -+2012-09-17 Ian Bolton -+ -+ * config/aarch64/aarch64.md (fmsub4): Rename fnma4. -+ * config/aarch64/aarch64.md (fnmsub4): Rename fms4. -+ * config/aarch64/aarch64.md (fnmadd4): Rename fnms4. -+ * config/aarch64/aarch64.md (*fnmadd4): New pattern. -+ -+2012-09-11 Sofiane Naci -+ -+ * config.sub: Update to version 2010-08-18. -+ * config.guess: Update to version 2010-08-14. -+ -+2012-09-10 James Greenhalgh -+ Richard Earnshaw -+ -+ * common/config/aarch64/aarch64-common.c -+ (aarch_option_optimization_table): New. -+ (TARGET_OPTION_OPTIMIZATION_TABLE): Define. -+ * gcc/config.gcc ([aarch64] target_has_targetm_common): Set to yes. -+ * gcc/config/aarch64/aarch64-elf.h (ASM_OUTPUT_DEF): New definition. -+ * gcc/config/aarch64/aarch64.c (TARGET_MIN_ANCHOR_OFFSET): Define. -+ (TARGET_MAX_ANCHOR_OFFSET): Likewise. -+ -+2012-09-10 Marcus Shawcroft -+ -+ * config/aarch64/aarch64.c (aarch64_classify_address): -+ Allow 16 byte modes in constant pool. -+ -+2012-07-23 Ian Bolton -+ -+ * gcc/config/aarch64/aarch64.c (aarch64_print_operand): Use -+ aarch64_classify_symbolic_expression for classifying operands. -+ -+ * gcc/config/aarch64/aarch64.c -+ (aarch64_classify_symbolic_expression): New function. -+ -+ * gcc/config/aarch64/aarch64.c (aarch64_symbolic_constant_p): -+ New function. -+ -+ * gcc/config/aarch64/predicates.md (aarch64_valid_symref): -+ Symbol with constant offset is a valid symbol reference. -+ -+ -+2012-07-17 Marcus Shawcroft -+ -+ * config/aarch64/aarch64.c -+ (aarch64_regno_ok_for_index_p): Handle NULL reg_renumber. -+ (aarch64_regno_ok_for_base_p): Likewise. -+ (offset_7bit_signed_scaled_p): New. -+ (offset_9bit_signed_unscaled_p): New. -+ (offset_12bit_unsigned_scaled_p): New. -+ (aarch64_classify_address): Replace pair_p with allow_reg_index_p. -+ Conservative test for valid TImode and TFmode addresses. Use -+ offset_7bit_signed_scaled_p offset_9bit_signed_unscaled_p and -+ offset_12bit_unsigned_scaled_p. Remove explicit TImode and TFmode -+ tests. -+ * config/aarch64/aarch64.md (movti_aarch64): Replace 'm' with 'Ump'. -+ (movtf_aarch64): Replace 'm' with 'Ump', replace 'Utf' with 'm'. -+ * config/aarch64/constraints.md (Utf): Remove. -+ (Ump) -+ -+2012-07-17 Marcus Shawcroft -+ -+ * config/aarch64/aarch64.c (aarch64_rtx_costs): -+ Move misplaced parenthesis. -+ -+2012-07-17 Marcus Shawcroft -+ -+ * config/aarch64/aarch64-simd.md (*aarch64_simd_mov): -+ Do not emit lsl for a shift of 0. -+ (*aarch64_simd_mov): Likwise. -+ -+2012-07-04 Tejas Belagod -+ -+ * config/aarch64/aarch64-linux.h (LINUX_TARGET_LINK_SPEC): Rename -+ LINUX_DYNAMIC_LINKER to GLIBC_DYNAMIC_LINKER. -+ -+2012-06-29 Tejas Belagod -+ -+ * config/aarch64/aarch64.h (aarch64_cmodel): Fix enum name. -+ -+2012-06-22 Tejas Belagod -+ -+ * config/aarch64/aarch64-simd.md (aarch64_sqdmulh_lane, -+ aarch64_sqdmll_lane_internal, -+ aarch64_sqdmlal_lane, aarch64_sqdmlal_laneq, -+ aarch64_sqdmlsl_lane, aarch64_sqdmlsl_laneq, -+ aarch64_sqdmll2_lane_internal, -+ aarch64_sqdmlal2_lane, aarch64_sqdmlal2_laneq, -+ aarch64_sqdmlsl2_lane, aarch64_sqdmlsl2_laneq, -+ aarch64_sqdmull_lane_internal, aarch64_sqdmull_lane, -+ aarch64_sqdmull_laneq, aarch64_sqdmull2_lane_internal, -+ aarch64_sqdmull2_lane, aarch64_sqdmull2_laneq): Change the -+ constraint of the indexed operand to use instead of w. -+ * config/aarch64/aarch64.c (aarch64_hard_regno_nregs): Add case for -+ FP_LO_REGS class. -+ (aarch64_regno_regclass): Return FP_LO_REGS if register in V0 - V15. -+ (aarch64_secondary_reload): Change condition to check for both FP reg -+ classes. -+ (aarch64_class_max_nregs): Add case for FP_LO_REGS. -+ * config/aarch64/aarch64.h (reg_class): New register class FP_LO_REGS. -+ (REG_CLASS_NAMES): Likewise. -+ (REG_CLASS_CONTENTS): Likewise. -+ (FP_LO_REGNUM_P): New. -+ * config/aarch64/aarch64.md (V15_REGNUM): New. -+ * config/aarch64/constraints.md (x): New register constraint. -+ * config/aarch64/iterators.md (vwx): New. -+ -+2012-06-22 Tejas Belagod -+ -+ * config/aarch64/arm_neon.h (vpadd_f64): Remove. -+ -+2012-06-22 Sofiane Naci -+ -+ [AArch64] Update LINK_SPEC. -+ -+ * config/aarch64/aarch64-linux.h (LINUX_TARGET_LINK_SPEC): Remove -+ %{version:-v}, %{b} and %{!dynamic-linker}. -+ -+2012-06-22 Sofiane Naci -+ -+ [AArch64] Replace sprintf with snprintf. -+ -+ * config/aarch64/aarch64.c -+ (aarch64_elf_asm_constructor): Replace sprintf with snprintf. -+ (aarch64_elf_asm_destructor): Likewise. -+ (aarch64_output_casesi): Likewise. -+ (aarch64_output_asm_insn): Likewise. -+ * config/aarch64/aarch64-builtins.c (init_aarch64_simd_builtins): -+ Likewise. -+ * config/aarch64/aarch64-simd.md (*aarch64_simd_mov): Replace -+ sprintf with snprintf, and fix code layout. -+ -+2012-06-22 Sofiane Naci -+ -+ [AArch64] Fix documentation layout. -+ -+ * doc/invoke.texi: Fix white spaces after dots. -+ Change aarch64*be-*-* to aarch64_be-*-*. -+ Add documentation for -mcmodel=tiny. -+ (-march): Fix formatting. -+ (-mcpu): Likewise. -+ (-mtune): Rephrase. -+ (-march and -mcpu feature modifiers): New subsection. -+ -+2012-06-22 Sofiane Naci -+ -+ [AArch64] Use Enums for code models option selection. -+ -+ * config/aarch64/aarch64-elf-raw.h (AARCH64_DEFAULT_MEM_MODEL): Delete. -+ * config/aarch64/aarch64-linux.h (AARCH64_DEFAULT_MEM_MODEL): Delete. -+ * config/aarch64/aarch64-opts.h (enum aarch64_code_model): New. -+ * config/aarch64/aarch64-protos.h: Update comments. -+ * config/aarch64/aarch64.c: Update comments. -+ (aarch64_default_mem_model): Rename to aarch64_code_model. -+ (aarch64_expand_mov_immediate): Remove error message. -+ (aarch64_select_rtx_section): Remove assertion and update comment. -+ (aarch64_override_options): Move memory model initialization from here. -+ (struct aarch64_mem_model): Delete. -+ (aarch64_memory_models[]): Delete. -+ (initialize_aarch64_memory_model): Rename to -+ initialize_aarch64_code_model and update. -+ (aarch64_classify_symbol): Handle AARCH64_CMODEL_TINY and -+ AARCH64_CMODEL_TINY_PIC -+ * config/aarch64/aarch64.h -+ (enum aarch64_memory_model): Delete. -+ (aarch64_default_mem_model): Rename to aarch64_cmodel. -+ (HAS_LONG_COND_BRANCH): Update. -+ (HAS_LONG_UNCOND_BRANCH): Update. -+ * config/aarch64/aarch64.opt -+ (cmodel): New. -+ (mcmodel): Update. -+ -+2012-06-22 Sofiane Naci -+ -+ [AArch64] Use Enums for TLS option selection. -+ -+ * config/aarch64/aarch64-opts.h (enum aarch64_tls_type): New. -+ * config/aarch64/aarch64.c -+ (aarch64_tls_dialect): Remove. -+ (tls_symbolic_operand_type): Update comment. -+ (aarch64_override_options): Remove TLS option setup code. -+ * config/aarch64/aarch64.h -+ (TARGET_TLS_TRADITIONAL): Remove. -+ (TARGET_TLS_DESC): Update definition. -+ (enum tls_dialect): Remove. -+ (enum tls_dialect aarch64_tls_dialect) Remove. -+ * config/aarch64/aarch64.opt -+ (tls_type): New. -+ (mtls-dialect): Update. -+ -+2012-05-25 Ian Bolton -+ Jim MacArthur -+ Marcus Shawcroft -+ Nigel Stephens -+ Ramana Radhakrishnan -+ Richard Earnshaw -+ Sofiane Naci -+ Stephen Thomas -+ Tejas Belagod -+ Yufeng Zhang -+ -+ * common/config/aarch64/aarch64-common.c: New file. -+ * config/aarch64/aarch64-arches.def: New file. -+ * config/aarch64/aarch64-builtins.c: New file. -+ * config/aarch64/aarch64-cores.def: New file. -+ * config/aarch64/aarch64-elf-raw.h: New file. -+ * config/aarch64/aarch64-elf.h: New file. -+ * config/aarch64/aarch64-generic.md: New file. -+ * config/aarch64/aarch64-linux.h: New file. -+ * config/aarch64/aarch64-modes.def: New file. -+ * config/aarch64/aarch64-option-extensions.def: New file. -+ * config/aarch64/aarch64-opts.h: New file. -+ * config/aarch64/aarch64-protos.h: New file. -+ * config/aarch64/aarch64-simd.md: New file. -+ * config/aarch64/aarch64-tune.md: New file. -+ * config/aarch64/aarch64.c: New file. -+ * config/aarch64/aarch64.h: New file. -+ * config/aarch64/aarch64.md: New file. -+ * config/aarch64/aarch64.opt: New file. -+ * config/aarch64/arm_neon.h: New file. -+ * config/aarch64/constraints.md: New file. -+ * config/aarch64/gentune.sh: New file. -+ * config/aarch64/iterators.md: New file. -+ * config/aarch64/large.md: New file. -+ * config/aarch64/predicates.md: New file. -+ * config/aarch64/small.md: New file. -+ * config/aarch64/sync.md: New file. -+ * config/aarch64/t-aarch64-linux: New file. -+ * config/aarch64/t-aarch64: New file. -+ * config.gcc: Add AArch64. -+ * configure.ac: Add AArch64 TLS support detection. -+ * configure: Regenerate. -+ * doc/extend.texi (Complex Numbers): Add AArch64. -+ * doc/invoke.texi (AArch64 Options): New. -+ * doc/md.texi (Machine Constraints): Add AArch64. -+ -+ * read-rtl.c (rtx_list): New data structure. -+ (int_iterator_mapping): New data structure. -+ (int_iterator_data): New. List of int iterator details. -+ (num_int_iterator_data): New. -+ (ints): New group list. -+ (find_int): New. Find an int iterator in a list. -+ (dummy_uses_int_iterator): Dummy handle. -+ (dummy_apply_int_iterator): Dummy handle. -+ (uses_int_iterator_p): New. -+ (apply_iterator_to_rtx): Handle case for rtx field specifier 'i'. -+ (initialize_iterators): Initialize int iterators data struts. -+ (find_int_iterator): New. Find an Int iterators from a hash-table. -+ (add_int_iterator: Add int iterator to database. -+ (read_rtx): Parse and read int iterators mapping and attributes. -+ Initialize int iterators group's hash-table. Memory management. -+ (read_rtx_code): Handle case for rtl field specifier 'i'. -Index: gcc/configure -=================================================================== ---- a/src/gcc/configure (.../gcc-4_7-branch) -+++ b/src/gcc/configure (.../ARM/aarch64-4.7-branch) -@@ -23381,6 +23381,19 @@ - tls_first_minor=19 - tls_as_opt='--fatal-warnings' - ;; -+ aarch64*-*-*) -+ conftest_s=' -+ .section ".tdata","awT",%progbits -+foo: .long 25 -+ .text -+ adrp x0, :tlsgd:x -+ add x0, x0, #:tlsgd_lo12:x -+ bl __tls_get_addr -+ nop' -+ tls_first_major=2 -+ tls_first_minor=20 -+ tls_as_opt='--fatal-warnings' -+ ;; - powerpc-*-*) - conftest_s=' - .section ".tdata","awT",@progbits -Index: gcc/testsuite/gcc.target/aarch64/fcvt_float_int.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/fcvt_float_int.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/fcvt_float_int.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,15 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+ -+#define GPF float -+#define SUFFIX(x) x##f -+#define GPI int -+ -+#include "fcvt.x" -+ -+/* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, *s\[0-9\]" 2 } } */ -+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 } } */ -+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 2 } } */ -+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 } } */ -+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 2 } } */ -+/* { dg-final { scan-assembler-times "fcvtas\tw\[0-9\]+, *s\[0-9\]" 2 } } */ - -Property changes on: gcc/testsuite/gcc.target/aarch64/fcvt_float_int.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/mnegl-2.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/mnegl-2.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/mnegl-2.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,16 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+ -+long long r; -+ -+void test_signed (int a, int b) -+{ -+ /* { dg-final { scan-assembler "smnegl\tx\[0-9\]*, w\[0-9\]*, w\[0-9\]*\n" } } */ -+ r = ((long long) a) * (-((long long) b)); -+} -+ -+void test_unsigned (unsigned int a, unsigned int b) -+{ -+ /* { dg-final { scan-assembler "umnegl\tx\[0-9\]*, w\[0-9\]*, w\[0-9\]*\n" } } */ -+ r = ((long long) a) * (-((long long) b)); -+} - -Property changes on: gcc/testsuite/gcc.target/aarch64/mnegl-2.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/fcvt_float_long.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/fcvt_float_long.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/fcvt_float_long.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,13 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+ -+#define GPF float -+#define SUFFIX(x) x##f -+#define GPI long -+ -+#include "fcvt.x" -+ -+/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, *s\[0-9\]" 2 } } */ -+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 3 } } */ -+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 3 } } */ -+/* { dg-final { scan-assembler-times "fcvtas\tx\[0-9\]+, *s\[0-9\]" 2 } } */ - -Property changes on: gcc/testsuite/gcc.target/aarch64/fcvt_float_long.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin.x -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin.x (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin.x (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,32 @@ -+ -+typedef float *__restrict__ pRF32; -+typedef double *__restrict__ pRF64; -+ -+ -+void max_F32 (pRF32 a, pRF32 b, pRF32 c) -+{ -+ int i; -+ for (i=0;i<16;i++) -+ c[i] = (a[i] > b[i] ? a[i] : b[i]); -+} -+ -+void min_F32 (pRF32 a, pRF32 b, pRF32 c) -+{ -+ int i; -+ for (i=0;i<16;i++) -+ c[i] = (a[i] < b[i] ? a[i] : b[i]); -+} -+ -+void max_F64 (pRF64 a, pRF64 b, pRF64 c) -+{ -+ int i; -+ for (i=0;i<16;i++) -+ c[i] = (a[i] > b[i] ? a[i] : b[i]); -+} -+ -+void min_F64 (pRF64 a, pRF64 b, pRF64 c) -+{ -+ int i; -+ for (i=0;i<16;i++) -+ c[i] = (a[i] < b[i] ? a[i] : b[i]); -+} -Index: gcc/testsuite/gcc.target/aarch64/frint.x -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/frint.x (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/frint.x (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,66 @@ -+extern GPF SUFFIX(trunc) (GPF); -+extern GPF SUFFIX(ceil) (GPF); -+extern GPF SUFFIX(floor) (GPF); -+extern GPF SUFFIX(nearbyint) (GPF); -+extern GPF SUFFIX(rint) (GPF); -+extern GPF SUFFIX(round) (GPF); -+ -+GPF test1a (GPF x) -+{ -+ return SUFFIX(__builtin_trunc)(x); -+} -+ -+GPF test1b (GPF x) -+{ -+ return SUFFIX(trunc)(x); -+} -+ -+GPF test2a (GPF x) -+{ -+ return SUFFIX(__builtin_ceil)(x); -+} -+ -+GPF test2b (GPF x) -+{ -+ return SUFFIX(ceil)(x); -+} -+ -+GPF test3a (GPF x) -+{ -+ return SUFFIX(__builtin_floor)(x); -+} -+ -+GPF test3b (GPF x) -+{ -+ return SUFFIX(floor)(x); -+} -+ -+GPF test4a (GPF x) -+{ -+ return SUFFIX(__builtin_nearbyint)(x); -+} -+ -+GPF test4b (GPF x) -+{ -+ return SUFFIX(nearbyint)(x); -+} -+ -+GPF test5a (GPF x) -+{ -+ return SUFFIX(__builtin_rint)(x); -+} -+ -+GPF test5b (GPF x) -+{ -+ return SUFFIX(rint)(x); -+} -+ -+GPF test6a (GPF x) -+{ -+ return SUFFIX(__builtin_round)(x); -+} -+ -+GPF test6b (GPF x) -+{ -+ return SUFFIX(round)(x); -+} -Index: gcc/testsuite/gcc.target/aarch64/tst-1.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/tst-1.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/tst-1.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,49 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+ -+volatile unsigned int w0, w1; -+volatile int result; -+ -+void test_si() { -+ /* { dg-final { scan-assembler "tst\tw\[0-9\]*, w\[0-9\]*\n" } } */ -+ result = !(w0 & w1); -+ /* { dg-final { scan-assembler "tst\tw\[0-9\]*, \(0x\[0-9a-fA-F\]+\)|\(\[0-9\]+\)" } } */ -+ result = !(w0 & 0x00f0); -+ /* { dg-final { scan-assembler "tst\tw\[0-9\]*.*lsl 4" } } */ -+ result = !(w0 & (w1 << 4)); -+} -+ -+void test_si_tbnz() { -+ /* { dg-final { scan-assembler "tbnz\t\[wx\]\[0-9\]*" } } */ -+jumpto: -+ if (w0 & 0x08) goto jumpto; -+} -+ -+void test_si_tbz() { -+ /* { dg-final { scan-assembler "tbz\t\[wx\]\[0-9\]*" } } */ -+jumpto: -+ if (!(w1 & 0x08)) goto jumpto; -+} -+ -+volatile unsigned long long x0, x1; -+ -+void test_di() { -+ /* { dg-final { scan-assembler "tst\tx\[0-9\]*, x\[0-9\]*\n" } } */ -+ result = !(x0 & x1); -+ /* { dg-final { scan-assembler "tst\tx\[0-9\]*, \(0x\[0-9a-fA-F\]+\)|\(\[0-9\]+\)" } } */ -+ result = !(x0 & 0x00f0); -+ /* { dg-final { scan-assembler "tst\tx\[0-9\]*.*lsl 4" } } */ -+ result = !(x0 & (x1 << 4)); -+} -+ -+void test_di_tbnz() { -+ /* { dg-final { scan-assembler "tbnz\tx\[0-9\]*" } } */ -+jumpto: -+ if (x0 & 0x08) goto jumpto; -+} -+ -+void test_di_tbz() { -+ /* { dg-final { scan-assembler "tbz\tx\[0-9\]*" } } */ -+jumpto: -+ if (!(x1 & 0x08)) goto jumpto; -+} - -Property changes on: gcc/testsuite/gcc.target/aarch64/tst-1.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,1181 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+ -+#include "../../../config/aarch64/arm_neon.h" -+ -+/* { dg-final { scan-assembler-times "\\tadd\\tx\[0-9\]+" 2 } } */ -+ -+uint64x1_t -+test_vaddd_u64 (uint64x1_t a, uint64x1_t b) -+{ -+ return vaddd_u64 (a, b); -+} -+ -+int64x1_t -+test_vaddd_s64 (int64x1_t a, int64x1_t b) -+{ -+ return vaddd_s64 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tadd\\td\[0-9\]+" 1 } } */ -+ -+int64x1_t -+test_vaddd_s64_2 (int64x1_t a, int64x1_t b, int64x1_t c, int64x1_t d) -+{ -+ return vqaddd_s64 (vaddd_s64 (vqaddd_s64 (a, b), vqaddd_s64 (c, d)), -+ vqaddd_s64 (a, d)); -+} -+ -+/* { dg-final { scan-assembler-times "\\tcmeq\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */ -+ -+uint64x1_t -+test_vceqd_s64 (int64x1_t a, int64x1_t b) -+{ -+ return vceqd_s64 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tcmeq\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */ -+ -+uint64x1_t -+test_vceqzd_s64 (int64x1_t a) -+{ -+ return vceqzd_s64 (a); -+} -+ -+/* { dg-final { scan-assembler-times "\\tcmge\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */ -+ -+uint64x1_t -+test_vcged_s64 (int64x1_t a, int64x1_t b) -+{ -+ return vcged_s64 (a, b); -+} -+ -+uint64x1_t -+test_vcled_s64 (int64x1_t a, int64x1_t b) -+{ -+ return vcled_s64 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tcmge\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */ -+ -+uint64x1_t -+test_vcgezd_s64 (int64x1_t a) -+{ -+ return vcgezd_s64 (a); -+} -+ -+/* { dg-final { scan-assembler-times "\\tcmhs\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */ -+ -+uint64x1_t -+test_vcged_u64 (uint64x1_t a, uint64x1_t b) -+{ -+ return vcged_u64 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tcmgt\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */ -+ -+uint64x1_t -+test_vcgtd_s64 (int64x1_t a, int64x1_t b) -+{ -+ return vcgtd_s64 (a, b); -+} -+ -+uint64x1_t -+test_vcltd_s64 (int64x1_t a, int64x1_t b) -+{ -+ return vcltd_s64 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tcmgt\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */ -+ -+uint64x1_t -+test_vcgtzd_s64 (int64x1_t a) -+{ -+ return vcgtzd_s64 (a); -+} -+ -+/* { dg-final { scan-assembler-times "\\tcmhi\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */ -+ -+uint64x1_t -+test_vcgtd_u64 (uint64x1_t a, uint64x1_t b) -+{ -+ return vcgtd_u64 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tcmle\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */ -+ -+uint64x1_t -+test_vclezd_s64 (int64x1_t a) -+{ -+ return vclezd_s64 (a); -+} -+ -+/* { dg-final { scan-assembler-times "\\tcmlt\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */ -+ -+uint64x1_t -+test_vcltzd_s64 (int64x1_t a) -+{ -+ return vcltzd_s64 (a); -+} -+ -+/* { dg-final { scan-assembler-times "\\tdup\\tb\[0-9\]+, v\[0-9\]+\.b" 2 } } */ -+ -+int8x1_t -+test_vdupb_lane_s8 (int8x16_t a) -+{ -+ return vdupb_lane_s8 (a, 2); -+} -+ -+uint8x1_t -+test_vdupb_lane_u8 (uint8x16_t a) -+{ -+ return vdupb_lane_u8 (a, 2); -+} -+ -+/* { dg-final { scan-assembler-times "\\tdup\\th\[0-9\]+, v\[0-9\]+\.h" 2 } } */ -+ -+int16x1_t -+test_vduph_lane_s16 (int16x8_t a) -+{ -+ return vduph_lane_s16 (a, 2); -+} -+ -+uint16x1_t -+test_vduph_lane_u16 (uint16x8_t a) -+{ -+ return vduph_lane_u16 (a, 2); -+} -+ -+/* { dg-final { scan-assembler-times "\\tdup\\ts\[0-9\]+, v\[0-9\]+\.s" 2 } } */ -+ -+int32x1_t -+test_vdups_lane_s32 (int32x4_t a) -+{ -+ return vdups_lane_s32 (a, 2); -+} -+ -+uint32x1_t -+test_vdups_lane_u32 (uint32x4_t a) -+{ -+ return vdups_lane_u32 (a, 2); -+} -+ -+/* { dg-final { scan-assembler-times "\\tdup\\td\[0-9\]+, v\[0-9\]+\.d" 2 } } */ -+ -+int64x1_t -+test_vdupd_lane_s64 (int64x2_t a) -+{ -+ return vdupd_lane_s64 (a, 2); -+} -+ -+uint64x1_t -+test_vdupd_lane_u64 (uint64x2_t a) -+{ -+ return vdupd_lane_u64 (a, 2); -+} -+ -+/* { dg-final { scan-assembler-times "\\tcmtst\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */ -+ -+int64x1_t -+test_vtst_s64 (int64x1_t a, int64x1_t b) -+{ -+ return vtstd_s64 (a, b); -+} -+ -+uint64x1_t -+test_vtst_u64 (uint64x1_t a, uint64x1_t b) -+{ -+ return vtstd_u64 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\taddp\\td\[0-9\]+, v\[0-9\]+\.2d" 1 } } */ -+ -+test_vpaddd_s64 (int64x2_t a) -+{ -+ return vpaddd_s64 (a); -+} -+ -+/* { dg-final { scan-assembler-times "\\tuqadd\\td\[0-9\]+" 1 } } */ -+ -+uint64x1_t -+test_vqaddd_u64 (uint64x1_t a, uint64x1_t b) -+{ -+ return vqaddd_u64 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tuqadd\\ts\[0-9\]+" 1 } } */ -+ -+uint32x1_t -+test_vqadds_u32 (uint32x1_t a, uint32x1_t b) -+{ -+ return vqadds_u32 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tuqadd\\th\[0-9\]+" 1 } } */ -+ -+uint16x1_t -+test_vqaddh_u16 (uint16x1_t a, uint16x1_t b) -+{ -+ return vqaddh_u16 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tuqadd\\tb\[0-9\]+" 1 } } */ -+ -+uint8x1_t -+test_vqaddb_u8 (uint8x1_t a, uint8x1_t b) -+{ -+ return vqaddb_u8 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqadd\\td\[0-9\]+" 5 } } */ -+ -+int64x1_t -+test_vqaddd_s64 (int64x1_t a, int64x1_t b) -+{ -+ return vqaddd_s64 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqadd\\ts\[0-9\]+, s\[0-9\]+" 1 } } */ -+ -+int32x1_t -+test_vqadds_s32 (int32x1_t a, int32x1_t b) -+{ -+ return vqadds_s32 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqadd\\th\[0-9\]+, h\[0-9\]+" 1 } } */ -+ -+int16x1_t -+test_vqaddh_s16 (int16x1_t a, int16x1_t b) -+{ -+ return vqaddh_s16 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqadd\\tb\[0-9\]+, b\[0-9\]+" 1 } } */ -+ -+int8x1_t -+test_vqaddb_s8 (int8x1_t a, int8x1_t b) -+{ -+ return vqaddb_s8 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmlal\\ts\[0-9\]+, h\[0-9\]+, h\[0-9\]+" 1 } } */ -+ -+int32x1_t -+test_vqdmlalh_s16 (int32x1_t a, int16x1_t b, int16x1_t c) -+{ -+ return vqdmlalh_s16 (a, b, c); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmlal\\ts\[0-9\]+, h\[0-9\]+, v" 1 } } */ -+ -+int32x1_t -+test_vqdmlalh_lane_s16 (int32x1_t a, int16x1_t b, int16x8_t c) -+{ -+ return vqdmlalh_lane_s16 (a, b, c, 3); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmlal\\td\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */ -+ -+int64x1_t -+test_vqdmlals_s32 (int64x1_t a, int32x1_t b, int32x1_t c) -+{ -+ return vqdmlals_s32 (a, b, c); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmlal\\td\[0-9\]+, s\[0-9\]+, v" 1 } } */ -+ -+int64x1_t -+test_vqdmlals_lane_s32 (int64x1_t a, int32x1_t b, int32x4_t c) -+{ -+ return vqdmlals_lane_s32 (a, b, c, 1); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmlsl\\ts\[0-9\]+, h\[0-9\]+, h\[0-9\]+" 1 } } */ -+ -+int32x1_t -+test_vqdmlslh_s16 (int32x1_t a, int16x1_t b, int16x1_t c) -+{ -+ return vqdmlslh_s16 (a, b, c); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmlsl\\ts\[0-9\]+, h\[0-9\]+, v" 1 } } */ -+ -+int32x1_t -+test_vqdmlslh_lane_s16 (int32x1_t a, int16x1_t b, int16x8_t c) -+{ -+ return vqdmlslh_lane_s16 (a, b, c, 3); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmlsl\\td\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */ -+ -+int64x1_t -+test_vqdmlsls_s32 (int64x1_t a, int32x1_t b, int32x1_t c) -+{ -+ return vqdmlsls_s32 (a, b, c); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmlsl\\td\[0-9\]+, s\[0-9\]+, v" 1 } } */ -+ -+int64x1_t -+test_vqdmlsls_lane_s32 (int64x1_t a, int32x1_t b, int32x4_t c) -+{ -+ return vqdmlsls_lane_s32 (a, b, c, 1); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmulh\\th\[0-9\]+, h\[0-9\]+, h\[0-9\]+" 1 } } */ -+ -+int16x1_t -+test_vqdmulhh_s16 (int16x1_t a, int16x1_t b) -+{ -+ return vqdmulhh_s16 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmulh\\th\[0-9\]+, h\[0-9\]+, v" 1 } } */ -+ -+int16x1_t -+test_vqdmulhh_lane_s16 (int16x1_t a, int16x8_t b) -+{ -+ return vqdmulhh_lane_s16 (a, b, 3); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmulh\\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */ -+ -+int32x1_t -+test_vqdmulhs_s32 (int32x1_t a, int32x1_t b) -+{ -+ return vqdmulhs_s32 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmulh\\ts\[0-9\]+, s\[0-9\]+, v" 1 } } */ -+ -+int32x1_t -+test_vqdmulhs_lane_s32 (int32x1_t a, int32x4_t b) -+{ -+ return vqdmulhs_lane_s32 (a, b, 3); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmull\\ts\[0-9\]+, h\[0-9\]+, h\[0-9\]+" 1 } } */ -+ -+int32x1_t -+test_vqdmullh_s16 (int16x1_t a, int16x1_t b) -+{ -+ return vqdmullh_s16 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmull\\ts\[0-9\]+, h\[0-9\]+, v" 1 } } */ -+ -+int32x1_t -+test_vqdmullh_lane_s16 (int16x1_t a, int16x8_t b) -+{ -+ return vqdmullh_lane_s16 (a, b, 3); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmull\\td\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */ -+ -+int64x1_t -+test_vqdmulls_s32 (int32x1_t a, int32x1_t b) -+{ -+ return vqdmulls_s32 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmull\\td\[0-9\]+, s\[0-9\]+, v" 1 } } */ -+ -+int64x1_t -+test_vqdmulls_lane_s32 (int32x1_t a, int32x4_t b) -+{ -+ return vqdmulls_lane_s32 (a, b, 1); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqrdmulh\\th\[0-9\]+, h\[0-9\]+, h\[0-9\]+" 1 } } */ -+ -+int16x1_t -+test_vqrdmulhh_s16 (int16x1_t a, int16x1_t b) -+{ -+ return vqrdmulhh_s16 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqrdmulh\\th\[0-9\]+, h\[0-9\]+, v" 1 } } */ -+ -+int16x1_t -+test_vqrdmulhh_lane_s16 (int16x1_t a, int16x8_t b) -+{ -+ return vqrdmulhh_lane_s16 (a, b, 6); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqrdmulh\\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */ -+ -+int32x1_t -+test_vqrdmulhs_s32 (int32x1_t a, int32x1_t b) -+{ -+ return vqrdmulhs_s32 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqrdmulh\\ts\[0-9\]+, s\[0-9\]+, v" 1 } } */ -+ -+int32x1_t -+test_vqrdmulhs_lane_s32 (int32x1_t a, int32x4_t b) -+{ -+ return vqrdmulhs_lane_s32 (a, b, 2); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsuqadd\\tb\[0-9\]+" 1 } } */ -+ -+int8x1_t -+test_vuqaddb_s8 (int8x1_t a, int8x1_t b) -+{ -+ return vuqaddb_s8 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsuqadd\\th\[0-9\]+" 1 } } */ -+ -+int16x1_t -+test_vuqaddh_s16 (int16x1_t a, int8x1_t b) -+{ -+ return vuqaddh_s16 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsuqadd\\ts\[0-9\]+" 1 } } */ -+ -+int32x1_t -+test_vuqadds_s32 (int32x1_t a, int8x1_t b) -+{ -+ return vuqadds_s32 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsuqadd\\td\[0-9\]+" 1 } } */ -+ -+int64x1_t -+test_vuqaddd_s64 (int64x1_t a, int8x1_t b) -+{ -+ return vuqaddd_s64 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tusqadd\\tb\[0-9\]+" 1 } } */ -+ -+uint8x1_t -+test_vsqaddb_u8 (uint8x1_t a, int8x1_t b) -+{ -+ return vsqaddb_u8 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tusqadd\\th\[0-9\]+" 1 } } */ -+ -+uint16x1_t -+test_vsqaddh_u16 (uint16x1_t a, int8x1_t b) -+{ -+ return vsqaddh_u16 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tusqadd\\ts\[0-9\]+" 1 } } */ -+ -+uint32x1_t -+test_vsqadds_u32 (uint32x1_t a, int8x1_t b) -+{ -+ return vsqadds_u32 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tusqadd\\td\[0-9\]+" 1 } } */ -+ -+uint64x1_t -+test_vsqaddd_u64 (uint64x1_t a, int8x1_t b) -+{ -+ return vsqaddd_u64 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqabs\\tb\[0-9\]+" 1 } } */ -+ -+int8x1_t -+test_vqabsb_s8 (int8x1_t a) -+{ -+ return vqabsb_s8 (a); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqabs\\th\[0-9\]+" 1 } } */ -+ -+int16x1_t -+test_vqabsh_s16 (int16x1_t a) -+{ -+ return vqabsh_s16 (a); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqabs\\ts\[0-9\]+" 1 } } */ -+ -+int32x1_t -+test_vqabss_s32 (int32x1_t a) -+{ -+ return vqabss_s32 (a); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqneg\\tb\[0-9\]+" 1 } } */ -+ -+int8x1_t -+test_vqnegb_s8 (int8x1_t a) -+{ -+ return vqnegb_s8 (a); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqneg\\th\[0-9\]+" 1 } } */ -+ -+int16x1_t -+test_vqnegh_s16 (int16x1_t a) -+{ -+ return vqnegh_s16 (a); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqneg\\ts\[0-9\]+" 1 } } */ -+ -+int32x1_t -+test_vqnegs_s32 (int32x1_t a) -+{ -+ return vqnegs_s32 (a); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqxtun\\tb\[0-9\]+" 1 } } */ -+ -+int8x1_t -+test_vqmovunh_s16 (int16x1_t a) -+{ -+ return vqmovunh_s16 (a); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqxtun\\th\[0-9\]+" 1 } } */ -+ -+int16x1_t -+test_vqmovuns_s32 (int32x1_t a) -+{ -+ return vqmovuns_s32 (a); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqxtun\\ts\[0-9\]+" 1 } } */ -+ -+int32x1_t -+test_vqmovund_s64 (int64x1_t a) -+{ -+ return vqmovund_s64 (a); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqxtn\\tb\[0-9\]+" 1 } } */ -+ -+int8x1_t -+test_vqmovnh_s16 (int16x1_t a) -+{ -+ return vqmovnh_s16 (a); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqxtn\\th\[0-9\]+" 1 } } */ -+ -+int16x1_t -+test_vqmovns_s32 (int32x1_t a) -+{ -+ return vqmovns_s32 (a); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqxtn\\ts\[0-9\]+" 1 } } */ -+ -+int32x1_t -+test_vqmovnd_s64 (int64x1_t a) -+{ -+ return vqmovnd_s64 (a); -+} -+ -+/* { dg-final { scan-assembler-times "\\tuqxtn\\tb\[0-9\]+" 1 } } */ -+ -+uint8x1_t -+test_vqmovnh_u16 (uint16x1_t a) -+{ -+ return vqmovnh_u16 (a); -+} -+ -+/* { dg-final { scan-assembler-times "\\tuqxtn\\th\[0-9\]+" 1 } } */ -+ -+uint16x1_t -+test_vqmovns_u32 (uint32x1_t a) -+{ -+ return vqmovns_u32 (a); -+} -+ -+/* { dg-final { scan-assembler-times "\\tuqxtn\\ts\[0-9\]+" 1 } } */ -+ -+uint32x1_t -+test_vqmovnd_u64 (uint64x1_t a) -+{ -+ return vqmovnd_u64 (a); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsub\\tx\[0-9\]+" 2 } } */ -+ -+uint64x1_t -+test_vsubd_u64 (uint64x1_t a, uint64x1_t b) -+{ -+ return vsubd_u64 (a, b); -+} -+ -+int64x1_t -+test_vsubd_s64 (int64x1_t a, int64x1_t b) -+{ -+ return vsubd_s64 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsub\\td\[0-9\]+" 1 } } */ -+ -+int64x1_t -+test_vsubd_s64_2 (int64x1_t a, int64x1_t b, int64x1_t c, int64x1_t d) -+{ -+ return vqsubd_s64 (vsubd_s64 (vqsubd_s64 (a, b), vqsubd_s64 (c, d)), -+ vqsubd_s64 (a, d)); -+} -+ -+/* { dg-final { scan-assembler-times "\\tuqsub\\td\[0-9\]+" 1 } } */ -+ -+uint64x1_t -+test_vqsubd_u64 (uint64x1_t a, uint64x1_t b) -+{ -+ return vqsubd_u64 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tuqsub\\ts\[0-9\]+" 1 } } */ -+ -+uint32x1_t -+test_vqsubs_u32 (uint32x1_t a, uint32x1_t b) -+{ -+ return vqsubs_u32 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tuqsub\\th\[0-9\]+" 1 } } */ -+ -+uint16x1_t -+test_vqsubh_u16 (uint16x1_t a, uint16x1_t b) -+{ -+ return vqsubh_u16 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tuqsub\\tb\[0-9\]+" 1 } } */ -+ -+uint8x1_t -+test_vqsubb_u8 (uint8x1_t a, uint8x1_t b) -+{ -+ return vqsubb_u8 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqsub\\td\[0-9\]+" 5 } } */ -+ -+int64x1_t -+test_vqsubd_s64 (int64x1_t a, int64x1_t b) -+{ -+ return vqsubd_s64 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqsub\\ts\[0-9\]+" 1 } } */ -+ -+int32x1_t -+test_vqsubs_s32 (int32x1_t a, int32x1_t b) -+{ -+ return vqsubs_s32 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqsub\\th\[0-9\]+" 1 } } */ -+ -+int16x1_t -+test_vqsubh_s16 (int16x1_t a, int16x1_t b) -+{ -+ return vqsubh_s16 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqsub\\tb\[0-9\]+" 1 } } */ -+ -+int8x1_t -+test_vqsubb_s8 (int8x1_t a, int8x1_t b) -+{ -+ return vqsubb_s8 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsshl\\td\[0-9\]+" 1 } } */ -+ -+int64x1_t -+test_vshld_s64 (int64x1_t a, int64x1_t b) -+{ -+ return vshld_s64 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tushl\\td\[0-9\]+" 1 } } */ -+ -+uint64x1_t -+test_vshld_u64 (uint64x1_t a, uint64x1_t b) -+{ -+ return vshld_u64 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsrshl\\td\[0-9\]+" 1 } } */ -+ -+int64x1_t -+test_vrshld_s64 (int64x1_t a, int64x1_t b) -+{ -+ return vrshld_s64 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\turshl\\td\[0-9\]+" 1 } } */ -+ -+uint64x1_t -+test_vrshld_u64 (uint64x1_t a, uint64x1_t b) -+{ -+ return vrshld_u64 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tasr\\tx\[0-9\]+" 1 } } */ -+ -+int64x1_t -+test_vshrd_n_s64 (int64x1_t a) -+{ -+ return vshrd_n_s64 (a, 5); -+} -+ -+/* { dg-final { scan-assembler-times "\\tlsr\\tx\[0-9\]+" 1 } } */ -+ -+uint64x1_t -+test_vshrd_n_u64 (uint64x1_t a) -+{ -+ return vshrd_n_u64 (a, 3); -+} -+ -+/* { dg-final { scan-assembler-times "\\tssra\\td\[0-9\]+" 1 } } */ -+ -+int64x1_t -+test_vsrad_n_s64 (int64x1_t a, int64x1_t b) -+{ -+ return vsrad_n_s64 (a, b, 2); -+} -+ -+/* { dg-final { scan-assembler-times "\\tusra\\td\[0-9\]+" 1 } } */ -+ -+uint64x1_t -+test_vsrad_n_u64 (uint64x1_t a, uint64x1_t b) -+{ -+ return vsrad_n_u64 (a, b, 5); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsrshr\\td\[0-9\]+" 1 } } */ -+ -+int64x1_t -+test_vrshrd_n_s64 (int64x1_t a) -+{ -+ return vrshrd_n_s64 (a, 5); -+} -+ -+/* { dg-final { scan-assembler-times "\\turshr\\td\[0-9\]+" 1 } } */ -+ -+uint64x1_t -+test_vrshrd_n_u64 (uint64x1_t a) -+{ -+ return vrshrd_n_u64 (a, 3); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsrsra\\td\[0-9\]+" 1 } } */ -+ -+int64x1_t -+test_vrsrad_n_s64 (int64x1_t a, int64x1_t b) -+{ -+ return vrsrad_n_s64 (a, b, 3); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsrsra\\td\[0-9\]+" 1 } } */ -+ -+uint64x1_t -+test_vrsrad_n_u64 (uint64x1_t a, uint64x1_t b) -+{ -+ return vrsrad_n_u64 (a, b, 4); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqrshl\\tb\[0-9\]+" 1 } } */ -+ -+int8x1_t -+test_vqrshlb_s8 (int8x1_t a, int8x1_t b) -+{ -+ return vqrshlb_s8 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqrshl\\th\[0-9\]+" 1 } } */ -+ -+int16x1_t -+test_vqrshlh_s16 (int16x1_t a, int16x1_t b) -+{ -+ return vqrshlh_s16 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqrshl\\ts\[0-9\]+" 1 } } */ -+ -+int32x1_t -+test_vqrshls_s32 (int32x1_t a, int32x1_t b) -+{ -+ return vqrshls_s32 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqrshl\\td\[0-9\]+" 1 } } */ -+ -+int64x1_t -+test_vqrshld_s64 (int64x1_t a, int64x1_t b) -+{ -+ return vqrshld_s64 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tuqrshl\\tb\[0-9\]+" 1 } } */ -+ -+uint8x1_t -+test_vqrshlb_u8 (uint8x1_t a, uint8x1_t b) -+{ -+ return vqrshlb_u8 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tuqrshl\\th\[0-9\]+" 1 } } */ -+ -+uint16x1_t -+test_vqrshlh_u16 (uint16x1_t a, uint16x1_t b) -+{ -+ return vqrshlh_u16 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tuqrshl\\ts\[0-9\]+" 1 } } */ -+ -+uint32x1_t -+test_vqrshls_u32 (uint32x1_t a, uint32x1_t b) -+{ -+ return vqrshls_u32 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tuqrshl\\td\[0-9\]+" 1 } } */ -+ -+uint64x1_t -+test_vqrshld_u64 (uint64x1_t a, uint64x1_t b) -+{ -+ return vqrshld_u64 (a, b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqshlu\\tb\[0-9\]+" 1 } } */ -+ -+int8x1_t -+test_vqshlub_n_s8 (int8x1_t a) -+{ -+ return vqshlub_n_s8 (a, 3); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqshlu\\th\[0-9\]+" 1 } } */ -+ -+int16x1_t -+test_vqshluh_n_s16 (int16x1_t a) -+{ -+ return vqshluh_n_s16 (a, 4); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqshlu\\ts\[0-9\]+" 1 } } */ -+ -+int32x1_t -+test_vqshlus_n_s32 (int32x1_t a) -+{ -+ return vqshlus_n_s32 (a, 5); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqshlu\\td\[0-9\]+" 1 } } */ -+ -+int64x1_t -+test_vqshlud_n_s64 (int64x1_t a) -+{ -+ return vqshlud_n_s64 (a, 6); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqshl\\tb\[0-9\]+" 2 } } */ -+ -+int8x1_t -+test_vqshlb_s8 (int8x1_t a, int8x1_t b) -+{ -+ return vqshlb_s8 (a, b); -+} -+ -+int8x1_t -+test_vqshlb_n_s8 (int8x1_t a) -+{ -+ return vqshlb_n_s8 (a, 2); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqshl\\th\[0-9\]+" 2 } } */ -+ -+int16x1_t -+test_vqshlh_s16 (int16x1_t a, int16x1_t b) -+{ -+ return vqshlh_s16 (a, b); -+} -+ -+int16x1_t -+test_vqshlh_n_s16 (int16x1_t a) -+{ -+ return vqshlh_n_s16 (a, 3); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqshl\\ts\[0-9\]+" 2 } } */ -+ -+int32x1_t -+test_vqshls_s32 (int32x1_t a, int32x1_t b) -+{ -+ return vqshls_s32 (a, b); -+} -+ -+int32x1_t -+test_vqshls_n_s32 (int32x1_t a) -+{ -+ return vqshls_n_s32 (a, 4); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqshl\\td\[0-9\]+" 2 } } */ -+ -+int64x1_t -+test_vqshld_s64 (int64x1_t a, int64x1_t b) -+{ -+ return vqshld_s64 (a, b); -+} -+ -+int64x1_t -+test_vqshld_n_s64 (int64x1_t a) -+{ -+ return vqshld_n_s64 (a, 5); -+} -+ -+/* { dg-final { scan-assembler-times "\\tuqshl\\tb\[0-9\]+" 2 } } */ -+ -+uint8x1_t -+test_vqshlb_u8 (uint8x1_t a, uint8x1_t b) -+{ -+ return vqshlb_u8 (a, b); -+} -+ -+uint8x1_t -+test_vqshlb_n_u8 (uint8x1_t a) -+{ -+ return vqshlb_n_u8 (a, 2); -+} -+ -+/* { dg-final { scan-assembler-times "\\tuqshl\\th\[0-9\]+" 2 } } */ -+ -+uint16x1_t -+test_vqshlh_u16 (uint16x1_t a, uint16x1_t b) -+{ -+ return vqshlh_u16 (a, b); -+} -+ -+uint16x1_t -+test_vqshlh_n_u16 (uint16x1_t a) -+{ -+ return vqshlh_n_u16 (a, 3); -+} -+ -+/* { dg-final { scan-assembler-times "\\tuqshl\\ts\[0-9\]+" 2 } } */ -+ -+uint32x1_t -+test_vqshls_u32 (uint32x1_t a, uint32x1_t b) -+{ -+ return vqshls_u32 (a, b); -+} -+ -+uint32x1_t -+test_vqshls_n_u32 (uint32x1_t a) -+{ -+ return vqshls_n_u32 (a, 4); -+} -+ -+/* { dg-final { scan-assembler-times "\\tuqshl\\td\[0-9\]+" 2 } } */ -+ -+uint64x1_t -+test_vqshld_u64 (uint64x1_t a, uint64x1_t b) -+{ -+ return vqshld_u64 (a, b); -+} -+ -+uint64x1_t -+test_vqshld_n_u64 (uint64x1_t a) -+{ -+ return vqshld_n_u64 (a, 5); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqshrun\\tb\[0-9\]+" 1 } } */ -+ -+int8x1_t -+test_vqshrunh_n_s16 (int16x1_t a) -+{ -+ return vqshrunh_n_s16 (a, 2); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqshrun\\th\[0-9\]+" 1 } } */ -+ -+int16x1_t -+test_vqshruns_n_s32 (int32x1_t a) -+{ -+ return vqshruns_n_s32 (a, 3); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqshrun\\ts\[0-9\]+" 1 } } */ -+ -+int32x1_t -+test_vqshrund_n_s64 (int64x1_t a) -+{ -+ return vqshrund_n_s64 (a, 4); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqrshrun\\tb\[0-9\]+" 1 } } */ -+ -+int8x1_t -+test_vqrshrunh_n_s16 (int16x1_t a) -+{ -+ return vqrshrunh_n_s16 (a, 2); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqrshrun\\th\[0-9\]+" 1 } } */ -+ -+int16x1_t -+test_vqrshruns_n_s32 (int32x1_t a) -+{ -+ return vqrshruns_n_s32 (a, 3); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqrshrun\\ts\[0-9\]+" 1 } } */ -+ -+int32x1_t -+test_vqrshrund_n_s64 (int64x1_t a) -+{ -+ return vqrshrund_n_s64 (a, 4); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqshrn\\tb\[0-9\]+" 1 } } */ -+ -+int8x1_t -+test_vqshrnh_n_s16 (int16x1_t a) -+{ -+ return vqshrnh_n_s16 (a, 2); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqshrn\\th\[0-9\]+" 1 } } */ -+ -+int16x1_t -+test_vqshrns_n_s32 (int32x1_t a) -+{ -+ return vqshrns_n_s32 (a, 3); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqshrn\\ts\[0-9\]+" 1 } } */ -+ -+int32x1_t -+test_vqshrnd_n_s64 (int64x1_t a) -+{ -+ return vqshrnd_n_s64 (a, 4); -+} -+ -+/* { dg-final { scan-assembler-times "\\tuqshrn\\tb\[0-9\]+" 1 } } */ -+ -+uint8x1_t -+test_vqshrnh_n_u16 (uint16x1_t a) -+{ -+ return vqshrnh_n_u16 (a, 2); -+} -+ -+/* { dg-final { scan-assembler-times "\\tuqshrn\\th\[0-9\]+" 1 } } */ -+ -+uint16x1_t -+test_vqshrns_n_u32 (uint32x1_t a) -+{ -+ return vqshrns_n_u32 (a, 3); -+} -+ -+/* { dg-final { scan-assembler-times "\\tuqshrn\\ts\[0-9\]+" 1 } } */ -+ -+uint32x1_t -+test_vqshrnd_n_u64 (uint64x1_t a) -+{ -+ return vqshrnd_n_u64 (a, 4); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqrshrn\\tb\[0-9\]+" 1 } } */ -+ -+int8x1_t -+test_vqrshrnh_n_s16 (int16x1_t a) -+{ -+ return vqrshrnh_n_s16 (a, 2); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqrshrn\\th\[0-9\]+" 1 } } */ -+ -+int16x1_t -+test_vqrshrns_n_s32 (int32x1_t a) -+{ -+ return vqrshrns_n_s32 (a, 3); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqrshrn\\ts\[0-9\]+" 1 } } */ -+ -+int32x1_t -+test_vqrshrnd_n_s64 (int64x1_t a) -+{ -+ return vqrshrnd_n_s64 (a, 4); -+} -+ -+/* { dg-final { scan-assembler-times "\\tuqrshrn\\tb\[0-9\]+" 1 } } */ -+ -+uint8x1_t -+test_vqrshrnh_n_u16 (uint16x1_t a) -+{ -+ return vqrshrnh_n_u16 (a, 2); -+} -+ -+/* { dg-final { scan-assembler-times "\\tuqrshrn\\th\[0-9\]+" 1 } } */ -+ -+uint16x1_t -+test_vqrshrns_n_u32 (uint32x1_t a) -+{ -+ return vqrshrns_n_u32 (a, 3); -+} -+ -+/* { dg-final { scan-assembler-times "\\tuqrshrn\\ts\[0-9\]+" 1 } } */ -+ -+uint32x1_t -+test_vqrshrnd_n_u64 (uint64x1_t a) -+{ -+ return vqrshrnd_n_u64 (a, 4); -+} -+ -+/* { dg-final { scan-assembler-times "\\tlsl\\tx\[0-9\]+" 2 } } */ -+ -+int64x1_t -+test_vshl_n_s64 (int64x1_t a) -+{ -+ return vshld_n_s64 (a, 9); -+} -+ -+uint64x1_t -+test_vshl_n_u64 (uint64x1_t a) -+{ -+ return vshld_n_u64 (a, 9); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsli\\td\[0-9\]+" 2 } } */ -+ -+int64x1_t -+test_vsli_n_s64 (int64x1_t a, int64x1_t b) -+{ -+ return vslid_n_s64 (a, b, 9); -+} -+ -+uint64x1_t -+test_vsli_n_u64 (uint64x1_t a, uint64x1_t b) -+{ -+ return vslid_n_u64 (a, b, 9); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsri\\td\[0-9\]+" 2 } } */ -+ -+int64x1_t -+test_vsri_n_s64 (int64x1_t a, int64x1_t b) -+{ -+ return vsrid_n_s64 (a, b, 9); -+} -+ -+uint64x1_t -+test_vsri_n_u64 (uint64x1_t a, uint64x1_t b) -+{ -+ return vsrid_n_u64 (a, b, 9); -+} - -Property changes on: gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/fcvt_double_long.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/fcvt_double_long.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/fcvt_double_long.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,13 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+ -+#define GPF double -+#define SUFFIX(x) x -+#define GPI long -+ -+#include "fcvt.x" -+ -+/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, *d\[0-9\]" 2 } } */ -+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 3 } } */ -+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 3 } } */ -+/* { dg-final { scan-assembler-times "fcvtas\tx\[0-9\]+, *d\[0-9\]" 2 } } */ - -Property changes on: gcc/testsuite/gcc.target/aarch64/fcvt_double_long.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/frint_double.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/frint_double.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/frint_double.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,14 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+ -+#define GPF double -+#define SUFFIX(x) x -+ -+#include "frint.x" -+ -+/* { dg-final { scan-assembler-times "frintz\td\[0-9\]" 2 } } */ -+/* { dg-final { scan-assembler-times "frintp\td\[0-9\]" 2 } } */ -+/* { dg-final { scan-assembler-times "frintm\td\[0-9\]" 2 } } */ -+/* { dg-final { scan-assembler-times "frinti\td\[0-9\]" 2 } } */ -+/* { dg-final { scan-assembler-times "frintx\td\[0-9\]" 2 } } */ -+/* { dg-final { scan-assembler-times "frinta\td\[0-9\]" 2 } } */ - -Property changes on: gcc/testsuite/gcc.target/aarch64/frint_double.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/pic-constantpool1.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/pic-constantpool1.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/pic-constantpool1.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,30 @@ -+/* { dg-options "-O2 -mcmodel=small -fPIC" } */ -+/* { dg-do compile } */ -+ -+extern int __finite (double __value) __attribute__ ((__nothrow__)) __attribute__ ((__const__)); -+int -+__ecvt_r (value, ndigit, decpt, sign, buf, len) -+ double value; -+ int ndigit, *decpt, *sign; -+ char *buf; -+{ -+ if ((sizeof (value) == sizeof (float) ? __finitef (value) : __finite (value)) && value != 0.0) -+ { -+ double d; -+ double f = 1.0; -+ d = -value; -+ if (d < 1.0e-307) -+ { -+ do -+ { -+ f *= 10.0; -+ } -+ while (d * f < 1.0); -+ } -+ } -+ if (ndigit <= 0 && len > 0) -+ { -+ buf[0] = '\0'; -+ *sign = (sizeof (value) == sizeof (float) ? __finitef (value) : __finite (value)) ? (sizeof (value) == sizeof (float) ? __signbitf (value) : __signbit (value)) != 0 : 0; -+ } -+} - -Property changes on: gcc/testsuite/gcc.target/aarch64/pic-constantpool1.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/ffs.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/ffs.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/ffs.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,12 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+ -+unsigned int functest(unsigned int x) -+{ -+ return __builtin_ffs(x); -+} -+ -+/* { dg-final { scan-assembler "cmp\tw" } } */ -+/* { dg-final { scan-assembler "rbit\tw" } } */ -+/* { dg-final { scan-assembler "clz\tw" } } */ -+/* { dg-final { scan-assembler "csinc\tw" } } */ -Index: gcc/testsuite/gcc.target/aarch64/arch-diagnostics-1.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/arch-diagnostics-1.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/arch-diagnostics-1.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,7 @@ -+/* { dg-error "unknown" "" {target "aarch64*-*-*" } } */ -+/* { dg-options "-O2 -march=dummy" } */ -+ -+void f () -+{ -+ return; -+} - -Property changes on: gcc/testsuite/gcc.target/aarch64/arch-diagnostics-1.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/csinv-1.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/csinv-1.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/csinv-1.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,50 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+ -+unsigned int -+test_csinv32_condasn1(unsigned int w0, -+ unsigned int w1, -+ unsigned int w2, -+ unsigned int w3) { -+ unsigned int w4; -+ -+ /* { dg-final { scan-assembler "csinv\tw\[0-9\]*.*ne" } } */ -+ w4 = (w0 == w1) ? ~w3 : w2; -+ return w4; -+} -+ -+unsigned int -+test_csinv32_condasn2(unsigned int w0, -+ unsigned int w1, -+ unsigned int w2, -+ unsigned int w3) { -+ unsigned int w4; -+ -+ /* { dg-final { scan-assembler "csinv\tw\[0-9\]*.*eq" } } */ -+ w4 = (w0 == w1) ? w3 : ~w2; -+ return w4; -+} -+ -+unsigned long long -+test_csinv64_condasn1(unsigned long long x0, -+ unsigned long long x1, -+ unsigned long long x2, -+ unsigned long long x3) { -+ unsigned long long x4; -+ -+ /* { dg-final { scan-assembler "csinv\tx\[0-9\]*.*ne" } } */ -+ x4 = (x0 == x1) ? ~x3 : x2; -+ return x4; -+} -+ -+unsigned long long -+test_csinv64_condasn2(unsigned long long x0, -+ unsigned long long x1, -+ unsigned long long x2, -+ unsigned long long x3) { -+ unsigned long long x4; -+ -+ /* { dg-final { scan-assembler "csinv\tx\[0-9\]*.*eq" } } */ -+ x4 = (x0 == x1) ? x3 : ~x2; -+ return x4; -+} - -Property changes on: gcc/testsuite/gcc.target/aarch64/csinv-1.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/vmlsq_laneq.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/vmlsq_laneq.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/vmlsq_laneq.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,158 @@ -+ -+/* { dg-do run } */ -+/* { dg-options "-O3" } */ -+ -+#include "arm_neon.h" -+ -+extern void abort (void); -+ -+void -+test1 () -+{ -+ int16x8_t val1, val2, val3; -+ int16x8_t result; -+ uint64_t act, exp; -+ -+ val1 = vcombine_s16 (vcreate_s16 (UINT64_C (0xffff9ab680000000)), -+ vcreate_s16 (UINT64_C (0x00000000ffff0000))); -+ val2 = vcombine_s16 (vcreate_s16 (UINT64_C (0x32b77fffffff7fff)), -+ vcreate_s16 (UINT64_C (0x0000ffff00007fff))); -+ val3 = vcombine_s16 (vcreate_s16 (UINT64_C (0x7fff00007fff0000)), -+ vcreate_s16 (UINT64_C (0x80007fff00000000))); -+ result = vmlsq_laneq_s16 (val1, val2, val3, 6); -+ -+ act = vgetq_lane_u64 (vreinterpretq_u64_s16 (result), 0); -+ exp = UINT64_C (0xb2b69ab5ffffffff); -+ if (act != exp) -+ abort (); -+ -+ act = vgetq_lane_u64 (vreinterpretq_u64_s16 (result), 1); -+ exp = UINT64_C (0x00007fffffffffff); -+ if (act != exp) -+ abort (); -+} -+ -+void -+test2 () -+{ -+ int32x4_t val1, val2, val3; -+ int32x4_t result; -+ uint64_t exp, act; -+ -+ val1 = vcombine_s32 (vcreate_s32 (UINT64_C (0x00008000f46f7fff)), -+ vcreate_s32 (UINT64_C (0x7fffffffffff8000))); -+ val2 = vcombine_s32 (vcreate_s32 (UINT64_C (0x7fff7fff0e700000)), -+ vcreate_s32 (UINT64_C (0xffff000080000000))); -+ val3 = vcombine_s32 (vcreate_s32 (UINT64_C (0x00000000ffff0000)), -+ vcreate_s32 (UINT64_C (0xd9edea1a8000fb28))); -+ result = vmlsq_laneq_s32 (val1, val2, val3, 3); -+ -+ act = vgetq_lane_u64 (vreinterpretq_u64_s32 (result), 0); -+ exp = UINT64_C (0xcefb6a1a1d0f7fff); -+ if (act != exp) -+ abort (); -+ -+ act = vgetq_lane_u64 (vreinterpretq_u64_s32 (result), 1); -+ exp = UINT64_C (0x6a19ffffffff8000); -+ if (act != exp) -+ abort (); -+} -+ -+void -+test3 () -+{ -+ uint16x8_t val1, val2, val3; -+ uint16x8_t result; -+ uint64_t act, exp; -+ -+ val1 = vcombine_u16 (vcreate_u16 (UINT64_C (0x000080008000802a)), -+ vcreate_u16 (UINT64_C (0x7fffffff00007fff))); -+ val2 = vcombine_u16 (vcreate_u16 (UINT64_C (0x7fffcdf1ffff0000)), -+ vcreate_u16 (UINT64_C (0xe2550000ffffffff))); -+ val3 = vcombine_u16 (vcreate_u16 (UINT64_C (0x80007fff80000000)), -+ vcreate_u16 (UINT64_C (0xbe2100007fffffff))); -+ -+ result = vmlsq_laneq_u16 (val1, val2, val3, 7); -+ -+ act = vgetq_lane_u64 (vreinterpretq_u64_u16 (result), 0); -+ exp = UINT64_C (0x3e2115ef3e21802a); -+ if (act != exp) -+ abort (); -+ -+ act = vgetq_lane_u64 (vreinterpretq_u64_u16 (result), 1); -+ exp = UINT64_C (0x3d0affffbe213e20); -+ if (act != exp) -+ abort (); -+} -+ -+void -+test4 () -+{ -+ uint32x4_t val1, val2, val3; -+ uint32x4_t result; -+ uint64_t act, exp; -+ -+ val1 = vcombine_u32 (vcreate_u32 (UINT64_C (0x3295fe3d7fff7fff)), -+ vcreate_u32 (UINT64_C (0x7fff00007fff7fff))); -+ val2 = vcombine_u32 (vcreate_u32 (UINT64_C (0xffff7fff7fff8000)), -+ vcreate_u32 (UINT64_C (0x7fff80008000ffff))); -+ val3 = vcombine_u32 (vcreate_u32 (UINT64_C (0x7fff7fff80008000)), -+ vcreate_u32 (UINT64_C (0x0000800053ab7fff))); -+ -+ result = vmlsq_laneq_u32 (val1, val2, val3, 2); -+ -+ act = vgetq_lane_u64 (vreinterpretq_u64_u32 (result), 0); -+ exp = UINT64_C (0x4640fe3cbffeffff); -+ if (act != exp) -+ abort (); -+ -+ act = vgetq_lane_u64 (vreinterpretq_u64_u32 (result), 1); -+ exp = UINT64_C (0xbffe8000d3abfffe); -+ if (act != exp) -+ abort (); -+} -+ -+void -+test5 () -+{ -+ float32x4_t val1, val2, val3; -+ float32x4_t result; -+ float32_t act; -+ -+ val1 = vcombine_f32 (vcreate_f32 (UINT64_C (0x3f49daf03ef3dc73)), -+ vcreate_f32 (UINT64_C (0x3f5d467a3ef3dc73))); -+ val2 = vcombine_f32 (vcreate_f32 (UINT64_C (0x3d2064c83d10cd28)), -+ vcreate_f32 (UINT64_C (0x3ea7d1a23d10cd28))); -+ val3 = vcombine_f32 (vcreate_f32 (UINT64_C (0x3f6131993edb1e04)), -+ vcreate_f32 (UINT64_C (0x3f37f4bf3edb1e04))); -+ -+ result = vmlsq_laneq_f32 (val1, val2, val3, 0); -+ -+ act = vgetq_lane_f32 (result, 0); -+ if (act != 0.46116194128990173f) -+ abort (); -+ -+ act = vgetq_lane_f32 (result, 1); -+ if (act != 0.7717385292053223f) -+ abort (); -+ -+ act = vgetq_lane_f32 (result, 2); -+ if (act != 0.46116194128990173f) -+ abort (); -+ -+ act = vgetq_lane_f32 (result, 3); -+ if (act != 0.7240825295448303f) -+ abort (); -+} -+ -+int -+main (void) -+{ -+ test1 (); -+ test2 (); -+ test3 (); -+ test4 (); -+ test5 (); -+ -+ return 0; -+} - -Property changes on: gcc/testsuite/gcc.target/aarch64/vmlsq_laneq.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/vect-fmaxv-fminv.x -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-fmaxv-fminv.x (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fmaxv-fminv.x (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,43 @@ -+ -+typedef float *__restrict__ pRF32; -+typedef double *__restrict__ pRF64; -+ -+float maxv_f32 (pRF32 a) -+{ -+ int i; -+ float s = a[0]; -+ for (i=1;i<8;i++) -+ s = (s > a[i] ? s : a[i]); -+ -+ return s; -+} -+ -+float minv_f32 (pRF32 a) -+{ -+ int i; -+ float s = a[0]; -+ for (i=1;i<16;i++) -+ s = (s < a[i] ? s : a[i]); -+ -+ return s; -+} -+ -+double maxv_f64 (pRF64 a) -+{ -+ int i; -+ double s = a[0]; -+ for (i=1;i<8;i++) -+ s = (s > a[i] ? s : a[i]); -+ -+ return s; -+} -+ -+double minv_f64 (pRF64 a) -+{ -+ int i; -+ double s = a[0]; -+ for (i=1;i<16;i++) -+ s = (s < a[i] ? s : a[i]); -+ -+ return s; -+} -Index: gcc/testsuite/gcc.target/aarch64/vect-faddv.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-faddv.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-faddv.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,31 @@ -+ -+/* { dg-do run } */ -+/* { dg-options "-O3 -ffast-math" } */ -+ -+extern void abort (void); -+ -+#include "vect-faddv.x" -+ -+int main (void) -+{ -+ float addv_f32_value = -120.0f; -+ double addv_f64_value = 120.0; -+ float af32[16]; -+ double af64[16]; -+ int i; -+ -+ /* Set up input vectors. */ -+ for (i=0; i<16; i++) -+ { -+ af32[i] = (float)-i; -+ af64[i] = (double)i; -+ } -+ -+ if (addv_f32 (af32) != addv_f32_value) -+ abort (); -+ -+ if (addv_f64 (af64) != addv_f64_value) -+ abort (); -+ -+ return 0; -+} - -Property changes on: gcc/testsuite/gcc.target/aarch64/vect-faddv.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/fcvt.x -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/fcvt.x (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/fcvt.x (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,55 @@ -+extern GPF SUFFIX(trunc) (GPF); -+extern GPF SUFFIX(ceil) (GPF); -+extern GPF SUFFIX(floor) (GPF); -+extern GPF SUFFIX(round) (GPF); -+ -+GPI test1a (GPF x) { -+ return SUFFIX(__builtin_trunc)(x); -+} -+ -+GPI test1b (GPF x) -+{ -+ return SUFFIX(trunc)(x); -+} -+ -+GPI test2a (GPF x) -+{ -+ return SUFFIX(__builtin_lceil)(x); -+} -+ -+GPI test2b (GPF x) -+{ -+ return SUFFIX(ceil)(x); -+} -+ -+GPI test2c (GPF x) -+{ -+ return SUFFIX(__builtin_ceil)(x); -+} -+ -+GPI test3a (GPF x) -+{ -+ return SUFFIX(__builtin_lfloor)(x); -+} -+ -+GPI test3b (GPF x) -+{ -+ return SUFFIX(floor)(x); -+} -+ -+GPI test3c (GPF x) -+{ -+ return SUFFIX(__builtin_floor)(x); -+} -+ -+GPI test4a (GPF x) -+{ -+ return SUFFIX(__builtin_round)(x); -+} -+ -+GPI test4b (GPF x) -+{ -+ return SUFFIX(round)(x); -+} -+ -+ -Index: gcc/testsuite/gcc.target/aarch64/clz.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/clz.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/clz.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,9 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+ -+unsigned int functest (unsigned int x) -+{ -+ return __builtin_clz (x); -+} -+ -+/* { dg-final { scan-assembler "clz\tw" } } */ -Index: gcc/testsuite/gcc.target/aarch64/fcvt_float_ulong.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/fcvt_float_ulong.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/fcvt_float_ulong.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,15 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+ -+#define GPF float -+#define SUFFIX(x) x##f -+#define GPI unsigned long -+ -+#include "fcvt.x" -+ -+/* { dg-final { scan-assembler-times "fcvtzu\tx\[0-9\]+, *s\[0-9\]" 2 } } */ -+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 } } */ -+/* { dg-final { scan-assembler-times "fcvtpu\tx\[0-9\]+, *s\[0-9\]" 2 } } */ -+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 } } */ -+/* { dg-final { scan-assembler-times "fcvtmu\tx\[0-9\]+, *s\[0-9\]" 2 } } */ -+/* { dg-final { scan-assembler-times "fcvtau\tx\[0-9\]+, *s\[0-9\]" 2 } } */ - -Property changes on: gcc/testsuite/gcc.target/aarch64/fcvt_float_ulong.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/csneg-1.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/csneg-1.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/csneg-1.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,50 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+ -+int -+test_csneg32_condasn1(int w0, -+ int w1, -+ int w2, -+ int w3) { -+ int w4; -+ -+ /* { dg-final { scan-assembler "csneg\tw\[0-9\]*.*ne" } } */ -+ w4 = (w0 == w1) ? -w3 : w2; -+ return w4; -+} -+ -+int -+test_csneg32_condasn2(int w0, -+ int w1, -+ int w2, -+ int w3) { -+ int w4; -+ -+ /* { dg-final { scan-assembler "csneg\tw\[0-9\]*.*eq" } } */ -+ w4 = (w0 == w1) ? w3 : -w2; -+ return w4; -+} -+ -+long long -+test_csneg64_condasn1(long long x0, -+ long long x1, -+ long long x2, -+ long long x3) { -+ long long x4; -+ -+ /* { dg-final { scan-assembler "csneg\tx\[0-9\]*.*ne" } } */ -+ x4 = (x0 == x1) ? -x3 : x2; -+ return x4; -+} -+ -+long long -+test_csneg64_condasn2(long long x0, -+ long long x1, -+ long long x2, -+ long long x3) { -+ long long x4; -+ -+ /* { dg-final { scan-assembler "csneg\tx\[0-9\]*.*eq" } } */ -+ x4 = (x0 == x1) ? x3 : -x2; -+ return x4; -+} - -Property changes on: gcc/testsuite/gcc.target/aarch64/csneg-1.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/fnmadd-fastmath.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/fnmadd-fastmath.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/fnmadd-fastmath.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,19 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2 -ffast-math" } */ -+ -+extern double fma (double, double, double); -+extern float fmaf (float, float, float); -+ -+double test_fma1 (double x, double y, double z) -+{ -+ return - fma (x, y, z); -+} -+ -+float test_fma2 (float x, float y, float z) -+{ -+ return - fmaf (x, y, z); -+} -+ -+/* { dg-final { scan-assembler-times "fnmadd\td\[0-9\]" 1 } } */ -+/* { dg-final { scan-assembler-times "fnmadd\ts\[0-9\]" 1 } } */ -+ -Index: gcc/testsuite/gcc.target/aarch64/ctz.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/ctz.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/ctz.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,11 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+ -+unsigned int functest (unsigned int x) -+{ -+ return __builtin_ctz (x); -+} -+ -+/* { dg-final { scan-assembler "rbit\tw" } } */ -+/* { dg-final { scan-assembler "clz\tw" } } */ -+ -Index: gcc/testsuite/gcc.target/aarch64/aarch64.exp -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aarch64.exp (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aarch64.exp (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,45 @@ -+# Specific regression driver for AArch64. -+# Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. -+# Contributed by ARM Ltd. -+# -+# This file is part of GCC. -+# -+# GCC is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License as published by -+# the Free Software Foundation; either version 3, or (at your option) -+# any later version. -+# -+# GCC is distributed in the hope that it will be useful, but -+# WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+# General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with GCC; see the file COPYING3. If not see -+# . */ -+ -+# GCC testsuite that uses the `dg.exp' driver. -+ -+# Exit immediately if this isn't an AArch64 target. -+if {![istarget aarch64*-*-*] } then { -+ return -+} -+ -+# Load support procs. -+load_lib gcc-dg.exp -+ -+# If a testcase doesn't have special options, use these. -+global DEFAULT_CFLAGS -+if ![info exists DEFAULT_CFLAGS] then { -+ set DEFAULT_CFLAGS " -ansi -pedantic-errors" -+} -+ -+# Initialize `dg'. -+dg-init -+ -+# Main loop. -+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \ -+ "" $DEFAULT_CFLAGS -+ -+# All done. -+dg-finish -Index: gcc/testsuite/gcc.target/aarch64/frint_float.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/frint_float.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/frint_float.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,14 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+ -+#define GPF float -+#define SUFFIX(x) x##f -+ -+#include "frint.x" -+ -+/* { dg-final { scan-assembler-times "frintz\ts\[0-9\]" 2 } } */ -+/* { dg-final { scan-assembler-times "frintp\ts\[0-9\]" 2 } } */ -+/* { dg-final { scan-assembler-times "frintm\ts\[0-9\]" 2 } } */ -+/* { dg-final { scan-assembler-times "frinti\ts\[0-9\]" 2 } } */ -+/* { dg-final { scan-assembler-times "frintx\ts\[0-9\]" 2 } } */ -+/* { dg-final { scan-assembler-times "frinta\ts\[0-9\]" 2 } } */ - -Property changes on: gcc/testsuite/gcc.target/aarch64/frint_float.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/vector_intrinsics.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/vector_intrinsics.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/vector_intrinsics.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,803 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+ -+#include "../../../config/aarch64/arm_neon.h" -+ -+ -+/* { dg-final { scan-assembler-times "\\tfmax\\tv\[0-9\]+\.2s, v\[0-9\].2s, v\[0-9\].2s" 1 } } */ -+ -+float32x2_t -+test_vmax_f32 (float32x2_t __a, float32x2_t __b) -+{ -+ return vmax_f32(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsmax\\tv\[0-9\]+\.8b, v\[0-9\].8b, v\[0-9\].8b" 1 } } */ -+ -+int8x8_t -+test_vmax_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return vmax_s8(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tumax\\tv\[0-9\]+\.8b, v\[0-9\].8b, v\[0-9\].8b" 1 } } */ -+ -+uint8x8_t -+test_vmax_u8 (uint8x8_t __a, uint8x8_t __b) -+{ -+ return vmax_u8(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsmax\\tv\[0-9\]+\.4h, v\[0-9\].4h, v\[0-9\].4h" 1 } } */ -+ -+int16x4_t -+test_vmax_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return vmax_s16(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tumax\\tv\[0-9\]+\.4h, v\[0-9\].4h, v\[0-9\].4h" 1 } } */ -+ -+uint16x4_t -+test_vmax_u16 (uint16x4_t __a, uint16x4_t __b) -+{ -+ return vmax_u16(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsmax\\tv\[0-9\]+\.2s, v\[0-9\].2s, v\[0-9\].2s" 1 } } */ -+ -+int32x2_t -+test_vmax_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return vmax_s32(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tumax\\tv\[0-9\]+\.2s, v\[0-9\].2s, v\[0-9\].2s" 1 } } */ -+ -+uint32x2_t -+test_vmax_u32 (uint32x2_t __a, uint32x2_t __b) -+{ -+ return vmax_u32(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tfmax\\tv\[0-9\]+\.4s, v\[0-9\].4s, v\[0-9\].4s" 1 } } */ -+ -+float32x4_t -+test_vmaxq_f32 (float32x4_t __a, float32x4_t __b) -+{ -+ return vmaxq_f32(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tfmax\\tv\[0-9\]+\.2d, v\[0-9\].2d, v\[0-9\].2d" 1 } } */ -+ -+float64x2_t -+test_vmaxq_f64 (float64x2_t __a, float64x2_t __b) -+{ -+ return vmaxq_f64(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsmax\\tv\[0-9\]+\.16b, v\[0-9\].16b, v\[0-9\].16b" 1 } } */ -+ -+int8x16_t -+test_vmaxq_s8 (int8x16_t __a, int8x16_t __b) -+{ -+ return vmaxq_s8(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tumax\\tv\[0-9\]+\.16b, v\[0-9\].16b, v\[0-9\].16b" 1 } } */ -+ -+uint8x16_t -+test_vmaxq_u8 (uint8x16_t __a, uint8x16_t __b) -+{ -+ return vmaxq_u8(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsmax\\tv\[0-9\]+\.8h, v\[0-9\].8h, v\[0-9\].8h" 1 } } */ -+ -+int16x8_t -+test_vmaxq_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return vmaxq_s16(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tumax\\tv\[0-9\]+\.8h, v\[0-9\].8h, v\[0-9\].8h" 1 } } */ -+ -+uint16x8_t -+test_vmaxq_u16 (uint16x8_t __a, uint16x8_t __b) -+{ -+ return vmaxq_u16(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsmax\\tv\[0-9\]+\.4s, v\[0-9\].4s, v\[0-9\].4s" 1 } } */ -+ -+int32x4_t -+test_vmaxq_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return vmaxq_s32(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tumax\\tv\[0-9\]+\.4s, v\[0-9\].4s, v\[0-9\].4s" 1 } } */ -+ -+uint32x4_t -+test_vmaxq_u32 (uint32x4_t __a, uint32x4_t __b) -+{ -+ return vmaxq_u32(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tfmin\\tv\[0-9\]+\.2s, v\[0-9\].2s, v\[0-9\].2s" 1 } } */ -+ -+float32x2_t -+test_vmin_f32 (float32x2_t __a, float32x2_t __b) -+{ -+ return vmin_f32(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsmin\\tv\[0-9\]+\.8b, v\[0-9\].8b, v\[0-9\].8b" 1 } } */ -+ -+int8x8_t -+test_vmin_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return vmin_s8(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tumin\\tv\[0-9\]+\.8b, v\[0-9\].8b, v\[0-9\].8b" 1 } } */ -+ -+uint8x8_t -+test_vmin_u8 (uint8x8_t __a, uint8x8_t __b) -+{ -+ return vmin_u8(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsmin\\tv\[0-9\]+\.4h, v\[0-9\].4h, v\[0-9\].4h" 1 } } */ -+ -+int16x4_t -+test_vmin_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return vmin_s16(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tumin\\tv\[0-9\]+\.4h, v\[0-9\].4h, v\[0-9\].4h" 1 } } */ -+ -+uint16x4_t -+test_vmin_u16 (uint16x4_t __a, uint16x4_t __b) -+{ -+ return vmin_u16(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsmin\\tv\[0-9\]+\.2s, v\[0-9\].2s, v\[0-9\].2s" 1 } } */ -+ -+int32x2_t -+test_vmin_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return vmin_s32(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tumin\\tv\[0-9\]+\.2s, v\[0-9\].2s, v\[0-9\].2s" 1 } } */ -+ -+uint32x2_t -+test_vmin_u32 (uint32x2_t __a, uint32x2_t __b) -+{ -+ return vmin_u32(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tfmin\\tv\[0-9\]+\.4s, v\[0-9\].4s, v\[0-9\].4s" 1 } } */ -+ -+float32x4_t -+test_vminq_f32 (float32x4_t __a, float32x4_t __b) -+{ -+ return vminq_f32(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tfmin\\tv\[0-9\]+\.2d, v\[0-9\].2d, v\[0-9\].2d" 1 } } */ -+ -+float64x2_t -+test_vminq_f64 (float64x2_t __a, float64x2_t __b) -+{ -+ return vminq_f64(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsmin\\tv\[0-9\]+\.16b, v\[0-9\].16b, v\[0-9\].16b" 1 } } */ -+ -+int8x16_t -+test_vminq_s8 (int8x16_t __a, int8x16_t __b) -+{ -+ return vminq_s8(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tumin\\tv\[0-9\]+\.16b, v\[0-9\].16b, v\[0-9\].16b" 1 } } */ -+ -+uint8x16_t -+test_vminq_u8 (uint8x16_t __a, uint8x16_t __b) -+{ -+ return vminq_u8(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsmin\\tv\[0-9\]+\.8h, v\[0-9\].8h, v\[0-9\].8h" 1 } } */ -+ -+int16x8_t -+test_vminq_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return vminq_s16(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tumin\\tv\[0-9\]+\.8h, v\[0-9\].8h, v\[0-9\].8h" 1 } } */ -+ -+uint16x8_t -+test_vminq_u16 (uint16x8_t __a, uint16x8_t __b) -+{ -+ return vminq_u16(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsmin\\tv\[0-9\]+\.4s, v\[0-9\].4s, v\[0-9\].4s" 1 } } */ -+ -+int32x4_t -+test_vminq_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return vminq_s32(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tumin\\tv\[0-9\]+\.4s, v\[0-9\].4s, v\[0-9\].4s" 1 } } */ -+ -+uint32x4_t -+test_vminq_u32 (uint32x4_t __a, uint32x4_t __b) -+{ -+ return vminq_u32(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\taddp\\tv\[0-9\]+\.8b, v\[0-9\].8b, v\[0-9\].8b" 2 } } */ -+ -+int8x8_t -+test_vpadd_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return vpadd_s8(__a, __b); -+} -+ -+uint8x8_t -+test_vpadd_u8 (uint8x8_t __a, uint8x8_t __b) -+{ -+ return vpadd_u8(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\taddp\\tv\[0-9\]+\.4h, v\[0-9\].4h, v\[0-9\].4h" 2 } } */ -+ -+int16x4_t -+test_vpadd_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return vpadd_s16(__a, __b); -+} -+ -+uint16x4_t -+test_vpadd_u16 (uint16x4_t __a, uint16x4_t __b) -+{ -+ return vpadd_u16(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\taddp\\tv\[0-9\]+\.2s, v\[0-9\].2s, v\[0-9\].2s" 2 } } */ -+ -+int32x2_t -+test_vpadd_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return vpadd_s32(__a, __b); -+} -+ -+uint32x2_t -+test_vpadd_u32 (uint32x2_t __a, uint32x2_t __b) -+{ -+ return vpadd_u32(__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmlal\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 1 } } */ -+ -+int32x4_t -+test_vqdmlal_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c) -+{ -+ return vqdmlal_s16 (__a, __b, __c); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmlal2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */ -+ -+int32x4_t -+test_vqdmlal_high_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c) -+{ -+ return vqdmlal_high_s16 (__a, __b, __c); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmlal2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.h" 3 } } */ -+ -+int32x4_t -+test_vqdmlal_high_lane_s16 (int32x4_t a, int16x8_t b, int16x8_t c) -+{ -+ return vqdmlal_high_lane_s16 (a, b, c, 3); -+} -+ -+int32x4_t -+test_vqdmlal_high_laneq_s16 (int32x4_t a, int16x8_t b, int16x8_t c) -+{ -+ return vqdmlal_high_laneq_s16 (a, b, c, 6); -+} -+ -+int32x4_t -+test_vqdmlal_high_n_s16 (int32x4_t __a, int16x8_t __b, int16_t __c) -+{ -+ return vqdmlal_high_n_s16 (__a, __b, __c); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmlal\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.h" 3 } } */ -+ -+int32x4_t -+test_vqdmlal_lane_s16 (int32x4_t a, int16x4_t b, int16x8_t c) -+{ -+ return vqdmlal_lane_s16 (a, b, c, 3); -+} -+ -+int32x4_t -+test_vqdmlal_laneq_s16 (int32x4_t a, int16x4_t b, int16x8_t c) -+{ -+ return vqdmlal_laneq_s16 (a, b, c, 6); -+} -+ -+int32x4_t -+test_vqdmlal_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c) -+{ -+ return vqdmlal_n_s16 (__a, __b, __c); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmlal\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 1 } } */ -+ -+int64x2_t -+test_vqdmlal_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c) -+{ -+ return vqdmlal_s32 (__a, __b, __c); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmlal2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 1 } } */ -+ -+int64x2_t -+test_vqdmlal_high_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c) -+{ -+ return vqdmlal_high_s32 (__a, __b, __c); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmlal2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.s" 3 } } */ -+ -+int64x2_t -+test_vqdmlal_high_lane_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c) -+{ -+ return vqdmlal_high_lane_s32 (__a, __b, __c, 1); -+} -+ -+int64x2_t -+test_vqdmlal_high_laneq_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c) -+{ -+ return vqdmlal_high_laneq_s32 (__a, __b, __c, 3); -+} -+ -+int64x2_t -+test_vqdmlal_high_n_s32 (int64x2_t __a, int32x4_t __b, int32_t __c) -+{ -+ return vqdmlal_high_n_s32 (__a, __b, __c); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmlal\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.s" 3 } } */ -+ -+int64x2_t -+test_vqdmlal_lane_s32 (int64x2_t __a, int32x2_t __b, int32x4_t __c) -+{ -+ return vqdmlal_lane_s32 (__a, __b, __c, 1); -+} -+ -+int64x2_t -+test_vqdmlal_laneq_s32 (int64x2_t __a, int32x2_t __b, int32x4_t __c) -+{ -+ return vqdmlal_laneq_s32 (__a, __b, __c, 3); -+} -+ -+int64x2_t -+test_vqdmlal_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c) -+{ -+ return vqdmlal_n_s32 (__a, __b, __c); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmlsl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 1 } } */ -+ -+int32x4_t -+test_vqdmlsl_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c) -+{ -+ return vqdmlsl_s16 (__a, __b, __c); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmlsl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */ -+ -+int32x4_t -+test_vqdmlsl_high_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c) -+{ -+ return vqdmlsl_high_s16 (__a, __b, __c); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmlsl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.h" 3 } } */ -+ -+int32x4_t -+test_vqdmlsl_high_lane_s16 (int32x4_t a, int16x8_t b, int16x8_t c) -+{ -+ return vqdmlsl_high_lane_s16 (a, b, c, 3); -+} -+ -+int32x4_t -+test_vqdmlsl_high_laneq_s16 (int32x4_t a, int16x8_t b, int16x8_t c) -+{ -+ return vqdmlsl_high_laneq_s16 (a, b, c, 6); -+} -+ -+int32x4_t -+test_vqdmlsl_high_n_s16 (int32x4_t __a, int16x8_t __b, int16_t __c) -+{ -+ return vqdmlsl_high_n_s16 (__a, __b, __c); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmlsl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.h" 3 } } */ -+ -+int32x4_t -+test_vqdmlsl_lane_s16 (int32x4_t a, int16x4_t b, int16x8_t c) -+{ -+ return vqdmlsl_lane_s16 (a, b, c, 3); -+} -+ -+int32x4_t -+test_vqdmlsl_laneq_s16 (int32x4_t a, int16x4_t b, int16x8_t c) -+{ -+ return vqdmlsl_laneq_s16 (a, b, c, 6); -+} -+ -+int32x4_t -+test_vqdmlsl_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c) -+{ -+ return vqdmlsl_n_s16 (__a, __b, __c); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmlsl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 1 } } */ -+ -+int64x2_t -+test_vqdmlsl_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c) -+{ -+ return vqdmlsl_s32 (__a, __b, __c); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmlsl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 1 } } */ -+ -+int64x2_t -+test_vqdmlsl_high_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c) -+{ -+ return vqdmlsl_high_s32 (__a, __b, __c); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmlsl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.s" 3 } } */ -+ -+int64x2_t -+test_vqdmlsl_high_lane_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c) -+{ -+ return vqdmlsl_high_lane_s32 (__a, __b, __c, 1); -+} -+ -+int64x2_t -+test_vqdmlsl_high_laneq_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c) -+{ -+ return vqdmlsl_high_laneq_s32 (__a, __b, __c, 3); -+} -+ -+int64x2_t -+test_vqdmlsl_high_n_s32 (int64x2_t __a, int32x4_t __b, int32_t __c) -+{ -+ return vqdmlsl_high_n_s32 (__a, __b, __c); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmlsl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.s" 3 } } */ -+ -+int64x2_t -+test_vqdmlsl_lane_s32 (int64x2_t __a, int32x2_t __b, int32x4_t __c) -+{ -+ return vqdmlsl_lane_s32 (__a, __b, __c, 1); -+} -+ -+int64x2_t -+test_vqdmlsl_laneq_s32 (int64x2_t __a, int32x2_t __b, int32x4_t __c) -+{ -+ return vqdmlsl_laneq_s32 (__a, __b, __c, 3); -+} -+ -+int64x2_t -+test_vqdmlsl_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c) -+{ -+ return vqdmlsl_n_s32 (__a, __b, __c); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmull\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 1 } } */ -+ -+int32x4_t -+test_vqdmull_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return vqdmull_s16 (__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmull2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */ -+ -+int32x4_t -+test_vqdmull_high_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return vqdmull_high_s16 (__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmull2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.h" 3 } } */ -+ -+int32x4_t -+test_vqdmull_high_lane_s16 (int16x8_t a, int16x8_t b) -+{ -+ return vqdmull_high_lane_s16 (a, b, 3); -+} -+ -+int32x4_t -+test_vqdmull_high_laneq_s16 (int16x8_t a, int16x8_t b) -+{ -+ return vqdmull_high_laneq_s16 (a, b, 6); -+} -+ -+int32x4_t -+test_vqdmull_high_n_s16 (int16x8_t __a, int16_t __b) -+{ -+ return vqdmull_high_n_s16 (__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmull\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.h" 3 } } */ -+ -+int32x4_t -+test_vqdmull_lane_s16 (int16x4_t a, int16x8_t b) -+{ -+ return vqdmull_lane_s16 (a, b, 3); -+} -+ -+int32x4_t -+test_vqdmull_laneq_s16 (int16x4_t a, int16x8_t b) -+{ -+ return vqdmull_laneq_s16 (a, b, 6); -+} -+ -+int32x4_t -+test_vqdmull_n_s16 (int16x4_t __a, int16_t __b) -+{ -+ return vqdmull_n_s16 (__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmull\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 1 } } */ -+ -+int64x2_t -+test_vqdmull_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return vqdmull_s32 (__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmull2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 1 } } */ -+ -+int64x2_t -+test_vqdmull_high_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return vqdmull_high_s32 (__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmull2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.s" 3 } } */ -+ -+int64x2_t -+test_vqdmull_high_lane_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return vqdmull_high_lane_s32 (__a, __b, 1); -+} -+ -+int64x2_t -+test_vqdmull_high_laneq_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return vqdmull_high_laneq_s32 (__a, __b, 3); -+} -+ -+int64x2_t -+test_vqdmull_high_n_s32 (int32x4_t __a, int32_t __b) -+{ -+ return vqdmull_high_n_s32 (__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsqdmull\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.s" 3 } } */ -+ -+int64x2_t -+test_vqdmull_lane_s32 (int32x2_t __a, int32x4_t __b) -+{ -+ return vqdmull_lane_s32 (__a, __b, 1); -+} -+ -+int64x2_t -+test_vqdmull_laneq_s32 (int32x2_t __a, int32x4_t __b) -+{ -+ return vqdmull_laneq_s32 (__a, __b, 1); -+} -+ -+int64x2_t -+test_vqdmull_n_s32 (int32x2_t __a, int32_t __b) -+{ -+ return vqdmull_n_s32 (__a, __b); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsshll\\tv\[0-9\]+\.2d" 1 } } */ -+ -+int64x2_t -+test_vshll_n_s32 (int32x2_t __a) -+{ -+ return vshll_n_s32 (__a, 9); -+} -+ -+/* { dg-final { scan-assembler-times "\\tushll\\tv\[0-9\]+\.2d" 1 } } */ -+ -+uint64x2_t -+test_vshll_n_u32 (uint32x2_t __a) -+{ -+ return vshll_n_u32 (__a, 9); -+} -+ -+/* { dg-final { scan-assembler-times "\\tshll\\tv\[0-9\]+\.2d" 2 } } */ -+ -+int64x2_t -+test_vshll_n_s32_2 (int32x2_t __a) -+{ -+ return vshll_n_s32 (__a, 32); -+} -+ -+uint64x2_t -+test_vshll_n_u32_2 (uint32x2_t __a) -+{ -+ return vshll_n_u32 (__a, 32); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsshll\\tv\[0-9\]+\.4s" 1 } } */ -+ -+int32x4_t -+test_vshll_n_s16 (int16x4_t __a) -+{ -+ return vshll_n_s16 (__a, 3); -+} -+ -+/* { dg-final { scan-assembler-times "\\tushll\\tv\[0-9\]+\.4s" 1 } } */ -+ -+uint32x4_t -+test_vshll_n_u16 (uint16x4_t __a) -+{ -+ return vshll_n_u16 (__a, 3); -+} -+ -+/* { dg-final { scan-assembler-times "\\tshll\\tv\[0-9\]+\.4s" 2 } } */ -+ -+int32x4_t -+test_vshll_n_s16_2 (int16x4_t __a) -+{ -+ return vshll_n_s16 (__a, 16); -+} -+ -+uint32x4_t -+test_vshll_n_u16_2 (uint16x4_t __a) -+{ -+ return vshll_n_u16 (__a, 16); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsshll\\tv\[0-9\]+\.8h" 1 } } */ -+ -+int16x8_t -+test_vshll_n_s8 (int8x8_t __a) -+{ -+ return vshll_n_s8 (__a, 3); -+} -+ -+/* { dg-final { scan-assembler-times "\\tushll\\tv\[0-9\]+\.8h" 1 } } */ -+ -+uint16x8_t -+test_vshll_n_u8 (uint8x8_t __a) -+{ -+ return vshll_n_u8 (__a, 3); -+} -+ -+/* { dg-final { scan-assembler-times "\\tshll\\tv\[0-9\]+\.8h" 2 } } */ -+ -+int16x8_t -+test_vshll_n_s8_2 (int8x8_t __a) -+{ -+ return vshll_n_s8 (__a, 8); -+} -+ -+uint16x8_t -+test_vshll_n_u8_2 (uint8x8_t __a) -+{ -+ return vshll_n_u8 (__a, 8); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsshll2\\tv\[0-9\]+\.2d" 1 } } */ -+ -+int64x2_t -+test_vshll_high_n_s32 (int32x4_t __a) -+{ -+ return vshll_high_n_s32 (__a, 9); -+} -+ -+/* { dg-final { scan-assembler-times "\\tushll2\\tv\[0-9\]+\.2d" 1 } } */ -+ -+uint64x2_t -+test_vshll_high_n_u32 (uint32x4_t __a) -+{ -+ return vshll_high_n_u32 (__a, 9); -+} -+ -+/* { dg-final { scan-assembler-times "\\tshll2\\tv\[0-9\]+\.2d" 2 } } */ -+ -+int64x2_t -+test_vshll_high_n_s32_2 (int32x4_t __a) -+{ -+ return vshll_high_n_s32 (__a, 32); -+} -+ -+uint64x2_t -+test_vshll_high_n_u32_2 (uint32x4_t __a) -+{ -+ return vshll_high_n_u32 (__a, 32); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsshll2\\tv\[0-9\]+\.4s" 1 } } */ -+ -+int32x4_t -+test_vshll_high_n_s16 (int16x8_t __a) -+{ -+ return vshll_high_n_s16 (__a, 3); -+} -+ -+/* { dg-final { scan-assembler-times "\\tushll2\\tv\[0-9\]+\.4s" 1 } } */ -+ -+uint32x4_t -+test_vshll_high_n_u16 (uint16x8_t __a) -+{ -+ return vshll_high_n_u16 (__a, 3); -+} -+ -+/* { dg-final { scan-assembler-times "\\tshll2\\tv\[0-9\]+\.4s" 2 } } */ -+ -+int32x4_t -+test_vshll_high_n_s16_2 (int16x8_t __a) -+{ -+ return vshll_high_n_s16 (__a, 16); -+} -+ -+uint32x4_t -+test_vshll_high_n_u16_2 (uint16x8_t __a) -+{ -+ return vshll_high_n_u16 (__a, 16); -+} -+ -+/* { dg-final { scan-assembler-times "\\tsshll2\\tv\[0-9\]+\.8h" 1 } } */ -+ -+int16x8_t -+test_vshll_high_n_s8 (int8x16_t __a) -+{ -+ return vshll_high_n_s8 (__a, 3); -+} -+ -+/* { dg-final { scan-assembler-times "\\tushll2\\tv\[0-9\]+\.8h" 1 } } */ -+ -+uint16x8_t -+test_vshll_high_n_u8 (uint8x16_t __a) -+{ -+ return vshll_high_n_u8 (__a, 3); -+} -+ -+/* { dg-final { scan-assembler-times "\\tshll2\\tv\[0-9\]+\.8h" 2 } } */ -+ -+int16x8_t -+test_vshll_high_n_s8_2 (int8x16_t __a) -+{ -+ return vshll_high_n_s8 (__a, 8); -+} -+ -+uint16x8_t -+test_vshll_high_n_u8_2 (uint8x16_t __a) -+{ -+ return vshll_high_n_u8 (__a, 8); -+} - -Property changes on: gcc/testsuite/gcc.target/aarch64/vector_intrinsics.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/vect-faddv.x -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-faddv.x (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-faddv.x (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,23 @@ -+ -+typedef float *__restrict__ pRF32; -+typedef double *__restrict__ pRF64; -+ -+float addv_f32 (pRF32 a) -+{ -+ int i; -+ float s = 0.0; -+ for (i=0; i<16; i++) -+ s += a[i]; -+ -+ return s; -+} -+ -+double addv_f64 (pRF64 a) -+{ -+ int i; -+ double s = 0.0; -+ for (i=0; i<16; i++) -+ s += a[i]; -+ -+ return s; -+} -Index: gcc/testsuite/gcc.target/aarch64/table-intrinsics.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/table-intrinsics.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/table-intrinsics.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,439 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O3" } */ -+ -+#include "arm_neon.h" -+ -+int8x8_t -+tbl_tests8_ (int8x8_t tab, int8x8_t idx) -+{ -+ return vtbl1_s8 (tab, idx); -+} -+ -+uint8x8_t -+tbl_testu8_ (uint8x8_t tab, uint8x8_t idx) -+{ -+ return vtbl1_u8 (tab, idx); -+} -+ -+poly8x8_t -+tbl_testp8_ (poly8x8_t tab, uint8x8_t idx) -+{ -+ return vtbl1_p8 (tab, idx); -+} -+ -+int8x8_t -+tbl_tests8_2 (int8x8x2_t tab, int8x8_t idx) -+{ -+ return vtbl2_s8 (tab, idx); -+} -+ -+uint8x8_t -+tbl_testu8_2 (uint8x8x2_t tab, uint8x8_t idx) -+{ -+ return vtbl2_u8 (tab, idx); -+} -+ -+poly8x8_t -+tbl_testp8_2 (poly8x8x2_t tab, uint8x8_t idx) -+{ -+ return vtbl2_p8 (tab, idx); -+} -+ -+int8x8_t -+tbl_tests8_3 (int8x8x3_t tab, int8x8_t idx) -+{ -+ return vtbl3_s8 (tab, idx); -+} -+ -+uint8x8_t -+tbl_testu8_3 (uint8x8x3_t tab, uint8x8_t idx) -+{ -+ return vtbl3_u8 (tab, idx); -+} -+ -+poly8x8_t -+tbl_testp8_3 (poly8x8x3_t tab, uint8x8_t idx) -+{ -+ return vtbl3_p8 (tab, idx); -+} -+ -+int8x8_t -+tbl_tests8_4 (int8x8x4_t tab, int8x8_t idx) -+{ -+ return vtbl4_s8 (tab, idx); -+} -+ -+uint8x8_t -+tbl_testu8_4 (uint8x8x4_t tab, uint8x8_t idx) -+{ -+ return vtbl4_u8 (tab, idx); -+} -+ -+poly8x8_t -+tbl_testp8_4 (poly8x8x4_t tab, uint8x8_t idx) -+{ -+ return vtbl4_p8 (tab, idx); -+} -+ -+int8x8_t -+tb_tests8_ (int8x8_t r, int8x8_t tab, int8x8_t idx) -+{ -+ return vtbx1_s8 (r, tab, idx); -+} -+ -+uint8x8_t -+tb_testu8_ (uint8x8_t r, uint8x8_t tab, uint8x8_t idx) -+{ -+ return vtbx1_u8 (r, tab, idx); -+} -+ -+poly8x8_t -+tb_testp8_ (poly8x8_t r, poly8x8_t tab, uint8x8_t idx) -+{ -+ return vtbx1_p8 (r, tab, idx); -+} -+ -+int8x8_t -+tb_tests8_2 (int8x8_t r, int8x8x2_t tab, int8x8_t idx) -+{ -+ return vtbx2_s8 (r, tab, idx); -+} -+ -+uint8x8_t -+tb_testu8_2 (uint8x8_t r, uint8x8x2_t tab, uint8x8_t idx) -+{ -+ return vtbx2_u8 (r, tab, idx); -+} -+ -+poly8x8_t -+tb_testp8_2 (poly8x8_t r, poly8x8x2_t tab, uint8x8_t idx) -+{ -+ return vtbx2_p8 (r, tab, idx); -+} -+ -+int8x8_t -+tb_tests8_3 (int8x8_t r, int8x8x3_t tab, int8x8_t idx) -+{ -+ return vtbx3_s8 (r, tab, idx); -+} -+ -+uint8x8_t -+tb_testu8_3 (uint8x8_t r, uint8x8x3_t tab, uint8x8_t idx) -+{ -+ return vtbx3_u8 (r, tab, idx); -+} -+ -+poly8x8_t -+tb_testp8_3 (poly8x8_t r, poly8x8x3_t tab, uint8x8_t idx) -+{ -+ return vtbx3_p8 (r, tab, idx); -+} -+ -+int8x8_t -+tb_tests8_4 (int8x8_t r, int8x8x4_t tab, int8x8_t idx) -+{ -+ return vtbx4_s8 (r, tab, idx); -+} -+ -+uint8x8_t -+tb_testu8_4 (uint8x8_t r, uint8x8x4_t tab, uint8x8_t idx) -+{ -+ return vtbx4_u8 (r, tab, idx); -+} -+ -+poly8x8_t -+tb_testp8_4 (poly8x8_t r, poly8x8x4_t tab, uint8x8_t idx) -+{ -+ return vtbx4_p8 (r, tab, idx); -+} -+ -+int8x8_t -+qtbl_tests8_ (int8x16_t tab, int8x8_t idx) -+{ -+ return vqtbl1_s8 (tab, idx); -+} -+ -+uint8x8_t -+qtbl_testu8_ (uint8x16_t tab, uint8x8_t idx) -+{ -+ return vqtbl1_u8 (tab, idx); -+} -+ -+poly8x8_t -+qtbl_testp8_ (poly8x16_t tab, uint8x8_t idx) -+{ -+ return vqtbl1_p8 (tab, idx); -+} -+ -+int8x8_t -+qtbl_tests8_2 (int8x16x2_t tab, int8x8_t idx) -+{ -+ return vqtbl2_s8 (tab, idx); -+} -+ -+uint8x8_t -+qtbl_testu8_2 (uint8x16x2_t tab, uint8x8_t idx) -+{ -+ return vqtbl2_u8 (tab, idx); -+} -+ -+poly8x8_t -+qtbl_testp8_2 (poly8x16x2_t tab, uint8x8_t idx) -+{ -+ return vqtbl2_p8 (tab, idx); -+} -+ -+int8x8_t -+qtbl_tests8_3 (int8x16x3_t tab, int8x8_t idx) -+{ -+ return vqtbl3_s8 (tab, idx); -+} -+ -+uint8x8_t -+qtbl_testu8_3 (uint8x16x3_t tab, uint8x8_t idx) -+{ -+ return vqtbl3_u8 (tab, idx); -+} -+ -+poly8x8_t -+qtbl_testp8_3 (poly8x16x3_t tab, uint8x8_t idx) -+{ -+ return vqtbl3_p8 (tab, idx); -+} -+ -+int8x8_t -+qtbl_tests8_4 (int8x16x4_t tab, int8x8_t idx) -+{ -+ return vqtbl4_s8 (tab, idx); -+} -+ -+uint8x8_t -+qtbl_testu8_4 (uint8x16x4_t tab, uint8x8_t idx) -+{ -+ return vqtbl4_u8 (tab, idx); -+} -+ -+poly8x8_t -+qtbl_testp8_4 (poly8x16x4_t tab, uint8x8_t idx) -+{ -+ return vqtbl4_p8 (tab, idx); -+} -+ -+int8x8_t -+qtb_tests8_ (int8x8_t r, int8x16_t tab, int8x8_t idx) -+{ -+ return vqtbx1_s8 (r, tab, idx); -+} -+ -+uint8x8_t -+qtb_testu8_ (uint8x8_t r, uint8x16_t tab, uint8x8_t idx) -+{ -+ return vqtbx1_u8 (r, tab, idx); -+} -+ -+poly8x8_t -+qtb_testp8_ (poly8x8_t r, poly8x16_t tab, uint8x8_t idx) -+{ -+ return vqtbx1_p8 (r, tab, idx); -+} -+ -+int8x8_t -+qtb_tests8_2 (int8x8_t r, int8x16x2_t tab, int8x8_t idx) -+{ -+ return vqtbx2_s8 (r, tab, idx); -+} -+ -+uint8x8_t -+qtb_testu8_2 (uint8x8_t r, uint8x16x2_t tab, uint8x8_t idx) -+{ -+ return vqtbx2_u8 (r, tab, idx); -+} -+ -+poly8x8_t -+qtb_testp8_2 (poly8x8_t r, poly8x16x2_t tab, uint8x8_t idx) -+{ -+ return vqtbx2_p8 (r, tab, idx); -+} -+ -+int8x8_t -+qtb_tests8_3 (int8x8_t r, int8x16x3_t tab, int8x8_t idx) -+{ -+ return vqtbx3_s8 (r, tab, idx); -+} -+ -+uint8x8_t -+qtb_testu8_3 (uint8x8_t r, uint8x16x3_t tab, uint8x8_t idx) -+{ -+ return vqtbx3_u8 (r, tab, idx); -+} -+ -+poly8x8_t -+qtb_testp8_3 (poly8x8_t r, poly8x16x3_t tab, uint8x8_t idx) -+{ -+ return vqtbx3_p8 (r, tab, idx); -+} -+ -+int8x8_t -+qtb_tests8_4 (int8x8_t r, int8x16x4_t tab, int8x8_t idx) -+{ -+ return vqtbx4_s8 (r, tab, idx); -+} -+ -+uint8x8_t -+qtb_testu8_4 (uint8x8_t r, uint8x16x4_t tab, uint8x8_t idx) -+{ -+ return vqtbx4_u8 (r, tab, idx); -+} -+ -+poly8x8_t -+qtb_testp8_4 (poly8x8_t r, poly8x16x4_t tab, uint8x8_t idx) -+{ -+ return vqtbx4_p8 (r, tab, idx); -+} -+ -+int8x16_t -+qtblq_tests8_ (int8x16_t tab, int8x16_t idx) -+{ -+ return vqtbl1q_s8 (tab, idx); -+} -+ -+uint8x16_t -+qtblq_testu8_ (uint8x16_t tab, uint8x16_t idx) -+{ -+ return vqtbl1q_u8 (tab, idx); -+} -+ -+poly8x16_t -+qtblq_testp8_ (poly8x16_t tab, uint8x16_t idx) -+{ -+ return vqtbl1q_p8 (tab, idx); -+} -+ -+int8x16_t -+qtblq_tests8_2 (int8x16x2_t tab, int8x16_t idx) -+{ -+ return vqtbl2q_s8 (tab, idx); -+} -+ -+uint8x16_t -+qtblq_testu8_2 (uint8x16x2_t tab, uint8x16_t idx) -+{ -+ return vqtbl2q_u8 (tab, idx); -+} -+ -+poly8x16_t -+qtblq_testp8_2 (poly8x16x2_t tab, uint8x16_t idx) -+{ -+ return vqtbl2q_p8 (tab, idx); -+} -+ -+int8x16_t -+qtblq_tests8_3 (int8x16x3_t tab, int8x16_t idx) -+{ -+ return vqtbl3q_s8 (tab, idx); -+} -+ -+uint8x16_t -+qtblq_testu8_3 (uint8x16x3_t tab, uint8x16_t idx) -+{ -+ return vqtbl3q_u8 (tab, idx); -+} -+ -+poly8x16_t -+qtblq_testp8_3 (poly8x16x3_t tab, uint8x16_t idx) -+{ -+ return vqtbl3q_p8 (tab, idx); -+} -+ -+int8x16_t -+qtblq_tests8_4 (int8x16x4_t tab, int8x16_t idx) -+{ -+ return vqtbl4q_s8 (tab, idx); -+} -+ -+uint8x16_t -+qtblq_testu8_4 (uint8x16x4_t tab, uint8x16_t idx) -+{ -+ return vqtbl4q_u8 (tab, idx); -+} -+ -+poly8x16_t -+qtblq_testp8_4 (poly8x16x4_t tab, uint8x16_t idx) -+{ -+ return vqtbl4q_p8 (tab, idx); -+} -+ -+int8x16_t -+qtbxq_tests8_ (int8x16_t r, int8x16_t tab, int8x16_t idx) -+{ -+ return vqtbx1q_s8 (r, tab, idx); -+} -+ -+uint8x16_t -+qtbxq_testu8_ (uint8x16_t r, uint8x16_t tab, uint8x16_t idx) -+{ -+ return vqtbx1q_u8 (r, tab, idx); -+} -+ -+poly8x16_t -+qtbxq_testp8_ (poly8x16_t r, poly8x16_t tab, uint8x16_t idx) -+{ -+ return vqtbx1q_p8 (r, tab, idx); -+} -+ -+int8x16_t -+qtbxq_tests8_2 (int8x16_t r, int8x16x2_t tab, int8x16_t idx) -+{ -+ return vqtbx2q_s8 (r, tab, idx); -+} -+ -+uint8x16_t -+qtbxq_testu8_2 (uint8x16_t r, uint8x16x2_t tab, uint8x16_t idx) -+{ -+ return vqtbx2q_u8 (r, tab, idx); -+} -+ -+poly8x16_t -+qtbxq_testp8_2 (poly8x16_t r, poly8x16x2_t tab, uint8x16_t idx) -+{ -+ return vqtbx2q_p8 (r, tab, idx); -+} -+ -+int8x16_t -+qtbxq_tests8_3 (int8x16_t r, int8x16x3_t tab, int8x16_t idx) -+{ -+ return vqtbx3q_s8 (r, tab, idx); -+} -+ -+uint8x16_t -+qtbxq_testu8_3 (uint8x16_t r, uint8x16x3_t tab, uint8x16_t idx) -+{ -+ return vqtbx3q_u8 (r, tab, idx); -+} -+ -+poly8x16_t -+qtbxq_testp8_3 (poly8x16_t r, poly8x16x3_t tab, uint8x16_t idx) -+{ -+ return vqtbx3q_p8 (r, tab, idx); -+} -+ -+int8x16_t -+qtbxq_tests8_4 (int8x16_t r, int8x16x4_t tab, int8x16_t idx) -+{ -+ return vqtbx4q_s8 (r, tab, idx); -+} -+ -+uint8x16_t -+qtbxq_testu8_4 (uint8x16_t r, uint8x16x4_t tab, uint8x16_t idx) -+{ -+ return vqtbx4q_u8 (r, tab, idx); -+} -+ -+poly8x16_t -+qtbxq_testp8_4 (poly8x16_t r, poly8x16x4_t tab, uint8x16_t idx) -+{ -+ return vqtbx4q_p8 (r, tab, idx); -+} -+ -+/* { dg-final { scan-assembler-times "tbl v" 42} } */ -+/* { dg-final { scan-assembler-times "tbx v" 30} } */ - -Property changes on: gcc/testsuite/gcc.target/aarch64/table-intrinsics.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/reload-valid-spoff.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/reload-valid-spoff.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/reload-valid-spoff.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,66 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2 -mcmodel=large -fno-builtin" } */ -+/* { dg-skip-if "-mcmodel=large -fPIC not currently supported" { aarch64-*-* } { "-fPIC" } { "" } } */ -+ -+typedef long unsigned int size_t; -+typedef unsigned short int sa_family_t; -+ -+struct sockaddr -+{ -+ sa_family_t sa_family; -+ char sa_data[14]; -+}; -+struct arpreq -+{ -+ int arp_flags; -+ struct sockaddr arp_netmask; -+}; -+typedef struct _IO_FILE FILE; -+extern char *fgets (char *__restrict __s, int __n, FILE *__restrict __stream); -+extern struct _IO_FILE *stderr; -+extern int optind; -+struct aftype { -+ int (*input) (int type, char *bufp, struct sockaddr *); -+}; -+struct aftype *ap; -+static int arp_set(char **args) -+{ -+ char host[128]; -+ struct arpreq req; -+ struct sockaddr sa; -+ memset((char *) &req, 0, sizeof(req)); -+ if (*args == ((void *)0)) { -+ fprintf(stderr, ("arp: need host name\n")); -+ } -+ safe_strncpy(host, *args++, (sizeof host)); -+ if (ap->input(0, host, &sa) < 0) { -+ } -+ while (*args != ((void *)0)) { -+ if (!__extension__ ({ size_t __s1_len, __s2_len; (__builtin_constant_p (*args) && __builtin_constant_p ("netmask") && (__s1_len = strlen (*args), __s2_len = strlen ("netmask"), (!((size_t)(const void *)((*args) + 1) - (size_t)(const void *)(*args) == 1) || __s1_len >= 4) && (!((size_t)(const void *)(("netmask") + 1) - (size_t)(const void *)("netmask") == 1) || __s2_len >= 4)) ? __builtin_strcmp (*args, "netmask") : (__builtin_constant_p (*args) && ((size_t)(const void *)((*args) + 1) - (size_t)(const void *)(*args) == 1) && (__s1_len = strlen (*args), __s1_len < 4) ? (__builtin_constant_p ("netmask") && ((size_t)(const void *)(("netmask") + 1) - (size_t)(const void *)("netmask") == 1) ? __builtin_strcmp (*args, "netmask") : (__extension__ ({ __const unsigned char *__s2 = (__const unsigned char *) (__const char *) ("netmask"); register int __result = (((__const unsigned char *) (__const char *) (*args))[0] - __s2[0]); if (__s1_len > 0 && __result == 0) { __result = (((__const unsigned char *) (__const char *) (*args))[1] - __s2[1]); if (__s1_len > 1 && __result == 0) { __result = (((__const unsigned char *) (__const char *) (*args))[2] - __s2[2]); if (__s1_len > 2 && __result == 0) __result = (((__const unsigned char *) (__const char *) (*args))[3] - __s2[3]); } } __result; }))) : (__builtin_constant_p ("netmask") && ((size_t)(const void *)(("netmask") + 1) - (size_t)(const void *)("netmask") == 1) && (__s2_len = strlen ("netmask"), __s2_len < 4) ? (__builtin_constant_p (*args) && ((size_t)(const void *)((*args) + 1) - (size_t)(const void *)(*args) == 1) ? __builtin_strcmp (*args, "netmask") : (__extension__ ({ __const unsigned char *__s1 = (__const unsigned char *) (__const char *) (*args); register int __result = __s1[0] - ((__const unsigned char *) (__const char *) ("netmask"))[0]; if (__s2_len > 0 && __result == 0) { __result = (__s1[1] - ((__const unsigned char *) (__const char *) ("netmask"))[1]); if (__s2_len > 1 && __result == 0) { __result = (__s1[2] - ((__const unsigned char *) (__const char *) ("netmask"))[2]); if (__s2_len > 2 && __result == 0) __result = (__s1[3] - ((__const unsigned char *) (__const char *) ("netmask"))[3]); } } __result; }))) : __builtin_strcmp (*args, "netmask")))); })) { -+ if (__extension__ ({ size_t __s1_len, __s2_len; (__builtin_constant_p (*args) && __builtin_constant_p ("255.255.255.255") && (__s1_len = strlen (*args), __s2_len = strlen ("255.255.255.255"), (!((size_t)(const void *)((*args) + 1) - (size_t)(const void *)(*args) == 1) || __s1_len >= 4) && (!((size_t)(const void *)(("255.255.255.255") + 1) - (size_t)(const void *)("255.255.255.255") == 1) || __s2_len >= 4)) ? __builtin_strcmp (*args, "255.255.255.255") : (__builtin_constant_p (*args) && ((size_t)(const void *)((*args) + 1) - (size_t)(const void *)(*args) == 1) && (__s1_len = strlen (*args), __s1_len < 4) ? (__builtin_constant_p ("255.255.255.255") && ((size_t)(const void *)(("255.255.255.255") + 1) - (size_t)(const void *)("255.255.255.255") == 1) ? __builtin_strcmp (*args, "255.255.255.255") : (__extension__ ({ __const unsigned char *__s2 = (__const unsigned char *) (__const char *) ("255.255.255.255"); register int __result = (((__const unsigned char *) (__const char *) (*args))[0] - __s2[0]); if (__s1_len > 0 && __result == 0) { __result = (((__const unsigned char *) (__const char *) (*args))[1] - __s2[1]); if (__s1_len > 1 && __result == 0) { __result = (((__const unsigned char *) (__const char *) (*args))[2] - __s2[2]); if (__s1_len > 2 && __result == 0) __result = (((__const unsigned char *) (__const char *) (*args))[3] - __s2[3]); } } __result; }))) : (__builtin_constant_p ("255.255.255.255") && ((size_t)(const void *)(("255.255.255.255") + 1) - (size_t)(const void *)("255.255.255.255") == 1) && (__s2_len = strlen ("255.255.255.255"), __s2_len < 4) ? (__builtin_constant_p (*args) && ((size_t)(const void *)((*args) + 1) - (size_t)(const void *)(*args) == 1) ? __builtin_strcmp (*args, "255.255.255.255") : (__extension__ ({ __const unsigned char *__s1 = (__const unsigned char *) (__const char *) (*args); register int __result = __s1[0] - ((__const unsigned char *) (__const char *) ("255.255.255.255"))[0]; if (__s2_len > 0 && __result == 0) { __result = (__s1[1] - ((__const unsigned char *) (__const char *) ("255.255.255.255"))[1]); if (__s2_len > 1 && __result == 0) { __result = (__s1[2] - ((__const unsigned char *) (__const char *) ("255.255.255.255"))[2]); if (__s2_len > 2 && __result == 0) __result = (__s1[3] - ((__const unsigned char *) (__const char *) ("255.255.255.255"))[3]); } } __result; }))) : __builtin_strcmp (*args, "255.255.255.255")))); }) != 0) { -+ memcpy((char *) &req.arp_netmask, (char *) &sa, -+ sizeof(struct sockaddr)); -+ } -+ } -+ } -+} -+static int arp_file(char *name) -+{ -+ char buff[1024]; -+ char *sp, *args[32]; -+ int linenr, argc; -+ FILE *fp; -+ while (fgets(buff, sizeof(buff), fp) != (char *) ((void *)0)) { -+ if (arp_set(args) != 0) -+ fprintf(stderr, ("arp: cannot set entry on line %u on line %u of etherfile %s !\n"), -+ linenr, name); -+ } -+} -+int main(int argc, char **argv) -+{ -+ int i, lop, what; -+ switch (what) { -+ case 0: -+ what = arp_file(argv[optind] ? argv[optind] : "/etc/ethers"); -+ } -+} - -Property changes on: gcc/testsuite/gcc.target/aarch64/reload-valid-spoff.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/asm-1.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/asm-1.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/asm-1.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,15 @@ -+ -+/* { dg-do compile } */ -+/* { dg-options "-O3" } */ -+ -+typedef struct -+{ -+ int i; -+ int y; -+} __attribute__ ((aligned (16))) struct64_t; -+ -+void foo () -+{ -+ struct64_t tmp; -+ asm volatile ("ldr q0, %[value]" : : [value]"m"(tmp)); -+} - -Property changes on: gcc/testsuite/gcc.target/aarch64/asm-1.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/vsqrt.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/vsqrt.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/vsqrt.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,66 @@ -+ -+ -+/* { dg-do run } */ -+/* { dg-options "-O3" } */ -+ -+#include "arm_neon.h" -+#include "stdio.h" -+ -+extern void abort (void); -+ -+void -+test_square_root_v2sf () -+{ -+ float32x2_t val = {4.0f, 9.0f}; -+ float32x2_t res; -+ -+ res = vsqrt_f32 (val); -+ -+ if (vget_lane_f32 (res, 0) != 2.0f) -+ abort (); -+ if (vget_lane_f32 (res, 1) != 3.0f) -+ abort (); -+} -+ -+void -+test_square_root_v4sf () -+{ -+ float32x4_t val = {4.0f, 9.0f, 16.0f, 25.0f}; -+ float32x4_t res; -+ -+ res = vsqrtq_f32 (val); -+ -+ if (vgetq_lane_f32 (res, 0) != 2.0f) -+ abort (); -+ if (vgetq_lane_f32 (res, 1) != 3.0f) -+ abort (); -+ if (vgetq_lane_f32 (res, 2) != 4.0f) -+ abort (); -+ if (vgetq_lane_f32 (res, 3) != 5.0f) -+ abort (); -+} -+ -+void -+test_square_root_v2df () -+{ -+ float64x2_t val = {4.0, 9.0}; -+ float64x2_t res; -+ -+ res = vsqrtq_f64 (val); -+ -+ if (vgetq_lane_f64 (res, 0) != 2.0) -+ abort (); -+ -+ if (vgetq_lane_f64 (res, 1) != 3.0) -+ abort (); -+} -+ -+int -+main (void) -+{ -+ test_square_root_v2sf (); -+ test_square_root_v4sf (); -+ test_square_root_v2df (); -+ -+ return 0; -+} - -Property changes on: gcc/testsuite/gcc.target/aarch64/vsqrt.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/volatile-bitfields-2.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/volatile-bitfields-2.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/volatile-bitfields-2.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,17 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+ -+typedef struct { -+ volatile unsigned long a:8; -+ volatile unsigned long b:8; -+ volatile unsigned long c:16; -+} BitStruct; -+ -+BitStruct bits; -+ -+unsigned long foo () -+{ -+ return bits.b; -+} -+ -+/* { dg-final { scan-assembler "ldr\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" } } */ - -Property changes on: gcc/testsuite/gcc.target/aarch64/volatile-bitfields-2.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/pic-symrefplus.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/pic-symrefplus.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/pic-symrefplus.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,128 @@ -+/* { dg-options "-O2 -mcmodel=small -fPIC -fno-builtin" } */ -+/* { dg-do compile } */ -+ -+typedef long unsigned int size_t; -+enum -+{ -+ __LC_TIME = 2, -+}; -+enum -+{ -+ ABDAY_1 = (((__LC_TIME) << 16) | (0)), -+ DAY_1, -+ ABMON_1, -+ MON_1, -+ D_T_FMT, -+}; -+typedef struct __locale_struct -+{ -+ struct locale_data *__locales[13]; -+} *__locale_t; -+struct tm -+{ -+ int tm_sec; -+ int tm_min; -+ int tm_hour; -+}; -+struct locale_data -+{ -+ const char *name; -+ struct -+ { -+ const char *string; -+ } -+ values []; -+}; -+extern const struct locale_data _nl_C_LC_TIME __attribute__ ((visibility ("hidden"))); -+char * -+__strptime_internal (rp, fmt, tmp, statep , locale) -+ const char *rp; -+ const char *fmt; -+ __locale_t locale; -+ void *statep; -+{ -+ struct locale_data *const current = locale->__locales[__LC_TIME]; -+ const char *rp_backup; -+ const char *rp_longest; -+ int cnt; -+ size_t val; -+ enum ptime_locale_status { not, loc, raw } decided_longest; -+ struct __strptime_state -+ { -+ enum ptime_locale_status decided : 2; -+ } s; -+ struct tm tmb; -+ struct tm *tm; -+ if (statep == ((void *)0)) -+ { -+ memset (&s, 0, sizeof (s)); -+ } -+ { -+ tm = &tmb; -+ } -+ while (*fmt != '\0') -+ { -+ if (*fmt != '%') -+ { -+ if (*fmt++ != *rp++) return ((void *)0); -+ continue; -+ } -+ if (statep != ((void *)0)) -+ { -+ ++fmt; -+ } -+ rp_backup = rp; -+ switch (*fmt++) -+ { -+ case '%': -+ for (cnt = 0; cnt < 7; ++cnt) -+ { -+ const char *trp; -+ if (s.decided !=raw) -+ { -+ if (({ size_t len = strlen ((current->values[((int) (DAY_1 + cnt) & 0xffff)].string)); int result = __strncasecmp_l (((current->values[((int) (DAY_1 + cnt) & 0xffff)].string)), (trp), len, locale) == 0; if (result) (trp) += len; result; }) -+ && trp > rp_longest) -+ { -+ } -+ if (({ size_t len = strlen ((current->values[((int) (ABDAY_1 + cnt) & 0xffff)].string)); int result = __strncasecmp_l (((current->values[((int) (ABDAY_1 + cnt) & 0xffff)].string)), (trp), len, locale) == 0; if (result) (trp) += len; result; }) -+ && trp > rp_longest) -+ { -+ } -+ } -+ if (s.decided != loc -+ && (((trp = rp, ({ size_t len = strlen ((&_nl_C_LC_TIME.values[((int) (DAY_1) & 0xffff)].string)[cnt]); int result = __strncasecmp_l (((&_nl_C_LC_TIME.values[((int) (DAY_1) & 0xffff)].string)[cnt]), (trp), len, locale) == 0; if (result) (trp) += len; result; })) -+ && trp > rp_longest) -+ || ((trp = rp, ({ size_t len = strlen ((&_nl_C_LC_TIME.values[((int) (ABDAY_1) & 0xffff)].string)[cnt]); int result = __strncasecmp_l (((&_nl_C_LC_TIME.values[((int) (ABDAY_1) & 0xffff)].string)[cnt]), (rp), len, locale) == 0; if (result) (rp) += len; result; })) -+ && trp > rp_longest))) -+ { -+ } -+ } -+ { -+ const char *trp; -+ if (s.decided != loc -+ && (((trp = rp, ({ size_t len = strlen ((&_nl_C_LC_TIME.values[((int) (MON_1) & 0xffff)].string)[cnt]); int result = __strncasecmp_l (((&_nl_C_LC_TIME.values[((int) (MON_1) & 0xffff)].string)[cnt]), (trp), len, locale) == 0; if (result) (trp) += len; result; })) -+ && trp > rp_longest) -+ || ((trp = rp, ({ size_t len = strlen ((&_nl_C_LC_TIME.values[((int) (ABMON_1) & 0xffff)].string)[cnt]); int result = __strncasecmp_l (((&_nl_C_LC_TIME.values[((int) (ABMON_1) & 0xffff)].string)[cnt]), (trp), len, locale) == 0; if (result) (trp) += len; result; })) -+ && trp > rp_longest))) -+ { -+ } -+ } -+ case 'c': -+ { -+ if (!(*((current->values[((int) (D_T_FMT) & 0xffff)].string)) != '\0' && (rp = __strptime_internal (rp, ((current->values[((int) (D_T_FMT) & 0xffff)].string)), tm, &s , locale)) != ((void *)0))) -+ { -+ rp = rp_backup; -+ } -+ } -+ case 'C': -+ do { int __n = 2; val = 0; while (*rp == ' ') ++rp; if (*rp < '0' || *rp > '9') return ((void *)0); do { val *= 10; val += *rp++ - '0'; } while (--__n > 0 && val * 10 <= 99 && *rp >= '0' && *rp <= '9'); if (val < 0 || val > 99) return ((void *)0); } while (0); -+ case 'F': -+ if (!(*("%Y-%m-%d") != '\0' && (rp = __strptime_internal (rp, ("%Y-%m-%d"), tm, &s , locale)) != ((void *)0))) -+ tm->tm_hour = val % 12; -+ } -+ } -+} -+char * -+__strptime_l (buf, format, tm , locale) -+{ -+} - -Property changes on: gcc/testsuite/gcc.target/aarch64/pic-symrefplus.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/adc-1.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/adc-1.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/adc-1.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,18 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+ -+volatile unsigned int w0, w1, w2, w3, w4; -+volatile int result; -+ -+void test_si() { -+ /* { dg-final { scan-assembler "adc\tw\[0-9\]*, w\[0-9\]*, w\[0-9\]*\n" } } */ -+ w0 = w1 + w2 + (w3 >= w4); -+} -+ -+volatile unsigned long long int x0, x1, x2, x3, x4; -+ -+void test_di() { -+ /* { dg-final { scan-assembler "adc\tx\[0-9\]*, x\[0-9\]*, x\[0-9\]*\n" } } */ -+ x0 = x1 + x2 + (x3 >= x4); -+} -+ - -Property changes on: gcc/testsuite/gcc.target/aarch64/adc-1.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/mneg-2.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/mneg-2.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/mneg-2.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,10 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+ -+int r; -+ -+void test (int a, int b) -+{ -+ /* { dg-final { scan-assembler "mneg\tw\[0-9\]*, w\[0-9\]*, w\[0-9\]*\n" } } */ -+ r = a * (-b); -+} - -Property changes on: gcc/testsuite/gcc.target/aarch64/mneg-2.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/vect-compile.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-compile.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-compile.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,20 @@ -+ -+/* { dg-do compile } */ -+/* { dg-options "-O3" } */ -+ -+#include "vect.x" -+ -+/* { dg-final { scan-assembler "orn\\tv" } } */ -+/* { dg-final { scan-assembler "bic\\tv" } } */ -+/* { dg-final { scan-assembler "mla\\tv" } } */ -+/* { dg-final { scan-assembler "mls\\tv" } } */ -+/* { dg-final { scan-assembler "smax\\tv" } } */ -+/* { dg-final { scan-assembler "smin\\tv" } } */ -+/* { dg-final { scan-assembler "umax\\tv" } } */ -+/* { dg-final { scan-assembler "umin\\tv" } } */ -+/* { dg-final { scan-assembler "umaxv" } } */ -+/* { dg-final { scan-assembler "uminv" } } */ -+/* { dg-final { scan-assembler "smaxv" } } */ -+/* { dg-final { scan-assembler "sminv" } } */ -+/* { dg-final { scan-assembler-times "addv" 2} } */ -+/* { dg-final { scan-assembler-times "addp" 2} } */ - -Property changes on: gcc/testsuite/gcc.target/aarch64/vect-compile.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-1.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-1.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-1.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,7 @@ -+/* { dg-error "unknown" "" {target "aarch64*-*-*" } } */ -+/* { dg-options "-O2 -mcpu=dummy" } */ -+ -+void f () -+{ -+ return; -+} - -Property changes on: gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-1.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/vect-abs-compile.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-abs-compile.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-abs-compile.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,12 @@ -+ -+/* { dg-do compile } */ -+/* { dg-options "-O3" } */ -+ -+#define N 16 -+ -+#include "vect-abs.x" -+ -+/* { dg-final { scan-assembler "abs\\tv\[0-9\]+\.16b" } } */ -+/* { dg-final { scan-assembler "abs\\tv\[0-9\]+\.8h" } } */ -+/* { dg-final { scan-assembler "abs\\tv\[0-9\]+\.4s" } } */ -+/* { dg-final { scan-assembler "abs\\tv\[0-9\]+\.2d" } } */ - -Property changes on: gcc/testsuite/gcc.target/aarch64/vect-abs-compile.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,13 @@ -+ -+ -+/* { dg-do compile } */ -+/* { dg-options "-O3" } */ -+ -+#include "vect-fp.x" -+ -+/* { dg-final { scan-assembler "fadd\\tv" } } */ -+/* { dg-final { scan-assembler "fsub\\tv" } } */ -+/* { dg-final { scan-assembler "fmul\\tv" } } */ -+/* { dg-final { scan-assembler "fdiv\\tv" } } */ -+/* { dg-final { scan-assembler "fneg\\tv" } } */ -+/* { dg-final { scan-assembler "fabs\\tv" } } */ - -Property changes on: gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-3.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-3.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-3.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,7 @@ -+/* { dg-error "unknown" "" {target "aarch64*-*-*" } } */ -+/* { dg-options "-O2 -mcpu=example-1+dummy" } */ -+ -+void f () -+{ -+ return; -+} - -Property changes on: gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-3.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/vect-mull-compile.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-mull-compile.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-mull-compile.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,16 @@ -+ -+/* { dg-do compile } */ -+/* { dg-options "-O3" } */ -+ -+#define N 16 -+ -+#include "vect-mull.x" -+ -+DEF_MULL2 (DEF_MULLB) -+DEF_MULL2 (DEF_MULLH) -+DEF_MULL2 (DEF_MULLS) -+ -+/* { dg-final { scan-assembler-times "smull v" 3 } } */ -+/* { dg-final { scan-assembler-times "smull2 v" 3 } } */ -+/* { dg-final { scan-assembler-times "umull v" 3 } } */ -+/* { dg-final { scan-assembler-times "umull2 v" 3 } } */ - -Property changes on: gcc/testsuite/gcc.target/aarch64/vect-mull-compile.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/fcvt_double_ulong.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/fcvt_double_ulong.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/fcvt_double_ulong.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,15 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+ -+#define GPF double -+#define SUFFIX(x) x -+#define GPI unsigned long -+ -+#include "fcvt.x" -+ -+/* { dg-final { scan-assembler-times "fcvtzu\tx\[0-9\]+, *d\[0-9\]" 2 } } */ -+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 } } */ -+/* { dg-final { scan-assembler-times "fcvtpu\tx\[0-9\]+, *d\[0-9\]" 2 } } */ -+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 } } */ -+/* { dg-final { scan-assembler-times "fcvtmu\tx\[0-9\]+, *d\[0-9\]" 2 } } */ -+/* { dg-final { scan-assembler-times "fcvtau\tx\[0-9\]+, *d\[0-9\]" 2 } } */ - -Property changes on: gcc/testsuite/gcc.target/aarch64/fcvt_double_ulong.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/mnegl-1.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/mnegl-1.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/mnegl-1.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,16 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+ -+long long r; -+ -+void test_signed (int a, int b) -+{ -+ /* { dg-final { scan-assembler "smnegl\tx\[0-9\]*, w\[0-9\]*, w\[0-9\]*\n" } } */ -+ r = (-((long long) a)) * ((long long) b); -+} -+ -+void test_unsigned (unsigned int a, unsigned int b) -+{ -+ /* { dg-final { scan-assembler "umnegl\tx\[0-9\]*, w\[0-9\]*, w\[0-9\]*\n" } } */ -+ r = (-((long long) a)) * ((long long) b); -+} - -Property changes on: gcc/testsuite/gcc.target/aarch64/mnegl-1.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/clrsb.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/clrsb.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/clrsb.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,9 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+ -+unsigned int functest (unsigned int x) -+{ -+ return __builtin_clrsb (x); -+} -+ -+/* { dg-final { scan-assembler "cls\tw" } } */ -Index: gcc/testsuite/gcc.target/aarch64/index.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/index.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/index.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,111 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+/* { dg-final { scan-assembler-not "\[us\]xtw\t" } } */ -+/* { dg-final { scan-assembler-not "\[us\]bfiz\t" } } */ -+/* { dg-final { scan-assembler-not "lsl\t" } } */ -+ -+int -+load_scaled_sxtw (int *arr, int i) -+{ -+ return arr[arr[i]]; -+} -+ -+unsigned int -+load_scaled_uxtw (unsigned int *arr, unsigned int i) -+{ -+ return arr[arr[i]]; -+} -+ -+void -+store_scaled_sxtw (int *arr, int i) -+{ -+ arr[arr[i]] = 0; -+} -+ -+void -+store_scaled_uxtw (unsigned int *arr, unsigned int i) -+{ -+ arr[arr[i]] = 0; -+} -+ -+int -+load_unscaled_sxtw (signed char *arr, int i) -+{ -+ return arr[arr[i]]; -+} -+ -+unsigned int -+load_unscaled_uxtw (unsigned char *arr, unsigned int i) -+{ -+ return arr[arr[i]]; -+} -+ -+void -+store_unscaled_sxtw (signed char *arr, int i) -+{ -+ arr[arr[i]] = 0; -+} -+ -+void -+store_unscaled_uxtw (unsigned char *arr, unsigned int i) -+{ -+ arr[arr[i]] = 0; -+} -+ -+ -+ -+int -+load_scaled_tmp_sxtw (int *arr, int i) -+{ -+ int j = arr[i]; -+ return arr[j]; -+} -+ -+unsigned int -+load_scaled_tmp_uxtw (unsigned int *arr, unsigned int i) -+{ -+ unsigned int j = arr[i]; -+ return arr[j]; -+} -+ -+void -+store_scaled_tmp_sxtw (int *arr, int i) -+{ -+ int j = arr[i]; -+ arr[j] = 0; -+} -+ -+void -+store_scaled_tmp_uxtw (unsigned int *arr, unsigned int i) -+{ -+ unsigned int j = arr[i]; -+ arr[j] = 0; -+} -+ -+int -+load_unscaled_tmp_sxtw (signed char *arr, int i) -+{ -+ signed char j = arr[i]; -+ return arr[j]; -+} -+ -+unsigned int -+load_unscaled_tmp_uxtw (unsigned char *arr, unsigned int i) -+{ -+ unsigned char j = arr[i]; -+ return arr[j]; -+} -+ -+void -+store_unscaled_tmp_sxtw (signed char *arr, int i) -+{ -+ signed char j = arr[i]; -+ arr[j] = 0; -+} -+ -+void -+store_unscaled_tmp_uxtw (unsigned char *arr, unsigned int i) -+{ -+ unsigned char j = arr[i]; -+ arr[j] = 0; -+} - -Property changes on: gcc/testsuite/gcc.target/aarch64/index.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin-compile.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin-compile.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin-compile.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,7 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O3 -ffast-math" } */ -+ -+#include "vect-fmax-fmin.x" -+ -+/* { dg-final { scan-assembler "fmaxnm\\tv" } } */ -+/* { dg-final { scan-assembler "fminnm\\tv" } } */ - -Property changes on: gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin-compile.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/arch-diagnostics-2.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/arch-diagnostics-2.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/arch-diagnostics-2.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,7 @@ -+/* { dg-error "missing" "" {target "aarch64*-*-*" } } */ -+/* { dg-options "-O2 -march=+dummy" } */ -+ -+void f () -+{ -+ return; -+} - -Property changes on: gcc/testsuite/gcc.target/aarch64/arch-diagnostics-2.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/vect-fmaxv-fminv-compile.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-fmaxv-fminv-compile.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fmaxv-fminv-compile.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,10 @@ -+ -+/* { dg-do compile } */ -+/* { dg-options "-O3 -ffast-math" } */ -+ -+#include "vect-fmaxv-fminv.x" -+ -+/* { dg-final { scan-assembler "fminnmv" } } */ -+/* { dg-final { scan-assembler "fmaxnmv" } } */ -+/* { dg-final { scan-assembler "fminnmp" } } */ -+/* { dg-final { scan-assembler "fmaxnmp" } } */ - -Property changes on: gcc/testsuite/gcc.target/aarch64/vect-fmaxv-fminv-compile.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/vfp-1.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/vfp-1.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/vfp-1.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,109 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+ -+extern float fabsf (float); -+extern float sqrtf (float); -+extern double fabs (double); -+extern double sqrt (double); -+ -+volatile float f1, f2, f3; -+volatile int cond1, cond2; -+ -+void test_sf() { -+ /* abssf2 */ -+ /* { dg-final { scan-assembler "fabs\ts\[0-9\]*" } } */ -+ f1 = fabsf (f1); -+ /* negsf2 */ -+ /* { dg-final { scan-assembler "fneg\ts\[0-9\]*" } } */ -+ f1 = -f1; -+ /* addsf3 */ -+ /* { dg-final { scan-assembler "fadd\ts\[0-9\]*" } } */ -+ f1 = f2 + f3; -+ /* subsf3 */ -+ /* { dg-final { scan-assembler "fsub\ts\[0-9\]*" } } */ -+ f1 = f2 - f3; -+ /* divsf3 */ -+ /* { dg-final { scan-assembler "fdiv\ts\[0-9\]*" } } */ -+ f1 = f2 / f3; -+ /* mulsf3 */ -+ /* { dg-final { scan-assembler "fmul\ts\[0-9\]*" } } */ -+ f1 = f2 * f3; -+ /* sqrtsf2 */ -+ /* { dg-final { scan-assembler "fsqrt\ts\[0-9\]*" } } */ -+ f1 = sqrtf (f1); -+ /* cmpsf */ -+ /* { dg-final { scan-assembler "fcmp\ts\[0-9\]*" } } */ -+ if (f1 < f2) -+ cond1 = 1; -+ else -+ cond2 = 1; -+} -+ -+volatile double d1, d2, d3; -+ -+void test_df() { -+ /* absdf2 */ -+ /* { dg-final { scan-assembler "fabs\td\[0-9\]*" } } */ -+ d1 = fabs (d1); -+ /* negdf2 */ -+ /* { dg-final { scan-assembler "fneg\td\[0-9\]*" } } */ -+ d1 = -d1; -+ /* adddf3 */ -+ /* { dg-final { scan-assembler "fadd\td\[0-9\]*" } } */ -+ d1 = d2 + d3; -+ /* subdf3 */ -+ /* { dg-final { scan-assembler "fsub\td\[0-9\]*" } } */ -+ d1 = d2 - d3; -+ /* divdf3 */ -+ /* { dg-final { scan-assembler "fdiv\td\[0-9\]*" } } */ -+ d1 = d2 / d3; -+ /* muldf3 */ -+ /* { dg-final { scan-assembler "fmul\td\[0-9\]*" } } */ -+ d1 = d2 * d3; -+ /* sqrtdf2 */ -+ /* { dg-final { scan-assembler "fsqrt\td\[0-9\]*" } } */ -+ d1 = sqrt (d1); -+ /* cmpdf */ -+ /* { dg-final { scan-assembler "fcmp\td\[0-9\]*" } } */ -+ if (d1 < d2) -+ cond1 = 1; -+ else -+ cond2 = 1; -+} -+ -+volatile int i1; -+volatile unsigned int u1; -+ -+void test_convert () { -+ /* extendsfdf2 */ -+ /* { dg-final { scan-assembler "fcvt\td\[0-9\]*" } } */ -+ d1 = f1; -+ /* truncdfsf2 */ -+ /* { dg-final { scan-assembler "fcvt\ts\[0-9\]*" } } */ -+ f1 = d1; -+ /* fixsfsi2 */ -+ /* { dg-final { scan-assembler "fcvtzs\tw\[0-9\], s\[0-9\]*" } } */ -+ i1 = f1; -+ /* fixdfsi2 */ -+ /* { dg-final { scan-assembler "fcvtzs\tw\[0-9\], d\[0-9\]*" } } */ -+ i1 = d1; -+ /* fixunsfsi2 */ -+ /* { dg-final { scan-assembler "fcvtzu\tw\[0-9\], s\[0-9\]*" } } */ -+ u1 = f1; -+ /* fixunsdfsi2 */ -+ /* { dg-final { scan-assembler "fcvtzu\tw\[0-9\], d\[0-9\]*" } } */ -+ u1 = d1; -+ /* floatsisf2 */ -+ /* { dg-final { scan-assembler "scvtf\ts\[0-9\]*" } } */ -+ f1 = i1; -+ /* floatsidf2 */ -+ /* { dg-final { scan-assembler "scvtf\td\[0-9\]*" } } */ -+ d1 = i1; -+ /* floatunssisf2 */ -+ /* { dg-final { scan-assembler "ucvtf\ts\[0-9\]*" } } */ -+ f1 = u1; -+ /* floatunssidf2 */ -+ /* { dg-final { scan-assembler "ucvtf\td\[0-9\]*" } } */ -+ d1 = u1; -+} -+ - -Property changes on: gcc/testsuite/gcc.target/aarch64/vfp-1.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/arg-type-diagnostics-1.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/arg-type-diagnostics-1.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/arg-type-diagnostics-1.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,15 @@ -+/* { dg-do compile { target { aarch64*-*-* } } } */ -+/* { dg-options "-O2" } */ -+ -+#include "arm_neon.h" -+ -+void foo () -+{ -+ int a; -+ int32x2_t arg1; -+ int32x2_t arg2; -+ int32x2_t result; -+ arg1 = vcreate_s32 (UINT64_C (0x0000ffffffffffff)); -+ arg2 = vcreate_s32 (UINT64_C (0x16497fffffffffff)); -+ result = __builtin_aarch64_srsra_nv2si (arg1, arg2, a); /* { dg-error "incompatible type for argument" } */ -+} - -Property changes on: gcc/testsuite/gcc.target/aarch64/arg-type-diagnostics-1.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/vect.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/vect.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,93 @@ -+ -+/* { dg-do run } */ -+/* { dg-options "-O3" } */ -+ -+#include "vect.x" -+ -+extern void abort (void); -+ -+void set_vector (int *a, int n) -+{ -+ int i; -+ for (i=0; i<16; i++) -+ a[i] = n; -+} -+ -+void check_vector (pRINT c, pRINT result, char *str) -+{ -+ int i; -+ for (i=0; i<16 ; i++) -+ if (c[i] != result[i]) -+ abort (); -+} -+ -+#define TEST(func, sign) set_vector (sign##c, 0); \ -+ func (sign##a, sign##b, sign##c); \ -+ check_vector (sign##c, func##_vector, #func); -+ -+ -+#define TESTV(func, sign) \ -+ if (func (sign##a) != func##_value) \ -+ abort (); -+ -+#define TESTVLL(func, sign) \ -+ if (func (ll##sign##a) != func##_value) \ -+ abort (); -+ -+int main (void) -+{ -+ int sa[16]; -+ int sb[16]; -+ int sc[16]; -+ unsigned int ua[16]; -+ unsigned int ub[16]; -+ unsigned int uc[16]; -+ long long llsa[16]; -+ unsigned long long llua[16]; -+ int i; -+ -+ /* Table of standard values to compare against. */ -+ unsigned int test_bic_vector[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; -+ unsigned int test_orn_vector[] = {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}; -+ int mla_vector[] = {0, 1, 4, 9, 16, 25, 36, 49, 64, 81, 100, 121, 144, 169, 196, 225}; -+ int mls_vector[] = {0, -1, -4, -9, -16, -25, -36, -49, -64, -81, -100, -121, -144, -169, -196, -225}; -+ int smax_vector[] = {0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15}; -+ int smin_vector[] = {0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15}; -+ unsigned int umax_vector[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}; -+ unsigned int umin_vector[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}; -+ int reduce_smax_value = 0; -+ int reduce_smin_value = -15; -+ unsigned int reduce_umax_value = 15; -+ unsigned int reduce_umin_value = 0; -+ unsigned int reduce_add_u32_value = 120; -+ int reduce_add_s32_value = -120; -+ long long reduce_add_s64_value = -120; -+ unsigned long long reduce_add_u64_value = 120; -+ -+ /* Set up input vectors. */ -+ for (i=0; i < 16; i++) -+ { -+ sa[i] = sb[i] = -i; -+ llsa[i] = (long long)-i; -+ ua[i] = ub[i] = i; -+ llua[i] = (unsigned long long)i; -+ } -+ -+ TEST (test_bic, s); -+ TEST (test_orn, s); -+ TEST (mla, s); -+ TEST (mls, s); -+ TEST (smax, s); -+ TEST (smin, s); -+ TEST (umax, u); -+ TEST (umin, u); -+ TESTV (reduce_smax, s); -+ TESTV (reduce_smin, s); -+ TESTV (reduce_umax, u); -+ TESTV (reduce_umin, u); -+ TESTV (reduce_add_u32, u); -+ TESTV (reduce_add_s32, s); -+ TESTVLL (reduce_add_u64, u); -+ TESTVLL (reduce_add_s64, s); -+ return 0; -+} - -Property changes on: gcc/testsuite/gcc.target/aarch64/vect.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/vect-abs.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-abs.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-abs.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,131 @@ -+ -+/* { dg-do run } */ -+/* { dg-options "-O3" } */ -+ -+#include "limits.h" -+ -+extern void abort (void); -+ -+#define N 16 -+ -+#include "vect-abs.x" -+ -+#define SET_VEC(size, type) void set_vector_##size (pRINT##size a) \ -+ { \ -+ int i; \ -+ for (i=0; i> (32 - size)) - i); \ -+ c[i] = (type)((INT_MAX >> (32 - size)) - i * 2); \ -+ } \ -+ } -+ -+#define CHECK_VEC(size, sign) void check_vector_##sign##size (pR##sign##INT##size a, \ -+ pR##sign##INT##size b) \ -+ { \ -+ int i; \ -+ for (i=0; i. */ -+ -+#ifndef VALIDATE_MEMORY_H -+#define VALIDATE_MEMORY_H -+ -+enum structure_type -+{ -+ flat = 0, -+ i32in128, -+ f32in64, -+ i8in64, -+ i16in64, -+ i32in64, -+}; -+ -+/* Some explicit declarations as I can't include files outside the testsuite. -+ */ -+typedef long unsigned int size_t; -+int memcmp (void *, void *, size_t); -+ -+/* These two arrays contain element size and block size data for the enumeration -+ above. */ -+const int element_size[] = { 1, 4, 4, 1, 2, 4 }; -+const int block_reverse_size[] = { 1, 16, 8, 8, 8, 8 }; -+ -+int -+validate_memory (void *mem1, char *mem2, size_t size, enum structure_type type) -+{ -+ /* In big-endian mode, the data in mem2 will have been byte-reversed in -+ register sized groups, while the data in mem1 will have been byte-reversed -+ according to the true structure of the data. To compare them, we need to -+ compare chunks of data in reverse order. -+ -+ This is only implemented for homogeneous data layouts at the moment. For -+ hetrogeneous structures a custom compare case will need to be written. */ -+ -+ unsigned int i; -+ char *cmem1 = (char *) mem1; -+ switch (type) -+ { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ case i8in64: -+ case i16in64: -+ case i32in64: -+ case f32in64: -+ case i32in128: -+ for (i = 0; i < size; i += element_size[type]) -+ { -+ if (memcmp (cmem1 + i, -+ mem2 + block_reverse_size[type] - i - element_size[type], -+ element_size[type])) -+ return 1; -+ } -+ return 0; -+ break; -+#endif -+ default: -+ break; -+ } -+ return memcmp (mem1, mem2, size); -+} -+ -+#endif /* VALIDATE_MEMORY_H. */ - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/validate_memory.h -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/test_17.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_17.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_17.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,37 @@ -+/* Test AAPCS layout (VFP variant) */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define VFP -+#define TESTFILE "test_17.c" -+ -+__complex__ x = 1.0+2.0i; -+ -+struct y -+{ -+ int p; -+ int q; -+ int r; -+ int s; -+} v = { 1, 2, 3, 4 }; -+ -+struct z -+{ -+ double x[4]; -+}; -+ -+float f1 = 25.0; -+struct z a = { 5.0, 6.0, 7.0, 8.0 }; -+struct z b = { 9.0, 10.0, 11.0, 12.0 }; -+ -+#include "abitest.h" -+#else -+ ARG(double, 11.0, D0) -+ DOTS -+ ANON(struct z, a, D1) -+ ANON(struct z, b, STACK) -+ ANON(int , 5, W0) -+ ANON(double, f1, STACK+32) -+ LAST_ANON(double, 0.5, STACK+40) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/test_17.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-1.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-1.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-1.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,126 @@ -+/* Test AAPCS64 layout. -+ -+ Test the comformance to the alignment and padding requirements. -+ -+ B.4 If the argument type is a Composite Type then the size of the -+ argument is rounded up to the nearest multiple of 8 bytes. -+ C.4 If the argument is an HFA, a Quad-precision Floating-point or Short -+ Vector Type then the NSAA is rounded up to the larger of 8 or the -+ Natural Alignment of the argument's type. -+ C.12 The NSAA is rounded up to the larger of 8 or the Natural Alignment -+ of the argument's type. -+ C.14 If the size of the argument is less than 8 bytes then the size of -+ the argument is set ot 8 bytes. The effect is as if the argument -+ was copied to the least significant bits of a 64-bit register and -+ the remaining bits filled with unspecified values. */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define TESTFILE "test_align-1.c" -+#include "type-def.h" -+ -+struct y -+{ -+ int p; -+ int q; -+ int r; -+ int s; -+}; -+ -+struct y v1 = { 1, 2, 3, 4 }; -+struct y v2 = { 5, 6, 7, 8 }; -+struct y v3 = { 9, 10, 11, 12 }; -+struct y v4 = { 13, 14, 15, 16 }; -+ -+struct z -+{ -+ double x[4]; -+}; -+ -+struct z a = { 5.0, 6.0, 7.0, 8.0 }; -+struct z b = { 9.0, 10.0, 11.0, 12.0 }; -+ -+vf4_t c = { 13.f, 14.f, 15.f, 16.f }; -+ -+struct x -+{ -+ vf4_t v; -+} w; -+ -+char ch='a'; -+short sh=13; -+int i=14; -+long long ll=15; -+ -+struct s1 -+{ -+ short sh[3]; -+} s1; -+ -+struct s2 -+{ -+ int i[2]; -+ char c; -+} s2; -+ -+struct ldx2_t -+{ -+ long double ld[2]; -+} ldx2 = { 12345.67890L, 23456.78901L }; -+ -+union u_t -+{ -+ long double ld; -+ double d[2]; -+} u; -+ -+#define HAS_DATA_INIT_FUNC -+void init_data () -+{ -+ w.v = (vf4_t){ 17.f, 18.f, 19.f, 20.f }; -+ s1.sh[0] = 16; -+ s1.sh[1] = 17; -+ s1.sh[2] = 18; -+ s2.i[0] = 19; -+ s2.i[1] = 20; -+ s2.c = 21; -+ u.ld = 34567.89012L; -+} -+ -+#include "abitest.h" -+#else -+ -+ ARG(struct y, v1, X0) -+ ARG(struct y, v2, X2) -+ ARG(struct y, v3, X4) -+ ARG(struct y, v4, X6) -+ ARG(struct z, a, D0) -+ ARG(struct z, b, D4) -+ ARG(double, 12.5, STACK) -+ ARG(vf4_t, c, STACK+16) /* [C.4] 16-byte aligned short vector */ -+ ARG(double, 17.0, STACK+32) -+ ARG(struct x, w, STACK+48) /* [C.12] 16-byte aligned small struct */ -+#ifndef __AAPCS64_BIG_ENDIAN__ -+ ARG(char, ch, STACK+64) /* [C.14] char padded to the size of 8 bytes */ -+ ARG(short, sh, STACK+72) /* [C.14] short padded to the size of 8 bytes */ -+ ARG(int, i, STACK+80) /* [C.14] int padded to the size of 8 bytes */ -+#else -+ ARG(char, ch, STACK+71) -+ ARG(short, sh, STACK+78) -+ ARG(int, i, STACK+84) -+#endif -+ ARG(long long, ll, STACK+88) -+ ARG(struct s1, s1, STACK+96) /* [B.4] small struct padded to the size of 8 bytes */ -+ ARG(double, 18.0, STACK+104) -+ ARG(struct s2, s2, STACK+112) /* [B.4] small struct padded to the size of 16 bytes */ -+ ARG(double, 19.0, STACK+128) -+ ARG(long double, 30.0L, STACK+144) /* [C.4] 16-byte aligned quad-precision */ -+ ARG(double, 31.0, STACK+160) -+ ARG(struct ldx2_t, ldx2, STACK+176) /* [C.4] 16-byte aligned HFA */ -+ ARG(double, 32.0, STACK+208) -+ ARG(__int128, 33, STACK+224) /* [C.12] 16-byte aligned 128-bit integer */ -+ ARG(double, 34.0, STACK+240) -+ ARG(union u_t, u, STACK+256) /* [C.12] 16-byte aligned small composite (union in this case) */ -+ LAST_ARG_NONFLAT (int, 35.0, STACK+272, i32in64) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-1.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/test_18.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_18.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_18.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,34 @@ -+/* Test AAPCS layout (VFP variant) */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+ -+#define TESTFILE "test_18.c" -+ -+ -+struct y -+{ -+ long p; -+ long q; -+ long r; -+ long s; -+} v = { 1, 2, 3, 4 }; -+ -+struct z -+{ -+ double x[4]; -+}; -+ -+struct z a = { 5.0, 6.0, 7.0, 8.0 }; -+struct z b = { 9.0, 10.0, 11.0, 12.0 }; -+ -+#include "abitest.h" -+#else -+ ARG(int, 7, W0) -+ PTR(struct y, v, X1) -+ ARG(struct z, a, D0) -+ ARG(double, 1.0, D4) -+ ARG(struct z, b, STACK) -+ LAST_ARG(double, 0.5, STACK+32) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/test_18.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-2.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-2.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-2.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,42 @@ -+/* Test AAPCS64 layout. -+ -+ C.8 If the argument has an alignment of 16 then the NGRN is rounded up -+ the next even number. -+ -+ The case of a small struture containing only one 16-byte aligned -+ quad-word integer is covered in this test. */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define TESTFILE "test_align-2.c" -+#include "type-def.h" -+ -+struct y -+{ -+ union int128_t v; -+} w; -+ -+struct x -+{ -+ long long p; -+ int q; -+} s = {0xDEADBEEFCAFEBABELL, 0xFEEBDAED}; -+ -+#define HAS_DATA_INIT_FUNC -+void init_data () -+{ -+ /* Init signed quad-word integer. */ -+ w.v.l64 = 0xfdb9753102468aceLL; -+ w.v.h64 = 0xeca8642013579bdfLL; -+} -+ -+#include "abitest.h" -+#else -+ ARG(int, 0xAB, W0) -+ ARG(struct y, w, X2) -+ ARG(int, 0xCD, W4) -+ ARG(struct x, s, X5) -+ LAST_ARG(int, 0xFF00FF00, W7) -+ -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-2.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/test_19.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_19.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_19.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,35 @@ -+/* Test AAPCS64 layout. */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define TESTFILE "test_19.c" -+ -+struct y -+{ -+ int p1; -+ int p2; -+ float q; -+ int r1; -+ int r2; -+ char x; -+} v = { -1, 1, 2.0f, 3, 18, 19, 20}; -+ -+struct z -+{ -+ double x[4]; -+}; -+ -+struct z a = { 5.0, 6.0, 7.0, 8.0 }; -+struct z b = { 9.0, 10.0, 11.0, 12.0 }; -+ -+#include "abitest.h" -+#else -+ ARG(int, 7, W0) -+ DOTS -+ ANON(double, 4.0, D0) -+ ANON(struct z, a, D1) -+ ANON(struct z, b, STACK) -+ PTR_ANON(struct y, v, X1) -+ LAST_ANON(int, 10, W2) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/test_19.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-3.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-3.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-3.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,46 @@ -+/* Test AAPCS64 layout. -+ -+ C.8 If the argument has an alignment of 16 then the NGRN is rounded up -+ the next even number. -+ C.9 If the argument is an Integral Type, the size of the argument is -+ equal to 16 and the NGRN is less than 7, the argument is copied -+ to x[NGRN] and x[NGRN+1]. x[NGRN] shall contain the lower addressed -+ double-word of the memory representation of the argument. The -+ NGRN is incremented by two. The argument has now been allocated. -+ -+ The case of passing a 128-bit integer in two general registers is covered -+ in this test. */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define TESTFILE "test_align-3.c" -+#include "type-def.h" -+ -+union int128_t qword; -+ -+int gInt[4]; -+ -+#define HAS_DATA_INIT_FUNC -+void init_data () -+{ -+ /* Initialize the quadword integer via the union. */ -+ qword.l64 = 0xDEADBEEFCAFEBABELL; -+ qword.h64 = 0x123456789ABCDEF0LL; -+ -+ gInt[0] = 12345; -+ gInt[1] = 23456; -+ gInt[2] = 34567; -+ gInt[3] = 45678; -+} -+ -+ -+#include "abitest.h" -+#else -+ ARG(int, gInt[0], W0) -+ ARG(int, gInt[1], W1) -+ ARG(int, gInt[2], W2) -+ ARG(__int128, qword.i, X4) -+ LAST_ARG(int, gInt[3], W6) -+ -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-3.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-4.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-4.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-4.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,42 @@ -+/* Test AAPCS64 layout. -+ -+ C.3 If the argument is an HFA then the NSRN is set to 8 and the size -+ of the argument is rounded up to the nearest multiple of 8 bytes. -+ -+ TODO: add the check of an HFA containing half-precision floating-point -+ when __f16 is supported in A64 GCC. */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define TESTFILE "test_align-4.c" -+ -+struct z1 -+{ -+ double x[4]; -+}; -+ -+struct z1 a = { 5.0, 6.0, 7.0, 8.0 }; -+ -+struct z2 -+{ -+ float x[3]; -+}; -+ -+struct z2 b = { 13.f, 14.f, 15.f }; -+struct z2 c = { 16.f, 17.f, 18.f }; -+ -+#include "abitest.h" -+#else -+ -+ ARG(struct z1, a, D0) -+ ARG(double, 9.0, D4) -+ ARG(double, 10.0, D5) -+ ARG(struct z2, b, STACK) /* [C.3] on stack and size padded to 16 bytes */ -+#ifndef __AAPCS64_BIG_ENDIAN__ -+ ARG(float, 15.5f, STACK+16) /* [C.3] NSRN has been set to 8 */ -+#else -+ ARG(float, 15.5f, STACK+20) -+#endif -+ LAST_ARG(struct z2, c, STACK+24) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-4.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-1.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-1.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-1.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,50 @@ -+/* Test AAPCS64 layout and __builtin_va_arg. -+ -+ This test covers fundamental data types as specified in AAPCS64 \S 4.1. -+ It is focus on unnamed parameter passed in registers. */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define AAPCS64_TEST_STDARG -+#define TESTFILE "va_arg-1.c" -+#include "type-def.h" -+ -+vf2_t vf2 = (vf2_t){ 17.f, 18.f }; -+vi4_t vi4 = (vi4_t){ 0xdeadbabe, 0xbabecafe, 0xcafebeef, 0xbeefdead }; -+union int128_t qword; -+signed char sc = 0xed; -+signed int sc_promoted = 0xffffffed; -+signed short ss = 0xcba9; -+signed int ss_promoted = 0xffffcba9; -+float fp = 65432.12345f; -+double fp_promoted = (double)65432.12345f; -+ -+#define HAS_DATA_INIT_FUNC -+void init_data () -+{ -+ /* Init signed quad-word integer. */ -+ qword.l64 = 0xfdb9753102468aceLL; -+ qword.h64 = 0xeca8642013579bdfLL; -+} -+ -+#include "abitest.h" -+#else -+ ARG ( int , 0xff , X0, LAST_NAMED_ARG_ID) -+ DOTS -+ ANON_PROMOTED(unsigned char , 0xfe , unsigned int, 0xfe , X1, 1) -+ ANON_PROMOTED( signed char , sc , signed int, sc_promoted, X2, 2) -+ ANON_PROMOTED(unsigned short , 0xdcba, unsigned int, 0xdcba , X3, 3) -+ ANON_PROMOTED( signed short , ss , signed int, ss_promoted, X4, 4) -+ ANON (unsigned int , 0xdeadbeef, X5, 5) -+ ANON ( signed int , 0xcafebabe, X6, 6) -+ ANON (unsigned long long, 0xba98765432101234ULL, X7, 7) -+ ANON ( signed long long, 0xa987654321012345LL , STACK, 8) -+ ANON ( __int128, qword.i , STACK+16, 9) -+ ANON_PROMOTED( float , fp , double, fp_promoted, D0, 10) -+ ANON ( double , 9876543.212345, D1, 11) -+ ANON ( long double , 98765432123456789.987654321L, Q2, 12) -+ ANON ( vf2_t, vf2 , D3, 13) -+ ANON ( vi4_t, vi4 , Q4, 14) -+ LAST_ANON ( int , 0xeeee, STACK+32,15) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-1.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-2.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-2.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-2.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,59 @@ -+/* Test AAPCS64 layout and __builtin_va_arg. -+ -+ This test covers fundamental data types as specified in AAPCS64 \S 4.1. -+ It is focus on unnamed parameter passed on stack. */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define AAPCS64_TEST_STDARG -+#define TESTFILE "va_arg-2.c" -+#include "type-def.h" -+ -+vf2_t vf2 = (vf2_t){ 17.f, 18.f }; -+vi4_t vi4 = (vi4_t){ 0xdeadbabe, 0xbabecafe, 0xcafebeef, 0xbeefdead }; -+union int128_t qword; -+signed char sc = 0xed; -+signed int sc_promoted = 0xffffffed; -+signed short ss = 0xcba9; -+signed int ss_promoted = 0xffffcba9; -+float fp = 65432.12345f; -+double fp_promoted = (double)65432.12345f; -+ -+#define HAS_DATA_INIT_FUNC -+void init_data () -+{ -+ /* Init signed quad-word integer. */ -+ qword.l64 = 0xfdb9753102468aceLL; -+ qword.h64 = 0xeca8642013579bdfLL; -+} -+ -+#include "abitest.h" -+#else -+ ARG ( int , 0xff , X0, 0) -+ ARG ( float , 1.0f , S0, 1) -+ ARG ( float , 1.0f , S1, 2) -+ ARG ( float , 1.0f , S2, 3) -+ ARG ( float , 1.0f , S3, 4) -+ ARG ( float , 1.0f , S4, 5) -+ ARG ( float , 1.0f , S5, 6) -+ ARG ( float , 1.0f , S6, 7) -+ ARG ( float , 1.0f , S7, LAST_NAMED_ARG_ID) -+ DOTS -+ ANON ( __int128, qword.i , X2, 8) -+ ANON ( signed long long, 0xa987654321012345LL , X4, 9) -+ ANON ( __int128, qword.i , X6, 10) -+ ANON_PROMOTED(unsigned char , 0xfe , unsigned int, 0xfe , STACK, 11) -+ ANON_PROMOTED( signed char , sc , signed int, sc_promoted, STACK+8, 12) -+ ANON_PROMOTED(unsigned short , 0xdcba, unsigned int, 0xdcba , STACK+16, 13) -+ ANON_PROMOTED( signed short , ss , signed int, ss_promoted, STACK+24, 14) -+ ANON (unsigned int , 0xdeadbeef, STACK+32, 15) -+ ANON ( signed int , 0xcafebabe, STACK+40, 16) -+ ANON (unsigned long long, 0xba98765432101234ULL, STACK+48, 17) -+ ANON_PROMOTED( float , fp , double, fp_promoted, STACK+56, 18) -+ ANON ( double , 9876543.212345, STACK+64, 19) -+ ANON ( long double , 98765432123456789.987654321L, STACK+80, 20) -+ ANON ( vf2_t, vf2 , STACK+96, 21) -+ ANON ( vi4_t, vi4 , STACK+112,22) -+ LAST_ANON ( int , 0xeeee, STACK+128,23) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-2.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-3.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-3.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-3.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,86 @@ -+/* Test AAPCS64 layout and __builtin_va_arg. -+ -+ This test covers most composite types as described in AAPCS64 \S 4.3. -+ Homogeneous floating-point aggregate types are covered in other tests. */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define AAPCS64_TEST_STDARG -+#define TESTFILE "va_arg-3.c" -+#include "type-def.h" -+ -+struct x0 -+{ -+ char ch; -+ int i; -+} y0 = { 'a', 12345 }; -+ -+struct x1 -+{ -+ int a; -+ int b; -+ int c; -+ int d; -+} y1 = { 0xdeadbeef, 0xcafebabe, 0x87654321, 0xabcedf975 }; -+ -+struct x2 -+{ -+ long long a; -+ long long b; -+ char ch; -+} y2 = { 0x12, 0x34, 0x56 }; -+ -+union x3 -+{ -+ char ch; -+ int i; -+ long long ll; -+} y3; -+ -+union x4 -+{ -+ int i; -+ struct x2 y2; -+} y4; -+ -+struct x5 -+{ -+ union int128_t qword; -+} y5; -+ -+#define HAS_DATA_INIT_FUNC -+void init_data () -+{ -+ /* Init small union. */ -+ y3.ll = 0xfedcba98LL; -+ -+ /* Init big union. */ -+ y4.y2.a = 0x78; -+ y4.y2.b = 0x89; -+ y4.y2.ch= 0x9a; -+ -+ /* Init signed quad-word integer. */ -+ y5.qword.l64 = 0xfdb9753102468aceLL; -+ y5.qword.h64 = 0xeca8642013579bdfLL; -+} -+ -+#include "abitest.h" -+#else -+ ARG (float ,1.0f, S0, LAST_NAMED_ARG_ID) -+ DOTS -+ ANON (struct x0, y0, X0, 1) -+ ANON (struct x1, y1, X1, 2) -+ PTR_ANON (struct x2, y2, X3, 3) -+ ANON (union x3, y3, X4, 4) -+ PTR_ANON (union x4, y4, X5, 5) -+ ANON (struct x5, y5, X6, 6) -+ ANON (struct x0, y0, STACK, 7) -+ ANON (struct x1, y1, STACK+8, 8) -+ PTR_ANON (struct x2, y2, STACK+24, 9) -+ ANON (union x3, y3, STACK+32, 10) -+ PTR_ANON (union x4, y4, STACK+40, 11) -+ ANON (int , 1, STACK+48, 12) -+ ANON (struct x5, y5, STACK+64, 13) -+ LAST_ANON(int , 2, STACK+80, 14) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-3.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/test_1.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_1.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_1.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,31 @@ -+/* Test AAPCS64 layout */ -+ -+/* C.7 If the argument is an Integral Type, the size of the argument is -+ less than or equal to 8 bytes and the NGRN is less than 8, the -+ argument is copied to the least significant bits in x[NGRN]. The -+ NGRN is incremented by one. The argument has now been allocated. */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define TESTFILE "test_1.c" -+/* TODO: review if we need this */ -+#define RUNTIME_ENDIANNESS_CHECK -+#include "abitest.h" -+#else -+ ARG(int, 4, W0) -+ ARG(double, 4.0, D0) -+ ARG(int, 3, W1) -+ /* TODO: review the way of memcpy char, short, etc. */ -+#ifndef __AAPCS64_BIG_ENDIAN__ -+ ARG(char, 0xEF, X2) -+ ARG(short, 0xBEEF, X3) -+ ARG(int, 0xDEADBEEF, X4) -+#else -+ /* TODO: need the model/qemu to be big-endian as well */ -+ ARG(char, 0xEF, X2+7) -+ ARG(short, 0xBEEF, X3+6) -+ ARG(int, 0xDEADBEEF, X4+4) -+#endif -+ LAST_ARG(long long, 0xDEADBEEFCAFEBABELL, X5) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/test_1.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/abitest-2.h -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest-2.h (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest-2.h (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,101 @@ -+/* This header file should be included for the purpose of function return -+ value testing. */ -+ -+#include "abitest-common.h" -+#include "validate_memory.h" -+ -+void (*testfunc_ptr)(char* stack); -+ -+/* Helper macros to generate function name. Example of the function name: -+ func_return_val_1. */ -+#define FUNC_BASE_NAME func_return_val_ -+#define FUNC_NAME_COMBINE(base,suffix) base ## suffix -+#define FUNC_NAME_1(base,suffix) FUNC_NAME_COMBINE(base,suffix) -+#define FUNC_NAME(suffix) FUNC_NAME_1(FUNC_BASE_NAME,suffix) -+#define TEST_FUNC_BASE_NAME testfunc_ -+#define TEST_FUNC_NAME(suffix) FUNC_NAME_1(TEST_FUNC_BASE_NAME,suffix) -+ -+#undef DUMP_STATUS -+#ifdef DUMP_ENABLED -+#define DUMP_STATUS(type,val) printf ("### Checking "#type" "#val"\n"); -+#else -+#define DUMP_STATUS(type,val) -+#endif -+ -+/* Generate code to do memcmp to check if the returned value is in the -+ correct location and has the expected value. -+ Note that for value that is returned in the caller-allocated memory -+ block, we get the address from the saved x8 register. x8 is saved -+ just after the callee is returned; we assume that x8 has not been -+ clobbered at then, although there is no requirement for the callee -+ preserve the value stored in x8. Luckily, all test cases here are -+ simple enough that x8 doesn't normally get clobbered (although not -+ guaranteed). */ -+#undef FUNC_VAL_CHECK -+#define FUNC_VAL_CHECK(id, type, val, offset, layout) \ -+void TEST_FUNC_NAME(id)(char* stack) \ -+{ \ -+ type __x = val; \ -+ char* addr; \ -+ DUMP_STATUS(type,val) \ -+ if (offset != X8) \ -+ addr = stack + offset; \ -+ else \ -+ addr = *(char **)(stack + X8); \ -+ if (validate_memory (&__x, addr, sizeof (type), layout) != 0) \ -+ abort(); \ -+} -+ -+/* Composite larger than 16 bytes is replaced by a pointer to a copy prepared -+ by the caller, so here we extrat the pointer, deref it and compare the -+ content with that of the original one. */ -+#define PTR(type, val, offset, ...) { \ -+ type * ptr; \ -+ DUMP_ARG(type,val) \ -+ ptr = *(type **)(stack + offset); \ -+ if (memcmp (ptr, &val, sizeof (type)) != 0) abort (); \ -+} -+ -+#include TESTFILE -+ -+MYFUNCTYPE myfunc () PCSATTR; -+ -+/* Define the function to return VAL of type TYPE. I and D in the -+ parameter list are two dummy parameters to help improve the detection -+ of bugs like a short vector being returned in X0 after copied from V0. */ -+#undef FUNC_VAL_CHECK -+#define FUNC_VAL_CHECK(id, type, var, offset, layout) \ -+__attribute__ ((noinline)) type FUNC_NAME (id) (int i, double d, type t) \ -+ { \ -+ asm (""::"r" (i),"r" (d)); /* asm prevents function from getting \ -+ optimized away. Using i and d prevents \ -+ warnings about unused parameters. \ -+ */ \ -+ return t; \ -+ } -+#include TESTFILE -+ -+ -+/* Call the function to return value and call the checking function -+ to validate. See the comment above for the reason of having 0 and 0.0 -+ in the function argument list. */ -+#undef FUNC_VAL_CHECK -+#define FUNC_VAL_CHECK(id, type, var, offset, layout) \ -+ { \ -+ testfunc_ptr = TEST_FUNC_NAME(id); \ -+ FUNC_NAME(id) (0, 0.0, var); \ -+ myfunc (); \ -+ } -+ -+int main() -+{ -+ which_kind_of_test = TK_RETURN; -+ -+#ifdef HAS_DATA_INIT_FUNC -+ init_data (); -+#endif -+ -+#include TESTFILE -+ -+ return 0; -+} - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/abitest-2.h -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/abitest.h -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest.h (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest.h (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,159 @@ -+/* This header file should be included for the purpose of parameter passing -+ testing and va_arg code gen testing. -+ -+ To test va_arg code gen, #define AAPCS64_TEST_STDARG in the test case. -+ -+ The parameter passing test is done by passing variables/constants to -+ 'myfunc', which pushes its incoming arguments to a memory block on the -+ stack and then passes the memory block address to 'testfunc'. It is inside -+ 'testfunc' that the real parameter passing check is carried out. -+ -+ The function body of 'myfunc' is in abitest.S. The declaration of 'myfunc' -+ is constructed during the pre-processing stage. -+ -+ The va_arg code gen test has a similar workflow, apart from an extra set-up -+ step before calling 'myfunc'. All arguments are passed to 'stdarg_func' -+ first, which assigned these arguments to its local variables via either -+ direct assignment or va_arg macro, depending on whether an argument is named -+ or not. Afterwards, 'stdarg_func' calls 'myfunc' with the aforementioned -+ local variables as the arguments to finish the remaining steps. */ -+ -+#include "abitest-common.h" -+#include "validate_memory.h" -+ -+#ifdef AAPCS64_TEST_STDARG -+/* Generate va_start (ap, last_named_arg). Note that this requires -+ LAST_NAMED_ARG_ID to be defined/used correctly in the test file. */ -+#ifndef LAST_NAMED_ARG_ID -+#define LAST_NAMED_ARG_ID 65535 -+#endif -+#ifndef VA_START -+#undef VA_START_1 -+#define VA_START_1(ap, id) va_start (ap, _f##id); -+#define VA_START(ap, id) VA_START_1 (ap, id); -+#endif -+#endif /* AAPCS64_TEST_STDARG */ -+ -+/* Some debugging facility. */ -+#undef DUMP_ARG -+#ifdef DUMP_ENABLED -+#define DUMP_ARG(type,val) printf ("### Checking ARG "#type" "#val"\n") -+#else -+#define DUMP_ARG(type,val) -+#endif -+ -+ -+/* Function called from myfunc (defined in abitest.S) to check the arguments -+ passed to myfunc. myfunc has pushed all the arguments into the memory -+ block pointed by STACK. */ -+void testfunc(char* stack) -+{ -+#define AARCH64_MACRO_DEF_CHECK_INCOMING_ARGS -+#include "macro-def.h" -+#include TESTFILE -+#undef AARCH64_MACRO_DEF_CHECK_INCOMING_ARGS -+ return; -+} -+ -+ -+#ifndef AAPCS64_TEST_STDARG -+/* Test parameter passing. */ -+ -+/* Function declaration of myfunc. */ -+MYFUNCTYPE myfunc( -+#define AARCH64_MACRO_DEF_GEN_PARAM_TYPE_LIST -+#include "macro-def.h" -+#include TESTFILE -+#undef AARCH64_MACRO_DEF_GEN_PARAM_TYPE_LIST -+) PCSATTR; -+ -+#else /* AAPCS64_TEST_STDARG */ -+/* Test stdarg macros, e.g. va_arg. */ -+#include -+ -+/* Dummy function to help reset parameter passing registers, i.e. X0-X7 -+ and V0-V7 (by being passed 0 in W0-W7 and 0.f in S0-S7). */ -+__attribute__ ((noinline)) void -+dummy_func (int w0, int w1, int w2, int w3, int w4, int w5, int w6, int w7, -+ float s0, float s1, float s2, float s3, float s4, float s5, -+ float s6, float s7) -+{ -+ asm (""); /* Prevent function from getting optimized away */ -+ return; -+} -+ -+/* Function declaration of myfunc. */ -+MYFUNCTYPE myfunc( -+#define AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST -+#include "macro-def.h" -+#include TESTFILE -+#undef AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST -+) PCSATTR; -+ -+/* Function definition of stdarg_func. -+ stdarg_func is a variadic function; it retrieves all of its arguments, -+ both named and unnamed, and passes them to myfunc in the identical -+ order. myfunc will carry out the check on the passed values. Remember -+ that myfunc is not a variadic function. */ -+MYFUNCTYPE stdarg_func( -+#define AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST_WITH_IDENT -+#include "macro-def.h" -+#include TESTFILE -+#undef AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST_WITH_IDENT -+) PCSATTR -+{ -+ /* Start of the function body of stdarg_func. */ -+ va_list ap; -+ -+ VA_START (ap, LAST_NAMED_ARG_ID) -+ /* Zeroize the content of X0-X7 and V0-V7 to make sure that any va_arg -+ failure will not be hidden by the old data being in these registers. */ -+ dummy_func (0, 0, 0, 0, 0, 0, 0, 0, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f); -+ /* A full memory barrier to ensure that compiler won't optimize away -+ va_arg code gen. */ -+ __sync_synchronize (); -+ { -+ /* Assign all the function incoming arguments to local variables. */ -+#define AARCH64_VARIADIC_MACRO_DEF_ASSIGN_LOCAL_VARS_WITH_ARGS -+#include "macro-def.h" -+#include TESTFILE -+#undef AARCH64_VARIADIC_MACRO_DEF_ASSIGN_LOCAL_VARS_WITH_ARGS -+ -+ /* Call myfunc and pass in the local variables prepared above. */ -+ myfunc ( -+#define AARCH64_VARIADIC_MACRO_DEF_GEN_ARGUMENT_LIST -+#include "macro-def.h" -+#include TESTFILE -+#undef AARCH64_VARIADIC_MACRO_DEF_GEN_ARGUMENT_LIST -+); -+ } -+ va_end (ap); -+} -+ -+#endif /* AAPCS64_TEST_STDARG */ -+ -+ -+int main() -+{ -+#ifdef RUNTIME_ENDIANNESS_CHECK -+ rt_endian_check(); -+#endif -+#ifdef HAS_DATA_INIT_FUNC -+ init_data (); -+#endif -+ -+#ifndef AAPCS64_TEST_STDARG -+ which_kind_of_test = TK_PARAM; -+ myfunc( -+#else -+ which_kind_of_test = TK_VA_ARG; -+ stdarg_func( -+#endif -+#define AARCH64_MACRO_DEF_GEN_ARGUMENT_LIST -+#include "macro-def.h" -+#include TESTFILE -+#undef AARCH64_MACRO_DEF_GEN_ARGUMENT_LIST -+); -+ return 0; -+} -+ - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/abitest.h -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/test_2.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_2.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_2.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,16 @@ -+/* Test AAPCS64 layout */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define VFP -+#define TESTFILE "test_2.c" -+#include "abitest.h" -+ -+#else -+ ARG(float, 1.0f, S0) -+ ARG(double, 4.0, D1) -+ ARG(float, 2.0f, S2) -+ ARG(double, 5.0, D3) -+ LAST_ARG(int, 3, W0) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/test_2.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-4.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-4.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-4.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,93 @@ -+/* Test AAPCS64 layout and __builtin_va_arg. -+ -+ This test covers homogeneous floating-point aggregate types and homogeneous -+ short-vector aggregate types as described in AAPCS64 \S 4.3.5. */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define AAPCS64_TEST_STDARG -+#define TESTFILE "va_arg-4.c" -+#include "type-def.h" -+ -+struct hfa_fx1_t hfa_fx1 = {12.345f}; -+struct hfa_fx2_t hfa_fx2 = {123.456f, 234.456f}; -+struct hfa_dx2_t hfa_dx2 = {234.567, 345.678}; -+struct hfa_dx4_t hfa_dx4 = {1234.123, 2345.234, 3456.345, 4567.456}; -+struct hfa_ldx3_t hfa_ldx3 = {123456.7890, 234567.8901, 345678.9012}; -+struct non_hfa_fx5_t non_hfa_fx5 = {456.789f, 567.890f, 678.901f, 789.012f, 890.123f}; -+struct hfa_ffs_t hfa_ffs; -+struct non_hfa_ffs_t non_hfa_ffs; -+struct non_hfa_ffs_2_t non_hfa_ffs_2; -+struct hva_vf2x1_t hva_vf2x1; -+struct hva_vf2x2_t hva_vf2x2; -+struct hva_vi4x1_t hva_vi4x1; -+struct non_hfa_ffd_t non_hfa_ffd = {23.f, 24.f, 25.0}; -+struct non_hfa_ii_t non_hfa_ii = {26, 27}; -+struct non_hfa_c_t non_hfa_c = {28}; -+struct non_hfa_ffvf2_t non_hfa_ffvf2; -+struct non_hfa_fffd_t non_hfa_fffd = {33.f, 34.f, 35.f, 36.0}; -+union hfa_union_t hfa_union; -+union non_hfa_union_t non_hfa_union; -+ -+#define HAS_DATA_INIT_FUNC -+void init_data () -+{ -+ hva_vf2x1.a = (vf2_t){17.f, 18.f}; -+ hva_vf2x2.a = (vf2_t){19.f, 20.f}; -+ hva_vf2x2.b = (vf2_t){21.f, 22.f}; -+ hva_vi4x1.a = (vi4_t){19, 20, 21, 22}; -+ -+ non_hfa_ffvf2.a = 29.f; -+ non_hfa_ffvf2.b = 30.f; -+ non_hfa_ffvf2.c = (vf2_t){31.f, 32.f}; -+ -+ hfa_union.s.a = 37.f; -+ hfa_union.s.b = 38.f; -+ hfa_union.c = 39.f; -+ -+ non_hfa_union.a = 40.0; -+ non_hfa_union.b = 41.f; -+ -+ hfa_ffs.a = 42.f; -+ hfa_ffs.b = 43.f; -+ hfa_ffs.c.a = 44.f; -+ hfa_ffs.c.b = 45.f; -+ -+ non_hfa_ffs.a = 46.f; -+ non_hfa_ffs.b = 47.f; -+ non_hfa_ffs.c.a = 48.0; -+ non_hfa_ffs.c.b = 49.0; -+ -+ non_hfa_ffs_2.s.a = 50; -+ non_hfa_ffs_2.s.b = 51; -+ non_hfa_ffs_2.c = 52.f; -+ non_hfa_ffs_2.d = 53.f; -+} -+ -+#include "abitest.h" -+#else -+ ARG (int , 1, X0, LAST_NAMED_ARG_ID) -+ DOTS -+ /* HFA or HVA passed in fp/simd registers or on stack. */ -+ ANON (struct hfa_fx1_t , hfa_fx1 , S0 , 0) -+ ANON (struct hfa_fx2_t , hfa_fx2 , S1 , 1) -+ ANON (struct hfa_dx2_t , hfa_dx2 , D3 , 2) -+ ANON (struct hva_vf2x1_t, hva_vf2x1, D5 , 11) -+ ANON (struct hva_vi4x1_t, hva_vi4x1, Q6 , 12) -+ ANON (struct hfa_dx4_t , hfa_dx4 , STACK , 3) -+ ANON (struct hfa_ffs_t , hfa_ffs , STACK+32, 4) -+ ANON (union hfa_union_t, hfa_union, STACK+48, 5) -+ ANON (struct hfa_ldx3_t , hfa_ldx3 , STACK+64, 6) -+ /* Non-H[FV]A passed in general registers or on stack or via reference. */ -+ PTR_ANON (struct non_hfa_fx5_t , non_hfa_fx5 , X1 , 10) -+ ANON (struct non_hfa_ffd_t , non_hfa_ffd , X2 , 13) -+ ANON (struct non_hfa_ii_t , non_hfa_ii , X4 , 14) -+ ANON (struct non_hfa_c_t , non_hfa_c , X5 , 15) -+ ANON (struct non_hfa_ffvf2_t, non_hfa_ffvf2, X6 , 16) -+ PTR_ANON (struct non_hfa_fffd_t , non_hfa_fffd , STACK+112, 17) -+ PTR_ANON (struct non_hfa_ffs_t , non_hfa_ffs , STACK+120, 18) -+ ANON (struct non_hfa_ffs_2_t, non_hfa_ffs_2, STACK+128, 19) -+ ANON (union non_hfa_union_t, non_hfa_union, STACK+144, 20) -+ LAST_ANON(int , 2 , STACK+152, 30) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-4.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/test_3.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_3.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_3.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,18 @@ -+/* Test AAPCS layout (VFP variant) */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define VFP -+#define TESTFILE "test_3.c" -+ -+__complex__ x = 1.0+2.0i; -+ -+#include "abitest.h" -+#else -+ARG (float, 1.0f, S0) -+ARG (__complex__ double, x, D1) -+ARG (float, 2.0f, S3) -+ARG (double, 5.0, D4) -+LAST_ARG_NONFLAT (int, 3, X0, i32in64) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/test_3.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-5.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-5.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-5.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,47 @@ -+/* Test AAPCS64 layout and __builtin_va_arg. -+ -+ This test is focus on certain unnamed homogeneous floating-point aggregate -+ types passed in fp/simd registers. */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define AAPCS64_TEST_STDARG -+#define TESTFILE "va_arg-5.c" -+#include "type-def.h" -+ -+struct hfa_fx1_t hfa_fx1 = {12.345f}; -+struct hfa_fx2_t hfa_fx2 = {123.456f, 234.456f}; -+struct hfa_dx2_t hfa_dx2 = {234.567, 345.678}; -+struct hfa_dx4_t hfa_dx4 = {1234.123, 2345.234, 3456.345, 4567.456}; -+struct hfa_ldx3_t hfa_ldx3 = {123456.7890, 234567.8901, 345678.9012}; -+struct hfa_ffs_t hfa_ffs; -+union hfa_union_t hfa_union; -+ -+#define HAS_DATA_INIT_FUNC -+void init_data () -+{ -+ hfa_union.s.a = 37.f; -+ hfa_union.s.b = 38.f; -+ hfa_union.c = 39.f; -+ -+ hfa_ffs.a = 42.f; -+ hfa_ffs.b = 43.f; -+ hfa_ffs.c.a = 44.f; -+ hfa_ffs.c.b = 45.f; -+} -+ -+#include "abitest.h" -+#else -+ ARG (int, 1, X0, LAST_NAMED_ARG_ID) -+ DOTS -+ /* HFA passed in fp/simd registers or on stack. */ -+ ANON (struct hfa_dx4_t , hfa_dx4 , D0 , 0) -+ ANON (struct hfa_ldx3_t , hfa_ldx3 , Q4 , 1) -+ ANON (struct hfa_ffs_t , hfa_ffs , STACK , 2) -+ ANON (union hfa_union_t, hfa_union, STACK+16, 3) -+ ANON (struct hfa_fx1_t , hfa_fx1 , STACK+24, 4) -+ ANON (struct hfa_fx2_t , hfa_fx2 , STACK+32, 5) -+ ANON (struct hfa_dx2_t , hfa_dx2 , STACK+40, 6) -+ LAST_ANON(double , 1.0 , STACK+56, 7) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-5.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/macro-def.h -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/macro-def.h (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/macro-def.h (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,286 @@ -+/* This header file defines a set of macros to be used in the construction -+ of parameter passing and/or va_arg code gen tests during the -+ pre-processing stage. It is included inside abitest.h. -+ -+ The following macros are defined here: -+ -+ LAST_ARG -+ ARG -+ DOTS -+ ANON -+ LAST_ANON -+ PTR -+ PTR_ANON -+ LAST_ANONPTR -+ -+ These macros are given different definitions depending on which one of -+ the following macros is defined. -+ -+ AARCH64_MACRO_DEF_CHECK_INCOMING_ARGS -+ AARCH64_MACRO_DEF_GEN_PARAM_TYPE_LIST -+ AARCH64_MACRO_DEF_GEN_ARGUMENT_LIST -+ AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST -+ AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST_WITH_IDENT -+ AARCH64_VARIADIC_MACRO_DEF_ASSIGN_LOCAL_VARS_WITH_ARGS -+ AARCH64_VARIADIC_MACRO_DEF_GEN_ARGUMENT_LIST -+ -+ Do not define more than one of the above macros. */ -+ -+ -+/* AARCH64_MACRO_DEF_CHECK_INCOMING_ARGS -+ Define macros to check the incoming arguments. */ -+ -+#ifdef AARCH64_MACRO_DEF_CHECK_INCOMING_ARGS -+ -+#undef LAST_ARG -+#undef ARG -+#undef DOTS -+#undef ANON -+#undef LAST_ANON -+#undef PTR -+#undef PTR_ANON -+#undef LAST_ANONPTR -+#undef ANON_PROMOTED -+ -+/* Generate memcmp to check if the incoming args have the expected values. */ -+#define LAST_ARG_NONFLAT(type, val, offset, layout, ...) \ -+{ \ -+ type __x = val; \ -+ DUMP_ARG(type,val); \ -+ if (validate_memory (&__x, stack + offset, sizeof (type), layout) != 0) \ -+ abort(); \ -+} -+#define LAST_ARG(type,val,offset,...) LAST_ARG_NONFLAT (type, val, offset, \ -+ flat,__VA_ARGS__) -+#define ARG_NONFLAT(type,val,offset,layout,...) LAST_ARG_NONFLAT (type, val, \ -+ offset, \ -+ layout, \ -+ __VA_ARGS__) -+#define ARG(type,val,offset,...) LAST_ARG_NONFLAT(type, val, offset, \ -+ flat, __VA_ARGS__) -+#define ANON(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__) -+#define LAST_ANON(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__) -+#define ANON_PROMOTED(type,val,type_promoted, val_promoted, offset,...) \ -+ ANON(type_promoted, val_promoted, offset, __VA_ARGS__) -+/* Composite larger than 16 bytes is replaced by a pointer to a copy prepared -+ by the caller, so here we extrat the pointer, deref it and compare the -+ content with that of the original one. */ -+#define PTR(type, val, offset, ...) { \ -+ type * ptr; \ -+ DUMP_ARG(type,val); \ -+ ptr = *(type **)(stack + offset); \ -+ if (memcmp (ptr, &val, sizeof (type)) != 0) abort (); \ -+} -+#define PTR_ANON(type, val, offset, ...) PTR(type, val, offset, __VA_ARGS__) -+#define LAST_ANONPTR(type, val, offset, ...) PTR(type, val, offset, __VA_ARGS__) -+#define DOTS -+ -+#endif /* AARCH64_MACRO_DEF_CHECK_INCOMING_ARGS */ -+ -+ -+/* AARCH64_MACRO_DEF_GEN_PARAM_TYPE_LIST -+ Define macros to generate parameter type list. */ -+ -+#ifdef AARCH64_MACRO_DEF_GEN_PARAM_TYPE_LIST -+ -+#undef LAST_ARG -+#undef ARG -+#undef DOTS -+#undef ANON -+#undef LAST_ANON -+#undef PTR -+#undef PTR_ANON -+#undef LAST_ANONPTR -+ -+/* Generate parameter type list (without identifiers). */ -+#define LAST_ARG(type,val,offset) type -+#define LAST_ARG_NONFLAT(type, val, offset, layout) type -+#define ARG(type,val,offset) LAST_ARG(type, val, offset), -+#define ARG_NONFLAT(type, val, offset, layout) LAST_ARG (type, val, offset), -+#define DOTS ... -+#define ANON(type,val, offset) -+#define LAST_ANON(type,val, offset) -+#define PTR(type, val, offset) LAST_ARG(type, val, offset), -+#define PTR_ANON(type, val, offset) -+#define LAST_ANONPTR(type, val, offset) -+ -+#endif /* AARCH64_MACRO_DEF_GEN_PARAM_TYPE_LIST */ -+ -+ -+/* AARCH64_MACRO_DEF_GEN_ARGUMENT_LIST -+ Define macros to generate argument list. */ -+ -+#ifdef AARCH64_MACRO_DEF_GEN_ARGUMENT_LIST -+ -+#undef LAST_ARG -+#undef ARG -+#undef DOTS -+#undef ANON -+#undef LAST_ANON -+#undef PTR -+#undef PTR_ANON -+#undef LAST_ANONPTR -+#undef ANON_PROMOTED -+ -+/* Generate the argument list; use VAL as the argument name. */ -+#define LAST_ARG(type,val,offset,...) val -+#define LAST_ARG_NONFLAT(type,val,offset,layout,...) val -+#define ARG(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__), -+#define ARG_NONFLAT(type, val, offset, layout,...) LAST_ARG (type, val, \ -+ offset, \ -+ __VA_ARGS__), -+#define DOTS -+#define LAST_ANON(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__) -+#define ANON(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__), -+#define PTR(type, val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__), -+#define PTR_ANON(type, val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__), -+#define LAST_ANONPTR(type, val, offset,...) LAST_ARG(type, val, offset, __VA_ARGS__) -+#define ANON_PROMOTED(type,val,type_promoted, val_promoted, offset,...) \ -+ LAST_ARG(type, val, offset, __VA_ARGS__), -+ -+#endif /* AARCH64_MACRO_DEF_GEN_ARGUMENT_LIST */ -+ -+ -+/* AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST -+ Define variadic macros to generate parameter type list. */ -+ -+#ifdef AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST -+ -+#undef LAST_ARG -+#undef ARG -+#undef DOTS -+#undef ANON -+#undef LAST_ANON -+#undef PTR -+#undef PTR_ANON -+#undef LAST_ANONPTR -+#undef ANON_PROMOTED -+ -+/* Generate parameter type list (without identifiers). */ -+#define LAST_ARG(type,val,offset,...) type -+#define LAST_ARG_NONFLAT(type, val, offset, layout, ...) type -+#define ARG(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__), -+#define ARG_NONFLAT(type, val, offset, layout, ...) LAST_ARG (type, val, \ -+ offset, \ -+ __VA_ARGS__), -+#define DOTS -+#define ANON(type,val, offset,...) ARG(type,val,offset, __VA_ARGS__) -+#define LAST_ANON(type,val, offset,...) LAST_ARG(type,val, offset, __VA_ARGS__) -+#define PTR(type, val, offset,...) LAST_ARG(type, val, offset, __VA_ARGS__), -+#define PTR_ANON(type, val, offset,...) PTR(type, val, offset, __VA_ARGS__) -+#define LAST_ANONPTR(type, val, offset,...) LAST_ARG(type, val, offset, __VA_ARGS__) -+#define ANON_PROMOTED(type,val,type_promoted, val_promoted, offset,...) \ -+ LAST_ARG(type_promoted, val_promoted, offset, __VA_ARGS__), -+ -+#endif /* AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST */ -+ -+ -+/* AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST_WITH_IDENT -+ Define variadic macros to generate parameter type list with -+ identifiers. */ -+ -+#ifdef AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST_WITH_IDENT -+ -+#undef LAST_ARG -+#undef ARG -+#undef DOTS -+#undef ANON -+#undef LAST_ANON -+#undef PTR -+#undef PTR_ANON -+#undef LAST_ANONPTR -+#undef ANON_PROMOTED -+ -+/* Generate parameter type list (with identifiers). -+ The identifiers are named with prefix _f and suffix of the value of -+ __VA_ARGS__. */ -+#define LAST_ARG(type,val,offset,...) type _f##__VA_ARGS__ -+#define LAST_ARG_NONFLAT(type, val, offset, layout, ...) type _f##__VA_ARGS__ -+#define ARG(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__), -+#define ARG_NONFLAT(type, val, offset, layout, ...) LAST_ARG (type, val, \ -+ offset, \ -+ __VA_ARGS__), -+#define DOTS ... -+#define ANON(type,val, offset,...) -+#define LAST_ANON(type,val, offset,...) -+#define PTR(type, val, offset,...) LAST_ARG(type, val, offset, __VA_ARGS__), -+#define PTR_ANON(type, val, offset,...) -+#define LAST_ANONPTR(type, val, offset,...) -+#define ANON_PROMOTED(type,val,type_promoted, val_promoted, offset,...) -+ -+#endif /* AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST_WITH_IDENT */ -+ -+ -+/* AARCH64_VARIADIC_MACRO_DEF_ASSIGN_LOCAL_VARS_WITH_ARGS -+ Define variadic macros to generate assignment from the function -+ incoming arguments to local variables. */ -+ -+#ifdef AARCH64_VARIADIC_MACRO_DEF_ASSIGN_LOCAL_VARS_WITH_ARGS -+ -+#undef LAST_ARG -+#undef ARG -+#undef DOTS -+#undef ANON -+#undef LAST_ANON -+#undef PTR -+#undef PTR_ANON -+#undef LAST_ANONPTR -+#undef ANON_PROMOTED -+ -+/* Generate assignment statements. For named args, direct assignment from -+ the formal parameter is generated; for unnamed args, va_arg is used. -+ The names of the local variables start with _x and end with the value of -+ __VA_ARGS__. */ -+#define LAST_ARG(type,val,offset,...) type _x##__VA_ARGS__ = _f##__VA_ARGS__; -+#define LAST_ARG_NONFLAT(type, val, offset, layout, ...) \ -+ type _x##__VA_ARGS__ = _f##__VA_ARGS__; -+#define ARG(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__) -+#define ARG_NONFLAT(type,val,offset,layout,...) \ -+ LAST_ARG (type, val, offset, __VA_ARGS__) -+#define ANON(type,val,offset,...) type _x##__VA_ARGS__ = va_arg (ap, type); -+#define LAST_ANON(type,val,offset,...) ANON(type, val, offset, __VA_ARGS__) -+#define PTR(type, val,offset,...) ARG(type, val, offset, __VA_ARGS__) -+#define PTR_ANON(type, val, offset,...) ANON(type, val,offset, __VA_ARGS__) -+#define LAST_ANONPTR(type, val, offset,...) ANON(type, val, offset, __VA_ARGS__) -+#define ANON_PROMOTED(type,val,type_promoted, val_promoted, offset,...) \ -+ ANON(type_promoted, val_promoted, offset, __VA_ARGS__) -+ -+#define DOTS -+ -+#endif /* AARCH64_VARIADIC_MACRO_DEF_ASSIGN_LOCAL_VARS_WITH_ARGS */ -+ -+ -+/* AARCH64_VARIADIC_MACRO_DEF_GEN_ARGUMENT_LIST -+ Define variadic macros to generate argument list using the variables -+ generated during AARCH64_VARIADIC_MACRO_DEF_ASSIGN_LOCAL_VARS_WITH_ARGS. */ -+ -+#ifdef AARCH64_VARIADIC_MACRO_DEF_GEN_ARGUMENT_LIST -+ -+#undef LAST_ARG -+#undef ARG -+#undef DOTS -+#undef ANON -+#undef LAST_ANON -+#undef PTR -+#undef PTR_ANON -+#undef LAST_ANONPTR -+#undef ANON_PROMOTED -+ -+/* Generate the argument list; the names start with _x and end with the value of -+ __VA_ARGS__. All arguments (named or unnamed) in stdarg_func are passed to -+ myfunc as named arguments. */ -+#define LAST_ARG(type,val,offset,...) _x##__VA_ARGS__ -+#define LAST_ARG_NONFLAT(type, val, offset, layout, ...) _x##__VA_ARGS__ -+#define ARG(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__), -+#define ARG_NONFLAT(type, val, offset, layout, ...) \ -+ LAST_ARG_NONFLAT (type, val, offset, layout, __VA_ARGS__), -+#define DOTS -+#define LAST_ANON(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__) -+#define ANON(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__), -+#define PTR(type, val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__), -+#define PTR_ANON(type, val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__), -+#define LAST_ANONPTR(type, val, offset,...) LAST_ARG(type, val, offset, __VA_ARGS__) -+#define ANON_PROMOTED(type,val,type_promoted, val_promoted, offset,...) \ -+ ANON(type_promoted, val_promoted, offset, __VA_ARGS__) -+ -+#endif /* AARCH64_VARIADIC_MACRO_DEF_GEN_ARGUMENT_LIST */ - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/macro-def.h -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/test_4.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_4.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_4.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,20 @@ -+/* Test AAPCS layout (VFP variant) */ -+ -+/* { dg-do run { target arm*-*-eabi* } } */ -+/* { dg-require-effective-target arm_hard_vfp_ok } */ -+/* { dg-require-effective-target arm32 } */ -+/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ -+ -+#ifndef IN_FRAMEWORK -+#define VFP -+#define TESTFILE "test_4.c" -+ -+__complex__ float x = 1.0f + 2.0fi; -+#include "abitest.h" -+#else -+ARG (float, 1.0f, S0) -+ARG (__complex__ float, x, S1) -+ARG (float, 2.0f, S3) -+ARG (double, 5.0, D4) -+LAST_ARG_NONFLAT (int, 3, X0, i32in64) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/test_4.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-6.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-6.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-6.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,40 @@ -+/* Test AAPCS64 layout and __builtin_va_arg. -+ -+ This test is focus on certain unnamed homogeneous floating-point aggregate -+ types passed in fp/simd registers. */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define AAPCS64_TEST_STDARG -+#define TESTFILE "va_arg-6.c" -+#include "type-def.h" -+ -+struct hfa_fx1_t hfa_fx1 = {12.345f}; -+struct hfa_dx2_t hfa_dx2 = {234.567, 345.678}; -+struct hfa_ffs_t hfa_ffs; -+union hfa_union_t hfa_union; -+ -+#define HAS_DATA_INIT_FUNC -+void init_data () -+{ -+ hfa_union.s.a = 37.f; -+ hfa_union.s.b = 38.f; -+ hfa_union.c = 39.f; -+ -+ hfa_ffs.a = 42.f; -+ hfa_ffs.b = 43.f; -+ hfa_ffs.c.a = 44.f; -+ hfa_ffs.c.b = 45.f; -+} -+ -+#include "abitest.h" -+#else -+ ARG (int, 1, X0, LAST_NAMED_ARG_ID) -+ DOTS -+ ANON (struct hfa_ffs_t , hfa_ffs , S0 , 0) -+ ANON (union hfa_union_t, hfa_union, S4 , 1) -+ ANON (struct hfa_dx2_t , hfa_dx2 , D6 , 2) -+ ANON (struct hfa_fx1_t , hfa_fx1 , STACK , 3) -+ LAST_ANON(double , 1.0 , STACK+8, 4) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-6.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/test_5.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_5.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_5.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,24 @@ -+/* Test AAPCS64 layout */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define VFP -+#define TESTFILE "test_5.c" -+ -+__complex__ float x = 1.0+2.0i; -+ -+struct y -+{ -+ long p; -+ long q; -+} v = { 1, 2}; -+ -+#include "abitest.h" -+#else -+ ARG(float, 1.0f, S0) -+ ARG(__complex__ float, x, S1) -+ ARG(float, 2.0f, S3) -+ ARG(double, 5.0, D4) -+ LAST_ARG(struct y, v, X0) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/test_5.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-7.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-7.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-7.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,31 @@ -+/* Test AAPCS64 layout and __builtin_va_arg. -+ -+ This test covers complex types. Complex floating-point types are treated -+ as homogeneous floating-point aggregates, while complex integral types -+ are treated as general composite types. */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define AAPCS64_TEST_STDARG -+#define TESTFILE "va_arg-7.c" -+#include "type-def.h" -+ -+_Complex __int128 complex_qword = 567890 + 678901i; -+ -+#include "abitest.h" -+#else -+ ARG (int, 1, X0, LAST_NAMED_ARG_ID) -+ DOTS -+ /* Complex floating-point types are passed in fp/simd registers. */ -+ ANON (_Complex float , 12.3f + 23.4fi , S0, 0) -+ ANON (_Complex double , 34.56 + 45.67i , D2, 1) -+ ANON (_Complex long double, 56789.01234L + 67890.12345Li, Q4, 2) -+ -+ /* Complex integral types are passed in general registers or via reference. */ -+ ANON (_Complex short , (short)12345 + (short)23456i, X1, 10) -+ ANON (_Complex int , 34567 + 45678i , X2, 11) -+ PTR_ANON (_Complex __int128 , complex_qword , X3, 12) -+ -+ LAST_ANON(int , 1 , X4, 20) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-7.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/test_6.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_6.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_6.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,26 @@ -+/* Test AAPCS layout (VFP variant) */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define TESTFILE "test_6.c" -+ -+__complex__ double x = 1.0+2.0i; -+ -+struct y -+{ -+ int p; -+ int q; -+ int r; -+ int s; -+} v = { 1, 2, 3, 4 }; -+ -+#include "abitest.h" -+#else -+ ARG(struct y, v, X0) -+ ARG(float, 1.0f, S0) -+ ARG(__complex__ double, x, D1) -+ ARG(float, 2.0f, S3) -+ ARG(double, 5.0, D4) -+ LAST_ARG(int, 3, W2) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/test_6.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-8.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-8.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-8.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,25 @@ -+/* Test AAPCS64 layout and __builtin_va_arg. -+ -+ Miscellaneous test: HFA anonymous parameter passed in SIMD/FP regs. */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define AAPCS64_TEST_STDARG -+#define TESTFILE "va_arg-8.c" -+ -+struct z -+{ -+ double x[4]; -+}; -+ -+struct z a = { 5.0, 6.0, 7.0, 8.0 }; -+ -+#include "abitest.h" -+#else -+ ARG(int, 0xdeadbeef, W0, LAST_NAMED_ARG_ID) -+ DOTS -+ ANON(double, 4.0, D0, 1) -+ LAST_ANON(struct z, a, D1, 2) -+ -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-8.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/test_7.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_7.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_7.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,30 @@ -+/* Test AAPCS layout (VFP variant) */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define TESTFILE "test_7.c" -+ -+__complex__ float x = 1.0f + 2.0i; -+ -+struct y -+{ -+ int p; -+ int q; -+ int r; -+ int s; -+} v = { 1, 2, 3, 4 }, v1 = {5, 6, 7, 8}, v2 = {9, 10, 11, 12}; -+ -+#include "abitest.h" -+#else -+ARG (struct y, v, X0) -+ARG (struct y, v1, X2) -+ARG (struct y, v2, X4) -+ARG (int, 4, W6) -+ARG (float, 1.0f, S0) -+ARG (__complex__ float, x, S1) -+ARG (float, 2.0f, S3) -+ARG (double, 5.0, D4) -+ARG (int, 3, W7) -+LAST_ARG_NONFLAT (int, 5, STACK, i32in64) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/test_7.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-9.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-9.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-9.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,31 @@ -+/* Test AAPCS64 layout and __builtin_va_arg. -+ -+ Miscellaneous test: HFA anonymous parameter passed in SIMD/FP regs. */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define AAPCS64_TEST_STDARG -+#define TESTFILE "va_arg-9.c" -+ -+struct z -+{ -+ double x[4]; -+}; -+ -+double d1 = 25.0; -+struct z a = { 5.0, 6.0, 7.0, 8.0 }; -+struct z b = { 9.0, 10.0, 11.0, 12.0 }; -+ -+#include "abitest.h" -+#else -+ ARG(double, 11.0, D0, LAST_NAMED_ARG_ID) -+ DOTS -+ ANON(int, 8, W0, 1) -+ ANON(struct z, a, D1, 2) -+ ANON(struct z, b, STACK, 3) -+ ANON(int, 5, W1, 4) -+ ANON(double, d1, STACK+32, 5) -+ LAST_ANON(double, 0.5, STACK+40, 6) -+ -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-9.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/test_8.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_8.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_8.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,24 @@ -+/* Test AAPCS layout (VFP variant) */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define VFP -+#define TESTFILE "test_8.c" -+ -+struct z -+{ -+ double x[4]; -+}; -+ -+struct z a = { 5.0, 6.0, 7.0, 8.0 }; -+struct z b = { 9.0, 10.0, 11.0, 12.0 }; -+ -+#include "abitest.h" -+#else -+ ARG(struct z, a, D0) -+ ARG(struct z, b, D4) -+ ARG(double, 0.5, STACK) -+ ARG(int, 7, W0) -+ LAST_ARG(int, 8, W1) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/test_8.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/test_complex.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_complex.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_complex.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,18 @@ -+/* Test AAPCS layout (VFP variant) */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define TESTFILE "test_complex.c" -+ -+__complex__ float x = 1.0+2.0i; -+__complex__ int y = 5 + 6i; -+__complex__ double z = 2.0 + 3.0i; -+ -+#include "abitest.h" -+#else -+ ARG(__complex__ float, x, S0) -+ ARG(__complex__ int, y, X0) -+ ARG(__complex__ double, z, D2) -+ LAST_ARG (int, 5, W1) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/test_complex.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/test_9.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_9.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_9.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,32 @@ -+/* Test AAPCS layout (VFP variant) */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define VFP -+#define TESTFILE "test_9.c" -+ -+struct y -+{ -+ int p; -+ int q; -+ int r; -+ int s; -+} v = { 1, 2, 3, 4 }; -+ -+struct z -+{ -+ double x[4]; -+}; -+ -+struct z a = { 5.0, 6.0, 7.0, 8.0 }; -+struct z b = { 9.0, 10.0, 11.0, 12.0 }; -+ -+#include "abitest.h" -+#else -+ ARG(int, 7, W0) -+ ARG(struct y, v, X1) -+ ARG(struct z, a, D0) -+ ARG(struct z, b, D4) -+ LAST_ARG(double, 0.5, STACK) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/test_9.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/aapcs64.exp -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/aapcs64.exp (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/aapcs64.exp (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,67 @@ -+# Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. -+# Contributed by ARM Ltd. -+# -+# This file is part of GCC. -+# -+# GCC is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License as published by -+# the Free Software Foundation; either version 3, or (at your option) -+# any later version. -+# -+# GCC is distributed in the hope that it will be useful, but -+# WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+# General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with GCC; see the file COPYING3. If not see -+# . */ -+ -+load_lib c-torture.exp -+load_lib target-supports.exp -+load_lib torture-options.exp -+ -+if { ![istarget aarch64*-*-*] } then { -+ return -+} -+ -+torture-init -+set-torture-options $C_TORTURE_OPTIONS -+set additional_flags "-W -Wall -Wno-abi" -+ -+# Test parameter passing. -+foreach src [lsort [glob -nocomplain $srcdir/$subdir/test_*.c]] { -+ if {[runtest_file_p $runtests $src]} { -+ c-torture-execute [list $src \ -+ $srcdir/$subdir/abitest.S] \ -+ $additional_flags -+ } -+} -+ -+# Test unnamed argument retrieval via the va_arg macro. -+foreach src [lsort [glob -nocomplain $srcdir/$subdir/va_arg-*.c]] { -+ if {[runtest_file_p $runtests $src]} { -+ c-torture-execute [list $src \ -+ $srcdir/$subdir/abitest.S] \ -+ $additional_flags -+ } -+} -+ -+# Test function return value. -+foreach src [lsort [glob -nocomplain $srcdir/$subdir/func-ret-*.c]] { -+ if {[runtest_file_p $runtests $src]} { -+ c-torture-execute [list $src \ -+ $srcdir/$subdir/abitest.S] \ -+ $additional_flags -+ } -+} -+ -+# Test no internal compiler errors. -+foreach src [lsort [glob -nocomplain $srcdir/$subdir/ice_*.c]] { -+ if {[runtest_file_p $runtests $src]} { -+ c-torture [list $src] \ -+ $additional_flags -+ } -+} -+ -+torture-finish -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/test_20.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_20.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_20.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,22 @@ -+/* Test AAPCS64 layout */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define TESTFILE "test_20.c" -+ -+#include "abitest.h" -+ -+#else -+ ARG(int, 8, W0) -+ ARG(double, 1.0, D0) -+ ARG(double, 2.0, D1) -+ ARG(double, 3.0, D2) -+ ARG(double, 4.0, D3) -+ ARG(double, 5.0, D4) -+ ARG(double, 6.0, D5) -+ ARG(double, 7.0, D6) -+ DOTS -+ ANON(_Complex double, 1234.0 + 567.0i, STACK) -+ LAST_ANON(double, -987.0, STACK+16) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/test_20.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/test_21.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_21.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_21.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,21 @@ -+/* Test AAPCS64 layout */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define TESTFILE "test_21.c" -+ -+#include "abitest.h" -+ -+#else -+ ARG(int, 8, W0) -+ ARG(double, 1.0, D0) -+ ARG(double, 2.0, D1) -+ ARG(double, 3.0, D2) -+ ARG(double, 4.0, D3) -+ ARG(double, 5.0, D4) -+ ARG(double, 6.0, D5) -+ ARG(double, 7.0, D6) -+ ARG(_Complex double, 1234.0 + 567.0i, STACK) -+ LAST_ARG(double, -987.0, STACK+16) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/test_21.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-1.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-1.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-1.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,44 @@ -+/* Test AAPCS64 function result return. -+ -+ This test covers most fundamental data types as specified in -+ AAPCS64 \S 4.1. */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+/* { dg-additional-sources "abitest.S" } */ -+ -+#ifndef IN_FRAMEWORK -+#define TESTFILE "func-ret-1.c" -+#include "type-def.h" -+ -+vf2_t vf2 = (vf2_t){ 17.f, 18.f }; -+vi4_t vi4 = (vi4_t){ 0xdeadbabe, 0xbabecafe, 0xcafebeef, 0xbeefdead }; -+union int128_t qword; -+ -+int *int_ptr = (int *)0xabcdef0123456789ULL; -+ -+#define HAS_DATA_INIT_FUNC -+void init_data () -+{ -+ /* Init signed quad-word integer. */ -+ qword.l64 = 0xfdb9753102468aceLL; -+ qword.h64 = 0xeca8642013579bdfLL; -+} -+ -+#include "abitest-2.h" -+#else -+FUNC_VAL_CHECK (0, unsigned char , 0xfe , X0, i8in64) -+FUNC_VAL_CHECK (1, signed char , 0xed , X0, i8in64) -+FUNC_VAL_CHECK (2, unsigned short, 0xdcba , X0, i16in64) -+FUNC_VAL_CHECK (3, signed short, 0xcba9 , X0, i16in64) -+FUNC_VAL_CHECK (4, unsigned int , 0xdeadbeef, X0, i32in64) -+FUNC_VAL_CHECK (5, signed int , 0xcafebabe, X0, i32in64) -+FUNC_VAL_CHECK (6, unsigned long long, 0xba98765432101234ULL, X0, flat) -+FUNC_VAL_CHECK (7, signed long long, 0xa987654321012345LL, X0, flat) -+FUNC_VAL_CHECK (8, __int128, qword.i, X0, flat) -+FUNC_VAL_CHECK (9, float, 65432.12345f, S0, flat) -+FUNC_VAL_CHECK (10, double, 9876543.212345, D0, flat) -+FUNC_VAL_CHECK (11, long double, 98765432123456789.987654321L, Q0, flat) -+FUNC_VAL_CHECK (12, vf2_t, vf2, D0, f32in64) -+FUNC_VAL_CHECK (13, vi4_t, vi4, Q0, i32in128) -+FUNC_VAL_CHECK (14, int *, int_ptr, X0, flat) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-1.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/test_22.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_22.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_22.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,19 @@ -+/* Test AAPCS64 layout */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define TESTFILE "test_22.c" -+ -+struct y -+{ -+ float p; -+ float q; -+} v = { 345.0f, 678.0f }; -+ -+#include "abitest.h" -+#else -+ ARG(float, 123.0f, S0) -+ ARG(struct y, v, S1) -+ LAST_ARG(float, 901.0f, S3) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/test_22.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-2.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-2.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-2.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,71 @@ -+/* Test AAPCS64 function result return. -+ -+ This test covers most composite types as described in AAPCS64 \S 4.3. -+ Homogeneous floating-point aggregate types are covered in func-ret-3.c. */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+/* { dg-additional-sources "abitest.S" } */ -+ -+#ifndef IN_FRAMEWORK -+#define TESTFILE "func-ret-2.c" -+ -+struct x0 -+{ -+ char ch; -+ int i; -+} ys0 = { 'a', 12345 }; -+ -+struct x1 -+{ -+ int a; -+ unsigned int b; -+ unsigned int c; -+ unsigned int d; -+} ys1 = { 0xdeadbeef, 0xcafebabe, 0x87654321, 0xbcedf975 }; -+ -+struct x2 -+{ -+ long long a; -+ long long b; -+ char ch; -+} y2 = { 0x12, 0x34, 0x56 }; -+ -+union x3 -+{ -+ char ch; -+ int i; -+ long long ll; -+} y3; -+ -+union x4 -+{ -+ int i; -+ struct x2 y2; -+} y4; -+ -+#define HAS_DATA_INIT_FUNC -+void init_data () -+{ -+ /* Init small union. */ -+ y3.ll = 0xfedcba98LL; -+ -+ /* Init big union. */ -+ y4.y2.a = 0x78; -+ y4.y2.b = 0x89; -+ y4.y2.ch= 0x9a; -+} -+ -+ -+#include "abitest-2.h" -+#else -+ /* Composite smaller than or equal to 16 bytes returned in X0 and X1. */ -+FUNC_VAL_CHECK ( 0, struct x0, ys0, X0, flat) -+FUNC_VAL_CHECK ( 1, struct x1, ys1, X0, flat) -+FUNC_VAL_CHECK ( 2, union x3, y3, X0, flat) -+ -+ /* Composite larger than 16 bytes returned in the caller-reserved memory -+ block of which the address is passed as an additional argument to the -+ function in X8. */ -+FUNC_VAL_CHECK (10, struct x2, y2, X8, flat) -+FUNC_VAL_CHECK (11, union x4, y4, X8, flat) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-2.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/type-def.h -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/type-def.h (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/type-def.h (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,157 @@ -+/* This header file defines some types that are used in the AAPCS64 tests. */ -+ -+ -+/* 64-bit vector of 2 floats. */ -+typedef float vf2_t __attribute__((vector_size (8))); -+ -+/* 128-bit vector of 4 floats. */ -+typedef float vf4_t __attribute__((vector_size (16))); -+ -+/* 128-bit vector of 4 ints. */ -+typedef int vi4_t __attribute__((vector_size (16))); -+ -+/* signed quad-word (in an union for the convenience of initialization). */ -+union int128_t -+{ -+ __int128 i; -+ struct -+ { -+ signed long long l64; -+ signed long long h64; -+ }; -+}; -+ -+/* Homogeneous floating-point composite types. */ -+ -+struct hfa_fx1_t -+{ -+ float a; -+}; -+ -+struct hfa_fx2_t -+{ -+ float a; -+ float b; -+}; -+ -+struct hfa_dx2_t -+{ -+ double a; -+ double b; -+}; -+ -+struct hfa_dx4_t -+{ -+ double a; -+ double b; -+ double c; -+ double d; -+}; -+ -+struct hfa_ldx3_t -+{ -+ long double a; -+ long double b; -+ long double c; -+}; -+ -+struct hfa_ffs_t -+{ -+ float a; -+ float b; -+ struct hfa_fx2_t c; -+}; -+ -+union hfa_union_t -+{ -+ struct -+ { -+ float a; -+ float b; -+ } s; -+ float c; -+}; -+ -+/* Non homogeneous floating-point-composite types. */ -+ -+struct non_hfa_fx5_t -+{ -+ float a; -+ float b; -+ float c; -+ float d; -+ float e; -+}; -+ -+struct non_hfa_ffs_t -+{ -+ float a; -+ float b; -+ struct hfa_dx2_t c; -+}; -+ -+struct non_hfa_ffs_2_t -+{ -+ struct -+ { -+ int a; -+ int b; -+ } s; -+ float c; -+ float d; -+}; -+ -+struct hva_vf2x1_t -+{ -+ vf2_t a; -+}; -+ -+struct hva_vf2x2_t -+{ -+ vf2_t a; -+ vf2_t b; -+}; -+ -+struct hva_vi4x1_t -+{ -+ vi4_t a; -+}; -+ -+struct non_hfa_ffd_t -+{ -+ float a; -+ float b; -+ double c; -+}; -+ -+struct non_hfa_ii_t -+{ -+ int a; -+ int b; -+}; -+ -+struct non_hfa_c_t -+{ -+ char a; -+}; -+ -+struct non_hfa_ffvf2_t -+{ -+ float a; -+ float b; -+ vf2_t c; -+}; -+ -+struct non_hfa_fffd_t -+{ -+ float a; -+ float b; -+ float c; -+ double d; -+}; -+ -+union non_hfa_union_t -+{ -+ double a; -+ float b; -+}; - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/type-def.h -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/test_23.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_23.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_23.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,42 @@ -+/* Test AAPCS64 layout. -+ -+ Larger than machine-supported vector size. The behaviour is unspecified by -+ the AAPCS64 document; the implementation opts for pass by reference. */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define TESTFILE "test_23.c" -+ -+typedef char A __attribute__ ((vector_size (64))); -+ -+struct y -+{ -+ double df[8]; -+}; -+ -+union u -+{ -+ struct y x; -+ A a; -+} u; -+ -+#define HAS_DATA_INIT_FUNC -+void init_data () -+{ -+ u.x.df[0] = 1.0; -+ u.x.df[1] = 2.0; -+ u.x.df[2] = 3.0; -+ u.x.df[3] = 4.0; -+ u.x.df[4] = 5.0; -+ u.x.df[5] = 6.0; -+ u.x.df[6] = 7.0; -+ u.x.df[7] = 8.0; -+} -+ -+#include "abitest.h" -+#else -+ARG (float, 123.0f, S0) -+PTR (A, u.a, X0) -+LAST_ARG_NONFLAT (int, 0xdeadbeef, X1, i32in64) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/test_23.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-3.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-3.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-3.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,93 @@ -+/* Test AAPCS64 function result return. -+ -+ This test covers homogeneous floating-point aggregate types as described -+ in AAPCS64 \S 4.3.5. */ -+ -+/* { dg-do run { target aarch64-*-* } } */ -+/* { dg-additional-sources "abitest.S" } */ -+/* { dg-require-effective-target aarch64_big_endian } */ -+ -+#ifndef IN_FRAMEWORK -+#define TESTFILE "func-ret-3.c" -+#include "type-def.h" -+ -+struct hfa_fx1_t hfa_fx1 = {12.345f}; -+struct hfa_fx2_t hfa_fx2 = {123.456f, 234.456f}; -+struct hfa_dx2_t hfa_dx2 = {234.567, 345.678}; -+struct hfa_dx4_t hfa_dx4 = {1234.123, 2345.234, 3456.345, 4567.456}; -+struct hfa_ldx3_t hfa_ldx3 = {123456.7890, 234567.8901, 345678.9012}; -+struct non_hfa_fx5_t non_hfa_fx5 = {456.789f, 567.890f, 678.901f, 789.012f, 890.123f}; -+struct hfa_ffs_t hfa_ffs; -+struct non_hfa_ffs_t non_hfa_ffs; -+struct non_hfa_ffs_2_t non_hfa_ffs_2; -+struct hva_vf2x1_t hva_vf2x1; -+struct hva_vi4x1_t hva_vi4x1; -+struct non_hfa_ffd_t non_hfa_ffd = {23.f, 24.f, 25.0}; -+struct non_hfa_ii_t non_hfa_ii = {26, 27}; -+struct non_hfa_c_t non_hfa_c = {28}; -+struct non_hfa_ffvf2_t non_hfa_ffvf2; -+struct non_hfa_fffd_t non_hfa_fffd = {33.f, 34.f, 35.f, 36.0}; -+union hfa_union_t hfa_union; -+union non_hfa_union_t non_hfa_union; -+ -+#define HAS_DATA_INIT_FUNC -+void init_data () -+{ -+ hva_vf2x1.a = (vf2_t){17.f, 18.f}; -+ hva_vi4x1.a = (vi4_t){19, 20, 21, 22}; -+ -+ non_hfa_ffvf2.a = 29.f; -+ non_hfa_ffvf2.b = 30.f; -+ non_hfa_ffvf2.c = (vf2_t){31.f, 32.f}; -+ -+ hfa_union.s.a = 37.f; -+ hfa_union.s.b = 38.f; -+ hfa_union.c = 39.f; -+ -+ non_hfa_union.a = 40.0; -+ non_hfa_union.b = 41.f; -+ -+ hfa_ffs.a = 42.f; -+ hfa_ffs.b = 43.f; -+ hfa_ffs.c.a = 44.f; -+ hfa_ffs.c.b = 45.f; -+ -+ non_hfa_ffs.a = 46.f; -+ non_hfa_ffs.b = 47.f; -+ non_hfa_ffs.c.a = 48.0; -+ non_hfa_ffs.c.b = 49.0; -+ -+ non_hfa_ffs_2.s.a = 50; -+ non_hfa_ffs_2.s.b = 51; -+ non_hfa_ffs_2.c = 52.f; -+ non_hfa_ffs_2.d = 53.f; -+} -+ -+#include "abitest-2.h" -+#else -+ /* HFA returned in fp/simd registers. */ -+ -+FUNC_VAL_CHECK ( 0, struct hfa_fx1_t , hfa_fx1 , S0, flat) -+FUNC_VAL_CHECK ( 1, struct hfa_fx2_t , hfa_fx2 , S0, flat) -+FUNC_VAL_CHECK ( 2, struct hfa_dx2_t , hfa_dx2 , D0, flat) -+ -+FUNC_VAL_CHECK ( 3, struct hfa_dx4_t , hfa_dx4 , D0, flat) -+FUNC_VAL_CHECK ( 4, struct hfa_ldx3_t, hfa_ldx3 , Q0, flat) -+FUNC_VAL_CHECK ( 5, struct hfa_ffs_t , hfa_ffs , S0, flat) -+FUNC_VAL_CHECK ( 6, union hfa_union_t, hfa_union, S0, flat) -+ -+FUNC_VAL_CHECK ( 7, struct hva_vf2x1_t, hva_vf2x1, D0, flat) -+FUNC_VAL_CHECK ( 8, struct hva_vi4x1_t, hva_vi4x1, Q0, flat) -+ -+ /* Non-HFA returned in general registers or via a pointer in X8. */ -+FUNC_VAL_CHECK (10, struct non_hfa_fx5_t , non_hfa_fx5 , X8, flat) -+FUNC_VAL_CHECK (13, struct non_hfa_ffd_t , non_hfa_ffd , X0, flat) -+FUNC_VAL_CHECK (14, struct non_hfa_ii_t , non_hfa_ii , X0, flat) -+FUNC_VAL_CHECK (15, struct non_hfa_c_t , non_hfa_c , X0, flat) -+FUNC_VAL_CHECK (16, struct non_hfa_ffvf2_t, non_hfa_ffvf2, X0, flat) -+FUNC_VAL_CHECK (17, struct non_hfa_fffd_t , non_hfa_fffd , X8, flat) -+FUNC_VAL_CHECK (18, struct non_hfa_ffs_t , non_hfa_ffs , X8, flat) -+FUNC_VAL_CHECK (19, struct non_hfa_ffs_2_t, non_hfa_ffs_2, X0, flat) -+FUNC_VAL_CHECK (20, union non_hfa_union_t, non_hfa_union, X0, flat) -+ -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-3.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/test_quad_double.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_quad_double.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_quad_double.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,26 @@ -+/* Test AAPCS64 layout. -+ -+ Test parameter passing of floating-point quad precision types. */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define TESTFILE "test_quad_double.c" -+ -+typedef long double TFtype; -+typedef _Complex long double CTFtype; -+ -+TFtype x = 1.0; -+TFtype y = 2.0; -+ -+CTFtype cx = 3.0 + 4.0i; -+CTFtype cy = 5.0 + 6.0i; -+ -+#include "abitest.h" -+#else -+ ARG ( TFtype, x, Q0) -+ ARG (CTFtype, cx, Q1) -+ DOTS -+ ANON (CTFtype, cy, Q3) -+ LAST_ANON ( TFtype, y, Q5) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/test_quad_double.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/test_24.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_24.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_24.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,22 @@ -+/* Test AAPCS64 layout. */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define TESTFILE "test_24.c" -+ -+typedef long double TFtype; -+ -+#include "abitest.h" -+#else -+ ARG(TFtype, 1.0, Q0) -+ ARG(TFtype, 2.0, Q1) -+ ARG(TFtype, 3.0, Q2) -+ ARG(TFtype, 4.0, Q3) -+ ARG(TFtype, 5.0, Q4) -+ ARG(TFtype, 6.0, Q5) -+ ARG(TFtype, 7.0, Q6) -+ ARG(TFtype, 8.0, Q7) -+ ARG(double, 9.0, STACK) -+ LAST_ARG(TFtype, 10.0, STACK+16) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/test_24.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-4.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-4.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-4.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,27 @@ -+/* Test AAPCS64 function result return. -+ -+ This test covers complex types. Complex floating-point types are treated -+ as homogeneous floating-point aggregates, while complex integral types -+ are treated as general composite types. */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+/* { dg-additional-sources "abitest.S" } */ -+/* { dg-require-effective-target aarch64_big_endian } */ -+ -+#ifndef IN_FRAMEWORK -+#define TESTFILE "func-ret-4.c" -+ -+#include "abitest-2.h" -+#else -+ /* Complex floating-point types are passed in fp/simd registers. */ -+FUNC_VAL_CHECK ( 0, _Complex float , 12.3f + 23.4fi, S0, flat) -+FUNC_VAL_CHECK ( 1, _Complex double, 34.56 + 45.67i, D0, flat) -+FUNC_VAL_CHECK ( 2, _Complex long double, 56789.01234 + 67890.12345i, Q0, flat) -+ -+ /* Complex integral types are passed in general registers or via a pointer in -+ X8. */ -+FUNC_VAL_CHECK (10, _Complex short , 12345 + 23456i, X0, flat) -+FUNC_VAL_CHECK (11, _Complex int , 34567 + 45678i, X0, flat) -+FUNC_VAL_CHECK (12, _Complex __int128, 567890 + 678901i, X8, flat) -+ -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-4.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/test_25.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_25.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_25.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,61 @@ -+/* Test AAPCS64 layout -+ -+ Test homogeneous floating-point aggregates and homogeneous short-vector -+ aggregates, which should be passed in SIMD/FP registers or via the -+ stack. */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define TESTFILE "test_25.c" -+ -+typedef float vf2_t __attribute__((vector_size (8))); -+struct x0 -+{ -+ vf2_t v; -+} s0; -+struct x3 -+{ -+ vf2_t v[2]; -+} s3; -+struct x4 -+{ -+ vf2_t v[3]; -+} s4; -+ -+typedef float vf4_t __attribute__((vector_size(16))); -+struct x1 -+{ -+ vf4_t v; -+} s1; -+ -+struct x2 -+{ -+ double df[3]; -+} s2; -+ -+#define HAS_DATA_INIT_FUNC -+void init_data () -+{ -+ s0.v = (vf2_t){ 17.f, 18.f }; -+ s1.v = (vf4_t){ 567.890f, 678.901f, 789.012f, 890.123f }; -+ s2.df[0] = 123.456; -+ s2.df[1] = 234.567; -+ s2.df[2] = 345.678; -+ s3.v[0] = (vf2_t){ 19.f, 20.f, 21.f, 22.f }; -+ s3.v[1] = (vf2_t){ 23.f, 24.f, 25.f, 26.f }; -+ s4.v[0] = (vf2_t){ 27.f, 28.f, 29.f, 30.f }; -+ s4.v[1] = (vf2_t){ 31.f, 32.f, 33.f, 34.f }; -+ s4.v[2] = (vf2_t){ 35.f, 36.f, 37.f, 38.f }; -+} -+ -+#include "abitest.h" -+#else -+ARG_NONFLAT (struct x0, s0, Q0, f32in64) -+ARG (struct x2, s2, D1) -+ARG (struct x1, s1, Q4) -+ARG (struct x3, s3, D5) -+ARG (struct x4, s4, STACK) -+ARG_NONFLAT (int, 0xdeadbeef, X0, i32in64) -+LAST_ARG (double, 456.789, STACK+24) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/test_25.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/abitest-common.h -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest-common.h (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest-common.h (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,139 @@ -+#undef __AAPCS64_BIG_ENDIAN__ -+#ifdef __GNUC__ -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+#define __AAPCS64_BIG_ENDIAN__ -+#endif -+#else -+#error unknown compiler -+#endif -+ -+#define IN_FRAMEWORK -+ -+#define D0 0 -+#define D1 8 -+#define D2 16 -+#define D3 24 -+#define D4 32 -+#define D5 40 -+#define D6 48 -+#define D7 56 -+ -+#define S0 64 -+#define S1 68 -+#define S2 72 -+#define S3 76 -+#define S4 80 -+#define S5 84 -+#define S6 88 -+#define S7 92 -+ -+#define W0 96 -+#define W1 100 -+#define W2 104 -+#define W3 108 -+#define W4 112 -+#define W5 116 -+#define W6 120 -+#define W7 124 -+ -+#define X0 128 -+#define X1 136 -+#define X2 144 -+#define X3 152 -+#define X4 160 -+#define X5 168 -+#define X6 176 -+#define X7 184 -+ -+#define Q0 192 -+#define Q1 208 -+#define Q2 224 -+#define Q3 240 -+#define Q4 256 -+#define Q5 272 -+#define Q6 288 -+#define Q7 304 -+ -+#define X8 320 -+#define X9 328 -+ -+#define STACK 336 -+ -+/* The type of test. 'myfunc' in abitest.S needs to know which kind of -+ test it is running to decide what to do at the runtime. Keep the -+ related code in abitest.S synchronized if anything is changed here. */ -+enum aapcs64_test_kind -+{ -+ TK_PARAM = 0, /* Test parameter passing. */ -+ TK_VA_ARG, /* Test va_arg code generation. */ -+ TK_RETURN /* Test function return value. */ -+}; -+ -+int which_kind_of_test; -+ -+extern int printf (const char*, ...); -+extern void abort (void); -+extern void dumpregs () __asm("myfunc"); -+ -+#ifndef MYFUNCTYPE -+#define MYFUNCTYPE void -+#endif -+ -+#ifndef PCSATTR -+#define PCSATTR -+#endif -+ -+ -+#ifdef RUNTIME_ENDIANNESS_CHECK -+#ifndef RUNTIME_ENDIANNESS_CHECK_FUNCTION_DEFINED -+/* This helper funtion defined to detect whether there is any incompatibility -+ issue on endianness between compilation time and run-time environments. -+ TODO: review the implementation when the work of big-endian support in A64 -+ GCC starts. -+ */ -+static void rt_endian_check () -+{ -+ const char* msg_endian[2] = {"little-endian", "big-endian"}; -+ const char* msg_env[2] = {"compile-time", "run-time"}; -+ union -+ { -+ unsigned int ui; -+ unsigned char ch[4]; -+ } u; -+ int flag = -1; -+ -+ u.ui = 0xCAFEBABE; -+ -+ printf ("u.ui=0x%X, u.ch[0]=0x%X\n", u.ui, u.ch[0]); -+ -+ if (u.ch[0] == 0xBE) -+ { -+ /* Little-Endian at run-time */ -+#ifdef __AAPCS64_BIG_ENDIAN__ -+ /* Big-Endian at compile-time */ -+ flag = 1; -+#endif -+ } -+ else -+ { -+ /* Big-Endian at run-time */ -+#ifndef __AAPCS64_BIG_ENDIAN__ -+ /* Little-Endian at compile-time */ -+ flag = 0; -+#endif -+ } -+ -+ if (flag != -1) -+ { -+ /* Endianness conflict exists */ -+ printf ("Error: endianness conflicts between %s and %s:\n\ -+\t%s: %s\n\t%s: %s\n", msg_env[0], msg_env[1], msg_env[0], msg_endian[flag], -+ msg_env[1], msg_endian[1-flag]); -+ abort (); -+ } -+ -+ return; -+} -+#endif -+#define RUNTIME_ENDIANNESS_CHECK_FUNCTION_DEFINED -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/abitest-common.h -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/aapcs64/test_26.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_26.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/aapcs64/test_26.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,54 @@ -+/* Test AAPCS64 layout. -+ -+ Test some small structures that should be passed in GPRs. */ -+ -+/* { dg-do run { target aarch64*-*-* } } */ -+ -+#ifndef IN_FRAMEWORK -+#define TESTFILE "test_26.c" -+ -+struct y0 -+{ -+ char ch; -+} c0 = { 'A' }; -+ -+struct y2 -+{ -+ long long ll[2]; -+} c2 = { 0xDEADBEEF, 0xCAFEBABE }; -+ -+struct y3 -+{ -+ int i[3]; -+} c3 = { 56789, 67890, 78901 }; -+ -+typedef float vf2_t __attribute__((vector_size (8))); -+struct x0 -+{ -+ vf2_t v; -+} s0; -+ -+typedef short vh4_t __attribute__((vector_size (8))); -+ -+struct x1 -+{ -+ vh4_t v[2]; -+} s1; -+ -+#define HAS_DATA_INIT_FUNC -+void init_data () -+{ -+ s0.v = (vf2_t){ 17.f, 18.f }; -+ s1.v[0] = (vh4_t){ 345, 456, 567, 678 }; -+ s1.v[1] = (vh4_t){ 789, 890, 901, 123 }; -+} -+ -+#include "abitest.h" -+#else -+ARG (struct y0, c0, X0) -+ARG (struct y2, c2, X1) -+ARG (struct y3, c3, X3) -+ARG_NONFLAT (struct x0, s0, D0, f32in64) -+ARG (struct x1, s1, D1) -+LAST_ARG_NONFLAT (int, 89012, X5, i32in64) -+#endif - -Property changes on: gcc/testsuite/gcc.target/aarch64/aapcs64/test_26.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,105 @@ -+/* { dg-do run } */ -+/* { dg-options "-O3 -ffast-math" } */ -+ -+extern void abort (void); -+ -+#include "vect-fmax-fmin.x" -+ -+#include "vect-fmaxv-fminv.x" -+ -+#define DEFN_SETV(type) \ -+ set_vector_##type (pR##type a, type n) \ -+ { \ -+ int i; \ -+ for (i=0; i<16; i++) \ -+ a[i] = n; \ -+ } -+ -+#define DEFN_CHECKV(type) \ -+ void check_vector_##type (pR##type a, pR##type vec) \ -+ { \ -+ int i; \ -+ for (i=0; i<16; i++) \ -+ if (a[i] != vec[i]) \ -+ abort (); \ -+ } -+ -+#define TEST2(fname, type) \ -+ set_vector_##type (c##type, 0.0); \ -+ fname##_##type (a##type, b##type); \ -+ check_vector_##type (c##type, fname##_##type##_vector); -+ -+#define TEST3(fname, type) \ -+ set_vector_##type (c##type, 0.0); \ -+ fname##_##type (a##type, b##type, c##type); \ -+ check_vector_##type (c##type, fname##_##type##_vector); -+ -+#define TEST(fname, N) \ -+ TEST##N (fname, F32); \ -+ TEST##N (fname, F64); -+ -+typedef float F32; -+typedef double F64; -+ -+DEFN_SETV (F32) -+DEFN_SETV (F64) -+ -+DEFN_CHECKV (F32) -+DEFN_CHECKV (F64) -+ -+int main (void) -+{ -+ -+ F32 aF32[16]; -+ F32 bF32[16]; -+ F32 cF32[16]; -+ -+ F64 aF64[16]; -+ F64 bF64[16]; -+ F64 cF64[16]; -+ int i; -+ -+ /* Golden vectors. */ -+ F32 max_F32_vector[] = { 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, -+ 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0 }; -+ -+ F64 max_F64_vector[] = { 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, -+ 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0 }; -+ -+ F32 min_F32_vector[] = { 0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, -+ 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0, 0.0 }; -+ -+ F64 min_F64_vector[] = { 0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, -+ 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0, 0.0 }; -+ -+ F32 minv_F32_value = 0.0f; -+ F32 maxv_F32_value = 15.0f; -+ -+ F64 minv_F64_value = 0.0; -+ F64 maxv_F64_value = 15.0; -+ -+ /* Setup input vectors. */ -+ for (i=0; i<16; i++) -+ { -+ aF32[i] = (float)(15-i); -+ bF32[i] = (float)i; -+ aF64[i] = (double)(15-i); -+ bF64[i] = (double)i; -+ } -+ -+ TEST (max, 3); -+ TEST (min, 3); -+ -+ /* Test across lanes ops. */ -+ if (maxv_f32 (max_F32_vector) != maxv_F32_value) -+ abort (); -+ if (minv_f32 (min_F32_vector) != minv_F32_value) -+ abort (); -+ -+ if (maxv_f64 (max_F64_vector) != maxv_F64_value) -+ abort (); -+ if (minv_f64 (min_F64_vector) != minv_F64_value) -+ abort (); -+ -+ return 0; -+} - -Property changes on: gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/volatile-bitfields-3.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/volatile-bitfields-3.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/volatile-bitfields-3.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,17 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+ -+typedef struct { -+ volatile unsigned long a:8; -+ volatile unsigned long b:8; -+ volatile unsigned long c:16; -+} BitStruct; -+ -+BitStruct bits; -+ -+unsigned long foo () -+{ -+ return bits.c; -+} -+ -+/* { dg-final { scan-assembler "ldr\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" } } */ - -Property changes on: gcc/testsuite/gcc.target/aarch64/volatile-bitfields-3.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/mneg-1.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/mneg-1.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/mneg-1.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,10 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+ -+int r; -+ -+void test (int a, int b) -+{ -+ /* { dg-final { scan-assembler "mneg\tw\[0-9\]*, w\[0-9\]*, w\[0-9\]*\n" } } */ -+ r = (-a) * b; -+} - -Property changes on: gcc/testsuite/gcc.target/aarch64/mneg-1.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/fcvt_float_uint.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/fcvt_float_uint.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/fcvt_float_uint.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,15 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+ -+#define GPF float -+#define SUFFIX(x) x##f -+#define GPI unsigned int -+ -+#include "fcvt.x" -+ -+/* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\]+, *s\[0-9\]" 2 } } */ -+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 } } */ -+/* { dg-final { scan-assembler-times "fcvtpu\tw\[0-9\]+, *s\[0-9\]" 2 } } */ -+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 } } */ -+/* { dg-final { scan-assembler-times "fcvtmu\tw\[0-9\]+, *s\[0-9\]" 2 } } */ -+/* { dg-final { scan-assembler-times "fcvtau\tw\[0-9\]+, *s\[0-9\]" 2 } } */ - -Property changes on: gcc/testsuite/gcc.target/aarch64/fcvt_float_uint.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/adc-2.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/adc-2.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/adc-2.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,277 @@ -+/* { dg-do run } */ -+/* { dg-options "-O2" } */ -+ -+extern void abort (void); -+ -+/* This series of tests looks for the optimization: -+ x = (a >= b) + c + d -+ => -+ cmp a, b -+ adc x, c, d -+ */ -+ -+unsigned long -+ltu_add (unsigned long a, unsigned long b, unsigned long c, unsigned long d) -+{ -+ return (a < b) + c + d; -+} -+ -+unsigned long -+gtu_add (unsigned long a, unsigned long b, unsigned long c, unsigned long d) -+{ -+ return (a > b) + c + d; -+} -+ -+unsigned long -+leu_add (unsigned long a, unsigned long b, unsigned long c, unsigned long d) -+{ -+ return (a <= b) + c + d; -+} -+ -+unsigned long -+geu_add (unsigned long a, unsigned long b, unsigned long c, unsigned long d) -+{ -+ return (a >= b) + c + d; -+} -+ -+unsigned long -+equ_add (unsigned long a, unsigned long b, unsigned long c, unsigned long d) -+{ -+ return (a == b) + c + d; -+} -+ -+unsigned long -+neu_add (unsigned long a, unsigned long b, unsigned long c, unsigned long d) -+{ -+ return (a != b) + c + d; -+} -+ -+long -+lt_add ( long a, long b, long c, long d) -+{ -+ return (a < b) + c + d; -+} -+ -+long -+gt_add ( long a, long b, long c, long d) -+{ -+ return (a > b) + c + d; -+} -+ -+long -+le_add ( long a, long b, long c, long d) -+{ -+ return (a <= b) + c + d; -+} -+ -+long -+ge_add ( long a, long b, long c, long d) -+{ -+ return (a >= b) + c + d; -+} -+ -+long -+eq_add ( long a, long b, long c, long d) -+{ -+ return (a == b) + c + d; -+} -+ -+long -+ne_add ( long a, long b, long c, long d) -+{ -+ return (a != b) + c + d; -+} -+ -+ -+int -+main () -+{ -+ if (ltu_add(1,2,3,4) != 8) -+ { -+ abort(); -+ } -+ -+ if (ltu_add(2,2,3,4) != 7) -+ { -+ abort(); -+ } -+ -+ if (ltu_add(3,2,3,4) != 7) -+ { -+ abort(); -+ } -+ -+ if (gtu_add(2,1,3,4) != 8) -+ { -+ abort(); -+ } -+ -+ if (gtu_add(2,2,3,4) != 7) -+ { -+ abort(); -+ } -+ -+ if (gtu_add(1,2,3,4) != 7) -+ { -+ abort(); -+ } -+ -+ if (leu_add(1,2,3,4) != 8) -+ { -+ abort(); -+ } -+ -+ if (leu_add(2,2,3,4) != 8) -+ { -+ abort(); -+ } -+ -+ if (leu_add(3,2,3,4) != 7) -+ { -+ abort(); -+ } -+ -+ if (leu_add(2,1,3,4) != 7) -+ { -+ abort(); -+ } -+ -+ if (geu_add(2,1,3,4) != 8) -+ { -+ abort(); -+ } -+ if (geu_add(2,2,3,4) != 8) -+ { -+ abort(); -+ } -+ -+ if (geu_add(1,2,3,4) != 7) -+ { -+ abort(); -+ } -+ -+ if (equ_add(1,2,3,4) != 7) -+ { -+ abort(); -+ } -+ -+ if (equ_add(2,2,3,4) != 8) -+ { -+ abort(); -+ } -+ -+ if (equ_add(3,2,3,4) != 7) -+ { -+ abort(); -+ } -+ -+ if (neu_add(1,2,3,4) != 8) -+ { -+ abort(); -+ } -+ -+ if (neu_add(2,2,3,4) != 7) -+ { -+ abort(); -+ } -+ -+ if (neu_add(3,2,3,4) != 8) -+ { -+ abort(); -+ } -+ -+ if (lt_add(1,2,3,4) != 8) -+ { -+ abort(); -+ } -+ -+ if (lt_add(2,2,3,4) != 7) -+ { -+ abort(); -+ } -+ -+ if (lt_add(3,2,3,4) != 7) -+ { -+ abort(); -+ } -+ -+ if (gt_add(2,1,3,4) != 8) -+ { -+ abort(); -+ } -+ -+ if (gt_add(2,2,3,4) != 7) -+ { -+ abort(); -+ } -+ -+ if (gt_add(1,2,3,4) != 7) -+ { -+ abort(); -+ } -+ -+ if (le_add(1,2,3,4) != 8) -+ { -+ abort(); -+ } -+ -+ if (le_add(2,2,3,4) != 8) -+ { -+ abort(); -+ } -+ -+ if (le_add(3,2,3,4) != 7) -+ { -+ abort(); -+ } -+ -+ if (le_add(2,1,3,4) != 7) -+ { -+ abort(); -+ } -+ -+ if (ge_add(2,1,3,4) != 8) -+ { -+ abort(); -+ } -+ if (ge_add(2,2,3,4) != 8) -+ { -+ abort(); -+ } -+ -+ if (ge_add(1,2,3,4) != 7) -+ { -+ abort(); -+ } -+ -+ if (eq_add(1,2,3,4) != 7) -+ { -+ abort(); -+ } -+ -+ if (eq_add(2,2,3,4) != 8) -+ { -+ abort(); -+ } -+ -+ if (eq_add(3,2,3,4) != 7) -+ { -+ abort(); -+ } -+ -+ if (ne_add(1,2,3,4) != 8) -+ { -+ abort(); -+ } -+ -+ if (ne_add(2,2,3,4) != 7) -+ { -+ abort(); -+ } -+ -+ if (ne_add(3,2,3,4) != 8) -+ { -+ abort(); -+ } -+ return 0; -+} - -Property changes on: gcc/testsuite/gcc.target/aarch64/adc-2.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/mneg-3.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/mneg-3.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/mneg-3.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,10 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+ -+int r; -+ -+void test (int a, int b) -+{ -+ /* { dg-final { scan-assembler "mneg\tw\[0-9\]*, w\[0-9\]*, w\[0-9\]*\n" } } */ -+ r = - (a * b); -+} - -Property changes on: gcc/testsuite/gcc.target/aarch64/mneg-3.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/vect.x -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/vect.x (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect.x (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,140 @@ -+typedef int *__restrict__ pRINT; -+typedef unsigned int *__restrict__ pRUINT; -+typedef long long *__restrict__ pRINT64; -+typedef unsigned long long *__restrict__ pRUINT64; -+ -+void test_orn (pRUINT a, pRUINT b, pRUINT c) -+{ -+ int i; -+ for (i = 0; i < 16; i++) -+ c[i] = a[i] | (~b[i]); -+} -+ -+void test_bic (pRUINT a, pRUINT b, pRUINT c) -+{ -+ int i; -+ for (i = 0; i < 16; i++) -+ c[i] = a[i] & (~b[i]); -+} -+ -+void mla (pRINT a, pRINT b, pRINT c) -+{ -+ int i; -+ for (i=0;i<16;i++) -+ c[i] += a[i] * b[i]; -+} -+ -+void mls (pRINT a, pRINT b, pRINT c) -+{ -+ int i; -+ for (i=0;i<16;i++) -+ c[i] -= a[i] * b[i]; -+} -+ -+void smax (pRINT a, pRINT b, pRINT c) -+{ -+ int i; -+ for (i=0;i<16;i++) -+ c[i] = (a[i] > b[i] ? a[i] : b[i]); -+} -+ -+void smin (pRINT a, pRINT b, pRINT c) -+{ -+ int i; -+ for (i=0;i<16;i++) -+ c[i] = (a[i] < b[i] ? a[i] : b[i]); -+} -+ -+void umax (pRUINT a, pRUINT b, pRUINT c) -+{ -+ int i; -+ for (i=0;i<16;i++) -+ c[i] = (a[i] > b[i] ? a[i] : b[i]); -+} -+ -+void umin (pRUINT a, pRUINT b, pRUINT c) -+{ -+ int i; -+ for (i=0;i<16;i++) -+ c[i] = (a[i] < b[i] ? a[i] : b[i]); -+} -+ -+unsigned int reduce_umax (pRUINT a) -+{ -+ int i; -+ unsigned int s = a[0]; -+ for (i = 1; i < 16; i++) -+ s = (s > a[i] ? s : a[i]); -+ -+ return s; -+} -+ -+unsigned int reduce_umin (pRUINT a) -+{ -+ int i; -+ unsigned int s = a[0]; -+ for (i = 1; i < 16; i++) -+ s = (s < a[i] ? s : a[i]); -+ -+ return s; -+} -+ -+int reduce_smax (pRINT a) -+{ -+ int i; -+ int s = a[0]; -+ for (i = 1; i < 16; i++) -+ s = (s > a[i] ? s : a[i]); -+ -+ return s; -+} -+ -+int reduce_smin (pRINT a) -+{ -+ int i; -+ int s = a[0]; -+ for (i = 1; i < 16; i++) -+ s = (s < a[i] ? s : a[i]); -+ -+ return s; -+} -+ -+unsigned int reduce_add_u32 (pRINT a) -+{ -+ int i; -+ unsigned int s = 0; -+ for (i = 0; i < 16; i++) -+ s += a[i]; -+ -+ return s; -+} -+ -+int reduce_add_s32 (pRINT a) -+{ -+ int i; -+ int s = 0; -+ for (i = 0; i < 16; i++) -+ s += a[i]; -+ -+ return s; -+} -+ -+unsigned long long reduce_add_u64 (pRUINT64 a) -+{ -+ int i; -+ unsigned long long s = 0; -+ for (i = 0; i < 16; i++) -+ s += a[i]; -+ -+ return s; -+} -+ -+long long reduce_add_s64 (pRINT64 a) -+{ -+ int i; -+ long long s = 0; -+ for (i = 0; i < 16; i++) -+ s += a[i]; -+ -+ return s; -+} -Index: gcc/testsuite/gcc.target/aarch64/extend.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/extend.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/extend.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,170 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+ -+int -+ldr_uxtw (int *arr, unsigned int i) -+{ -+ /* { dg-final { scan-assembler "ldr\tw\[0-9\]+,.*uxtw #?2]" } } */ -+ return arr[i]; -+} -+ -+int -+ldr_uxtw0 (char *arr, unsigned int i) -+{ -+ /* { dg-final { scan-assembler "ldr\tw\[0-9\]+,.*uxtw]" } } */ -+ return arr[i]; -+} -+ -+int -+ldr_sxtw (int *arr, int i) -+{ -+ /* { dg-final { scan-assembler "ldr\tw\[0-9\]+,.*sxtw #?2]" } } */ -+ return arr[i]; -+} -+ -+int -+ldr_sxtw0 (char *arr, int i) -+{ -+ /* { dg-final { scan-assembler "ldr\tw\[0-9\]+,.*sxtw]" } } */ -+ return arr[i]; -+} -+ -+unsigned long long -+adddi_uxtw (unsigned long long a, unsigned int i) -+{ -+ /* { dg-final { scan-assembler "add\tx\[0-9\]+,.*uxtw #?3" } } */ -+ return a + ((unsigned long long)i << 3); -+} -+ -+unsigned long long -+adddi_uxtw0 (unsigned long long a, unsigned int i) -+{ -+ /* { dg-final { scan-assembler "add\tx\[0-9\]+,.*uxtw\n" } } */ -+ return a + i; -+} -+ -+long long -+adddi_sxtw (long long a, int i) -+{ -+ /* { dg-final { scan-assembler "add\tx\[0-9\]+,.*sxtw #?3" } } */ -+ return a + ((long long)i << 3); -+} -+ -+long long -+adddi_sxtw0 (long long a, int i) -+{ -+ /* { dg-final { scan-assembler "add\tx\[0-9\]+,.*sxtw\n" } } */ -+ return a + i; -+} -+ -+unsigned long long -+subdi_uxtw (unsigned long long a, unsigned int i) -+{ -+ /* { dg-final { scan-assembler "sub\tx\[0-9\]+,.*uxtw #?3" } } */ -+ return a - ((unsigned long long)i << 3); -+} -+ -+unsigned long long -+subdi_uxtw0 (unsigned long long a, unsigned int i) -+{ -+ /* { dg-final { scan-assembler "sub\tx\[0-9\]+,.*uxtw\n" } } */ -+ return a - i; -+} -+ -+long long -+subdi_sxtw (long long a, int i) -+{ -+ /* { dg-final { scan-assembler "sub\tx\[0-9\]+,.*sxtw #?3" } } */ -+ return a - ((long long)i << 3); -+} -+ -+long long -+subdi_sxtw0 (long long a, int i) -+{ -+ /* { dg-final { scan-assembler "sub\tx\[0-9\]+,.*sxtw\n" } } */ -+ return a - (long long)i; -+} -+ -+unsigned long long -+subdi_uxth (unsigned long long a, unsigned short i) -+{ -+ /* { dg-final { scan-assembler "sub\tx\[0-9\]+,.*uxth #?1" } } */ -+ return a - ((unsigned long long)i << 1); -+} -+ -+unsigned long long -+subdi_uxth0 (unsigned long long a, unsigned short i) -+{ -+ /* { dg-final { scan-assembler "sub\tx\[0-9\]+,.*uxth\n" } } */ -+ return a - i; -+} -+ -+long long -+subdi_sxth (long long a, short i) -+{ -+ /* { dg-final { scan-assembler "sub\tx\[0-9\]+,.*sxth #?1" } } */ -+ return a - ((long long)i << 1); -+} -+ -+long long -+subdi_sxth0 (long long a, short i) -+{ -+ /* { dg-final { scan-assembler "sub\tx\[0-9\]+,.*sxth\n" } } */ -+ return a - (long long)i; -+} -+ -+unsigned int -+subsi_uxth (unsigned int a, unsigned short i) -+{ -+ /* { dg-final { scan-assembler "sub\tw\[0-9\]+,.*uxth #?1" } } */ -+ return a - ((unsigned int)i << 1); -+} -+ -+unsigned int -+subsi_uxth0 (unsigned int a, unsigned short i) -+{ -+ /* { dg-final { scan-assembler "sub\tw\[0-9\]+,.*uxth\n" } } */ -+ return a - i; -+} -+ -+int -+subsi_sxth (int a, short i) -+{ -+ /* { dg-final { scan-assembler "sub\tw\[0-9\]+,.*sxth #?1" } } */ -+ return a - ((int)i << 1); -+} -+ -+int -+subsi_sxth0 (int a, short i) -+{ -+ /* { dg-final { scan-assembler "sub\tw\[0-9\]+,.*sxth\n" } } */ -+ return a - (int)i; -+} -+ -+unsigned int -+addsi_uxth (unsigned int a, unsigned short i) -+{ -+ /* { dg-final { scan-assembler "add\tw\[0-9\]+,.*uxth #?1" } } */ -+ return a + ((unsigned int)i << 1); -+} -+ -+unsigned int -+addsi_uxth0 (unsigned int a, unsigned short i) -+{ -+ /* { dg-final { scan-assembler "add\tw\[0-9\]+,.*uxth\n" } } */ -+ return a + i; -+} -+ -+int -+addsi_sxth (int a, short i) -+{ -+ /* { dg-final { scan-assembler "add\tw\[0-9\]+,.*sxth #?1" } } */ -+ return a + ((int)i << 1); -+} -+ -+int -+addsi_sxth0 (int a, short i) -+{ -+ /* { dg-final { scan-assembler "add\tw\[0-9\]+,.*sxth\n" } } */ -+ return a + (int)i; -+} - -Property changes on: gcc/testsuite/gcc.target/aarch64/extend.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.target/aarch64/vect-fp.x -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-fp.x (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fp.x (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,44 @@ -+ -+typedef float F32; -+typedef double F64; -+typedef float *__restrict__ pRF32; -+typedef double *__restrict__ pRF64; -+ -+extern float fabsf (float); -+extern double fabs (double); -+ -+#define DEF3(fname, type, op) \ -+ void fname##_##type (pR##type a, \ -+ pR##type b, \ -+ pR##type c) \ -+ { \ -+ int i; \ -+ for (i=0; i<16; i++) \ -+ a[i] = b[i] op c[i]; \ -+ } -+ -+#define DEF2(fname, type, op) \ -+ void fname##_##type (pR##type a, \ -+ pR##type b) \ -+ { \ -+ int i; \ -+ for (i=0; i<16; i++) \ -+ a[i] = op(b[i]); \ -+ } -+ -+ -+#define DEFN3(fname, op) \ -+ DEF3 (fname, F32, op) \ -+ DEF3 (fname, F64, op) -+ -+#define DEFN2(fname, op) \ -+ DEF2 (fname, F32, op) \ -+ DEF2 (fname, F64, op) -+ -+DEFN3 (add, +) -+DEFN3 (sub, -) -+DEFN3 (mul, *) -+DEFN3 (div, /) -+DEFN2 (neg, -) -+DEF2 (abs, F32, fabsf) -+DEF2 (abs, F64, fabs) -Index: gcc/testsuite/gcc.target/aarch64/vect-abs.x -=================================================================== ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-abs.x (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-abs.x (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,36 @@ -+ -+extern int abs (int); -+extern long labs (long); -+ -+typedef signed char *__restrict__ pRINT8; -+typedef short *__restrict__ pRINT16; -+typedef int *__restrict__ pRINT32; -+typedef long *__restrict__ pRLONG; -+typedef long long *__restrict__ pRINT64; -+ -+#define DEF_ABS(size) void absolute_s##size (pRINT##size a, pRINT##size b) \ -+ { \ -+ int i; \ -+ for (i=0; i 0 ? b[i] : -b[i]); \ -+ } -+ -+DEF_ABS (8); -+DEF_ABS (16); -+DEF_ABS (32); -+DEF_ABS (64); -+ -+/* Test abs () vectorization. */ -+void absolute_s32_lib (pRINT32 a, pRINT32 b) -+{ -+ int i; -+ for (i=0; i */ - - /* { dg-do compile } */ --/* { dg-skip-if "No stabs" { mmix-*-* *-*-aix* alpha*-*-* hppa*64*-*-* ia64-*-* tile*-*-* *-*-vxworks* } { "*" } { "" } } */ -+/* { dg-skip-if "No stabs" { aarch64*-*-* mmix-*-* *-*-aix* alpha*-*-* hppa*64*-*-* ia64-*-* tile*-*-* *-*-vxworks* } { "*" } { "" } } */ - /* { dg-options "-gstabs" } */ - - int -Index: gcc/testsuite/gcc.dg/stack-usage-1.c -=================================================================== ---- a/src/gcc/testsuite/gcc.dg/stack-usage-1.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.dg/stack-usage-1.c (.../ARM/aarch64-4.7-branch) -@@ -7,7 +7,9 @@ - function FOO is reported as 256 or 264 in the stack usage (.su) file. - Then check that this is the actual stack usage in the assembly file. */ - --#if defined(__i386__) -+#if defined(__aarch64__) -+# define SIZE 256 /* No frame pointer for leaf functions (default) */ -+#elif defined(__i386__) - # define SIZE 248 - #elif defined(__x86_64__) - # ifndef _WIN64 -Index: gcc/testsuite/gcc.dg/torture/pr51106-2.s -=================================================================== ---- a/src/gcc/testsuite/gcc.dg/torture/pr51106-2.s (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.dg/torture/pr51106-2.s (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,2 @@ -+ .cpu generic -+ .file "pr51106-2.c" - -Property changes on: gcc/testsuite/gcc.dg/torture/pr51106-2.s -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/gcc.dg/20020312-2.c -=================================================================== ---- a/src/gcc/testsuite/gcc.dg/20020312-2.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.dg/20020312-2.c (.../ARM/aarch64-4.7-branch) -@@ -92,6 +92,8 @@ - # else - # define PIC_REG "gr17" - #endif -+#elif defined (__aarch64__) -+/* No pic register -- yet. */ - #else - # error "Modify the test for your target." - #endif -Index: gcc/testsuite/gcc.dg/builtin-apply2.c -=================================================================== ---- a/src/gcc/testsuite/gcc.dg/builtin-apply2.c (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/gcc.dg/builtin-apply2.c (.../ARM/aarch64-4.7-branch) -@@ -1,5 +1,5 @@ - /* { dg-do run } */ --/* { dg-skip-if "Variadic funcs have all args on stack. Normal funcs have args in registers." { "avr-*-*" } { "*" } { "" } } */ -+/* { dg-skip-if "Variadic funcs have all args on stack. Normal funcs have args in registers." { "aarch64*-*-* avr-*-* " } { "*" } { "" } } */ - /* { dg-skip-if "Variadic funcs use Base AAPCS. Normal funcs use VFP variant." { "arm*-*-*" } { "-mfloat-abi=hard" } { "" } } */ - - /* PR target/12503 */ -Index: gcc/testsuite/g++.dg/abi/aarch64_guard1.C -=================================================================== ---- a/src/gcc/testsuite/g++.dg/abi/aarch64_guard1.C (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/g++.dg/abi/aarch64_guard1.C (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,17 @@ -+// Check that the initialization guard variable is an 8-byte aligned, -+// 8-byte doubleword and that only the least significant bit is used -+// for initialization guard variables. -+// { dg-do compile { target aarch64*-*-* } } -+// { dg-options "-O -fdump-tree-original" } -+ -+int bar(); -+ -+int *foo () -+{ -+ static int x = bar (); -+ return &x; -+} -+ -+// { dg-final { scan-assembler _ZGVZ3foovE1x,8,8 } } -+// { dg-final { scan-tree-dump "_ZGVZ3foovE1x & 1" "original" } } -+// { dg-final { cleanup-tree-dump "original" } } - -Property changes on: gcc/testsuite/g++.dg/abi/aarch64_guard1.C -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/testsuite/g++.dg/other/pr23205-2.C -=================================================================== ---- a/src/gcc/testsuite/g++.dg/other/pr23205-2.C (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/g++.dg/other/pr23205-2.C (.../ARM/aarch64-4.7-branch) -@@ -1,5 +1,5 @@ - /* { dg-do compile } */ --/* { dg-skip-if "No stabs" { mmix-*-* *-*-aix* alpha*-*-* hppa*64*-*-* ia64-*-* tile*-*-* } { "*" } { "" } } */ -+/* { dg-skip-if "No stabs" { aarch64*-*-* mmix-*-* *-*-aix* alpha*-*-* hppa*64*-*-* ia64-*-* tile*-*-* } { "*" } { "" } } */ - /* { dg-options "-gstabs+ -fno-eliminate-unused-debug-types -ftoplevel-reorder" } */ - - const int foobar = 4; -Index: gcc/testsuite/g++.dg/other/PR23205.C -=================================================================== ---- a/src/gcc/testsuite/g++.dg/other/PR23205.C (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/g++.dg/other/PR23205.C (.../ARM/aarch64-4.7-branch) -@@ -1,5 +1,5 @@ - /* { dg-do compile } */ --/* { dg-skip-if "No stabs" { mmix-*-* *-*-aix* alpha*-*-* hppa*64*-*-* ia64-*-* tile*-*-* *-*-vxworks } { "*" } { "" } } */ -+/* { dg-skip-if "No stabs" { aarch64*-*-* mmix-*-* *-*-aix* alpha*-*-* hppa*64*-*-* ia64-*-* tile*-*-* *-*-vxworks } { "*" } { "" } } */ - /* { dg-options "-gstabs+ -fno-eliminate-unused-debug-types" } */ - - const int foobar = 4; -Index: gcc/testsuite/ChangeLog.aarch64 -=================================================================== ---- a/src/gcc/testsuite/ChangeLog.aarch64 (.../gcc-4_7-branch) -+++ b/src/gcc/testsuite/ChangeLog.aarch64 (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,178 @@ -+2012-09-18 Ian Bolton -+ -+ * gcc.target/aarch64/clrsb.c: New test. -+ * gcc.target/aarch64/clz.c: New test. -+ * gcc.target/aarch64/ctz.c: New test. -+ -+2012-09-17 Ian Bolton -+ -+ * gcc.target/aarch64/ffs.c: New test. -+ -+2012-09-17 Ian Bolton -+ -+ * gcc.target/aarch64/fmadd.c: Added extra tests. -+ * gcc.target/aarch64/fnmadd-fastmath.c: New test. -+ -+2012-05-25 Ian Bolton -+ Jim MacArthur -+ Marcus Shawcroft -+ Nigel Stephens -+ Ramana Radhakrishnan -+ Richard Earnshaw -+ Sofiane Naci -+ Stephen Thomas -+ Tejas Belagod -+ Yufeng Zhang -+ -+ * gcc.target/aarch64/aapcs/aapcs64.exp: New file. -+ * gcc.target/aarch64/aapcs/abitest-2.h: New file. -+ * gcc.target/aarch64/aapcs/abitest-common.h: New file. -+ * gcc.target/aarch64/aapcs/abitest.S: New file. -+ * gcc.target/aarch64/aapcs/abitest.h: New file. -+ * gcc.target/aarch64/aapcs/func-ret-1.c: New file. -+ * gcc.target/aarch64/aapcs/func-ret-2.c: New file. -+ * gcc.target/aarch64/aapcs/func-ret-3.c: New file. -+ * gcc.target/aarch64/aapcs/func-ret-3.x: New file. -+ * gcc.target/aarch64/aapcs/func-ret-4.c: New file. -+ * gcc.target/aarch64/aapcs/func-ret-4.x: New file. -+ * gcc.target/aarch64/aapcs/ice_1.c: New file. -+ * gcc.target/aarch64/aapcs/ice_2.c: New file. -+ * gcc.target/aarch64/aapcs/ice_3.c: New file. -+ * gcc.target/aarch64/aapcs/ice_4.c: New file. -+ * gcc.target/aarch64/aapcs/ice_5.c: New file. -+ * gcc.target/aarch64/aapcs/macro-def.h: New file. -+ * gcc.target/aarch64/aapcs/test_1.c: New file. -+ * gcc.target/aarch64/aapcs/test_10.c: New file. -+ * gcc.target/aarch64/aapcs/test_11.c: New file. -+ * gcc.target/aarch64/aapcs/test_12.c: New file. -+ * gcc.target/aarch64/aapcs/test_13.c: New file. -+ * gcc.target/aarch64/aapcs/test_14.c: New file. -+ * gcc.target/aarch64/aapcs/test_15.c: New file. -+ * gcc.target/aarch64/aapcs/test_16.c: New file. -+ * gcc.target/aarch64/aapcs/test_17.c: New file. -+ * gcc.target/aarch64/aapcs/test_18.c: New file. -+ * gcc.target/aarch64/aapcs/test_19.c: New file. -+ * gcc.target/aarch64/aapcs/test_2.c: New file. -+ * gcc.target/aarch64/aapcs/test_20.c: New file. -+ * gcc.target/aarch64/aapcs/test_21.c: New file. -+ * gcc.target/aarch64/aapcs/test_22.c: New file. -+ * gcc.target/aarch64/aapcs/test_23.c: New file. -+ * gcc.target/aarch64/aapcs/test_24.c: New file. -+ * gcc.target/aarch64/aapcs/test_25.c: New file. -+ * gcc.target/aarch64/aapcs/test_26.c: New file. -+ * gcc.target/aarch64/aapcs/test_3.c: New file. -+ * gcc.target/aarch64/aapcs/test_4.c: New file. -+ * gcc.target/aarch64/aapcs/test_5.c: New file. -+ * gcc.target/aarch64/aapcs/test_6.c: New file. -+ * gcc.target/aarch64/aapcs/test_7.c: New file. -+ * gcc.target/aarch64/aapcs/test_8.c: New file. -+ * gcc.target/aarch64/aapcs/test_9.c: New file. -+ * gcc.target/aarch64/aapcs/test_align-1.c: New file. -+ * gcc.target/aarch64/aapcs/test_align-2.c: New file. -+ * gcc.target/aarch64/aapcs/test_align-3.c: New file. -+ * gcc.target/aarch64/aapcs/test_align-4.c: New file. -+ * gcc.target/aarch64/aapcs/test_complex.c: New file. -+ * gcc.target/aarch64/aapcs/test_int128.c: New file. -+ * gcc.target/aarch64/aapcs/test_quad_double.c: New file. -+ * gcc.target/aarch64/aapcs/type-def.h: New file. -+ * gcc.target/aarch64/aapcs/va_arg-1.c: New file. -+ * gcc.target/aarch64/aapcs/va_arg-10.c: New file. -+ * gcc.target/aarch64/aapcs/va_arg-11.c: New file. -+ * gcc.target/aarch64/aapcs/va_arg-12.c: New file. -+ * gcc.target/aarch64/aapcs/va_arg-2.c: New file. -+ * gcc.target/aarch64/aapcs/va_arg-3.c: New file. -+ * gcc.target/aarch64/aapcs/va_arg-4.c: New file. -+ * gcc.target/aarch64/aapcs/va_arg-5.c: New file. -+ * gcc.target/aarch64/aapcs/va_arg-6.c: New file. -+ * gcc.target/aarch64/aapcs/va_arg-7.c: New file. -+ * gcc.target/aarch64/aapcs/va_arg-8.c: New file. -+ * gcc.target/aarch64/aapcs/va_arg-9.c: New file. -+ * gcc.target/aarch64/aapcs/validate_memory.h: New file. -+ * gcc.target/aarch64/aarch64.exp: New file. -+ * gcc.target/aarch64/adc-1.c: New file. -+ * gcc.target/aarch64/adc-2.c: New file. -+ * gcc.target/aarch64/asm-1.c: New file. -+ * gcc.target/aarch64/csinc-1.c: New file. -+ * gcc.target/aarch64/csinv-1.c: New file. -+ * gcc.target/aarch64/csneg-1.c: New file. -+ * gcc.target/aarch64/extend.c: New file. -+ * gcc.target/aarch64/fcvt.x: New file. -+ * gcc.target/aarch64/fcvt_double_int.c: New file. -+ * gcc.target/aarch64/fcvt_double_long.c: New file. -+ * gcc.target/aarch64/fcvt_double_uint.c: New file. -+ * gcc.target/aarch64/fcvt_double_ulong.c: New file. -+ * gcc.target/aarch64/fcvt_float_int.c: New file. -+ * gcc.target/aarch64/fcvt_float_long.c: New file. -+ * gcc.target/aarch64/fcvt_float_uint.c: New file. -+ * gcc.target/aarch64/fcvt_float_ulong.c: New file. -+ * gcc.target/aarch64/fmadd.c: New file. -+ * gcc.target/aarch64/frint.x: New file. -+ * gcc.target/aarch64/frint_double.c: New file. -+ * gcc.target/aarch64/frint_float.c: New file. -+ * gcc.target/aarch64/index.c: New file. -+ * gcc.target/aarch64/mneg-1.c: New file. -+ * gcc.target/aarch64/mneg-2.c: New file. -+ * gcc.target/aarch64/mneg-3.c: New file. -+ * gcc.target/aarch64/mnegl-1.c: New file. -+ * gcc.target/aarch64/mnegl-2.c: New file. -+ * gcc.target/aarch64/narrow_high-intrinsics.c: New file. -+ * gcc.target/aarch64/pic-constantpool1.c: New file. -+ * gcc.target/aarch64/pic-symrefplus.c: New file. -+ * gcc.target/aarch64/reload-valid-spoff.c: New file. -+ * gcc.target/aarch64/scalar_intrinsics.c: New file. -+ * gcc.target/aarch64/table-intrinsics.c: New file. -+ * gcc.target/aarch64/tst-1.c: New file. -+ * gcc.target/aarch64/vect-abs-compile.c: New file. -+ * gcc.target/aarch64/vect-abs.c: New file. -+ * gcc.target/aarch64/vect-abs.x: New file. -+ * gcc.target/aarch64/vect-compile.c: New file. -+ * gcc.target/aarch64/vect-faddv-compile.c: New file. -+ * gcc.target/aarch64/vect-faddv.c: New file. -+ * gcc.target/aarch64/vect-faddv.x: New file. -+ * gcc.target/aarch64/vect-fmax-fmin-compile.c: New file. -+ * gcc.target/aarch64/vect-fmax-fmin.c: New file. -+ * gcc.target/aarch64/vect-fmax-fmin.x: New file. -+ * gcc.target/aarch64/vect-fmaxv-fminv-compile.c: New file. -+ * gcc.target/aarch64/vect-fmaxv-fminv.x: New file. -+ * gcc.target/aarch64/vect-fp-compile.c: New file. -+ * gcc.target/aarch64/vect-fp.c: New file. -+ * gcc.target/aarch64/vect-fp.x: New file. -+ * gcc.target/aarch64/vect-mull-compile.c: New file. -+ * gcc.target/aarch64/vect-mull.c: New file. -+ * gcc.target/aarch64/vect-mull.x: New file. -+ * gcc.target/aarch64/vect.c: New file. -+ * gcc.target/aarch64/vect.x: New file. -+ * gcc.target/aarch64/vector_intrinsics.c: New file. -+ * gcc.target/aarch64/vfp-1.c: New file. -+ * gcc.target/aarch64/volatile-bitfields-1.c: New file. -+ * gcc.target/aarch64/volatile-bitfields-2.c: New file. -+ * gcc.target/aarch64/volatile-bitfields-3.c: New file. -+ * lib/target-supports.exp -+ (check_profiling_available): Add AArch64. -+ (check_effective_target_vect_int): Likewise. -+ (check_effective_target_vect_shift): Likewise. -+ (check_effective_target_vect_float): Likewise. -+ (check_effective_target_vect_double): Likewise. -+ (check_effective_target_vect_widen_mult_qi_to_hi): Likewise. -+ (check_effective_target_vect_widen_mult_hi_to_si): Likewise. -+ (check_effective_target_vect_pack_trunc): Likewise. -+ (check_effective_target_vect_unpack): Likewise. -+ (check_effective_target_vect_hw_misalign): Likewise. -+ (check_effective_target_vect_short_mult): Likewise. -+ (check_effective_target_vect_int_mult): Likewise. -+ (check_effective_target_sync_int_long): Likewise. -+ (check_effective_target_sync_char_short): Likewise. -+ (check_vect_support_and_set_flags): Likewise. -+ * g++.dg/abi/aarch64_guard1.C: New file. -+ * g++.dg/other/PR23205.C: Enable aarch64. -+ * g++.dg/other/pr23205-2.C: Likewise. -+ * g++.old-deja/g++.abi/ptrmem.C: Likewise. -+ * gcc.c-torture/execute/20101011-1.c: Likewise. -+ * gcc.dg/torture/fp-int-convert-float128-timode.c: Likewise. -+ * gcc.dg/torture/fp-int-convert-float128.c: Likewise. -+ * gcc.dg/20020312-2.c: Likewise. -+ * gcc.dg/20040813-1.c: Likewise. -+ * gcc.dg/builtin-apply2.c: Likewise. -+ * gcc.dg/const-float128-ped.c: Likewise. -+ * gcc.dg/const-float128.c: Likewise. -+ * gcc.dg/stack-usage-1.c: Likewise. -Index: gcc/common/config/aarch64/aarch64-common.c -=================================================================== ---- a/src/gcc/common/config/aarch64/aarch64-common.c (.../gcc-4_7-branch) -+++ b/src/gcc/common/config/aarch64/aarch64-common.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,77 @@ -+/* Common hooks for AArch64. -+ Copyright (C) 2012 Free Software Foundation, Inc. -+ Contributed by ARM Ltd. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+#include "config.h" -+#include "system.h" -+#include "coretypes.h" -+#include "tm.h" -+#include "tm_p.h" -+#include "common/common-target.h" -+#include "common/common-target-def.h" -+#include "opts.h" -+#include "flags.h" -+ -+#ifdef TARGET_BIG_ENDIAN_DEFAULT -+#undef TARGET_DEFAULT_TARGET_FLAGS -+#define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END) -+#endif -+ -+#undef TARGET_HANDLE_OPTION -+#define TARGET_HANDLE_OPTION aarch64_handle_option -+ -+/* Implement TARGET_HANDLE_OPTION. -+ This function handles the target specific options for CPU/target selection. -+ -+ march wins over mcpu, so when march is defined, mcpu takes the same value, -+ otherwise march remains undefined. mtune can be used with either march or -+ mcpu. If march and mcpu are used together, the rightmost option wins. -+ mtune can be used with either march or mcpu. */ -+ -+static bool -+aarch64_handle_option (struct gcc_options *opts, -+ struct gcc_options *opts_set ATTRIBUTE_UNUSED, -+ const struct cl_decoded_option *decoded, -+ location_t loc ATTRIBUTE_UNUSED) -+{ -+ size_t code = decoded->opt_index; -+ const char *arg = decoded->arg; -+ -+ switch (code) -+ { -+ case OPT_march_: -+ opts->x_aarch64_arch_string = arg; -+ opts->x_aarch64_cpu_string = arg; -+ return true; -+ -+ case OPT_mcpu_: -+ opts->x_aarch64_cpu_string = arg; -+ opts->x_aarch64_arch_string = NULL; -+ return true; -+ -+ case OPT_mtune_: -+ opts->x_aarch64_tune_string = arg; -+ return true; -+ -+ default: -+ return true; -+ } -+} -+ -+struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER; - -Property changes on: gcc/common/config/aarch64/aarch64-common.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/configure.ac -=================================================================== ---- a/src/gcc/configure.ac (.../gcc-4_7-branch) -+++ b/src/gcc/configure.ac (.../ARM/aarch64-4.7-branch) -@@ -2966,6 +2966,19 @@ - tls_first_minor=19 - tls_as_opt='--fatal-warnings' - ;; -+ aarch64*-*-*) -+ conftest_s=' -+ .section ".tdata","awT",%progbits -+foo: .long 25 -+ .text -+ adrp x0, :tlsgd:x -+ add x0, x0, #:tlsgd_lo12:x -+ bl __tls_get_addr -+ nop' -+ tls_first_major=2 -+ tls_first_minor=20 -+ tls_as_opt='--fatal-warnings' -+ ;; - powerpc-*-*) - conftest_s=' - .section ".tdata","awT",@progbits -Index: gcc/read-rtl.c -=================================================================== ---- a/src/gcc/read-rtl.c (.../gcc-4_7-branch) -+++ b/src/gcc/read-rtl.c (.../ARM/aarch64-4.7-branch) -@@ -94,6 +94,26 @@ - #define BELLWETHER_CODE(CODE) \ - ((CODE) < NUM_RTX_CODE ? CODE : bellwether_codes[CODE - NUM_RTX_CODE]) - -+/* One element in the (rtx, opno) pair list. */ -+struct rtx_list { -+ /* rtx. */ -+ rtx x; -+ /* Position of the operand to replace. */ -+ int opno; -+}; -+ -+/* A structure to track which rtx uses which int iterator. */ -+struct int_iterator_mapping { -+ /* Iterator. */ -+ struct mapping *iterator; -+ /* list of rtx using ITERATOR. */ -+ struct rtx_list *rtxs; -+ int num_rtx; -+}; -+ -+static struct int_iterator_mapping *int_iterator_data; -+static int num_int_iterator_data; -+ - static int find_mode (const char *); - static bool uses_mode_iterator_p (rtx, int); - static void apply_mode_iterator (rtx, int); -@@ -121,8 +141,8 @@ - static rtx read_nested_rtx (struct map_value **); - static rtx read_rtx_variadic (struct map_value **, rtx); - --/* The mode and code iterator structures. */ --static struct iterator_group modes, codes; -+/* The mode, code and int iterator structures. */ -+static struct iterator_group modes, codes, ints; - - /* Index I is the value of BELLWETHER_CODE (I + NUM_RTX_CODE). */ - static enum rtx_code *bellwether_codes; -@@ -179,6 +199,59 @@ - PUT_CODE (x, (enum rtx_code) code); - } - -+/* Since GCC does not construct a table of valid constants, -+ we have to accept any int as valid. No cross-checking can -+ be done. */ -+static int -+find_int (const char *name) -+{ -+ char *endptr; -+ int ret; -+ -+ if (ISDIGIT (*name)) -+ { -+ ret = strtol (name, &endptr, 0); -+ gcc_assert (*endptr == '\0'); -+ return ret; -+ } -+ else -+ fatal_with_file_and_line ("unknown int `%s'", name); -+} -+ -+static bool -+dummy_uses_int_iterator (rtx x ATTRIBUTE_UNUSED, int index ATTRIBUTE_UNUSED) -+{ -+ return false; -+} -+ -+static void -+dummy_apply_int_iterator (rtx x ATTRIBUTE_UNUSED, int code ATTRIBUTE_UNUSED) -+{ -+ /* Do nothing. */ -+} -+ -+/* Stand-alone int iterator usage-checking function. */ -+static bool -+uses_int_iterator_p (rtx x, struct mapping *iterator, int opno) -+{ -+ int i; -+ for (i=0; i < num_int_iterator_data; i++) -+ if (int_iterator_data[i].iterator->group == iterator->group && -+ int_iterator_data[i].iterator->index == iterator->index) -+ { -+ /* Found an existing entry. Check if X is in its list. */ -+ struct int_iterator_mapping it = int_iterator_data[i]; -+ int j; -+ -+ for (j=0; j < it.num_rtx; j++) -+ { -+ if (it.rtxs[j].x == x && it.rtxs[j].opno == opno) -+ return true; -+ } -+ } -+ return false; -+} -+ - /* Map a code or mode attribute string P to the underlying string for - ITERATOR and VALUE. */ - -@@ -341,7 +414,9 @@ - x = rtx_alloc (bellwether_code); - memcpy (x, original, RTX_CODE_SIZE (bellwether_code)); - -- /* Change the mode or code itself. */ -+ /* Change the mode or code itself. -+ For int iterators, apply_iterator () does nothing. This is -+ because we want to apply int iterators to operands below. */ - group = iterator->group; - if (group->uses_iterator_p (x, iterator->index + group->num_builtins)) - group->apply_iterator (x, value); -@@ -379,6 +454,10 @@ - unknown_mode_attr); - } - break; -+ case 'i': -+ if (uses_int_iterator_p (original, iterator, i)) -+ XINT (x, i) = value; -+ break; - - default: - break; -@@ -419,6 +498,10 @@ - return true; - break; - -+ case 'i': -+ if (uses_int_iterator_p (x, iterator, i)) -+ return true; -+ - default: - break; - } -@@ -480,6 +563,7 @@ - - iterator = (struct mapping *) *slot; - for (elem = mtd->queue; elem != 0; elem = XEXP (elem, 1)) -+ { - if (uses_iterator_p (XEXP (elem, 0), iterator)) - { - /* For each iterator we expand, we set UNKNOWN_MODE_ATTR to NULL. -@@ -509,6 +593,7 @@ - XEXP (elem, 0) = x; - } - } -+ } - return 1; - } - -@@ -553,7 +638,7 @@ - return &value->next; - } - --/* Do one-time initialization of the mode and code attributes. */ -+/* Do one-time initialization of the mode, code and int attributes. */ - - static void - initialize_iterators (void) -@@ -579,6 +664,15 @@ - codes.uses_iterator_p = uses_code_iterator_p; - codes.apply_iterator = apply_code_iterator; - -+ ints.attrs = htab_create (13, leading_string_hash, leading_string_eq_p, 0); -+ ints.iterators = htab_create (13, leading_string_hash, -+ leading_string_eq_p, 0); -+ ints.num_builtins = 0; -+ ints.find_builtin = find_int; -+ ints.uses_iterator_p = dummy_uses_int_iterator; -+ ints.apply_iterator = dummy_apply_int_iterator; -+ num_int_iterator_data = 0; -+ - lower = add_mapping (&modes, modes.attrs, "mode"); - upper = add_mapping (&modes, modes.attrs, "MODE"); - lower_ptr = &lower->values; -@@ -728,6 +822,61 @@ - return group->find_builtin (name); - } - -+/* We cannot use the same design as code and mode iterators as ints -+ can be any arbitrary number and there is no way to represent each -+ int iterator's placeholder with a unique numeric identifier. Therefore -+ we create a (rtx *, op, iterator *) triplet database. */ -+ -+static struct mapping * -+find_int_iterator (struct iterator_group *group, const char *name) -+{ -+ struct mapping *m; -+ -+ m = (struct mapping *) htab_find (group->iterators, &name); -+ if (m == 0) -+ fatal_with_file_and_line ("invalid iterator \"%s\"\n", name); -+ return m; -+} -+ -+/* Add to triplet-database for int iterators. */ -+static void -+add_int_iterator (struct mapping *iterator, rtx x, int opno) -+{ -+ -+ /* Find iterator in int_iterator_data. If already present, -+ add this R to its list of rtxs. If not present, create -+ a new entry for INT_ITERATOR_DATA and add the R to its -+ rtx list. */ -+ int i; -+ for (i=0; i < num_int_iterator_data; i++) -+ if (int_iterator_data[i].iterator->index == iterator->index) -+ { -+ /* Found an existing entry. Add rtx to this iterator's list. */ -+ int_iterator_data[i].rtxs = -+ XRESIZEVEC (struct rtx_list, -+ int_iterator_data[i].rtxs, -+ int_iterator_data[i].num_rtx + 1); -+ int_iterator_data[i].rtxs[int_iterator_data[i].num_rtx].x = x; -+ int_iterator_data[i].rtxs[int_iterator_data[i].num_rtx].opno = opno; -+ int_iterator_data[i].num_rtx++; -+ return; -+ } -+ -+ /* New INT_ITERATOR_DATA entry. */ -+ if (num_int_iterator_data == 0) -+ int_iterator_data = XNEWVEC (struct int_iterator_mapping, 1); -+ else -+ int_iterator_data = XRESIZEVEC (struct int_iterator_mapping, -+ int_iterator_data, -+ num_int_iterator_data + 1); -+ int_iterator_data[num_int_iterator_data].iterator = iterator; -+ int_iterator_data[num_int_iterator_data].rtxs = XNEWVEC (struct rtx_list, 1); -+ int_iterator_data[num_int_iterator_data].rtxs[0].x = x; -+ int_iterator_data[num_int_iterator_data].rtxs[0].opno = opno; -+ int_iterator_data[num_int_iterator_data].num_rtx = 1; -+ num_int_iterator_data++; -+} -+ - /* Finish reading a declaration of the form: - - (define... [ ... ]) -@@ -817,6 +966,7 @@ - static rtx queue_head; - struct map_value *mode_maps; - struct iterator_traverse_data mtd; -+ int i; - - /* Do one-time initialization. */ - if (queue_head == 0) -@@ -852,7 +1002,18 @@ - check_code_iterator (read_mapping (&codes, codes.iterators)); - return false; - } -+ if (strcmp (rtx_name, "define_int_attr") == 0) -+ { -+ read_mapping (&ints, ints.attrs); -+ return false; -+ } -+ if (strcmp (rtx_name, "define_int_iterator") == 0) -+ { -+ read_mapping (&ints, ints.iterators); -+ return false; -+ } - -+ - mode_maps = 0; - XEXP (queue_head, 0) = read_rtx_code (rtx_name, &mode_maps); - XEXP (queue_head, 1) = 0; -@@ -860,6 +1021,15 @@ - mtd.queue = queue_head; - mtd.mode_maps = mode_maps; - mtd.unknown_mode_attr = mode_maps ? mode_maps->string : NULL; -+ htab_traverse (ints.iterators, apply_iterator_traverse, &mtd); -+ /* Free used memory from recording int iterator usage. */ -+ for (i=0; i < num_int_iterator_data; i++) -+ if (int_iterator_data[i].num_rtx > 0) -+ XDELETEVEC (int_iterator_data[i].rtxs); -+ if (num_int_iterator_data > 0) -+ XDELETEVEC (int_iterator_data); -+ num_int_iterator_data = 0; -+ - htab_traverse (modes.iterators, apply_iterator_traverse, &mtd); - htab_traverse (codes.iterators, apply_iterator_traverse, &mtd); - if (mtd.unknown_mode_attr) -@@ -1057,14 +1227,30 @@ - XWINT (return_rtx, i) = tmp_wide; - break; - -- case 'i': - case 'n': -- read_name (&name); - validate_const_int (name.string); - tmp_int = atoi (name.string); - XINT (return_rtx, i) = tmp_int; - break; -- -+ case 'i': -+ /* Can be an iterator or an integer constant. */ -+ read_name (&name); -+ if (!ISDIGIT (name.string[0])) -+ { -+ struct mapping *iterator; -+ /* An iterator. */ -+ iterator = find_int_iterator (&ints, name.string); -+ /* Build (iterator, rtx, op) triplet-database. */ -+ add_int_iterator (iterator, return_rtx, i); -+ } -+ else -+ { -+ /* A numeric constant. */ -+ validate_const_int (name.string); -+ tmp_int = atoi (name.string); -+ XINT (return_rtx, i) = tmp_int; -+ } -+ break; - default: - gcc_unreachable (); - } -Index: gcc/config.gcc -=================================================================== ---- a/src/gcc/config.gcc (.../gcc-4_7-branch) -+++ b/src/gcc/config.gcc (.../ARM/aarch64-4.7-branch) -@@ -316,6 +316,13 @@ - tmake_file=m32c/t-m32c - target_has_targetm_common=no - ;; -+aarch64*-*-*) -+ cpu_type=aarch64 -+ need_64bit_hwint=yes -+ extra_headers="arm_neon.h" -+ extra_objs="aarch64-builtins.o" -+ target_has_targetm_common=yes -+ ;; - alpha*-*-*) - cpu_type=alpha - need_64bit_hwint=yes -@@ -769,6 +776,27 @@ - esac - - case ${target} in -+aarch64*-*-elf) -+ tm_file="${tm_file} dbxelf.h elfos.h newlib-stdint.h" -+ tm_file="${tm_file} aarch64/aarch64-elf.h aarch64/aarch64-elf-raw.h" -+ tmake_file="${tmake_file} aarch64/t-aarch64" -+ use_gcc_stdint=wrap -+ case $target in -+ aarch64_be-*) -+ tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1" -+ ;; -+ esac -+ ;; -+aarch64*-*-linux*) -+ tm_file="${tm_file} dbxelf.h elfos.h gnu-user.h linux.h glibc-stdint.h" -+ tm_file="${tm_file} aarch64/aarch64-elf.h aarch64/aarch64-linux.h" -+ tmake_file="${tmake_file} aarch64/t-aarch64 aarch64/t-aarch64-linux" -+ case $target in -+ aarch64_be-*) -+ tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1" -+ ;; -+ esac -+ ;; - alpha*-*-linux*) - tm_file="${tm_file} alpha/elf.h alpha/linux.h alpha/linux-elf.h glibc-stdint.h" - extra_options="${extra_options} alpha/elf.opt" -@@ -3023,6 +3051,92 @@ - - supported_defaults= - case "${target}" in -+ aarch64*-*-*) -+ supported_defaults="cpu arch" -+ for which in cpu arch; do -+ -+ eval "val=\$with_$which" -+ base_val=`echo $val | sed -e 's/\+.*//'` -+ ext_val=`echo $val | sed -e 's/[a-z0-9\-]\+//'` -+ -+ if [ $which = arch ]; then -+ def=aarch64-arches.def -+ pattern=AARCH64_ARCH -+ else -+ def=aarch64-cores.def -+ pattern=AARCH64_CORE -+ fi -+ -+ ext_mask=AARCH64_CPU_DEFAULT_FLAGS -+ -+ # Find the base CPU or ARCH id in aarch64-cores.def or -+ # aarch64-arches.def -+ if [ x"$base_val" = x ] \ -+ || grep "^$pattern(\"$base_val\"," \ -+ ${srcdir}/config/aarch64/$def \ -+ > /dev/null; then -+ -+ if [ $which = arch ]; then -+ base_id=`grep "^$pattern(\"$base_val\"," \ -+ ${srcdir}/config/aarch64/$def | \ -+ sed -e 's/^[^,]*,[ ]*//' | \ -+ sed -e 's/,.*$//'` -+ else -+ base_id=`grep "^$pattern(\"$base_val\"," \ -+ ${srcdir}/config/aarch64/$def | \ -+ sed -e 's/^[^,]*,[ ]*//' | \ -+ sed -e 's/,.*$//'` -+ fi -+ -+ while [ x"$ext_val" != x ] -+ do -+ ext_val=`echo $ext_val | sed -e 's/\+//'` -+ ext=`echo $ext_val | sed -e 's/\+.*//'` -+ base_ext=`echo $ext | sed -e 's/^no//'` -+ -+ if [ x"$base_ext" = x ] \ -+ || grep "^AARCH64_OPT_EXTENSION(\"$base_ext\"," \ -+ ${srcdir}/config/aarch64/aarch64-option-extensions.def \ -+ > /dev/null; then -+ -+ ext_on=`grep "^AARCH64_OPT_EXTENSION(\"$base_ext\"," \ -+ ${srcdir}/config/aarch64/aarch64-option-extensions.def | \ -+ sed -e 's/^[^,]*,[ ]*//' | \ -+ sed -e 's/,.*$//'` -+ ext_off=`grep "^AARCH64_OPT_EXTENSION(\"$base_ext\"," \ -+ ${srcdir}/config/aarch64/aarch64-option-extensions.def | \ -+ sed -e 's/^[^,]*,[ ]*[^,]*,[ ]*//' | \ -+ sed -e 's/,.*$//' | \ -+ sed -e 's/).*$//'` -+ -+ if [ $ext = $base_ext ]; then -+ # Adding extension -+ ext_mask="("$ext_mask") | ("$ext_on")" -+ else -+ # Removing extension -+ ext_mask="("$ext_mask") & ~("$ext_off")" -+ fi -+ -+ true -+ else -+ echo "Unknown extension used in --with-$which=$val" 1>&2 -+ exit 1 -+ fi -+ ext_val=`echo $ext_val | sed -e 's/[a-z0-9]\+//'` -+ done -+ -+ ext_mask="(("$ext_mask") << 6)" -+ if [ x"$base_id" != x ]; then -+ target_cpu_cname="TARGET_CPU_$base_id | $ext_mask" -+ fi -+ true -+ else -+ echo "Unknown $which used in --with-$which=$val" 1>&2 -+ exit 1 -+ fi -+ done -+ ;; -+ - alpha*-*-*) - supported_defaults="cpu tune" - for which in cpu tune; do -@@ -3511,6 +3625,15 @@ - # Set some miscellaneous flags for particular targets. - target_cpu_default2= - case ${target} in -+ aarch64*-*-*) -+ if test x$target_cpu_cname = x -+ then -+ target_cpu_default2=TARGET_CPU_generic -+ else -+ target_cpu_default2=$target_cpu_cname -+ fi -+ ;; -+ - alpha*-*-*) - if test x$gas = xyes - then -Index: gcc/config/aarch64/aarch64-simd.md -=================================================================== ---- a/src/gcc/config/aarch64/aarch64-simd.md (.../gcc-4_7-branch) -+++ b/src/gcc/config/aarch64/aarch64-simd.md (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,2764 @@ -+;; Machine description for AArch64 AdvSIMD architecture. -+;; Copyright (C) 2011, 2012 Free Software Foundation, Inc. -+;; Contributed by ARM Ltd. -+;; -+;; This file is part of GCC. -+;; -+;; GCC is free software; you can redistribute it and/or modify it -+;; under the terms of the GNU General Public License as published by -+;; the Free Software Foundation; either version 3, or (at your option) -+;; any later version. -+;; -+;; GCC is distributed in the hope that it will be useful, but -+;; WITHOUT ANY WARRANTY; without even the implied warranty of -+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+;; General Public License for more details. -+;; -+;; You should have received a copy of the GNU General Public License -+;; along with GCC; see the file COPYING3. If not see -+;; . -+ -+ -+; Main data types used by the insntructions -+ -+(define_attr "simd_mode" "unknown,none,V8QI,V16QI,V4HI,V8HI,V2SI,V4SI,V2DI,V2SF,V4SF,V2DF,DI,DF,SI,HI,QI" -+ (const_string "unknown")) -+ -+ -+; Classification of AdvSIMD instructions for scheduling purposes. -+; Do not set this attribute and the "v8type" attribute together in -+; any instruction pattern. -+ -+; simd_abd integer absolute difference and accumulate. -+; simd_abdl integer absolute difference and accumulate (long). -+; simd_adal integer add and accumulate (long). -+; simd_add integer addition/subtraction. -+; simd_addl integer addition/subtraction (long). -+; simd_addlv across lanes integer sum (long). -+; simd_addn integer addition/subtraction (narrow). -+; simd_addn2 integer addition/subtraction (narrow, high). -+; simd_addv across lanes integer sum. -+; simd_cls count leading sign/zero bits. -+; simd_cmp compare / create mask. -+; simd_cnt population count. -+; simd_dup duplicate element. -+; simd_dupgp duplicate general purpose register. -+; simd_ext bitwise extract from pair. -+; simd_fadd floating point add/sub. -+; simd_fcmp floating point compare. -+; simd_fcvti floating point convert to integer. -+; simd_fcvtl floating-point convert upsize. -+; simd_fcvtn floating-point convert downsize (narrow). -+; simd_fcvtn2 floating-point convert downsize (narrow, high). -+; simd_fdiv floating point division. -+; simd_fminmax floating point min/max. -+; simd_fminmaxv across lanes floating point min/max. -+; simd_fmla floating point multiply-add. -+; simd_fmla_elt floating point multiply-add (by element). -+; simd_fmul floating point multiply. -+; simd_fmul_elt floating point multiply (by element). -+; simd_fnegabs floating point neg/abs. -+; simd_frcpe floating point reciprocal estimate. -+; simd_frcps floating point reciprocal step. -+; simd_frecx floating point reciprocal exponent. -+; simd_frint floating point round to integer. -+; simd_fsqrt floating point square root. -+; simd_icvtf integer convert to floating point. -+; simd_ins insert element. -+; simd_insgp insert general purpose register. -+; simd_load1 load multiple structures to one register (LD1). -+; simd_load1r load single structure to all lanes of one register (LD1R). -+; simd_load1s load single structure to one lane of one register (LD1 [index]). -+; simd_load2 load multiple structures to two registers (LD1, LD2). -+; simd_load2r load single structure to all lanes of two registers (LD1R, LD2R). -+; simd_load2s load single structure to one lane of two registers (LD2 [index]). -+; simd_load3 load multiple structures to three registers (LD1, LD3). -+; simd_load3r load single structure to all lanes of three registers (LD3R). -+; simd_load3s load single structure to one lane of three registers (LD3 [index]). -+; simd_load4 load multiple structures to four registers (LD1, LD2, LD4). -+; simd_load4r load single structure to all lanes of four registers (LD4R). -+; simd_load4s load single structure to one lane of four registers (LD4 [index]). -+; simd_logic logical operation. -+; simd_logic_imm logcial operation (immediate). -+; simd_minmax integer min/max. -+; simd_minmaxv across lanes integer min/max, -+; simd_mla integer multiply-accumulate. -+; simd_mla_elt integer multiply-accumulate (by element). -+; simd_mlal integer multiply-accumulate (long). -+; simd_mlal_elt integer multiply-accumulate (by element, long). -+; simd_move move register. -+; simd_move_imm move immediate. -+; simd_movgp move element to general purpose register. -+; simd_mul integer multiply. -+; simd_mul_elt integer multiply (by element). -+; simd_mull integer multiply (long). -+; simd_mull_elt integer multiply (by element, long). -+; simd_negabs integer negate/absolute. -+; simd_rbit bitwise reverse. -+; simd_rcpe integer reciprocal estimate. -+; simd_rcps integer reciprocal square root. -+; simd_rev element reverse. -+; simd_sat_add integer saturating addition/subtraction. -+; simd_sat_mlal integer saturating multiply-accumulate (long). -+; simd_sat_mlal_elt integer saturating multiply-accumulate (by element, long). -+; simd_sat_mul integer saturating multiply. -+; simd_sat_mul_elt integer saturating multiply (by element). -+; simd_sat_mull integer saturating multiply (long). -+; simd_sat_mull_elt integer saturating multiply (by element, long). -+; simd_sat_negabs integer saturating negate/absolute. -+; simd_sat_shift integer saturating shift. -+; simd_sat_shift_imm integer saturating shift (immediate). -+; simd_sat_shiftn_imm integer saturating shift (narrow, immediate). -+; simd_sat_shiftn2_imm integer saturating shift (narrow, high, immediate). -+; simd_shift shift register/vector. -+; simd_shift_acc shift accumulate. -+; simd_shift_imm shift immediate. -+; simd_shift_imm_acc shift immediate and accumualte. -+; simd_shiftl shift register/vector (long). -+; simd_shiftl_imm shift register/vector (long, immediate). -+; simd_shiftn_imm shift register/vector (narrow, immediate). -+; simd_shiftn2_imm shift register/vector (narrow, high, immediate). -+; simd_store1 store multiple structures from one register (ST1). -+; simd_store1s store single structure from one lane of one register (ST1 [index]). -+; simd_store2 store multiple structures from two registers (ST1, ST2). -+; simd_store2s store single structure from one lane of two registers (ST2 [index]). -+; simd_store3 store multiple structures from three registers (ST1, ST3). -+; simd_store3s store single structure from one lane of three register (ST3 [index]). -+; simd_store4 store multiple structures from four registers (ST1, ST2, ST4). -+; simd_store4s store single structure from one lane for four registers (ST4 [index]). -+; simd_tbl table lookup. -+; simd_trn transpose. -+; simd_zip zip/unzip. -+ -+(define_attr "simd_type" -+ "simd_abd,\ -+ simd_abdl,\ -+ simd_adal,\ -+ simd_add,\ -+ simd_addl,\ -+ simd_addlv,\ -+ simd_addn,\ -+ simd_addn2,\ -+ simd_addv,\ -+ simd_cls,\ -+ simd_cmp,\ -+ simd_cnt,\ -+ simd_dup,\ -+ simd_dupgp,\ -+ simd_ext,\ -+ simd_fadd,\ -+ simd_fcmp,\ -+ simd_fcvti,\ -+ simd_fcvtl,\ -+ simd_fcvtn,\ -+ simd_fcvtn2,\ -+ simd_fdiv,\ -+ simd_fminmax,\ -+ simd_fminmaxv,\ -+ simd_fmla,\ -+ simd_fmla_elt,\ -+ simd_fmul,\ -+ simd_fmul_elt,\ -+ simd_fnegabs,\ -+ simd_frcpe,\ -+ simd_frcps,\ -+ simd_frecx,\ -+ simd_frint,\ -+ simd_fsqrt,\ -+ simd_icvtf,\ -+ simd_ins,\ -+ simd_insgp,\ -+ simd_load1,\ -+ simd_load1r,\ -+ simd_load1s,\ -+ simd_load2,\ -+ simd_load2r,\ -+ simd_load2s,\ -+ simd_load3,\ -+ simd_load3r,\ -+ simd_load3s,\ -+ simd_load4,\ -+ simd_load4r,\ -+ simd_load4s,\ -+ simd_logic,\ -+ simd_logic_imm,\ -+ simd_minmax,\ -+ simd_minmaxv,\ -+ simd_mla,\ -+ simd_mla_elt,\ -+ simd_mlal,\ -+ simd_mlal_elt,\ -+ simd_movgp,\ -+ simd_move,\ -+ simd_move_imm,\ -+ simd_mul,\ -+ simd_mul_elt,\ -+ simd_mull,\ -+ simd_mull_elt,\ -+ simd_negabs,\ -+ simd_rbit,\ -+ simd_rcpe,\ -+ simd_rcps,\ -+ simd_rev,\ -+ simd_sat_add,\ -+ simd_sat_mlal,\ -+ simd_sat_mlal_elt,\ -+ simd_sat_mul,\ -+ simd_sat_mul_elt,\ -+ simd_sat_mull,\ -+ simd_sat_mull_elt,\ -+ simd_sat_negabs,\ -+ simd_sat_shift,\ -+ simd_sat_shift_imm,\ -+ simd_sat_shiftn_imm,\ -+ simd_sat_shiftn2_imm,\ -+ simd_shift,\ -+ simd_shift_acc,\ -+ simd_shift_imm,\ -+ simd_shift_imm_acc,\ -+ simd_shiftl,\ -+ simd_shiftl_imm,\ -+ simd_shiftn_imm,\ -+ simd_shiftn2_imm,\ -+ simd_store1,\ -+ simd_store1s,\ -+ simd_store2,\ -+ simd_store2s,\ -+ simd_store3,\ -+ simd_store3s,\ -+ simd_store4,\ -+ simd_store4s,\ -+ simd_tbl,\ -+ simd_trn,\ -+ simd_zip,\ -+ none" -+ (const_string "none")) -+ -+ -+; The "neon_type" attribute is used by the AArch32 backend. Below is a mapping -+; from "simd_type" to "neon_type". -+ -+(define_attr "neon_type" -+ "neon_int_1,neon_int_2,neon_int_3,neon_int_4,neon_int_5,neon_vqneg_vqabs, -+ neon_vmov,neon_vaba,neon_vsma,neon_vaba_qqq, -+ neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,neon_mul_qqq_8_16_32_ddd_32, -+ neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar, -+ neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,neon_mla_qqq_8_16, -+ neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long, -+ neon_mla_qqq_32_qqd_32_scalar,neon_mul_ddd_16_scalar_32_16_long_scalar, -+ neon_mul_qqd_32_scalar,neon_mla_ddd_16_scalar_qdd_32_16_long_scalar, -+ neon_shift_1,neon_shift_2,neon_shift_3,neon_vshl_ddd, -+ neon_vqshl_vrshl_vqrshl_qqq,neon_vsra_vrsra,neon_fp_vadd_ddd_vabs_dd, -+ neon_fp_vadd_qqq_vabs_qq,neon_fp_vsum,neon_fp_vmul_ddd,neon_fp_vmul_qqd, -+ neon_fp_vmla_ddd,neon_fp_vmla_qqq,neon_fp_vmla_ddd_scalar, -+ neon_fp_vmla_qqq_scalar,neon_fp_vrecps_vrsqrts_ddd, -+ neon_fp_vrecps_vrsqrts_qqq,neon_bp_simple,neon_bp_2cycle,neon_bp_3cycle, -+ neon_ldr,neon_str,neon_vld1_1_2_regs,neon_vld1_3_4_regs, -+ neon_vld2_2_regs_vld1_vld2_all_lanes,neon_vld2_4_regs,neon_vld3_vld4, -+ neon_vst1_1_2_regs_vst2_2_regs,neon_vst1_3_4_regs, -+ neon_vst2_4_regs_vst3_vst4,neon_vst3_vst4,neon_vld1_vld2_lane, -+ neon_vld3_vld4_lane,neon_vst1_vst2_lane,neon_vst3_vst4_lane, -+ neon_vld3_vld4_all_lanes,neon_mcr,neon_mcr_2_mcrr,neon_mrc,neon_mrrc, -+ neon_ldm_2,neon_stm_2,none,unknown" -+ (cond [ -+ (eq_attr "simd_type" "simd_dup") (const_string "neon_bp_simple") -+ (eq_attr "simd_type" "simd_movgp") (const_string "neon_bp_simple") -+ (eq_attr "simd_type" "simd_add,simd_logic,simd_logic_imm") (const_string "neon_int_1") -+ (eq_attr "simd_type" "simd_negabs,simd_addlv") (const_string "neon_int_3") -+ (eq_attr "simd_type" "simd_addn,simd_addn2,simd_addl,simd_sat_add,simd_sat_negabs") (const_string "neon_int_4") -+ (eq_attr "simd_type" "simd_move") (const_string "neon_vmov") -+ (eq_attr "simd_type" "simd_ins") (const_string "neon_mcr") -+ (and (eq_attr "simd_type" "simd_mul,simd_sat_mul") (eq_attr "simd_mode" "V8QI,V4HI")) (const_string "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long") -+ (and (eq_attr "simd_type" "simd_mul,simd_sat_mul") (eq_attr "simd_mode" "V2SI,V8QI,V16QI,V2SI")) (const_string "neon_mul_qqq_8_16_32_ddd_32") -+ (and (eq_attr "simd_type" "simd_mull,simd_sat_mull") (eq_attr "simd_mode" "V8QI,V16QI,V4HI,V8HI")) (const_string "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long") -+ (and (eq_attr "simd_type" "simd_mull,simd_sat_mull") (eq_attr "simd_mode" "V2SI,V4SI,V2DI")) (const_string "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar") -+ (and (eq_attr "simd_type" "simd_mla,simd_sat_mlal") (eq_attr "simd_mode" "V8QI,V4HI")) (const_string "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long") -+ (and (eq_attr "simd_type" "simd_mla,simd_sat_mlal") (eq_attr "simd_mode" "V2SI")) (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long") -+ (and (eq_attr "simd_type" "simd_mla,simd_sat_mlal") (eq_attr "simd_mode" "V16QI,V8HI")) (const_string "neon_mla_qqq_8_16") -+ (and (eq_attr "simd_type" "simd_mla,simd_sat_mlal") (eq_attr "simd_mode" "V4SI")) (const_string "neon_mla_qqq_32_qqd_32_scalar") -+ (and (eq_attr "simd_type" "simd_mlal") (eq_attr "simd_mode" "V8QI,V16QI,V4HI,V8HI")) (const_string "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long") -+ (and (eq_attr "simd_type" "simd_mlal") (eq_attr "simd_mode" "V2SI,V4SI,V2DI")) (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long") -+ (and (eq_attr "simd_type" "simd_fmla") (eq_attr "simd_mode" "V2SF")) (const_string "neon_fp_vmla_ddd") -+ (and (eq_attr "simd_type" "simd_fmla") (eq_attr "simd_mode" "V4SF,V2DF")) (const_string "neon_fp_vmla_qqq") -+ (and (eq_attr "simd_type" "simd_fmla_elt") (eq_attr "simd_mode" "V2SF")) (const_string "neon_fp_vmla_ddd_scalar") -+ (and (eq_attr "simd_type" "simd_fmla_elt") (eq_attr "simd_mode" "V4SF,V2DF")) (const_string "neon_fp_vmla_qqq_scalar") -+ (and (eq_attr "simd_type" "simd_fmul,simd_fmul_elt,simd_fdiv,simd_fsqrt") (eq_attr "simd_mode" "V2SF")) (const_string "neon_fp_vmul_ddd") -+ (and (eq_attr "simd_type" "simd_fmul,simd_fmul_elt,simd_fdiv,simd_fsqrt") (eq_attr "simd_mode" "V4SF,V2DF")) (const_string "neon_fp_vmul_qqd") -+ (and (eq_attr "simd_type" "simd_fadd") (eq_attr "simd_mode" "V2SF")) (const_string "neon_fp_vadd_ddd_vabs_dd") -+ (and (eq_attr "simd_type" "simd_fadd") (eq_attr "simd_mode" "V4SF,V2DF")) (const_string "neon_fp_vadd_qqq_vabs_qq") -+ (and (eq_attr "simd_type" "simd_fnegabs,simd_fminmax,simd_fminmaxv") (eq_attr "simd_mode" "V2SF")) (const_string "neon_fp_vadd_ddd_vabs_dd") -+ (and (eq_attr "simd_type" "simd_fnegabs,simd_fminmax,simd_fminmaxv") (eq_attr "simd_mode" "V4SF,V2DF")) (const_string "neon_fp_vadd_qqq_vabs_qq") -+ (and (eq_attr "simd_type" "simd_shift,simd_shift_acc") (eq_attr "simd_mode" "V8QI,V4HI,V2SI")) (const_string "neon_vshl_ddd") -+ (and (eq_attr "simd_type" "simd_shift,simd_shift_acc") (eq_attr "simd_mode" "V16QI,V8HI,V4SI,V2DI")) (const_string "neon_shift_3") -+ (eq_attr "simd_type" "simd_minmax,simd_minmaxv") (const_string "neon_int_5") -+ (eq_attr "simd_type" "simd_shiftn_imm,simd_shiftn2_imm,simd_shiftl_imm,") (const_string "neon_shift_1") -+ (eq_attr "simd_type" "simd_load1,simd_load2") (const_string "neon_vld1_1_2_regs") -+ (eq_attr "simd_type" "simd_load3,simd_load3") (const_string "neon_vld1_3_4_regs") -+ (eq_attr "simd_type" "simd_load1r,simd_load2r,simd_load3r,simd_load4r") (const_string "neon_vld2_2_regs_vld1_vld2_all_lanes") -+ (eq_attr "simd_type" "simd_load1s,simd_load2s") (const_string "neon_vld1_vld2_lane") -+ (eq_attr "simd_type" "simd_load3s,simd_load4s") (const_string "neon_vld3_vld4_lane") -+ (eq_attr "simd_type" "simd_store1,simd_store2") (const_string "neon_vst1_1_2_regs_vst2_2_regs") -+ (eq_attr "simd_type" "simd_store3,simd_store4") (const_string "neon_vst1_3_4_regs") -+ (eq_attr "simd_type" "simd_store1s,simd_store2s") (const_string "neon_vst1_vst2_lane") -+ (eq_attr "simd_type" "simd_store3s,simd_store4s") (const_string "neon_vst3_vst4_lane") -+ (and (eq_attr "simd_type" "simd_frcpe,simd_frcps") (eq_attr "simd_mode" "V2SF")) (const_string "neon_fp_vrecps_vrsqrts_ddd") -+ (and (eq_attr "simd_type" "simd_frcpe,simd_frcps") (eq_attr "simd_mode" "V4SF,V2DF")) (const_string "neon_fp_vrecps_vrsqrts_qqq") -+ (eq_attr "simd_type" "none") (const_string "none") -+ ] -+ (const_string "unknown"))) -+ -+ -+(define_expand "mov" -+ [(set (match_operand:VALL 0 "nonimmediate_operand" "") -+ (match_operand:VALL 1 "general_operand" ""))] -+ "TARGET_SIMD" -+ " -+ if (GET_CODE (operands[0]) == MEM) -+ operands[1] = force_reg (mode, operands[1]); -+ " -+) -+ -+(define_expand "movmisalign" -+ [(set (match_operand:VALL 0 "nonimmediate_operand" "") -+ (match_operand:VALL 1 "general_operand" ""))] -+ "TARGET_SIMD" -+{ -+ /* This pattern is not permitted to fail during expansion: if both arguments -+ are non-registers (e.g. memory := constant, which can be created by the -+ auto-vectorizer), force operand 1 into a register. */ -+ if (!register_operand (operands[0], mode) -+ && !register_operand (operands[1], mode)) -+ operands[1] = force_reg (mode, operands[1]); -+}) -+ -+(define_insn "aarch64_simd_dup" -+ [(set (match_operand:VDQ 0 "register_operand" "=w") -+ (vec_duplicate:VDQ (match_operand: 1 "register_operand" "r")))] -+ "TARGET_SIMD" -+ "dup\\t%0., %1" -+ [(set_attr "simd_type" "simd_dupgp") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "aarch64_dup_lane" -+ [(set (match_operand:VDQ_I 0 "register_operand" "=w") -+ (vec_duplicate:VDQ_I -+ (vec_select: -+ (match_operand: 1 "register_operand" "w") -+ (parallel [(match_operand:SI 2 "immediate_operand" "i")]) -+ )))] -+ "TARGET_SIMD" -+ "dup\\t%0, %1.[%2]" -+ [(set_attr "simd_type" "simd_dup") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "aarch64_dup_lane" -+ [(set (match_operand:SDQ_I 0 "register_operand" "=w") -+ (vec_select: -+ (match_operand: 1 "register_operand" "w") -+ (parallel [(match_operand:SI 2 "immediate_operand" "i")]) -+ ))] -+ "TARGET_SIMD" -+ "dup\\t%0, %1.[%2]" -+ [(set_attr "simd_type" "simd_dup") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "aarch64_simd_dup" -+ [(set (match_operand:VDQF 0 "register_operand" "=w") -+ (vec_duplicate:VDQF (match_operand: 1 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "dup\\t%0., %1.[0]" -+ [(set_attr "simd_type" "simd_dup") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "*aarch64_simd_mov" -+ [(set (match_operand:VD 0 "nonimmediate_operand" -+ "=w, m, w, ?r, ?w, ?r, w") -+ (match_operand:VD 1 "general_operand" -+ "m, w, w, w, r, r, Dn"))] -+ "TARGET_SIMD -+ && (register_operand (operands[0], mode) -+ || register_operand (operands[1], mode))" -+{ -+ switch (which_alternative) -+ { -+ case 0: return "ld1\t{%0.}, %1"; -+ case 1: return "st1\t{%1.}, %0"; -+ case 2: return "orr\t%0., %1., %1."; -+ case 3: return "umov\t%0, %1.d[0]"; -+ case 4: return "ins\t%0.d[0], %1"; -+ case 5: return "mov\t%0, %1"; -+ case 6: -+ { -+ int is_valid; -+ unsigned char widthc; -+ int width; -+ static char templ[40]; -+ int shift = 0, mvn = 0; -+ const char *mnemonic; -+ int length = 0; -+ -+ is_valid = -+ aarch64_simd_immediate_valid_for_move (operands[1], mode, -+ &operands[1], &width, &widthc, -+ &mvn, &shift); -+ gcc_assert (is_valid != 0); -+ -+ mnemonic = mvn ? "mvni" : "movi"; -+ if (widthc != 'd') -+ length += snprintf (templ, sizeof (templ), -+ "%s\t%%0.%d%c, %%1", -+ mnemonic, 64 / width, widthc); -+ else -+ length += snprintf (templ, sizeof (templ), "%s\t%%d0, %%1", mnemonic); -+ -+ if (shift != 0) -+ length += snprintf (templ + length, sizeof (templ) - length, -+ ", lsl %d", shift); -+ return templ; -+ } -+ default: gcc_unreachable (); -+ } -+} -+ [(set_attr "simd_type" "simd_load1,simd_store1,simd_move,simd_movgp,simd_insgp,simd_move,simd_move_imm") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "*aarch64_simd_mov" -+ [(set (match_operand:VQ 0 "nonimmediate_operand" -+ "=w, m, w, ?r, ?w, ?r, w") -+ (match_operand:VQ 1 "general_operand" -+ "m, w, w, w, r, r, Dn"))] -+ "TARGET_SIMD -+ && (register_operand (operands[0], mode) -+ || register_operand (operands[1], mode))" -+{ -+ switch (which_alternative) -+ { -+ case 0: return "ld1\t{%0.}, %1"; -+ case 1: return "st1\t{%1.}, %0"; -+ case 2: return "orr\t%0., %1., %1."; -+ case 3: return "umov\t%0, %1.d[0]\;umov\t%H0, %1.d[1]"; -+ case 4: return "ins\t%0.d[0], %1\;ins\t%0.d[1], %H1"; -+ case 5: return "mov\t%0, %1;mov\t%H0, %H1"; -+ case 6: -+ { -+ int is_valid; -+ unsigned char widthc; -+ int width; -+ static char templ[40]; -+ int shift = 0, mvn = 0; -+ -+ is_valid = -+ aarch64_simd_immediate_valid_for_move (operands[1], mode, -+ &operands[1], &width, &widthc, -+ &mvn, &shift); -+ gcc_assert (is_valid != 0); -+ if (shift) -+ snprintf (templ, sizeof (templ), "%s\t%%0.%d%c, %%1, lsl %d", -+ mvn ? "mvni" : "movi", -+ 128 / width, widthc, shift); -+ else -+ snprintf (templ, sizeof (templ), "%s\t%%0.%d%c, %%1", -+ mvn ? "mvni" : "movi", -+ 128 / width, widthc); -+ return templ; -+ } -+ default: gcc_unreachable (); -+ } -+} -+ [(set_attr "simd_type" "simd_load1,simd_store1,simd_move,simd_movgp,simd_insgp,simd_move,simd_move_imm") -+ (set_attr "simd_mode" "") -+ (set_attr "length" "4,4,4,8,8,8,4")] -+) -+ -+(define_insn "orn3" -+ [(set (match_operand:VDQ 0 "register_operand" "=w") -+ (ior:VDQ (not:VDQ (match_operand:VDQ 1 "register_operand" "w")) -+ (match_operand:VDQ 2 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "orn\t%0., %2., %1." -+ [(set_attr "simd_type" "simd_logic") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "bic3" -+ [(set (match_operand:VDQ 0 "register_operand" "=w") -+ (and:VDQ (not:VDQ (match_operand:VDQ 1 "register_operand" "w")) -+ (match_operand:VDQ 2 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "bic\t%0., %2., %1." -+ [(set_attr "simd_type" "simd_logic") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "add3" -+ [(set (match_operand:VDQ 0 "register_operand" "=w") -+ (plus:VDQ (match_operand:VDQ 1 "register_operand" "w") -+ (match_operand:VDQ 2 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "add\t%0., %1., %2." -+ [(set_attr "simd_type" "simd_add") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "sub3" -+ [(set (match_operand:VDQ 0 "register_operand" "=w") -+ (minus:VDQ (match_operand:VDQ 1 "register_operand" "w") -+ (match_operand:VDQ 2 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "sub\t%0., %1., %2." -+ [(set_attr "simd_type" "simd_add") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "mul3" -+ [(set (match_operand:VDQM 0 "register_operand" "=w") -+ (mult:VDQM (match_operand:VDQM 1 "register_operand" "w") -+ (match_operand:VDQM 2 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "mul\t%0., %1., %2." -+ [(set_attr "simd_type" "simd_mul") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "neg2" -+ [(set (match_operand:VDQM 0 "register_operand" "=w") -+ (neg:VDQM (match_operand:VDQM 1 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "neg\t%0., %1." -+ [(set_attr "simd_type" "simd_negabs") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "abs2" -+ [(set (match_operand:VDQ 0 "register_operand" "=w") -+ (abs:VDQ (match_operand:VDQ 1 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "abs\t%0., %1." -+ [(set_attr "simd_type" "simd_negabs") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "and3" -+ [(set (match_operand:VDQ 0 "register_operand" "=w") -+ (and:VDQ (match_operand:VDQ 1 "register_operand" "w") -+ (match_operand:VDQ 2 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "and\t%0., %1., %2." -+ [(set_attr "simd_type" "simd_logic") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "ior3" -+ [(set (match_operand:VDQ 0 "register_operand" "=w") -+ (ior:VDQ (match_operand:VDQ 1 "register_operand" "w") -+ (match_operand:VDQ 2 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "orr\t%0., %1., %2." -+ [(set_attr "simd_type" "simd_logic") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "xor3" -+ [(set (match_operand:VDQ 0 "register_operand" "=w") -+ (xor:VDQ (match_operand:VDQ 1 "register_operand" "w") -+ (match_operand:VDQ 2 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "eor\t%0., %1., %2." -+ [(set_attr "simd_type" "simd_logic") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "one_cmpl2" -+ [(set (match_operand:VDQ 0 "register_operand" "=w") -+ (not:VDQ (match_operand:VDQ 1 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "not\t%0., %1." -+ [(set_attr "simd_type" "simd_logic") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "aarch64_simd_vec_set" -+ [(set (match_operand:VQ_S 0 "register_operand" "=w") -+ (vec_merge:VQ_S -+ (vec_duplicate:VQ_S -+ (match_operand: 1 "register_operand" "r")) -+ (match_operand:VQ_S 3 "register_operand" "0") -+ (match_operand:SI 2 "immediate_operand" "i")))] -+ "TARGET_SIMD" -+ "ins\t%0.[%p2], %w1"; -+ [(set_attr "simd_type" "simd_insgp") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "aarch64_simd_lshr" -+ [(set (match_operand:VDQ 0 "register_operand" "=w") -+ (lshiftrt:VDQ (match_operand:VDQ 1 "register_operand" "w") -+ (match_operand:VDQ 2 "aarch64_simd_rshift_imm" "Dr")))] -+ "TARGET_SIMD" -+ "ushr\t%0., %1., %2" -+ [(set_attr "simd_type" "simd_shift_imm") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "aarch64_simd_ashr" -+ [(set (match_operand:VDQ 0 "register_operand" "=w") -+ (ashiftrt:VDQ (match_operand:VDQ 1 "register_operand" "w") -+ (match_operand:VDQ 2 "aarch64_simd_rshift_imm" "Dr")))] -+ "TARGET_SIMD" -+ "sshr\t%0., %1., %2" -+ [(set_attr "simd_type" "simd_shift_imm") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "aarch64_simd_imm_shl" -+ [(set (match_operand:VDQ 0 "register_operand" "=w") -+ (ashift:VDQ (match_operand:VDQ 1 "register_operand" "w") -+ (match_operand:VDQ 2 "aarch64_simd_lshift_imm" "Dl")))] -+ "TARGET_SIMD" -+ "shl\t%0., %1., %2" -+ [(set_attr "simd_type" "simd_shift_imm") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "aarch64_simd_reg_sshl" -+ [(set (match_operand:VDQ 0 "register_operand" "=w") -+ (ashift:VDQ (match_operand:VDQ 1 "register_operand" "w") -+ (match_operand:VDQ 2 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "sshl\t%0., %1., %2." -+ [(set_attr "simd_type" "simd_shift") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "aarch64_simd_reg_shl_unsigned" -+ [(set (match_operand:VDQ 0 "register_operand" "=w") -+ (unspec:VDQ [(match_operand:VDQ 1 "register_operand" "w") -+ (match_operand:VDQ 2 "register_operand" "w")] -+ UNSPEC_ASHIFT_UNSIGNED))] -+ "TARGET_SIMD" -+ "ushl\t%0., %1., %2." -+ [(set_attr "simd_type" "simd_shift") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "aarch64_simd_reg_shl_signed" -+ [(set (match_operand:VDQ 0 "register_operand" "=w") -+ (unspec:VDQ [(match_operand:VDQ 1 "register_operand" "w") -+ (match_operand:VDQ 2 "register_operand" "w")] -+ UNSPEC_ASHIFT_SIGNED))] -+ "TARGET_SIMD" -+ "sshl\t%0., %1., %2." -+ [(set_attr "simd_type" "simd_shift") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_expand "ashl3" -+ [(match_operand:VDQ 0 "register_operand" "") -+ (match_operand:VDQ 1 "register_operand" "") -+ (match_operand:SI 2 "general_operand" "")] -+ "TARGET_SIMD" -+{ -+ int bit_width = GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT; -+ int shift_amount; -+ -+ if (CONST_INT_P (operands[2])) -+ { -+ shift_amount = INTVAL (operands[2]); -+ if (shift_amount >= 0 && shift_amount < bit_width) -+ { -+ rtx tmp = aarch64_simd_gen_const_vector_dup (mode, -+ shift_amount); -+ emit_insn (gen_aarch64_simd_imm_shl (operands[0], -+ operands[1], -+ tmp)); -+ DONE; -+ } -+ else -+ { -+ operands[2] = force_reg (SImode, operands[2]); -+ } -+ } -+ else if (MEM_P (operands[2])) -+ { -+ operands[2] = force_reg (SImode, operands[2]); -+ } -+ -+ if (REG_P (operands[2])) -+ { -+ rtx tmp = gen_reg_rtx (mode); -+ emit_insn (gen_aarch64_simd_dup (tmp, -+ convert_to_mode (mode, -+ operands[2], -+ 0))); -+ emit_insn (gen_aarch64_simd_reg_sshl (operands[0], operands[1], -+ tmp)); -+ DONE; -+ } -+ else -+ FAIL; -+} -+) -+ -+(define_expand "lshr3" -+ [(match_operand:VDQ 0 "register_operand" "") -+ (match_operand:VDQ 1 "register_operand" "") -+ (match_operand:SI 2 "general_operand" "")] -+ "TARGET_SIMD" -+{ -+ int bit_width = GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT; -+ int shift_amount; -+ -+ if (CONST_INT_P (operands[2])) -+ { -+ shift_amount = INTVAL (operands[2]); -+ if (shift_amount > 0 && shift_amount <= bit_width) -+ { -+ rtx tmp = aarch64_simd_gen_const_vector_dup (mode, -+ shift_amount); -+ emit_insn (gen_aarch64_simd_lshr (operands[0], -+ operands[1], -+ tmp)); -+ DONE; -+ } -+ else -+ operands[2] = force_reg (SImode, operands[2]); -+ } -+ else if (MEM_P (operands[2])) -+ { -+ operands[2] = force_reg (SImode, operands[2]); -+ } -+ -+ if (REG_P (operands[2])) -+ { -+ rtx tmp = gen_reg_rtx (SImode); -+ rtx tmp1 = gen_reg_rtx (mode); -+ emit_insn (gen_negsi2 (tmp, operands[2])); -+ emit_insn (gen_aarch64_simd_dup (tmp1, -+ convert_to_mode (mode, -+ tmp, 0))); -+ emit_insn (gen_aarch64_simd_reg_shl_unsigned (operands[0], -+ operands[1], -+ tmp1)); -+ DONE; -+ } -+ else -+ FAIL; -+} -+) -+ -+(define_expand "ashr3" -+ [(match_operand:VDQ 0 "register_operand" "") -+ (match_operand:VDQ 1 "register_operand" "") -+ (match_operand:SI 2 "general_operand" "")] -+ "TARGET_SIMD" -+{ -+ int bit_width = GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT; -+ int shift_amount; -+ -+ if (CONST_INT_P (operands[2])) -+ { -+ shift_amount = INTVAL (operands[2]); -+ if (shift_amount > 0 && shift_amount <= bit_width) -+ { -+ rtx tmp = aarch64_simd_gen_const_vector_dup (mode, -+ shift_amount); -+ emit_insn (gen_aarch64_simd_ashr (operands[0], -+ operands[1], -+ tmp)); -+ DONE; -+ } -+ else -+ operands[2] = force_reg (SImode, operands[2]); -+ } -+ else if (MEM_P (operands[2])) -+ { -+ operands[2] = force_reg (SImode, operands[2]); -+ } -+ -+ if (REG_P (operands[2])) -+ { -+ rtx tmp = gen_reg_rtx (SImode); -+ rtx tmp1 = gen_reg_rtx (mode); -+ emit_insn (gen_negsi2 (tmp, operands[2])); -+ emit_insn (gen_aarch64_simd_dup (tmp1, -+ convert_to_mode (mode, -+ tmp, 0))); -+ emit_insn (gen_aarch64_simd_reg_shl_signed (operands[0], -+ operands[1], -+ tmp1)); -+ DONE; -+ } -+ else -+ FAIL; -+} -+) -+ -+(define_expand "vashl3" -+ [(match_operand:VDQ 0 "register_operand" "") -+ (match_operand:VDQ 1 "register_operand" "") -+ (match_operand:VDQ 2 "register_operand" "")] -+ "TARGET_SIMD" -+{ -+ emit_insn (gen_aarch64_simd_reg_sshl (operands[0], operands[1], -+ operands[2])); -+ DONE; -+}) -+ -+;; Using mode VQ_S as there is no V2DImode neg! -+;; Negating individual lanes most certainly offsets the -+;; gain from vectorization. -+(define_expand "vashr3" -+ [(match_operand:VQ_S 0 "register_operand" "") -+ (match_operand:VQ_S 1 "register_operand" "") -+ (match_operand:VQ_S 2 "register_operand" "")] -+ "TARGET_SIMD" -+{ -+ rtx neg = gen_reg_rtx (mode); -+ emit (gen_neg2 (neg, operands[2])); -+ emit_insn (gen_aarch64_simd_reg_shl_signed (operands[0], operands[1], -+ neg)); -+ DONE; -+}) -+ -+(define_expand "vlshr3" -+ [(match_operand:VQ_S 0 "register_operand" "") -+ (match_operand:VQ_S 1 "register_operand" "") -+ (match_operand:VQ_S 2 "register_operand" "")] -+ "TARGET_SIMD" -+{ -+ rtx neg = gen_reg_rtx (mode); -+ emit (gen_neg2 (neg, operands[2])); -+ emit_insn (gen_aarch64_simd_reg_shl_unsigned (operands[0], operands[1], -+ neg)); -+ DONE; -+}) -+ -+(define_expand "vec_set" -+ [(match_operand:VQ_S 0 "register_operand" "+w") -+ (match_operand: 1 "register_operand" "r") -+ (match_operand:SI 2 "immediate_operand" "")] -+ "TARGET_SIMD" -+ { -+ HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]); -+ emit_insn (gen_aarch64_simd_vec_set (operands[0], operands[1], -+ GEN_INT (elem), operands[0])); -+ DONE; -+ } -+) -+ -+(define_insn "aarch64_simd_vec_setv2di" -+ [(set (match_operand:V2DI 0 "register_operand" "=w") -+ (vec_merge:V2DI -+ (vec_duplicate:V2DI -+ (match_operand:DI 1 "register_operand" "r")) -+ (match_operand:V2DI 3 "register_operand" "0") -+ (match_operand:SI 2 "immediate_operand" "i")))] -+ "TARGET_SIMD" -+ "ins\t%0.d[%p2], %1"; -+ [(set_attr "simd_type" "simd_insgp") -+ (set_attr "simd_mode" "V2DI")] -+) -+ -+(define_expand "vec_setv2di" -+ [(match_operand:V2DI 0 "register_operand" "+w") -+ (match_operand:DI 1 "register_operand" "r") -+ (match_operand:SI 2 "immediate_operand" "")] -+ "TARGET_SIMD" -+ { -+ HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]); -+ emit_insn (gen_aarch64_simd_vec_setv2di (operands[0], operands[1], -+ GEN_INT (elem), operands[0])); -+ DONE; -+ } -+) -+ -+(define_insn "aarch64_simd_vec_set" -+ [(set (match_operand:VDQF 0 "register_operand" "=w") -+ (vec_merge:VDQF -+ (vec_duplicate:VDQF -+ (match_operand: 1 "register_operand" "w")) -+ (match_operand:VDQF 3 "register_operand" "0") -+ (match_operand:SI 2 "immediate_operand" "i")))] -+ "TARGET_SIMD" -+ "ins\t%0.[%p2], %1.[0]"; -+ [(set_attr "simd_type" "simd_ins") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_expand "vec_set" -+ [(match_operand:VDQF 0 "register_operand" "+w") -+ (match_operand: 1 "register_operand" "w") -+ (match_operand:SI 2 "immediate_operand" "")] -+ "TARGET_SIMD" -+ { -+ HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]); -+ emit_insn (gen_aarch64_simd_vec_set (operands[0], operands[1], -+ GEN_INT (elem), operands[0])); -+ DONE; -+ } -+) -+ -+ -+(define_insn "aarch64_mla" -+ [(set (match_operand:VQ_S 0 "register_operand" "=w") -+ (plus:VQ_S (mult:VQ_S (match_operand:VQ_S 2 "register_operand" "w") -+ (match_operand:VQ_S 3 "register_operand" "w")) -+ (match_operand:VQ_S 1 "register_operand" "0")))] -+ "TARGET_SIMD" -+ "mla\t%0., %2., %3." -+ [(set_attr "simd_type" "simd_mla") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "aarch64_mls" -+ [(set (match_operand:VQ_S 0 "register_operand" "=w") -+ (minus:VQ_S (match_operand:VQ_S 1 "register_operand" "0") -+ (mult:VQ_S (match_operand:VQ_S 2 "register_operand" "w") -+ (match_operand:VQ_S 3 "register_operand" "w"))))] -+ "TARGET_SIMD" -+ "mls\t%0., %2., %3." -+ [(set_attr "simd_type" "simd_mla") -+ (set_attr "simd_mode" "")] -+) -+ -+;; Max/Min operations. -+(define_insn "3" -+ [(set (match_operand:VQ_S 0 "register_operand" "=w") -+ (MAXMIN:VQ_S (match_operand:VQ_S 1 "register_operand" "w") -+ (match_operand:VQ_S 2 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "\t%0., %1., %2." -+ [(set_attr "simd_type" "simd_minmax") -+ (set_attr "simd_mode" "")] -+) -+ -+;; Move into low-half clearing high half to 0. -+ -+(define_insn "move_lo_quad_" -+ [(set (match_operand:VQ 0 "register_operand" "=w") -+ (vec_concat:VQ -+ (match_operand: 1 "register_operand" "w") -+ (vec_duplicate: (const_int 0))))] -+ "TARGET_SIMD" -+ "mov\\t%d0, %d1"; -+ [(set_attr "simd_type" "simd_dup") -+ (set_attr "simd_mode" "")] -+) -+ -+;; Move into high-half. -+ -+(define_insn "aarch64_simd_move_hi_quad_" -+ [(set (match_operand:VQ 0 "register_operand" "+w") -+ (vec_concat:VQ -+ (vec_select: -+ (match_dup 0) -+ (match_operand:VQ 2 "vect_par_cnst_lo_half" "")) -+ (match_operand: 1 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "ins\\t%0.d[1], %1.d[0]"; -+ [(set_attr "simd_type" "simd_ins") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_expand "move_hi_quad_" -+ [(match_operand:VQ 0 "register_operand" "") -+ (match_operand: 1 "register_operand" "")] -+ "TARGET_SIMD" -+{ -+ rtx p = aarch64_simd_vect_par_cnst_half (mode, false); -+ emit_insn (gen_aarch64_simd_move_hi_quad_ (operands[0], -+ operands[1], p)); -+ DONE; -+}) -+ -+;; Narrowing operations. -+ -+;; For doubles. -+(define_insn "aarch64_simd_vec_pack_trunc_" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (truncate: (match_operand:VQN 1 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "xtn\\t%0., %1." -+ [(set_attr "simd_type" "simd_shiftn_imm") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_expand "vec_pack_trunc_" -+ [(match_operand: 0 "register_operand" "") -+ (match_operand:VDN 1 "register_operand" "") -+ (match_operand:VDN 2 "register_operand" "")] -+ "TARGET_SIMD" -+{ -+ rtx tempreg = gen_reg_rtx (mode); -+ -+ emit_insn (gen_move_lo_quad_ (tempreg, operands[1])); -+ emit_insn (gen_move_hi_quad_ (tempreg, operands[2])); -+ emit_insn (gen_aarch64_simd_vec_pack_trunc_ (operands[0], tempreg)); -+ DONE; -+}) -+ -+;; For quads. -+ -+(define_insn "vec_pack_trunc_" -+ [(set (match_operand: 0 "register_operand" "+&w") -+ (vec_concat: -+ (truncate: (match_operand:VQN 1 "register_operand" "w")) -+ (truncate: (match_operand:VQN 2 "register_operand" "w"))))] -+ "TARGET_SIMD" -+ "xtn\\t%0., %1.\;xtn2\\t%0., %2." -+ [(set_attr "simd_type" "simd_shiftn2_imm") -+ (set_attr "simd_mode" "") -+ (set_attr "length" "8")] -+) -+ -+;; Widening operations. -+ -+(define_insn "aarch64_simd_vec_unpack_lo_" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (ANY_EXTEND: (vec_select: -+ (match_operand:VQW 1 "register_operand" "w") -+ (match_operand:VQW 2 "vect_par_cnst_lo_half" "") -+ )))] -+ "TARGET_SIMD" -+ "shll %0., %1., 0" -+ [(set_attr "simd_type" "simd_shiftl_imm") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "aarch64_simd_vec_unpack_hi_" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (ANY_EXTEND: (vec_select: -+ (match_operand:VQW 1 "register_operand" "w") -+ (match_operand:VQW 2 "vect_par_cnst_hi_half" "") -+ )))] -+ "TARGET_SIMD" -+ "shll2 %0., %1., 0" -+ [(set_attr "simd_type" "simd_shiftl_imm") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_expand "vec_unpack_hi_" -+ [(match_operand: 0 "register_operand" "") -+ (ANY_EXTEND: (match_operand:VQW 1 "register_operand"))] -+ "TARGET_SIMD" -+ { -+ rtx p = aarch64_simd_vect_par_cnst_half (mode, true); -+ emit_insn (gen_aarch64_simd_vec_unpack_hi_ (operands[0], -+ operands[1], p)); -+ DONE; -+ } -+) -+ -+(define_expand "vec_unpack_lo_" -+ [(match_operand: 0 "register_operand" "") -+ (ANY_EXTEND: (match_operand:VQW 1 "register_operand" ""))] -+ "TARGET_SIMD" -+ { -+ rtx p = aarch64_simd_vect_par_cnst_half (mode, false); -+ emit_insn (gen_aarch64_simd_vec_unpack_lo_ (operands[0], -+ operands[1], p)); -+ DONE; -+ } -+) -+ -+;; Widening arithmetic. -+ -+(define_insn "aarch64_simd_vec_mult_lo_" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (mult: (ANY_EXTEND: (vec_select: -+ (match_operand:VQW 1 "register_operand" "w") -+ (match_operand:VQW 3 "vect_par_cnst_lo_half" ""))) -+ (ANY_EXTEND: (vec_select: -+ (match_operand:VQW 2 "register_operand" "w") -+ (match_dup 3)))))] -+ "TARGET_SIMD" -+ "mull %0., %1., %2." -+ [(set_attr "simd_type" "simd_mull") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_expand "vec_widen_mult_lo_" -+ [(match_operand: 0 "register_operand" "") -+ (ANY_EXTEND: (match_operand:VQW 1 "register_operand" "")) -+ (ANY_EXTEND: (match_operand:VQW 2 "register_operand" ""))] -+ "TARGET_SIMD" -+ { -+ rtx p = aarch64_simd_vect_par_cnst_half (mode, false); -+ emit_insn (gen_aarch64_simd_vec_mult_lo_ (operands[0], -+ operands[1], -+ operands[2], p)); -+ DONE; -+ } -+) -+ -+(define_insn "aarch64_simd_vec_mult_hi_" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (mult: (ANY_EXTEND: (vec_select: -+ (match_operand:VQW 1 "register_operand" "w") -+ (match_operand:VQW 3 "vect_par_cnst_hi_half" ""))) -+ (ANY_EXTEND: (vec_select: -+ (match_operand:VQW 2 "register_operand" "w") -+ (match_dup 3)))))] -+ "TARGET_SIMD" -+ "mull2 %0., %1., %2." -+ [(set_attr "simd_type" "simd_mull") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_expand "vec_widen_mult_hi_" -+ [(match_operand: 0 "register_operand" "") -+ (ANY_EXTEND: (match_operand:VQW 1 "register_operand" "")) -+ (ANY_EXTEND: (match_operand:VQW 2 "register_operand" ""))] -+ "TARGET_SIMD" -+ { -+ rtx p = aarch64_simd_vect_par_cnst_half (mode, true); -+ emit_insn (gen_aarch64_simd_vec_mult_hi_ (operands[0], -+ operands[1], -+ operands[2], p)); -+ DONE; -+ -+ } -+) -+ -+;; FP vector operations. -+;; AArch64 AdvSIMD supports single-precision (32-bit) and -+;; double-precision (64-bit) floating-point data types and arithmetic as -+;; defined by the IEEE 754-2008 standard. This makes them vectorizable -+;; without the need for -ffast-math or -funsafe-math-optimizations. -+;; -+;; Floating-point operations can raise an exception. Vectorizing such -+;; operations are safe because of reasons explained below. -+;; -+;; ARMv8 permits an extension to enable trapped floating-point -+;; exception handling, however this is an optional feature. In the -+;; event of a floating-point exception being raised by vectorised -+;; code then: -+;; 1. If trapped floating-point exceptions are available, then a trap -+;; will be taken when any lane raises an enabled exception. A trap -+;; handler may determine which lane raised the exception. -+;; 2. Alternatively a sticky exception flag is set in the -+;; floating-point status register (FPSR). Software may explicitly -+;; test the exception flags, in which case the tests will either -+;; prevent vectorisation, allowing precise identification of the -+;; failing operation, or if tested outside of vectorisable regions -+;; then the specific operation and lane are not of interest. -+ -+;; FP arithmetic operations. -+ -+(define_insn "add3" -+ [(set (match_operand:VDQF 0 "register_operand" "=w") -+ (plus:VDQF (match_operand:VDQF 1 "register_operand" "w") -+ (match_operand:VDQF 2 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "fadd\\t%0., %1., %2." -+ [(set_attr "simd_type" "simd_fadd") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "sub3" -+ [(set (match_operand:VDQF 0 "register_operand" "=w") -+ (minus:VDQF (match_operand:VDQF 1 "register_operand" "w") -+ (match_operand:VDQF 2 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "fsub\\t%0., %1., %2." -+ [(set_attr "simd_type" "simd_fadd") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "mul3" -+ [(set (match_operand:VDQF 0 "register_operand" "=w") -+ (mult:VDQF (match_operand:VDQF 1 "register_operand" "w") -+ (match_operand:VDQF 2 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "fmul\\t%0., %1., %2." -+ [(set_attr "simd_type" "simd_fmul") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "div3" -+ [(set (match_operand:VDQF 0 "register_operand" "=w") -+ (div:VDQF (match_operand:VDQF 1 "register_operand" "w") -+ (match_operand:VDQF 2 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "fdiv\\t%0., %1., %2." -+ [(set_attr "simd_type" "simd_fdiv") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "neg2" -+ [(set (match_operand:VDQF 0 "register_operand" "=w") -+ (neg:VDQF (match_operand:VDQF 1 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "fneg\\t%0., %1." -+ [(set_attr "simd_type" "simd_fnegabs") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "abs2" -+ [(set (match_operand:VDQF 0 "register_operand" "=w") -+ (abs:VDQF (match_operand:VDQF 1 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "fabs\\t%0., %1." -+ [(set_attr "simd_type" "simd_fnegabs") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "fma4" -+ [(set (match_operand:VDQF 0 "register_operand" "=w") -+ (fma:VDQF (match_operand:VDQF 1 "register_operand" "w") -+ (match_operand:VDQF 2 "register_operand" "w") -+ (match_operand:VDQF 3 "register_operand" "0")))] -+ "TARGET_SIMD" -+ "fmla\\t%0., %1., %2." -+ [(set_attr "simd_type" "simd_fmla") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "aarch64_vmls" -+ [(set (match_operand:VDQF 0 "register_operand" "=w") -+ (minus:VDQF (match_operand:VDQF 1 "register_operand" "0") -+ (mult:VDQF (match_operand:VDQF 2 "register_operand" "w") -+ (match_operand:VDQF 3 "register_operand" "w"))))] -+ "TARGET_SIMD" -+ "fmls\\t%0., %2., %3." -+ [(set_attr "simd_type" "simd_fmla") -+ (set_attr "simd_mode" "")] -+) -+ -+;; FP Max/Min -+;; Max/Min are introduced by idiom recognition by GCC's mid-end. An -+;; expression like: -+;; a = (b < c) ? b : c; -+;; is idiom-matched as MIN_EXPR only if -ffinite-math-only is enabled -+;; either explicitly or indirectly via -ffast-math. -+;; -+;; MIN_EXPR and MAX_EXPR eventually map to 'smin' and 'smax' in RTL. -+;; The 'smax' and 'smin' RTL standard pattern names do not specify which -+;; operand will be returned when both operands are zero (i.e. they may not -+;; honour signed zeroes), or when either operand is NaN. Therefore GCC -+;; only introduces MIN_EXPR/MAX_EXPR in fast math mode or when not honouring -+;; NaNs. -+ -+(define_insn "smax3" -+ [(set (match_operand:VDQF 0 "register_operand" "=w") -+ (smax:VDQF (match_operand:VDQF 1 "register_operand" "w") -+ (match_operand:VDQF 2 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "fmaxnm\\t%0., %1., %2." -+ [(set_attr "simd_type" "simd_fminmax") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "smin3" -+ [(set (match_operand:VDQF 0 "register_operand" "=w") -+ (smin:VDQF (match_operand:VDQF 1 "register_operand" "w") -+ (match_operand:VDQF 2 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "fminnm\\t%0., %1., %2." -+ [(set_attr "simd_type" "simd_fminmax") -+ (set_attr "simd_mode" "")] -+) -+ -+;; FP 'across lanes' max and min ops. -+ -+(define_insn "reduc_s_v4sf" -+ [(set (match_operand:V4SF 0 "register_operand" "=w") -+ (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "w")] -+ FMAXMINV))] -+ "TARGET_SIMD" -+ "fnmv\\t%s0, %1.4s"; -+ [(set_attr "simd_type" "simd_fminmaxv") -+ (set_attr "simd_mode" "V4SF")] -+) -+ -+(define_insn "reduc_s_" -+ [(set (match_operand:V2F 0 "register_operand" "=w") -+ (unspec:V2F [(match_operand:V2F 1 "register_operand" "w")] -+ FMAXMINV))] -+ "TARGET_SIMD" -+ "fnmp\\t%0., %1., %1."; -+ [(set_attr "simd_type" "simd_fminmax") -+ (set_attr "simd_mode" "")] -+) -+ -+;; FP 'across lanes' add. -+ -+(define_insn "aarch64_addvv4sf" -+ [(set (match_operand:V4SF 0 "register_operand" "=w") -+ (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "w")] -+ UNSPEC_FADDV))] -+ "TARGET_SIMD" -+ "faddp\\t%0.4s, %1.4s, %1.4s" -+ [(set_attr "simd_type" "simd_fadd") -+ (set_attr "simd_mode" "V4SF")] -+) -+ -+(define_expand "reduc_uplus_v4sf" -+ [(set (match_operand:V4SF 0 "register_operand" "=w") -+ (match_operand:V4SF 1 "register_operand" "w"))] -+ "TARGET_SIMD" -+{ -+ rtx tmp = gen_reg_rtx (V4SFmode); -+ emit_insn (gen_aarch64_addvv4sf (tmp, operands[1])); -+ emit_insn (gen_aarch64_addvv4sf (operands[0], tmp)); -+ DONE; -+}) -+ -+(define_expand "reduc_splus_v4sf" -+ [(set (match_operand:V4SF 0 "register_operand" "=w") -+ (match_operand:V4SF 1 "register_operand" "w"))] -+ "TARGET_SIMD" -+{ -+ rtx tmp = gen_reg_rtx (V4SFmode); -+ emit_insn (gen_aarch64_addvv4sf (tmp, operands[1])); -+ emit_insn (gen_aarch64_addvv4sf (operands[0], tmp)); -+ DONE; -+}) -+ -+(define_insn "aarch64_addv" -+ [(set (match_operand:V2F 0 "register_operand" "=w") -+ (unspec:V2F [(match_operand:V2F 1 "register_operand" "w")] -+ UNSPEC_FADDV))] -+ "TARGET_SIMD" -+ "faddp\\t%0, %1." -+ [(set_attr "simd_type" "simd_fadd") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_expand "reduc_uplus_" -+ [(set (match_operand:V2F 0 "register_operand" "=w") -+ (unspec:V2F [(match_operand:V2F 1 "register_operand" "w")] -+ UNSPEC_FADDV))] -+ "TARGET_SIMD" -+ "" -+) -+ -+(define_expand "reduc_splus_" -+ [(set (match_operand:V2F 0 "register_operand" "=w") -+ (unspec:V2F [(match_operand:V2F 1 "register_operand" "w")] -+ UNSPEC_FADDV))] -+ "TARGET_SIMD" -+ "" -+) -+ -+;; Reduction across lanes. -+ -+(define_insn "aarch64_addv" -+ [(set (match_operand:VDQV 0 "register_operand" "=w") -+ (unspec:VDQV [(match_operand:VDQV 1 "register_operand" "w")] -+ UNSPEC_ADDV))] -+ "TARGET_SIMD" -+ "addv\\t%0, %1." -+ [(set_attr "simd_type" "simd_addv") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_expand "reduc_splus_" -+ [(set (match_operand:VDQV 0 "register_operand" "=w") -+ (unspec:VDQV [(match_operand:VDQV 1 "register_operand" "w")] -+ UNSPEC_ADDV))] -+ "TARGET_SIMD" -+ "" -+) -+ -+(define_expand "reduc_uplus_" -+ [(set (match_operand:VDQV 0 "register_operand" "=w") -+ (unspec:VDQV [(match_operand:VDQV 1 "register_operand" "w")] -+ UNSPEC_ADDV))] -+ "TARGET_SIMD" -+ "" -+) -+ -+(define_insn "aarch64_addvv2di" -+ [(set (match_operand:V2DI 0 "register_operand" "=w") -+ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "w")] -+ UNSPEC_ADDV))] -+ "TARGET_SIMD" -+ "addp\\t%d0, %1.2d" -+ [(set_attr "simd_type" "simd_add") -+ (set_attr "simd_mode" "V2DI")] -+) -+ -+(define_expand "reduc_uplus_v2di" -+ [(set (match_operand:V2DI 0 "register_operand" "=w") -+ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "w")] -+ UNSPEC_ADDV))] -+ "TARGET_SIMD" -+ "" -+) -+ -+(define_expand "reduc_splus_v2di" -+ [(set (match_operand:V2DI 0 "register_operand" "=w") -+ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "w")] -+ UNSPEC_ADDV))] -+ "TARGET_SIMD" -+ "" -+) -+ -+(define_insn "aarch64_addvv2si" -+ [(set (match_operand:V2SI 0 "register_operand" "=w") -+ (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "w")] -+ UNSPEC_ADDV))] -+ "TARGET_SIMD" -+ "addp\\t%0.2s, %1.2s, %1.2s" -+ [(set_attr "simd_type" "simd_add") -+ (set_attr "simd_mode" "V2SI")] -+) -+ -+(define_expand "reduc_uplus_v2si" -+ [(set (match_operand:V2SI 0 "register_operand" "=w") -+ (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "w")] -+ UNSPEC_ADDV))] -+ "TARGET_SIMD" -+ "" -+) -+ -+(define_expand "reduc_splus_v2si" -+ [(set (match_operand:V2SI 0 "register_operand" "=w") -+ (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "w")] -+ UNSPEC_ADDV))] -+ "TARGET_SIMD" -+ "" -+) -+ -+(define_insn "reduc__" -+ [(set (match_operand:VDQV 0 "register_operand" "=w") -+ (unspec:VDQV [(match_operand:VDQV 1 "register_operand" "w")] -+ MAXMINV))] -+ "TARGET_SIMD" -+ "v\\t%0, %1." -+ [(set_attr "simd_type" "simd_minmaxv") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "reduc__v2si" -+ [(set (match_operand:V2SI 0 "register_operand" "=w") -+ (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "w")] -+ MAXMINV))] -+ "TARGET_SIMD" -+ "p\\t%0.2s, %1.2s, %1.2s" -+ [(set_attr "simd_type" "simd_minmax") -+ (set_attr "simd_mode" "V2SI")] -+) -+ -+;; Patterns for AArch64 SIMD Intrinsics. -+ -+(define_expand "aarch64_create" -+ [(match_operand:VD_RE 0 "register_operand" "") -+ (match_operand:DI 1 "general_operand" "")] -+ "TARGET_SIMD" -+{ -+ rtx src = gen_lowpart (mode, operands[1]); -+ emit_move_insn (operands[0], src); -+ DONE; -+}) -+ -+(define_insn "aarch64_get_lane_signed" -+ [(set (match_operand: 0 "register_operand" "=r") -+ (sign_extend: -+ (vec_select: -+ (match_operand:VQ_S 1 "register_operand" "w") -+ (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))] -+ "TARGET_SIMD" -+ "smov\\t%0, %1.[%2]" -+ [(set_attr "simd_type" "simd_movgp") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "aarch64_get_lane_unsigned" -+ [(set (match_operand: 0 "register_operand" "=r") -+ (zero_extend: -+ (vec_select: -+ (match_operand:VDQ 1 "register_operand" "w") -+ (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))] -+ "TARGET_SIMD" -+ "umov\\t%0, %1.[%2]" -+ [(set_attr "simd_type" "simd_movgp") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "aarch64_get_lane" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (vec_select: -+ (match_operand:VDQF 1 "register_operand" "w") -+ (parallel [(match_operand:SI 2 "immediate_operand" "i")])))] -+ "TARGET_SIMD" -+ "mov\\t%0.[0], %1.[%2]" -+ [(set_attr "simd_type" "simd_ins") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_expand "aarch64_get_lanedi" -+ [(match_operand:DI 0 "register_operand" "=r") -+ (match_operand:DI 1 "register_operand" "w") -+ (match_operand:SI 2 "immediate_operand" "i")] -+ "TARGET_SIMD" -+{ -+ aarch64_simd_lane_bounds (operands[2], 0, 1); -+ emit_move_insn (operands[0], operands[1]); -+ DONE; -+}) -+ -+(define_expand "aarch64_reinterpretv8qi" -+ [(match_operand:V8QI 0 "register_operand" "") -+ (match_operand:VDC 1 "register_operand" "")] -+ "TARGET_SIMD" -+{ -+ aarch64_simd_reinterpret (operands[0], operands[1]); -+ DONE; -+}) -+ -+(define_expand "aarch64_reinterpretv4hi" -+ [(match_operand:V4HI 0 "register_operand" "") -+ (match_operand:VDC 1 "register_operand" "")] -+ "TARGET_SIMD" -+{ -+ aarch64_simd_reinterpret (operands[0], operands[1]); -+ DONE; -+}) -+ -+(define_expand "aarch64_reinterpretv2si" -+ [(match_operand:V2SI 0 "register_operand" "") -+ (match_operand:VDC 1 "register_operand" "")] -+ "TARGET_SIMD" -+{ -+ aarch64_simd_reinterpret (operands[0], operands[1]); -+ DONE; -+}) -+ -+(define_expand "aarch64_reinterpretv2sf" -+ [(match_operand:V2SF 0 "register_operand" "") -+ (match_operand:VDC 1 "register_operand" "")] -+ "TARGET_SIMD" -+{ -+ aarch64_simd_reinterpret (operands[0], operands[1]); -+ DONE; -+}) -+ -+(define_expand "aarch64_reinterpretdi" -+ [(match_operand:DI 0 "register_operand" "") -+ (match_operand:VD_RE 1 "register_operand" "")] -+ "TARGET_SIMD" -+{ -+ aarch64_simd_reinterpret (operands[0], operands[1]); -+ DONE; -+}) -+ -+(define_expand "aarch64_reinterpretv16qi" -+ [(match_operand:V16QI 0 "register_operand" "") -+ (match_operand:VQ 1 "register_operand" "")] -+ "TARGET_SIMD" -+{ -+ aarch64_simd_reinterpret (operands[0], operands[1]); -+ DONE; -+}) -+ -+(define_expand "aarch64_reinterpretv8hi" -+ [(match_operand:V8HI 0 "register_operand" "") -+ (match_operand:VQ 1 "register_operand" "")] -+ "TARGET_SIMD" -+{ -+ aarch64_simd_reinterpret (operands[0], operands[1]); -+ DONE; -+}) -+ -+(define_expand "aarch64_reinterpretv4si" -+ [(match_operand:V4SI 0 "register_operand" "") -+ (match_operand:VQ 1 "register_operand" "")] -+ "TARGET_SIMD" -+{ -+ aarch64_simd_reinterpret (operands[0], operands[1]); -+ DONE; -+}) -+ -+(define_expand "aarch64_reinterpretv4sf" -+ [(match_operand:V4SF 0 "register_operand" "") -+ (match_operand:VQ 1 "register_operand" "")] -+ "TARGET_SIMD" -+{ -+ aarch64_simd_reinterpret (operands[0], operands[1]); -+ DONE; -+}) -+ -+(define_expand "aarch64_reinterpretv2di" -+ [(match_operand:V2DI 0 "register_operand" "") -+ (match_operand:VQ 1 "register_operand" "")] -+ "TARGET_SIMD" -+{ -+ aarch64_simd_reinterpret (operands[0], operands[1]); -+ DONE; -+}) -+ -+(define_expand "aarch64_reinterpretv2df" -+ [(match_operand:V2DF 0 "register_operand" "") -+ (match_operand:VQ 1 "register_operand" "")] -+ "TARGET_SIMD" -+{ -+ aarch64_simd_reinterpret (operands[0], operands[1]); -+ DONE; -+}) -+ -+;; In this insn, operand 1 should be low, and operand 2 the high part of the -+;; dest vector. -+ -+(define_insn "aarch64_combine" -+ [(set (match_operand: 0 "register_operand" "=&w") -+ (vec_concat: (match_operand:VDC 1 "register_operand" "w") -+ (match_operand:VDC 2 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "mov\\t%0.d[0], %1.d[0]\;ins\\t%0.d[1], %2.d[0]" -+ [(set_attr "simd_type" "simd_ins") -+ (set_attr "simd_mode" "")] -+) -+ -+;; l. -+ -+(define_insn "aarch64_l2_internal" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (ADDSUB: (ANY_EXTEND: (vec_select: -+ (match_operand:VQW 1 "register_operand" "w") -+ (match_operand:VQW 3 "vect_par_cnst_hi_half" ""))) -+ (ANY_EXTEND: (vec_select: -+ (match_operand:VQW 2 "register_operand" "w") -+ (match_dup 3)))))] -+ "TARGET_SIMD" -+ "l2 %0., %1., %2." -+ [(set_attr "simd_type" "simd_addl") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_expand "aarch64_saddl2" -+ [(match_operand: 0 "register_operand" "=w") -+ (match_operand:VQW 1 "register_operand" "w") -+ (match_operand:VQW 2 "register_operand" "w")] -+ "TARGET_SIMD" -+{ -+ rtx p = aarch64_simd_vect_par_cnst_half (mode, true); -+ emit_insn (gen_aarch64_saddl2_internal (operands[0], operands[1], -+ operands[2], p)); -+ DONE; -+}) -+ -+(define_expand "aarch64_uaddl2" -+ [(match_operand: 0 "register_operand" "=w") -+ (match_operand:VQW 1 "register_operand" "w") -+ (match_operand:VQW 2 "register_operand" "w")] -+ "TARGET_SIMD" -+{ -+ rtx p = aarch64_simd_vect_par_cnst_half (mode, true); -+ emit_insn (gen_aarch64_uaddl2_internal (operands[0], operands[1], -+ operands[2], p)); -+ DONE; -+}) -+ -+(define_expand "aarch64_ssubl2" -+ [(match_operand: 0 "register_operand" "=w") -+ (match_operand:VQW 1 "register_operand" "w") -+ (match_operand:VQW 2 "register_operand" "w")] -+ "TARGET_SIMD" -+{ -+ rtx p = aarch64_simd_vect_par_cnst_half (mode, true); -+ emit_insn (gen_aarch64_ssubl2_internal (operands[0], operands[1], -+ operands[2], p)); -+ DONE; -+}) -+ -+(define_expand "aarch64_usubl2" -+ [(match_operand: 0 "register_operand" "=w") -+ (match_operand:VQW 1 "register_operand" "w") -+ (match_operand:VQW 2 "register_operand" "w")] -+ "TARGET_SIMD" -+{ -+ rtx p = aarch64_simd_vect_par_cnst_half (mode, true); -+ emit_insn (gen_aarch64_usubl2_internal (operands[0], operands[1], -+ operands[2], p)); -+ DONE; -+}) -+ -+(define_insn "aarch64_l" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (ADDSUB: (ANY_EXTEND: -+ (match_operand:VDW 1 "register_operand" "w")) -+ (ANY_EXTEND: -+ (match_operand:VDW 2 "register_operand" "w"))))] -+ "TARGET_SIMD" -+ "l %0., %1., %2." -+ [(set_attr "simd_type" "simd_addl") -+ (set_attr "simd_mode" "")] -+) -+ -+;; w. -+ -+(define_insn "aarch64_w" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (ADDSUB: (match_operand: 1 "register_operand" "w") -+ (ANY_EXTEND: -+ (match_operand:VDW 2 "register_operand" "w"))))] -+ "TARGET_SIMD" -+ "w\\t%0., %1., %2." -+ [(set_attr "simd_type" "simd_addl") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "aarch64_w2_internal" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (ADDSUB: (match_operand: 1 "register_operand" "w") -+ (ANY_EXTEND: -+ (vec_select: -+ (match_operand:VQW 2 "register_operand" "w") -+ (match_operand:VQW 3 "vect_par_cnst_hi_half" "")))))] -+ "TARGET_SIMD" -+ "w2\\t%0., %1., %2." -+ [(set_attr "simd_type" "simd_addl") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_expand "aarch64_saddw2" -+ [(match_operand: 0 "register_operand" "=w") -+ (match_operand: 1 "register_operand" "w") -+ (match_operand:VQW 2 "register_operand" "w")] -+ "TARGET_SIMD" -+{ -+ rtx p = aarch64_simd_vect_par_cnst_half (mode, true); -+ emit_insn (gen_aarch64_saddw2_internal (operands[0], operands[1], -+ operands[2], p)); -+ DONE; -+}) -+ -+(define_expand "aarch64_uaddw2" -+ [(match_operand: 0 "register_operand" "=w") -+ (match_operand: 1 "register_operand" "w") -+ (match_operand:VQW 2 "register_operand" "w")] -+ "TARGET_SIMD" -+{ -+ rtx p = aarch64_simd_vect_par_cnst_half (mode, true); -+ emit_insn (gen_aarch64_uaddw2_internal (operands[0], operands[1], -+ operands[2], p)); -+ DONE; -+}) -+ -+ -+(define_expand "aarch64_ssubw2" -+ [(match_operand: 0 "register_operand" "=w") -+ (match_operand: 1 "register_operand" "w") -+ (match_operand:VQW 2 "register_operand" "w")] -+ "TARGET_SIMD" -+{ -+ rtx p = aarch64_simd_vect_par_cnst_half (mode, true); -+ emit_insn (gen_aarch64_ssubw2_internal (operands[0], operands[1], -+ operands[2], p)); -+ DONE; -+}) -+ -+(define_expand "aarch64_usubw2" -+ [(match_operand: 0 "register_operand" "=w") -+ (match_operand: 1 "register_operand" "w") -+ (match_operand:VQW 2 "register_operand" "w")] -+ "TARGET_SIMD" -+{ -+ rtx p = aarch64_simd_vect_par_cnst_half (mode, true); -+ emit_insn (gen_aarch64_usubw2_internal (operands[0], operands[1], -+ operands[2], p)); -+ DONE; -+}) -+ -+;; h. -+ -+(define_insn "aarch64_h" -+ [(set (match_operand:VQ_S 0 "register_operand" "=w") -+ (unspec:VQ_S [(match_operand:VQ_S 1 "register_operand" "w") -+ (match_operand:VQ_S 2 "register_operand" "w")] -+ HADDSUB))] -+ "TARGET_SIMD" -+ "h\\t%0., %1., %2." -+ [(set_attr "simd_type" "simd_add") -+ (set_attr "simd_mode" "")] -+) -+ -+;; hn. -+ -+(define_insn "aarch64_hn" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (unspec: [(match_operand:VQN 1 "register_operand" "w") -+ (match_operand:VQN 2 "register_operand" "w")] -+ ADDSUBHN))] -+ "TARGET_SIMD" -+ "hn\\t%0., %1., %2." -+ [(set_attr "simd_type" "simd_addn") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "aarch64_hn2" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (unspec: [(match_operand: 1 "register_operand" "0") -+ (match_operand:VQN 2 "register_operand" "w") -+ (match_operand:VQN 3 "register_operand" "w")] -+ ADDSUBHN2))] -+ "TARGET_SIMD" -+ "hn2\\t%0., %2., %3." -+ [(set_attr "simd_type" "simd_addn2") -+ (set_attr "simd_mode" "")] -+) -+ -+;; pmul. -+ -+(define_insn "aarch64_pmul" -+ [(set (match_operand:VB 0 "register_operand" "=w") -+ (unspec:VB [(match_operand:VB 1 "register_operand" "w") -+ (match_operand:VB 2 "register_operand" "w")] -+ UNSPEC_PMUL))] -+ "TARGET_SIMD" -+ "pmul\\t%0., %1., %2." -+ [(set_attr "simd_type" "simd_mul") -+ (set_attr "simd_mode" "")] -+) -+ -+;; q -+ -+(define_insn "aarch64_" -+ [(set (match_operand:VSDQ_I 0 "register_operand" "=w") -+ (BINQOPS:VSDQ_I (match_operand:VSDQ_I 1 "register_operand" "w") -+ (match_operand:VSDQ_I 2 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "\\t%0, %1, %2" -+ [(set_attr "simd_type" "simd_add") -+ (set_attr "simd_mode" "")] -+) -+ -+;; suqadd and usqadd -+ -+(define_insn "aarch64_qadd" -+ [(set (match_operand:VSDQ_I 0 "register_operand" "=w") -+ (unspec:VSDQ_I [(match_operand:VSDQ_I 1 "register_operand" "0") -+ (match_operand:VSDQ_I 2 "register_operand" "w")] -+ USSUQADD))] -+ "TARGET_SIMD" -+ "qadd\\t%0, %2" -+ [(set_attr "simd_type" "simd_sat_add") -+ (set_attr "simd_mode" "")] -+) -+ -+;; sqmovun -+ -+(define_insn "aarch64_sqmovun" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (unspec: [(match_operand:VSQN_HSDI 1 "register_operand" "w")] -+ UNSPEC_SQXTUN))] -+ "TARGET_SIMD" -+ "sqxtun\\t%0, %1" -+ [(set_attr "simd_type" "simd_sat_shiftn_imm") -+ (set_attr "simd_mode" "")] -+ ) -+ -+;; sqmovn and uqmovn -+ -+(define_insn "aarch64_qmovn" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (unspec: [(match_operand:VSQN_HSDI 1 "register_operand" "w")] -+ SUQMOVN))] -+ "TARGET_SIMD" -+ "qxtn\\t%0, %1" -+ [(set_attr "simd_type" "simd_sat_shiftn_imm") -+ (set_attr "simd_mode" "")] -+ ) -+ -+;; q -+ -+(define_insn "aarch64_s" -+ [(set (match_operand:VSDQ_I_BHSI 0 "register_operand" "=w") -+ (UNQOPS:VSDQ_I_BHSI -+ (match_operand:VSDQ_I_BHSI 1 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "s\\t%0, %1" -+ [(set_attr "simd_type" "simd_sat_negabs") -+ (set_attr "simd_mode" "")] -+) -+ -+;; sqdmulh. -+ -+(define_insn "aarch64_sqdmulh" -+ [(set (match_operand:VSDQ_HSI 0 "register_operand" "=w") -+ (unspec:VSDQ_HSI -+ [(match_operand:VSDQ_HSI 1 "register_operand" "w") -+ (match_operand:VSDQ_HSI 2 "register_operand" "w")] -+ VQDMULH))] -+ "TARGET_SIMD" -+ "sqdmulh\\t%0, %1, %2" -+ [(set_attr "simd_type" "simd_sat_mul") -+ (set_attr "simd_mode" "")] -+) -+ -+;; sqdmulh_lane -+ -+(define_insn "aarch64_sqdmulh_lane" -+ [(set (match_operand:VSDQ_HSI 0 "register_operand" "=w") -+ (unspec:VSDQ_HSI -+ [(match_operand:VSDQ_HSI 1 "register_operand" "w") -+ (vec_select: -+ (match_operand: 2 "register_operand" "") -+ (parallel [(match_operand:SI 3 "immediate_operand" "i")]))] -+ VQDMULH))] -+ "TARGET_SIMD" -+ "* -+ aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); -+ return \"sqdmulh\\t%0, %1, %2.[%3]\";" -+ [(set_attr "simd_type" "simd_sat_mul") -+ (set_attr "simd_mode" "")] -+) -+ -+;; vqdml[sa]l -+ -+(define_insn "aarch64_sqdmll" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (SBINQOPS: -+ (match_operand: 1 "register_operand" "0") -+ (ss_ashift: -+ (mult: -+ (sign_extend: -+ (match_operand:VSD_HSI 2 "register_operand" "w")) -+ (sign_extend: -+ (match_operand:VSD_HSI 3 "register_operand" "w"))) -+ (const_int 1))))] -+ "TARGET_SIMD" -+ "sqdmll\\t%0, %2, %3" -+ [(set_attr "simd_type" "simd_sat_mlal") -+ (set_attr "simd_mode" "")] -+) -+ -+;; vqdml[sa]l_lane -+ -+(define_insn "aarch64_sqdmll_lane_internal" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (SBINQOPS: -+ (match_operand: 1 "register_operand" "0") -+ (ss_ashift: -+ (mult: -+ (sign_extend: -+ (match_operand:VD_HSI 2 "register_operand" "w")) -+ (sign_extend: -+ (vec_duplicate:VD_HSI -+ (vec_select: -+ (match_operand: 3 "register_operand" "") -+ (parallel [(match_operand:SI 4 "immediate_operand" "i")]))) -+ )) -+ (const_int 1))))] -+ "TARGET_SIMD" -+ "sqdmll\\t%0, %2, %3.[%4]" -+ [(set_attr "simd_type" "simd_sat_mlal") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "aarch64_sqdmll_lane_internal" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (SBINQOPS: -+ (match_operand: 1 "register_operand" "0") -+ (ss_ashift: -+ (mult: -+ (sign_extend: -+ (match_operand:SD_HSI 2 "register_operand" "w")) -+ (sign_extend: -+ (vec_select: -+ (match_operand: 3 "register_operand" "") -+ (parallel [(match_operand:SI 4 "immediate_operand" "i")]))) -+ ) -+ (const_int 1))))] -+ "TARGET_SIMD" -+ "sqdmll\\t%0, %2, %3.[%4]" -+ [(set_attr "simd_type" "simd_sat_mlal") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_expand "aarch64_sqdmlal_lane" -+ [(match_operand: 0 "register_operand" "=w") -+ (match_operand: 1 "register_operand" "0") -+ (match_operand:VSD_HSI 2 "register_operand" "w") -+ (match_operand: 3 "register_operand" "") -+ (match_operand:SI 4 "immediate_operand" "i")] -+ "TARGET_SIMD" -+{ -+ aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (mode) / 2); -+ emit_insn (gen_aarch64_sqdmlal_lane_internal (operands[0], operands[1], -+ operands[2], operands[3], -+ operands[4])); -+ DONE; -+}) -+ -+(define_expand "aarch64_sqdmlal_laneq" -+ [(match_operand: 0 "register_operand" "=w") -+ (match_operand: 1 "register_operand" "0") -+ (match_operand:VSD_HSI 2 "register_operand" "w") -+ (match_operand: 3 "register_operand" "") -+ (match_operand:SI 4 "immediate_operand" "i")] -+ "TARGET_SIMD" -+{ -+ aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (mode)); -+ emit_insn (gen_aarch64_sqdmlal_lane_internal (operands[0], operands[1], -+ operands[2], operands[3], -+ operands[4])); -+ DONE; -+}) -+ -+(define_expand "aarch64_sqdmlsl_lane" -+ [(match_operand: 0 "register_operand" "=w") -+ (match_operand: 1 "register_operand" "0") -+ (match_operand:VSD_HSI 2 "register_operand" "w") -+ (match_operand: 3 "register_operand" "") -+ (match_operand:SI 4 "immediate_operand" "i")] -+ "TARGET_SIMD" -+{ -+ aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (mode) / 2); -+ emit_insn (gen_aarch64_sqdmlsl_lane_internal (operands[0], operands[1], -+ operands[2], operands[3], -+ operands[4])); -+ DONE; -+}) -+ -+(define_expand "aarch64_sqdmlsl_laneq" -+ [(match_operand: 0 "register_operand" "=w") -+ (match_operand: 1 "register_operand" "0") -+ (match_operand:VSD_HSI 2 "register_operand" "w") -+ (match_operand: 3 "register_operand" "") -+ (match_operand:SI 4 "immediate_operand" "i")] -+ "TARGET_SIMD" -+{ -+ aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (mode)); -+ emit_insn (gen_aarch64_sqdmlsl_lane_internal (operands[0], operands[1], -+ operands[2], operands[3], -+ operands[4])); -+ DONE; -+}) -+ -+;; vqdml[sa]l_n -+ -+(define_insn "aarch64_sqdmll_n" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (SBINQOPS: -+ (match_operand: 1 "register_operand" "0") -+ (ss_ashift: -+ (mult: -+ (sign_extend: -+ (match_operand:VD_HSI 2 "register_operand" "w")) -+ (sign_extend: -+ (vec_duplicate:VD_HSI -+ (match_operand: 3 "register_operand" "w")))) -+ (const_int 1))))] -+ "TARGET_SIMD" -+ "sqdmll\\t%0, %2, %3.[0]" -+ [(set_attr "simd_type" "simd_sat_mlal") -+ (set_attr "simd_mode" "")] -+) -+ -+;; sqdml[as]l2 -+ -+(define_insn "aarch64_sqdmll2_internal" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (SBINQOPS: -+ (match_operand: 1 "register_operand" "0") -+ (ss_ashift: -+ (mult: -+ (sign_extend: -+ (vec_select: -+ (match_operand:VQ_HSI 2 "register_operand" "w") -+ (match_operand:VQ_HSI 4 "vect_par_cnst_hi_half" ""))) -+ (sign_extend: -+ (vec_select: -+ (match_operand:VQ_HSI 3 "register_operand" "w") -+ (match_dup 4)))) -+ (const_int 1))))] -+ "TARGET_SIMD" -+ "sqdmll2\\t%0, %2, %3" -+ [(set_attr "simd_type" "simd_sat_mlal") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_expand "aarch64_sqdmlal2" -+ [(match_operand: 0 "register_operand" "=w") -+ (match_operand: 1 "register_operand" "w") -+ (match_operand:VQ_HSI 2 "register_operand" "w") -+ (match_operand:VQ_HSI 3 "register_operand" "w")] -+ "TARGET_SIMD" -+{ -+ rtx p = aarch64_simd_vect_par_cnst_half (mode, true); -+ emit_insn (gen_aarch64_sqdmlal2_internal (operands[0], operands[1], -+ operands[2], operands[3], p)); -+ DONE; -+}) -+ -+(define_expand "aarch64_sqdmlsl2" -+ [(match_operand: 0 "register_operand" "=w") -+ (match_operand: 1 "register_operand" "w") -+ (match_operand:VQ_HSI 2 "register_operand" "w") -+ (match_operand:VQ_HSI 3 "register_operand" "w")] -+ "TARGET_SIMD" -+{ -+ rtx p = aarch64_simd_vect_par_cnst_half (mode, true); -+ emit_insn (gen_aarch64_sqdmlsl2_internal (operands[0], operands[1], -+ operands[2], operands[3], p)); -+ DONE; -+}) -+ -+;; vqdml[sa]l2_lane -+ -+(define_insn "aarch64_sqdmll2_lane_internal" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (SBINQOPS: -+ (match_operand: 1 "register_operand" "0") -+ (ss_ashift: -+ (mult: -+ (sign_extend: -+ (vec_select: -+ (match_operand:VQ_HSI 2 "register_operand" "w") -+ (match_operand:VQ_HSI 5 "vect_par_cnst_hi_half" ""))) -+ (sign_extend: -+ (vec_duplicate: -+ (vec_select: -+ (match_operand: 3 "register_operand" "") -+ (parallel [(match_operand:SI 4 "immediate_operand" "i")]) -+ )))) -+ (const_int 1))))] -+ "TARGET_SIMD" -+ "sqdmll2\\t%0, %2, %3.[%4]" -+ [(set_attr "simd_type" "simd_sat_mlal") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_expand "aarch64_sqdmlal2_lane" -+ [(match_operand: 0 "register_operand" "=w") -+ (match_operand: 1 "register_operand" "w") -+ (match_operand:VQ_HSI 2 "register_operand" "w") -+ (match_operand: 3 "register_operand" "") -+ (match_operand:SI 4 "immediate_operand" "i")] -+ "TARGET_SIMD" -+{ -+ rtx p = aarch64_simd_vect_par_cnst_half (mode, true); -+ aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (mode) / 2); -+ emit_insn (gen_aarch64_sqdmlal2_lane_internal (operands[0], operands[1], -+ operands[2], operands[3], -+ operands[4], p)); -+ DONE; -+}) -+ -+(define_expand "aarch64_sqdmlal2_laneq" -+ [(match_operand: 0 "register_operand" "=w") -+ (match_operand: 1 "register_operand" "w") -+ (match_operand:VQ_HSI 2 "register_operand" "w") -+ (match_operand: 3 "register_operand" "") -+ (match_operand:SI 4 "immediate_operand" "i")] -+ "TARGET_SIMD" -+{ -+ rtx p = aarch64_simd_vect_par_cnst_half (mode, true); -+ aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (mode)); -+ emit_insn (gen_aarch64_sqdmlal2_lane_internal (operands[0], operands[1], -+ operands[2], operands[3], -+ operands[4], p)); -+ DONE; -+}) -+ -+(define_expand "aarch64_sqdmlsl2_lane" -+ [(match_operand: 0 "register_operand" "=w") -+ (match_operand: 1 "register_operand" "w") -+ (match_operand:VQ_HSI 2 "register_operand" "w") -+ (match_operand: 3 "register_operand" "") -+ (match_operand:SI 4 "immediate_operand" "i")] -+ "TARGET_SIMD" -+{ -+ rtx p = aarch64_simd_vect_par_cnst_half (mode, true); -+ aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (mode) / 2); -+ emit_insn (gen_aarch64_sqdmlsl2_lane_internal (operands[0], operands[1], -+ operands[2], operands[3], -+ operands[4], p)); -+ DONE; -+}) -+ -+(define_expand "aarch64_sqdmlsl2_laneq" -+ [(match_operand: 0 "register_operand" "=w") -+ (match_operand: 1 "register_operand" "w") -+ (match_operand:VQ_HSI 2 "register_operand" "w") -+ (match_operand: 3 "register_operand" "") -+ (match_operand:SI 4 "immediate_operand" "i")] -+ "TARGET_SIMD" -+{ -+ rtx p = aarch64_simd_vect_par_cnst_half (mode, true); -+ aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (mode)); -+ emit_insn (gen_aarch64_sqdmlsl2_lane_internal (operands[0], operands[1], -+ operands[2], operands[3], -+ operands[4], p)); -+ DONE; -+}) -+ -+(define_insn "aarch64_sqdmll2_n_internal" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (SBINQOPS: -+ (match_operand: 1 "register_operand" "0") -+ (ss_ashift: -+ (mult: -+ (sign_extend: -+ (vec_select: -+ (match_operand:VQ_HSI 2 "register_operand" "w") -+ (match_operand:VQ_HSI 4 "vect_par_cnst_hi_half" ""))) -+ (sign_extend: -+ (vec_duplicate: -+ (match_operand: 3 "register_operand" "w")))) -+ (const_int 1))))] -+ "TARGET_SIMD" -+ "sqdmll2\\t%0, %2, %3.[0]" -+ [(set_attr "simd_type" "simd_sat_mlal") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_expand "aarch64_sqdmlal2_n" -+ [(match_operand: 0 "register_operand" "=w") -+ (match_operand: 1 "register_operand" "w") -+ (match_operand:VQ_HSI 2 "register_operand" "w") -+ (match_operand: 3 "register_operand" "w")] -+ "TARGET_SIMD" -+{ -+ rtx p = aarch64_simd_vect_par_cnst_half (mode, true); -+ emit_insn (gen_aarch64_sqdmlal2_n_internal (operands[0], operands[1], -+ operands[2], operands[3], -+ p)); -+ DONE; -+}) -+ -+(define_expand "aarch64_sqdmlsl2_n" -+ [(match_operand: 0 "register_operand" "=w") -+ (match_operand: 1 "register_operand" "w") -+ (match_operand:VQ_HSI 2 "register_operand" "w") -+ (match_operand: 3 "register_operand" "w")] -+ "TARGET_SIMD" -+{ -+ rtx p = aarch64_simd_vect_par_cnst_half (mode, true); -+ emit_insn (gen_aarch64_sqdmlsl2_n_internal (operands[0], operands[1], -+ operands[2], operands[3], -+ p)); -+ DONE; -+}) -+ -+;; vqdmull -+ -+(define_insn "aarch64_sqdmull" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (ss_ashift: -+ (mult: -+ (sign_extend: -+ (match_operand:VSD_HSI 1 "register_operand" "w")) -+ (sign_extend: -+ (match_operand:VSD_HSI 2 "register_operand" "w"))) -+ (const_int 1)))] -+ "TARGET_SIMD" -+ "sqdmull\\t%0, %1, %2" -+ [(set_attr "simd_type" "simd_sat_mul") -+ (set_attr "simd_mode" "")] -+) -+ -+;; vqdmull_lane -+ -+(define_insn "aarch64_sqdmull_lane_internal" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (ss_ashift: -+ (mult: -+ (sign_extend: -+ (match_operand:VD_HSI 1 "register_operand" "w")) -+ (sign_extend: -+ (vec_duplicate:VD_HSI -+ (vec_select: -+ (match_operand: 2 "register_operand" "") -+ (parallel [(match_operand:SI 3 "immediate_operand" "i")]))) -+ )) -+ (const_int 1)))] -+ "TARGET_SIMD" -+ "sqdmull\\t%0, %1, %2.[%3]" -+ [(set_attr "simd_type" "simd_sat_mul") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "aarch64_sqdmull_lane_internal" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (ss_ashift: -+ (mult: -+ (sign_extend: -+ (match_operand:SD_HSI 1 "register_operand" "w")) -+ (sign_extend: -+ (vec_select: -+ (match_operand: 2 "register_operand" "") -+ (parallel [(match_operand:SI 3 "immediate_operand" "i")])) -+ )) -+ (const_int 1)))] -+ "TARGET_SIMD" -+ "sqdmull\\t%0, %1, %2.[%3]" -+ [(set_attr "simd_type" "simd_sat_mul") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_expand "aarch64_sqdmull_lane" -+ [(match_operand: 0 "register_operand" "=w") -+ (match_operand:VSD_HSI 1 "register_operand" "w") -+ (match_operand: 2 "register_operand" "") -+ (match_operand:SI 3 "immediate_operand" "i")] -+ "TARGET_SIMD" -+{ -+ aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode) / 2); -+ emit_insn (gen_aarch64_sqdmull_lane_internal (operands[0], operands[1], -+ operands[2], operands[3])); -+ DONE; -+}) -+ -+(define_expand "aarch64_sqdmull_laneq" -+ [(match_operand: 0 "register_operand" "=w") -+ (match_operand:VD_HSI 1 "register_operand" "w") -+ (match_operand: 2 "register_operand" "") -+ (match_operand:SI 3 "immediate_operand" "i")] -+ "TARGET_SIMD" -+{ -+ aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); -+ emit_insn (gen_aarch64_sqdmull_lane_internal -+ (operands[0], operands[1], operands[2], operands[3])); -+ DONE; -+}) -+ -+;; vqdmull_n -+ -+(define_insn "aarch64_sqdmull_n" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (ss_ashift: -+ (mult: -+ (sign_extend: -+ (match_operand:VD_HSI 1 "register_operand" "w")) -+ (sign_extend: -+ (vec_duplicate:VD_HSI -+ (match_operand: 2 "register_operand" "w"))) -+ ) -+ (const_int 1)))] -+ "TARGET_SIMD" -+ "sqdmull\\t%0, %1, %2.[0]" -+ [(set_attr "simd_type" "simd_sat_mul") -+ (set_attr "simd_mode" "")] -+) -+ -+;; vqdmull2 -+ -+ -+ -+(define_insn "aarch64_sqdmull2_internal" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (ss_ashift: -+ (mult: -+ (sign_extend: -+ (vec_select: -+ (match_operand:VQ_HSI 1 "register_operand" "w") -+ (match_operand:VQ_HSI 3 "vect_par_cnst_hi_half" ""))) -+ (sign_extend: -+ (vec_select: -+ (match_operand:VQ_HSI 2 "register_operand" "w") -+ (match_dup 3))) -+ ) -+ (const_int 1)))] -+ "TARGET_SIMD" -+ "sqdmull2\\t%0, %1, %2" -+ [(set_attr "simd_type" "simd_sat_mul") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_expand "aarch64_sqdmull2" -+ [(match_operand: 0 "register_operand" "=w") -+ (match_operand:VQ_HSI 1 "register_operand" "w") -+ (match_operand: 2 "register_operand" "w")] -+ "TARGET_SIMD" -+{ -+ rtx p = aarch64_simd_vect_par_cnst_half (mode, true); -+ emit_insn (gen_aarch64_sqdmull2_internal (operands[0], operands[1], -+ operands[2], p)); -+ DONE; -+}) -+ -+;; vqdmull2_lane -+ -+(define_insn "aarch64_sqdmull2_lane_internal" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (ss_ashift: -+ (mult: -+ (sign_extend: -+ (vec_select: -+ (match_operand:VQ_HSI 1 "register_operand" "w") -+ (match_operand:VQ_HSI 4 "vect_par_cnst_hi_half" ""))) -+ (sign_extend: -+ (vec_duplicate: -+ (vec_select: -+ (match_operand: 2 "register_operand" "") -+ (parallel [(match_operand:SI 3 "immediate_operand" "i")]))) -+ )) -+ (const_int 1)))] -+ "TARGET_SIMD" -+ "sqdmull2\\t%0, %1, %2.[%3]" -+ [(set_attr "simd_type" "simd_sat_mul") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_expand "aarch64_sqdmull2_lane" -+ [(match_operand: 0 "register_operand" "=w") -+ (match_operand:VQ_HSI 1 "register_operand" "w") -+ (match_operand: 2 "register_operand" "") -+ (match_operand:SI 3 "immediate_operand" "i")] -+ "TARGET_SIMD" -+{ -+ rtx p = aarch64_simd_vect_par_cnst_half (mode, true); -+ aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode) / 2); -+ emit_insn (gen_aarch64_sqdmull2_lane_internal (operands[0], operands[1], -+ operands[2], operands[3], -+ p)); -+ DONE; -+}) -+ -+(define_expand "aarch64_sqdmull2_laneq" -+ [(match_operand: 0 "register_operand" "=w") -+ (match_operand:VQ_HSI 1 "register_operand" "w") -+ (match_operand: 2 "register_operand" "") -+ (match_operand:SI 3 "immediate_operand" "i")] -+ "TARGET_SIMD" -+{ -+ rtx p = aarch64_simd_vect_par_cnst_half (mode, true); -+ aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); -+ emit_insn (gen_aarch64_sqdmull2_lane_internal (operands[0], operands[1], -+ operands[2], operands[3], -+ p)); -+ DONE; -+}) -+ -+;; vqdmull2_n -+ -+(define_insn "aarch64_sqdmull2_n_internal" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (ss_ashift: -+ (mult: -+ (sign_extend: -+ (vec_select: -+ (match_operand:VQ_HSI 1 "register_operand" "w") -+ (match_operand:VQ_HSI 3 "vect_par_cnst_hi_half" ""))) -+ (sign_extend: -+ (vec_duplicate: -+ (match_operand: 2 "register_operand" "w"))) -+ ) -+ (const_int 1)))] -+ "TARGET_SIMD" -+ "sqdmull2\\t%0, %1, %2.[0]" -+ [(set_attr "simd_type" "simd_sat_mul") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_expand "aarch64_sqdmull2_n" -+ [(match_operand: 0 "register_operand" "=w") -+ (match_operand:VQ_HSI 1 "register_operand" "w") -+ (match_operand: 2 "register_operand" "w")] -+ "TARGET_SIMD" -+{ -+ rtx p = aarch64_simd_vect_par_cnst_half (mode, true); -+ emit_insn (gen_aarch64_sqdmull2_n_internal (operands[0], operands[1], -+ operands[2], p)); -+ DONE; -+}) -+ -+;; vshl -+ -+(define_insn "aarch64_shl" -+ [(set (match_operand:VSDQ_I_DI 0 "register_operand" "=w") -+ (unspec:VSDQ_I_DI -+ [(match_operand:VSDQ_I_DI 1 "register_operand" "w") -+ (match_operand:VSDQ_I_DI 2 "register_operand" "w")] -+ VSHL))] -+ "TARGET_SIMD" -+ "shl\\t%0, %1, %2"; -+ [(set_attr "simd_type" "simd_shift") -+ (set_attr "simd_mode" "")] -+) -+ -+ -+;; vqshl -+ -+(define_insn "aarch64_qshl" -+ [(set (match_operand:VSDQ_I 0 "register_operand" "=w") -+ (unspec:VSDQ_I -+ [(match_operand:VSDQ_I 1 "register_operand" "w") -+ (match_operand:VSDQ_I 2 "register_operand" "w")] -+ VQSHL))] -+ "TARGET_SIMD" -+ "qshl\\t%0, %1, %2"; -+ [(set_attr "simd_type" "simd_sat_shift") -+ (set_attr "simd_mode" "")] -+) -+ -+;; vshl_n -+ -+(define_expand "aarch64_sshl_n" -+ [(match_operand:VSDQ_I_DI 0 "register_operand" "=w") -+ (match_operand:VSDQ_I_DI 1 "register_operand" "w") -+ (match_operand:SI 2 "immediate_operand" "i")] -+ "TARGET_SIMD" -+{ -+ emit_insn (gen_ashl3 (operands[0], operands[1], operands[2])); -+ DONE; -+}) -+ -+(define_expand "aarch64_ushl_n" -+ [(match_operand:VSDQ_I_DI 0 "register_operand" "=w") -+ (match_operand:VSDQ_I_DI 1 "register_operand" "w") -+ (match_operand:SI 2 "immediate_operand" "i")] -+ "TARGET_SIMD" -+{ -+ emit_insn (gen_ashl3 (operands[0], operands[1], operands[2])); -+ DONE; -+}) -+ -+;; vshll_n -+ -+(define_insn "aarch64_shll_n" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (unspec: [(match_operand:VDW 1 "register_operand" "w") -+ (match_operand:SI 2 "immediate_operand" "i")] -+ VSHLL))] -+ "TARGET_SIMD" -+ "* -+ int bit_width = GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT; -+ aarch64_simd_const_bounds (operands[2], 0, bit_width + 1); -+ if (INTVAL (operands[2]) == bit_width) -+ { -+ return \"shll\\t%0., %1., %2\"; -+ } -+ else { -+ return \"shll\\t%0., %1., %2\"; -+ }" -+ [(set_attr "simd_type" "simd_shift_imm") -+ (set_attr "simd_mode" "")] -+) -+ -+;; vshll_high_n -+ -+(define_insn "aarch64_shll2_n" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (unspec: [(match_operand:VQW 1 "register_operand" "w") -+ (match_operand:SI 2 "immediate_operand" "i")] -+ VSHLL))] -+ "TARGET_SIMD" -+ "* -+ int bit_width = GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT; -+ aarch64_simd_const_bounds (operands[2], 0, bit_width + 1); -+ if (INTVAL (operands[2]) == bit_width) -+ { -+ return \"shll2\\t%0., %1., %2\"; -+ } -+ else { -+ return \"shll2\\t%0., %1., %2\"; -+ }" -+ [(set_attr "simd_type" "simd_shift_imm") -+ (set_attr "simd_mode" "")] -+) -+ -+;; vshr_n -+ -+(define_expand "aarch64_sshr_n" -+ [(match_operand:VSDQ_I_DI 0 "register_operand" "=w") -+ (match_operand:VSDQ_I_DI 1 "register_operand" "w") -+ (match_operand:SI 2 "immediate_operand" "i")] -+ "TARGET_SIMD" -+{ -+ emit_insn (gen_ashr3 (operands[0], operands[1], operands[2])); -+ DONE; -+}) -+ -+(define_expand "aarch64_ushr_n" -+ [(match_operand:VSDQ_I_DI 0 "register_operand" "=w") -+ (match_operand:VSDQ_I_DI 1 "register_operand" "w") -+ (match_operand:SI 2 "immediate_operand" "i")] -+ "TARGET_SIMD" -+{ -+ emit_insn (gen_lshr3 (operands[0], operands[1], operands[2])); -+ DONE; -+}) -+ -+;; vrshr_n -+ -+(define_insn "aarch64_shr_n" -+ [(set (match_operand:VSDQ_I_DI 0 "register_operand" "=w") -+ (unspec:VSDQ_I_DI [(match_operand:VSDQ_I_DI 1 "register_operand" "w") -+ (match_operand:SI 2 "immediate_operand" "i")] -+ VRSHR_N))] -+ "TARGET_SIMD" -+ "* -+ int bit_width = GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT; -+ aarch64_simd_const_bounds (operands[2], 1, bit_width + 1); -+ return \"shr\\t%0, %1, %2\";" -+ [(set_attr "simd_type" "simd_shift_imm") -+ (set_attr "simd_mode" "")] -+) -+ -+;; v(r)sra_n -+ -+(define_insn "aarch64_sra_n" -+ [(set (match_operand:VSDQ_I_DI 0 "register_operand" "=w") -+ (unspec:VSDQ_I_DI [(match_operand:VSDQ_I_DI 1 "register_operand" "0") -+ (match_operand:VSDQ_I_DI 2 "register_operand" "w") -+ (match_operand:SI 3 "immediate_operand" "i")] -+ VSRA))] -+ "TARGET_SIMD" -+ "* -+ int bit_width = GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT; -+ aarch64_simd_const_bounds (operands[3], 1, bit_width + 1); -+ return \"sra\\t%0, %2, %3\";" -+ [(set_attr "simd_type" "simd_shift_imm_acc") -+ (set_attr "simd_mode" "")] -+) -+ -+;; vsi_n -+ -+(define_insn "aarch64_si_n" -+ [(set (match_operand:VSDQ_I_DI 0 "register_operand" "=w") -+ (unspec:VSDQ_I_DI [(match_operand:VSDQ_I_DI 1 "register_operand" "0") -+ (match_operand:VSDQ_I_DI 2 "register_operand" "w") -+ (match_operand:SI 3 "immediate_operand" "i")] -+ VSLRI))] -+ "TARGET_SIMD" -+ "* -+ int bit_width = GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT; -+ aarch64_simd_const_bounds (operands[3], 1 - , -+ bit_width - + 1); -+ return \"si\\t%0, %2, %3\";" -+ [(set_attr "simd_type" "simd_shift_imm") -+ (set_attr "simd_mode" "")] -+) -+ -+;; vqshl(u) -+ -+(define_insn "aarch64_qshl_n" -+ [(set (match_operand:VSDQ_I 0 "register_operand" "=w") -+ (unspec:VSDQ_I [(match_operand:VSDQ_I 1 "register_operand" "w") -+ (match_operand:SI 2 "immediate_operand" "i")] -+ VQSHL_N))] -+ "TARGET_SIMD" -+ "* -+ int bit_width = GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT; -+ aarch64_simd_const_bounds (operands[2], 0, bit_width); -+ return \"qshl\\t%0, %1, %2\";" -+ [(set_attr "simd_type" "simd_sat_shift_imm") -+ (set_attr "simd_mode" "")] -+) -+ -+ -+;; vq(r)shr(u)n_n -+ -+(define_insn "aarch64_qshrn_n" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (unspec: [(match_operand:VSQN_HSDI 1 "register_operand" "w") -+ (match_operand:SI 2 "immediate_operand" "i")] -+ VQSHRN_N))] -+ "TARGET_SIMD" -+ "* -+ int bit_width = GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT; -+ aarch64_simd_const_bounds (operands[2], 1, bit_width + 1); -+ return \"qshrn\\t%0, %1, %2\";" -+ [(set_attr "simd_type" "simd_sat_shiftn_imm") -+ (set_attr "simd_mode" "")] -+) -+ -+ -+;; cm(eq|ge|le|lt|gt) -+ -+(define_insn "aarch64_cm" -+ [(set (match_operand: 0 "register_operand" "=w,w") -+ (unspec: -+ [(match_operand:VSDQ_I_DI 1 "register_operand" "w,w") -+ (match_operand:VSDQ_I_DI 2 "nonmemory_operand" "w,Z")] -+ VCMP_S))] -+ "TARGET_SIMD" -+ "@ -+ cm\t%0, %1, %2 -+ cm\t%0, %1, #0" -+ [(set_attr "simd_type" "simd_cmp") -+ (set_attr "simd_mode" "")] -+) -+ -+;; cm(hs|hi|tst) -+ -+(define_insn "aarch64_cm" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (unspec: -+ [(match_operand:VSDQ_I_DI 1 "register_operand" "w") -+ (match_operand:VSDQ_I_DI 2 "register_operand" "w")] -+ VCMP_U))] -+ "TARGET_SIMD" -+ "cm\t%0, %1, %2" -+ [(set_attr "simd_type" "simd_cmp") -+ (set_attr "simd_mode" "")] -+) -+ -+;; addp -+ -+(define_insn "aarch64_addp" -+ [(set (match_operand:VD_BHSI 0 "register_operand" "=w") -+ (unspec:VD_BHSI -+ [(match_operand:VD_BHSI 1 "register_operand" "w") -+ (match_operand:VD_BHSI 2 "register_operand" "w")] -+ UNSPEC_ADDP))] -+ "TARGET_SIMD" -+ "addp\t%0, %1, %2" -+ [(set_attr "simd_type" "simd_add") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "aarch64_addpdi" -+ [(set (match_operand:DI 0 "register_operand" "=w") -+ (unspec:DI -+ [(match_operand:V2DI 1 "register_operand" "w")] -+ UNSPEC_ADDP))] -+ "TARGET_SIMD" -+ "addp\t%d0, %1.2d" -+ [(set_attr "simd_type" "simd_add") -+ (set_attr "simd_mode" "DI")] -+) -+ -+;; v(max|min) -+ -+(define_expand "aarch64_" -+ [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w") -+ (MAXMIN:VDQ_BHSI (match_operand:VDQ_BHSI 1 "register_operand" "w") -+ (match_operand:VDQ_BHSI 2 "register_operand" "w")))] -+ "TARGET_SIMD" -+{ -+ emit_insn (gen_3 (operands[0], operands[1], operands[2])); -+ DONE; -+}) -+ -+ -+(define_insn "aarch64_" -+ [(set (match_operand:VDQF 0 "register_operand" "=w") -+ (unspec:VDQF [(match_operand:VDQF 1 "register_operand" "w") -+ (match_operand:VDQF 2 "register_operand" "w")] -+ FMAXMIN))] -+ "TARGET_SIMD" -+ "\t%0., %1., %2." -+ [(set_attr "simd_type" "simd_fminmax") -+ (set_attr "simd_mode" "")] -+) -+ -+;; sqrt -+ -+(define_insn "sqrt2" -+ [(set (match_operand:VDQF 0 "register_operand" "=w") -+ (sqrt:VDQF (match_operand:VDQF 1 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "fsqrt\\t%0., %1." -+ [(set_attr "simd_type" "simd_fsqrt") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_expand "aarch64_sqrt" -+ [(match_operand:VDQF 0 "register_operand" "=w") -+ (match_operand:VDQF 1 "register_operand" "w")] -+ "TARGET_SIMD" -+{ -+ emit_insn (gen_sqrt2 (operands[0], operands[1])); -+ DONE; -+}) -Index: gcc/config/aarch64/predicates.md -=================================================================== ---- a/src/gcc/config/aarch64/predicates.md (.../gcc-4_7-branch) -+++ b/src/gcc/config/aarch64/predicates.md (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,267 @@ -+;; Machine description for AArch64 architecture. -+;; Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. -+;; Contributed by ARM Ltd. -+;; -+;; This file is part of GCC. -+;; -+;; GCC is free software; you can redistribute it and/or modify it -+;; under the terms of the GNU General Public License as published by -+;; the Free Software Foundation; either version 3, or (at your option) -+;; any later version. -+;; -+;; GCC is distributed in the hope that it will be useful, but -+;; WITHOUT ANY WARRANTY; without even the implied warranty of -+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+;; General Public License for more details. -+;; -+;; You should have received a copy of the GNU General Public License -+;; along with GCC; see the file COPYING3. If not see -+;; . -+ -+(define_special_predicate "cc_register" -+ (and (match_code "reg") -+ (and (match_test "REGNO (op) == CC_REGNUM") -+ (ior (match_test "mode == GET_MODE (op)") -+ (match_test "mode == VOIDmode -+ && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC")))) -+) -+ -+(define_predicate "aarch64_reg_or_zero" -+ (and (match_code "reg,subreg,const_int") -+ (ior (match_operand 0 "register_operand") -+ (match_test "op == const0_rtx")))) -+ -+(define_predicate "aarch64_reg_zero_or_m1" -+ (and (match_code "reg,subreg,const_int") -+ (ior (match_operand 0 "register_operand") -+ (ior (match_test "op == const0_rtx") -+ (match_test "op == constm1_rtx"))))) -+ -+(define_predicate "aarch64_fp_compare_operand" -+ (ior (match_operand 0 "register_operand") -+ (and (match_code "const_double") -+ (match_test "aarch64_const_double_zero_rtx_p (op)")))) -+ -+(define_predicate "aarch64_plus_immediate" -+ (and (match_code "const_int") -+ (ior (match_test "aarch64_uimm12_shift (INTVAL (op))") -+ (match_test "aarch64_uimm12_shift (-INTVAL (op))")))) -+ -+(define_predicate "aarch64_plus_operand" -+ (ior (match_operand 0 "register_operand") -+ (match_operand 0 "aarch64_plus_immediate"))) -+ -+(define_predicate "aarch64_pluslong_immediate" -+ (and (match_code "const_int") -+ (match_test "(INTVAL (op) < 0xffffff && INTVAL (op) > -0xffffff)"))) -+ -+(define_predicate "aarch64_pluslong_operand" -+ (ior (match_operand 0 "register_operand") -+ (match_operand 0 "aarch64_pluslong_immediate"))) -+ -+(define_predicate "aarch64_logical_immediate" -+ (and (match_code "const_int") -+ (match_test "aarch64_bitmask_imm (INTVAL (op), mode)"))) -+ -+(define_predicate "aarch64_logical_operand" -+ (ior (match_operand 0 "register_operand") -+ (match_operand 0 "aarch64_logical_immediate"))) -+ -+(define_predicate "aarch64_shift_imm_si" -+ (and (match_code "const_int") -+ (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 32"))) -+ -+(define_predicate "aarch64_shift_imm_di" -+ (and (match_code "const_int") -+ (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 64"))) -+ -+(define_predicate "aarch64_reg_or_shift_imm_si" -+ (ior (match_operand 0 "register_operand") -+ (match_operand 0 "aarch64_shift_imm_si"))) -+ -+(define_predicate "aarch64_reg_or_shift_imm_di" -+ (ior (match_operand 0 "register_operand") -+ (match_operand 0 "aarch64_shift_imm_di"))) -+ -+;; The imm3 field is a 3-bit field that only accepts immediates in the -+;; range 0..4. -+(define_predicate "aarch64_imm3" -+ (and (match_code "const_int") -+ (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 4"))) -+ -+(define_predicate "aarch64_pwr_imm3" -+ (and (match_code "const_int") -+ (match_test "INTVAL (op) != 0 -+ && (unsigned) exact_log2 (INTVAL (op)) <= 4"))) -+ -+(define_predicate "aarch64_pwr_2_si" -+ (and (match_code "const_int") -+ (match_test "INTVAL (op) != 0 -+ && (unsigned) exact_log2 (INTVAL (op)) < 32"))) -+ -+(define_predicate "aarch64_pwr_2_di" -+ (and (match_code "const_int") -+ (match_test "INTVAL (op) != 0 -+ && (unsigned) exact_log2 (INTVAL (op)) < 64"))) -+ -+(define_predicate "aarch64_mem_pair_operand" -+ (and (match_code "mem") -+ (match_test "aarch64_legitimate_address_p (mode, XEXP (op, 0), PARALLEL, -+ 0)"))) -+ -+(define_predicate "aarch64_const_address" -+ (and (match_code "symbol_ref") -+ (match_test "mode == DImode && CONSTANT_ADDRESS_P (op)"))) -+ -+(define_predicate "aarch64_valid_symref" -+ (match_code "const, symbol_ref, label_ref") -+{ -+ enum aarch64_symbol_type symbol_type; -+ return (aarch64_symbolic_constant_p (op, SYMBOL_CONTEXT_ADR, &symbol_type) -+ && symbol_type != SYMBOL_FORCE_TO_MEM); -+}) -+ -+(define_predicate "aarch64_tls_ie_symref" -+ (match_code "symbol_ref, label_ref") -+{ -+ switch (GET_CODE (op)) -+ { -+ case CONST: -+ op = XEXP (op, 0); -+ if (GET_CODE (op) != PLUS -+ || GET_CODE (XEXP (op, 0)) != SYMBOL_REF -+ || GET_CODE (XEXP (op, 1)) != CONST_INT) -+ return false; -+ op = XEXP (op, 0); -+ -+ case SYMBOL_REF: -+ return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_INITIAL_EXEC; -+ -+ default: -+ gcc_unreachable (); -+ } -+}) -+ -+(define_predicate "aarch64_tls_le_symref" -+ (match_code "symbol_ref, label_ref") -+{ -+ switch (GET_CODE (op)) -+ { -+ case CONST: -+ op = XEXP (op, 0); -+ if (GET_CODE (op) != PLUS -+ || GET_CODE (XEXP (op, 0)) != SYMBOL_REF -+ || GET_CODE (XEXP (op, 1)) != CONST_INT) -+ return false; -+ op = XEXP (op, 0); -+ -+ case SYMBOL_REF: -+ return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_EXEC; -+ -+ default: -+ gcc_unreachable (); -+ } -+}) -+ -+(define_predicate "aarch64_mov_operand" -+ (and (match_code "reg,subreg,mem,const_int,symbol_ref,high") -+ (ior (match_operand 0 "register_operand") -+ (ior (match_operand 0 "memory_operand") -+ (ior (match_test "GET_CODE (op) == HIGH -+ && aarch64_valid_symref (XEXP (op, 0), -+ GET_MODE (XEXP (op, 0)))") -+ (ior (match_test "CONST_INT_P (op) -+ && aarch64_move_imm (INTVAL (op), mode)") -+ (match_test "aarch64_const_address (op, mode)"))))))) -+ -+(define_predicate "aarch64_movti_operand" -+ (and (match_code "reg,subreg,mem,const_int") -+ (ior (match_operand 0 "register_operand") -+ (ior (match_operand 0 "memory_operand") -+ (match_operand 0 "const_int_operand"))))) -+ -+(define_predicate "aarch64_reg_or_imm" -+ (and (match_code "reg,subreg,const_int") -+ (ior (match_operand 0 "register_operand") -+ (match_operand 0 "const_int_operand")))) -+ -+;; True for integer comparisons and for FP comparisons other than LTGT or UNEQ. -+(define_special_predicate "aarch64_comparison_operator" -+ (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,ordered,unlt,unle,unge,ungt")) -+ -+;; True if the operand is memory reference suitable for a load/store exclusive. -+(define_predicate "aarch64_sync_memory_operand" -+ (and (match_operand 0 "memory_operand") -+ (match_code "reg" "0"))) -+ -+;; Predicates for parallel expanders based on mode. -+(define_special_predicate "vect_par_cnst_hi_half" -+ (match_code "parallel") -+{ -+ HOST_WIDE_INT count = XVECLEN (op, 0); -+ int nunits = GET_MODE_NUNITS (mode); -+ int i; -+ -+ if (count < 1 -+ || count != nunits / 2) -+ return false; -+ -+ if (!VECTOR_MODE_P (mode)) -+ return false; -+ -+ for (i = 0; i < count; i++) -+ { -+ rtx elt = XVECEXP (op, 0, i); -+ int val; -+ -+ if (GET_CODE (elt) != CONST_INT) -+ return false; -+ -+ val = INTVAL (elt); -+ if (val != (nunits / 2) + i) -+ return false; -+ } -+ return true; -+}) -+ -+(define_special_predicate "vect_par_cnst_lo_half" -+ (match_code "parallel") -+{ -+ HOST_WIDE_INT count = XVECLEN (op, 0); -+ int nunits = GET_MODE_NUNITS (mode); -+ int i; -+ -+ if (count < 1 -+ || count != nunits / 2) -+ return false; -+ -+ if (!VECTOR_MODE_P (mode)) -+ return false; -+ -+ for (i = 0; i < count; i++) -+ { -+ rtx elt = XVECEXP (op, 0, i); -+ int val; -+ -+ if (GET_CODE (elt) != CONST_INT) -+ return false; -+ -+ val = INTVAL (elt); -+ if (val != i) -+ return false; -+ } -+ return true; -+}) -+ -+ -+(define_special_predicate "aarch64_simd_lshift_imm" -+ (match_code "const_vector") -+{ -+ return aarch64_simd_shift_imm_p (op, mode, true); -+}) -+ -+(define_special_predicate "aarch64_simd_rshift_imm" -+ (match_code "const_vector") -+{ -+ return aarch64_simd_shift_imm_p (op, mode, false); -+}) -Index: gcc/config/aarch64/aarch64-elf.h -=================================================================== ---- a/src/gcc/config/aarch64/aarch64-elf.h (.../gcc-4_7-branch) -+++ b/src/gcc/config/aarch64/aarch64-elf.h (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,123 @@ -+/* Machine description for AArch64 architecture. -+ Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. -+ Contributed by ARM Ltd. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3, or (at your option) -+ any later version. -+ -+ GCC is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+#ifndef GCC_AARCH64_ELF_H -+#define GCC_AARCH64_ELF_H -+ -+ -+#define ASM_OUTPUT_LABELREF(FILE, NAME) \ -+ aarch64_asm_output_labelref (FILE, NAME) -+ -+#define TEXT_SECTION_ASM_OP "\t.text" -+#define DATA_SECTION_ASM_OP "\t.data" -+#define BSS_SECTION_ASM_OP "\t.bss" -+ -+#define CTORS_SECTION_ASM_OP "\t.section\t.init_array,\"aw\",%init_array" -+#define DTORS_SECTION_ASM_OP "\t.section\t.fini_array,\"aw\",%fini_array" -+ -+#undef INIT_SECTION_ASM_OP -+#undef FINI_SECTION_ASM_OP -+#define INIT_ARRAY_SECTION_ASM_OP CTORS_SECTION_ASM_OP -+#define FINI_ARRAY_SECTION_ASM_OP DTORS_SECTION_ASM_OP -+ -+/* Since we use .init_array/.fini_array we don't need the markers at -+ the start and end of the ctors/dtors arrays. */ -+#define CTOR_LIST_BEGIN asm (CTORS_SECTION_ASM_OP) -+#define CTOR_LIST_END /* empty */ -+#define DTOR_LIST_BEGIN asm (DTORS_SECTION_ASM_OP) -+#define DTOR_LIST_END /* empty */ -+ -+#undef TARGET_ASM_CONSTRUCTOR -+#define TARGET_ASM_CONSTRUCTOR aarch64_elf_asm_constructor -+ -+#undef TARGET_ASM_DESTRUCTOR -+#define TARGET_ASM_DESTRUCTOR aarch64_elf_asm_destructor -+ -+#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN -+/* Support for -falign-* switches. Use .p2align to ensure that code -+ sections are padded with NOP instructions, rather than zeros. */ -+#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ -+ do \ -+ { \ -+ if ((LOG) != 0) \ -+ { \ -+ if ((MAX_SKIP) == 0) \ -+ fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ -+ else \ -+ fprintf ((FILE), "\t.p2align %d,,%d\n", \ -+ (int) (LOG), (int) (MAX_SKIP)); \ -+ } \ -+ } while (0) -+ -+#endif /* HAVE_GAS_MAX_SKIP_P2ALIGN */ -+ -+#define JUMP_TABLES_IN_TEXT_SECTION 0 -+ -+#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ -+ do { \ -+ switch (GET_MODE (BODY)) \ -+ { \ -+ case QImode: \ -+ asm_fprintf (STREAM, "\t.byte\t(%LL%d - %LLrtx%d) / 4\n", \ -+ VALUE, REL); \ -+ break; \ -+ case HImode: \ -+ asm_fprintf (STREAM, "\t.2byte\t(%LL%d - %LLrtx%d) / 4\n", \ -+ VALUE, REL); \ -+ break; \ -+ case SImode: \ -+ case DImode: /* See comment in aarch64_output_casesi. */ \ -+ asm_fprintf (STREAM, "\t.word\t(%LL%d - %LLrtx%d) / 4\n", \ -+ VALUE, REL); \ -+ break; \ -+ default: \ -+ gcc_unreachable (); \ -+ } \ -+ } while (0) -+ -+#define ASM_OUTPUT_ALIGN(STREAM, POWER) \ -+ fprintf(STREAM, "\t.align\t%d\n", (int)POWER) -+ -+#define ASM_COMMENT_START "//" -+ -+#define REGISTER_PREFIX "" -+#define LOCAL_LABEL_PREFIX "." -+#define USER_LABEL_PREFIX "" -+ -+#define GLOBAL_ASM_OP "\t.global\t" -+ -+#ifndef ASM_SPEC -+#define ASM_SPEC "\ -+%{mbig-endian:-EB} \ -+%{mlittle-endian:-EL} \ -+%{mcpu=*:-mcpu=%*} \ -+%{march=*:-march=%*}" -+#endif -+ -+#undef TYPE_OPERAND_FMT -+#define TYPE_OPERAND_FMT "%%%s" -+ -+#undef TARGET_ASM_NAMED_SECTION -+#define TARGET_ASM_NAMED_SECTION aarch64_elf_asm_named_section -+ -+/* Stabs debug not required. */ -+#undef DBX_DEBUGGING_INFO -+ -+#endif /* GCC_AARCH64_ELF_H */ - -Property changes on: gcc/config/aarch64/aarch64-elf.h -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/config/aarch64/arm_neon.h -=================================================================== ---- a/src/gcc/config/aarch64/arm_neon.h (.../gcc-4_7-branch) -+++ b/src/gcc/config/aarch64/arm_neon.h (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,24156 @@ -+/* ARM NEON intrinsics include file. -+ -+ Copyright (C) 2011, 2012 Free Software Foundation, Inc. -+ Contributed by ARM Ltd. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ Under Section 7 of GPL version 3, you are granted additional -+ permissions described in the GCC Runtime Library Exception, version -+ 3.1, as published by the Free Software Foundation. -+ -+ You should have received a copy of the GNU General Public License and -+ a copy of the GCC Runtime Library Exception along with this program; -+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -+ . */ -+ -+#ifndef _AARCH64_NEON_H_ -+#define _AARCH64_NEON_H_ -+ -+#include -+ -+typedef __builtin_aarch64_simd_qi int8x8_t -+ __attribute__ ((__vector_size__ (8))); -+typedef __builtin_aarch64_simd_hi int16x4_t -+ __attribute__ ((__vector_size__ (8))); -+typedef __builtin_aarch64_simd_si int32x2_t -+ __attribute__ ((__vector_size__ (8))); -+typedef __builtin_aarch64_simd_di int64x1_t; -+typedef __builtin_aarch64_simd_si int32x1_t; -+typedef __builtin_aarch64_simd_hi int16x1_t; -+typedef __builtin_aarch64_simd_qi int8x1_t; -+typedef __builtin_aarch64_simd_df float64x1_t; -+typedef __builtin_aarch64_simd_sf float32x2_t -+ __attribute__ ((__vector_size__ (8))); -+typedef __builtin_aarch64_simd_poly8 poly8x8_t -+ __attribute__ ((__vector_size__ (8))); -+typedef __builtin_aarch64_simd_poly16 poly16x4_t -+ __attribute__ ((__vector_size__ (8))); -+typedef __builtin_aarch64_simd_uqi uint8x8_t -+ __attribute__ ((__vector_size__ (8))); -+typedef __builtin_aarch64_simd_uhi uint16x4_t -+ __attribute__ ((__vector_size__ (8))); -+typedef __builtin_aarch64_simd_usi uint32x2_t -+ __attribute__ ((__vector_size__ (8))); -+typedef __builtin_aarch64_simd_udi uint64x1_t; -+typedef __builtin_aarch64_simd_usi uint32x1_t; -+typedef __builtin_aarch64_simd_uhi uint16x1_t; -+typedef __builtin_aarch64_simd_uqi uint8x1_t; -+typedef __builtin_aarch64_simd_qi int8x16_t -+ __attribute__ ((__vector_size__ (16))); -+typedef __builtin_aarch64_simd_hi int16x8_t -+ __attribute__ ((__vector_size__ (16))); -+typedef __builtin_aarch64_simd_si int32x4_t -+ __attribute__ ((__vector_size__ (16))); -+typedef __builtin_aarch64_simd_di int64x2_t -+ __attribute__ ((__vector_size__ (16))); -+typedef __builtin_aarch64_simd_sf float32x4_t -+ __attribute__ ((__vector_size__ (16))); -+typedef __builtin_aarch64_simd_df float64x2_t -+ __attribute__ ((__vector_size__ (16))); -+typedef __builtin_aarch64_simd_poly8 poly8x16_t -+ __attribute__ ((__vector_size__ (16))); -+typedef __builtin_aarch64_simd_poly16 poly16x8_t -+ __attribute__ ((__vector_size__ (16))); -+typedef __builtin_aarch64_simd_uqi uint8x16_t -+ __attribute__ ((__vector_size__ (16))); -+typedef __builtin_aarch64_simd_uhi uint16x8_t -+ __attribute__ ((__vector_size__ (16))); -+typedef __builtin_aarch64_simd_usi uint32x4_t -+ __attribute__ ((__vector_size__ (16))); -+typedef __builtin_aarch64_simd_udi uint64x2_t -+ __attribute__ ((__vector_size__ (16))); -+ -+typedef float float32_t; -+typedef double float64_t; -+typedef __builtin_aarch64_simd_poly8 poly8_t; -+typedef __builtin_aarch64_simd_poly16 poly16_t; -+ -+typedef struct int8x8x2_t -+{ -+ int8x8_t val[2]; -+} int8x8x2_t; -+ -+typedef struct int8x16x2_t -+{ -+ int8x16_t val[2]; -+} int8x16x2_t; -+ -+typedef struct int16x4x2_t -+{ -+ int16x4_t val[2]; -+} int16x4x2_t; -+ -+typedef struct int16x8x2_t -+{ -+ int16x8_t val[2]; -+} int16x8x2_t; -+ -+typedef struct int32x2x2_t -+{ -+ int32x2_t val[2]; -+} int32x2x2_t; -+ -+typedef struct int32x4x2_t -+{ -+ int32x4_t val[2]; -+} int32x4x2_t; -+ -+typedef struct int64x1x2_t -+{ -+ int64x1_t val[2]; -+} int64x1x2_t; -+ -+typedef struct int64x2x2_t -+{ -+ int64x2_t val[2]; -+} int64x2x2_t; -+ -+typedef struct uint8x8x2_t -+{ -+ uint8x8_t val[2]; -+} uint8x8x2_t; -+ -+typedef struct uint8x16x2_t -+{ -+ uint8x16_t val[2]; -+} uint8x16x2_t; -+ -+typedef struct uint16x4x2_t -+{ -+ uint16x4_t val[2]; -+} uint16x4x2_t; -+ -+typedef struct uint16x8x2_t -+{ -+ uint16x8_t val[2]; -+} uint16x8x2_t; -+ -+typedef struct uint32x2x2_t -+{ -+ uint32x2_t val[2]; -+} uint32x2x2_t; -+ -+typedef struct uint32x4x2_t -+{ -+ uint32x4_t val[2]; -+} uint32x4x2_t; -+ -+typedef struct uint64x1x2_t -+{ -+ uint64x1_t val[2]; -+} uint64x1x2_t; -+ -+typedef struct uint64x2x2_t -+{ -+ uint64x2_t val[2]; -+} uint64x2x2_t; -+ -+typedef struct float32x2x2_t -+{ -+ float32x2_t val[2]; -+} float32x2x2_t; -+ -+typedef struct float32x4x2_t -+{ -+ float32x4_t val[2]; -+} float32x4x2_t; -+ -+typedef struct float64x2x2_t -+{ -+ float64x2_t val[2]; -+} float64x2x2_t; -+ -+typedef struct float64x1x2_t -+{ -+ float64x1_t val[2]; -+} float64x1x2_t; -+ -+typedef struct poly8x8x2_t -+{ -+ poly8x8_t val[2]; -+} poly8x8x2_t; -+ -+typedef struct poly8x16x2_t -+{ -+ poly8x16_t val[2]; -+} poly8x16x2_t; -+ -+typedef struct poly16x4x2_t -+{ -+ poly16x4_t val[2]; -+} poly16x4x2_t; -+ -+typedef struct poly16x8x2_t -+{ -+ poly16x8_t val[2]; -+} poly16x8x2_t; -+ -+typedef struct int8x8x3_t -+{ -+ int8x8_t val[3]; -+} int8x8x3_t; -+ -+typedef struct int8x16x3_t -+{ -+ int8x16_t val[3]; -+} int8x16x3_t; -+ -+typedef struct int16x4x3_t -+{ -+ int16x4_t val[3]; -+} int16x4x3_t; -+ -+typedef struct int16x8x3_t -+{ -+ int16x8_t val[3]; -+} int16x8x3_t; -+ -+typedef struct int32x2x3_t -+{ -+ int32x2_t val[3]; -+} int32x2x3_t; -+ -+typedef struct int32x4x3_t -+{ -+ int32x4_t val[3]; -+} int32x4x3_t; -+ -+typedef struct int64x1x3_t -+{ -+ int64x1_t val[3]; -+} int64x1x3_t; -+ -+typedef struct int64x2x3_t -+{ -+ int64x2_t val[3]; -+} int64x2x3_t; -+ -+typedef struct uint8x8x3_t -+{ -+ uint8x8_t val[3]; -+} uint8x8x3_t; -+ -+typedef struct uint8x16x3_t -+{ -+ uint8x16_t val[3]; -+} uint8x16x3_t; -+ -+typedef struct uint16x4x3_t -+{ -+ uint16x4_t val[3]; -+} uint16x4x3_t; -+ -+typedef struct uint16x8x3_t -+{ -+ uint16x8_t val[3]; -+} uint16x8x3_t; -+ -+typedef struct uint32x2x3_t -+{ -+ uint32x2_t val[3]; -+} uint32x2x3_t; -+ -+typedef struct uint32x4x3_t -+{ -+ uint32x4_t val[3]; -+} uint32x4x3_t; -+ -+typedef struct uint64x1x3_t -+{ -+ uint64x1_t val[3]; -+} uint64x1x3_t; -+ -+typedef struct uint64x2x3_t -+{ -+ uint64x2_t val[3]; -+} uint64x2x3_t; -+ -+typedef struct float32x2x3_t -+{ -+ float32x2_t val[3]; -+} float32x2x3_t; -+ -+typedef struct float32x4x3_t -+{ -+ float32x4_t val[3]; -+} float32x4x3_t; -+ -+typedef struct float64x2x3_t -+{ -+ float64x2_t val[3]; -+} float64x2x3_t; -+ -+typedef struct float64x1x3_t -+{ -+ float64x1_t val[3]; -+} float64x1x3_t; -+ -+typedef struct poly8x8x3_t -+{ -+ poly8x8_t val[3]; -+} poly8x8x3_t; -+ -+typedef struct poly8x16x3_t -+{ -+ poly8x16_t val[3]; -+} poly8x16x3_t; -+ -+typedef struct poly16x4x3_t -+{ -+ poly16x4_t val[3]; -+} poly16x4x3_t; -+ -+typedef struct poly16x8x3_t -+{ -+ poly16x8_t val[3]; -+} poly16x8x3_t; -+ -+typedef struct int8x8x4_t -+{ -+ int8x8_t val[4]; -+} int8x8x4_t; -+ -+typedef struct int8x16x4_t -+{ -+ int8x16_t val[4]; -+} int8x16x4_t; -+ -+typedef struct int16x4x4_t -+{ -+ int16x4_t val[4]; -+} int16x4x4_t; -+ -+typedef struct int16x8x4_t -+{ -+ int16x8_t val[4]; -+} int16x8x4_t; -+ -+typedef struct int32x2x4_t -+{ -+ int32x2_t val[4]; -+} int32x2x4_t; -+ -+typedef struct int32x4x4_t -+{ -+ int32x4_t val[4]; -+} int32x4x4_t; -+ -+typedef struct int64x1x4_t -+{ -+ int64x1_t val[4]; -+} int64x1x4_t; -+ -+typedef struct int64x2x4_t -+{ -+ int64x2_t val[4]; -+} int64x2x4_t; -+ -+typedef struct uint8x8x4_t -+{ -+ uint8x8_t val[4]; -+} uint8x8x4_t; -+ -+typedef struct uint8x16x4_t -+{ -+ uint8x16_t val[4]; -+} uint8x16x4_t; -+ -+typedef struct uint16x4x4_t -+{ -+ uint16x4_t val[4]; -+} uint16x4x4_t; -+ -+typedef struct uint16x8x4_t -+{ -+ uint16x8_t val[4]; -+} uint16x8x4_t; -+ -+typedef struct uint32x2x4_t -+{ -+ uint32x2_t val[4]; -+} uint32x2x4_t; -+ -+typedef struct uint32x4x4_t -+{ -+ uint32x4_t val[4]; -+} uint32x4x4_t; -+ -+typedef struct uint64x1x4_t -+{ -+ uint64x1_t val[4]; -+} uint64x1x4_t; -+ -+typedef struct uint64x2x4_t -+{ -+ uint64x2_t val[4]; -+} uint64x2x4_t; -+ -+typedef struct float32x2x4_t -+{ -+ float32x2_t val[4]; -+} float32x2x4_t; -+ -+typedef struct float32x4x4_t -+{ -+ float32x4_t val[4]; -+} float32x4x4_t; -+ -+typedef struct float64x2x4_t -+{ -+ float64x2_t val[4]; -+} float64x2x4_t; -+ -+typedef struct float64x1x4_t -+{ -+ float64x1_t val[4]; -+} float64x1x4_t; -+ -+typedef struct poly8x8x4_t -+{ -+ poly8x8_t val[4]; -+} poly8x8x4_t; -+ -+typedef struct poly8x16x4_t -+{ -+ poly8x16_t val[4]; -+} poly8x16x4_t; -+ -+typedef struct poly16x4x4_t -+{ -+ poly16x4_t val[4]; -+} poly16x4x4_t; -+ -+typedef struct poly16x8x4_t -+{ -+ poly16x8_t val[4]; -+} poly16x8x4_t; -+ -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vadd_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return __a + __b; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vadd_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return __a + __b; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vadd_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return __a + __b; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vadd_f32 (float32x2_t __a, float32x2_t __b) -+{ -+ return __a + __b; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vadd_u8 (uint8x8_t __a, uint8x8_t __b) -+{ -+ return __a + __b; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vadd_u16 (uint16x4_t __a, uint16x4_t __b) -+{ -+ return __a + __b; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vadd_u32 (uint32x2_t __a, uint32x2_t __b) -+{ -+ return __a + __b; -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vadd_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return __a + __b; -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vadd_u64 (uint64x1_t __a, uint64x1_t __b) -+{ -+ return __a + __b; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vaddq_s8 (int8x16_t __a, int8x16_t __b) -+{ -+ return __a + __b; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vaddq_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return __a + __b; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vaddq_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return __a + __b; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vaddq_s64 (int64x2_t __a, int64x2_t __b) -+{ -+ return __a + __b; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vaddq_f32 (float32x4_t __a, float32x4_t __b) -+{ -+ return __a + __b; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vaddq_f64 (float64x2_t __a, float64x2_t __b) -+{ -+ return __a + __b; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vaddq_u8 (uint8x16_t __a, uint8x16_t __b) -+{ -+ return __a + __b; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vaddq_u16 (uint16x8_t __a, uint16x8_t __b) -+{ -+ return __a + __b; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vaddq_u32 (uint32x4_t __a, uint32x4_t __b) -+{ -+ return __a + __b; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vaddq_u64 (uint64x2_t __a, uint64x2_t __b) -+{ -+ return __a + __b; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vaddl_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return (int16x8_t) __builtin_aarch64_saddlv8qi (__a, __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vaddl_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return (int32x4_t) __builtin_aarch64_saddlv4hi (__a, __b); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vaddl_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return (int64x2_t) __builtin_aarch64_saddlv2si (__a, __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vaddl_u8 (uint8x8_t __a, uint8x8_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_uaddlv8qi ((int8x8_t) __a, -+ (int8x8_t) __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vaddl_u16 (uint16x4_t __a, uint16x4_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_uaddlv4hi ((int16x4_t) __a, -+ (int16x4_t) __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vaddl_u32 (uint32x2_t __a, uint32x2_t __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_uaddlv2si ((int32x2_t) __a, -+ (int32x2_t) __b); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vaddl_high_s8 (int8x16_t __a, int8x16_t __b) -+{ -+ return (int16x8_t) __builtin_aarch64_saddl2v16qi (__a, __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vaddl_high_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return (int32x4_t) __builtin_aarch64_saddl2v8hi (__a, __b); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vaddl_high_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return (int64x2_t) __builtin_aarch64_saddl2v4si (__a, __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vaddl_high_u8 (uint8x16_t __a, uint8x16_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_uaddl2v16qi ((int8x16_t) __a, -+ (int8x16_t) __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vaddl_high_u16 (uint16x8_t __a, uint16x8_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_uaddl2v8hi ((int16x8_t) __a, -+ (int16x8_t) __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vaddl_high_u32 (uint32x4_t __a, uint32x4_t __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_uaddl2v4si ((int32x4_t) __a, -+ (int32x4_t) __b); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vaddw_s8 (int16x8_t __a, int8x8_t __b) -+{ -+ return (int16x8_t) __builtin_aarch64_saddwv8qi (__a, __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vaddw_s16 (int32x4_t __a, int16x4_t __b) -+{ -+ return (int32x4_t) __builtin_aarch64_saddwv4hi (__a, __b); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vaddw_s32 (int64x2_t __a, int32x2_t __b) -+{ -+ return (int64x2_t) __builtin_aarch64_saddwv2si (__a, __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vaddw_u8 (uint16x8_t __a, uint8x8_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_uaddwv8qi ((int16x8_t) __a, -+ (int8x8_t) __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vaddw_u16 (uint32x4_t __a, uint16x4_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_uaddwv4hi ((int32x4_t) __a, -+ (int16x4_t) __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vaddw_u32 (uint64x2_t __a, uint32x2_t __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_uaddwv2si ((int64x2_t) __a, -+ (int32x2_t) __b); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vaddw_high_s8 (int16x8_t __a, int8x16_t __b) -+{ -+ return (int16x8_t) __builtin_aarch64_saddw2v16qi (__a, __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vaddw_high_s16 (int32x4_t __a, int16x8_t __b) -+{ -+ return (int32x4_t) __builtin_aarch64_saddw2v8hi (__a, __b); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vaddw_high_s32 (int64x2_t __a, int32x4_t __b) -+{ -+ return (int64x2_t) __builtin_aarch64_saddw2v4si (__a, __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vaddw_high_u8 (uint16x8_t __a, uint8x16_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_uaddw2v16qi ((int16x8_t) __a, -+ (int8x16_t) __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vaddw_high_u16 (uint32x4_t __a, uint16x8_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_uaddw2v8hi ((int32x4_t) __a, -+ (int16x8_t) __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vaddw_high_u32 (uint64x2_t __a, uint32x4_t __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_uaddw2v4si ((int64x2_t) __a, -+ (int32x4_t) __b); -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vhadd_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return (int8x8_t) __builtin_aarch64_shaddv8qi (__a, __b); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vhadd_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return (int16x4_t) __builtin_aarch64_shaddv4hi (__a, __b); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vhadd_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return (int32x2_t) __builtin_aarch64_shaddv2si (__a, __b); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vhadd_u8 (uint8x8_t __a, uint8x8_t __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_uhaddv8qi ((int8x8_t) __a, -+ (int8x8_t) __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vhadd_u16 (uint16x4_t __a, uint16x4_t __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_uhaddv4hi ((int16x4_t) __a, -+ (int16x4_t) __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vhadd_u32 (uint32x2_t __a, uint32x2_t __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_uhaddv2si ((int32x2_t) __a, -+ (int32x2_t) __b); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vhaddq_s8 (int8x16_t __a, int8x16_t __b) -+{ -+ return (int8x16_t) __builtin_aarch64_shaddv16qi (__a, __b); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vhaddq_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return (int16x8_t) __builtin_aarch64_shaddv8hi (__a, __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vhaddq_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return (int32x4_t) __builtin_aarch64_shaddv4si (__a, __b); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vhaddq_u8 (uint8x16_t __a, uint8x16_t __b) -+{ -+ return (uint8x16_t) __builtin_aarch64_uhaddv16qi ((int8x16_t) __a, -+ (int8x16_t) __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vhaddq_u16 (uint16x8_t __a, uint16x8_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_uhaddv8hi ((int16x8_t) __a, -+ (int16x8_t) __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vhaddq_u32 (uint32x4_t __a, uint32x4_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_uhaddv4si ((int32x4_t) __a, -+ (int32x4_t) __b); -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vrhadd_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return (int8x8_t) __builtin_aarch64_srhaddv8qi (__a, __b); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vrhadd_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return (int16x4_t) __builtin_aarch64_srhaddv4hi (__a, __b); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vrhadd_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return (int32x2_t) __builtin_aarch64_srhaddv2si (__a, __b); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vrhadd_u8 (uint8x8_t __a, uint8x8_t __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_urhaddv8qi ((int8x8_t) __a, -+ (int8x8_t) __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vrhadd_u16 (uint16x4_t __a, uint16x4_t __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_urhaddv4hi ((int16x4_t) __a, -+ (int16x4_t) __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vrhadd_u32 (uint32x2_t __a, uint32x2_t __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_urhaddv2si ((int32x2_t) __a, -+ (int32x2_t) __b); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vrhaddq_s8 (int8x16_t __a, int8x16_t __b) -+{ -+ return (int8x16_t) __builtin_aarch64_srhaddv16qi (__a, __b); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vrhaddq_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return (int16x8_t) __builtin_aarch64_srhaddv8hi (__a, __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vrhaddq_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return (int32x4_t) __builtin_aarch64_srhaddv4si (__a, __b); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vrhaddq_u8 (uint8x16_t __a, uint8x16_t __b) -+{ -+ return (uint8x16_t) __builtin_aarch64_urhaddv16qi ((int8x16_t) __a, -+ (int8x16_t) __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vrhaddq_u16 (uint16x8_t __a, uint16x8_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_urhaddv8hi ((int16x8_t) __a, -+ (int16x8_t) __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vrhaddq_u32 (uint32x4_t __a, uint32x4_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_urhaddv4si ((int32x4_t) __a, -+ (int32x4_t) __b); -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vaddhn_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return (int8x8_t) __builtin_aarch64_addhnv8hi (__a, __b); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vaddhn_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return (int16x4_t) __builtin_aarch64_addhnv4si (__a, __b); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vaddhn_s64 (int64x2_t __a, int64x2_t __b) -+{ -+ return (int32x2_t) __builtin_aarch64_addhnv2di (__a, __b); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vaddhn_u16 (uint16x8_t __a, uint16x8_t __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_addhnv8hi ((int16x8_t) __a, -+ (int16x8_t) __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vaddhn_u32 (uint32x4_t __a, uint32x4_t __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_addhnv4si ((int32x4_t) __a, -+ (int32x4_t) __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vaddhn_u64 (uint64x2_t __a, uint64x2_t __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_addhnv2di ((int64x2_t) __a, -+ (int64x2_t) __b); -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vraddhn_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return (int8x8_t) __builtin_aarch64_raddhnv8hi (__a, __b); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vraddhn_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return (int16x4_t) __builtin_aarch64_raddhnv4si (__a, __b); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vraddhn_s64 (int64x2_t __a, int64x2_t __b) -+{ -+ return (int32x2_t) __builtin_aarch64_raddhnv2di (__a, __b); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vraddhn_u16 (uint16x8_t __a, uint16x8_t __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_raddhnv8hi ((int16x8_t) __a, -+ (int16x8_t) __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vraddhn_u32 (uint32x4_t __a, uint32x4_t __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_raddhnv4si ((int32x4_t) __a, -+ (int32x4_t) __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vraddhn_u64 (uint64x2_t __a, uint64x2_t __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_raddhnv2di ((int64x2_t) __a, -+ (int64x2_t) __b); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vaddhn_high_s16 (int8x8_t __a, int16x8_t __b, int16x8_t __c) -+{ -+ return (int8x16_t) __builtin_aarch64_addhn2v8hi (__a, __b, __c); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vaddhn_high_s32 (int16x4_t __a, int32x4_t __b, int32x4_t __c) -+{ -+ return (int16x8_t) __builtin_aarch64_addhn2v4si (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vaddhn_high_s64 (int32x2_t __a, int64x2_t __b, int64x2_t __c) -+{ -+ return (int32x4_t) __builtin_aarch64_addhn2v2di (__a, __b, __c); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vaddhn_high_u16 (uint8x8_t __a, uint16x8_t __b, uint16x8_t __c) -+{ -+ return (uint8x16_t) __builtin_aarch64_addhn2v8hi ((int8x8_t) __a, -+ (int16x8_t) __b, -+ (int16x8_t) __c); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vaddhn_high_u32 (uint16x4_t __a, uint32x4_t __b, uint32x4_t __c) -+{ -+ return (uint16x8_t) __builtin_aarch64_addhn2v4si ((int16x4_t) __a, -+ (int32x4_t) __b, -+ (int32x4_t) __c); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vaddhn_high_u64 (uint32x2_t __a, uint64x2_t __b, uint64x2_t __c) -+{ -+ return (uint32x4_t) __builtin_aarch64_addhn2v2di ((int32x2_t) __a, -+ (int64x2_t) __b, -+ (int64x2_t) __c); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vraddhn_high_s16 (int8x8_t __a, int16x8_t __b, int16x8_t __c) -+{ -+ return (int8x16_t) __builtin_aarch64_raddhn2v8hi (__a, __b, __c); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vraddhn_high_s32 (int16x4_t __a, int32x4_t __b, int32x4_t __c) -+{ -+ return (int16x8_t) __builtin_aarch64_raddhn2v4si (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vraddhn_high_s64 (int32x2_t __a, int64x2_t __b, int64x2_t __c) -+{ -+ return (int32x4_t) __builtin_aarch64_raddhn2v2di (__a, __b, __c); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vraddhn_high_u16 (uint8x8_t __a, uint16x8_t __b, uint16x8_t __c) -+{ -+ return (uint8x16_t) __builtin_aarch64_raddhn2v8hi ((int8x8_t) __a, -+ (int16x8_t) __b, -+ (int16x8_t) __c); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vraddhn_high_u32 (uint16x4_t __a, uint32x4_t __b, uint32x4_t __c) -+{ -+ return (uint16x8_t) __builtin_aarch64_raddhn2v4si ((int16x4_t) __a, -+ (int32x4_t) __b, -+ (int32x4_t) __c); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vraddhn_high_u64 (uint32x2_t __a, uint64x2_t __b, uint64x2_t __c) -+{ -+ return (uint32x4_t) __builtin_aarch64_raddhn2v2di ((int32x2_t) __a, -+ (int64x2_t) __b, -+ (int64x2_t) __c); -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vdiv_f32 (float32x2_t __a, float32x2_t __b) -+{ -+ return __a / __b; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vdivq_f32 (float32x4_t __a, float32x4_t __b) -+{ -+ return __a / __b; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vdivq_f64 (float64x2_t __a, float64x2_t __b) -+{ -+ return __a / __b; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vmul_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return __a * __b; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vmul_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return __a * __b; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vmul_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return __a * __b; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vmul_f32 (float32x2_t __a, float32x2_t __b) -+{ -+ return __a * __b; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vmul_u8 (uint8x8_t __a, uint8x8_t __b) -+{ -+ return __a * __b; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vmul_u16 (uint16x4_t __a, uint16x4_t __b) -+{ -+ return __a * __b; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vmul_u32 (uint32x2_t __a, uint32x2_t __b) -+{ -+ return __a * __b; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vmul_p8 (poly8x8_t __a, poly8x8_t __b) -+{ -+ return (poly8x8_t) __builtin_aarch64_pmulv8qi ((int8x8_t) __a, -+ (int8x8_t) __b); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vmulq_s8 (int8x16_t __a, int8x16_t __b) -+{ -+ return __a * __b; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vmulq_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return __a * __b; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vmulq_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return __a * __b; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vmulq_f32 (float32x4_t __a, float32x4_t __b) -+{ -+ return __a * __b; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vmulq_f64 (float64x2_t __a, float64x2_t __b) -+{ -+ return __a * __b; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vmulq_u8 (uint8x16_t __a, uint8x16_t __b) -+{ -+ return __a * __b; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vmulq_u16 (uint16x8_t __a, uint16x8_t __b) -+{ -+ return __a * __b; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vmulq_u32 (uint32x4_t __a, uint32x4_t __b) -+{ -+ return __a * __b; -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vmulq_p8 (poly8x16_t __a, poly8x16_t __b) -+{ -+ return (poly8x16_t) __builtin_aarch64_pmulv16qi ((int8x16_t) __a, -+ (int8x16_t) __b); -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vand_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return __a & __b; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vand_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return __a & __b; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vand_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return __a & __b; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vand_u8 (uint8x8_t __a, uint8x8_t __b) -+{ -+ return __a & __b; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vand_u16 (uint16x4_t __a, uint16x4_t __b) -+{ -+ return __a & __b; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vand_u32 (uint32x2_t __a, uint32x2_t __b) -+{ -+ return __a & __b; -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vand_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return __a & __b; -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vand_u64 (uint64x1_t __a, uint64x1_t __b) -+{ -+ return __a & __b; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vandq_s8 (int8x16_t __a, int8x16_t __b) -+{ -+ return __a & __b; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vandq_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return __a & __b; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vandq_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return __a & __b; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vandq_s64 (int64x2_t __a, int64x2_t __b) -+{ -+ return __a & __b; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vandq_u8 (uint8x16_t __a, uint8x16_t __b) -+{ -+ return __a & __b; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vandq_u16 (uint16x8_t __a, uint16x8_t __b) -+{ -+ return __a & __b; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vandq_u32 (uint32x4_t __a, uint32x4_t __b) -+{ -+ return __a & __b; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vandq_u64 (uint64x2_t __a, uint64x2_t __b) -+{ -+ return __a & __b; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vorr_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return __a | __b; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vorr_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return __a | __b; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vorr_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return __a | __b; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vorr_u8 (uint8x8_t __a, uint8x8_t __b) -+{ -+ return __a | __b; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vorr_u16 (uint16x4_t __a, uint16x4_t __b) -+{ -+ return __a | __b; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vorr_u32 (uint32x2_t __a, uint32x2_t __b) -+{ -+ return __a | __b; -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vorr_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return __a | __b; -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vorr_u64 (uint64x1_t __a, uint64x1_t __b) -+{ -+ return __a | __b; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vorrq_s8 (int8x16_t __a, int8x16_t __b) -+{ -+ return __a | __b; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vorrq_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return __a | __b; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vorrq_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return __a | __b; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vorrq_s64 (int64x2_t __a, int64x2_t __b) -+{ -+ return __a | __b; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vorrq_u8 (uint8x16_t __a, uint8x16_t __b) -+{ -+ return __a | __b; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vorrq_u16 (uint16x8_t __a, uint16x8_t __b) -+{ -+ return __a | __b; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vorrq_u32 (uint32x4_t __a, uint32x4_t __b) -+{ -+ return __a | __b; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vorrq_u64 (uint64x2_t __a, uint64x2_t __b) -+{ -+ return __a | __b; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+veor_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return __a ^ __b; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+veor_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return __a ^ __b; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+veor_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return __a ^ __b; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+veor_u8 (uint8x8_t __a, uint8x8_t __b) -+{ -+ return __a ^ __b; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+veor_u16 (uint16x4_t __a, uint16x4_t __b) -+{ -+ return __a ^ __b; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+veor_u32 (uint32x2_t __a, uint32x2_t __b) -+{ -+ return __a ^ __b; -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+veor_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return __a ^ __b; -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+veor_u64 (uint64x1_t __a, uint64x1_t __b) -+{ -+ return __a ^ __b; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+veorq_s8 (int8x16_t __a, int8x16_t __b) -+{ -+ return __a ^ __b; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+veorq_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return __a ^ __b; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+veorq_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return __a ^ __b; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+veorq_s64 (int64x2_t __a, int64x2_t __b) -+{ -+ return __a ^ __b; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+veorq_u8 (uint8x16_t __a, uint8x16_t __b) -+{ -+ return __a ^ __b; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+veorq_u16 (uint16x8_t __a, uint16x8_t __b) -+{ -+ return __a ^ __b; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+veorq_u32 (uint32x4_t __a, uint32x4_t __b) -+{ -+ return __a ^ __b; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+veorq_u64 (uint64x2_t __a, uint64x2_t __b) -+{ -+ return __a ^ __b; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vbic_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return __a & ~__b; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vbic_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return __a & ~__b; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vbic_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return __a & ~__b; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vbic_u8 (uint8x8_t __a, uint8x8_t __b) -+{ -+ return __a & ~__b; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vbic_u16 (uint16x4_t __a, uint16x4_t __b) -+{ -+ return __a & ~__b; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vbic_u32 (uint32x2_t __a, uint32x2_t __b) -+{ -+ return __a & ~__b; -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vbic_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return __a & ~__b; -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vbic_u64 (uint64x1_t __a, uint64x1_t __b) -+{ -+ return __a & ~__b; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vbicq_s8 (int8x16_t __a, int8x16_t __b) -+{ -+ return __a & ~__b; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vbicq_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return __a & ~__b; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vbicq_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return __a & ~__b; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vbicq_s64 (int64x2_t __a, int64x2_t __b) -+{ -+ return __a & ~__b; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vbicq_u8 (uint8x16_t __a, uint8x16_t __b) -+{ -+ return __a & ~__b; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vbicq_u16 (uint16x8_t __a, uint16x8_t __b) -+{ -+ return __a & ~__b; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vbicq_u32 (uint32x4_t __a, uint32x4_t __b) -+{ -+ return __a & ~__b; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vbicq_u64 (uint64x2_t __a, uint64x2_t __b) -+{ -+ return __a & ~__b; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vorn_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return __a | ~__b; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vorn_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return __a | ~__b; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vorn_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return __a | ~__b; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vorn_u8 (uint8x8_t __a, uint8x8_t __b) -+{ -+ return __a | ~__b; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vorn_u16 (uint16x4_t __a, uint16x4_t __b) -+{ -+ return __a | ~__b; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vorn_u32 (uint32x2_t __a, uint32x2_t __b) -+{ -+ return __a | ~__b; -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vorn_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return __a | ~__b; -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vorn_u64 (uint64x1_t __a, uint64x1_t __b) -+{ -+ return __a | ~__b; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vornq_s8 (int8x16_t __a, int8x16_t __b) -+{ -+ return __a | ~__b; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vornq_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return __a | ~__b; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vornq_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return __a | ~__b; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vornq_s64 (int64x2_t __a, int64x2_t __b) -+{ -+ return __a | ~__b; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vornq_u8 (uint8x16_t __a, uint8x16_t __b) -+{ -+ return __a | ~__b; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vornq_u16 (uint16x8_t __a, uint16x8_t __b) -+{ -+ return __a | ~__b; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vornq_u32 (uint32x4_t __a, uint32x4_t __b) -+{ -+ return __a | ~__b; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vornq_u64 (uint64x2_t __a, uint64x2_t __b) -+{ -+ return __a | ~__b; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vsub_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return __a - __b; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vsub_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return __a - __b; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vsub_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return __a - __b; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vsub_f32 (float32x2_t __a, float32x2_t __b) -+{ -+ return __a - __b; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vsub_u8 (uint8x8_t __a, uint8x8_t __b) -+{ -+ return __a - __b; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vsub_u16 (uint16x4_t __a, uint16x4_t __b) -+{ -+ return __a - __b; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vsub_u32 (uint32x2_t __a, uint32x2_t __b) -+{ -+ return __a - __b; -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vsub_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return __a - __b; -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vsub_u64 (uint64x1_t __a, uint64x1_t __b) -+{ -+ return __a - __b; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vsubq_s8 (int8x16_t __a, int8x16_t __b) -+{ -+ return __a - __b; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vsubq_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return __a - __b; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vsubq_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return __a - __b; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vsubq_s64 (int64x2_t __a, int64x2_t __b) -+{ -+ return __a - __b; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vsubq_f32 (float32x4_t __a, float32x4_t __b) -+{ -+ return __a - __b; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vsubq_f64 (float64x2_t __a, float64x2_t __b) -+{ -+ return __a - __b; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vsubq_u8 (uint8x16_t __a, uint8x16_t __b) -+{ -+ return __a - __b; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vsubq_u16 (uint16x8_t __a, uint16x8_t __b) -+{ -+ return __a - __b; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vsubq_u32 (uint32x4_t __a, uint32x4_t __b) -+{ -+ return __a - __b; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vsubq_u64 (uint64x2_t __a, uint64x2_t __b) -+{ -+ return __a - __b; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vsubl_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return (int16x8_t) __builtin_aarch64_ssublv8qi (__a, __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vsubl_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return (int32x4_t) __builtin_aarch64_ssublv4hi (__a, __b); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vsubl_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return (int64x2_t) __builtin_aarch64_ssublv2si (__a, __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vsubl_u8 (uint8x8_t __a, uint8x8_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_usublv8qi ((int8x8_t) __a, -+ (int8x8_t) __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vsubl_u16 (uint16x4_t __a, uint16x4_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_usublv4hi ((int16x4_t) __a, -+ (int16x4_t) __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vsubl_u32 (uint32x2_t __a, uint32x2_t __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_usublv2si ((int32x2_t) __a, -+ (int32x2_t) __b); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vsubl_high_s8 (int8x16_t __a, int8x16_t __b) -+{ -+ return (int16x8_t) __builtin_aarch64_ssubl2v16qi (__a, __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vsubl_high_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return (int32x4_t) __builtin_aarch64_ssubl2v8hi (__a, __b); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vsubl_high_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return (int64x2_t) __builtin_aarch64_ssubl2v4si (__a, __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vsubl_high_u8 (uint8x16_t __a, uint8x16_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_usubl2v16qi ((int8x16_t) __a, -+ (int8x16_t) __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vsubl_high_u16 (uint16x8_t __a, uint16x8_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_usubl2v8hi ((int16x8_t) __a, -+ (int16x8_t) __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vsubl_high_u32 (uint32x4_t __a, uint32x4_t __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_usubl2v4si ((int32x4_t) __a, -+ (int32x4_t) __b); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vsubw_s8 (int16x8_t __a, int8x8_t __b) -+{ -+ return (int16x8_t) __builtin_aarch64_ssubwv8qi (__a, __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vsubw_s16 (int32x4_t __a, int16x4_t __b) -+{ -+ return (int32x4_t) __builtin_aarch64_ssubwv4hi (__a, __b); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vsubw_s32 (int64x2_t __a, int32x2_t __b) -+{ -+ return (int64x2_t) __builtin_aarch64_ssubwv2si (__a, __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vsubw_u8 (uint16x8_t __a, uint8x8_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_usubwv8qi ((int16x8_t) __a, -+ (int8x8_t) __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vsubw_u16 (uint32x4_t __a, uint16x4_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_usubwv4hi ((int32x4_t) __a, -+ (int16x4_t) __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vsubw_u32 (uint64x2_t __a, uint32x2_t __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_usubwv2si ((int64x2_t) __a, -+ (int32x2_t) __b); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vsubw_high_s8 (int16x8_t __a, int8x16_t __b) -+{ -+ return (int16x8_t) __builtin_aarch64_ssubw2v16qi (__a, __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vsubw_high_s16 (int32x4_t __a, int16x8_t __b) -+{ -+ return (int32x4_t) __builtin_aarch64_ssubw2v8hi (__a, __b); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vsubw_high_s32 (int64x2_t __a, int32x4_t __b) -+{ -+ return (int64x2_t) __builtin_aarch64_ssubw2v4si (__a, __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vsubw_high_u8 (uint16x8_t __a, uint8x16_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_usubw2v16qi ((int16x8_t) __a, -+ (int8x16_t) __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vsubw_high_u16 (uint32x4_t __a, uint16x8_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_usubw2v8hi ((int32x4_t) __a, -+ (int16x8_t) __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vsubw_high_u32 (uint64x2_t __a, uint32x4_t __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_usubw2v4si ((int64x2_t) __a, -+ (int32x4_t) __b); -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vqadd_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return (int8x8_t) __builtin_aarch64_sqaddv8qi (__a, __b); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vqadd_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return (int16x4_t) __builtin_aarch64_sqaddv4hi (__a, __b); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vqadd_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return (int32x2_t) __builtin_aarch64_sqaddv2si (__a, __b); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vqadd_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return (int64x1_t) __builtin_aarch64_sqadddi (__a, __b); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vqadd_u8 (uint8x8_t __a, uint8x8_t __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_uqaddv8qi ((int8x8_t) __a, -+ (int8x8_t) __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vqadd_u16 (uint16x4_t __a, uint16x4_t __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_uqaddv4hi ((int16x4_t) __a, -+ (int16x4_t) __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vqadd_u32 (uint32x2_t __a, uint32x2_t __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_uqaddv2si ((int32x2_t) __a, -+ (int32x2_t) __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vqadd_u64 (uint64x1_t __a, uint64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_uqadddi ((int64x1_t) __a, -+ (int64x1_t) __b); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vqaddq_s8 (int8x16_t __a, int8x16_t __b) -+{ -+ return (int8x16_t) __builtin_aarch64_sqaddv16qi (__a, __b); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vqaddq_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return (int16x8_t) __builtin_aarch64_sqaddv8hi (__a, __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqaddq_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return (int32x4_t) __builtin_aarch64_sqaddv4si (__a, __b); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqaddq_s64 (int64x2_t __a, int64x2_t __b) -+{ -+ return (int64x2_t) __builtin_aarch64_sqaddv2di (__a, __b); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vqaddq_u8 (uint8x16_t __a, uint8x16_t __b) -+{ -+ return (uint8x16_t) __builtin_aarch64_uqaddv16qi ((int8x16_t) __a, -+ (int8x16_t) __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vqaddq_u16 (uint16x8_t __a, uint16x8_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_uqaddv8hi ((int16x8_t) __a, -+ (int16x8_t) __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vqaddq_u32 (uint32x4_t __a, uint32x4_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_uqaddv4si ((int32x4_t) __a, -+ (int32x4_t) __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vqaddq_u64 (uint64x2_t __a, uint64x2_t __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_uqaddv2di ((int64x2_t) __a, -+ (int64x2_t) __b); -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vqsub_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return (int8x8_t) __builtin_aarch64_sqsubv8qi (__a, __b); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vqsub_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return (int16x4_t) __builtin_aarch64_sqsubv4hi (__a, __b); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vqsub_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return (int32x2_t) __builtin_aarch64_sqsubv2si (__a, __b); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vqsub_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return (int64x1_t) __builtin_aarch64_sqsubdi (__a, __b); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vqsub_u8 (uint8x8_t __a, uint8x8_t __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_uqsubv8qi ((int8x8_t) __a, -+ (int8x8_t) __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vqsub_u16 (uint16x4_t __a, uint16x4_t __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_uqsubv4hi ((int16x4_t) __a, -+ (int16x4_t) __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vqsub_u32 (uint32x2_t __a, uint32x2_t __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_uqsubv2si ((int32x2_t) __a, -+ (int32x2_t) __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vqsub_u64 (uint64x1_t __a, uint64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_uqsubdi ((int64x1_t) __a, -+ (int64x1_t) __b); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vqsubq_s8 (int8x16_t __a, int8x16_t __b) -+{ -+ return (int8x16_t) __builtin_aarch64_sqsubv16qi (__a, __b); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vqsubq_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return (int16x8_t) __builtin_aarch64_sqsubv8hi (__a, __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqsubq_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return (int32x4_t) __builtin_aarch64_sqsubv4si (__a, __b); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqsubq_s64 (int64x2_t __a, int64x2_t __b) -+{ -+ return (int64x2_t) __builtin_aarch64_sqsubv2di (__a, __b); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vqsubq_u8 (uint8x16_t __a, uint8x16_t __b) -+{ -+ return (uint8x16_t) __builtin_aarch64_uqsubv16qi ((int8x16_t) __a, -+ (int8x16_t) __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vqsubq_u16 (uint16x8_t __a, uint16x8_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_uqsubv8hi ((int16x8_t) __a, -+ (int16x8_t) __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vqsubq_u32 (uint32x4_t __a, uint32x4_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_uqsubv4si ((int32x4_t) __a, -+ (int32x4_t) __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vqsubq_u64 (uint64x2_t __a, uint64x2_t __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_uqsubv2di ((int64x2_t) __a, -+ (int64x2_t) __b); -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vqneg_s8 (int8x8_t __a) -+{ -+ return (int8x8_t) __builtin_aarch64_sqnegv8qi (__a); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vqneg_s16 (int16x4_t __a) -+{ -+ return (int16x4_t) __builtin_aarch64_sqnegv4hi (__a); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vqneg_s32 (int32x2_t __a) -+{ -+ return (int32x2_t) __builtin_aarch64_sqnegv2si (__a); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vqnegq_s8 (int8x16_t __a) -+{ -+ return (int8x16_t) __builtin_aarch64_sqnegv16qi (__a); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vqnegq_s16 (int16x8_t __a) -+{ -+ return (int16x8_t) __builtin_aarch64_sqnegv8hi (__a); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqnegq_s32 (int32x4_t __a) -+{ -+ return (int32x4_t) __builtin_aarch64_sqnegv4si (__a); -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vqabs_s8 (int8x8_t __a) -+{ -+ return (int8x8_t) __builtin_aarch64_sqabsv8qi (__a); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vqabs_s16 (int16x4_t __a) -+{ -+ return (int16x4_t) __builtin_aarch64_sqabsv4hi (__a); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vqabs_s32 (int32x2_t __a) -+{ -+ return (int32x2_t) __builtin_aarch64_sqabsv2si (__a); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vqabsq_s8 (int8x16_t __a) -+{ -+ return (int8x16_t) __builtin_aarch64_sqabsv16qi (__a); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vqabsq_s16 (int16x8_t __a) -+{ -+ return (int16x8_t) __builtin_aarch64_sqabsv8hi (__a); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqabsq_s32 (int32x4_t __a) -+{ -+ return (int32x4_t) __builtin_aarch64_sqabsv4si (__a); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vqdmulh_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return (int16x4_t) __builtin_aarch64_sqdmulhv4hi (__a, __b); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vqdmulh_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return (int32x2_t) __builtin_aarch64_sqdmulhv2si (__a, __b); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vqdmulhq_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return (int16x8_t) __builtin_aarch64_sqdmulhv8hi (__a, __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqdmulhq_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return (int32x4_t) __builtin_aarch64_sqdmulhv4si (__a, __b); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vqrdmulh_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return (int16x4_t) __builtin_aarch64_sqrdmulhv4hi (__a, __b); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vqrdmulh_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return (int32x2_t) __builtin_aarch64_sqrdmulhv2si (__a, __b); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vqrdmulhq_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return (int16x8_t) __builtin_aarch64_sqrdmulhv8hi (__a, __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqrdmulhq_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return (int32x4_t) __builtin_aarch64_sqrdmulhv4si (__a, __b); -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vcreate_s8 (uint64_t __a) -+{ -+ return (int8x8_t) __a; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vcreate_s16 (uint64_t __a) -+{ -+ return (int16x4_t) __a; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vcreate_s32 (uint64_t __a) -+{ -+ return (int32x2_t) __a; -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vcreate_s64 (uint64_t __a) -+{ -+ return (int64x1_t) __a; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vcreate_f32 (uint64_t __a) -+{ -+ return (float32x2_t) __a; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vcreate_u8 (uint64_t __a) -+{ -+ return (uint8x8_t) __a; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vcreate_u16 (uint64_t __a) -+{ -+ return (uint16x4_t) __a; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vcreate_u32 (uint64_t __a) -+{ -+ return (uint32x2_t) __a; -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vcreate_u64 (uint64_t __a) -+{ -+ return (uint64x1_t) __a; -+} -+ -+__extension__ static __inline float64x1_t __attribute__ ((__always_inline__)) -+vcreate_f64 (uint64_t __a) -+{ -+ return (float64x1_t) __builtin_aarch64_createdf (__a); -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vcreate_p8 (uint64_t __a) -+{ -+ return (poly8x8_t) __a; -+} -+ -+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) -+vcreate_p16 (uint64_t __a) -+{ -+ return (poly16x4_t) __a; -+} -+ -+__extension__ static __inline int8_t __attribute__ ((__always_inline__)) -+vget_lane_s8 (int8x8_t __a, const int __b) -+{ -+ return (int8_t) __builtin_aarch64_get_lane_signedv8qi (__a, __b); -+} -+ -+__extension__ static __inline int16_t __attribute__ ((__always_inline__)) -+vget_lane_s16 (int16x4_t __a, const int __b) -+{ -+ return (int16_t) __builtin_aarch64_get_lane_signedv4hi (__a, __b); -+} -+ -+__extension__ static __inline int32_t __attribute__ ((__always_inline__)) -+vget_lane_s32 (int32x2_t __a, const int __b) -+{ -+ return (int32_t) __builtin_aarch64_get_lane_signedv2si (__a, __b); -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vget_lane_f32 (float32x2_t __a, const int __b) -+{ -+ return (float32_t) __builtin_aarch64_get_lanev2sf (__a, __b); -+} -+ -+__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) -+vget_lane_u8 (uint8x8_t __a, const int __b) -+{ -+ return (uint8_t) __builtin_aarch64_get_lane_unsignedv8qi ((int8x8_t) __a, -+ __b); -+} -+ -+__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) -+vget_lane_u16 (uint16x4_t __a, const int __b) -+{ -+ return (uint16_t) __builtin_aarch64_get_lane_unsignedv4hi ((int16x4_t) __a, -+ __b); -+} -+ -+__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) -+vget_lane_u32 (uint32x2_t __a, const int __b) -+{ -+ return (uint32_t) __builtin_aarch64_get_lane_unsignedv2si ((int32x2_t) __a, -+ __b); -+} -+ -+__extension__ static __inline poly8_t __attribute__ ((__always_inline__)) -+vget_lane_p8 (poly8x8_t __a, const int __b) -+{ -+ return (poly8_t) __builtin_aarch64_get_lane_unsignedv8qi ((int8x8_t) __a, -+ __b); -+} -+ -+__extension__ static __inline poly16_t __attribute__ ((__always_inline__)) -+vget_lane_p16 (poly16x4_t __a, const int __b) -+{ -+ return (poly16_t) __builtin_aarch64_get_lane_unsignedv4hi ((int16x4_t) __a, -+ __b); -+} -+ -+__extension__ static __inline int64_t __attribute__ ((__always_inline__)) -+vget_lane_s64 (int64x1_t __a, const int __b) -+{ -+ return (int64_t) __builtin_aarch64_get_lanedi (__a, __b); -+} -+ -+__extension__ static __inline uint64_t __attribute__ ((__always_inline__)) -+vget_lane_u64 (uint64x1_t __a, const int __b) -+{ -+ return (uint64_t) __builtin_aarch64_get_lanedi ((int64x1_t) __a, __b); -+} -+ -+__extension__ static __inline int8_t __attribute__ ((__always_inline__)) -+vgetq_lane_s8 (int8x16_t __a, const int __b) -+{ -+ return (int8_t) __builtin_aarch64_get_lane_signedv16qi (__a, __b); -+} -+ -+__extension__ static __inline int16_t __attribute__ ((__always_inline__)) -+vgetq_lane_s16 (int16x8_t __a, const int __b) -+{ -+ return (int16_t) __builtin_aarch64_get_lane_signedv8hi (__a, __b); -+} -+ -+__extension__ static __inline int32_t __attribute__ ((__always_inline__)) -+vgetq_lane_s32 (int32x4_t __a, const int __b) -+{ -+ return (int32_t) __builtin_aarch64_get_lane_signedv4si (__a, __b); -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vgetq_lane_f32 (float32x4_t __a, const int __b) -+{ -+ return (float32_t) __builtin_aarch64_get_lanev4sf (__a, __b); -+} -+ -+__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -+vgetq_lane_f64 (float64x2_t __a, const int __b) -+{ -+ return (float64_t) __builtin_aarch64_get_lanev2df (__a, __b); -+} -+ -+__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) -+vgetq_lane_u8 (uint8x16_t __a, const int __b) -+{ -+ return (uint8_t) __builtin_aarch64_get_lane_unsignedv16qi ((int8x16_t) __a, -+ __b); -+} -+ -+__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) -+vgetq_lane_u16 (uint16x8_t __a, const int __b) -+{ -+ return (uint16_t) __builtin_aarch64_get_lane_unsignedv8hi ((int16x8_t) __a, -+ __b); -+} -+ -+__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) -+vgetq_lane_u32 (uint32x4_t __a, const int __b) -+{ -+ return (uint32_t) __builtin_aarch64_get_lane_unsignedv4si ((int32x4_t) __a, -+ __b); -+} -+ -+__extension__ static __inline poly8_t __attribute__ ((__always_inline__)) -+vgetq_lane_p8 (poly8x16_t __a, const int __b) -+{ -+ return (poly8_t) __builtin_aarch64_get_lane_unsignedv16qi ((int8x16_t) __a, -+ __b); -+} -+ -+__extension__ static __inline poly16_t __attribute__ ((__always_inline__)) -+vgetq_lane_p16 (poly16x8_t __a, const int __b) -+{ -+ return (poly16_t) __builtin_aarch64_get_lane_unsignedv8hi ((int16x8_t) __a, -+ __b); -+} -+ -+__extension__ static __inline int64_t __attribute__ ((__always_inline__)) -+vgetq_lane_s64 (int64x2_t __a, const int __b) -+{ -+ return __builtin_aarch64_get_lane_unsignedv2di (__a, __b); -+} -+ -+__extension__ static __inline uint64_t __attribute__ ((__always_inline__)) -+vgetq_lane_u64 (uint64x2_t __a, const int __b) -+{ -+ return (uint64_t) __builtin_aarch64_get_lane_unsignedv2di ((int64x2_t) __a, -+ __b); -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vreinterpret_p8_s8 (int8x8_t __a) -+{ -+ return (poly8x8_t) __builtin_aarch64_reinterpretv8qiv8qi (__a); -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vreinterpret_p8_s16 (int16x4_t __a) -+{ -+ return (poly8x8_t) __builtin_aarch64_reinterpretv8qiv4hi (__a); -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vreinterpret_p8_s32 (int32x2_t __a) -+{ -+ return (poly8x8_t) __builtin_aarch64_reinterpretv8qiv2si (__a); -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vreinterpret_p8_s64 (int64x1_t __a) -+{ -+ return (poly8x8_t) __builtin_aarch64_reinterpretv8qidi (__a); -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vreinterpret_p8_f32 (float32x2_t __a) -+{ -+ return (poly8x8_t) __builtin_aarch64_reinterpretv8qiv2sf (__a); -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vreinterpret_p8_u8 (uint8x8_t __a) -+{ -+ return (poly8x8_t) __builtin_aarch64_reinterpretv8qiv8qi ((int8x8_t) __a); -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vreinterpret_p8_u16 (uint16x4_t __a) -+{ -+ return (poly8x8_t) __builtin_aarch64_reinterpretv8qiv4hi ((int16x4_t) __a); -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vreinterpret_p8_u32 (uint32x2_t __a) -+{ -+ return (poly8x8_t) __builtin_aarch64_reinterpretv8qiv2si ((int32x2_t) __a); -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vreinterpret_p8_u64 (uint64x1_t __a) -+{ -+ return (poly8x8_t) __builtin_aarch64_reinterpretv8qidi ((int64x1_t) __a); -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vreinterpret_p8_p16 (poly16x4_t __a) -+{ -+ return (poly8x8_t) __builtin_aarch64_reinterpretv8qiv4hi ((int16x4_t) __a); -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vreinterpretq_p8_s8 (int8x16_t __a) -+{ -+ return (poly8x16_t) __builtin_aarch64_reinterpretv16qiv16qi (__a); -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vreinterpretq_p8_s16 (int16x8_t __a) -+{ -+ return (poly8x16_t) __builtin_aarch64_reinterpretv16qiv8hi (__a); -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vreinterpretq_p8_s32 (int32x4_t __a) -+{ -+ return (poly8x16_t) __builtin_aarch64_reinterpretv16qiv4si (__a); -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vreinterpretq_p8_s64 (int64x2_t __a) -+{ -+ return (poly8x16_t) __builtin_aarch64_reinterpretv16qiv2di (__a); -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vreinterpretq_p8_f32 (float32x4_t __a) -+{ -+ return (poly8x16_t) __builtin_aarch64_reinterpretv16qiv4sf (__a); -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vreinterpretq_p8_u8 (uint8x16_t __a) -+{ -+ return (poly8x16_t) __builtin_aarch64_reinterpretv16qiv16qi ((int8x16_t) -+ __a); -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vreinterpretq_p8_u16 (uint16x8_t __a) -+{ -+ return (poly8x16_t) __builtin_aarch64_reinterpretv16qiv8hi ((int16x8_t) -+ __a); -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vreinterpretq_p8_u32 (uint32x4_t __a) -+{ -+ return (poly8x16_t) __builtin_aarch64_reinterpretv16qiv4si ((int32x4_t) -+ __a); -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vreinterpretq_p8_u64 (uint64x2_t __a) -+{ -+ return (poly8x16_t) __builtin_aarch64_reinterpretv16qiv2di ((int64x2_t) -+ __a); -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vreinterpretq_p8_p16 (poly16x8_t __a) -+{ -+ return (poly8x16_t) __builtin_aarch64_reinterpretv16qiv8hi ((int16x8_t) -+ __a); -+} -+ -+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) -+vreinterpret_p16_s8 (int8x8_t __a) -+{ -+ return (poly16x4_t) __builtin_aarch64_reinterpretv4hiv8qi (__a); -+} -+ -+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) -+vreinterpret_p16_s16 (int16x4_t __a) -+{ -+ return (poly16x4_t) __builtin_aarch64_reinterpretv4hiv4hi (__a); -+} -+ -+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) -+vreinterpret_p16_s32 (int32x2_t __a) -+{ -+ return (poly16x4_t) __builtin_aarch64_reinterpretv4hiv2si (__a); -+} -+ -+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) -+vreinterpret_p16_s64 (int64x1_t __a) -+{ -+ return (poly16x4_t) __builtin_aarch64_reinterpretv4hidi (__a); -+} -+ -+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) -+vreinterpret_p16_f32 (float32x2_t __a) -+{ -+ return (poly16x4_t) __builtin_aarch64_reinterpretv4hiv2sf (__a); -+} -+ -+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) -+vreinterpret_p16_u8 (uint8x8_t __a) -+{ -+ return (poly16x4_t) __builtin_aarch64_reinterpretv4hiv8qi ((int8x8_t) __a); -+} -+ -+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) -+vreinterpret_p16_u16 (uint16x4_t __a) -+{ -+ return (poly16x4_t) __builtin_aarch64_reinterpretv4hiv4hi ((int16x4_t) __a); -+} -+ -+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) -+vreinterpret_p16_u32 (uint32x2_t __a) -+{ -+ return (poly16x4_t) __builtin_aarch64_reinterpretv4hiv2si ((int32x2_t) __a); -+} -+ -+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) -+vreinterpret_p16_u64 (uint64x1_t __a) -+{ -+ return (poly16x4_t) __builtin_aarch64_reinterpretv4hidi ((int64x1_t) __a); -+} -+ -+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) -+vreinterpret_p16_p8 (poly8x8_t __a) -+{ -+ return (poly16x4_t) __builtin_aarch64_reinterpretv4hiv8qi ((int8x8_t) __a); -+} -+ -+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) -+vreinterpretq_p16_s8 (int8x16_t __a) -+{ -+ return (poly16x8_t) __builtin_aarch64_reinterpretv8hiv16qi (__a); -+} -+ -+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) -+vreinterpretq_p16_s16 (int16x8_t __a) -+{ -+ return (poly16x8_t) __builtin_aarch64_reinterpretv8hiv8hi (__a); -+} -+ -+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) -+vreinterpretq_p16_s32 (int32x4_t __a) -+{ -+ return (poly16x8_t) __builtin_aarch64_reinterpretv8hiv4si (__a); -+} -+ -+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) -+vreinterpretq_p16_s64 (int64x2_t __a) -+{ -+ return (poly16x8_t) __builtin_aarch64_reinterpretv8hiv2di (__a); -+} -+ -+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) -+vreinterpretq_p16_f32 (float32x4_t __a) -+{ -+ return (poly16x8_t) __builtin_aarch64_reinterpretv8hiv4sf (__a); -+} -+ -+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) -+vreinterpretq_p16_u8 (uint8x16_t __a) -+{ -+ return (poly16x8_t) __builtin_aarch64_reinterpretv8hiv16qi ((int8x16_t) -+ __a); -+} -+ -+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) -+vreinterpretq_p16_u16 (uint16x8_t __a) -+{ -+ return (poly16x8_t) __builtin_aarch64_reinterpretv8hiv8hi ((int16x8_t) __a); -+} -+ -+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) -+vreinterpretq_p16_u32 (uint32x4_t __a) -+{ -+ return (poly16x8_t) __builtin_aarch64_reinterpretv8hiv4si ((int32x4_t) __a); -+} -+ -+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) -+vreinterpretq_p16_u64 (uint64x2_t __a) -+{ -+ return (poly16x8_t) __builtin_aarch64_reinterpretv8hiv2di ((int64x2_t) __a); -+} -+ -+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) -+vreinterpretq_p16_p8 (poly8x16_t __a) -+{ -+ return (poly16x8_t) __builtin_aarch64_reinterpretv8hiv16qi ((int8x16_t) -+ __a); -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vreinterpret_f32_s8 (int8x8_t __a) -+{ -+ return (float32x2_t) __builtin_aarch64_reinterpretv2sfv8qi (__a); -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vreinterpret_f32_s16 (int16x4_t __a) -+{ -+ return (float32x2_t) __builtin_aarch64_reinterpretv2sfv4hi (__a); -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vreinterpret_f32_s32 (int32x2_t __a) -+{ -+ return (float32x2_t) __builtin_aarch64_reinterpretv2sfv2si (__a); -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vreinterpret_f32_s64 (int64x1_t __a) -+{ -+ return (float32x2_t) __builtin_aarch64_reinterpretv2sfdi (__a); -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vreinterpret_f32_u8 (uint8x8_t __a) -+{ -+ return (float32x2_t) __builtin_aarch64_reinterpretv2sfv8qi ((int8x8_t) __a); -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vreinterpret_f32_u16 (uint16x4_t __a) -+{ -+ return (float32x2_t) __builtin_aarch64_reinterpretv2sfv4hi ((int16x4_t) -+ __a); -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vreinterpret_f32_u32 (uint32x2_t __a) -+{ -+ return (float32x2_t) __builtin_aarch64_reinterpretv2sfv2si ((int32x2_t) -+ __a); -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vreinterpret_f32_u64 (uint64x1_t __a) -+{ -+ return (float32x2_t) __builtin_aarch64_reinterpretv2sfdi ((int64x1_t) __a); -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vreinterpret_f32_p8 (poly8x8_t __a) -+{ -+ return (float32x2_t) __builtin_aarch64_reinterpretv2sfv8qi ((int8x8_t) __a); -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vreinterpret_f32_p16 (poly16x4_t __a) -+{ -+ return (float32x2_t) __builtin_aarch64_reinterpretv2sfv4hi ((int16x4_t) -+ __a); -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vreinterpretq_f32_s8 (int8x16_t __a) -+{ -+ return (float32x4_t) __builtin_aarch64_reinterpretv4sfv16qi (__a); -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vreinterpretq_f32_s16 (int16x8_t __a) -+{ -+ return (float32x4_t) __builtin_aarch64_reinterpretv4sfv8hi (__a); -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vreinterpretq_f32_s32 (int32x4_t __a) -+{ -+ return (float32x4_t) __builtin_aarch64_reinterpretv4sfv4si (__a); -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vreinterpretq_f32_s64 (int64x2_t __a) -+{ -+ return (float32x4_t) __builtin_aarch64_reinterpretv4sfv2di (__a); -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vreinterpretq_f32_u8 (uint8x16_t __a) -+{ -+ return (float32x4_t) __builtin_aarch64_reinterpretv4sfv16qi ((int8x16_t) -+ __a); -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vreinterpretq_f32_u16 (uint16x8_t __a) -+{ -+ return (float32x4_t) __builtin_aarch64_reinterpretv4sfv8hi ((int16x8_t) -+ __a); -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vreinterpretq_f32_u32 (uint32x4_t __a) -+{ -+ return (float32x4_t) __builtin_aarch64_reinterpretv4sfv4si ((int32x4_t) -+ __a); -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vreinterpretq_f32_u64 (uint64x2_t __a) -+{ -+ return (float32x4_t) __builtin_aarch64_reinterpretv4sfv2di ((int64x2_t) -+ __a); -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vreinterpretq_f32_p8 (poly8x16_t __a) -+{ -+ return (float32x4_t) __builtin_aarch64_reinterpretv4sfv16qi ((int8x16_t) -+ __a); -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vreinterpretq_f32_p16 (poly16x8_t __a) -+{ -+ return (float32x4_t) __builtin_aarch64_reinterpretv4sfv8hi ((int16x8_t) -+ __a); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vreinterpret_s64_s8 (int8x8_t __a) -+{ -+ return (int64x1_t) __builtin_aarch64_reinterpretdiv8qi (__a); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vreinterpret_s64_s16 (int16x4_t __a) -+{ -+ return (int64x1_t) __builtin_aarch64_reinterpretdiv4hi (__a); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vreinterpret_s64_s32 (int32x2_t __a) -+{ -+ return (int64x1_t) __builtin_aarch64_reinterpretdiv2si (__a); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vreinterpret_s64_f32 (float32x2_t __a) -+{ -+ return (int64x1_t) __builtin_aarch64_reinterpretdiv2sf (__a); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vreinterpret_s64_u8 (uint8x8_t __a) -+{ -+ return (int64x1_t) __builtin_aarch64_reinterpretdiv8qi ((int8x8_t) __a); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vreinterpret_s64_u16 (uint16x4_t __a) -+{ -+ return (int64x1_t) __builtin_aarch64_reinterpretdiv4hi ((int16x4_t) __a); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vreinterpret_s64_u32 (uint32x2_t __a) -+{ -+ return (int64x1_t) __builtin_aarch64_reinterpretdiv2si ((int32x2_t) __a); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vreinterpret_s64_u64 (uint64x1_t __a) -+{ -+ return (int64x1_t) __builtin_aarch64_reinterpretdidi ((int64x1_t) __a); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vreinterpret_s64_p8 (poly8x8_t __a) -+{ -+ return (int64x1_t) __builtin_aarch64_reinterpretdiv8qi ((int8x8_t) __a); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vreinterpret_s64_p16 (poly16x4_t __a) -+{ -+ return (int64x1_t) __builtin_aarch64_reinterpretdiv4hi ((int16x4_t) __a); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vreinterpretq_s64_s8 (int8x16_t __a) -+{ -+ return (int64x2_t) __builtin_aarch64_reinterpretv2div16qi (__a); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vreinterpretq_s64_s16 (int16x8_t __a) -+{ -+ return (int64x2_t) __builtin_aarch64_reinterpretv2div8hi (__a); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vreinterpretq_s64_s32 (int32x4_t __a) -+{ -+ return (int64x2_t) __builtin_aarch64_reinterpretv2div4si (__a); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vreinterpretq_s64_f32 (float32x4_t __a) -+{ -+ return (int64x2_t) __builtin_aarch64_reinterpretv2div4sf (__a); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vreinterpretq_s64_u8 (uint8x16_t __a) -+{ -+ return (int64x2_t) __builtin_aarch64_reinterpretv2div16qi ((int8x16_t) __a); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vreinterpretq_s64_u16 (uint16x8_t __a) -+{ -+ return (int64x2_t) __builtin_aarch64_reinterpretv2div8hi ((int16x8_t) __a); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vreinterpretq_s64_u32 (uint32x4_t __a) -+{ -+ return (int64x2_t) __builtin_aarch64_reinterpretv2div4si ((int32x4_t) __a); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vreinterpretq_s64_u64 (uint64x2_t __a) -+{ -+ return (int64x2_t) __builtin_aarch64_reinterpretv2div2di ((int64x2_t) __a); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vreinterpretq_s64_p8 (poly8x16_t __a) -+{ -+ return (int64x2_t) __builtin_aarch64_reinterpretv2div16qi ((int8x16_t) __a); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vreinterpretq_s64_p16 (poly16x8_t __a) -+{ -+ return (int64x2_t) __builtin_aarch64_reinterpretv2div8hi ((int16x8_t) __a); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vreinterpret_u64_s8 (int8x8_t __a) -+{ -+ return (uint64x1_t) __builtin_aarch64_reinterpretdiv8qi (__a); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vreinterpret_u64_s16 (int16x4_t __a) -+{ -+ return (uint64x1_t) __builtin_aarch64_reinterpretdiv4hi (__a); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vreinterpret_u64_s32 (int32x2_t __a) -+{ -+ return (uint64x1_t) __builtin_aarch64_reinterpretdiv2si (__a); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vreinterpret_u64_s64 (int64x1_t __a) -+{ -+ return (uint64x1_t) __builtin_aarch64_reinterpretdidi (__a); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vreinterpret_u64_f32 (float32x2_t __a) -+{ -+ return (uint64x1_t) __builtin_aarch64_reinterpretdiv2sf (__a); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vreinterpret_u64_u8 (uint8x8_t __a) -+{ -+ return (uint64x1_t) __builtin_aarch64_reinterpretdiv8qi ((int8x8_t) __a); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vreinterpret_u64_u16 (uint16x4_t __a) -+{ -+ return (uint64x1_t) __builtin_aarch64_reinterpretdiv4hi ((int16x4_t) __a); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vreinterpret_u64_u32 (uint32x2_t __a) -+{ -+ return (uint64x1_t) __builtin_aarch64_reinterpretdiv2si ((int32x2_t) __a); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vreinterpret_u64_p8 (poly8x8_t __a) -+{ -+ return (uint64x1_t) __builtin_aarch64_reinterpretdiv8qi ((int8x8_t) __a); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vreinterpret_u64_p16 (poly16x4_t __a) -+{ -+ return (uint64x1_t) __builtin_aarch64_reinterpretdiv4hi ((int16x4_t) __a); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vreinterpretq_u64_s8 (int8x16_t __a) -+{ -+ return (uint64x2_t) __builtin_aarch64_reinterpretv2div16qi (__a); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vreinterpretq_u64_s16 (int16x8_t __a) -+{ -+ return (uint64x2_t) __builtin_aarch64_reinterpretv2div8hi (__a); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vreinterpretq_u64_s32 (int32x4_t __a) -+{ -+ return (uint64x2_t) __builtin_aarch64_reinterpretv2div4si (__a); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vreinterpretq_u64_s64 (int64x2_t __a) -+{ -+ return (uint64x2_t) __builtin_aarch64_reinterpretv2div2di (__a); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vreinterpretq_u64_f32 (float32x4_t __a) -+{ -+ return (uint64x2_t) __builtin_aarch64_reinterpretv2div4sf (__a); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vreinterpretq_u64_u8 (uint8x16_t __a) -+{ -+ return (uint64x2_t) __builtin_aarch64_reinterpretv2div16qi ((int8x16_t) -+ __a); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vreinterpretq_u64_u16 (uint16x8_t __a) -+{ -+ return (uint64x2_t) __builtin_aarch64_reinterpretv2div8hi ((int16x8_t) __a); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vreinterpretq_u64_u32 (uint32x4_t __a) -+{ -+ return (uint64x2_t) __builtin_aarch64_reinterpretv2div4si ((int32x4_t) __a); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vreinterpretq_u64_p8 (poly8x16_t __a) -+{ -+ return (uint64x2_t) __builtin_aarch64_reinterpretv2div16qi ((int8x16_t) -+ __a); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vreinterpretq_u64_p16 (poly16x8_t __a) -+{ -+ return (uint64x2_t) __builtin_aarch64_reinterpretv2div8hi ((int16x8_t) __a); -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vreinterpret_s8_s16 (int16x4_t __a) -+{ -+ return (int8x8_t) __builtin_aarch64_reinterpretv8qiv4hi (__a); -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vreinterpret_s8_s32 (int32x2_t __a) -+{ -+ return (int8x8_t) __builtin_aarch64_reinterpretv8qiv2si (__a); -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vreinterpret_s8_s64 (int64x1_t __a) -+{ -+ return (int8x8_t) __builtin_aarch64_reinterpretv8qidi (__a); -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vreinterpret_s8_f32 (float32x2_t __a) -+{ -+ return (int8x8_t) __builtin_aarch64_reinterpretv8qiv2sf (__a); -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vreinterpret_s8_u8 (uint8x8_t __a) -+{ -+ return (int8x8_t) __builtin_aarch64_reinterpretv8qiv8qi ((int8x8_t) __a); -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vreinterpret_s8_u16 (uint16x4_t __a) -+{ -+ return (int8x8_t) __builtin_aarch64_reinterpretv8qiv4hi ((int16x4_t) __a); -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vreinterpret_s8_u32 (uint32x2_t __a) -+{ -+ return (int8x8_t) __builtin_aarch64_reinterpretv8qiv2si ((int32x2_t) __a); -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vreinterpret_s8_u64 (uint64x1_t __a) -+{ -+ return (int8x8_t) __builtin_aarch64_reinterpretv8qidi ((int64x1_t) __a); -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vreinterpret_s8_p8 (poly8x8_t __a) -+{ -+ return (int8x8_t) __builtin_aarch64_reinterpretv8qiv8qi ((int8x8_t) __a); -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vreinterpret_s8_p16 (poly16x4_t __a) -+{ -+ return (int8x8_t) __builtin_aarch64_reinterpretv8qiv4hi ((int16x4_t) __a); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vreinterpretq_s8_s16 (int16x8_t __a) -+{ -+ return (int8x16_t) __builtin_aarch64_reinterpretv16qiv8hi (__a); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vreinterpretq_s8_s32 (int32x4_t __a) -+{ -+ return (int8x16_t) __builtin_aarch64_reinterpretv16qiv4si (__a); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vreinterpretq_s8_s64 (int64x2_t __a) -+{ -+ return (int8x16_t) __builtin_aarch64_reinterpretv16qiv2di (__a); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vreinterpretq_s8_f32 (float32x4_t __a) -+{ -+ return (int8x16_t) __builtin_aarch64_reinterpretv16qiv4sf (__a); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vreinterpretq_s8_u8 (uint8x16_t __a) -+{ -+ return (int8x16_t) __builtin_aarch64_reinterpretv16qiv16qi ((int8x16_t) -+ __a); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vreinterpretq_s8_u16 (uint16x8_t __a) -+{ -+ return (int8x16_t) __builtin_aarch64_reinterpretv16qiv8hi ((int16x8_t) __a); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vreinterpretq_s8_u32 (uint32x4_t __a) -+{ -+ return (int8x16_t) __builtin_aarch64_reinterpretv16qiv4si ((int32x4_t) __a); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vreinterpretq_s8_u64 (uint64x2_t __a) -+{ -+ return (int8x16_t) __builtin_aarch64_reinterpretv16qiv2di ((int64x2_t) __a); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vreinterpretq_s8_p8 (poly8x16_t __a) -+{ -+ return (int8x16_t) __builtin_aarch64_reinterpretv16qiv16qi ((int8x16_t) -+ __a); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vreinterpretq_s8_p16 (poly16x8_t __a) -+{ -+ return (int8x16_t) __builtin_aarch64_reinterpretv16qiv8hi ((int16x8_t) __a); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vreinterpret_s16_s8 (int8x8_t __a) -+{ -+ return (int16x4_t) __builtin_aarch64_reinterpretv4hiv8qi (__a); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vreinterpret_s16_s32 (int32x2_t __a) -+{ -+ return (int16x4_t) __builtin_aarch64_reinterpretv4hiv2si (__a); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vreinterpret_s16_s64 (int64x1_t __a) -+{ -+ return (int16x4_t) __builtin_aarch64_reinterpretv4hidi (__a); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vreinterpret_s16_f32 (float32x2_t __a) -+{ -+ return (int16x4_t) __builtin_aarch64_reinterpretv4hiv2sf (__a); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vreinterpret_s16_u8 (uint8x8_t __a) -+{ -+ return (int16x4_t) __builtin_aarch64_reinterpretv4hiv8qi ((int8x8_t) __a); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vreinterpret_s16_u16 (uint16x4_t __a) -+{ -+ return (int16x4_t) __builtin_aarch64_reinterpretv4hiv4hi ((int16x4_t) __a); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vreinterpret_s16_u32 (uint32x2_t __a) -+{ -+ return (int16x4_t) __builtin_aarch64_reinterpretv4hiv2si ((int32x2_t) __a); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vreinterpret_s16_u64 (uint64x1_t __a) -+{ -+ return (int16x4_t) __builtin_aarch64_reinterpretv4hidi ((int64x1_t) __a); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vreinterpret_s16_p8 (poly8x8_t __a) -+{ -+ return (int16x4_t) __builtin_aarch64_reinterpretv4hiv8qi ((int8x8_t) __a); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vreinterpret_s16_p16 (poly16x4_t __a) -+{ -+ return (int16x4_t) __builtin_aarch64_reinterpretv4hiv4hi ((int16x4_t) __a); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vreinterpretq_s16_s8 (int8x16_t __a) -+{ -+ return (int16x8_t) __builtin_aarch64_reinterpretv8hiv16qi (__a); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vreinterpretq_s16_s32 (int32x4_t __a) -+{ -+ return (int16x8_t) __builtin_aarch64_reinterpretv8hiv4si (__a); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vreinterpretq_s16_s64 (int64x2_t __a) -+{ -+ return (int16x8_t) __builtin_aarch64_reinterpretv8hiv2di (__a); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vreinterpretq_s16_f32 (float32x4_t __a) -+{ -+ return (int16x8_t) __builtin_aarch64_reinterpretv8hiv4sf (__a); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vreinterpretq_s16_u8 (uint8x16_t __a) -+{ -+ return (int16x8_t) __builtin_aarch64_reinterpretv8hiv16qi ((int8x16_t) __a); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vreinterpretq_s16_u16 (uint16x8_t __a) -+{ -+ return (int16x8_t) __builtin_aarch64_reinterpretv8hiv8hi ((int16x8_t) __a); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vreinterpretq_s16_u32 (uint32x4_t __a) -+{ -+ return (int16x8_t) __builtin_aarch64_reinterpretv8hiv4si ((int32x4_t) __a); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vreinterpretq_s16_u64 (uint64x2_t __a) -+{ -+ return (int16x8_t) __builtin_aarch64_reinterpretv8hiv2di ((int64x2_t) __a); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vreinterpretq_s16_p8 (poly8x16_t __a) -+{ -+ return (int16x8_t) __builtin_aarch64_reinterpretv8hiv16qi ((int8x16_t) __a); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vreinterpretq_s16_p16 (poly16x8_t __a) -+{ -+ return (int16x8_t) __builtin_aarch64_reinterpretv8hiv8hi ((int16x8_t) __a); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vreinterpret_s32_s8 (int8x8_t __a) -+{ -+ return (int32x2_t) __builtin_aarch64_reinterpretv2siv8qi (__a); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vreinterpret_s32_s16 (int16x4_t __a) -+{ -+ return (int32x2_t) __builtin_aarch64_reinterpretv2siv4hi (__a); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vreinterpret_s32_s64 (int64x1_t __a) -+{ -+ return (int32x2_t) __builtin_aarch64_reinterpretv2sidi (__a); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vreinterpret_s32_f32 (float32x2_t __a) -+{ -+ return (int32x2_t) __builtin_aarch64_reinterpretv2siv2sf (__a); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vreinterpret_s32_u8 (uint8x8_t __a) -+{ -+ return (int32x2_t) __builtin_aarch64_reinterpretv2siv8qi ((int8x8_t) __a); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vreinterpret_s32_u16 (uint16x4_t __a) -+{ -+ return (int32x2_t) __builtin_aarch64_reinterpretv2siv4hi ((int16x4_t) __a); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vreinterpret_s32_u32 (uint32x2_t __a) -+{ -+ return (int32x2_t) __builtin_aarch64_reinterpretv2siv2si ((int32x2_t) __a); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vreinterpret_s32_u64 (uint64x1_t __a) -+{ -+ return (int32x2_t) __builtin_aarch64_reinterpretv2sidi ((int64x1_t) __a); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vreinterpret_s32_p8 (poly8x8_t __a) -+{ -+ return (int32x2_t) __builtin_aarch64_reinterpretv2siv8qi ((int8x8_t) __a); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vreinterpret_s32_p16 (poly16x4_t __a) -+{ -+ return (int32x2_t) __builtin_aarch64_reinterpretv2siv4hi ((int16x4_t) __a); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vreinterpretq_s32_s8 (int8x16_t __a) -+{ -+ return (int32x4_t) __builtin_aarch64_reinterpretv4siv16qi (__a); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vreinterpretq_s32_s16 (int16x8_t __a) -+{ -+ return (int32x4_t) __builtin_aarch64_reinterpretv4siv8hi (__a); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vreinterpretq_s32_s64 (int64x2_t __a) -+{ -+ return (int32x4_t) __builtin_aarch64_reinterpretv4siv2di (__a); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vreinterpretq_s32_f32 (float32x4_t __a) -+{ -+ return (int32x4_t) __builtin_aarch64_reinterpretv4siv4sf (__a); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vreinterpretq_s32_u8 (uint8x16_t __a) -+{ -+ return (int32x4_t) __builtin_aarch64_reinterpretv4siv16qi ((int8x16_t) __a); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vreinterpretq_s32_u16 (uint16x8_t __a) -+{ -+ return (int32x4_t) __builtin_aarch64_reinterpretv4siv8hi ((int16x8_t) __a); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vreinterpretq_s32_u32 (uint32x4_t __a) -+{ -+ return (int32x4_t) __builtin_aarch64_reinterpretv4siv4si ((int32x4_t) __a); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vreinterpretq_s32_u64 (uint64x2_t __a) -+{ -+ return (int32x4_t) __builtin_aarch64_reinterpretv4siv2di ((int64x2_t) __a); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vreinterpretq_s32_p8 (poly8x16_t __a) -+{ -+ return (int32x4_t) __builtin_aarch64_reinterpretv4siv16qi ((int8x16_t) __a); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vreinterpretq_s32_p16 (poly16x8_t __a) -+{ -+ return (int32x4_t) __builtin_aarch64_reinterpretv4siv8hi ((int16x8_t) __a); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vreinterpret_u8_s8 (int8x8_t __a) -+{ -+ return (uint8x8_t) __builtin_aarch64_reinterpretv8qiv8qi (__a); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vreinterpret_u8_s16 (int16x4_t __a) -+{ -+ return (uint8x8_t) __builtin_aarch64_reinterpretv8qiv4hi (__a); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vreinterpret_u8_s32 (int32x2_t __a) -+{ -+ return (uint8x8_t) __builtin_aarch64_reinterpretv8qiv2si (__a); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vreinterpret_u8_s64 (int64x1_t __a) -+{ -+ return (uint8x8_t) __builtin_aarch64_reinterpretv8qidi (__a); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vreinterpret_u8_f32 (float32x2_t __a) -+{ -+ return (uint8x8_t) __builtin_aarch64_reinterpretv8qiv2sf (__a); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vreinterpret_u8_u16 (uint16x4_t __a) -+{ -+ return (uint8x8_t) __builtin_aarch64_reinterpretv8qiv4hi ((int16x4_t) __a); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vreinterpret_u8_u32 (uint32x2_t __a) -+{ -+ return (uint8x8_t) __builtin_aarch64_reinterpretv8qiv2si ((int32x2_t) __a); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vreinterpret_u8_u64 (uint64x1_t __a) -+{ -+ return (uint8x8_t) __builtin_aarch64_reinterpretv8qidi ((int64x1_t) __a); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vreinterpret_u8_p8 (poly8x8_t __a) -+{ -+ return (uint8x8_t) __builtin_aarch64_reinterpretv8qiv8qi ((int8x8_t) __a); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vreinterpret_u8_p16 (poly16x4_t __a) -+{ -+ return (uint8x8_t) __builtin_aarch64_reinterpretv8qiv4hi ((int16x4_t) __a); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vreinterpretq_u8_s8 (int8x16_t __a) -+{ -+ return (uint8x16_t) __builtin_aarch64_reinterpretv16qiv16qi (__a); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vreinterpretq_u8_s16 (int16x8_t __a) -+{ -+ return (uint8x16_t) __builtin_aarch64_reinterpretv16qiv8hi (__a); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vreinterpretq_u8_s32 (int32x4_t __a) -+{ -+ return (uint8x16_t) __builtin_aarch64_reinterpretv16qiv4si (__a); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vreinterpretq_u8_s64 (int64x2_t __a) -+{ -+ return (uint8x16_t) __builtin_aarch64_reinterpretv16qiv2di (__a); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vreinterpretq_u8_f32 (float32x4_t __a) -+{ -+ return (uint8x16_t) __builtin_aarch64_reinterpretv16qiv4sf (__a); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vreinterpretq_u8_u16 (uint16x8_t __a) -+{ -+ return (uint8x16_t) __builtin_aarch64_reinterpretv16qiv8hi ((int16x8_t) -+ __a); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vreinterpretq_u8_u32 (uint32x4_t __a) -+{ -+ return (uint8x16_t) __builtin_aarch64_reinterpretv16qiv4si ((int32x4_t) -+ __a); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vreinterpretq_u8_u64 (uint64x2_t __a) -+{ -+ return (uint8x16_t) __builtin_aarch64_reinterpretv16qiv2di ((int64x2_t) -+ __a); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vreinterpretq_u8_p8 (poly8x16_t __a) -+{ -+ return (uint8x16_t) __builtin_aarch64_reinterpretv16qiv16qi ((int8x16_t) -+ __a); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vreinterpretq_u8_p16 (poly16x8_t __a) -+{ -+ return (uint8x16_t) __builtin_aarch64_reinterpretv16qiv8hi ((int16x8_t) -+ __a); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vreinterpret_u16_s8 (int8x8_t __a) -+{ -+ return (uint16x4_t) __builtin_aarch64_reinterpretv4hiv8qi (__a); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vreinterpret_u16_s16 (int16x4_t __a) -+{ -+ return (uint16x4_t) __builtin_aarch64_reinterpretv4hiv4hi (__a); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vreinterpret_u16_s32 (int32x2_t __a) -+{ -+ return (uint16x4_t) __builtin_aarch64_reinterpretv4hiv2si (__a); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vreinterpret_u16_s64 (int64x1_t __a) -+{ -+ return (uint16x4_t) __builtin_aarch64_reinterpretv4hidi (__a); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vreinterpret_u16_f32 (float32x2_t __a) -+{ -+ return (uint16x4_t) __builtin_aarch64_reinterpretv4hiv2sf (__a); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vreinterpret_u16_u8 (uint8x8_t __a) -+{ -+ return (uint16x4_t) __builtin_aarch64_reinterpretv4hiv8qi ((int8x8_t) __a); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vreinterpret_u16_u32 (uint32x2_t __a) -+{ -+ return (uint16x4_t) __builtin_aarch64_reinterpretv4hiv2si ((int32x2_t) __a); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vreinterpret_u16_u64 (uint64x1_t __a) -+{ -+ return (uint16x4_t) __builtin_aarch64_reinterpretv4hidi ((int64x1_t) __a); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vreinterpret_u16_p8 (poly8x8_t __a) -+{ -+ return (uint16x4_t) __builtin_aarch64_reinterpretv4hiv8qi ((int8x8_t) __a); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vreinterpret_u16_p16 (poly16x4_t __a) -+{ -+ return (uint16x4_t) __builtin_aarch64_reinterpretv4hiv4hi ((int16x4_t) __a); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vreinterpretq_u16_s8 (int8x16_t __a) -+{ -+ return (uint16x8_t) __builtin_aarch64_reinterpretv8hiv16qi (__a); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vreinterpretq_u16_s16 (int16x8_t __a) -+{ -+ return (uint16x8_t) __builtin_aarch64_reinterpretv8hiv8hi (__a); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vreinterpretq_u16_s32 (int32x4_t __a) -+{ -+ return (uint16x8_t) __builtin_aarch64_reinterpretv8hiv4si (__a); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vreinterpretq_u16_s64 (int64x2_t __a) -+{ -+ return (uint16x8_t) __builtin_aarch64_reinterpretv8hiv2di (__a); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vreinterpretq_u16_f32 (float32x4_t __a) -+{ -+ return (uint16x8_t) __builtin_aarch64_reinterpretv8hiv4sf (__a); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vreinterpretq_u16_u8 (uint8x16_t __a) -+{ -+ return (uint16x8_t) __builtin_aarch64_reinterpretv8hiv16qi ((int8x16_t) -+ __a); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vreinterpretq_u16_u32 (uint32x4_t __a) -+{ -+ return (uint16x8_t) __builtin_aarch64_reinterpretv8hiv4si ((int32x4_t) __a); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vreinterpretq_u16_u64 (uint64x2_t __a) -+{ -+ return (uint16x8_t) __builtin_aarch64_reinterpretv8hiv2di ((int64x2_t) __a); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vreinterpretq_u16_p8 (poly8x16_t __a) -+{ -+ return (uint16x8_t) __builtin_aarch64_reinterpretv8hiv16qi ((int8x16_t) -+ __a); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vreinterpretq_u16_p16 (poly16x8_t __a) -+{ -+ return (uint16x8_t) __builtin_aarch64_reinterpretv8hiv8hi ((int16x8_t) __a); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vreinterpret_u32_s8 (int8x8_t __a) -+{ -+ return (uint32x2_t) __builtin_aarch64_reinterpretv2siv8qi (__a); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vreinterpret_u32_s16 (int16x4_t __a) -+{ -+ return (uint32x2_t) __builtin_aarch64_reinterpretv2siv4hi (__a); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vreinterpret_u32_s32 (int32x2_t __a) -+{ -+ return (uint32x2_t) __builtin_aarch64_reinterpretv2siv2si (__a); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vreinterpret_u32_s64 (int64x1_t __a) -+{ -+ return (uint32x2_t) __builtin_aarch64_reinterpretv2sidi (__a); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vreinterpret_u32_f32 (float32x2_t __a) -+{ -+ return (uint32x2_t) __builtin_aarch64_reinterpretv2siv2sf (__a); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vreinterpret_u32_u8 (uint8x8_t __a) -+{ -+ return (uint32x2_t) __builtin_aarch64_reinterpretv2siv8qi ((int8x8_t) __a); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vreinterpret_u32_u16 (uint16x4_t __a) -+{ -+ return (uint32x2_t) __builtin_aarch64_reinterpretv2siv4hi ((int16x4_t) __a); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vreinterpret_u32_u64 (uint64x1_t __a) -+{ -+ return (uint32x2_t) __builtin_aarch64_reinterpretv2sidi ((int64x1_t) __a); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vreinterpret_u32_p8 (poly8x8_t __a) -+{ -+ return (uint32x2_t) __builtin_aarch64_reinterpretv2siv8qi ((int8x8_t) __a); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vreinterpret_u32_p16 (poly16x4_t __a) -+{ -+ return (uint32x2_t) __builtin_aarch64_reinterpretv2siv4hi ((int16x4_t) __a); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vreinterpretq_u32_s8 (int8x16_t __a) -+{ -+ return (uint32x4_t) __builtin_aarch64_reinterpretv4siv16qi (__a); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vreinterpretq_u32_s16 (int16x8_t __a) -+{ -+ return (uint32x4_t) __builtin_aarch64_reinterpretv4siv8hi (__a); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vreinterpretq_u32_s32 (int32x4_t __a) -+{ -+ return (uint32x4_t) __builtin_aarch64_reinterpretv4siv4si (__a); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vreinterpretq_u32_s64 (int64x2_t __a) -+{ -+ return (uint32x4_t) __builtin_aarch64_reinterpretv4siv2di (__a); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vreinterpretq_u32_f32 (float32x4_t __a) -+{ -+ return (uint32x4_t) __builtin_aarch64_reinterpretv4siv4sf (__a); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vreinterpretq_u32_u8 (uint8x16_t __a) -+{ -+ return (uint32x4_t) __builtin_aarch64_reinterpretv4siv16qi ((int8x16_t) -+ __a); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vreinterpretq_u32_u16 (uint16x8_t __a) -+{ -+ return (uint32x4_t) __builtin_aarch64_reinterpretv4siv8hi ((int16x8_t) __a); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vreinterpretq_u32_u64 (uint64x2_t __a) -+{ -+ return (uint32x4_t) __builtin_aarch64_reinterpretv4siv2di ((int64x2_t) __a); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vreinterpretq_u32_p8 (poly8x16_t __a) -+{ -+ return (uint32x4_t) __builtin_aarch64_reinterpretv4siv16qi ((int8x16_t) -+ __a); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vreinterpretq_u32_p16 (poly16x8_t __a) -+{ -+ return (uint32x4_t) __builtin_aarch64_reinterpretv4siv8hi ((int16x8_t) __a); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vcombine_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return (int8x16_t) __builtin_aarch64_combinev8qi (__a, __b); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vcombine_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return (int16x8_t) __builtin_aarch64_combinev4hi (__a, __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vcombine_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return (int32x4_t) __builtin_aarch64_combinev2si (__a, __b); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vcombine_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return (int64x2_t) __builtin_aarch64_combinedi (__a, __b); -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vcombine_f32 (float32x2_t __a, float32x2_t __b) -+{ -+ return (float32x4_t) __builtin_aarch64_combinev2sf (__a, __b); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vcombine_u8 (uint8x8_t __a, uint8x8_t __b) -+{ -+ return (uint8x16_t) __builtin_aarch64_combinev8qi ((int8x8_t) __a, -+ (int8x8_t) __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vcombine_u16 (uint16x4_t __a, uint16x4_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_combinev4hi ((int16x4_t) __a, -+ (int16x4_t) __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vcombine_u32 (uint32x2_t __a, uint32x2_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_combinev2si ((int32x2_t) __a, -+ (int32x2_t) __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vcombine_u64 (uint64x1_t __a, uint64x1_t __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_combinedi ((int64x1_t) __a, -+ (int64x1_t) __b); -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vcombine_f64 (float64x1_t __a, float64x1_t __b) -+{ -+ return (float64x2_t) __builtin_aarch64_combinedf (__a, __b); -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vcombine_p8 (poly8x8_t __a, poly8x8_t __b) -+{ -+ return (poly8x16_t) __builtin_aarch64_combinev8qi ((int8x8_t) __a, -+ (int8x8_t) __b); -+} -+ -+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) -+vcombine_p16 (poly16x4_t __a, poly16x4_t __b) -+{ -+ return (poly16x8_t) __builtin_aarch64_combinev4hi ((int16x4_t) __a, -+ (int16x4_t) __b); -+} -+ -+/* Start of temporary inline asm implementations. */ -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vaba_s8 (int8x8_t a, int8x8_t b, int8x8_t c) -+{ -+ int8x8_t result; -+ __asm__ ("saba %0.8b,%2.8b,%3.8b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vaba_s16 (int16x4_t a, int16x4_t b, int16x4_t c) -+{ -+ int16x4_t result; -+ __asm__ ("saba %0.4h,%2.4h,%3.4h" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vaba_s32 (int32x2_t a, int32x2_t b, int32x2_t c) -+{ -+ int32x2_t result; -+ __asm__ ("saba %0.2s,%2.2s,%3.2s" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vaba_u8 (uint8x8_t a, uint8x8_t b, uint8x8_t c) -+{ -+ uint8x8_t result; -+ __asm__ ("uaba %0.8b,%2.8b,%3.8b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vaba_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t c) -+{ -+ uint16x4_t result; -+ __asm__ ("uaba %0.4h,%2.4h,%3.4h" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vaba_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t c) -+{ -+ uint32x2_t result; -+ __asm__ ("uaba %0.2s,%2.2s,%3.2s" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vabal_high_s8 (int16x8_t a, int8x16_t b, int8x16_t c) -+{ -+ int16x8_t result; -+ __asm__ ("sabal2 %0.8h,%2.16b,%3.16b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vabal_high_s16 (int32x4_t a, int16x8_t b, int16x8_t c) -+{ -+ int32x4_t result; -+ __asm__ ("sabal2 %0.4s,%2.8h,%3.8h" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vabal_high_s32 (int64x2_t a, int32x4_t b, int32x4_t c) -+{ -+ int64x2_t result; -+ __asm__ ("sabal2 %0.2d,%2.4s,%3.4s" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vabal_high_u8 (uint16x8_t a, uint8x16_t b, uint8x16_t c) -+{ -+ uint16x8_t result; -+ __asm__ ("uabal2 %0.8h,%2.16b,%3.16b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vabal_high_u16 (uint32x4_t a, uint16x8_t b, uint16x8_t c) -+{ -+ uint32x4_t result; -+ __asm__ ("uabal2 %0.4s,%2.8h,%3.8h" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vabal_high_u32 (uint64x2_t a, uint32x4_t b, uint32x4_t c) -+{ -+ uint64x2_t result; -+ __asm__ ("uabal2 %0.2d,%2.4s,%3.4s" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vabal_s8 (int16x8_t a, int8x8_t b, int8x8_t c) -+{ -+ int16x8_t result; -+ __asm__ ("sabal %0.8h,%2.8b,%3.8b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vabal_s16 (int32x4_t a, int16x4_t b, int16x4_t c) -+{ -+ int32x4_t result; -+ __asm__ ("sabal %0.4s,%2.4h,%3.4h" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vabal_s32 (int64x2_t a, int32x2_t b, int32x2_t c) -+{ -+ int64x2_t result; -+ __asm__ ("sabal %0.2d,%2.2s,%3.2s" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vabal_u8 (uint16x8_t a, uint8x8_t b, uint8x8_t c) -+{ -+ uint16x8_t result; -+ __asm__ ("uabal %0.8h,%2.8b,%3.8b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vabal_u16 (uint32x4_t a, uint16x4_t b, uint16x4_t c) -+{ -+ uint32x4_t result; -+ __asm__ ("uabal %0.4s,%2.4h,%3.4h" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vabal_u32 (uint64x2_t a, uint32x2_t b, uint32x2_t c) -+{ -+ uint64x2_t result; -+ __asm__ ("uabal %0.2d,%2.2s,%3.2s" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vabaq_s8 (int8x16_t a, int8x16_t b, int8x16_t c) -+{ -+ int8x16_t result; -+ __asm__ ("saba %0.16b,%2.16b,%3.16b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vabaq_s16 (int16x8_t a, int16x8_t b, int16x8_t c) -+{ -+ int16x8_t result; -+ __asm__ ("saba %0.8h,%2.8h,%3.8h" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vabaq_s32 (int32x4_t a, int32x4_t b, int32x4_t c) -+{ -+ int32x4_t result; -+ __asm__ ("saba %0.4s,%2.4s,%3.4s" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vabaq_u8 (uint8x16_t a, uint8x16_t b, uint8x16_t c) -+{ -+ uint8x16_t result; -+ __asm__ ("uaba %0.16b,%2.16b,%3.16b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vabaq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c) -+{ -+ uint16x8_t result; -+ __asm__ ("uaba %0.8h,%2.8h,%3.8h" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vabaq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c) -+{ -+ uint32x4_t result; -+ __asm__ ("uaba %0.4s,%2.4s,%3.4s" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vabd_f32 (float32x2_t a, float32x2_t b) -+{ -+ float32x2_t result; -+ __asm__ ("fabd %0.2s, %1.2s, %2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vabd_s8 (int8x8_t a, int8x8_t b) -+{ -+ int8x8_t result; -+ __asm__ ("sabd %0.8b, %1.8b, %2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vabd_s16 (int16x4_t a, int16x4_t b) -+{ -+ int16x4_t result; -+ __asm__ ("sabd %0.4h, %1.4h, %2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vabd_s32 (int32x2_t a, int32x2_t b) -+{ -+ int32x2_t result; -+ __asm__ ("sabd %0.2s, %1.2s, %2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vabd_u8 (uint8x8_t a, uint8x8_t b) -+{ -+ uint8x8_t result; -+ __asm__ ("uabd %0.8b, %1.8b, %2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vabd_u16 (uint16x4_t a, uint16x4_t b) -+{ -+ uint16x4_t result; -+ __asm__ ("uabd %0.4h, %1.4h, %2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vabd_u32 (uint32x2_t a, uint32x2_t b) -+{ -+ uint32x2_t result; -+ __asm__ ("uabd %0.2s, %1.2s, %2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -+vabdd_f64 (float64_t a, float64_t b) -+{ -+ float64_t result; -+ __asm__ ("fabd %d0, %d1, %d2" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vabdl_high_s8 (int8x16_t a, int8x16_t b) -+{ -+ int16x8_t result; -+ __asm__ ("sabdl2 %0.8h,%1.16b,%2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vabdl_high_s16 (int16x8_t a, int16x8_t b) -+{ -+ int32x4_t result; -+ __asm__ ("sabdl2 %0.4s,%1.8h,%2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vabdl_high_s32 (int32x4_t a, int32x4_t b) -+{ -+ int64x2_t result; -+ __asm__ ("sabdl2 %0.2d,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vabdl_high_u8 (uint8x16_t a, uint8x16_t b) -+{ -+ uint16x8_t result; -+ __asm__ ("uabdl2 %0.8h,%1.16b,%2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vabdl_high_u16 (uint16x8_t a, uint16x8_t b) -+{ -+ uint32x4_t result; -+ __asm__ ("uabdl2 %0.4s,%1.8h,%2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vabdl_high_u32 (uint32x4_t a, uint32x4_t b) -+{ -+ uint64x2_t result; -+ __asm__ ("uabdl2 %0.2d,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vabdl_s8 (int8x8_t a, int8x8_t b) -+{ -+ int16x8_t result; -+ __asm__ ("sabdl %0.8h, %1.8b, %2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vabdl_s16 (int16x4_t a, int16x4_t b) -+{ -+ int32x4_t result; -+ __asm__ ("sabdl %0.4s, %1.4h, %2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vabdl_s32 (int32x2_t a, int32x2_t b) -+{ -+ int64x2_t result; -+ __asm__ ("sabdl %0.2d, %1.2s, %2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vabdl_u8 (uint8x8_t a, uint8x8_t b) -+{ -+ uint16x8_t result; -+ __asm__ ("uabdl %0.8h, %1.8b, %2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vabdl_u16 (uint16x4_t a, uint16x4_t b) -+{ -+ uint32x4_t result; -+ __asm__ ("uabdl %0.4s, %1.4h, %2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vabdl_u32 (uint32x2_t a, uint32x2_t b) -+{ -+ uint64x2_t result; -+ __asm__ ("uabdl %0.2d, %1.2s, %2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vabdq_f32 (float32x4_t a, float32x4_t b) -+{ -+ float32x4_t result; -+ __asm__ ("fabd %0.4s, %1.4s, %2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vabdq_f64 (float64x2_t a, float64x2_t b) -+{ -+ float64x2_t result; -+ __asm__ ("fabd %0.2d, %1.2d, %2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vabdq_s8 (int8x16_t a, int8x16_t b) -+{ -+ int8x16_t result; -+ __asm__ ("sabd %0.16b, %1.16b, %2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vabdq_s16 (int16x8_t a, int16x8_t b) -+{ -+ int16x8_t result; -+ __asm__ ("sabd %0.8h, %1.8h, %2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vabdq_s32 (int32x4_t a, int32x4_t b) -+{ -+ int32x4_t result; -+ __asm__ ("sabd %0.4s, %1.4s, %2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vabdq_u8 (uint8x16_t a, uint8x16_t b) -+{ -+ uint8x16_t result; -+ __asm__ ("uabd %0.16b, %1.16b, %2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vabdq_u16 (uint16x8_t a, uint16x8_t b) -+{ -+ uint16x8_t result; -+ __asm__ ("uabd %0.8h, %1.8h, %2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vabdq_u32 (uint32x4_t a, uint32x4_t b) -+{ -+ uint32x4_t result; -+ __asm__ ("uabd %0.4s, %1.4s, %2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vabds_f32 (float32_t a, float32_t b) -+{ -+ float32_t result; -+ __asm__ ("fabd %s0, %s1, %s2" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vabs_f32 (float32x2_t a) -+{ -+ float32x2_t result; -+ __asm__ ("fabs %0.2s,%1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vabs_s8 (int8x8_t a) -+{ -+ int8x8_t result; -+ __asm__ ("abs %0.8b,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vabs_s16 (int16x4_t a) -+{ -+ int16x4_t result; -+ __asm__ ("abs %0.4h,%1.4h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vabs_s32 (int32x2_t a) -+{ -+ int32x2_t result; -+ __asm__ ("abs %0.2s,%1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vabsq_f32 (float32x4_t a) -+{ -+ float32x4_t result; -+ __asm__ ("fabs %0.4s,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vabsq_f64 (float64x2_t a) -+{ -+ float64x2_t result; -+ __asm__ ("fabs %0.2d,%1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vabsq_s8 (int8x16_t a) -+{ -+ int8x16_t result; -+ __asm__ ("abs %0.16b,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vabsq_s16 (int16x8_t a) -+{ -+ int16x8_t result; -+ __asm__ ("abs %0.8h,%1.8h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vabsq_s32 (int32x4_t a) -+{ -+ int32x4_t result; -+ __asm__ ("abs %0.4s,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vabsq_s64 (int64x2_t a) -+{ -+ int64x2_t result; -+ __asm__ ("abs %0.2d,%1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -+vacged_f64 (float64_t a, float64_t b) -+{ -+ float64_t result; -+ __asm__ ("facge %d0,%d1,%d2" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vacges_f32 (float32_t a, float32_t b) -+{ -+ float32_t result; -+ __asm__ ("facge %s0,%s1,%s2" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -+vacgtd_f64 (float64_t a, float64_t b) -+{ -+ float64_t result; -+ __asm__ ("facgt %d0,%d1,%d2" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vacgts_f32 (float32_t a, float32_t b) -+{ -+ float32_t result; -+ __asm__ ("facgt %s0,%s1,%s2" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16_t __attribute__ ((__always_inline__)) -+vaddlv_s8 (int8x8_t a) -+{ -+ int16_t result; -+ __asm__ ("saddlv %h0,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32_t __attribute__ ((__always_inline__)) -+vaddlv_s16 (int16x4_t a) -+{ -+ int32_t result; -+ __asm__ ("saddlv %s0,%1.4h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) -+vaddlv_u8 (uint8x8_t a) -+{ -+ uint16_t result; -+ __asm__ ("uaddlv %h0,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) -+vaddlv_u16 (uint16x4_t a) -+{ -+ uint32_t result; -+ __asm__ ("uaddlv %s0,%1.4h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16_t __attribute__ ((__always_inline__)) -+vaddlvq_s8 (int8x16_t a) -+{ -+ int16_t result; -+ __asm__ ("saddlv %h0,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32_t __attribute__ ((__always_inline__)) -+vaddlvq_s16 (int16x8_t a) -+{ -+ int32_t result; -+ __asm__ ("saddlv %s0,%1.8h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64_t __attribute__ ((__always_inline__)) -+vaddlvq_s32 (int32x4_t a) -+{ -+ int64_t result; -+ __asm__ ("saddlv %d0,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) -+vaddlvq_u8 (uint8x16_t a) -+{ -+ uint16_t result; -+ __asm__ ("uaddlv %h0,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) -+vaddlvq_u16 (uint16x8_t a) -+{ -+ uint32_t result; -+ __asm__ ("uaddlv %s0,%1.8h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64_t __attribute__ ((__always_inline__)) -+vaddlvq_u32 (uint32x4_t a) -+{ -+ uint64_t result; -+ __asm__ ("uaddlv %d0,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8_t __attribute__ ((__always_inline__)) -+vaddv_s8 (int8x8_t a) -+{ -+ int8_t result; -+ __asm__ ("addv %b0,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16_t __attribute__ ((__always_inline__)) -+vaddv_s16 (int16x4_t a) -+{ -+ int16_t result; -+ __asm__ ("addv %h0,%1.4h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) -+vaddv_u8 (uint8x8_t a) -+{ -+ uint8_t result; -+ __asm__ ("addv %b0,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) -+vaddv_u16 (uint16x4_t a) -+{ -+ uint16_t result; -+ __asm__ ("addv %h0,%1.4h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8_t __attribute__ ((__always_inline__)) -+vaddvq_s8 (int8x16_t a) -+{ -+ int8_t result; -+ __asm__ ("addv %b0,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16_t __attribute__ ((__always_inline__)) -+vaddvq_s16 (int16x8_t a) -+{ -+ int16_t result; -+ __asm__ ("addv %h0,%1.8h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32_t __attribute__ ((__always_inline__)) -+vaddvq_s32 (int32x4_t a) -+{ -+ int32_t result; -+ __asm__ ("addv %s0,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) -+vaddvq_u8 (uint8x16_t a) -+{ -+ uint8_t result; -+ __asm__ ("addv %b0,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) -+vaddvq_u16 (uint16x8_t a) -+{ -+ uint16_t result; -+ __asm__ ("addv %h0,%1.8h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) -+vaddvq_u32 (uint32x4_t a) -+{ -+ uint32_t result; -+ __asm__ ("addv %s0,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vbsl_f32 (uint32x2_t a, float32x2_t b, float32x2_t c) -+{ -+ float32x2_t result; -+ __asm__ ("bsl %0.8b, %2.8b, %3.8b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vbsl_p8 (uint8x8_t a, poly8x8_t b, poly8x8_t c) -+{ -+ poly8x8_t result; -+ __asm__ ("bsl %0.8b, %2.8b, %3.8b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) -+vbsl_p16 (uint16x4_t a, poly16x4_t b, poly16x4_t c) -+{ -+ poly16x4_t result; -+ __asm__ ("bsl %0.8b, %2.8b, %3.8b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vbsl_s8 (uint8x8_t a, int8x8_t b, int8x8_t c) -+{ -+ int8x8_t result; -+ __asm__ ("bsl %0.8b, %2.8b, %3.8b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vbsl_s16 (uint16x4_t a, int16x4_t b, int16x4_t c) -+{ -+ int16x4_t result; -+ __asm__ ("bsl %0.8b, %2.8b, %3.8b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vbsl_s32 (uint32x2_t a, int32x2_t b, int32x2_t c) -+{ -+ int32x2_t result; -+ __asm__ ("bsl %0.8b, %2.8b, %3.8b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vbsl_s64 (uint64x1_t a, int64x1_t b, int64x1_t c) -+{ -+ int64x1_t result; -+ __asm__ ("bsl %0.8b, %2.8b, %3.8b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vbsl_u8 (uint8x8_t a, uint8x8_t b, uint8x8_t c) -+{ -+ uint8x8_t result; -+ __asm__ ("bsl %0.8b, %2.8b, %3.8b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vbsl_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t c) -+{ -+ uint16x4_t result; -+ __asm__ ("bsl %0.8b, %2.8b, %3.8b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vbsl_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t c) -+{ -+ uint32x2_t result; -+ __asm__ ("bsl %0.8b, %2.8b, %3.8b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vbsl_u64 (uint64x1_t a, uint64x1_t b, uint64x1_t c) -+{ -+ uint64x1_t result; -+ __asm__ ("bsl %0.8b, %2.8b, %3.8b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vbslq_f32 (uint32x4_t a, float32x4_t b, float32x4_t c) -+{ -+ float32x4_t result; -+ __asm__ ("bsl %0.16b, %2.16b, %3.16b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vbslq_f64 (float64x2_t a, float64x2_t b, float64x2_t c) -+{ -+ float64x2_t result; -+ __asm__ ("bsl %0.16b, %2.16b, %3.16b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vbslq_p8 (uint8x16_t a, poly8x16_t b, poly8x16_t c) -+{ -+ poly8x16_t result; -+ __asm__ ("bsl %0.16b, %2.16b, %3.16b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) -+vbslq_p16 (uint16x8_t a, poly16x8_t b, poly16x8_t c) -+{ -+ poly16x8_t result; -+ __asm__ ("bsl %0.16b, %2.16b, %3.16b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vbslq_s8 (uint8x16_t a, int8x16_t b, int8x16_t c) -+{ -+ int8x16_t result; -+ __asm__ ("bsl %0.16b, %2.16b, %3.16b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vbslq_s16 (uint16x8_t a, int16x8_t b, int16x8_t c) -+{ -+ int16x8_t result; -+ __asm__ ("bsl %0.16b, %2.16b, %3.16b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vbslq_s32 (uint32x4_t a, int32x4_t b, int32x4_t c) -+{ -+ int32x4_t result; -+ __asm__ ("bsl %0.16b, %2.16b, %3.16b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vbslq_s64 (uint64x2_t a, int64x2_t b, int64x2_t c) -+{ -+ int64x2_t result; -+ __asm__ ("bsl %0.16b, %2.16b, %3.16b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vbslq_u8 (uint8x16_t a, uint8x16_t b, uint8x16_t c) -+{ -+ uint8x16_t result; -+ __asm__ ("bsl %0.16b, %2.16b, %3.16b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vbslq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c) -+{ -+ uint16x8_t result; -+ __asm__ ("bsl %0.16b, %2.16b, %3.16b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vbslq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c) -+{ -+ uint32x4_t result; -+ __asm__ ("bsl %0.16b, %2.16b, %3.16b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vbslq_u64 (uint64x2_t a, uint64x2_t b, uint64x2_t c) -+{ -+ uint64x2_t result; -+ __asm__ ("bsl %0.16b, %2.16b, %3.16b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vcage_f32 (float32x2_t a, float32x2_t b) -+{ -+ uint32x2_t result; -+ __asm__ ("facge %0.2s, %1.2s, %2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vcageq_f32 (float32x4_t a, float32x4_t b) -+{ -+ uint32x4_t result; -+ __asm__ ("facge %0.4s, %1.4s, %2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vcageq_f64 (float64x2_t a, float64x2_t b) -+{ -+ uint64x2_t result; -+ __asm__ ("facge %0.2d, %1.2d, %2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vcagt_f32 (float32x2_t a, float32x2_t b) -+{ -+ uint32x2_t result; -+ __asm__ ("facgt %0.2s, %1.2s, %2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vcagtq_f32 (float32x4_t a, float32x4_t b) -+{ -+ uint32x4_t result; -+ __asm__ ("facgt %0.4s, %1.4s, %2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vcagtq_f64 (float64x2_t a, float64x2_t b) -+{ -+ uint64x2_t result; -+ __asm__ ("facgt %0.2d, %1.2d, %2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vcale_f32 (float32x2_t a, float32x2_t b) -+{ -+ uint32x2_t result; -+ __asm__ ("facge %0.2s, %2.2s, %1.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vcaleq_f32 (float32x4_t a, float32x4_t b) -+{ -+ uint32x4_t result; -+ __asm__ ("facge %0.4s, %2.4s, %1.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vcaleq_f64 (float64x2_t a, float64x2_t b) -+{ -+ uint64x2_t result; -+ __asm__ ("facge %0.2d, %2.2d, %1.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vcalt_f32 (float32x2_t a, float32x2_t b) -+{ -+ uint32x2_t result; -+ __asm__ ("facgt %0.2s, %2.2s, %1.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vcaltq_f32 (float32x4_t a, float32x4_t b) -+{ -+ uint32x4_t result; -+ __asm__ ("facgt %0.4s, %2.4s, %1.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vcaltq_f64 (float64x2_t a, float64x2_t b) -+{ -+ uint64x2_t result; -+ __asm__ ("facgt %0.2d, %2.2d, %1.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vceq_f32 (float32x2_t a, float32x2_t b) -+{ -+ uint32x2_t result; -+ __asm__ ("fcmeq %0.2s, %1.2s, %2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vceq_f64 (float64x1_t a, float64x1_t b) -+{ -+ uint64x1_t result; -+ __asm__ ("fcmeq %d0, %d1, %d2" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -+vceqd_f64 (float64_t a, float64_t b) -+{ -+ float64_t result; -+ __asm__ ("fcmeq %d0,%d1,%d2" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vceqq_f32 (float32x4_t a, float32x4_t b) -+{ -+ uint32x4_t result; -+ __asm__ ("fcmeq %0.4s, %1.4s, %2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vceqq_f64 (float64x2_t a, float64x2_t b) -+{ -+ uint64x2_t result; -+ __asm__ ("fcmeq %0.2d, %1.2d, %2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vceqs_f32 (float32_t a, float32_t b) -+{ -+ float32_t result; -+ __asm__ ("fcmeq %s0,%s1,%s2" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -+vceqzd_f64 (float64_t a) -+{ -+ float64_t result; -+ __asm__ ("fcmeq %d0,%d1,#0" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vceqzs_f32 (float32_t a) -+{ -+ float32_t result; -+ __asm__ ("fcmeq %s0,%s1,#0" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vcge_f32 (float32x2_t a, float32x2_t b) -+{ -+ uint32x2_t result; -+ __asm__ ("fcmge %0.2s, %1.2s, %2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vcge_f64 (float64x1_t a, float64x1_t b) -+{ -+ uint64x1_t result; -+ __asm__ ("fcmge %d0, %d1, %d2" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vcgeq_f32 (float32x4_t a, float32x4_t b) -+{ -+ uint32x4_t result; -+ __asm__ ("fcmge %0.4s, %1.4s, %2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vcgeq_f64 (float64x2_t a, float64x2_t b) -+{ -+ uint64x2_t result; -+ __asm__ ("fcmge %0.2d, %1.2d, %2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vcgt_f32 (float32x2_t a, float32x2_t b) -+{ -+ uint32x2_t result; -+ __asm__ ("fcmgt %0.2s, %1.2s, %2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vcgt_f64 (float64x1_t a, float64x1_t b) -+{ -+ uint64x1_t result; -+ __asm__ ("fcmgt %d0, %d1, %d2" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vcgtq_f32 (float32x4_t a, float32x4_t b) -+{ -+ uint32x4_t result; -+ __asm__ ("fcmgt %0.4s, %1.4s, %2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vcgtq_f64 (float64x2_t a, float64x2_t b) -+{ -+ uint64x2_t result; -+ __asm__ ("fcmgt %0.2d, %1.2d, %2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vcle_f32 (float32x2_t a, float32x2_t b) -+{ -+ uint32x2_t result; -+ __asm__ ("fcmge %0.2s, %2.2s, %1.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vcle_f64 (float64x1_t a, float64x1_t b) -+{ -+ uint64x1_t result; -+ __asm__ ("fcmge %d0, %d2, %d1" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vcleq_f32 (float32x4_t a, float32x4_t b) -+{ -+ uint32x4_t result; -+ __asm__ ("fcmge %0.4s, %2.4s, %1.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vcleq_f64 (float64x2_t a, float64x2_t b) -+{ -+ uint64x2_t result; -+ __asm__ ("fcmge %0.2d, %2.2d, %1.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vcls_s8 (int8x8_t a) -+{ -+ int8x8_t result; -+ __asm__ ("cls %0.8b,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vcls_s16 (int16x4_t a) -+{ -+ int16x4_t result; -+ __asm__ ("cls %0.4h,%1.4h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vcls_s32 (int32x2_t a) -+{ -+ int32x2_t result; -+ __asm__ ("cls %0.2s,%1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vclsq_s8 (int8x16_t a) -+{ -+ int8x16_t result; -+ __asm__ ("cls %0.16b,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vclsq_s16 (int16x8_t a) -+{ -+ int16x8_t result; -+ __asm__ ("cls %0.8h,%1.8h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vclsq_s32 (int32x4_t a) -+{ -+ int32x4_t result; -+ __asm__ ("cls %0.4s,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vclt_f32 (float32x2_t a, float32x2_t b) -+{ -+ uint32x2_t result; -+ __asm__ ("fcmgt %0.2s, %2.2s, %1.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vclt_f64 (float64x1_t a, float64x1_t b) -+{ -+ uint64x1_t result; -+ __asm__ ("fcmgt %d0, %d2, %d1" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vcltq_f32 (float32x4_t a, float32x4_t b) -+{ -+ uint32x4_t result; -+ __asm__ ("fcmgt %0.4s, %2.4s, %1.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vcltq_f64 (float64x2_t a, float64x2_t b) -+{ -+ uint64x2_t result; -+ __asm__ ("fcmgt %0.2d, %2.2d, %1.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vclz_s8 (int8x8_t a) -+{ -+ int8x8_t result; -+ __asm__ ("clz %0.8b,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vclz_s16 (int16x4_t a) -+{ -+ int16x4_t result; -+ __asm__ ("clz %0.4h,%1.4h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vclz_s32 (int32x2_t a) -+{ -+ int32x2_t result; -+ __asm__ ("clz %0.2s,%1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vclz_u8 (uint8x8_t a) -+{ -+ uint8x8_t result; -+ __asm__ ("clz %0.8b,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vclz_u16 (uint16x4_t a) -+{ -+ uint16x4_t result; -+ __asm__ ("clz %0.4h,%1.4h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vclz_u32 (uint32x2_t a) -+{ -+ uint32x2_t result; -+ __asm__ ("clz %0.2s,%1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vclzq_s8 (int8x16_t a) -+{ -+ int8x16_t result; -+ __asm__ ("clz %0.16b,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vclzq_s16 (int16x8_t a) -+{ -+ int16x8_t result; -+ __asm__ ("clz %0.8h,%1.8h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vclzq_s32 (int32x4_t a) -+{ -+ int32x4_t result; -+ __asm__ ("clz %0.4s,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vclzq_u8 (uint8x16_t a) -+{ -+ uint8x16_t result; -+ __asm__ ("clz %0.16b,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vclzq_u16 (uint16x8_t a) -+{ -+ uint16x8_t result; -+ __asm__ ("clz %0.8h,%1.8h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vclzq_u32 (uint32x4_t a) -+{ -+ uint32x4_t result; -+ __asm__ ("clz %0.4s,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vcnt_p8 (poly8x8_t a) -+{ -+ poly8x8_t result; -+ __asm__ ("cnt %0.8b,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vcnt_s8 (int8x8_t a) -+{ -+ int8x8_t result; -+ __asm__ ("cnt %0.8b,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vcnt_u8 (uint8x8_t a) -+{ -+ uint8x8_t result; -+ __asm__ ("cnt %0.8b,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vcntq_p8 (poly8x16_t a) -+{ -+ poly8x16_t result; -+ __asm__ ("cnt %0.16b,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vcntq_s8 (int8x16_t a) -+{ -+ int8x16_t result; -+ __asm__ ("cnt %0.16b,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vcntq_u8 (uint8x16_t a) -+{ -+ uint8x16_t result; -+ __asm__ ("cnt %0.16b,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vcopyq_lane_f32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ float32x4_t c_ = (c); \ -+ float32x4_t a_ = (a); \ -+ float32x4_t result; \ -+ __asm__ ("ins %0.s[%2], %3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "i"(b), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vcopyq_lane_f64(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ float64x2_t c_ = (c); \ -+ float64x2_t a_ = (a); \ -+ float64x2_t result; \ -+ __asm__ ("ins %0.d[%2], %3.d[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "i"(b), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vcopyq_lane_p8(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ poly8x16_t c_ = (c); \ -+ poly8x16_t a_ = (a); \ -+ poly8x16_t result; \ -+ __asm__ ("ins %0.b[%2], %3.b[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "i"(b), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vcopyq_lane_p16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ poly16x8_t c_ = (c); \ -+ poly16x8_t a_ = (a); \ -+ poly16x8_t result; \ -+ __asm__ ("ins %0.h[%2], %3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "i"(b), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vcopyq_lane_s8(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int8x16_t c_ = (c); \ -+ int8x16_t a_ = (a); \ -+ int8x16_t result; \ -+ __asm__ ("ins %0.b[%2], %3.b[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "i"(b), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vcopyq_lane_s16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t c_ = (c); \ -+ int16x8_t a_ = (a); \ -+ int16x8_t result; \ -+ __asm__ ("ins %0.h[%2], %3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "i"(b), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vcopyq_lane_s32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t c_ = (c); \ -+ int32x4_t a_ = (a); \ -+ int32x4_t result; \ -+ __asm__ ("ins %0.s[%2], %3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "i"(b), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vcopyq_lane_s64(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int64x2_t c_ = (c); \ -+ int64x2_t a_ = (a); \ -+ int64x2_t result; \ -+ __asm__ ("ins %0.d[%2], %3.d[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "i"(b), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vcopyq_lane_u8(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint8x16_t c_ = (c); \ -+ uint8x16_t a_ = (a); \ -+ uint8x16_t result; \ -+ __asm__ ("ins %0.b[%2], %3.b[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "i"(b), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vcopyq_lane_u16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t c_ = (c); \ -+ uint16x8_t a_ = (a); \ -+ uint16x8_t result; \ -+ __asm__ ("ins %0.h[%2], %3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "i"(b), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vcopyq_lane_u32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t c_ = (c); \ -+ uint32x4_t a_ = (a); \ -+ uint32x4_t result; \ -+ __asm__ ("ins %0.s[%2], %3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "i"(b), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vcopyq_lane_u64(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint64x2_t c_ = (c); \ -+ uint64x2_t a_ = (a); \ -+ uint64x2_t result; \ -+ __asm__ ("ins %0.d[%2], %3.d[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "i"(b), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+/* vcvt_f16_f32 not supported */ -+ -+/* vcvt_f32_f16 not supported */ -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vcvt_f32_f64 (float64x2_t a) -+{ -+ float32x2_t result; -+ __asm__ ("fcvtn %0.2s,%1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vcvt_f32_s32 (int32x2_t a) -+{ -+ float32x2_t result; -+ __asm__ ("scvtf %0.2s, %1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vcvt_f32_u32 (uint32x2_t a) -+{ -+ float32x2_t result; -+ __asm__ ("ucvtf %0.2s, %1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vcvt_f64_f32 (float32x2_t a) -+{ -+ float64x2_t result; -+ __asm__ ("fcvtl %0.2d,%1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x1_t __attribute__ ((__always_inline__)) -+vcvt_f64_s64 (uint64x1_t a) -+{ -+ float64x1_t result; -+ __asm__ ("scvtf %d0, %d1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x1_t __attribute__ ((__always_inline__)) -+vcvt_f64_u64 (uint64x1_t a) -+{ -+ float64x1_t result; -+ __asm__ ("ucvtf %d0, %d1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+/* vcvt_high_f16_f32 not supported */ -+ -+/* vcvt_high_f32_f16 not supported */ -+ -+static float32x2_t vdup_n_f32 (float32_t); -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vcvt_high_f32_f64 (float32x2_t a, float64x2_t b) -+{ -+ float32x4_t result = vcombine_f32 (a, vdup_n_f32 (0.0f)); -+ __asm__ ("fcvtn2 %0.4s,%2.2d" -+ : "+w"(result) -+ : "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vcvt_high_f64_f32 (float32x4_t a) -+{ -+ float64x2_t result; -+ __asm__ ("fcvtl2 %0.2d,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vcvt_n_f32_s32(a, b) \ -+ __extension__ \ -+ ({ \ -+ int32x2_t a_ = (a); \ -+ float32x2_t result; \ -+ __asm__ ("scvtf %0.2s, %1.2s, #%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vcvt_n_f32_u32(a, b) \ -+ __extension__ \ -+ ({ \ -+ uint32x2_t a_ = (a); \ -+ float32x2_t result; \ -+ __asm__ ("ucvtf %0.2s, %1.2s, #%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vcvt_n_s32_f32(a, b) \ -+ __extension__ \ -+ ({ \ -+ float32x2_t a_ = (a); \ -+ int32x2_t result; \ -+ __asm__ ("fcvtzs %0.2s, %1.2s, #%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vcvt_n_u32_f32(a, b) \ -+ __extension__ \ -+ ({ \ -+ float32x2_t a_ = (a); \ -+ uint32x2_t result; \ -+ __asm__ ("fcvtzu %0.2s, %1.2s, #%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vcvt_s32_f32 (float32x2_t a) -+{ -+ int32x2_t result; -+ __asm__ ("fcvtzs %0.2s, %1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vcvt_u32_f32 (float32x2_t a) -+{ -+ uint32x2_t result; -+ __asm__ ("fcvtzu %0.2s, %1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vcvta_s32_f32 (float32x2_t a) -+{ -+ int32x2_t result; -+ __asm__ ("fcvtas %0.2s, %1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vcvta_u32_f32 (float32x2_t a) -+{ -+ uint32x2_t result; -+ __asm__ ("fcvtau %0.2s, %1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -+vcvtad_s64_f64 (float64_t a) -+{ -+ float64_t result; -+ __asm__ ("fcvtas %d0,%d1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -+vcvtad_u64_f64 (float64_t a) -+{ -+ float64_t result; -+ __asm__ ("fcvtau %d0,%d1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vcvtaq_s32_f32 (float32x4_t a) -+{ -+ int32x4_t result; -+ __asm__ ("fcvtas %0.4s, %1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vcvtaq_s64_f64 (float64x2_t a) -+{ -+ int64x2_t result; -+ __asm__ ("fcvtas %0.2d, %1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vcvtaq_u32_f32 (float32x4_t a) -+{ -+ uint32x4_t result; -+ __asm__ ("fcvtau %0.4s, %1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vcvtaq_u64_f64 (float64x2_t a) -+{ -+ uint64x2_t result; -+ __asm__ ("fcvtau %0.2d, %1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vcvtas_s64_f64 (float32_t a) -+{ -+ float32_t result; -+ __asm__ ("fcvtas %s0,%s1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vcvtas_u64_f64 (float32_t a) -+{ -+ float32_t result; -+ __asm__ ("fcvtau %s0,%s1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64_t __attribute__ ((__always_inline__)) -+vcvtd_f64_s64 (int64_t a) -+{ -+ int64_t result; -+ __asm__ ("scvtf %d0,%d1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64_t __attribute__ ((__always_inline__)) -+vcvtd_f64_u64 (uint64_t a) -+{ -+ uint64_t result; -+ __asm__ ("ucvtf %d0,%d1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vcvtd_n_f64_s64(a, b) \ -+ __extension__ \ -+ ({ \ -+ int64_t a_ = (a); \ -+ int64_t result; \ -+ __asm__ ("scvtf %d0,%d1,%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vcvtd_n_f64_u64(a, b) \ -+ __extension__ \ -+ ({ \ -+ uint64_t a_ = (a); \ -+ uint64_t result; \ -+ __asm__ ("ucvtf %d0,%d1,%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vcvtd_n_s64_f64(a, b) \ -+ __extension__ \ -+ ({ \ -+ float64_t a_ = (a); \ -+ float64_t result; \ -+ __asm__ ("fcvtzs %d0,%d1,%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vcvtd_n_u64_f64(a, b) \ -+ __extension__ \ -+ ({ \ -+ float64_t a_ = (a); \ -+ float64_t result; \ -+ __asm__ ("fcvtzu %d0,%d1,%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -+vcvtd_s64_f64 (float64_t a) -+{ -+ float64_t result; -+ __asm__ ("fcvtzs %d0,%d1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -+vcvtd_u64_f64 (float64_t a) -+{ -+ float64_t result; -+ __asm__ ("fcvtzu %d0,%d1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vcvtm_s32_f32 (float32x2_t a) -+{ -+ int32x2_t result; -+ __asm__ ("fcvtms %0.2s, %1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vcvtm_u32_f32 (float32x2_t a) -+{ -+ uint32x2_t result; -+ __asm__ ("fcvtmu %0.2s, %1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -+vcvtmd_s64_f64 (float64_t a) -+{ -+ float64_t result; -+ __asm__ ("fcvtms %d0,%d1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -+vcvtmd_u64_f64 (float64_t a) -+{ -+ float64_t result; -+ __asm__ ("fcvtmu %d0,%d1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vcvtmq_s32_f32 (float32x4_t a) -+{ -+ int32x4_t result; -+ __asm__ ("fcvtms %0.4s, %1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vcvtmq_s64_f64 (float64x2_t a) -+{ -+ int64x2_t result; -+ __asm__ ("fcvtms %0.2d, %1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vcvtmq_u32_f32 (float32x4_t a) -+{ -+ uint32x4_t result; -+ __asm__ ("fcvtmu %0.4s, %1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vcvtmq_u64_f64 (float64x2_t a) -+{ -+ uint64x2_t result; -+ __asm__ ("fcvtmu %0.2d, %1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vcvtms_s64_f64 (float32_t a) -+{ -+ float32_t result; -+ __asm__ ("fcvtms %s0,%s1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vcvtms_u64_f64 (float32_t a) -+{ -+ float32_t result; -+ __asm__ ("fcvtmu %s0,%s1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vcvtn_s32_f32 (float32x2_t a) -+{ -+ int32x2_t result; -+ __asm__ ("fcvtns %0.2s, %1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vcvtn_u32_f32 (float32x2_t a) -+{ -+ uint32x2_t result; -+ __asm__ ("fcvtnu %0.2s, %1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -+vcvtnd_s64_f64 (float64_t a) -+{ -+ float64_t result; -+ __asm__ ("fcvtns %d0,%d1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -+vcvtnd_u64_f64 (float64_t a) -+{ -+ float64_t result; -+ __asm__ ("fcvtnu %d0,%d1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vcvtnq_s32_f32 (float32x4_t a) -+{ -+ int32x4_t result; -+ __asm__ ("fcvtns %0.4s, %1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vcvtnq_s64_f64 (float64x2_t a) -+{ -+ int64x2_t result; -+ __asm__ ("fcvtns %0.2d, %1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vcvtnq_u32_f32 (float32x4_t a) -+{ -+ uint32x4_t result; -+ __asm__ ("fcvtnu %0.4s, %1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vcvtnq_u64_f64 (float64x2_t a) -+{ -+ uint64x2_t result; -+ __asm__ ("fcvtnu %0.2d, %1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vcvtns_s64_f64 (float32_t a) -+{ -+ float32_t result; -+ __asm__ ("fcvtns %s0,%s1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vcvtns_u64_f64 (float32_t a) -+{ -+ float32_t result; -+ __asm__ ("fcvtnu %s0,%s1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vcvtp_s32_f32 (float32x2_t a) -+{ -+ int32x2_t result; -+ __asm__ ("fcvtps %0.2s, %1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vcvtp_u32_f32 (float32x2_t a) -+{ -+ uint32x2_t result; -+ __asm__ ("fcvtpu %0.2s, %1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -+vcvtpd_s64_f64 (float64_t a) -+{ -+ float64_t result; -+ __asm__ ("fcvtps %d0,%d1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -+vcvtpd_u64_f64 (float64_t a) -+{ -+ float64_t result; -+ __asm__ ("fcvtpu %d0,%d1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vcvtpq_s32_f32 (float32x4_t a) -+{ -+ int32x4_t result; -+ __asm__ ("fcvtps %0.4s, %1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vcvtpq_s64_f64 (float64x2_t a) -+{ -+ int64x2_t result; -+ __asm__ ("fcvtps %0.2d, %1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vcvtpq_u32_f32 (float32x4_t a) -+{ -+ uint32x4_t result; -+ __asm__ ("fcvtpu %0.4s, %1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vcvtpq_u64_f64 (float64x2_t a) -+{ -+ uint64x2_t result; -+ __asm__ ("fcvtpu %0.2d, %1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vcvtps_s64_f64 (float32_t a) -+{ -+ float32_t result; -+ __asm__ ("fcvtps %s0,%s1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vcvtps_u64_f64 (float32_t a) -+{ -+ float32_t result; -+ __asm__ ("fcvtpu %s0,%s1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vcvtq_f32_s32 (int32x4_t a) -+{ -+ float32x4_t result; -+ __asm__ ("scvtf %0.4s, %1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vcvtq_f32_u32 (uint32x4_t a) -+{ -+ float32x4_t result; -+ __asm__ ("ucvtf %0.4s, %1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vcvtq_f64_s64 (int64x2_t a) -+{ -+ float64x2_t result; -+ __asm__ ("scvtf %0.2d, %1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vcvtq_f64_u64 (uint64x2_t a) -+{ -+ float64x2_t result; -+ __asm__ ("ucvtf %0.2d, %1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vcvtq_n_f32_s32(a, b) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t a_ = (a); \ -+ float32x4_t result; \ -+ __asm__ ("scvtf %0.4s, %1.4s, #%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vcvtq_n_f32_u32(a, b) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t a_ = (a); \ -+ float32x4_t result; \ -+ __asm__ ("ucvtf %0.4s, %1.4s, #%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vcvtq_n_f64_s64(a, b) \ -+ __extension__ \ -+ ({ \ -+ int64x2_t a_ = (a); \ -+ float64x2_t result; \ -+ __asm__ ("scvtf %0.2d, %1.2d, #%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vcvtq_n_f64_u64(a, b) \ -+ __extension__ \ -+ ({ \ -+ uint64x2_t a_ = (a); \ -+ float64x2_t result; \ -+ __asm__ ("ucvtf %0.2d, %1.2d, #%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vcvtq_n_s32_f32(a, b) \ -+ __extension__ \ -+ ({ \ -+ float32x4_t a_ = (a); \ -+ int32x4_t result; \ -+ __asm__ ("fcvtzs %0.4s, %1.4s, #%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vcvtq_n_s64_f64(a, b) \ -+ __extension__ \ -+ ({ \ -+ float64x2_t a_ = (a); \ -+ int64x2_t result; \ -+ __asm__ ("fcvtzs %0.2d, %1.2d, #%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vcvtq_n_u32_f32(a, b) \ -+ __extension__ \ -+ ({ \ -+ float32x4_t a_ = (a); \ -+ uint32x4_t result; \ -+ __asm__ ("fcvtzu %0.4s, %1.4s, #%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vcvtq_n_u64_f64(a, b) \ -+ __extension__ \ -+ ({ \ -+ float64x2_t a_ = (a); \ -+ uint64x2_t result; \ -+ __asm__ ("fcvtzu %0.2d, %1.2d, #%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vcvtq_s32_f32 (float32x4_t a) -+{ -+ int32x4_t result; -+ __asm__ ("fcvtzs %0.4s, %1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vcvtq_s64_f64 (float64x2_t a) -+{ -+ int64x2_t result; -+ __asm__ ("fcvtzs %0.2d, %1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vcvtq_u32_f32 (float32x4_t a) -+{ -+ uint32x4_t result; -+ __asm__ ("fcvtzu %0.4s, %1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vcvtq_u64_f64 (float64x2_t a) -+{ -+ uint64x2_t result; -+ __asm__ ("fcvtzu %0.2d, %1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32_t __attribute__ ((__always_inline__)) -+vcvts_f64_s32 (int32_t a) -+{ -+ int32_t result; -+ __asm__ ("scvtf %s0,%s1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) -+vcvts_f64_u32 (uint32_t a) -+{ -+ uint32_t result; -+ __asm__ ("ucvtf %s0,%s1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vcvts_n_f32_s32(a, b) \ -+ __extension__ \ -+ ({ \ -+ int32_t a_ = (a); \ -+ int32_t result; \ -+ __asm__ ("scvtf %s0,%s1,%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vcvts_n_f32_u32(a, b) \ -+ __extension__ \ -+ ({ \ -+ uint32_t a_ = (a); \ -+ uint32_t result; \ -+ __asm__ ("ucvtf %s0,%s1,%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vcvts_n_s32_f32(a, b) \ -+ __extension__ \ -+ ({ \ -+ float32_t a_ = (a); \ -+ float32_t result; \ -+ __asm__ ("fcvtzs %s0,%s1,%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vcvts_n_u32_f32(a, b) \ -+ __extension__ \ -+ ({ \ -+ float32_t a_ = (a); \ -+ float32_t result; \ -+ __asm__ ("fcvtzu %s0,%s1,%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vcvts_s64_f64 (float32_t a) -+{ -+ float32_t result; -+ __asm__ ("fcvtzs %s0,%s1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vcvts_u64_f64 (float32_t a) -+{ -+ float32_t result; -+ __asm__ ("fcvtzu %s0,%s1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vcvtx_f32_f64 (float64x2_t a) -+{ -+ float32x2_t result; -+ __asm__ ("fcvtxn %0.2s,%1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vcvtx_high_f32_f64 (float64x2_t a) -+{ -+ float32x4_t result; -+ __asm__ ("fcvtxn2 %0.4s,%1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vcvtxd_f32_f64 (float64_t a) -+{ -+ float32_t result; -+ __asm__ ("fcvtxn %s0,%d1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vdup_lane_f32(a, b) \ -+ __extension__ \ -+ ({ \ -+ float32x2_t a_ = (a); \ -+ float32x2_t result; \ -+ __asm__ ("dup %0.2s,%1.s[%2]" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vdup_lane_p8(a, b) \ -+ __extension__ \ -+ ({ \ -+ poly8x8_t a_ = (a); \ -+ poly8x8_t result; \ -+ __asm__ ("dup %0.8b,%1.b[%2]" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vdup_lane_p16(a, b) \ -+ __extension__ \ -+ ({ \ -+ poly16x4_t a_ = (a); \ -+ poly16x4_t result; \ -+ __asm__ ("dup %0.4h,%1.h[%2]" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vdup_lane_s8(a, b) \ -+ __extension__ \ -+ ({ \ -+ int8x8_t a_ = (a); \ -+ int8x8_t result; \ -+ __asm__ ("dup %0.8b,%1.b[%2]" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vdup_lane_s16(a, b) \ -+ __extension__ \ -+ ({ \ -+ int16x4_t a_ = (a); \ -+ int16x4_t result; \ -+ __asm__ ("dup %0.4h,%1.h[%2]" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vdup_lane_s32(a, b) \ -+ __extension__ \ -+ ({ \ -+ int32x2_t a_ = (a); \ -+ int32x2_t result; \ -+ __asm__ ("dup %0.2s,%1.s[%2]" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vdup_lane_s64(a, b) \ -+ __extension__ \ -+ ({ \ -+ int64x1_t a_ = (a); \ -+ int64x1_t result; \ -+ __asm__ ("ins %0.d[0],%1.d[%2]" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vdup_lane_u8(a, b) \ -+ __extension__ \ -+ ({ \ -+ uint8x8_t a_ = (a); \ -+ uint8x8_t result; \ -+ __asm__ ("dup %0.8b,%1.b[%2]" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vdup_lane_u16(a, b) \ -+ __extension__ \ -+ ({ \ -+ uint16x4_t a_ = (a); \ -+ uint16x4_t result; \ -+ __asm__ ("dup %0.4h,%1.h[%2]" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vdup_lane_u32(a, b) \ -+ __extension__ \ -+ ({ \ -+ uint32x2_t a_ = (a); \ -+ uint32x2_t result; \ -+ __asm__ ("dup %0.2s,%1.s[%2]" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vdup_lane_u64(a, b) \ -+ __extension__ \ -+ ({ \ -+ uint64x1_t a_ = (a); \ -+ uint64x1_t result; \ -+ __asm__ ("ins %0.d[0],%1.d[%2]" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vdup_n_f32 (float32_t a) -+{ -+ float32x2_t result; -+ __asm__ ("dup %0.2s, %w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vdup_n_p8 (uint32_t a) -+{ -+ poly8x8_t result; -+ __asm__ ("dup %0.8b,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) -+vdup_n_p16 (uint32_t a) -+{ -+ poly16x4_t result; -+ __asm__ ("dup %0.4h,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vdup_n_s8 (int32_t a) -+{ -+ int8x8_t result; -+ __asm__ ("dup %0.8b,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vdup_n_s16 (int32_t a) -+{ -+ int16x4_t result; -+ __asm__ ("dup %0.4h,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vdup_n_s32 (int32_t a) -+{ -+ int32x2_t result; -+ __asm__ ("dup %0.2s,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vdup_n_s64 (int64_t a) -+{ -+ int64x1_t result; -+ __asm__ ("ins %0.d[0],%x1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vdup_n_u8 (uint32_t a) -+{ -+ uint8x8_t result; -+ __asm__ ("dup %0.8b,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vdup_n_u16 (uint32_t a) -+{ -+ uint16x4_t result; -+ __asm__ ("dup %0.4h,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vdup_n_u32 (uint32_t a) -+{ -+ uint32x2_t result; -+ __asm__ ("dup %0.2s,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vdup_n_u64 (uint64_t a) -+{ -+ uint64x1_t result; -+ __asm__ ("ins %0.d[0],%x1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vdupd_lane_f64(a, b) \ -+ __extension__ \ -+ ({ \ -+ float64x2_t a_ = (a); \ -+ float64_t result; \ -+ __asm__ ("dup %d0, %1.d[%2]" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vdupq_lane_f32(a, b) \ -+ __extension__ \ -+ ({ \ -+ float32x2_t a_ = (a); \ -+ float32x4_t result; \ -+ __asm__ ("dup %0.4s,%1.s[%2]" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vdupq_lane_f64(a, b) \ -+ __extension__ \ -+ ({ \ -+ float64x1_t a_ = (a); \ -+ float64x2_t result; \ -+ __asm__ ("dup %0.2d,%1.d[%2]" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vdupq_lane_p8(a, b) \ -+ __extension__ \ -+ ({ \ -+ poly8x8_t a_ = (a); \ -+ poly8x16_t result; \ -+ __asm__ ("dup %0.16b,%1.b[%2]" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vdupq_lane_p16(a, b) \ -+ __extension__ \ -+ ({ \ -+ poly16x4_t a_ = (a); \ -+ poly16x8_t result; \ -+ __asm__ ("dup %0.8h,%1.h[%2]" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vdupq_lane_s8(a, b) \ -+ __extension__ \ -+ ({ \ -+ int8x8_t a_ = (a); \ -+ int8x16_t result; \ -+ __asm__ ("dup %0.16b,%1.b[%2]" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vdupq_lane_s16(a, b) \ -+ __extension__ \ -+ ({ \ -+ int16x4_t a_ = (a); \ -+ int16x8_t result; \ -+ __asm__ ("dup %0.8h,%1.h[%2]" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vdupq_lane_s32(a, b) \ -+ __extension__ \ -+ ({ \ -+ int32x2_t a_ = (a); \ -+ int32x4_t result; \ -+ __asm__ ("dup %0.4s,%1.s[%2]" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vdupq_lane_s64(a, b) \ -+ __extension__ \ -+ ({ \ -+ int64x1_t a_ = (a); \ -+ int64x2_t result; \ -+ __asm__ ("dup %0.2d,%1.d[%2]" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vdupq_lane_u8(a, b) \ -+ __extension__ \ -+ ({ \ -+ uint8x8_t a_ = (a); \ -+ uint8x16_t result; \ -+ __asm__ ("dup %0.16b,%1.b[%2]" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vdupq_lane_u16(a, b) \ -+ __extension__ \ -+ ({ \ -+ uint16x4_t a_ = (a); \ -+ uint16x8_t result; \ -+ __asm__ ("dup %0.8h,%1.h[%2]" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vdupq_lane_u32(a, b) \ -+ __extension__ \ -+ ({ \ -+ uint32x2_t a_ = (a); \ -+ uint32x4_t result; \ -+ __asm__ ("dup %0.4s,%1.s[%2]" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vdupq_lane_u64(a, b) \ -+ __extension__ \ -+ ({ \ -+ uint64x1_t a_ = (a); \ -+ uint64x2_t result; \ -+ __asm__ ("dup %0.2d,%1.d[%2]" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vdupq_n_f32 (float32_t a) -+{ -+ float32x4_t result; -+ __asm__ ("dup %0.4s, %w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vdupq_n_f64 (float64_t a) -+{ -+ float64x2_t result; -+ __asm__ ("dup %0.2d, %x1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vdupq_n_p8 (uint32_t a) -+{ -+ poly8x16_t result; -+ __asm__ ("dup %0.16b,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) -+vdupq_n_p16 (uint32_t a) -+{ -+ poly16x8_t result; -+ __asm__ ("dup %0.8h,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vdupq_n_s8 (int32_t a) -+{ -+ int8x16_t result; -+ __asm__ ("dup %0.16b,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vdupq_n_s16 (int32_t a) -+{ -+ int16x8_t result; -+ __asm__ ("dup %0.8h,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vdupq_n_s32 (int32_t a) -+{ -+ int32x4_t result; -+ __asm__ ("dup %0.4s,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vdupq_n_s64 (int64_t a) -+{ -+ int64x2_t result; -+ __asm__ ("dup %0.2d,%x1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vdupq_n_u8 (uint32_t a) -+{ -+ uint8x16_t result; -+ __asm__ ("dup %0.16b,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vdupq_n_u16 (uint32_t a) -+{ -+ uint16x8_t result; -+ __asm__ ("dup %0.8h,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vdupq_n_u32 (uint32_t a) -+{ -+ uint32x4_t result; -+ __asm__ ("dup %0.4s,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vdupq_n_u64 (uint64_t a) -+{ -+ uint64x2_t result; -+ __asm__ ("dup %0.2d,%x1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vdups_lane_f32(a, b) \ -+ __extension__ \ -+ ({ \ -+ float32x4_t a_ = (a); \ -+ float32_t result; \ -+ __asm__ ("dup %s0, %1.s[%2]" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vext_f32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float32x2_t b_ = (b); \ -+ float32x2_t a_ = (a); \ -+ float32x2_t result; \ -+ __asm__ ("ext %0.8b, %1.8b, %2.8b, #%3*4" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vext_f64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float64x1_t b_ = (b); \ -+ float64x1_t a_ = (a); \ -+ float64x1_t result; \ -+ __asm__ ("ext %0.8b, %1.8b, %2.8b, #%3*8" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vext_p8(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ poly8x8_t b_ = (b); \ -+ poly8x8_t a_ = (a); \ -+ poly8x8_t result; \ -+ __asm__ ("ext %0.8b,%1.8b,%2.8b,%3" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vext_p16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ poly16x4_t b_ = (b); \ -+ poly16x4_t a_ = (a); \ -+ poly16x4_t result; \ -+ __asm__ ("ext %0.8b, %1.8b, %2.8b, #%3*2" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vext_s8(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int8x8_t b_ = (b); \ -+ int8x8_t a_ = (a); \ -+ int8x8_t result; \ -+ __asm__ ("ext %0.8b,%1.8b,%2.8b,%3" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vext_s16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int16x4_t b_ = (b); \ -+ int16x4_t a_ = (a); \ -+ int16x4_t result; \ -+ __asm__ ("ext %0.8b, %1.8b, %2.8b, #%3*2" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vext_s32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int32x2_t b_ = (b); \ -+ int32x2_t a_ = (a); \ -+ int32x2_t result; \ -+ __asm__ ("ext %0.8b, %1.8b, %2.8b, #%3*4" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vext_s64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int64x1_t b_ = (b); \ -+ int64x1_t a_ = (a); \ -+ int64x1_t result; \ -+ __asm__ ("ext %0.8b, %1.8b, %2.8b, #%3*8" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vext_u8(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint8x8_t b_ = (b); \ -+ uint8x8_t a_ = (a); \ -+ uint8x8_t result; \ -+ __asm__ ("ext %0.8b,%1.8b,%2.8b,%3" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vext_u16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint16x4_t b_ = (b); \ -+ uint16x4_t a_ = (a); \ -+ uint16x4_t result; \ -+ __asm__ ("ext %0.8b, %1.8b, %2.8b, #%3*2" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vext_u32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint32x2_t b_ = (b); \ -+ uint32x2_t a_ = (a); \ -+ uint32x2_t result; \ -+ __asm__ ("ext %0.8b, %1.8b, %2.8b, #%3*4" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vext_u64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint64x1_t b_ = (b); \ -+ uint64x1_t a_ = (a); \ -+ uint64x1_t result; \ -+ __asm__ ("ext %0.8b, %1.8b, %2.8b, #%3*8" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vextq_f32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float32x4_t b_ = (b); \ -+ float32x4_t a_ = (a); \ -+ float32x4_t result; \ -+ __asm__ ("ext %0.16b, %1.16b, %2.16b, #%3*4" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vextq_f64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float64x2_t b_ = (b); \ -+ float64x2_t a_ = (a); \ -+ float64x2_t result; \ -+ __asm__ ("ext %0.16b, %1.16b, %2.16b, #%3*8" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vextq_p8(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ poly8x16_t b_ = (b); \ -+ poly8x16_t a_ = (a); \ -+ poly8x16_t result; \ -+ __asm__ ("ext %0.16b, %1.16b, %2.16b, #%3" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vextq_p16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ poly16x8_t b_ = (b); \ -+ poly16x8_t a_ = (a); \ -+ poly16x8_t result; \ -+ __asm__ ("ext %0.16b, %1.16b, %2.16b, #%3*2" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vextq_s8(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int8x16_t b_ = (b); \ -+ int8x16_t a_ = (a); \ -+ int8x16_t result; \ -+ __asm__ ("ext %0.16b, %1.16b, %2.16b, #%3" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vextq_s16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t b_ = (b); \ -+ int16x8_t a_ = (a); \ -+ int16x8_t result; \ -+ __asm__ ("ext %0.16b, %1.16b, %2.16b, #%3*2" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vextq_s32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t b_ = (b); \ -+ int32x4_t a_ = (a); \ -+ int32x4_t result; \ -+ __asm__ ("ext %0.16b, %1.16b, %2.16b, #%3*4" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vextq_s64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int64x2_t b_ = (b); \ -+ int64x2_t a_ = (a); \ -+ int64x2_t result; \ -+ __asm__ ("ext %0.16b, %1.16b, %2.16b, #%3*8" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vextq_u8(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint8x16_t b_ = (b); \ -+ uint8x16_t a_ = (a); \ -+ uint8x16_t result; \ -+ __asm__ ("ext %0.16b, %1.16b, %2.16b, #%3" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vextq_u16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t b_ = (b); \ -+ uint16x8_t a_ = (a); \ -+ uint16x8_t result; \ -+ __asm__ ("ext %0.16b, %1.16b, %2.16b, #%3*2" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vextq_u32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t b_ = (b); \ -+ uint32x4_t a_ = (a); \ -+ uint32x4_t result; \ -+ __asm__ ("ext %0.16b, %1.16b, %2.16b, #%3*4" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vextq_u64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint64x2_t b_ = (b); \ -+ uint64x2_t a_ = (a); \ -+ uint64x2_t result; \ -+ __asm__ ("ext %0.16b, %1.16b, %2.16b, #%3*8" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vfma_f32 (float32x2_t a, float32x2_t b, float32x2_t c) -+{ -+ float32x2_t result; -+ __asm__ ("fmla %0.2s,%2.2s,%3.2s" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vfma_lane_f32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ float32x2_t c_ = (c); \ -+ float32x2_t b_ = (b); \ -+ float32x2_t a_ = (a); \ -+ float32x2_t result; \ -+ __asm__ ("fmla %0.2s,%2.2s,%3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vfmad_lane_f64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float64x2_t b_ = (b); \ -+ float64_t a_ = (a); \ -+ float64_t result; \ -+ __asm__ ("fmla %d0,%d1,%2.d[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vfmaq_f32 (float32x4_t a, float32x4_t b, float32x4_t c) -+{ -+ float32x4_t result; -+ __asm__ ("fmla %0.4s,%2.4s,%3.4s" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vfmaq_f64 (float64x2_t a, float64x2_t b, float64x2_t c) -+{ -+ float64x2_t result; -+ __asm__ ("fmla %0.2d,%2.2d,%3.2d" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vfmaq_lane_f32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ float32x4_t c_ = (c); \ -+ float32x4_t b_ = (b); \ -+ float32x4_t a_ = (a); \ -+ float32x4_t result; \ -+ __asm__ ("fmla %0.4s,%2.4s,%3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vfmaq_lane_f64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float64x2_t b_ = (b); \ -+ float64x2_t a_ = (a); \ -+ float64x2_t result; \ -+ __asm__ ("fmla %0.2d,%1.2d,%2.d[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vfmas_lane_f32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float32x4_t b_ = (b); \ -+ float32_t a_ = (a); \ -+ float32_t result; \ -+ __asm__ ("fmla %s0,%s1,%2.s[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vfms_f32 (float32x2_t a, float32x2_t b, float32x2_t c) -+{ -+ float32x2_t result; -+ __asm__ ("fmls %0.2s,%2.2s,%3.2s" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vfmsd_lane_f64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float64x2_t b_ = (b); \ -+ float64_t a_ = (a); \ -+ float64_t result; \ -+ __asm__ ("fmls %d0,%d1,%2.d[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vfmsq_f32 (float32x4_t a, float32x4_t b, float32x4_t c) -+{ -+ float32x4_t result; -+ __asm__ ("fmls %0.4s,%2.4s,%3.4s" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vfmsq_f64 (float64x2_t a, float64x2_t b, float64x2_t c) -+{ -+ float64x2_t result; -+ __asm__ ("fmls %0.2d,%2.2d,%3.2d" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vfmss_lane_f32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float32x4_t b_ = (b); \ -+ float32_t a_ = (a); \ -+ float32_t result; \ -+ __asm__ ("fmls %s0,%s1,%2.s[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vget_high_f32 (float32x4_t a) -+{ -+ float32x2_t result; -+ __asm__ ("ins %0.d[0], %1.d[1]" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x1_t __attribute__ ((__always_inline__)) -+vget_high_f64 (float64x2_t a) -+{ -+ float64x1_t result; -+ __asm__ ("ins %0.d[0], %1.d[1]" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vget_high_p8 (poly8x16_t a) -+{ -+ poly8x8_t result; -+ __asm__ ("ins %0.d[0], %1.d[1]" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) -+vget_high_p16 (poly16x8_t a) -+{ -+ poly16x4_t result; -+ __asm__ ("ins %0.d[0], %1.d[1]" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vget_high_s8 (int8x16_t a) -+{ -+ int8x8_t result; -+ __asm__ ("ins %0.d[0], %1.d[1]" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vget_high_s16 (int16x8_t a) -+{ -+ int16x4_t result; -+ __asm__ ("ins %0.d[0], %1.d[1]" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vget_high_s32 (int32x4_t a) -+{ -+ int32x2_t result; -+ __asm__ ("ins %0.d[0], %1.d[1]" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vget_high_s64 (int64x2_t a) -+{ -+ int64x1_t result; -+ __asm__ ("ins %0.d[0], %1.d[1]" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vget_high_u8 (uint8x16_t a) -+{ -+ uint8x8_t result; -+ __asm__ ("ins %0.d[0], %1.d[1]" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vget_high_u16 (uint16x8_t a) -+{ -+ uint16x4_t result; -+ __asm__ ("ins %0.d[0], %1.d[1]" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vget_high_u32 (uint32x4_t a) -+{ -+ uint32x2_t result; -+ __asm__ ("ins %0.d[0], %1.d[1]" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vget_high_u64 (uint64x2_t a) -+{ -+ uint64x1_t result; -+ __asm__ ("ins %0.d[0], %1.d[1]" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vget_lane_f64(a, b) \ -+ __extension__ \ -+ ({ \ -+ float64x1_t a_ = (a); \ -+ float64_t result; \ -+ __asm__ ("umov %x0, %1.d[%2]" \ -+ : "=r"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vget_low_f32 (float32x4_t a) -+{ -+ float32x2_t result; -+ __asm__ ("ins %0.d[0], %1.d[0]" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x1_t __attribute__ ((__always_inline__)) -+vget_low_f64 (float64x2_t a) -+{ -+ float64x1_t result; -+ __asm__ ("ins %0.d[0], %1.d[0]" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vget_low_p8 (poly8x16_t a) -+{ -+ poly8x8_t result; -+ __asm__ ("ins %0.d[0], %1.d[0]" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) -+vget_low_p16 (poly16x8_t a) -+{ -+ poly16x4_t result; -+ __asm__ ("ins %0.d[0], %1.d[0]" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vget_low_s8 (int8x16_t a) -+{ -+ int8x8_t result; -+ __asm__ ("ins %0.d[0], %1.d[0]" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vget_low_s16 (int16x8_t a) -+{ -+ int16x4_t result; -+ __asm__ ("ins %0.d[0], %1.d[0]" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vget_low_s32 (int32x4_t a) -+{ -+ int32x2_t result; -+ __asm__ ("ins %0.d[0], %1.d[0]" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vget_low_s64 (int64x2_t a) -+{ -+ int64x1_t result; -+ __asm__ ("ins %0.d[0], %1.d[0]" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vget_low_u8 (uint8x16_t a) -+{ -+ uint8x8_t result; -+ __asm__ ("ins %0.d[0], %1.d[0]" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vget_low_u16 (uint16x8_t a) -+{ -+ uint16x4_t result; -+ __asm__ ("ins %0.d[0], %1.d[0]" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vget_low_u32 (uint32x4_t a) -+{ -+ uint32x2_t result; -+ __asm__ ("ins %0.d[0], %1.d[0]" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vget_low_u64 (uint64x2_t a) -+{ -+ uint64x1_t result; -+ __asm__ ("ins %0.d[0], %1.d[0]" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vhsub_s8 (int8x8_t a, int8x8_t b) -+{ -+ int8x8_t result; -+ __asm__ ("shsub %0.8b, %1.8b, %2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vhsub_s16 (int16x4_t a, int16x4_t b) -+{ -+ int16x4_t result; -+ __asm__ ("shsub %0.4h, %1.4h, %2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vhsub_s32 (int32x2_t a, int32x2_t b) -+{ -+ int32x2_t result; -+ __asm__ ("shsub %0.2s, %1.2s, %2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vhsub_u8 (uint8x8_t a, uint8x8_t b) -+{ -+ uint8x8_t result; -+ __asm__ ("uhsub %0.8b, %1.8b, %2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vhsub_u16 (uint16x4_t a, uint16x4_t b) -+{ -+ uint16x4_t result; -+ __asm__ ("uhsub %0.4h, %1.4h, %2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vhsub_u32 (uint32x2_t a, uint32x2_t b) -+{ -+ uint32x2_t result; -+ __asm__ ("uhsub %0.2s, %1.2s, %2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vhsubq_s8 (int8x16_t a, int8x16_t b) -+{ -+ int8x16_t result; -+ __asm__ ("shsub %0.16b, %1.16b, %2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vhsubq_s16 (int16x8_t a, int16x8_t b) -+{ -+ int16x8_t result; -+ __asm__ ("shsub %0.8h, %1.8h, %2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vhsubq_s32 (int32x4_t a, int32x4_t b) -+{ -+ int32x4_t result; -+ __asm__ ("shsub %0.4s, %1.4s, %2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vhsubq_u8 (uint8x16_t a, uint8x16_t b) -+{ -+ uint8x16_t result; -+ __asm__ ("uhsub %0.16b, %1.16b, %2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vhsubq_u16 (uint16x8_t a, uint16x8_t b) -+{ -+ uint16x8_t result; -+ __asm__ ("uhsub %0.8h, %1.8h, %2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vhsubq_u32 (uint32x4_t a, uint32x4_t b) -+{ -+ uint32x4_t result; -+ __asm__ ("uhsub %0.4s, %1.4s, %2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vld1_dup_f32 (float32_t * a) -+{ -+ float32x2_t result; -+ __asm__ ("ld1r {%0.2s},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline float64x1_t __attribute__ ((__always_inline__)) -+vld1_dup_f64 (float64_t * a) -+{ -+ float64x1_t result; -+ __asm__ ("ld1 {%0.1d},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vld1_dup_p8 (poly8_t * a) -+{ -+ poly8x8_t result; -+ __asm__ ("ld1r {%0.8b},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) -+vld1_dup_p16 (poly16_t * a) -+{ -+ poly16x4_t result; -+ __asm__ ("ld1r {%0.4h},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vld1_dup_s8 (int8_t * a) -+{ -+ int8x8_t result; -+ __asm__ ("ld1r {%0.8b},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vld1_dup_s16 (int16_t * a) -+{ -+ int16x4_t result; -+ __asm__ ("ld1r {%0.4h},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vld1_dup_s32 (int32_t * a) -+{ -+ int32x2_t result; -+ __asm__ ("ld1r {%0.2s},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vld1_dup_s64 (int64_t * a) -+{ -+ int64x1_t result; -+ __asm__ ("ld1 {%0.1d},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vld1_dup_u8 (uint8_t * a) -+{ -+ uint8x8_t result; -+ __asm__ ("ld1r {%0.8b},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vld1_dup_u16 (uint16_t * a) -+{ -+ uint16x4_t result; -+ __asm__ ("ld1r {%0.4h},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vld1_dup_u32 (uint32_t * a) -+{ -+ uint32x2_t result; -+ __asm__ ("ld1r {%0.2s},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vld1_dup_u64 (uint64_t * a) -+{ -+ uint64x1_t result; -+ __asm__ ("ld1 {%0.1d},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vld1_f32 (float32_t * a) -+{ -+ float32x2_t result; -+ __asm__ ("ld1 {%0.2s},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline float64x1_t __attribute__ ((__always_inline__)) -+vld1_f64 (float64_t * a) -+{ -+ float64x1_t result; -+ __asm__ ("ld1 {%0.1d},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+#define vld1_lane_f32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float32x2_t b_ = (b); \ -+ float32_t * a_ = (a); \ -+ float32x2_t result; \ -+ __asm__ ("ld1 {%0.s}[%3],[%1]" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vld1_lane_f64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float64x1_t b_ = (b); \ -+ float64_t * a_ = (a); \ -+ float64x1_t result; \ -+ __asm__ ("ld1 {%0.d}[%3],[%1]" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vld1_lane_p8(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ poly8x8_t b_ = (b); \ -+ poly8_t * a_ = (a); \ -+ poly8x8_t result; \ -+ __asm__ ("ld1 {%0.b}[%3],[%1]" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vld1_lane_p16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ poly16x4_t b_ = (b); \ -+ poly16_t * a_ = (a); \ -+ poly16x4_t result; \ -+ __asm__ ("ld1 {%0.h}[%3],[%1]" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vld1_lane_s8(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int8x8_t b_ = (b); \ -+ int8_t * a_ = (a); \ -+ int8x8_t result; \ -+ __asm__ ("ld1 {%0.b}[%3],[%1]" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vld1_lane_s16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int16x4_t b_ = (b); \ -+ int16_t * a_ = (a); \ -+ int16x4_t result; \ -+ __asm__ ("ld1 {%0.h}[%3],[%1]" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vld1_lane_s32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int32x2_t b_ = (b); \ -+ int32_t * a_ = (a); \ -+ int32x2_t result; \ -+ __asm__ ("ld1 {%0.s}[%3],[%1]" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vld1_lane_s64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int64x1_t b_ = (b); \ -+ int64_t * a_ = (a); \ -+ int64x1_t result; \ -+ __asm__ ("ld1 {%0.d}[%3],[%1]" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vld1_lane_u8(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint8x8_t b_ = (b); \ -+ uint8_t * a_ = (a); \ -+ uint8x8_t result; \ -+ __asm__ ("ld1 {%0.b}[%3],[%1]" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vld1_lane_u16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint16x4_t b_ = (b); \ -+ uint16_t * a_ = (a); \ -+ uint16x4_t result; \ -+ __asm__ ("ld1 {%0.h}[%3],[%1]" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vld1_lane_u32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint32x2_t b_ = (b); \ -+ uint32_t * a_ = (a); \ -+ uint32x2_t result; \ -+ __asm__ ("ld1 {%0.s}[%3],[%1]" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vld1_lane_u64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint64x1_t b_ = (b); \ -+ uint64_t * a_ = (a); \ -+ uint64x1_t result; \ -+ __asm__ ("ld1 {%0.d}[%3],[%1]" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vld1_p8 (poly8_t * a) -+{ -+ poly8x8_t result; -+ __asm__ ("ld1 {%0.8b}, [%1]" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) -+vld1_p16 (poly16_t * a) -+{ -+ poly16x4_t result; -+ __asm__ ("ld1 {%0.4h}, [%1]" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vld1_s8 (int8_t * a) -+{ -+ int8x8_t result; -+ __asm__ ("ld1 {%0.8b},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vld1_s16 (int16_t * a) -+{ -+ int16x4_t result; -+ __asm__ ("ld1 {%0.4h},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vld1_s32 (int32_t * a) -+{ -+ int32x2_t result; -+ __asm__ ("ld1 {%0.2s},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vld1_s64 (int64_t * a) -+{ -+ int64x1_t result; -+ __asm__ ("ld1 {%0.1d},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vld1_u8 (uint8_t * a) -+{ -+ uint8x8_t result; -+ __asm__ ("ld1 {%0.8b},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vld1_u16 (uint16_t * a) -+{ -+ uint16x4_t result; -+ __asm__ ("ld1 {%0.4h},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vld1_u32 (uint32_t * a) -+{ -+ uint32x2_t result; -+ __asm__ ("ld1 {%0.2s},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vld1_u64 (uint64_t * a) -+{ -+ uint64x1_t result; -+ __asm__ ("ld1 {%0.1d},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vld1q_dup_f32 (float32_t * a) -+{ -+ float32x4_t result; -+ __asm__ ("ld1r {%0.4s},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vld1q_dup_f64 (float64_t * a) -+{ -+ float64x2_t result; -+ __asm__ ("ld1r {%0.2d},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vld1q_dup_p8 (poly8_t * a) -+{ -+ poly8x16_t result; -+ __asm__ ("ld1r {%0.16b},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) -+vld1q_dup_p16 (poly16_t * a) -+{ -+ poly16x8_t result; -+ __asm__ ("ld1r {%0.8h},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vld1q_dup_s8 (int8_t * a) -+{ -+ int8x16_t result; -+ __asm__ ("ld1r {%0.16b},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vld1q_dup_s16 (int16_t * a) -+{ -+ int16x8_t result; -+ __asm__ ("ld1r {%0.8h},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vld1q_dup_s32 (int32_t * a) -+{ -+ int32x4_t result; -+ __asm__ ("ld1r {%0.4s},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vld1q_dup_s64 (int64_t * a) -+{ -+ int64x2_t result; -+ __asm__ ("ld1r {%0.2d},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vld1q_dup_u8 (uint8_t * a) -+{ -+ uint8x16_t result; -+ __asm__ ("ld1r {%0.16b},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vld1q_dup_u16 (uint16_t * a) -+{ -+ uint16x8_t result; -+ __asm__ ("ld1r {%0.8h},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vld1q_dup_u32 (uint32_t * a) -+{ -+ uint32x4_t result; -+ __asm__ ("ld1r {%0.4s},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vld1q_dup_u64 (uint64_t * a) -+{ -+ uint64x2_t result; -+ __asm__ ("ld1r {%0.2d},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vld1q_f32 (float32_t * a) -+{ -+ float32x4_t result; -+ __asm__ ("ld1 {%0.4s},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vld1q_f64 (float64_t * a) -+{ -+ float64x2_t result; -+ __asm__ ("ld1 {%0.2d},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+#define vld1q_lane_f32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float32x4_t b_ = (b); \ -+ float32_t * a_ = (a); \ -+ float32x4_t result; \ -+ __asm__ ("ld1 {%0.s}[%3],[%1]" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vld1q_lane_f64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float64x2_t b_ = (b); \ -+ float64_t * a_ = (a); \ -+ float64x2_t result; \ -+ __asm__ ("ld1 {%0.d}[%3],[%1]" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vld1q_lane_p8(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ poly8x16_t b_ = (b); \ -+ poly8_t * a_ = (a); \ -+ poly8x16_t result; \ -+ __asm__ ("ld1 {%0.b}[%3],[%1]" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vld1q_lane_p16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ poly16x8_t b_ = (b); \ -+ poly16_t * a_ = (a); \ -+ poly16x8_t result; \ -+ __asm__ ("ld1 {%0.h}[%3],[%1]" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vld1q_lane_s8(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int8x16_t b_ = (b); \ -+ int8_t * a_ = (a); \ -+ int8x16_t result; \ -+ __asm__ ("ld1 {%0.b}[%3],[%1]" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vld1q_lane_s16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t b_ = (b); \ -+ int16_t * a_ = (a); \ -+ int16x8_t result; \ -+ __asm__ ("ld1 {%0.h}[%3],[%1]" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vld1q_lane_s32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t b_ = (b); \ -+ int32_t * a_ = (a); \ -+ int32x4_t result; \ -+ __asm__ ("ld1 {%0.s}[%3],[%1]" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vld1q_lane_s64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int64x2_t b_ = (b); \ -+ int64_t * a_ = (a); \ -+ int64x2_t result; \ -+ __asm__ ("ld1 {%0.d}[%3],[%1]" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vld1q_lane_u8(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint8x16_t b_ = (b); \ -+ uint8_t * a_ = (a); \ -+ uint8x16_t result; \ -+ __asm__ ("ld1 {%0.b}[%3],[%1]" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vld1q_lane_u16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t b_ = (b); \ -+ uint16_t * a_ = (a); \ -+ uint16x8_t result; \ -+ __asm__ ("ld1 {%0.h}[%3],[%1]" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vld1q_lane_u32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t b_ = (b); \ -+ uint32_t * a_ = (a); \ -+ uint32x4_t result; \ -+ __asm__ ("ld1 {%0.s}[%3],[%1]" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vld1q_lane_u64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint64x2_t b_ = (b); \ -+ uint64_t * a_ = (a); \ -+ uint64x2_t result; \ -+ __asm__ ("ld1 {%0.d}[%3],[%1]" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vld1q_p8 (poly8_t * a) -+{ -+ poly8x16_t result; -+ __asm__ ("ld1 {%0.16b},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) -+vld1q_p16 (poly16_t * a) -+{ -+ poly16x8_t result; -+ __asm__ ("ld1 {%0.8h},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vld1q_s8 (int8_t * a) -+{ -+ int8x16_t result; -+ __asm__ ("ld1 {%0.16b},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vld1q_s16 (int16_t * a) -+{ -+ int16x8_t result; -+ __asm__ ("ld1 {%0.8h},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vld1q_s32 (int32_t * a) -+{ -+ int32x4_t result; -+ __asm__ ("ld1 {%0.4s},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vld1q_s64 (int64_t * a) -+{ -+ int64x2_t result; -+ __asm__ ("ld1 {%0.2d},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vld1q_u8 (uint8_t * a) -+{ -+ uint8x16_t result; -+ __asm__ ("ld1 {%0.16b},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vld1q_u16 (uint16_t * a) -+{ -+ uint16x8_t result; -+ __asm__ ("ld1 {%0.8h},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vld1q_u32 (uint32_t * a) -+{ -+ uint32x4_t result; -+ __asm__ ("ld1 {%0.4s},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vld1q_u64 (uint64_t * a) -+{ -+ uint64x2_t result; -+ __asm__ ("ld1 {%0.2d},[%1]" -+ : "=w"(result) -+ : "r"(a) -+ : "memory"); -+ return result; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vmaxnm_f32 (float32x2_t a, float32x2_t b) -+{ -+ float32x2_t result; -+ __asm__ ("fmaxnm %0.2s,%1.2s,%2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vmaxnmq_f32 (float32x4_t a, float32x4_t b) -+{ -+ float32x4_t result; -+ __asm__ ("fmaxnm %0.4s,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vmaxnmq_f64 (float64x2_t a, float64x2_t b) -+{ -+ float64x2_t result; -+ __asm__ ("fmaxnm %0.2d,%1.2d,%2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vmaxnmvq_f32 (float32x4_t a) -+{ -+ float32_t result; -+ __asm__ ("fmaxnmv %s0,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8_t __attribute__ ((__always_inline__)) -+vmaxv_s8 (int8x8_t a) -+{ -+ int8_t result; -+ __asm__ ("smaxv %b0,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16_t __attribute__ ((__always_inline__)) -+vmaxv_s16 (int16x4_t a) -+{ -+ int16_t result; -+ __asm__ ("smaxv %h0,%1.4h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) -+vmaxv_u8 (uint8x8_t a) -+{ -+ uint8_t result; -+ __asm__ ("umaxv %b0,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) -+vmaxv_u16 (uint16x4_t a) -+{ -+ uint16_t result; -+ __asm__ ("umaxv %h0,%1.4h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vmaxvq_f32 (float32x4_t a) -+{ -+ float32_t result; -+ __asm__ ("fmaxv %s0,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8_t __attribute__ ((__always_inline__)) -+vmaxvq_s8 (int8x16_t a) -+{ -+ int8_t result; -+ __asm__ ("smaxv %b0,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16_t __attribute__ ((__always_inline__)) -+vmaxvq_s16 (int16x8_t a) -+{ -+ int16_t result; -+ __asm__ ("smaxv %h0,%1.8h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32_t __attribute__ ((__always_inline__)) -+vmaxvq_s32 (int32x4_t a) -+{ -+ int32_t result; -+ __asm__ ("smaxv %s0,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) -+vmaxvq_u8 (uint8x16_t a) -+{ -+ uint8_t result; -+ __asm__ ("umaxv %b0,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) -+vmaxvq_u16 (uint16x8_t a) -+{ -+ uint16_t result; -+ __asm__ ("umaxv %h0,%1.8h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) -+vmaxvq_u32 (uint32x4_t a) -+{ -+ uint32_t result; -+ __asm__ ("umaxv %s0,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vminnmvq_f32 (float32x4_t a) -+{ -+ float32_t result; -+ __asm__ ("fminnmv %s0,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8_t __attribute__ ((__always_inline__)) -+vminv_s8 (int8x8_t a) -+{ -+ int8_t result; -+ __asm__ ("sminv %b0,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16_t __attribute__ ((__always_inline__)) -+vminv_s16 (int16x4_t a) -+{ -+ int16_t result; -+ __asm__ ("sminv %h0,%1.4h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) -+vminv_u8 (uint8x8_t a) -+{ -+ uint8_t result; -+ __asm__ ("uminv %b0,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) -+vminv_u16 (uint16x4_t a) -+{ -+ uint16_t result; -+ __asm__ ("uminv %h0,%1.4h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vminvq_f32 (float32x4_t a) -+{ -+ float32_t result; -+ __asm__ ("fminv %s0,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8_t __attribute__ ((__always_inline__)) -+vminvq_s8 (int8x16_t a) -+{ -+ int8_t result; -+ __asm__ ("sminv %b0,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16_t __attribute__ ((__always_inline__)) -+vminvq_s16 (int16x8_t a) -+{ -+ int16_t result; -+ __asm__ ("sminv %h0,%1.8h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32_t __attribute__ ((__always_inline__)) -+vminvq_s32 (int32x4_t a) -+{ -+ int32_t result; -+ __asm__ ("sminv %s0,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8_t __attribute__ ((__always_inline__)) -+vminvq_u8 (uint8x16_t a) -+{ -+ uint8_t result; -+ __asm__ ("uminv %b0,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16_t __attribute__ ((__always_inline__)) -+vminvq_u16 (uint16x8_t a) -+{ -+ uint16_t result; -+ __asm__ ("uminv %h0,%1.8h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) -+vminvq_u32 (uint32x4_t a) -+{ -+ uint32_t result; -+ __asm__ ("uminv %s0,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vmla_lane_f32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ float32x4_t c_ = (c); \ -+ float32x2_t b_ = (b); \ -+ float32x2_t a_ = (a); \ -+ float32x2_t result; \ -+ float32x2_t t1; \ -+ __asm__ ("fmul %1.2s, %3.2s, %4.s[%5]; fadd %0.2s, %0.2s, %1.2s" \ -+ : "=w"(result), "=w"(t1) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmla_lane_s16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t c_ = (c); \ -+ int16x4_t b_ = (b); \ -+ int16x4_t a_ = (a); \ -+ int16x4_t result; \ -+ __asm__ ("mla %0.4h, %2.4h, %3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmla_lane_s32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t c_ = (c); \ -+ int32x2_t b_ = (b); \ -+ int32x2_t a_ = (a); \ -+ int32x2_t result; \ -+ __asm__ ("mla %0.2s, %2.2s, %3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmla_lane_u16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t c_ = (c); \ -+ uint16x4_t b_ = (b); \ -+ uint16x4_t a_ = (a); \ -+ uint16x4_t result; \ -+ __asm__ ("mla %0.4h, %2.4h, %3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmla_lane_u32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t c_ = (c); \ -+ uint32x2_t b_ = (b); \ -+ uint32x2_t a_ = (a); \ -+ uint32x2_t result; \ -+ __asm__ ("mla %0.2s, %2.2s, %3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmla_laneq_s16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t c_ = (c); \ -+ int16x4_t b_ = (b); \ -+ int16x4_t a_ = (a); \ -+ int16x4_t result; \ -+ __asm__ ("mla %0.4h, %2.4h, %3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmla_laneq_s32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t c_ = (c); \ -+ int32x2_t b_ = (b); \ -+ int32x2_t a_ = (a); \ -+ int32x2_t result; \ -+ __asm__ ("mla %0.2s, %2.2s, %3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmla_laneq_u16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t c_ = (c); \ -+ uint16x4_t b_ = (b); \ -+ uint16x4_t a_ = (a); \ -+ uint16x4_t result; \ -+ __asm__ ("mla %0.4h, %2.4h, %3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmla_laneq_u32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t c_ = (c); \ -+ uint32x2_t b_ = (b); \ -+ uint32x2_t a_ = (a); \ -+ uint32x2_t result; \ -+ __asm__ ("mla %0.2s, %2.2s, %3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vmla_n_f32 (float32x2_t a, float32x2_t b, float32_t c) -+{ -+ float32x2_t result; -+ float32x2_t t1; -+ __asm__ ("fmul %1.2s, %3.2s, %4.s[0]; fadd %0.2s, %0.2s, %1.2s" -+ : "=w"(result), "=w"(t1) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vmla_n_s16 (int16x4_t a, int16x4_t b, int16_t c) -+{ -+ int16x4_t result; -+ __asm__ ("mla %0.4h,%2.4h,%3.h[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vmla_n_s32 (int32x2_t a, int32x2_t b, int32_t c) -+{ -+ int32x2_t result; -+ __asm__ ("mla %0.2s,%2.2s,%3.s[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vmla_n_u16 (uint16x4_t a, uint16x4_t b, uint16_t c) -+{ -+ uint16x4_t result; -+ __asm__ ("mla %0.4h,%2.4h,%3.h[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vmla_n_u32 (uint32x2_t a, uint32x2_t b, uint32_t c) -+{ -+ uint32x2_t result; -+ __asm__ ("mla %0.2s,%2.2s,%3.s[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vmla_s8 (int8x8_t a, int8x8_t b, int8x8_t c) -+{ -+ int8x8_t result; -+ __asm__ ("mla %0.8b, %2.8b, %3.8b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vmla_s16 (int16x4_t a, int16x4_t b, int16x4_t c) -+{ -+ int16x4_t result; -+ __asm__ ("mla %0.4h, %2.4h, %3.4h" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vmla_s32 (int32x2_t a, int32x2_t b, int32x2_t c) -+{ -+ int32x2_t result; -+ __asm__ ("mla %0.2s, %2.2s, %3.2s" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vmla_u8 (uint8x8_t a, uint8x8_t b, uint8x8_t c) -+{ -+ uint8x8_t result; -+ __asm__ ("mla %0.8b, %2.8b, %3.8b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vmla_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t c) -+{ -+ uint16x4_t result; -+ __asm__ ("mla %0.4h, %2.4h, %3.4h" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vmla_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t c) -+{ -+ uint32x2_t result; -+ __asm__ ("mla %0.2s, %2.2s, %3.2s" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vmlal_high_lane_s16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t c_ = (c); \ -+ int16x8_t b_ = (b); \ -+ int32x4_t a_ = (a); \ -+ int32x4_t result; \ -+ __asm__ ("smlal2 %0.4s, %2.8h, %3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlal_high_lane_s32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t c_ = (c); \ -+ int32x4_t b_ = (b); \ -+ int64x2_t a_ = (a); \ -+ int64x2_t result; \ -+ __asm__ ("smlal2 %0.2d, %2.4s, %3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlal_high_lane_u16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t c_ = (c); \ -+ uint16x8_t b_ = (b); \ -+ uint32x4_t a_ = (a); \ -+ uint32x4_t result; \ -+ __asm__ ("umlal2 %0.4s, %2.8h, %3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlal_high_lane_u32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t c_ = (c); \ -+ uint32x4_t b_ = (b); \ -+ uint64x2_t a_ = (a); \ -+ uint64x2_t result; \ -+ __asm__ ("umlal2 %0.2d, %2.4s, %3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlal_high_laneq_s16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t c_ = (c); \ -+ int16x8_t b_ = (b); \ -+ int32x4_t a_ = (a); \ -+ int32x4_t result; \ -+ __asm__ ("smlal2 %0.4s, %2.8h, %3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlal_high_laneq_s32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t c_ = (c); \ -+ int32x4_t b_ = (b); \ -+ int64x2_t a_ = (a); \ -+ int64x2_t result; \ -+ __asm__ ("smlal2 %0.2d, %2.4s, %3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlal_high_laneq_u16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t c_ = (c); \ -+ uint16x8_t b_ = (b); \ -+ uint32x4_t a_ = (a); \ -+ uint32x4_t result; \ -+ __asm__ ("umlal2 %0.4s, %2.8h, %3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlal_high_laneq_u32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t c_ = (c); \ -+ uint32x4_t b_ = (b); \ -+ uint64x2_t a_ = (a); \ -+ uint64x2_t result; \ -+ __asm__ ("umlal2 %0.2d, %2.4s, %3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vmlal_high_n_s16 (int32x4_t a, int16x8_t b, int16_t c) -+{ -+ int32x4_t result; -+ __asm__ ("smlal2 %0.4s,%2.8h,%3.h[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vmlal_high_n_s32 (int64x2_t a, int32x4_t b, int32_t c) -+{ -+ int64x2_t result; -+ __asm__ ("smlal2 %0.2d,%2.4s,%3.s[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vmlal_high_n_u16 (uint32x4_t a, uint16x8_t b, uint16_t c) -+{ -+ uint32x4_t result; -+ __asm__ ("umlal2 %0.4s,%2.8h,%3.h[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vmlal_high_n_u32 (uint64x2_t a, uint32x4_t b, uint32_t c) -+{ -+ uint64x2_t result; -+ __asm__ ("umlal2 %0.2d,%2.4s,%3.s[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vmlal_high_s8 (int16x8_t a, int8x16_t b, int8x16_t c) -+{ -+ int16x8_t result; -+ __asm__ ("smlal2 %0.8h,%2.16b,%3.16b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vmlal_high_s16 (int32x4_t a, int16x8_t b, int16x8_t c) -+{ -+ int32x4_t result; -+ __asm__ ("smlal2 %0.4s,%2.8h,%3.8h" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vmlal_high_s32 (int64x2_t a, int32x4_t b, int32x4_t c) -+{ -+ int64x2_t result; -+ __asm__ ("smlal2 %0.2d,%2.4s,%3.4s" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vmlal_high_u8 (uint16x8_t a, uint8x16_t b, uint8x16_t c) -+{ -+ uint16x8_t result; -+ __asm__ ("umlal2 %0.8h,%2.16b,%3.16b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vmlal_high_u16 (uint32x4_t a, uint16x8_t b, uint16x8_t c) -+{ -+ uint32x4_t result; -+ __asm__ ("umlal2 %0.4s,%2.8h,%3.8h" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vmlal_high_u32 (uint64x2_t a, uint32x4_t b, uint32x4_t c) -+{ -+ uint64x2_t result; -+ __asm__ ("umlal2 %0.2d,%2.4s,%3.4s" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vmlal_lane_s16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t c_ = (c); \ -+ int16x4_t b_ = (b); \ -+ int32x4_t a_ = (a); \ -+ int32x4_t result; \ -+ __asm__ ("smlal %0.4s,%2.4h,%3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlal_lane_s32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t c_ = (c); \ -+ int32x2_t b_ = (b); \ -+ int64x2_t a_ = (a); \ -+ int64x2_t result; \ -+ __asm__ ("smlal %0.2d,%2.2s,%3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlal_lane_u16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t c_ = (c); \ -+ uint16x4_t b_ = (b); \ -+ uint32x4_t a_ = (a); \ -+ uint32x4_t result; \ -+ __asm__ ("umlal %0.4s,%2.4h,%3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlal_lane_u32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t c_ = (c); \ -+ uint32x2_t b_ = (b); \ -+ uint64x2_t a_ = (a); \ -+ uint64x2_t result; \ -+ __asm__ ("umlal %0.2d, %2.2s, %3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlal_laneq_s16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t c_ = (c); \ -+ int16x4_t b_ = (b); \ -+ int32x4_t a_ = (a); \ -+ int32x4_t result; \ -+ __asm__ ("smlal %0.4s, %2.4h, %3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlal_laneq_s32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t c_ = (c); \ -+ int32x2_t b_ = (b); \ -+ int64x2_t a_ = (a); \ -+ int64x2_t result; \ -+ __asm__ ("smlal %0.2d, %2.2s, %3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlal_laneq_u16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t c_ = (c); \ -+ uint16x4_t b_ = (b); \ -+ uint32x4_t a_ = (a); \ -+ uint32x4_t result; \ -+ __asm__ ("umlal %0.4s, %2.4h, %3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlal_laneq_u32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t c_ = (c); \ -+ uint32x2_t b_ = (b); \ -+ uint64x2_t a_ = (a); \ -+ uint64x2_t result; \ -+ __asm__ ("umlal %0.2d, %2.2s, %3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vmlal_n_s16 (int32x4_t a, int16x4_t b, int16_t c) -+{ -+ int32x4_t result; -+ __asm__ ("smlal %0.4s,%2.4h,%3.h[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vmlal_n_s32 (int64x2_t a, int32x2_t b, int32_t c) -+{ -+ int64x2_t result; -+ __asm__ ("smlal %0.2d,%2.2s,%3.s[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vmlal_n_u16 (uint32x4_t a, uint16x4_t b, uint16_t c) -+{ -+ uint32x4_t result; -+ __asm__ ("umlal %0.4s,%2.4h,%3.h[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vmlal_n_u32 (uint64x2_t a, uint32x2_t b, uint32_t c) -+{ -+ uint64x2_t result; -+ __asm__ ("umlal %0.2d,%2.2s,%3.s[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vmlal_s8 (int16x8_t a, int8x8_t b, int8x8_t c) -+{ -+ int16x8_t result; -+ __asm__ ("smlal %0.8h,%2.8b,%3.8b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vmlal_s16 (int32x4_t a, int16x4_t b, int16x4_t c) -+{ -+ int32x4_t result; -+ __asm__ ("smlal %0.4s,%2.4h,%3.4h" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vmlal_s32 (int64x2_t a, int32x2_t b, int32x2_t c) -+{ -+ int64x2_t result; -+ __asm__ ("smlal %0.2d,%2.2s,%3.2s" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vmlal_u8 (uint16x8_t a, uint8x8_t b, uint8x8_t c) -+{ -+ uint16x8_t result; -+ __asm__ ("umlal %0.8h,%2.8b,%3.8b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vmlal_u16 (uint32x4_t a, uint16x4_t b, uint16x4_t c) -+{ -+ uint32x4_t result; -+ __asm__ ("umlal %0.4s,%2.4h,%3.4h" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vmlal_u32 (uint64x2_t a, uint32x2_t b, uint32x2_t c) -+{ -+ uint64x2_t result; -+ __asm__ ("umlal %0.2d,%2.2s,%3.2s" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vmlaq_lane_f32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ float32x4_t c_ = (c); \ -+ float32x4_t b_ = (b); \ -+ float32x4_t a_ = (a); \ -+ float32x4_t result; \ -+ float32x4_t t1; \ -+ __asm__ ("fmul %1.4s, %3.4s, %4.s[%5]; fadd %0.4s, %0.4s, %1.4s" \ -+ : "=w"(result), "=w"(t1) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlaq_lane_s16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t c_ = (c); \ -+ int16x8_t b_ = (b); \ -+ int16x8_t a_ = (a); \ -+ int16x8_t result; \ -+ __asm__ ("mla %0.8h, %2.8h, %3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlaq_lane_s32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t c_ = (c); \ -+ int32x4_t b_ = (b); \ -+ int32x4_t a_ = (a); \ -+ int32x4_t result; \ -+ __asm__ ("mla %0.4s, %2.4s, %3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlaq_lane_u16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t c_ = (c); \ -+ uint16x8_t b_ = (b); \ -+ uint16x8_t a_ = (a); \ -+ uint16x8_t result; \ -+ __asm__ ("mla %0.8h, %2.8h, %3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlaq_lane_u32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t c_ = (c); \ -+ uint32x4_t b_ = (b); \ -+ uint32x4_t a_ = (a); \ -+ uint32x4_t result; \ -+ __asm__ ("mla %0.4s, %2.4s, %3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlaq_laneq_s16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t c_ = (c); \ -+ int16x8_t b_ = (b); \ -+ int16x8_t a_ = (a); \ -+ int16x8_t result; \ -+ __asm__ ("mla %0.8h, %2.8h, %3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlaq_laneq_s32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t c_ = (c); \ -+ int32x4_t b_ = (b); \ -+ int32x4_t a_ = (a); \ -+ int32x4_t result; \ -+ __asm__ ("mla %0.4s, %2.4s, %3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlaq_laneq_u16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t c_ = (c); \ -+ uint16x8_t b_ = (b); \ -+ uint16x8_t a_ = (a); \ -+ uint16x8_t result; \ -+ __asm__ ("mla %0.8h, %2.8h, %3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlaq_laneq_u32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t c_ = (c); \ -+ uint32x4_t b_ = (b); \ -+ uint32x4_t a_ = (a); \ -+ uint32x4_t result; \ -+ __asm__ ("mla %0.4s, %2.4s, %3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vmlaq_n_f32 (float32x4_t a, float32x4_t b, float32_t c) -+{ -+ float32x4_t result; -+ float32x4_t t1; -+ __asm__ ("fmul %1.4s, %3.4s, %4.s[0]; fadd %0.4s, %0.4s, %1.4s" -+ : "=w"(result), "=w"(t1) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vmlaq_n_f64 (float64x2_t a, float64x2_t b, float64_t c) -+{ -+ float64x2_t result; -+ float64x2_t t1; -+ __asm__ ("fmul %1.2d, %3.2d, %4.d[0]; fadd %0.2d, %0.2d, %1.2d" -+ : "=w"(result), "=w"(t1) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vmlaq_n_s16 (int16x8_t a, int16x8_t b, int16_t c) -+{ -+ int16x8_t result; -+ __asm__ ("mla %0.8h,%2.8h,%3.h[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vmlaq_n_s32 (int32x4_t a, int32x4_t b, int32_t c) -+{ -+ int32x4_t result; -+ __asm__ ("mla %0.4s,%2.4s,%3.s[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vmlaq_n_u16 (uint16x8_t a, uint16x8_t b, uint16_t c) -+{ -+ uint16x8_t result; -+ __asm__ ("mla %0.8h,%2.8h,%3.h[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vmlaq_n_u32 (uint32x4_t a, uint32x4_t b, uint32_t c) -+{ -+ uint32x4_t result; -+ __asm__ ("mla %0.4s,%2.4s,%3.s[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vmlaq_s8 (int8x16_t a, int8x16_t b, int8x16_t c) -+{ -+ int8x16_t result; -+ __asm__ ("mla %0.16b, %2.16b, %3.16b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vmlaq_s16 (int16x8_t a, int16x8_t b, int16x8_t c) -+{ -+ int16x8_t result; -+ __asm__ ("mla %0.8h, %2.8h, %3.8h" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vmlaq_s32 (int32x4_t a, int32x4_t b, int32x4_t c) -+{ -+ int32x4_t result; -+ __asm__ ("mla %0.4s, %2.4s, %3.4s" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vmlaq_u8 (uint8x16_t a, uint8x16_t b, uint8x16_t c) -+{ -+ uint8x16_t result; -+ __asm__ ("mla %0.16b, %2.16b, %3.16b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vmlaq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c) -+{ -+ uint16x8_t result; -+ __asm__ ("mla %0.8h, %2.8h, %3.8h" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vmlaq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c) -+{ -+ uint32x4_t result; -+ __asm__ ("mla %0.4s, %2.4s, %3.4s" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vmls_lane_f32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ float32x4_t c_ = (c); \ -+ float32x2_t b_ = (b); \ -+ float32x2_t a_ = (a); \ -+ float32x2_t result; \ -+ float32x2_t t1; \ -+ __asm__ ("fmul %1.2s, %3.2s, %4.s[%5]; fsub %0.2s, %0.2s, %1.2s" \ -+ : "=w"(result), "=w"(t1) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmls_lane_s16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t c_ = (c); \ -+ int16x4_t b_ = (b); \ -+ int16x4_t a_ = (a); \ -+ int16x4_t result; \ -+ __asm__ ("mls %0.4h,%2.4h,%3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmls_lane_s32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t c_ = (c); \ -+ int32x2_t b_ = (b); \ -+ int32x2_t a_ = (a); \ -+ int32x2_t result; \ -+ __asm__ ("mls %0.2s,%2.2s,%3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmls_lane_u16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t c_ = (c); \ -+ uint16x4_t b_ = (b); \ -+ uint16x4_t a_ = (a); \ -+ uint16x4_t result; \ -+ __asm__ ("mls %0.4h,%2.4h,%3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmls_lane_u32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t c_ = (c); \ -+ uint32x2_t b_ = (b); \ -+ uint32x2_t a_ = (a); \ -+ uint32x2_t result; \ -+ __asm__ ("mls %0.2s,%2.2s,%3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vmls_n_f32 (float32x2_t a, float32x2_t b, float32_t c) -+{ -+ float32x2_t result; -+ float32x2_t t1; -+ __asm__ ("fmul %1.2s, %3.2s, %4.s[0]; fsub %0.2s, %0.2s, %1.2s" -+ : "=w"(result), "=w"(t1) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vmls_n_s16 (int16x4_t a, int16x4_t b, int16_t c) -+{ -+ int16x4_t result; -+ __asm__ ("mls %0.4h, %2.4h, %3.h[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vmls_n_s32 (int32x2_t a, int32x2_t b, int32_t c) -+{ -+ int32x2_t result; -+ __asm__ ("mls %0.2s, %2.2s, %3.s[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vmls_n_u16 (uint16x4_t a, uint16x4_t b, uint16_t c) -+{ -+ uint16x4_t result; -+ __asm__ ("mls %0.4h, %2.4h, %3.h[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vmls_n_u32 (uint32x2_t a, uint32x2_t b, uint32_t c) -+{ -+ uint32x2_t result; -+ __asm__ ("mls %0.2s, %2.2s, %3.s[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vmls_s8 (int8x8_t a, int8x8_t b, int8x8_t c) -+{ -+ int8x8_t result; -+ __asm__ ("mls %0.8b,%2.8b,%3.8b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vmls_s16 (int16x4_t a, int16x4_t b, int16x4_t c) -+{ -+ int16x4_t result; -+ __asm__ ("mls %0.4h,%2.4h,%3.4h" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vmls_s32 (int32x2_t a, int32x2_t b, int32x2_t c) -+{ -+ int32x2_t result; -+ __asm__ ("mls %0.2s,%2.2s,%3.2s" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vmls_u8 (uint8x8_t a, uint8x8_t b, uint8x8_t c) -+{ -+ uint8x8_t result; -+ __asm__ ("mls %0.8b,%2.8b,%3.8b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vmls_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t c) -+{ -+ uint16x4_t result; -+ __asm__ ("mls %0.4h,%2.4h,%3.4h" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vmls_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t c) -+{ -+ uint32x2_t result; -+ __asm__ ("mls %0.2s,%2.2s,%3.2s" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vmlsl_high_lane_s16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t c_ = (c); \ -+ int16x8_t b_ = (b); \ -+ int32x4_t a_ = (a); \ -+ int32x4_t result; \ -+ __asm__ ("smlsl2 %0.4s, %2.8h, %3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlsl_high_lane_s32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t c_ = (c); \ -+ int32x4_t b_ = (b); \ -+ int64x2_t a_ = (a); \ -+ int64x2_t result; \ -+ __asm__ ("smlsl2 %0.2d, %2.4s, %3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlsl_high_lane_u16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t c_ = (c); \ -+ uint16x8_t b_ = (b); \ -+ uint32x4_t a_ = (a); \ -+ uint32x4_t result; \ -+ __asm__ ("umlsl2 %0.4s, %2.8h, %3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlsl_high_lane_u32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t c_ = (c); \ -+ uint32x4_t b_ = (b); \ -+ uint64x2_t a_ = (a); \ -+ uint64x2_t result; \ -+ __asm__ ("umlsl2 %0.2d, %2.4s, %3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlsl_high_laneq_s16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t c_ = (c); \ -+ int16x8_t b_ = (b); \ -+ int32x4_t a_ = (a); \ -+ int32x4_t result; \ -+ __asm__ ("smlsl2 %0.4s, %2.8h, %3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlsl_high_laneq_s32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t c_ = (c); \ -+ int32x4_t b_ = (b); \ -+ int64x2_t a_ = (a); \ -+ int64x2_t result; \ -+ __asm__ ("smlsl2 %0.2d, %2.4s, %3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlsl_high_laneq_u16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t c_ = (c); \ -+ uint16x8_t b_ = (b); \ -+ uint32x4_t a_ = (a); \ -+ uint32x4_t result; \ -+ __asm__ ("umlsl2 %0.4s, %2.8h, %3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlsl_high_laneq_u32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t c_ = (c); \ -+ uint32x4_t b_ = (b); \ -+ uint64x2_t a_ = (a); \ -+ uint64x2_t result; \ -+ __asm__ ("umlsl2 %0.2d, %2.4s, %3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vmlsl_high_n_s16 (int32x4_t a, int16x8_t b, int16_t c) -+{ -+ int32x4_t result; -+ __asm__ ("smlsl2 %0.4s, %2.8h, %3.h[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vmlsl_high_n_s32 (int64x2_t a, int32x4_t b, int32_t c) -+{ -+ int64x2_t result; -+ __asm__ ("smlsl2 %0.2d, %2.4s, %3.s[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vmlsl_high_n_u16 (uint32x4_t a, uint16x8_t b, uint16_t c) -+{ -+ uint32x4_t result; -+ __asm__ ("umlsl2 %0.4s, %2.8h, %3.h[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vmlsl_high_n_u32 (uint64x2_t a, uint32x4_t b, uint32_t c) -+{ -+ uint64x2_t result; -+ __asm__ ("umlsl2 %0.2d, %2.4s, %3.s[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vmlsl_high_s8 (int16x8_t a, int8x16_t b, int8x16_t c) -+{ -+ int16x8_t result; -+ __asm__ ("smlsl2 %0.8h,%2.16b,%3.16b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vmlsl_high_s16 (int32x4_t a, int16x8_t b, int16x8_t c) -+{ -+ int32x4_t result; -+ __asm__ ("smlsl2 %0.4s,%2.8h,%3.8h" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vmlsl_high_s32 (int64x2_t a, int32x4_t b, int32x4_t c) -+{ -+ int64x2_t result; -+ __asm__ ("smlsl2 %0.2d,%2.4s,%3.4s" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vmlsl_high_u8 (uint16x8_t a, uint8x16_t b, uint8x16_t c) -+{ -+ uint16x8_t result; -+ __asm__ ("umlsl2 %0.8h,%2.16b,%3.16b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vmlsl_high_u16 (uint32x4_t a, uint16x8_t b, uint16x8_t c) -+{ -+ uint32x4_t result; -+ __asm__ ("umlsl2 %0.4s,%2.8h,%3.8h" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vmlsl_high_u32 (uint64x2_t a, uint32x4_t b, uint32x4_t c) -+{ -+ uint64x2_t result; -+ __asm__ ("umlsl2 %0.2d,%2.4s,%3.4s" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vmlsl_lane_s16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t c_ = (c); \ -+ int16x4_t b_ = (b); \ -+ int32x4_t a_ = (a); \ -+ int32x4_t result; \ -+ __asm__ ("smlsl %0.4s, %2.4h, %3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlsl_lane_s32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t c_ = (c); \ -+ int32x2_t b_ = (b); \ -+ int64x2_t a_ = (a); \ -+ int64x2_t result; \ -+ __asm__ ("smlsl %0.2d, %2.2s, %3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlsl_lane_u16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t c_ = (c); \ -+ uint16x4_t b_ = (b); \ -+ uint32x4_t a_ = (a); \ -+ uint32x4_t result; \ -+ __asm__ ("umlsl %0.4s, %2.4h, %3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlsl_lane_u32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t c_ = (c); \ -+ uint32x2_t b_ = (b); \ -+ uint64x2_t a_ = (a); \ -+ uint64x2_t result; \ -+ __asm__ ("umlsl %0.2d, %2.2s, %3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlsl_laneq_s16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t c_ = (c); \ -+ int16x4_t b_ = (b); \ -+ int32x4_t a_ = (a); \ -+ int32x4_t result; \ -+ __asm__ ("smlsl %0.4s, %2.4h, %3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlsl_laneq_s32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t c_ = (c); \ -+ int32x2_t b_ = (b); \ -+ int64x2_t a_ = (a); \ -+ int64x2_t result; \ -+ __asm__ ("smlsl %0.2d, %2.2s, %3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlsl_laneq_u16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t c_ = (c); \ -+ uint16x4_t b_ = (b); \ -+ uint32x4_t a_ = (a); \ -+ uint32x4_t result; \ -+ __asm__ ("umlsl %0.4s, %2.4h, %3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlsl_laneq_u32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t c_ = (c); \ -+ uint32x2_t b_ = (b); \ -+ uint64x2_t a_ = (a); \ -+ uint64x2_t result; \ -+ __asm__ ("umlsl %0.2d, %2.2s, %3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vmlsl_n_s16 (int32x4_t a, int16x4_t b, int16_t c) -+{ -+ int32x4_t result; -+ __asm__ ("smlsl %0.4s, %2.4h, %3.h[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vmlsl_n_s32 (int64x2_t a, int32x2_t b, int32_t c) -+{ -+ int64x2_t result; -+ __asm__ ("smlsl %0.2d, %2.2s, %3.s[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vmlsl_n_u16 (uint32x4_t a, uint16x4_t b, uint16_t c) -+{ -+ uint32x4_t result; -+ __asm__ ("umlsl %0.4s, %2.4h, %3.h[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vmlsl_n_u32 (uint64x2_t a, uint32x2_t b, uint32_t c) -+{ -+ uint64x2_t result; -+ __asm__ ("umlsl %0.2d, %2.2s, %3.s[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vmlsl_s8 (int16x8_t a, int8x8_t b, int8x8_t c) -+{ -+ int16x8_t result; -+ __asm__ ("smlsl %0.8h, %2.8b, %3.8b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vmlsl_s16 (int32x4_t a, int16x4_t b, int16x4_t c) -+{ -+ int32x4_t result; -+ __asm__ ("smlsl %0.4s, %2.4h, %3.4h" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vmlsl_s32 (int64x2_t a, int32x2_t b, int32x2_t c) -+{ -+ int64x2_t result; -+ __asm__ ("smlsl %0.2d, %2.2s, %3.2s" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vmlsl_u8 (uint16x8_t a, uint8x8_t b, uint8x8_t c) -+{ -+ uint16x8_t result; -+ __asm__ ("umlsl %0.8h, %2.8b, %3.8b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vmlsl_u16 (uint32x4_t a, uint16x4_t b, uint16x4_t c) -+{ -+ uint32x4_t result; -+ __asm__ ("umlsl %0.4s, %2.4h, %3.4h" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vmlsl_u32 (uint64x2_t a, uint32x2_t b, uint32x2_t c) -+{ -+ uint64x2_t result; -+ __asm__ ("umlsl %0.2d, %2.2s, %3.2s" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vmlsq_lane_f32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ float32x4_t c_ = (c); \ -+ float32x4_t b_ = (b); \ -+ float32x4_t a_ = (a); \ -+ float32x4_t result; \ -+ float32x4_t t1; \ -+ __asm__ ("fmul %1.4s, %3.4s, %4.s[%5]; fsub %0.4s, %0.4s, %1.4s" \ -+ : "=w"(result), "=w"(t1) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlsq_lane_s16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t c_ = (c); \ -+ int16x8_t b_ = (b); \ -+ int16x8_t a_ = (a); \ -+ int16x8_t result; \ -+ __asm__ ("mls %0.8h,%2.8h,%3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlsq_lane_s32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t c_ = (c); \ -+ int32x4_t b_ = (b); \ -+ int32x4_t a_ = (a); \ -+ int32x4_t result; \ -+ __asm__ ("mls %0.4s,%2.4s,%3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlsq_lane_u16(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t c_ = (c); \ -+ uint16x8_t b_ = (b); \ -+ uint16x8_t a_ = (a); \ -+ uint16x8_t result; \ -+ __asm__ ("mls %0.8h,%2.8h,%3.h[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlsq_lane_u32(a, b, c, d) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t c_ = (c); \ -+ uint32x4_t b_ = (b); \ -+ uint32x4_t a_ = (a); \ -+ uint32x4_t result; \ -+ __asm__ ("mls %0.4s,%2.4s,%3.s[%4]" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmlsq_laneq_f32(__a, __b, __c, __d) \ -+ __extension__ \ -+ ({ \ -+ float32x4_t __c_ = (__c); \ -+ float32x4_t __b_ = (__b); \ -+ float32x4_t __a_ = (__a); \ -+ float32x4_t __result; \ -+ float32x4_t __t1; \ -+ __asm__ ("fmul %1.4s, %3.4s, %4.s[%5]; fsub %0.4s, %0.4s, %1.4s" \ -+ : "=w"(__result), "=w"(__t1) \ -+ : "0"(__a_), "w"(__b_), "w"(__c_), "i"(__d) \ -+ : /* No clobbers */); \ -+ __result; \ -+ }) -+ -+#define vmlsq_laneq_s16(__a, __b, __c, __d) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t __c_ = (__c); \ -+ int16x8_t __b_ = (__b); \ -+ int16x8_t __a_ = (__a); \ -+ int16x8_t __result; \ -+ __asm__ ("mls %0.8h, %2.8h, %3.h[%4]" \ -+ : "=w"(__result) \ -+ : "0"(__a_), "w"(__b_), "w"(__c_), "i"(__d) \ -+ : /* No clobbers */); \ -+ __result; \ -+ }) -+ -+#define vmlsq_laneq_s32(__a, __b, __c, __d) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t __c_ = (__c); \ -+ int32x4_t __b_ = (__b); \ -+ int32x4_t __a_ = (__a); \ -+ int32x4_t __result; \ -+ __asm__ ("mls %0.4s, %2.4s, %3.s[%4]" \ -+ : "=w"(__result) \ -+ : "0"(__a_), "w"(__b_), "w"(__c_), "i"(__d) \ -+ : /* No clobbers */); \ -+ __result; \ -+ }) -+ -+#define vmlsq_laneq_u16(__a, __b, __c, __d) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t __c_ = (__c); \ -+ uint16x8_t __b_ = (__b); \ -+ uint16x8_t __a_ = (__a); \ -+ uint16x8_t __result; \ -+ __asm__ ("mls %0.8h, %2.8h, %3.h[%4]" \ -+ : "=w"(__result) \ -+ : "0"(__a_), "w"(__b_), "w"(__c_), "i"(__d) \ -+ : /* No clobbers */); \ -+ __result; \ -+ }) -+ -+#define vmlsq_laneq_u32(__a, __b, __c, __d) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t __c_ = (__c); \ -+ uint32x4_t __b_ = (__b); \ -+ uint32x4_t __a_ = (__a); \ -+ uint32x4_t __result; \ -+ __asm__ ("mls %0.4s, %2.4s, %3.s[%4]" \ -+ : "=w"(__result) \ -+ : "0"(__a_), "w"(__b_), "w"(__c_), "i"(__d) \ -+ : /* No clobbers */); \ -+ __result; \ -+ }) -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vmlsq_n_f32 (float32x4_t a, float32x4_t b, float32_t c) -+{ -+ float32x4_t result; -+ float32x4_t t1; -+ __asm__ ("fmul %1.4s, %3.4s, %4.s[0]; fsub %0.4s, %0.4s, %1.4s" -+ : "=w"(result), "=w"(t1) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vmlsq_n_f64 (float64x2_t a, float64x2_t b, float64_t c) -+{ -+ float64x2_t result; -+ float64x2_t t1; -+ __asm__ ("fmul %1.2d, %3.2d, %4.d[0]; fsub %0.2d, %0.2d, %1.2d" -+ : "=w"(result), "=w"(t1) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vmlsq_n_s16 (int16x8_t a, int16x8_t b, int16_t c) -+{ -+ int16x8_t result; -+ __asm__ ("mls %0.8h, %2.8h, %3.h[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vmlsq_n_s32 (int32x4_t a, int32x4_t b, int32_t c) -+{ -+ int32x4_t result; -+ __asm__ ("mls %0.4s, %2.4s, %3.s[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vmlsq_n_u16 (uint16x8_t a, uint16x8_t b, uint16_t c) -+{ -+ uint16x8_t result; -+ __asm__ ("mls %0.8h, %2.8h, %3.h[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vmlsq_n_u32 (uint32x4_t a, uint32x4_t b, uint32_t c) -+{ -+ uint32x4_t result; -+ __asm__ ("mls %0.4s, %2.4s, %3.s[0]" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vmlsq_s8 (int8x16_t a, int8x16_t b, int8x16_t c) -+{ -+ int8x16_t result; -+ __asm__ ("mls %0.16b,%2.16b,%3.16b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vmlsq_s16 (int16x8_t a, int16x8_t b, int16x8_t c) -+{ -+ int16x8_t result; -+ __asm__ ("mls %0.8h,%2.8h,%3.8h" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vmlsq_s32 (int32x4_t a, int32x4_t b, int32x4_t c) -+{ -+ int32x4_t result; -+ __asm__ ("mls %0.4s,%2.4s,%3.4s" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vmlsq_u8 (uint8x16_t a, uint8x16_t b, uint8x16_t c) -+{ -+ uint8x16_t result; -+ __asm__ ("mls %0.16b,%2.16b,%3.16b" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vmlsq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c) -+{ -+ uint16x8_t result; -+ __asm__ ("mls %0.8h,%2.8h,%3.8h" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vmlsq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c) -+{ -+ uint32x4_t result; -+ __asm__ ("mls %0.4s,%2.4s,%3.4s" -+ : "=w"(result) -+ : "0"(a), "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vmov_n_f32 (float32_t a) -+{ -+ float32x2_t result; -+ __asm__ ("dup %0.2s, %w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vmov_n_p8 (uint32_t a) -+{ -+ poly8x8_t result; -+ __asm__ ("dup %0.8b,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) -+vmov_n_p16 (uint32_t a) -+{ -+ poly16x4_t result; -+ __asm__ ("dup %0.4h,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vmov_n_s8 (int32_t a) -+{ -+ int8x8_t result; -+ __asm__ ("dup %0.8b,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vmov_n_s16 (int32_t a) -+{ -+ int16x4_t result; -+ __asm__ ("dup %0.4h,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vmov_n_s32 (int32_t a) -+{ -+ int32x2_t result; -+ __asm__ ("dup %0.2s,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vmov_n_s64 (int64_t a) -+{ -+ int64x1_t result; -+ __asm__ ("ins %0.d[0],%x1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vmov_n_u8 (uint32_t a) -+{ -+ uint8x8_t result; -+ __asm__ ("dup %0.8b,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vmov_n_u16 (uint32_t a) -+{ -+ uint16x4_t result; -+ __asm__ ("dup %0.4h,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vmov_n_u32 (uint32_t a) -+{ -+ uint32x2_t result; -+ __asm__ ("dup %0.2s,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vmov_n_u64 (uint64_t a) -+{ -+ uint64x1_t result; -+ __asm__ ("ins %0.d[0],%x1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vmovl_high_s8 (int8x16_t a) -+{ -+ int16x8_t result; -+ __asm__ ("sshll2 %0.8h,%1.16b,#0" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vmovl_high_s16 (int16x8_t a) -+{ -+ int32x4_t result; -+ __asm__ ("sshll2 %0.4s,%1.8h,#0" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vmovl_high_s32 (int32x4_t a) -+{ -+ int64x2_t result; -+ __asm__ ("sshll2 %0.2d,%1.4s,#0" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vmovl_high_u8 (uint8x16_t a) -+{ -+ uint16x8_t result; -+ __asm__ ("ushll2 %0.8h,%1.16b,#0" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vmovl_high_u16 (uint16x8_t a) -+{ -+ uint32x4_t result; -+ __asm__ ("ushll2 %0.4s,%1.8h,#0" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vmovl_high_u32 (uint32x4_t a) -+{ -+ uint64x2_t result; -+ __asm__ ("ushll2 %0.2d,%1.4s,#0" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vmovl_s8 (int8x8_t a) -+{ -+ int16x8_t result; -+ __asm__ ("sshll %0.8h,%1.8b,#0" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vmovl_s16 (int16x4_t a) -+{ -+ int32x4_t result; -+ __asm__ ("sshll %0.4s,%1.4h,#0" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vmovl_s32 (int32x2_t a) -+{ -+ int64x2_t result; -+ __asm__ ("sshll %0.2d,%1.2s,#0" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vmovl_u8 (uint8x8_t a) -+{ -+ uint16x8_t result; -+ __asm__ ("ushll %0.8h,%1.8b,#0" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vmovl_u16 (uint16x4_t a) -+{ -+ uint32x4_t result; -+ __asm__ ("ushll %0.4s,%1.4h,#0" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vmovl_u32 (uint32x2_t a) -+{ -+ uint64x2_t result; -+ __asm__ ("ushll %0.2d,%1.2s,#0" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vmovn_high_s16 (int8x8_t a, int16x8_t b) -+{ -+ int8x16_t result = vcombine_s8 (a, vcreate_s8 (UINT64_C (0x0))); -+ __asm__ ("xtn2 %0.16b,%2.8h" -+ : "+w"(result) -+ : "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vmovn_high_s32 (int16x4_t a, int32x4_t b) -+{ -+ int16x8_t result = vcombine_s16 (a, vcreate_s16 (UINT64_C (0x0))); -+ __asm__ ("xtn2 %0.8h,%2.4s" -+ : "+w"(result) -+ : "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vmovn_high_s64 (int32x2_t a, int64x2_t b) -+{ -+ int32x4_t result = vcombine_s32 (a, vcreate_s32 (UINT64_C (0x0))); -+ __asm__ ("xtn2 %0.4s,%2.2d" -+ : "+w"(result) -+ : "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vmovn_high_u16 (uint8x8_t a, uint16x8_t b) -+{ -+ uint8x16_t result = vcombine_u8 (a, vcreate_u8 (UINT64_C (0x0))); -+ __asm__ ("xtn2 %0.16b,%2.8h" -+ : "+w"(result) -+ : "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vmovn_high_u32 (uint16x4_t a, uint32x4_t b) -+{ -+ uint16x8_t result = vcombine_u16 (a, vcreate_u16 (UINT64_C (0x0))); -+ __asm__ ("xtn2 %0.8h,%2.4s" -+ : "+w"(result) -+ : "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vmovn_high_u64 (uint32x2_t a, uint64x2_t b) -+{ -+ uint32x4_t result = vcombine_u32 (a, vcreate_u32 (UINT64_C (0x0))); -+ __asm__ ("xtn2 %0.4s,%2.2d" -+ : "+w"(result) -+ : "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vmovn_s16 (int16x8_t a) -+{ -+ int8x8_t result; -+ __asm__ ("xtn %0.8b,%1.8h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vmovn_s32 (int32x4_t a) -+{ -+ int16x4_t result; -+ __asm__ ("xtn %0.4h,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vmovn_s64 (int64x2_t a) -+{ -+ int32x2_t result; -+ __asm__ ("xtn %0.2s,%1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vmovn_u16 (uint16x8_t a) -+{ -+ uint8x8_t result; -+ __asm__ ("xtn %0.8b,%1.8h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vmovn_u32 (uint32x4_t a) -+{ -+ uint16x4_t result; -+ __asm__ ("xtn %0.4h,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vmovn_u64 (uint64x2_t a) -+{ -+ uint32x2_t result; -+ __asm__ ("xtn %0.2s,%1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vmovq_n_f32 (float32_t a) -+{ -+ float32x4_t result; -+ __asm__ ("dup %0.4s, %w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vmovq_n_p8 (uint32_t a) -+{ -+ poly8x16_t result; -+ __asm__ ("dup %0.16b,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) -+vmovq_n_p16 (uint32_t a) -+{ -+ poly16x8_t result; -+ __asm__ ("dup %0.8h,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vmovq_n_s8 (int32_t a) -+{ -+ int8x16_t result; -+ __asm__ ("dup %0.16b,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vmovq_n_s16 (int32_t a) -+{ -+ int16x8_t result; -+ __asm__ ("dup %0.8h,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vmovq_n_s32 (int32_t a) -+{ -+ int32x4_t result; -+ __asm__ ("dup %0.4s,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vmovq_n_s64 (int64_t a) -+{ -+ int64x2_t result; -+ __asm__ ("dup %0.2d,%x1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vmovq_n_u8 (uint32_t a) -+{ -+ uint8x16_t result; -+ __asm__ ("dup %0.16b,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vmovq_n_u16 (uint32_t a) -+{ -+ uint16x8_t result; -+ __asm__ ("dup %0.8h,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vmovq_n_u32 (uint32_t a) -+{ -+ uint32x4_t result; -+ __asm__ ("dup %0.4s,%w1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vmovq_n_u64 (uint64_t a) -+{ -+ uint64x2_t result; -+ __asm__ ("dup %0.2d,%x1" -+ : "=w"(result) -+ : "r"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vmul_lane_f32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float32x4_t b_ = (b); \ -+ float32x2_t a_ = (a); \ -+ float32x2_t result; \ -+ __asm__ ("fmul %0.2s,%1.2s,%2.s[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmul_lane_s16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t b_ = (b); \ -+ int16x4_t a_ = (a); \ -+ int16x4_t result; \ -+ __asm__ ("mul %0.4h,%1.4h,%2.h[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmul_lane_s32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t b_ = (b); \ -+ int32x2_t a_ = (a); \ -+ int32x2_t result; \ -+ __asm__ ("mul %0.2s,%1.2s,%2.s[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmul_lane_u16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t b_ = (b); \ -+ uint16x4_t a_ = (a); \ -+ uint16x4_t result; \ -+ __asm__ ("mul %0.4h,%1.4h,%2.h[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmul_lane_u32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t b_ = (b); \ -+ uint32x2_t a_ = (a); \ -+ uint32x2_t result; \ -+ __asm__ ("mul %0.2s, %1.2s, %2.s[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmul_laneq_f32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float32x4_t b_ = (b); \ -+ float32x2_t a_ = (a); \ -+ float32x2_t result; \ -+ __asm__ ("fmul %0.2s, %1.2s, %2.s[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmul_laneq_s16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t b_ = (b); \ -+ int16x4_t a_ = (a); \ -+ int16x4_t result; \ -+ __asm__ ("mul %0.4h, %1.4h, %2.h[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmul_laneq_s32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t b_ = (b); \ -+ int32x2_t a_ = (a); \ -+ int32x2_t result; \ -+ __asm__ ("mul %0.2s, %1.2s, %2.s[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmul_laneq_u16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t b_ = (b); \ -+ uint16x4_t a_ = (a); \ -+ uint16x4_t result; \ -+ __asm__ ("mul %0.4h, %1.4h, %2.h[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmul_laneq_u32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t b_ = (b); \ -+ uint32x2_t a_ = (a); \ -+ uint32x2_t result; \ -+ __asm__ ("mul %0.2s, %1.2s, %2.s[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vmul_n_f32 (float32x2_t a, float32_t b) -+{ -+ float32x2_t result; -+ __asm__ ("fmul %0.2s,%1.2s,%2.s[0]" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vmul_n_s16 (int16x4_t a, int16_t b) -+{ -+ int16x4_t result; -+ __asm__ ("mul %0.4h,%1.4h,%2.h[0]" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vmul_n_s32 (int32x2_t a, int32_t b) -+{ -+ int32x2_t result; -+ __asm__ ("mul %0.2s,%1.2s,%2.s[0]" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vmul_n_u16 (uint16x4_t a, uint16_t b) -+{ -+ uint16x4_t result; -+ __asm__ ("mul %0.4h,%1.4h,%2.h[0]" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vmul_n_u32 (uint32x2_t a, uint32_t b) -+{ -+ uint32x2_t result; -+ __asm__ ("mul %0.2s,%1.2s,%2.s[0]" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vmuld_lane_f64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float64x2_t b_ = (b); \ -+ float64_t a_ = (a); \ -+ float64_t result; \ -+ __asm__ ("fmul %d0,%d1,%2.d[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmull_high_lane_s16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t b_ = (b); \ -+ int16x8_t a_ = (a); \ -+ int32x4_t result; \ -+ __asm__ ("smull2 %0.4s, %1.8h, %2.h[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmull_high_lane_s32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t b_ = (b); \ -+ int32x4_t a_ = (a); \ -+ int64x2_t result; \ -+ __asm__ ("smull2 %0.2d, %1.4s, %2.s[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmull_high_lane_u16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t b_ = (b); \ -+ uint16x8_t a_ = (a); \ -+ uint32x4_t result; \ -+ __asm__ ("umull2 %0.4s, %1.8h, %2.h[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmull_high_lane_u32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t b_ = (b); \ -+ uint32x4_t a_ = (a); \ -+ uint64x2_t result; \ -+ __asm__ ("umull2 %0.2d, %1.4s, %2.s[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmull_high_laneq_s16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t b_ = (b); \ -+ int16x8_t a_ = (a); \ -+ int32x4_t result; \ -+ __asm__ ("smull2 %0.4s, %1.8h, %2.h[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmull_high_laneq_s32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t b_ = (b); \ -+ int32x4_t a_ = (a); \ -+ int64x2_t result; \ -+ __asm__ ("smull2 %0.2d, %1.4s, %2.s[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmull_high_laneq_u16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t b_ = (b); \ -+ uint16x8_t a_ = (a); \ -+ uint32x4_t result; \ -+ __asm__ ("umull2 %0.4s, %1.8h, %2.h[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmull_high_laneq_u32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t b_ = (b); \ -+ uint32x4_t a_ = (a); \ -+ uint64x2_t result; \ -+ __asm__ ("umull2 %0.2d, %1.4s, %2.s[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vmull_high_n_s16 (int16x8_t a, int16_t b) -+{ -+ int32x4_t result; -+ __asm__ ("smull2 %0.4s,%1.8h,%2.h[0]" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vmull_high_n_s32 (int32x4_t a, int32_t b) -+{ -+ int64x2_t result; -+ __asm__ ("smull2 %0.2d,%1.4s,%2.s[0]" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vmull_high_n_u16 (uint16x8_t a, uint16_t b) -+{ -+ uint32x4_t result; -+ __asm__ ("umull2 %0.4s,%1.8h,%2.h[0]" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vmull_high_n_u32 (uint32x4_t a, uint32_t b) -+{ -+ uint64x2_t result; -+ __asm__ ("umull2 %0.2d,%1.4s,%2.s[0]" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) -+vmull_high_p8 (poly8x16_t a, poly8x16_t b) -+{ -+ poly16x8_t result; -+ __asm__ ("pmull2 %0.8h,%1.16b,%2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vmull_high_s8 (int8x16_t a, int8x16_t b) -+{ -+ int16x8_t result; -+ __asm__ ("smull2 %0.8h,%1.16b,%2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vmull_high_s16 (int16x8_t a, int16x8_t b) -+{ -+ int32x4_t result; -+ __asm__ ("smull2 %0.4s,%1.8h,%2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vmull_high_s32 (int32x4_t a, int32x4_t b) -+{ -+ int64x2_t result; -+ __asm__ ("smull2 %0.2d,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vmull_high_u8 (uint8x16_t a, uint8x16_t b) -+{ -+ uint16x8_t result; -+ __asm__ ("umull2 %0.8h,%1.16b,%2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vmull_high_u16 (uint16x8_t a, uint16x8_t b) -+{ -+ uint32x4_t result; -+ __asm__ ("umull2 %0.4s,%1.8h,%2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vmull_high_u32 (uint32x4_t a, uint32x4_t b) -+{ -+ uint64x2_t result; -+ __asm__ ("umull2 %0.2d,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vmull_lane_s16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t b_ = (b); \ -+ int16x4_t a_ = (a); \ -+ int32x4_t result; \ -+ __asm__ ("smull %0.4s,%1.4h,%2.h[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmull_lane_s32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t b_ = (b); \ -+ int32x2_t a_ = (a); \ -+ int64x2_t result; \ -+ __asm__ ("smull %0.2d,%1.2s,%2.s[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmull_lane_u16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t b_ = (b); \ -+ uint16x4_t a_ = (a); \ -+ uint32x4_t result; \ -+ __asm__ ("umull %0.4s,%1.4h,%2.h[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmull_lane_u32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t b_ = (b); \ -+ uint32x2_t a_ = (a); \ -+ uint64x2_t result; \ -+ __asm__ ("umull %0.2d, %1.2s, %2.s[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmull_laneq_s16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t b_ = (b); \ -+ int16x4_t a_ = (a); \ -+ int32x4_t result; \ -+ __asm__ ("smull %0.4s, %1.4h, %2.h[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmull_laneq_s32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t b_ = (b); \ -+ int32x2_t a_ = (a); \ -+ int64x2_t result; \ -+ __asm__ ("smull %0.2d, %1.2s, %2.s[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmull_laneq_u16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t b_ = (b); \ -+ uint16x4_t a_ = (a); \ -+ uint32x4_t result; \ -+ __asm__ ("umull %0.4s, %1.4h, %2.h[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmull_laneq_u32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t b_ = (b); \ -+ uint32x2_t a_ = (a); \ -+ uint64x2_t result; \ -+ __asm__ ("umull %0.2d, %1.2s, %2.s[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vmull_n_s16 (int16x4_t a, int16_t b) -+{ -+ int32x4_t result; -+ __asm__ ("smull %0.4s,%1.4h,%2.h[0]" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vmull_n_s32 (int32x2_t a, int32_t b) -+{ -+ int64x2_t result; -+ __asm__ ("smull %0.2d,%1.2s,%2.s[0]" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vmull_n_u16 (uint16x4_t a, uint16_t b) -+{ -+ uint32x4_t result; -+ __asm__ ("umull %0.4s,%1.4h,%2.h[0]" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vmull_n_u32 (uint32x2_t a, uint32_t b) -+{ -+ uint64x2_t result; -+ __asm__ ("umull %0.2d,%1.2s,%2.s[0]" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) -+vmull_p8 (poly8x8_t a, poly8x8_t b) -+{ -+ poly16x8_t result; -+ __asm__ ("pmull %0.8h, %1.8b, %2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vmull_s8 (int8x8_t a, int8x8_t b) -+{ -+ int16x8_t result; -+ __asm__ ("smull %0.8h, %1.8b, %2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vmull_s16 (int16x4_t a, int16x4_t b) -+{ -+ int32x4_t result; -+ __asm__ ("smull %0.4s, %1.4h, %2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vmull_s32 (int32x2_t a, int32x2_t b) -+{ -+ int64x2_t result; -+ __asm__ ("smull %0.2d, %1.2s, %2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vmull_u8 (uint8x8_t a, uint8x8_t b) -+{ -+ uint16x8_t result; -+ __asm__ ("umull %0.8h, %1.8b, %2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vmull_u16 (uint16x4_t a, uint16x4_t b) -+{ -+ uint32x4_t result; -+ __asm__ ("umull %0.4s, %1.4h, %2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vmull_u32 (uint32x2_t a, uint32x2_t b) -+{ -+ uint64x2_t result; -+ __asm__ ("umull %0.2d, %1.2s, %2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vmulq_lane_f32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float32x4_t b_ = (b); \ -+ float32x4_t a_ = (a); \ -+ float32x4_t result; \ -+ __asm__ ("fmul %0.4s, %1.4s, %2.s[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmulq_lane_f64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float64x2_t b_ = (b); \ -+ float64x2_t a_ = (a); \ -+ float64x2_t result; \ -+ __asm__ ("fmul %0.2d,%1.2d,%2.d[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmulq_lane_s16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t b_ = (b); \ -+ int16x8_t a_ = (a); \ -+ int16x8_t result; \ -+ __asm__ ("mul %0.8h,%1.8h,%2.h[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmulq_lane_s32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t b_ = (b); \ -+ int32x4_t a_ = (a); \ -+ int32x4_t result; \ -+ __asm__ ("mul %0.4s,%1.4s,%2.s[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmulq_lane_u16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t b_ = (b); \ -+ uint16x8_t a_ = (a); \ -+ uint16x8_t result; \ -+ __asm__ ("mul %0.8h,%1.8h,%2.h[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmulq_lane_u32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t b_ = (b); \ -+ uint32x4_t a_ = (a); \ -+ uint32x4_t result; \ -+ __asm__ ("mul %0.4s, %1.4s, %2.s[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmulq_laneq_f32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float32x4_t b_ = (b); \ -+ float32x4_t a_ = (a); \ -+ float32x4_t result; \ -+ __asm__ ("fmul %0.4s, %1.4s, %2.s[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmulq_laneq_f64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float64x2_t b_ = (b); \ -+ float64x2_t a_ = (a); \ -+ float64x2_t result; \ -+ __asm__ ("fmul %0.2d,%1.2d,%2.d[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmulq_laneq_s16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t b_ = (b); \ -+ int16x8_t a_ = (a); \ -+ int16x8_t result; \ -+ __asm__ ("mul %0.8h, %1.8h, %2.h[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmulq_laneq_s32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t b_ = (b); \ -+ int32x4_t a_ = (a); \ -+ int32x4_t result; \ -+ __asm__ ("mul %0.4s, %1.4s, %2.s[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmulq_laneq_u16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t b_ = (b); \ -+ uint16x8_t a_ = (a); \ -+ uint16x8_t result; \ -+ __asm__ ("mul %0.8h, %1.8h, %2.h[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmulq_laneq_u32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t b_ = (b); \ -+ uint32x4_t a_ = (a); \ -+ uint32x4_t result; \ -+ __asm__ ("mul %0.4s, %1.4s, %2.s[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vmulq_n_f32 (float32x4_t a, float32_t b) -+{ -+ float32x4_t result; -+ __asm__ ("fmul %0.4s,%1.4s,%2.s[0]" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vmulq_n_f64 (float64x2_t a, float64_t b) -+{ -+ float64x2_t result; -+ __asm__ ("fmul %0.2d,%1.2d,%2.d[0]" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vmulq_n_s16 (int16x8_t a, int16_t b) -+{ -+ int16x8_t result; -+ __asm__ ("mul %0.8h,%1.8h,%2.h[0]" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vmulq_n_s32 (int32x4_t a, int32_t b) -+{ -+ int32x4_t result; -+ __asm__ ("mul %0.4s,%1.4s,%2.s[0]" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vmulq_n_u16 (uint16x8_t a, uint16_t b) -+{ -+ uint16x8_t result; -+ __asm__ ("mul %0.8h,%1.8h,%2.h[0]" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vmulq_n_u32 (uint32x4_t a, uint32_t b) -+{ -+ uint32x4_t result; -+ __asm__ ("mul %0.4s,%1.4s,%2.s[0]" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vmuls_lane_f32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float32x4_t b_ = (b); \ -+ float32_t a_ = (a); \ -+ float32_t result; \ -+ __asm__ ("fmul %s0,%s1,%2.s[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vmulx_f32 (float32x2_t a, float32x2_t b) -+{ -+ float32x2_t result; -+ __asm__ ("fmulx %0.2s,%1.2s,%2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vmulx_lane_f32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float32x4_t b_ = (b); \ -+ float32x2_t a_ = (a); \ -+ float32x2_t result; \ -+ __asm__ ("fmulx %0.2s,%1.2s,%2.s[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -+vmulxd_f64 (float64_t a, float64_t b) -+{ -+ float64_t result; -+ __asm__ ("fmulx %d0, %d1, %d2" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vmulxq_f32 (float32x4_t a, float32x4_t b) -+{ -+ float32x4_t result; -+ __asm__ ("fmulx %0.4s,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vmulxq_f64 (float64x2_t a, float64x2_t b) -+{ -+ float64x2_t result; -+ __asm__ ("fmulx %0.2d,%1.2d,%2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vmulxq_lane_f32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float32x4_t b_ = (b); \ -+ float32x4_t a_ = (a); \ -+ float32x4_t result; \ -+ __asm__ ("fmulx %0.4s,%1.4s,%2.s[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vmulxq_lane_f64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float64x2_t b_ = (b); \ -+ float64x2_t a_ = (a); \ -+ float64x2_t result; \ -+ __asm__ ("fmulx %0.2d,%1.2d,%2.d[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vmulxs_f32 (float32_t a, float32_t b) -+{ -+ float32_t result; -+ __asm__ ("fmulx %s0, %s1, %s2" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vmvn_p8 (poly8x8_t a) -+{ -+ poly8x8_t result; -+ __asm__ ("mvn %0.8b,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vmvn_s8 (int8x8_t a) -+{ -+ int8x8_t result; -+ __asm__ ("mvn %0.8b,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vmvn_s16 (int16x4_t a) -+{ -+ int16x4_t result; -+ __asm__ ("mvn %0.8b,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vmvn_s32 (int32x2_t a) -+{ -+ int32x2_t result; -+ __asm__ ("mvn %0.8b,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vmvn_u8 (uint8x8_t a) -+{ -+ uint8x8_t result; -+ __asm__ ("mvn %0.8b,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vmvn_u16 (uint16x4_t a) -+{ -+ uint16x4_t result; -+ __asm__ ("mvn %0.8b,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vmvn_u32 (uint32x2_t a) -+{ -+ uint32x2_t result; -+ __asm__ ("mvn %0.8b,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vmvnq_p8 (poly8x16_t a) -+{ -+ poly8x16_t result; -+ __asm__ ("mvn %0.16b,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vmvnq_s8 (int8x16_t a) -+{ -+ int8x16_t result; -+ __asm__ ("mvn %0.16b,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vmvnq_s16 (int16x8_t a) -+{ -+ int16x8_t result; -+ __asm__ ("mvn %0.16b,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vmvnq_s32 (int32x4_t a) -+{ -+ int32x4_t result; -+ __asm__ ("mvn %0.16b,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vmvnq_u8 (uint8x16_t a) -+{ -+ uint8x16_t result; -+ __asm__ ("mvn %0.16b,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vmvnq_u16 (uint16x8_t a) -+{ -+ uint16x8_t result; -+ __asm__ ("mvn %0.16b,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vmvnq_u32 (uint32x4_t a) -+{ -+ uint32x4_t result; -+ __asm__ ("mvn %0.16b,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vneg_f32 (float32x2_t a) -+{ -+ float32x2_t result; -+ __asm__ ("fneg %0.2s,%1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vneg_s8 (int8x8_t a) -+{ -+ int8x8_t result; -+ __asm__ ("neg %0.8b,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vneg_s16 (int16x4_t a) -+{ -+ int16x4_t result; -+ __asm__ ("neg %0.4h,%1.4h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vneg_s32 (int32x2_t a) -+{ -+ int32x2_t result; -+ __asm__ ("neg %0.2s,%1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vnegq_f32 (float32x4_t a) -+{ -+ float32x4_t result; -+ __asm__ ("fneg %0.4s,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vnegq_f64 (float64x2_t a) -+{ -+ float64x2_t result; -+ __asm__ ("fneg %0.2d,%1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vnegq_s8 (int8x16_t a) -+{ -+ int8x16_t result; -+ __asm__ ("neg %0.16b,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vnegq_s16 (int16x8_t a) -+{ -+ int16x8_t result; -+ __asm__ ("neg %0.8h,%1.8h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vnegq_s32 (int32x4_t a) -+{ -+ int32x4_t result; -+ __asm__ ("neg %0.4s,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vnegq_s64 (int64x2_t a) -+{ -+ int64x2_t result; -+ __asm__ ("neg %0.2d,%1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vpadal_s8 (int16x4_t a, int8x8_t b) -+{ -+ int16x4_t result; -+ __asm__ ("sadalp %0.4h,%2.8b" -+ : "=w"(result) -+ : "0"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vpadal_s16 (int32x2_t a, int16x4_t b) -+{ -+ int32x2_t result; -+ __asm__ ("sadalp %0.2s,%2.4h" -+ : "=w"(result) -+ : "0"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vpadal_s32 (int64x1_t a, int32x2_t b) -+{ -+ int64x1_t result; -+ __asm__ ("sadalp %0.1d,%2.2s" -+ : "=w"(result) -+ : "0"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vpadal_u8 (uint16x4_t a, uint8x8_t b) -+{ -+ uint16x4_t result; -+ __asm__ ("uadalp %0.4h,%2.8b" -+ : "=w"(result) -+ : "0"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vpadal_u16 (uint32x2_t a, uint16x4_t b) -+{ -+ uint32x2_t result; -+ __asm__ ("uadalp %0.2s,%2.4h" -+ : "=w"(result) -+ : "0"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vpadal_u32 (uint64x1_t a, uint32x2_t b) -+{ -+ uint64x1_t result; -+ __asm__ ("uadalp %0.1d,%2.2s" -+ : "=w"(result) -+ : "0"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vpadalq_s8 (int16x8_t a, int8x16_t b) -+{ -+ int16x8_t result; -+ __asm__ ("sadalp %0.8h,%2.16b" -+ : "=w"(result) -+ : "0"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vpadalq_s16 (int32x4_t a, int16x8_t b) -+{ -+ int32x4_t result; -+ __asm__ ("sadalp %0.4s,%2.8h" -+ : "=w"(result) -+ : "0"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vpadalq_s32 (int64x2_t a, int32x4_t b) -+{ -+ int64x2_t result; -+ __asm__ ("sadalp %0.2d,%2.4s" -+ : "=w"(result) -+ : "0"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vpadalq_u8 (uint16x8_t a, uint8x16_t b) -+{ -+ uint16x8_t result; -+ __asm__ ("uadalp %0.8h,%2.16b" -+ : "=w"(result) -+ : "0"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vpadalq_u16 (uint32x4_t a, uint16x8_t b) -+{ -+ uint32x4_t result; -+ __asm__ ("uadalp %0.4s,%2.8h" -+ : "=w"(result) -+ : "0"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vpadalq_u32 (uint64x2_t a, uint32x4_t b) -+{ -+ uint64x2_t result; -+ __asm__ ("uadalp %0.2d,%2.4s" -+ : "=w"(result) -+ : "0"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vpadd_f32 (float32x2_t a, float32x2_t b) -+{ -+ float32x2_t result; -+ __asm__ ("faddp %0.2s,%1.2s,%2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vpadd_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return __builtin_aarch64_addpv8qi (__a, __b); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vpadd_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return __builtin_aarch64_addpv4hi (__a, __b); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vpadd_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return __builtin_aarch64_addpv2si (__a, __b); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vpadd_u8 (uint8x8_t __a, uint8x8_t __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_addpv8qi ((int8x8_t) __a, -+ (int8x8_t) __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vpadd_u16 (uint16x4_t __a, uint16x4_t __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_addpv4hi ((int16x4_t) __a, -+ (int16x4_t) __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vpadd_u32 (uint32x2_t __a, uint32x2_t __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_addpv2si ((int32x2_t) __a, -+ (int32x2_t) __b); -+} -+ -+__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -+vpaddd_f64 (float64x2_t a) -+{ -+ float64_t result; -+ __asm__ ("faddp %d0,%1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vpaddl_s8 (int8x8_t a) -+{ -+ int16x4_t result; -+ __asm__ ("saddlp %0.4h,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vpaddl_s16 (int16x4_t a) -+{ -+ int32x2_t result; -+ __asm__ ("saddlp %0.2s,%1.4h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vpaddl_s32 (int32x2_t a) -+{ -+ int64x1_t result; -+ __asm__ ("saddlp %0.1d,%1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vpaddl_u8 (uint8x8_t a) -+{ -+ uint16x4_t result; -+ __asm__ ("uaddlp %0.4h,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vpaddl_u16 (uint16x4_t a) -+{ -+ uint32x2_t result; -+ __asm__ ("uaddlp %0.2s,%1.4h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vpaddl_u32 (uint32x2_t a) -+{ -+ uint64x1_t result; -+ __asm__ ("uaddlp %0.1d,%1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vpaddlq_s8 (int8x16_t a) -+{ -+ int16x8_t result; -+ __asm__ ("saddlp %0.8h,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vpaddlq_s16 (int16x8_t a) -+{ -+ int32x4_t result; -+ __asm__ ("saddlp %0.4s,%1.8h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vpaddlq_s32 (int32x4_t a) -+{ -+ int64x2_t result; -+ __asm__ ("saddlp %0.2d,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vpaddlq_u8 (uint8x16_t a) -+{ -+ uint16x8_t result; -+ __asm__ ("uaddlp %0.8h,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vpaddlq_u16 (uint16x8_t a) -+{ -+ uint32x4_t result; -+ __asm__ ("uaddlp %0.4s,%1.8h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vpaddlq_u32 (uint32x4_t a) -+{ -+ uint64x2_t result; -+ __asm__ ("uaddlp %0.2d,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vpaddq_f32 (float32x4_t a, float32x4_t b) -+{ -+ float32x4_t result; -+ __asm__ ("faddp %0.4s,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vpaddq_f64 (float64x2_t a, float64x2_t b) -+{ -+ float64x2_t result; -+ __asm__ ("faddp %0.2d,%1.2d,%2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vpaddq_s8 (int8x16_t a, int8x16_t b) -+{ -+ int8x16_t result; -+ __asm__ ("addp %0.16b,%1.16b,%2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vpaddq_s16 (int16x8_t a, int16x8_t b) -+{ -+ int16x8_t result; -+ __asm__ ("addp %0.8h,%1.8h,%2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vpaddq_s32 (int32x4_t a, int32x4_t b) -+{ -+ int32x4_t result; -+ __asm__ ("addp %0.4s,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vpaddq_s64 (int64x2_t a, int64x2_t b) -+{ -+ int64x2_t result; -+ __asm__ ("addp %0.2d,%1.2d,%2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vpaddq_u8 (uint8x16_t a, uint8x16_t b) -+{ -+ uint8x16_t result; -+ __asm__ ("addp %0.16b,%1.16b,%2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vpaddq_u16 (uint16x8_t a, uint16x8_t b) -+{ -+ uint16x8_t result; -+ __asm__ ("addp %0.8h,%1.8h,%2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vpaddq_u32 (uint32x4_t a, uint32x4_t b) -+{ -+ uint32x4_t result; -+ __asm__ ("addp %0.4s,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vpaddq_u64 (uint64x2_t a, uint64x2_t b) -+{ -+ uint64x2_t result; -+ __asm__ ("addp %0.2d,%1.2d,%2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vpadds_f32 (float32x2_t a) -+{ -+ float32_t result; -+ __asm__ ("faddp %s0,%1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vpmax_f32 (float32x2_t a, float32x2_t b) -+{ -+ float32x2_t result; -+ __asm__ ("fmaxp %0.2s, %1.2s, %2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vpmax_s8 (int8x8_t a, int8x8_t b) -+{ -+ int8x8_t result; -+ __asm__ ("smaxp %0.8b, %1.8b, %2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vpmax_s16 (int16x4_t a, int16x4_t b) -+{ -+ int16x4_t result; -+ __asm__ ("smaxp %0.4h, %1.4h, %2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vpmax_s32 (int32x2_t a, int32x2_t b) -+{ -+ int32x2_t result; -+ __asm__ ("smaxp %0.2s, %1.2s, %2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vpmax_u8 (uint8x8_t a, uint8x8_t b) -+{ -+ uint8x8_t result; -+ __asm__ ("umaxp %0.8b, %1.8b, %2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vpmax_u16 (uint16x4_t a, uint16x4_t b) -+{ -+ uint16x4_t result; -+ __asm__ ("umaxp %0.4h, %1.4h, %2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vpmax_u32 (uint32x2_t a, uint32x2_t b) -+{ -+ uint32x2_t result; -+ __asm__ ("umaxp %0.2s, %1.2s, %2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vpmaxnm_f32 (float32x2_t a, float32x2_t b) -+{ -+ float32x2_t result; -+ __asm__ ("fmaxnmp %0.2s,%1.2s,%2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vpmaxnmq_f32 (float32x4_t a, float32x4_t b) -+{ -+ float32x4_t result; -+ __asm__ ("fmaxnmp %0.4s,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vpmaxnmq_f64 (float64x2_t a, float64x2_t b) -+{ -+ float64x2_t result; -+ __asm__ ("fmaxnmp %0.2d,%1.2d,%2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -+vpmaxnmqd_f64 (float64x2_t a) -+{ -+ float64_t result; -+ __asm__ ("fmaxnmp %d0,%1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vpmaxnms_f32 (float32x2_t a) -+{ -+ float32_t result; -+ __asm__ ("fmaxnmp %s0,%1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vpmaxq_f32 (float32x4_t a, float32x4_t b) -+{ -+ float32x4_t result; -+ __asm__ ("fmaxp %0.4s, %1.4s, %2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vpmaxq_f64 (float64x2_t a, float64x2_t b) -+{ -+ float64x2_t result; -+ __asm__ ("fmaxp %0.2d, %1.2d, %2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vpmaxq_s8 (int8x16_t a, int8x16_t b) -+{ -+ int8x16_t result; -+ __asm__ ("smaxp %0.16b, %1.16b, %2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vpmaxq_s16 (int16x8_t a, int16x8_t b) -+{ -+ int16x8_t result; -+ __asm__ ("smaxp %0.8h, %1.8h, %2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vpmaxq_s32 (int32x4_t a, int32x4_t b) -+{ -+ int32x4_t result; -+ __asm__ ("smaxp %0.4s, %1.4s, %2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vpmaxq_u8 (uint8x16_t a, uint8x16_t b) -+{ -+ uint8x16_t result; -+ __asm__ ("umaxp %0.16b, %1.16b, %2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vpmaxq_u16 (uint16x8_t a, uint16x8_t b) -+{ -+ uint16x8_t result; -+ __asm__ ("umaxp %0.8h, %1.8h, %2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vpmaxq_u32 (uint32x4_t a, uint32x4_t b) -+{ -+ uint32x4_t result; -+ __asm__ ("umaxp %0.4s, %1.4s, %2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -+vpmaxqd_f64 (float64x2_t a) -+{ -+ float64_t result; -+ __asm__ ("fmaxp %d0,%1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vpmaxs_f32 (float32x2_t a) -+{ -+ float32_t result; -+ __asm__ ("fmaxp %s0,%1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vpmin_f32 (float32x2_t a, float32x2_t b) -+{ -+ float32x2_t result; -+ __asm__ ("fminp %0.2s, %1.2s, %2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vpmin_s8 (int8x8_t a, int8x8_t b) -+{ -+ int8x8_t result; -+ __asm__ ("sminp %0.8b, %1.8b, %2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vpmin_s16 (int16x4_t a, int16x4_t b) -+{ -+ int16x4_t result; -+ __asm__ ("sminp %0.4h, %1.4h, %2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vpmin_s32 (int32x2_t a, int32x2_t b) -+{ -+ int32x2_t result; -+ __asm__ ("sminp %0.2s, %1.2s, %2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vpmin_u8 (uint8x8_t a, uint8x8_t b) -+{ -+ uint8x8_t result; -+ __asm__ ("uminp %0.8b, %1.8b, %2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vpmin_u16 (uint16x4_t a, uint16x4_t b) -+{ -+ uint16x4_t result; -+ __asm__ ("uminp %0.4h, %1.4h, %2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vpmin_u32 (uint32x2_t a, uint32x2_t b) -+{ -+ uint32x2_t result; -+ __asm__ ("uminp %0.2s, %1.2s, %2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vpminnm_f32 (float32x2_t a, float32x2_t b) -+{ -+ float32x2_t result; -+ __asm__ ("fminnmp %0.2s,%1.2s,%2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vpminnmq_f32 (float32x4_t a, float32x4_t b) -+{ -+ float32x4_t result; -+ __asm__ ("fminnmp %0.4s,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vpminnmq_f64 (float64x2_t a, float64x2_t b) -+{ -+ float64x2_t result; -+ __asm__ ("fminnmp %0.2d,%1.2d,%2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -+vpminnmqd_f64 (float64x2_t a) -+{ -+ float64_t result; -+ __asm__ ("fminnmp %d0,%1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vpminnms_f32 (float32x2_t a) -+{ -+ float32_t result; -+ __asm__ ("fminnmp %s0,%1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vpminq_f32 (float32x4_t a, float32x4_t b) -+{ -+ float32x4_t result; -+ __asm__ ("fminp %0.4s, %1.4s, %2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vpminq_f64 (float64x2_t a, float64x2_t b) -+{ -+ float64x2_t result; -+ __asm__ ("fminp %0.2d, %1.2d, %2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vpminq_s8 (int8x16_t a, int8x16_t b) -+{ -+ int8x16_t result; -+ __asm__ ("sminp %0.16b, %1.16b, %2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vpminq_s16 (int16x8_t a, int16x8_t b) -+{ -+ int16x8_t result; -+ __asm__ ("sminp %0.8h, %1.8h, %2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vpminq_s32 (int32x4_t a, int32x4_t b) -+{ -+ int32x4_t result; -+ __asm__ ("sminp %0.4s, %1.4s, %2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vpminq_u8 (uint8x16_t a, uint8x16_t b) -+{ -+ uint8x16_t result; -+ __asm__ ("uminp %0.16b, %1.16b, %2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vpminq_u16 (uint16x8_t a, uint16x8_t b) -+{ -+ uint16x8_t result; -+ __asm__ ("uminp %0.8h, %1.8h, %2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vpminq_u32 (uint32x4_t a, uint32x4_t b) -+{ -+ uint32x4_t result; -+ __asm__ ("uminp %0.4s, %1.4s, %2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -+vpminqd_f64 (float64x2_t a) -+{ -+ float64_t result; -+ __asm__ ("fminp %d0,%1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vpmins_f32 (float32x2_t a) -+{ -+ float32_t result; -+ __asm__ ("fminp %s0,%1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vqdmulh_n_s16 (int16x4_t a, int16_t b) -+{ -+ int16x4_t result; -+ __asm__ ("sqdmulh %0.4h,%1.4h,%2.h[0]" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vqdmulh_n_s32 (int32x2_t a, int32_t b) -+{ -+ int32x2_t result; -+ __asm__ ("sqdmulh %0.2s,%1.2s,%2.s[0]" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vqdmulhq_n_s16 (int16x8_t a, int16_t b) -+{ -+ int16x8_t result; -+ __asm__ ("sqdmulh %0.8h,%1.8h,%2.h[0]" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqdmulhq_n_s32 (int32x4_t a, int32_t b) -+{ -+ int32x4_t result; -+ __asm__ ("sqdmulh %0.4s,%1.4s,%2.s[0]" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vqmlalh_lane_s16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t b_ = (b); \ -+ int16_t a_ = (a); \ -+ int32_t result; \ -+ __asm__ ("sqdmlal %s0,%h1,%2.h[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline int32_t __attribute__ ((__always_inline__)) -+vqmlalh_s16 (int16_t a, int16_t b) -+{ -+ int32_t result; -+ __asm__ ("sqdmlal %s0,%h1,%h2" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vqmlals_lane_s32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t b_ = (b); \ -+ int32_t a_ = (a); \ -+ int64_t result; \ -+ __asm__ ("sqdmlal %d0,%s1,%2.s[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline int64_t __attribute__ ((__always_inline__)) -+vqmlals_s32 (int32_t a, int32_t b) -+{ -+ int64_t result; -+ __asm__ ("sqdmlal %d0,%s1,%s2" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vqmlslh_lane_s16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t b_ = (b); \ -+ int16_t a_ = (a); \ -+ int32_t result; \ -+ __asm__ ("sqdmlsl %s0,%h1,%2.h[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline int32_t __attribute__ ((__always_inline__)) -+vqmlslh_s16 (int16_t a, int16_t b) -+{ -+ int32_t result; -+ __asm__ ("sqdmlsl %s0,%h1,%h2" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vqmlsls_lane_s32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t b_ = (b); \ -+ int32_t a_ = (a); \ -+ int64_t result; \ -+ __asm__ ("sqdmlsl %d0,%s1,%2.s[%3]" \ -+ : "=w"(result) \ -+ : "w"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline int64_t __attribute__ ((__always_inline__)) -+vqmlsls_s32 (int32_t a, int32_t b) -+{ -+ int64_t result; -+ __asm__ ("sqdmlsl %d0,%s1,%s2" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vqmovn_high_s16 (int8x8_t a, int16x8_t b) -+{ -+ int8x16_t result = vcombine_s8 (a, vcreate_s8 (UINT64_C (0x0))); -+ __asm__ ("sqxtn2 %0.16b, %2.8h" -+ : "+w"(result) -+ : "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vqmovn_high_s32 (int16x4_t a, int32x4_t b) -+{ -+ int16x8_t result = vcombine_s16 (a, vcreate_s16 (UINT64_C (0x0))); -+ __asm__ ("sqxtn2 %0.8h, %2.4s" -+ : "+w"(result) -+ : "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqmovn_high_s64 (int32x2_t a, int64x2_t b) -+{ -+ int32x4_t result = vcombine_s32 (a, vcreate_s32 (UINT64_C (0x0))); -+ __asm__ ("sqxtn2 %0.4s, %2.2d" -+ : "+w"(result) -+ : "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vqmovn_high_u16 (uint8x8_t a, uint16x8_t b) -+{ -+ uint8x16_t result = vcombine_u8 (a, vcreate_u8 (UINT64_C (0x0))); -+ __asm__ ("uqxtn2 %0.16b, %2.8h" -+ : "+w"(result) -+ : "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vqmovn_high_u32 (uint16x4_t a, uint32x4_t b) -+{ -+ uint16x8_t result = vcombine_u16 (a, vcreate_u16 (UINT64_C (0x0))); -+ __asm__ ("uqxtn2 %0.8h, %2.4s" -+ : "+w"(result) -+ : "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vqmovn_high_u64 (uint32x2_t a, uint64x2_t b) -+{ -+ uint32x4_t result = vcombine_u32 (a, vcreate_u32 (UINT64_C (0x0))); -+ __asm__ ("uqxtn2 %0.4s, %2.2d" -+ : "+w"(result) -+ : "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vqmovun_high_s16 (uint8x8_t a, int16x8_t b) -+{ -+ uint8x16_t result = vcombine_u8 (a, vcreate_u8 (UINT64_C (0x0))); -+ __asm__ ("sqxtun2 %0.16b, %2.8h" -+ : "+w"(result) -+ : "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vqmovun_high_s32 (uint16x4_t a, int32x4_t b) -+{ -+ uint16x8_t result = vcombine_u16 (a, vcreate_u16 (UINT64_C (0x0))); -+ __asm__ ("sqxtun2 %0.8h, %2.4s" -+ : "+w"(result) -+ : "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vqmovun_high_s64 (uint32x2_t a, int64x2_t b) -+{ -+ uint32x4_t result = vcombine_u32 (a, vcreate_u32 (UINT64_C (0x0))); -+ __asm__ ("sqxtun2 %0.4s, %2.2d" -+ : "+w"(result) -+ : "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vqrdmulh_n_s16 (int16x4_t a, int16_t b) -+{ -+ int16x4_t result; -+ __asm__ ("sqrdmulh %0.4h,%1.4h,%2.h[0]" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vqrdmulh_n_s32 (int32x2_t a, int32_t b) -+{ -+ int32x2_t result; -+ __asm__ ("sqrdmulh %0.2s,%1.2s,%2.s[0]" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vqrdmulhq_n_s16 (int16x8_t a, int16_t b) -+{ -+ int16x8_t result; -+ __asm__ ("sqrdmulh %0.8h,%1.8h,%2.h[0]" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqrdmulhq_n_s32 (int32x4_t a, int32_t b) -+{ -+ int32x4_t result; -+ __asm__ ("sqrdmulh %0.4s,%1.4s,%2.s[0]" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vqrshrn_high_n_s16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t b_ = (b); \ -+ int8x8_t a_ = (a); \ -+ int8x16_t result = vcombine_s8 \ -+ (a_, vcreate_s8 (UINT64_C (0x0))); \ -+ __asm__ ("sqrshrn2 %0.16b, %1.8h, #%2" \ -+ : "+w"(result) \ -+ : "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vqrshrn_high_n_s32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t b_ = (b); \ -+ int16x4_t a_ = (a); \ -+ int16x8_t result = vcombine_s16 \ -+ (a_, vcreate_s16 (UINT64_C (0x0))); \ -+ __asm__ ("sqrshrn2 %0.8h, %1.4s, #%2" \ -+ : "+w"(result) \ -+ : "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vqrshrn_high_n_s64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int64x2_t b_ = (b); \ -+ int32x2_t a_ = (a); \ -+ int32x4_t result = vcombine_s32 \ -+ (a_, vcreate_s32 (UINT64_C (0x0))); \ -+ __asm__ ("sqrshrn2 %0.4s, %1.2d, #%2" \ -+ : "+w"(result) \ -+ : "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vqrshrn_high_n_u16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t b_ = (b); \ -+ uint8x8_t a_ = (a); \ -+ uint8x16_t result = vcombine_u8 \ -+ (a_, vcreate_u8 (UINT64_C (0x0))); \ -+ __asm__ ("uqrshrn2 %0.16b, %1.8h, #%2" \ -+ : "+w"(result) \ -+ : "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vqrshrn_high_n_u32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t b_ = (b); \ -+ uint16x4_t a_ = (a); \ -+ uint16x8_t result = vcombine_u16 \ -+ (a_, vcreate_u16 (UINT64_C (0x0))); \ -+ __asm__ ("uqrshrn2 %0.8h, %1.4s, #%2" \ -+ : "+w"(result) \ -+ : "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vqrshrn_high_n_u64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint64x2_t b_ = (b); \ -+ uint32x2_t a_ = (a); \ -+ uint32x4_t result = vcombine_u32 \ -+ (a_, vcreate_u32 (UINT64_C (0x0))); \ -+ __asm__ ("uqrshrn2 %0.4s, %1.2d, #%2" \ -+ : "+w"(result) \ -+ : "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vqrshrun_high_n_s16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t b_ = (b); \ -+ uint8x8_t a_ = (a); \ -+ uint8x16_t result = vcombine_u8 \ -+ (a_, vcreate_u8 (UINT64_C (0x0))); \ -+ __asm__ ("sqrshrun2 %0.16b, %1.8h, #%2" \ -+ : "+w"(result) \ -+ : "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vqrshrun_high_n_s32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t b_ = (b); \ -+ uint16x4_t a_ = (a); \ -+ uint16x8_t result = vcombine_u16 \ -+ (a_, vcreate_u16 (UINT64_C (0x0))); \ -+ __asm__ ("sqrshrun2 %0.8h, %1.4s, #%2" \ -+ : "+w"(result) \ -+ : "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vqrshrun_high_n_s64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int64x2_t b_ = (b); \ -+ uint32x2_t a_ = (a); \ -+ uint32x4_t result = vcombine_u32 \ -+ (a_, vcreate_u32 (UINT64_C (0x0))); \ -+ __asm__ ("sqrshrun2 %0.4s, %1.2d, #%2" \ -+ : "+w"(result) \ -+ : "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vqshrn_high_n_s16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t b_ = (b); \ -+ int8x8_t a_ = (a); \ -+ int8x16_t result = vcombine_s8 \ -+ (a_, vcreate_s8 (UINT64_C (0x0))); \ -+ __asm__ ("sqshrn2 %0.16b, %1.8h, #%2" \ -+ : "+w"(result) \ -+ : "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vqshrn_high_n_s32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t b_ = (b); \ -+ int16x4_t a_ = (a); \ -+ int16x8_t result = vcombine_s16 \ -+ (a_, vcreate_s16 (UINT64_C (0x0))); \ -+ __asm__ ("sqshrn2 %0.8h, %1.4s, #%2" \ -+ : "+w"(result) \ -+ : "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vqshrn_high_n_s64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int64x2_t b_ = (b); \ -+ int32x2_t a_ = (a); \ -+ int32x4_t result = vcombine_s32 \ -+ (a_, vcreate_s32 (UINT64_C (0x0))); \ -+ __asm__ ("sqshrn2 %0.4s, %1.2d, #%2" \ -+ : "+w"(result) \ -+ : "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vqshrn_high_n_u16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t b_ = (b); \ -+ uint8x8_t a_ = (a); \ -+ uint8x16_t result = vcombine_u8 \ -+ (a_, vcreate_u8 (UINT64_C (0x0))); \ -+ __asm__ ("uqshrn2 %0.16b, %1.8h, #%2" \ -+ : "+w"(result) \ -+ : "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vqshrn_high_n_u32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t b_ = (b); \ -+ uint16x4_t a_ = (a); \ -+ uint16x8_t result = vcombine_u16 \ -+ (a_, vcreate_u16 (UINT64_C (0x0))); \ -+ __asm__ ("uqshrn2 %0.8h, %1.4s, #%2" \ -+ : "+w"(result) \ -+ : "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vqshrn_high_n_u64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint64x2_t b_ = (b); \ -+ uint32x2_t a_ = (a); \ -+ uint32x4_t result = vcombine_u32 \ -+ (a_, vcreate_u32 (UINT64_C (0x0))); \ -+ __asm__ ("uqshrn2 %0.4s, %1.2d, #%2" \ -+ : "+w"(result) \ -+ : "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vqshrun_high_n_s16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t b_ = (b); \ -+ uint8x8_t a_ = (a); \ -+ uint8x16_t result = vcombine_u8 \ -+ (a_, vcreate_u8 (UINT64_C (0x0))); \ -+ __asm__ ("sqshrun2 %0.16b, %1.8h, #%2" \ -+ : "+w"(result) \ -+ : "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vqshrun_high_n_s32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t b_ = (b); \ -+ uint16x4_t a_ = (a); \ -+ uint16x8_t result = vcombine_u16 \ -+ (a_, vcreate_u16 (UINT64_C (0x0))); \ -+ __asm__ ("sqshrun2 %0.8h, %1.4s, #%2" \ -+ : "+w"(result) \ -+ : "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vqshrun_high_n_s64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int64x2_t b_ = (b); \ -+ uint32x2_t a_ = (a); \ -+ uint32x4_t result = vcombine_u32 \ -+ (a_, vcreate_u32 (UINT64_C (0x0))); \ -+ __asm__ ("sqshrun2 %0.4s, %1.2d, #%2" \ -+ : "+w"(result) \ -+ : "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vrbit_s8 (int8x8_t a) -+{ -+ int8x8_t result; -+ __asm__ ("rbit %0.8b,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vrbit_u8 (uint8x8_t a) -+{ -+ uint8x8_t result; -+ __asm__ ("rbit %0.8b,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vrbitq_s8 (int8x16_t a) -+{ -+ int8x16_t result; -+ __asm__ ("rbit %0.16b,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vrbitq_u8 (uint8x16_t a) -+{ -+ uint8x16_t result; -+ __asm__ ("rbit %0.16b,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vrecpe_f32 (float32x2_t a) -+{ -+ float32x2_t result; -+ __asm__ ("frecpe %0.2s,%1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vrecpe_u32 (uint32x2_t a) -+{ -+ uint32x2_t result; -+ __asm__ ("urecpe %0.2s,%1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -+vrecped_f64 (float64_t a) -+{ -+ float64_t result; -+ __asm__ ("frecpe %d0,%d1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vrecpeq_f32 (float32x4_t a) -+{ -+ float32x4_t result; -+ __asm__ ("frecpe %0.4s,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vrecpeq_f64 (float64x2_t a) -+{ -+ float64x2_t result; -+ __asm__ ("frecpe %0.2d,%1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vrecpeq_u32 (uint32x4_t a) -+{ -+ uint32x4_t result; -+ __asm__ ("urecpe %0.4s,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vrecpes_f32 (float32_t a) -+{ -+ float32_t result; -+ __asm__ ("frecpe %s0,%s1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vrecps_f32 (float32x2_t a, float32x2_t b) -+{ -+ float32x2_t result; -+ __asm__ ("frecps %0.2s,%1.2s,%2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -+vrecpsd_f64 (float64_t a, float64_t b) -+{ -+ float64_t result; -+ __asm__ ("frecps %d0,%d1,%d2" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vrecpsq_f32 (float32x4_t a, float32x4_t b) -+{ -+ float32x4_t result; -+ __asm__ ("frecps %0.4s,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vrecpsq_f64 (float64x2_t a, float64x2_t b) -+{ -+ float64x2_t result; -+ __asm__ ("frecps %0.2d,%1.2d,%2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vrecpss_f32 (float32_t a, float32_t b) -+{ -+ float32_t result; -+ __asm__ ("frecps %s0,%s1,%s2" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -+vrecpxd_f64 (float64_t a) -+{ -+ float64_t result; -+ __asm__ ("frecpe %d0,%d1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vrecpxs_f32 (float32_t a) -+{ -+ float32_t result; -+ __asm__ ("frecpe %s0,%s1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vrev16_p8 (poly8x8_t a) -+{ -+ poly8x8_t result; -+ __asm__ ("rev16 %0.8b,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vrev16_s8 (int8x8_t a) -+{ -+ int8x8_t result; -+ __asm__ ("rev16 %0.8b,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vrev16_u8 (uint8x8_t a) -+{ -+ uint8x8_t result; -+ __asm__ ("rev16 %0.8b,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vrev16q_p8 (poly8x16_t a) -+{ -+ poly8x16_t result; -+ __asm__ ("rev16 %0.16b,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vrev16q_s8 (int8x16_t a) -+{ -+ int8x16_t result; -+ __asm__ ("rev16 %0.16b,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vrev16q_u8 (uint8x16_t a) -+{ -+ uint8x16_t result; -+ __asm__ ("rev16 %0.16b,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vrev32_p8 (poly8x8_t a) -+{ -+ poly8x8_t result; -+ __asm__ ("rev32 %0.8b,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) -+vrev32_p16 (poly16x4_t a) -+{ -+ poly16x4_t result; -+ __asm__ ("rev32 %0.4h,%1.4h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vrev32_s8 (int8x8_t a) -+{ -+ int8x8_t result; -+ __asm__ ("rev32 %0.8b,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vrev32_s16 (int16x4_t a) -+{ -+ int16x4_t result; -+ __asm__ ("rev32 %0.4h,%1.4h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vrev32_u8 (uint8x8_t a) -+{ -+ uint8x8_t result; -+ __asm__ ("rev32 %0.8b,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vrev32_u16 (uint16x4_t a) -+{ -+ uint16x4_t result; -+ __asm__ ("rev32 %0.4h,%1.4h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vrev32q_p8 (poly8x16_t a) -+{ -+ poly8x16_t result; -+ __asm__ ("rev32 %0.16b,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) -+vrev32q_p16 (poly16x8_t a) -+{ -+ poly16x8_t result; -+ __asm__ ("rev32 %0.8h,%1.8h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vrev32q_s8 (int8x16_t a) -+{ -+ int8x16_t result; -+ __asm__ ("rev32 %0.16b,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vrev32q_s16 (int16x8_t a) -+{ -+ int16x8_t result; -+ __asm__ ("rev32 %0.8h,%1.8h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vrev32q_u8 (uint8x16_t a) -+{ -+ uint8x16_t result; -+ __asm__ ("rev32 %0.16b,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vrev32q_u16 (uint16x8_t a) -+{ -+ uint16x8_t result; -+ __asm__ ("rev32 %0.8h,%1.8h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vrev64_f32 (float32x2_t a) -+{ -+ float32x2_t result; -+ __asm__ ("rev64 %0.2s,%1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vrev64_p8 (poly8x8_t a) -+{ -+ poly8x8_t result; -+ __asm__ ("rev64 %0.8b,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) -+vrev64_p16 (poly16x4_t a) -+{ -+ poly16x4_t result; -+ __asm__ ("rev64 %0.4h,%1.4h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vrev64_s8 (int8x8_t a) -+{ -+ int8x8_t result; -+ __asm__ ("rev64 %0.8b,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vrev64_s16 (int16x4_t a) -+{ -+ int16x4_t result; -+ __asm__ ("rev64 %0.4h,%1.4h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vrev64_s32 (int32x2_t a) -+{ -+ int32x2_t result; -+ __asm__ ("rev64 %0.2s,%1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vrev64_u8 (uint8x8_t a) -+{ -+ uint8x8_t result; -+ __asm__ ("rev64 %0.8b,%1.8b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vrev64_u16 (uint16x4_t a) -+{ -+ uint16x4_t result; -+ __asm__ ("rev64 %0.4h,%1.4h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vrev64_u32 (uint32x2_t a) -+{ -+ uint32x2_t result; -+ __asm__ ("rev64 %0.2s,%1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vrev64q_f32 (float32x4_t a) -+{ -+ float32x4_t result; -+ __asm__ ("rev64 %0.4s,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vrev64q_p8 (poly8x16_t a) -+{ -+ poly8x16_t result; -+ __asm__ ("rev64 %0.16b,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) -+vrev64q_p16 (poly16x8_t a) -+{ -+ poly16x8_t result; -+ __asm__ ("rev64 %0.8h,%1.8h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vrev64q_s8 (int8x16_t a) -+{ -+ int8x16_t result; -+ __asm__ ("rev64 %0.16b,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vrev64q_s16 (int16x8_t a) -+{ -+ int16x8_t result; -+ __asm__ ("rev64 %0.8h,%1.8h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vrev64q_s32 (int32x4_t a) -+{ -+ int32x4_t result; -+ __asm__ ("rev64 %0.4s,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vrev64q_u8 (uint8x16_t a) -+{ -+ uint8x16_t result; -+ __asm__ ("rev64 %0.16b,%1.16b" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vrev64q_u16 (uint16x8_t a) -+{ -+ uint16x8_t result; -+ __asm__ ("rev64 %0.8h,%1.8h" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vrev64q_u32 (uint32x4_t a) -+{ -+ uint32x4_t result; -+ __asm__ ("rev64 %0.4s,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vrnd_f32 (float32x2_t a) -+{ -+ float32x2_t result; -+ __asm__ ("frintz %0.2s,%1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vrnda_f32 (float32x2_t a) -+{ -+ float32x2_t result; -+ __asm__ ("frinta %0.2s,%1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vrndm_f32 (float32x2_t a) -+{ -+ float32x2_t result; -+ __asm__ ("frintm %0.2s,%1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vrndn_f32 (float32x2_t a) -+{ -+ float32x2_t result; -+ __asm__ ("frintn %0.2s,%1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vrndp_f32 (float32x2_t a) -+{ -+ float32x2_t result; -+ __asm__ ("frintp %0.2s,%1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vrndq_f32 (float32x4_t a) -+{ -+ float32x4_t result; -+ __asm__ ("frintz %0.4s,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vrndq_f64 (float64x2_t a) -+{ -+ float64x2_t result; -+ __asm__ ("frintz %0.2d,%1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vrndqa_f32 (float32x4_t a) -+{ -+ float32x4_t result; -+ __asm__ ("frinta %0.4s,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vrndqa_f64 (float64x2_t a) -+{ -+ float64x2_t result; -+ __asm__ ("frinta %0.2d,%1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vrndqm_f32 (float32x4_t a) -+{ -+ float32x4_t result; -+ __asm__ ("frintm %0.4s,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vrndqm_f64 (float64x2_t a) -+{ -+ float64x2_t result; -+ __asm__ ("frintm %0.2d,%1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vrndqn_f32 (float32x4_t a) -+{ -+ float32x4_t result; -+ __asm__ ("frintn %0.4s,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vrndqn_f64 (float64x2_t a) -+{ -+ float64x2_t result; -+ __asm__ ("frintn %0.2d,%1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vrndqp_f32 (float32x4_t a) -+{ -+ float32x4_t result; -+ __asm__ ("frintp %0.4s,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vrndqp_f64 (float64x2_t a) -+{ -+ float64x2_t result; -+ __asm__ ("frintp %0.2d,%1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vrshrn_high_n_s16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t b_ = (b); \ -+ int8x8_t a_ = (a); \ -+ int8x16_t result = vcombine_s8 \ -+ (a_, vcreate_s8 (UINT64_C (0x0))); \ -+ __asm__ ("rshrn2 %0.16b,%2.8h,#%3" \ -+ : "+w"(result) \ -+ : "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vrshrn_high_n_s32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t b_ = (b); \ -+ int16x4_t a_ = (a); \ -+ int16x8_t result = vcombine_s16 \ -+ (a_, vcreate_s16 (UINT64_C (0x0))); \ -+ __asm__ ("rshrn2 %0.8h,%2.4s,#%3" \ -+ : "+w"(result) \ -+ : "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vrshrn_high_n_s64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int64x2_t b_ = (b); \ -+ int32x2_t a_ = (a); \ -+ int32x4_t result = vcombine_s32 \ -+ (a_, vcreate_s32 (UINT64_C (0x0))); \ -+ __asm__ ("rshrn2 %0.4s,%2.2d,#%3" \ -+ : "+w"(result) \ -+ : "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vrshrn_high_n_u16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t b_ = (b); \ -+ uint8x8_t a_ = (a); \ -+ uint8x16_t result = vcombine_u8 \ -+ (a_, vcreate_u8 (UINT64_C (0x0))); \ -+ __asm__ ("rshrn2 %0.16b,%2.8h,#%3" \ -+ : "+w"(result) \ -+ : "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vrshrn_high_n_u32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t b_ = (b); \ -+ uint16x4_t a_ = (a); \ -+ uint16x8_t result = vcombine_u16 \ -+ (a_, vcreate_u16 (UINT64_C (0x0))); \ -+ __asm__ ("rshrn2 %0.8h,%2.4s,#%3" \ -+ : "+w"(result) \ -+ : "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vrshrn_high_n_u64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint64x2_t b_ = (b); \ -+ uint32x2_t a_ = (a); \ -+ uint32x4_t result = vcombine_u32 \ -+ (a_, vcreate_u32 (UINT64_C (0x0))); \ -+ __asm__ ("rshrn2 %0.4s,%2.2d,#%3" \ -+ : "+w"(result) \ -+ : "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vrshrn_n_s16(a, b) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t a_ = (a); \ -+ int8x8_t result; \ -+ __asm__ ("rshrn %0.8b,%1.8h,%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vrshrn_n_s32(a, b) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t a_ = (a); \ -+ int16x4_t result; \ -+ __asm__ ("rshrn %0.4h,%1.4s,%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vrshrn_n_s64(a, b) \ -+ __extension__ \ -+ ({ \ -+ int64x2_t a_ = (a); \ -+ int32x2_t result; \ -+ __asm__ ("rshrn %0.2s,%1.2d,%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vrshrn_n_u16(a, b) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t a_ = (a); \ -+ uint8x8_t result; \ -+ __asm__ ("rshrn %0.8b,%1.8h,%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vrshrn_n_u32(a, b) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t a_ = (a); \ -+ uint16x4_t result; \ -+ __asm__ ("rshrn %0.4h,%1.4s,%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vrshrn_n_u64(a, b) \ -+ __extension__ \ -+ ({ \ -+ uint64x2_t a_ = (a); \ -+ uint32x2_t result; \ -+ __asm__ ("rshrn %0.2s,%1.2d,%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vrsqrte_f32 (float32x2_t a) -+{ -+ float32x2_t result; -+ __asm__ ("frsqrte %0.2s,%1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vrsqrte_f64 (float64x2_t a) -+{ -+ float64x2_t result; -+ __asm__ ("frsqrte %0.2d,%1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vrsqrte_u32 (uint32x2_t a) -+{ -+ uint32x2_t result; -+ __asm__ ("ursqrte %0.2s,%1.2s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -+vrsqrted_f64 (float64_t a) -+{ -+ float64_t result; -+ __asm__ ("frsqrte %d0,%d1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vrsqrteq_f32 (float32x4_t a) -+{ -+ float32x4_t result; -+ __asm__ ("frsqrte %0.4s,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vrsqrteq_f64 (float64x2_t a) -+{ -+ float64x2_t result; -+ __asm__ ("frsqrte %0.2d,%1.2d" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vrsqrteq_u32 (uint32x4_t a) -+{ -+ uint32x4_t result; -+ __asm__ ("ursqrte %0.4s,%1.4s" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vrsqrtes_f32 (float32_t a) -+{ -+ float32_t result; -+ __asm__ ("frsqrte %s0,%s1" -+ : "=w"(result) -+ : "w"(a) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vrsqrts_f32 (float32x2_t a, float32x2_t b) -+{ -+ float32x2_t result; -+ __asm__ ("frsqrts %0.2s,%1.2s,%2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -+vrsqrtsd_f64 (float64_t a, float64_t b) -+{ -+ float64_t result; -+ __asm__ ("frsqrts %d0,%d1,%d2" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vrsqrtsq_f32 (float32x4_t a, float32x4_t b) -+{ -+ float32x4_t result; -+ __asm__ ("frsqrts %0.4s,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vrsqrtsq_f64 (float64x2_t a, float64x2_t b) -+{ -+ float64x2_t result; -+ __asm__ ("frsqrts %0.2d,%1.2d,%2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vrsqrtss_f32 (float32_t a, float32_t b) -+{ -+ float32_t result; -+ __asm__ ("frsqrts %s0,%s1,%s2" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vrsrtsq_f64 (float64x2_t a, float64x2_t b) -+{ -+ float64x2_t result; -+ __asm__ ("frsqrts %0.2d,%1.2d,%2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vrsubhn_high_s16 (int8x8_t a, int16x8_t b, int16x8_t c) -+{ -+ int8x16_t result = vcombine_s8 (a, vcreate_s8 (UINT64_C (0x0))); -+ __asm__ ("rsubhn2 %0.16b, %1.8h, %2.8h" -+ : "+w"(result) -+ : "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vrsubhn_high_s32 (int16x4_t a, int32x4_t b, int32x4_t c) -+{ -+ int16x8_t result = vcombine_s16 (a, vcreate_s16 (UINT64_C (0x0))); -+ __asm__ ("rsubhn2 %0.8h, %1.4s, %2.4s" -+ : "+w"(result) -+ : "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vrsubhn_high_s64 (int32x2_t a, int64x2_t b, int64x2_t c) -+{ -+ int32x4_t result = vcombine_s32 (a, vcreate_s32 (UINT64_C (0x0))); -+ __asm__ ("rsubhn2 %0.4s, %1.2d, %2.2d" -+ : "+w"(result) -+ : "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vrsubhn_high_u16 (uint8x8_t a, uint16x8_t b, uint16x8_t c) -+{ -+ uint8x16_t result = vcombine_u8 (a, vcreate_u8 (UINT64_C (0x0))); -+ __asm__ ("rsubhn2 %0.16b, %1.8h, %2.8h" -+ : "+w"(result) -+ : "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vrsubhn_high_u32 (uint16x4_t a, uint32x4_t b, uint32x4_t c) -+{ -+ uint16x8_t result = vcombine_u16 (a, vcreate_u16 (UINT64_C (0x0))); -+ __asm__ ("rsubhn2 %0.8h, %1.4s, %2.4s" -+ : "+w"(result) -+ : "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vrsubhn_high_u64 (uint32x2_t a, uint64x2_t b, uint64x2_t c) -+{ -+ uint32x4_t result = vcombine_u32 (a, vcreate_u32 (UINT64_C (0x0))); -+ __asm__ ("rsubhn2 %0.4s, %1.2d, %2.2d" -+ : "+w"(result) -+ : "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vrsubhn_s16 (int16x8_t a, int16x8_t b) -+{ -+ int8x8_t result; -+ __asm__ ("rsubhn %0.8b, %1.8h, %2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vrsubhn_s32 (int32x4_t a, int32x4_t b) -+{ -+ int16x4_t result; -+ __asm__ ("rsubhn %0.4h, %1.4s, %2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vrsubhn_s64 (int64x2_t a, int64x2_t b) -+{ -+ int32x2_t result; -+ __asm__ ("rsubhn %0.2s, %1.2d, %2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vrsubhn_u16 (uint16x8_t a, uint16x8_t b) -+{ -+ uint8x8_t result; -+ __asm__ ("rsubhn %0.8b, %1.8h, %2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vrsubhn_u32 (uint32x4_t a, uint32x4_t b) -+{ -+ uint16x4_t result; -+ __asm__ ("rsubhn %0.4h, %1.4s, %2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vrsubhn_u64 (uint64x2_t a, uint64x2_t b) -+{ -+ uint32x2_t result; -+ __asm__ ("rsubhn %0.2s, %1.2d, %2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+#define vset_lane_f32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float32x2_t b_ = (b); \ -+ float32_t a_ = (a); \ -+ float32x2_t result; \ -+ __asm__ ("ins %0.s[%3], %w1" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vset_lane_f64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float64x1_t b_ = (b); \ -+ float64_t a_ = (a); \ -+ float64x1_t result; \ -+ __asm__ ("ins %0.d[%3], %x1" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vset_lane_p8(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ poly8x8_t b_ = (b); \ -+ poly8_t a_ = (a); \ -+ poly8x8_t result; \ -+ __asm__ ("ins %0.b[%3], %w1" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vset_lane_p16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ poly16x4_t b_ = (b); \ -+ poly16_t a_ = (a); \ -+ poly16x4_t result; \ -+ __asm__ ("ins %0.h[%3], %w1" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vset_lane_s8(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int8x8_t b_ = (b); \ -+ int8_t a_ = (a); \ -+ int8x8_t result; \ -+ __asm__ ("ins %0.b[%3], %w1" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vset_lane_s16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int16x4_t b_ = (b); \ -+ int16_t a_ = (a); \ -+ int16x4_t result; \ -+ __asm__ ("ins %0.h[%3], %w1" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vset_lane_s32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int32x2_t b_ = (b); \ -+ int32_t a_ = (a); \ -+ int32x2_t result; \ -+ __asm__ ("ins %0.s[%3], %w1" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vset_lane_s64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int64x1_t b_ = (b); \ -+ int64_t a_ = (a); \ -+ int64x1_t result; \ -+ __asm__ ("ins %0.d[%3], %x1" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vset_lane_u8(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint8x8_t b_ = (b); \ -+ uint8_t a_ = (a); \ -+ uint8x8_t result; \ -+ __asm__ ("ins %0.b[%3], %w1" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vset_lane_u16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint16x4_t b_ = (b); \ -+ uint16_t a_ = (a); \ -+ uint16x4_t result; \ -+ __asm__ ("ins %0.h[%3], %w1" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vset_lane_u32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint32x2_t b_ = (b); \ -+ uint32_t a_ = (a); \ -+ uint32x2_t result; \ -+ __asm__ ("ins %0.s[%3], %w1" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vset_lane_u64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint64x1_t b_ = (b); \ -+ uint64_t a_ = (a); \ -+ uint64x1_t result; \ -+ __asm__ ("ins %0.d[%3], %x1" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vsetq_lane_f32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float32x4_t b_ = (b); \ -+ float32_t a_ = (a); \ -+ float32x4_t result; \ -+ __asm__ ("ins %0.s[%3], %w1" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vsetq_lane_f64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float64x2_t b_ = (b); \ -+ float64_t a_ = (a); \ -+ float64x2_t result; \ -+ __asm__ ("ins %0.d[%3], %x1" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vsetq_lane_p8(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ poly8x16_t b_ = (b); \ -+ poly8_t a_ = (a); \ -+ poly8x16_t result; \ -+ __asm__ ("ins %0.b[%3], %w1" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vsetq_lane_p16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ poly16x8_t b_ = (b); \ -+ poly16_t a_ = (a); \ -+ poly16x8_t result; \ -+ __asm__ ("ins %0.h[%3], %w1" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vsetq_lane_s8(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int8x16_t b_ = (b); \ -+ int8_t a_ = (a); \ -+ int8x16_t result; \ -+ __asm__ ("ins %0.b[%3], %w1" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vsetq_lane_s16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t b_ = (b); \ -+ int16_t a_ = (a); \ -+ int16x8_t result; \ -+ __asm__ ("ins %0.h[%3], %w1" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vsetq_lane_s32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t b_ = (b); \ -+ int32_t a_ = (a); \ -+ int32x4_t result; \ -+ __asm__ ("ins %0.s[%3], %w1" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vsetq_lane_s64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int64x2_t b_ = (b); \ -+ int64_t a_ = (a); \ -+ int64x2_t result; \ -+ __asm__ ("ins %0.d[%3], %x1" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vsetq_lane_u8(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint8x16_t b_ = (b); \ -+ uint8_t a_ = (a); \ -+ uint8x16_t result; \ -+ __asm__ ("ins %0.b[%3], %w1" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vsetq_lane_u16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t b_ = (b); \ -+ uint16_t a_ = (a); \ -+ uint16x8_t result; \ -+ __asm__ ("ins %0.h[%3], %w1" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vsetq_lane_u32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t b_ = (b); \ -+ uint32_t a_ = (a); \ -+ uint32x4_t result; \ -+ __asm__ ("ins %0.s[%3], %w1" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vsetq_lane_u64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint64x2_t b_ = (b); \ -+ uint64_t a_ = (a); \ -+ uint64x2_t result; \ -+ __asm__ ("ins %0.d[%3], %x1" \ -+ : "=w"(result) \ -+ : "r"(a_), "0"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vshrn_high_n_s16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t b_ = (b); \ -+ int8x8_t a_ = (a); \ -+ int8x16_t result = vcombine_s8 \ -+ (a_, vcreate_s8 (UINT64_C (0x0))); \ -+ __asm__ ("shrn2 %0.16b,%2.8h,#%3" \ -+ : "+w"(result) \ -+ : "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vshrn_high_n_s32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t b_ = (b); \ -+ int16x4_t a_ = (a); \ -+ int16x8_t result = vcombine_s16 \ -+ (a_, vcreate_s16 (UINT64_C (0x0))); \ -+ __asm__ ("shrn2 %0.8h,%2.4s,#%3" \ -+ : "+w"(result) \ -+ : "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vshrn_high_n_s64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int64x2_t b_ = (b); \ -+ int32x2_t a_ = (a); \ -+ int32x4_t result = vcombine_s32 \ -+ (a_, vcreate_s32 (UINT64_C (0x0))); \ -+ __asm__ ("shrn2 %0.4s,%2.2d,#%3" \ -+ : "+w"(result) \ -+ : "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vshrn_high_n_u16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t b_ = (b); \ -+ uint8x8_t a_ = (a); \ -+ uint8x16_t result = vcombine_u8 \ -+ (a_, vcreate_u8 (UINT64_C (0x0))); \ -+ __asm__ ("shrn2 %0.16b,%2.8h,#%3" \ -+ : "+w"(result) \ -+ : "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vshrn_high_n_u32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t b_ = (b); \ -+ uint16x4_t a_ = (a); \ -+ uint16x8_t result = vcombine_u16 \ -+ (a_, vcreate_u16 (UINT64_C (0x0))); \ -+ __asm__ ("shrn2 %0.8h,%2.4s,#%3" \ -+ : "+w"(result) \ -+ : "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vshrn_high_n_u64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint64x2_t b_ = (b); \ -+ uint32x2_t a_ = (a); \ -+ uint32x4_t result = vcombine_u32 \ -+ (a_, vcreate_u32 (UINT64_C (0x0))); \ -+ __asm__ ("shrn2 %0.4s,%2.2d,#%3" \ -+ : "+w"(result) \ -+ : "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vshrn_n_s16(a, b) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t a_ = (a); \ -+ int8x8_t result; \ -+ __asm__ ("shrn %0.8b,%1.8h,%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vshrn_n_s32(a, b) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t a_ = (a); \ -+ int16x4_t result; \ -+ __asm__ ("shrn %0.4h,%1.4s,%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vshrn_n_s64(a, b) \ -+ __extension__ \ -+ ({ \ -+ int64x2_t a_ = (a); \ -+ int32x2_t result; \ -+ __asm__ ("shrn %0.2s,%1.2d,%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vshrn_n_u16(a, b) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t a_ = (a); \ -+ uint8x8_t result; \ -+ __asm__ ("shrn %0.8b,%1.8h,%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vshrn_n_u32(a, b) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t a_ = (a); \ -+ uint16x4_t result; \ -+ __asm__ ("shrn %0.4h,%1.4s,%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vshrn_n_u64(a, b) \ -+ __extension__ \ -+ ({ \ -+ uint64x2_t a_ = (a); \ -+ uint32x2_t result; \ -+ __asm__ ("shrn %0.2s,%1.2d,%2" \ -+ : "=w"(result) \ -+ : "w"(a_), "i"(b) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vsli_n_p8(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ poly8x8_t b_ = (b); \ -+ poly8x8_t a_ = (a); \ -+ poly8x8_t result; \ -+ __asm__ ("sli %0.8b,%2.8b,%3" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vsli_n_p16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ poly16x4_t b_ = (b); \ -+ poly16x4_t a_ = (a); \ -+ poly16x4_t result; \ -+ __asm__ ("sli %0.4h,%2.4h,%3" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vsliq_n_p8(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ poly8x16_t b_ = (b); \ -+ poly8x16_t a_ = (a); \ -+ poly8x16_t result; \ -+ __asm__ ("sli %0.16b,%2.16b,%3" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vsliq_n_p16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ poly16x8_t b_ = (b); \ -+ poly16x8_t a_ = (a); \ -+ poly16x8_t result; \ -+ __asm__ ("sli %0.8h,%2.8h,%3" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vsri_n_p8(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ poly8x8_t b_ = (b); \ -+ poly8x8_t a_ = (a); \ -+ poly8x8_t result; \ -+ __asm__ ("sri %0.8b,%2.8b,%3" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vsri_n_p16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ poly16x4_t b_ = (b); \ -+ poly16x4_t a_ = (a); \ -+ poly16x4_t result; \ -+ __asm__ ("sri %0.4h,%2.4h,%3" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vsriq_n_p8(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ poly8x16_t b_ = (b); \ -+ poly8x16_t a_ = (a); \ -+ poly8x16_t result; \ -+ __asm__ ("sri %0.16b,%2.16b,%3" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+#define vsriq_n_p16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ poly16x8_t b_ = (b); \ -+ poly16x8_t a_ = (a); \ -+ poly16x8_t result; \ -+ __asm__ ("sri %0.8h,%2.8h,%3" \ -+ : "=w"(result) \ -+ : "0"(a_), "w"(b_), "i"(c) \ -+ : /* No clobbers */); \ -+ result; \ -+ }) -+ -+__extension__ static __inline void __attribute__ ((__always_inline__)) -+vst1_f32 (float32_t * a, float32x2_t b) -+{ -+ __asm__ ("st1 {%1.2s},[%0]" -+ : -+ : "r"(a), "w"(b) -+ : "memory"); -+} -+ -+__extension__ static __inline void __attribute__ ((__always_inline__)) -+vst1_f64 (float64_t * a, float64x1_t b) -+{ -+ __asm__ ("st1 {%1.1d},[%0]" -+ : -+ : "r"(a), "w"(b) -+ : "memory"); -+} -+ -+#define vst1_lane_f32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float32x2_t b_ = (b); \ -+ float32_t * a_ = (a); \ -+ __asm__ ("st1 {%1.s}[%2],[%0]" \ -+ : \ -+ : "r"(a_), "w"(b_), "i"(c) \ -+ : "memory"); \ -+ }) -+ -+#define vst1_lane_f64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float64x1_t b_ = (b); \ -+ float64_t * a_ = (a); \ -+ __asm__ ("st1 {%1.d}[%2],[%0]" \ -+ : \ -+ : "r"(a_), "w"(b_), "i"(c) \ -+ : "memory"); \ -+ }) -+ -+#define vst1_lane_p8(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ poly8x8_t b_ = (b); \ -+ poly8_t * a_ = (a); \ -+ __asm__ ("st1 {%1.b}[%2],[%0]" \ -+ : \ -+ : "r"(a_), "w"(b_), "i"(c) \ -+ : "memory"); \ -+ }) -+ -+#define vst1_lane_p16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ poly16x4_t b_ = (b); \ -+ poly16_t * a_ = (a); \ -+ __asm__ ("st1 {%1.h}[%2],[%0]" \ -+ : \ -+ : "r"(a_), "w"(b_), "i"(c) \ -+ : "memory"); \ -+ }) -+ -+#define vst1_lane_s8(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int8x8_t b_ = (b); \ -+ int8_t * a_ = (a); \ -+ __asm__ ("st1 {%1.b}[%2],[%0]" \ -+ : \ -+ : "r"(a_), "w"(b_), "i"(c) \ -+ : "memory"); \ -+ }) -+ -+#define vst1_lane_s16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int16x4_t b_ = (b); \ -+ int16_t * a_ = (a); \ -+ __asm__ ("st1 {%1.h}[%2],[%0]" \ -+ : \ -+ : "r"(a_), "w"(b_), "i"(c) \ -+ : "memory"); \ -+ }) -+ -+#define vst1_lane_s32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int32x2_t b_ = (b); \ -+ int32_t * a_ = (a); \ -+ __asm__ ("st1 {%1.s}[%2],[%0]" \ -+ : \ -+ : "r"(a_), "w"(b_), "i"(c) \ -+ : "memory"); \ -+ }) -+ -+#define vst1_lane_s64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int64x1_t b_ = (b); \ -+ int64_t * a_ = (a); \ -+ __asm__ ("st1 {%1.d}[%2],[%0]" \ -+ : \ -+ : "r"(a_), "w"(b_), "i"(c) \ -+ : "memory"); \ -+ }) -+ -+#define vst1_lane_u8(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint8x8_t b_ = (b); \ -+ uint8_t * a_ = (a); \ -+ __asm__ ("st1 {%1.b}[%2],[%0]" \ -+ : \ -+ : "r"(a_), "w"(b_), "i"(c) \ -+ : "memory"); \ -+ }) -+ -+#define vst1_lane_u16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint16x4_t b_ = (b); \ -+ uint16_t * a_ = (a); \ -+ __asm__ ("st1 {%1.h}[%2],[%0]" \ -+ : \ -+ : "r"(a_), "w"(b_), "i"(c) \ -+ : "memory"); \ -+ }) -+ -+#define vst1_lane_u32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint32x2_t b_ = (b); \ -+ uint32_t * a_ = (a); \ -+ __asm__ ("st1 {%1.s}[%2],[%0]" \ -+ : \ -+ : "r"(a_), "w"(b_), "i"(c) \ -+ : "memory"); \ -+ }) -+ -+#define vst1_lane_u64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint64x1_t b_ = (b); \ -+ uint64_t * a_ = (a); \ -+ __asm__ ("st1 {%1.d}[%2],[%0]" \ -+ : \ -+ : "r"(a_), "w"(b_), "i"(c) \ -+ : "memory"); \ -+ }) -+ -+__extension__ static __inline void __attribute__ ((__always_inline__)) -+vst1_p8 (poly8_t * a, poly8x8_t b) -+{ -+ __asm__ ("st1 {%1.8b},[%0]" -+ : -+ : "r"(a), "w"(b) -+ : "memory"); -+} -+ -+__extension__ static __inline void __attribute__ ((__always_inline__)) -+vst1_p16 (poly16_t * a, poly16x4_t b) -+{ -+ __asm__ ("st1 {%1.4h},[%0]" -+ : -+ : "r"(a), "w"(b) -+ : "memory"); -+} -+ -+__extension__ static __inline void __attribute__ ((__always_inline__)) -+vst1_s8 (int8_t * a, int8x8_t b) -+{ -+ __asm__ ("st1 {%1.8b},[%0]" -+ : -+ : "r"(a), "w"(b) -+ : "memory"); -+} -+ -+__extension__ static __inline void __attribute__ ((__always_inline__)) -+vst1_s16 (int16_t * a, int16x4_t b) -+{ -+ __asm__ ("st1 {%1.4h},[%0]" -+ : -+ : "r"(a), "w"(b) -+ : "memory"); -+} -+ -+__extension__ static __inline void __attribute__ ((__always_inline__)) -+vst1_s32 (int32_t * a, int32x2_t b) -+{ -+ __asm__ ("st1 {%1.2s},[%0]" -+ : -+ : "r"(a), "w"(b) -+ : "memory"); -+} -+ -+__extension__ static __inline void __attribute__ ((__always_inline__)) -+vst1_s64 (int64_t * a, int64x1_t b) -+{ -+ __asm__ ("st1 {%1.1d},[%0]" -+ : -+ : "r"(a), "w"(b) -+ : "memory"); -+} -+ -+__extension__ static __inline void __attribute__ ((__always_inline__)) -+vst1_u8 (uint8_t * a, uint8x8_t b) -+{ -+ __asm__ ("st1 {%1.8b},[%0]" -+ : -+ : "r"(a), "w"(b) -+ : "memory"); -+} -+ -+__extension__ static __inline void __attribute__ ((__always_inline__)) -+vst1_u16 (uint16_t * a, uint16x4_t b) -+{ -+ __asm__ ("st1 {%1.4h},[%0]" -+ : -+ : "r"(a), "w"(b) -+ : "memory"); -+} -+ -+__extension__ static __inline void __attribute__ ((__always_inline__)) -+vst1_u32 (uint32_t * a, uint32x2_t b) -+{ -+ __asm__ ("st1 {%1.2s},[%0]" -+ : -+ : "r"(a), "w"(b) -+ : "memory"); -+} -+ -+__extension__ static __inline void __attribute__ ((__always_inline__)) -+vst1_u64 (uint64_t * a, uint64x1_t b) -+{ -+ __asm__ ("st1 {%1.1d},[%0]" -+ : -+ : "r"(a), "w"(b) -+ : "memory"); -+} -+ -+__extension__ static __inline void __attribute__ ((__always_inline__)) -+vst1q_f32 (float32_t * a, float32x4_t b) -+{ -+ __asm__ ("st1 {%1.4s},[%0]" -+ : -+ : "r"(a), "w"(b) -+ : "memory"); -+} -+ -+__extension__ static __inline void __attribute__ ((__always_inline__)) -+vst1q_f64 (float64_t * a, float64x2_t b) -+{ -+ __asm__ ("st1 {%1.2d},[%0]" -+ : -+ : "r"(a), "w"(b) -+ : "memory"); -+} -+ -+#define vst1q_lane_f32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float32x4_t b_ = (b); \ -+ float32_t * a_ = (a); \ -+ __asm__ ("st1 {%1.s}[%2],[%0]" \ -+ : \ -+ : "r"(a_), "w"(b_), "i"(c) \ -+ : "memory"); \ -+ }) -+ -+#define vst1q_lane_f64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ float64x2_t b_ = (b); \ -+ float64_t * a_ = (a); \ -+ __asm__ ("st1 {%1.d}[%2],[%0]" \ -+ : \ -+ : "r"(a_), "w"(b_), "i"(c) \ -+ : "memory"); \ -+ }) -+ -+#define vst1q_lane_p8(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ poly8x16_t b_ = (b); \ -+ poly8_t * a_ = (a); \ -+ __asm__ ("st1 {%1.b}[%2],[%0]" \ -+ : \ -+ : "r"(a_), "w"(b_), "i"(c) \ -+ : "memory"); \ -+ }) -+ -+#define vst1q_lane_p16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ poly16x8_t b_ = (b); \ -+ poly16_t * a_ = (a); \ -+ __asm__ ("st1 {%1.h}[%2],[%0]" \ -+ : \ -+ : "r"(a_), "w"(b_), "i"(c) \ -+ : "memory"); \ -+ }) -+ -+#define vst1q_lane_s8(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int8x16_t b_ = (b); \ -+ int8_t * a_ = (a); \ -+ __asm__ ("st1 {%1.b}[%2],[%0]" \ -+ : \ -+ : "r"(a_), "w"(b_), "i"(c) \ -+ : "memory"); \ -+ }) -+ -+#define vst1q_lane_s16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int16x8_t b_ = (b); \ -+ int16_t * a_ = (a); \ -+ __asm__ ("st1 {%1.h}[%2],[%0]" \ -+ : \ -+ : "r"(a_), "w"(b_), "i"(c) \ -+ : "memory"); \ -+ }) -+ -+#define vst1q_lane_s32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int32x4_t b_ = (b); \ -+ int32_t * a_ = (a); \ -+ __asm__ ("st1 {%1.s}[%2],[%0]" \ -+ : \ -+ : "r"(a_), "w"(b_), "i"(c) \ -+ : "memory"); \ -+ }) -+ -+#define vst1q_lane_s64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ int64x2_t b_ = (b); \ -+ int64_t * a_ = (a); \ -+ __asm__ ("st1 {%1.d}[%2],[%0]" \ -+ : \ -+ : "r"(a_), "w"(b_), "i"(c) \ -+ : "memory"); \ -+ }) -+ -+#define vst1q_lane_u8(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint8x16_t b_ = (b); \ -+ uint8_t * a_ = (a); \ -+ __asm__ ("st1 {%1.b}[%2],[%0]" \ -+ : \ -+ : "r"(a_), "w"(b_), "i"(c) \ -+ : "memory"); \ -+ }) -+ -+#define vst1q_lane_u16(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint16x8_t b_ = (b); \ -+ uint16_t * a_ = (a); \ -+ __asm__ ("st1 {%1.h}[%2],[%0]" \ -+ : \ -+ : "r"(a_), "w"(b_), "i"(c) \ -+ : "memory"); \ -+ }) -+ -+#define vst1q_lane_u32(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint32x4_t b_ = (b); \ -+ uint32_t * a_ = (a); \ -+ __asm__ ("st1 {%1.s}[%2],[%0]" \ -+ : \ -+ : "r"(a_), "w"(b_), "i"(c) \ -+ : "memory"); \ -+ }) -+ -+#define vst1q_lane_u64(a, b, c) \ -+ __extension__ \ -+ ({ \ -+ uint64x2_t b_ = (b); \ -+ uint64_t * a_ = (a); \ -+ __asm__ ("st1 {%1.d}[%2],[%0]" \ -+ : \ -+ : "r"(a_), "w"(b_), "i"(c) \ -+ : "memory"); \ -+ }) -+ -+__extension__ static __inline void __attribute__ ((__always_inline__)) -+vst1q_p8 (poly8_t * a, poly8x16_t b) -+{ -+ __asm__ ("st1 {%1.16b},[%0]" -+ : -+ : "r"(a), "w"(b) -+ : "memory"); -+} -+ -+__extension__ static __inline void __attribute__ ((__always_inline__)) -+vst1q_p16 (poly16_t * a, poly16x8_t b) -+{ -+ __asm__ ("st1 {%1.8h},[%0]" -+ : -+ : "r"(a), "w"(b) -+ : "memory"); -+} -+ -+__extension__ static __inline void __attribute__ ((__always_inline__)) -+vst1q_s8 (int8_t * a, int8x16_t b) -+{ -+ __asm__ ("st1 {%1.16b},[%0]" -+ : -+ : "r"(a), "w"(b) -+ : "memory"); -+} -+ -+__extension__ static __inline void __attribute__ ((__always_inline__)) -+vst1q_s16 (int16_t * a, int16x8_t b) -+{ -+ __asm__ ("st1 {%1.8h},[%0]" -+ : -+ : "r"(a), "w"(b) -+ : "memory"); -+} -+ -+__extension__ static __inline void __attribute__ ((__always_inline__)) -+vst1q_s32 (int32_t * a, int32x4_t b) -+{ -+ __asm__ ("st1 {%1.4s},[%0]" -+ : -+ : "r"(a), "w"(b) -+ : "memory"); -+} -+ -+__extension__ static __inline void __attribute__ ((__always_inline__)) -+vst1q_s64 (int64_t * a, int64x2_t b) -+{ -+ __asm__ ("st1 {%1.2d},[%0]" -+ : -+ : "r"(a), "w"(b) -+ : "memory"); -+} -+ -+__extension__ static __inline void __attribute__ ((__always_inline__)) -+vst1q_u8 (uint8_t * a, uint8x16_t b) -+{ -+ __asm__ ("st1 {%1.16b},[%0]" -+ : -+ : "r"(a), "w"(b) -+ : "memory"); -+} -+ -+__extension__ static __inline void __attribute__ ((__always_inline__)) -+vst1q_u16 (uint16_t * a, uint16x8_t b) -+{ -+ __asm__ ("st1 {%1.8h},[%0]" -+ : -+ : "r"(a), "w"(b) -+ : "memory"); -+} -+ -+__extension__ static __inline void __attribute__ ((__always_inline__)) -+vst1q_u32 (uint32_t * a, uint32x4_t b) -+{ -+ __asm__ ("st1 {%1.4s},[%0]" -+ : -+ : "r"(a), "w"(b) -+ : "memory"); -+} -+ -+__extension__ static __inline void __attribute__ ((__always_inline__)) -+vst1q_u64 (uint64_t * a, uint64x2_t b) -+{ -+ __asm__ ("st1 {%1.2d},[%0]" -+ : -+ : "r"(a), "w"(b) -+ : "memory"); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vsubhn_high_s16 (int8x8_t a, int16x8_t b, int16x8_t c) -+{ -+ int8x16_t result = vcombine_s8 (a, vcreate_s8 (UINT64_C (0x0))); -+ __asm__ ("subhn2 %0.16b, %1.8h, %2.8h" -+ : "+w"(result) -+ : "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vsubhn_high_s32 (int16x4_t a, int32x4_t b, int32x4_t c) -+{ -+ int16x8_t result = vcombine_s16 (a, vcreate_s16 (UINT64_C (0x0))); -+ __asm__ ("subhn2 %0.8h, %1.4s, %2.4s" -+ : "+w"(result) -+ : "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vsubhn_high_s64 (int32x2_t a, int64x2_t b, int64x2_t c) -+{ -+ int32x4_t result = vcombine_s32 (a, vcreate_s32 (UINT64_C (0x0))); -+ __asm__ ("subhn2 %0.4s, %1.2d, %2.2d" -+ : "+w"(result) -+ : "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vsubhn_high_u16 (uint8x8_t a, uint16x8_t b, uint16x8_t c) -+{ -+ uint8x16_t result = vcombine_u8 (a, vcreate_u8 (UINT64_C (0x0))); -+ __asm__ ("subhn2 %0.16b, %1.8h, %2.8h" -+ : "+w"(result) -+ : "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vsubhn_high_u32 (uint16x4_t a, uint32x4_t b, uint32x4_t c) -+{ -+ uint16x8_t result = vcombine_u16 (a, vcreate_u16 (UINT64_C (0x0))); -+ __asm__ ("subhn2 %0.8h, %1.4s, %2.4s" -+ : "+w"(result) -+ : "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vsubhn_high_u64 (uint32x2_t a, uint64x2_t b, uint64x2_t c) -+{ -+ uint32x4_t result = vcombine_u32 (a, vcreate_u32 (UINT64_C (0x0))); -+ __asm__ ("subhn2 %0.4s, %1.2d, %2.2d" -+ : "+w"(result) -+ : "w"(b), "w"(c) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vsubhn_s16 (int16x8_t a, int16x8_t b) -+{ -+ int8x8_t result; -+ __asm__ ("subhn %0.8b, %1.8h, %2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vsubhn_s32 (int32x4_t a, int32x4_t b) -+{ -+ int16x4_t result; -+ __asm__ ("subhn %0.4h, %1.4s, %2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vsubhn_s64 (int64x2_t a, int64x2_t b) -+{ -+ int32x2_t result; -+ __asm__ ("subhn %0.2s, %1.2d, %2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vsubhn_u16 (uint16x8_t a, uint16x8_t b) -+{ -+ uint8x8_t result; -+ __asm__ ("subhn %0.8b, %1.8h, %2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vsubhn_u32 (uint32x4_t a, uint32x4_t b) -+{ -+ uint16x4_t result; -+ __asm__ ("subhn %0.4h, %1.4s, %2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vsubhn_u64 (uint64x2_t a, uint64x2_t b) -+{ -+ uint32x2_t result; -+ __asm__ ("subhn %0.2s, %1.2d, %2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vtrn1_f32 (float32x2_t a, float32x2_t b) -+{ -+ float32x2_t result; -+ __asm__ ("trn1 %0.2s,%1.2s,%2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vtrn1_p8 (poly8x8_t a, poly8x8_t b) -+{ -+ poly8x8_t result; -+ __asm__ ("trn1 %0.8b,%1.8b,%2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) -+vtrn1_p16 (poly16x4_t a, poly16x4_t b) -+{ -+ poly16x4_t result; -+ __asm__ ("trn1 %0.4h,%1.4h,%2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vtrn1_s8 (int8x8_t a, int8x8_t b) -+{ -+ int8x8_t result; -+ __asm__ ("trn1 %0.8b,%1.8b,%2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vtrn1_s16 (int16x4_t a, int16x4_t b) -+{ -+ int16x4_t result; -+ __asm__ ("trn1 %0.4h,%1.4h,%2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vtrn1_s32 (int32x2_t a, int32x2_t b) -+{ -+ int32x2_t result; -+ __asm__ ("trn1 %0.2s,%1.2s,%2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vtrn1_u8 (uint8x8_t a, uint8x8_t b) -+{ -+ uint8x8_t result; -+ __asm__ ("trn1 %0.8b,%1.8b,%2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vtrn1_u16 (uint16x4_t a, uint16x4_t b) -+{ -+ uint16x4_t result; -+ __asm__ ("trn1 %0.4h,%1.4h,%2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vtrn1_u32 (uint32x2_t a, uint32x2_t b) -+{ -+ uint32x2_t result; -+ __asm__ ("trn1 %0.2s,%1.2s,%2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vtrn1q_f32 (float32x4_t a, float32x4_t b) -+{ -+ float32x4_t result; -+ __asm__ ("trn1 %0.4s,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vtrn1q_f64 (float64x2_t a, float64x2_t b) -+{ -+ float64x2_t result; -+ __asm__ ("trn1 %0.2d,%1.2d,%2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vtrn1q_p8 (poly8x16_t a, poly8x16_t b) -+{ -+ poly8x16_t result; -+ __asm__ ("trn1 %0.16b,%1.16b,%2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) -+vtrn1q_p16 (poly16x8_t a, poly16x8_t b) -+{ -+ poly16x8_t result; -+ __asm__ ("trn1 %0.8h,%1.8h,%2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vtrn1q_s8 (int8x16_t a, int8x16_t b) -+{ -+ int8x16_t result; -+ __asm__ ("trn1 %0.16b,%1.16b,%2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vtrn1q_s16 (int16x8_t a, int16x8_t b) -+{ -+ int16x8_t result; -+ __asm__ ("trn1 %0.8h,%1.8h,%2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vtrn1q_s32 (int32x4_t a, int32x4_t b) -+{ -+ int32x4_t result; -+ __asm__ ("trn1 %0.4s,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vtrn1q_s64 (int64x2_t a, int64x2_t b) -+{ -+ int64x2_t result; -+ __asm__ ("trn1 %0.2d,%1.2d,%2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vtrn1q_u8 (uint8x16_t a, uint8x16_t b) -+{ -+ uint8x16_t result; -+ __asm__ ("trn1 %0.16b,%1.16b,%2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vtrn1q_u16 (uint16x8_t a, uint16x8_t b) -+{ -+ uint16x8_t result; -+ __asm__ ("trn1 %0.8h,%1.8h,%2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vtrn1q_u32 (uint32x4_t a, uint32x4_t b) -+{ -+ uint32x4_t result; -+ __asm__ ("trn1 %0.4s,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vtrn1q_u64 (uint64x2_t a, uint64x2_t b) -+{ -+ uint64x2_t result; -+ __asm__ ("trn1 %0.2d,%1.2d,%2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vtrn2_f32 (float32x2_t a, float32x2_t b) -+{ -+ float32x2_t result; -+ __asm__ ("trn2 %0.2s,%1.2s,%2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vtrn2_p8 (poly8x8_t a, poly8x8_t b) -+{ -+ poly8x8_t result; -+ __asm__ ("trn2 %0.8b,%1.8b,%2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) -+vtrn2_p16 (poly16x4_t a, poly16x4_t b) -+{ -+ poly16x4_t result; -+ __asm__ ("trn2 %0.4h,%1.4h,%2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vtrn2_s8 (int8x8_t a, int8x8_t b) -+{ -+ int8x8_t result; -+ __asm__ ("trn2 %0.8b,%1.8b,%2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vtrn2_s16 (int16x4_t a, int16x4_t b) -+{ -+ int16x4_t result; -+ __asm__ ("trn2 %0.4h,%1.4h,%2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vtrn2_s32 (int32x2_t a, int32x2_t b) -+{ -+ int32x2_t result; -+ __asm__ ("trn2 %0.2s,%1.2s,%2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vtrn2_u8 (uint8x8_t a, uint8x8_t b) -+{ -+ uint8x8_t result; -+ __asm__ ("trn2 %0.8b,%1.8b,%2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vtrn2_u16 (uint16x4_t a, uint16x4_t b) -+{ -+ uint16x4_t result; -+ __asm__ ("trn2 %0.4h,%1.4h,%2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vtrn2_u32 (uint32x2_t a, uint32x2_t b) -+{ -+ uint32x2_t result; -+ __asm__ ("trn2 %0.2s,%1.2s,%2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vtrn2q_f32 (float32x4_t a, float32x4_t b) -+{ -+ float32x4_t result; -+ __asm__ ("trn2 %0.4s,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vtrn2q_f64 (float64x2_t a, float64x2_t b) -+{ -+ float64x2_t result; -+ __asm__ ("trn2 %0.2d,%1.2d,%2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vtrn2q_p8 (poly8x16_t a, poly8x16_t b) -+{ -+ poly8x16_t result; -+ __asm__ ("trn2 %0.16b,%1.16b,%2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) -+vtrn2q_p16 (poly16x8_t a, poly16x8_t b) -+{ -+ poly16x8_t result; -+ __asm__ ("trn2 %0.8h,%1.8h,%2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vtrn2q_s8 (int8x16_t a, int8x16_t b) -+{ -+ int8x16_t result; -+ __asm__ ("trn2 %0.16b,%1.16b,%2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vtrn2q_s16 (int16x8_t a, int16x8_t b) -+{ -+ int16x8_t result; -+ __asm__ ("trn2 %0.8h,%1.8h,%2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vtrn2q_s32 (int32x4_t a, int32x4_t b) -+{ -+ int32x4_t result; -+ __asm__ ("trn2 %0.4s,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vtrn2q_s64 (int64x2_t a, int64x2_t b) -+{ -+ int64x2_t result; -+ __asm__ ("trn2 %0.2d,%1.2d,%2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vtrn2q_u8 (uint8x16_t a, uint8x16_t b) -+{ -+ uint8x16_t result; -+ __asm__ ("trn2 %0.16b,%1.16b,%2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vtrn2q_u16 (uint16x8_t a, uint16x8_t b) -+{ -+ uint16x8_t result; -+ __asm__ ("trn2 %0.8h,%1.8h,%2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vtrn2q_u32 (uint32x4_t a, uint32x4_t b) -+{ -+ uint32x4_t result; -+ __asm__ ("trn2 %0.4s,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vtrn2q_u64 (uint64x2_t a, uint64x2_t b) -+{ -+ uint64x2_t result; -+ __asm__ ("trn2 %0.2d,%1.2d,%2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vtst_p8 (poly8x8_t a, poly8x8_t b) -+{ -+ uint8x8_t result; -+ __asm__ ("cmtst %0.8b, %1.8b, %2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vtst_p16 (poly16x4_t a, poly16x4_t b) -+{ -+ uint16x4_t result; -+ __asm__ ("cmtst %0.4h, %1.4h, %2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vtstq_p8 (poly8x16_t a, poly8x16_t b) -+{ -+ uint8x16_t result; -+ __asm__ ("cmtst %0.16b, %1.16b, %2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vtstq_p16 (poly16x8_t a, poly16x8_t b) -+{ -+ uint16x8_t result; -+ __asm__ ("cmtst %0.8h, %1.8h, %2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vuzp1_f32 (float32x2_t a, float32x2_t b) -+{ -+ float32x2_t result; -+ __asm__ ("uzp1 %0.2s,%1.2s,%2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vuzp1_p8 (poly8x8_t a, poly8x8_t b) -+{ -+ poly8x8_t result; -+ __asm__ ("uzp1 %0.8b,%1.8b,%2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) -+vuzp1_p16 (poly16x4_t a, poly16x4_t b) -+{ -+ poly16x4_t result; -+ __asm__ ("uzp1 %0.4h,%1.4h,%2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vuzp1_s8 (int8x8_t a, int8x8_t b) -+{ -+ int8x8_t result; -+ __asm__ ("uzp1 %0.8b,%1.8b,%2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vuzp1_s16 (int16x4_t a, int16x4_t b) -+{ -+ int16x4_t result; -+ __asm__ ("uzp1 %0.4h,%1.4h,%2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vuzp1_s32 (int32x2_t a, int32x2_t b) -+{ -+ int32x2_t result; -+ __asm__ ("uzp1 %0.2s,%1.2s,%2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vuzp1_u8 (uint8x8_t a, uint8x8_t b) -+{ -+ uint8x8_t result; -+ __asm__ ("uzp1 %0.8b,%1.8b,%2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vuzp1_u16 (uint16x4_t a, uint16x4_t b) -+{ -+ uint16x4_t result; -+ __asm__ ("uzp1 %0.4h,%1.4h,%2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vuzp1_u32 (uint32x2_t a, uint32x2_t b) -+{ -+ uint32x2_t result; -+ __asm__ ("uzp1 %0.2s,%1.2s,%2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vuzp1q_f32 (float32x4_t a, float32x4_t b) -+{ -+ float32x4_t result; -+ __asm__ ("uzp1 %0.4s,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vuzp1q_f64 (float64x2_t a, float64x2_t b) -+{ -+ float64x2_t result; -+ __asm__ ("uzp1 %0.2d,%1.2d,%2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vuzp1q_p8 (poly8x16_t a, poly8x16_t b) -+{ -+ poly8x16_t result; -+ __asm__ ("uzp1 %0.16b,%1.16b,%2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) -+vuzp1q_p16 (poly16x8_t a, poly16x8_t b) -+{ -+ poly16x8_t result; -+ __asm__ ("uzp1 %0.8h,%1.8h,%2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vuzp1q_s8 (int8x16_t a, int8x16_t b) -+{ -+ int8x16_t result; -+ __asm__ ("uzp1 %0.16b,%1.16b,%2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vuzp1q_s16 (int16x8_t a, int16x8_t b) -+{ -+ int16x8_t result; -+ __asm__ ("uzp1 %0.8h,%1.8h,%2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vuzp1q_s32 (int32x4_t a, int32x4_t b) -+{ -+ int32x4_t result; -+ __asm__ ("uzp1 %0.4s,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vuzp1q_s64 (int64x2_t a, int64x2_t b) -+{ -+ int64x2_t result; -+ __asm__ ("uzp1 %0.2d,%1.2d,%2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vuzp1q_u8 (uint8x16_t a, uint8x16_t b) -+{ -+ uint8x16_t result; -+ __asm__ ("uzp1 %0.16b,%1.16b,%2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vuzp1q_u16 (uint16x8_t a, uint16x8_t b) -+{ -+ uint16x8_t result; -+ __asm__ ("uzp1 %0.8h,%1.8h,%2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vuzp1q_u32 (uint32x4_t a, uint32x4_t b) -+{ -+ uint32x4_t result; -+ __asm__ ("uzp1 %0.4s,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vuzp1q_u64 (uint64x2_t a, uint64x2_t b) -+{ -+ uint64x2_t result; -+ __asm__ ("uzp1 %0.2d,%1.2d,%2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vuzp2_f32 (float32x2_t a, float32x2_t b) -+{ -+ float32x2_t result; -+ __asm__ ("uzp2 %0.2s,%1.2s,%2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vuzp2_p8 (poly8x8_t a, poly8x8_t b) -+{ -+ poly8x8_t result; -+ __asm__ ("uzp2 %0.8b,%1.8b,%2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) -+vuzp2_p16 (poly16x4_t a, poly16x4_t b) -+{ -+ poly16x4_t result; -+ __asm__ ("uzp2 %0.4h,%1.4h,%2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vuzp2_s8 (int8x8_t a, int8x8_t b) -+{ -+ int8x8_t result; -+ __asm__ ("uzp2 %0.8b,%1.8b,%2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vuzp2_s16 (int16x4_t a, int16x4_t b) -+{ -+ int16x4_t result; -+ __asm__ ("uzp2 %0.4h,%1.4h,%2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vuzp2_s32 (int32x2_t a, int32x2_t b) -+{ -+ int32x2_t result; -+ __asm__ ("uzp2 %0.2s,%1.2s,%2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vuzp2_u8 (uint8x8_t a, uint8x8_t b) -+{ -+ uint8x8_t result; -+ __asm__ ("uzp2 %0.8b,%1.8b,%2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vuzp2_u16 (uint16x4_t a, uint16x4_t b) -+{ -+ uint16x4_t result; -+ __asm__ ("uzp2 %0.4h,%1.4h,%2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vuzp2_u32 (uint32x2_t a, uint32x2_t b) -+{ -+ uint32x2_t result; -+ __asm__ ("uzp2 %0.2s,%1.2s,%2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vuzp2q_f32 (float32x4_t a, float32x4_t b) -+{ -+ float32x4_t result; -+ __asm__ ("uzp2 %0.4s,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vuzp2q_f64 (float64x2_t a, float64x2_t b) -+{ -+ float64x2_t result; -+ __asm__ ("uzp2 %0.2d,%1.2d,%2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vuzp2q_p8 (poly8x16_t a, poly8x16_t b) -+{ -+ poly8x16_t result; -+ __asm__ ("uzp2 %0.16b,%1.16b,%2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) -+vuzp2q_p16 (poly16x8_t a, poly16x8_t b) -+{ -+ poly16x8_t result; -+ __asm__ ("uzp2 %0.8h,%1.8h,%2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vuzp2q_s8 (int8x16_t a, int8x16_t b) -+{ -+ int8x16_t result; -+ __asm__ ("uzp2 %0.16b,%1.16b,%2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vuzp2q_s16 (int16x8_t a, int16x8_t b) -+{ -+ int16x8_t result; -+ __asm__ ("uzp2 %0.8h,%1.8h,%2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vuzp2q_s32 (int32x4_t a, int32x4_t b) -+{ -+ int32x4_t result; -+ __asm__ ("uzp2 %0.4s,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vuzp2q_s64 (int64x2_t a, int64x2_t b) -+{ -+ int64x2_t result; -+ __asm__ ("uzp2 %0.2d,%1.2d,%2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vuzp2q_u8 (uint8x16_t a, uint8x16_t b) -+{ -+ uint8x16_t result; -+ __asm__ ("uzp2 %0.16b,%1.16b,%2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vuzp2q_u16 (uint16x8_t a, uint16x8_t b) -+{ -+ uint16x8_t result; -+ __asm__ ("uzp2 %0.8h,%1.8h,%2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vuzp2q_u32 (uint32x4_t a, uint32x4_t b) -+{ -+ uint32x4_t result; -+ __asm__ ("uzp2 %0.4s,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vuzp2q_u64 (uint64x2_t a, uint64x2_t b) -+{ -+ uint64x2_t result; -+ __asm__ ("uzp2 %0.2d,%1.2d,%2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vzip1_f32 (float32x2_t a, float32x2_t b) -+{ -+ float32x2_t result; -+ __asm__ ("zip1 %0.2s,%1.2s,%2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vzip1_p8 (poly8x8_t a, poly8x8_t b) -+{ -+ poly8x8_t result; -+ __asm__ ("zip1 %0.8b,%1.8b,%2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) -+vzip1_p16 (poly16x4_t a, poly16x4_t b) -+{ -+ poly16x4_t result; -+ __asm__ ("zip1 %0.4h,%1.4h,%2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vzip1_s8 (int8x8_t a, int8x8_t b) -+{ -+ int8x8_t result; -+ __asm__ ("zip1 %0.8b,%1.8b,%2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vzip1_s16 (int16x4_t a, int16x4_t b) -+{ -+ int16x4_t result; -+ __asm__ ("zip1 %0.4h,%1.4h,%2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vzip1_s32 (int32x2_t a, int32x2_t b) -+{ -+ int32x2_t result; -+ __asm__ ("zip1 %0.2s,%1.2s,%2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vzip1_u8 (uint8x8_t a, uint8x8_t b) -+{ -+ uint8x8_t result; -+ __asm__ ("zip1 %0.8b,%1.8b,%2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vzip1_u16 (uint16x4_t a, uint16x4_t b) -+{ -+ uint16x4_t result; -+ __asm__ ("zip1 %0.4h,%1.4h,%2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vzip1_u32 (uint32x2_t a, uint32x2_t b) -+{ -+ uint32x2_t result; -+ __asm__ ("zip1 %0.2s,%1.2s,%2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vzip1q_f32 (float32x4_t a, float32x4_t b) -+{ -+ float32x4_t result; -+ __asm__ ("zip1 %0.4s,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vzip1q_f64 (float64x2_t a, float64x2_t b) -+{ -+ float64x2_t result; -+ __asm__ ("zip1 %0.2d,%1.2d,%2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vzip1q_p8 (poly8x16_t a, poly8x16_t b) -+{ -+ poly8x16_t result; -+ __asm__ ("zip1 %0.16b,%1.16b,%2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) -+vzip1q_p16 (poly16x8_t a, poly16x8_t b) -+{ -+ poly16x8_t result; -+ __asm__ ("zip1 %0.8h,%1.8h,%2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vzip1q_s8 (int8x16_t a, int8x16_t b) -+{ -+ int8x16_t result; -+ __asm__ ("zip1 %0.16b,%1.16b,%2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vzip1q_s16 (int16x8_t a, int16x8_t b) -+{ -+ int16x8_t result; -+ __asm__ ("zip1 %0.8h,%1.8h,%2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vzip1q_s32 (int32x4_t a, int32x4_t b) -+{ -+ int32x4_t result; -+ __asm__ ("zip1 %0.4s,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vzip1q_s64 (int64x2_t a, int64x2_t b) -+{ -+ int64x2_t result; -+ __asm__ ("zip1 %0.2d,%1.2d,%2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vzip1q_u8 (uint8x16_t a, uint8x16_t b) -+{ -+ uint8x16_t result; -+ __asm__ ("zip1 %0.16b,%1.16b,%2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vzip1q_u16 (uint16x8_t a, uint16x8_t b) -+{ -+ uint16x8_t result; -+ __asm__ ("zip1 %0.8h,%1.8h,%2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vzip1q_u32 (uint32x4_t a, uint32x4_t b) -+{ -+ uint32x4_t result; -+ __asm__ ("zip1 %0.4s,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vzip1q_u64 (uint64x2_t a, uint64x2_t b) -+{ -+ uint64x2_t result; -+ __asm__ ("zip1 %0.2d,%1.2d,%2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vzip2_f32 (float32x2_t a, float32x2_t b) -+{ -+ float32x2_t result; -+ __asm__ ("zip2 %0.2s,%1.2s,%2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vzip2_p8 (poly8x8_t a, poly8x8_t b) -+{ -+ poly8x8_t result; -+ __asm__ ("zip2 %0.8b,%1.8b,%2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) -+vzip2_p16 (poly16x4_t a, poly16x4_t b) -+{ -+ poly16x4_t result; -+ __asm__ ("zip2 %0.4h,%1.4h,%2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vzip2_s8 (int8x8_t a, int8x8_t b) -+{ -+ int8x8_t result; -+ __asm__ ("zip2 %0.8b,%1.8b,%2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vzip2_s16 (int16x4_t a, int16x4_t b) -+{ -+ int16x4_t result; -+ __asm__ ("zip2 %0.4h,%1.4h,%2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vzip2_s32 (int32x2_t a, int32x2_t b) -+{ -+ int32x2_t result; -+ __asm__ ("zip2 %0.2s,%1.2s,%2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vzip2_u8 (uint8x8_t a, uint8x8_t b) -+{ -+ uint8x8_t result; -+ __asm__ ("zip2 %0.8b,%1.8b,%2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vzip2_u16 (uint16x4_t a, uint16x4_t b) -+{ -+ uint16x4_t result; -+ __asm__ ("zip2 %0.4h,%1.4h,%2.4h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vzip2_u32 (uint32x2_t a, uint32x2_t b) -+{ -+ uint32x2_t result; -+ __asm__ ("zip2 %0.2s,%1.2s,%2.2s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vzip2q_f32 (float32x4_t a, float32x4_t b) -+{ -+ float32x4_t result; -+ __asm__ ("zip2 %0.4s,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vzip2q_f64 (float64x2_t a, float64x2_t b) -+{ -+ float64x2_t result; -+ __asm__ ("zip2 %0.2d,%1.2d,%2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vzip2q_p8 (poly8x16_t a, poly8x16_t b) -+{ -+ poly8x16_t result; -+ __asm__ ("zip2 %0.16b,%1.16b,%2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) -+vzip2q_p16 (poly16x8_t a, poly16x8_t b) -+{ -+ poly16x8_t result; -+ __asm__ ("zip2 %0.8h,%1.8h,%2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vzip2q_s8 (int8x16_t a, int8x16_t b) -+{ -+ int8x16_t result; -+ __asm__ ("zip2 %0.16b,%1.16b,%2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vzip2q_s16 (int16x8_t a, int16x8_t b) -+{ -+ int16x8_t result; -+ __asm__ ("zip2 %0.8h,%1.8h,%2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vzip2q_s32 (int32x4_t a, int32x4_t b) -+{ -+ int32x4_t result; -+ __asm__ ("zip2 %0.4s,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vzip2q_s64 (int64x2_t a, int64x2_t b) -+{ -+ int64x2_t result; -+ __asm__ ("zip2 %0.2d,%1.2d,%2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vzip2q_u8 (uint8x16_t a, uint8x16_t b) -+{ -+ uint8x16_t result; -+ __asm__ ("zip2 %0.16b,%1.16b,%2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vzip2q_u16 (uint16x8_t a, uint16x8_t b) -+{ -+ uint16x8_t result; -+ __asm__ ("zip2 %0.8h,%1.8h,%2.8h" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vzip2q_u32 (uint32x4_t a, uint32x4_t b) -+{ -+ uint32x4_t result; -+ __asm__ ("zip2 %0.4s,%1.4s,%2.4s" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vzip2q_u64 (uint64x2_t a, uint64x2_t b) -+{ -+ uint64x2_t result; -+ __asm__ ("zip2 %0.2d,%1.2d,%2.2d" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+/* End of temporary inline asm implementations. */ -+ -+/* Start of temporary inline asm for vldn, vstn and friends. */ -+ -+#define __LD2_FUNC(rettype, ptrtype, regsuffix, funcsuffix, Q) \ -+ __extension__ static __inline rettype \ -+ __attribute__ ((__always_inline__)) \ -+ vld2 ## Q ## _ ## funcsuffix (const ptrtype *ptr) \ -+ { \ -+ rettype result; \ -+ __asm__ ("ld2 {v16." #regsuffix ", v17." #regsuffix "}, %1\n\t" \ -+ "st1 {v16." #regsuffix ", v17." #regsuffix "}, %0\n\t" \ -+ : "=Q"(result) \ -+ : "Q"(*(const rettype *)ptr) \ -+ : "memory", "v16", "v17"); \ -+ return result; \ -+ } -+ -+#define __LD2_64x1_FUNC(rettype, ptrtype, funcsuffix) \ -+ __extension__ static __inline rettype \ -+ __attribute__ ((__always_inline__)) \ -+ vld2_ ## funcsuffix (const ptrtype *ptr) \ -+ { \ -+ rettype result; \ -+ __asm__ ("ld1 {v16.1d, v17.1d}, %1\n\t" \ -+ "st1 {v16.1d, v17.1d}, %0\n\t" \ -+ : "=Q"(result) \ -+ : "Q"(*(const rettype *)ptr) \ -+ : "memory", "v16", "v17"); \ -+ return result; \ -+ } -+ -+__LD2_FUNC (float32x2x2_t, float32_t, 2s, f32,) -+__LD2_64x1_FUNC (float64x1x2_t, float64_t, f64) -+__LD2_FUNC (poly8x8x2_t, poly8_t, 8b, p8,) -+__LD2_FUNC (poly16x4x2_t, poly16_t, 4h, p16,) -+__LD2_FUNC (int8x8x2_t, int8_t, 8b, s8,) -+__LD2_FUNC (int16x4x2_t, int16_t, 4h, s16,) -+__LD2_FUNC (int32x2x2_t, int32_t, 2s, s32,) -+__LD2_64x1_FUNC (int64x1x2_t, int64_t, s64) -+__LD2_FUNC (uint8x8x2_t, uint8_t, 8b, u8,) -+__LD2_FUNC (uint16x4x2_t, uint16_t, 4h, u16,) -+__LD2_FUNC (uint32x2x2_t, uint32_t, 2s, u32,) -+__LD2_64x1_FUNC (uint64x1x2_t, uint64_t, u64) -+__LD2_FUNC (float32x4x2_t, float32_t, 4s, f32, q) -+__LD2_FUNC (float64x2x2_t, float64_t, 2d, f64, q) -+__LD2_FUNC (poly8x16x2_t, poly8_t, 16b, p8, q) -+__LD2_FUNC (poly16x8x2_t, poly16_t, 8h, p16, q) -+__LD2_FUNC (int8x16x2_t, int8_t, 16b, s8, q) -+__LD2_FUNC (int16x8x2_t, int16_t, 8h, s16, q) -+__LD2_FUNC (int32x4x2_t, int32_t, 4s, s32, q) -+__LD2_FUNC (int64x2x2_t, int64_t, 2d, s64, q) -+__LD2_FUNC (uint8x16x2_t, uint8_t, 16b, u8, q) -+__LD2_FUNC (uint16x8x2_t, uint16_t, 8h, u16, q) -+__LD2_FUNC (uint32x4x2_t, uint32_t, 4s, u32, q) -+__LD2_FUNC (uint64x2x2_t, uint64_t, 2d, u64, q) -+ -+#define __LD3_FUNC(rettype, ptrtype, regsuffix, funcsuffix, Q) \ -+ __extension__ static __inline rettype \ -+ __attribute__ ((__always_inline__)) \ -+ vld3 ## Q ## _ ## funcsuffix (const ptrtype *ptr) \ -+ { \ -+ rettype result; \ -+ __asm__ ("ld3 {v16." #regsuffix " - v18." #regsuffix "}, %1\n\t" \ -+ "st1 {v16." #regsuffix " - v18." #regsuffix "}, %0\n\t" \ -+ : "=Q"(result) \ -+ : "Q"(*(const rettype *)ptr) \ -+ : "memory", "v16", "v17", "v18"); \ -+ return result; \ -+ } -+ -+#define __LD3_64x1_FUNC(rettype, ptrtype, funcsuffix) \ -+ __extension__ static __inline rettype \ -+ __attribute__ ((__always_inline__)) \ -+ vld3_ ## funcsuffix (const ptrtype *ptr) \ -+ { \ -+ rettype result; \ -+ __asm__ ("ld1 {v16.1d - v18.1d}, %1\n\t" \ -+ "st1 {v16.1d - v18.1d}, %0\n\t" \ -+ : "=Q"(result) \ -+ : "Q"(*(const rettype *)ptr) \ -+ : "memory", "v16", "v17", "v18"); \ -+ return result; \ -+ } -+ -+__LD3_FUNC (float32x2x3_t, float32_t, 2s, f32,) -+__LD3_64x1_FUNC (float64x1x3_t, float64_t, f64) -+__LD3_FUNC (poly8x8x3_t, poly8_t, 8b, p8,) -+__LD3_FUNC (poly16x4x3_t, poly16_t, 4h, p16,) -+__LD3_FUNC (int8x8x3_t, int8_t, 8b, s8,) -+__LD3_FUNC (int16x4x3_t, int16_t, 4h, s16,) -+__LD3_FUNC (int32x2x3_t, int32_t, 2s, s32,) -+__LD3_64x1_FUNC (int64x1x3_t, int64_t, s64) -+__LD3_FUNC (uint8x8x3_t, uint8_t, 8b, u8,) -+__LD3_FUNC (uint16x4x3_t, uint16_t, 4h, u16,) -+__LD3_FUNC (uint32x2x3_t, uint32_t, 2s, u32,) -+__LD3_64x1_FUNC (uint64x1x3_t, uint64_t, u64) -+__LD3_FUNC (float32x4x3_t, float32_t, 4s, f32, q) -+__LD3_FUNC (float64x2x3_t, float64_t, 2d, f64, q) -+__LD3_FUNC (poly8x16x3_t, poly8_t, 16b, p8, q) -+__LD3_FUNC (poly16x8x3_t, poly16_t, 8h, p16, q) -+__LD3_FUNC (int8x16x3_t, int8_t, 16b, s8, q) -+__LD3_FUNC (int16x8x3_t, int16_t, 8h, s16, q) -+__LD3_FUNC (int32x4x3_t, int32_t, 4s, s32, q) -+__LD3_FUNC (int64x2x3_t, int64_t, 2d, s64, q) -+__LD3_FUNC (uint8x16x3_t, uint8_t, 16b, u8, q) -+__LD3_FUNC (uint16x8x3_t, uint16_t, 8h, u16, q) -+__LD3_FUNC (uint32x4x3_t, uint32_t, 4s, u32, q) -+__LD3_FUNC (uint64x2x3_t, uint64_t, 2d, u64, q) -+ -+#define __LD4_FUNC(rettype, ptrtype, regsuffix, funcsuffix, Q) \ -+ __extension__ static __inline rettype \ -+ __attribute__ ((__always_inline__)) \ -+ vld4 ## Q ## _ ## funcsuffix (const ptrtype *ptr) \ -+ { \ -+ rettype result; \ -+ __asm__ ("ld4 {v16." #regsuffix " - v19." #regsuffix "}, %1\n\t" \ -+ "st1 {v16." #regsuffix " - v19." #regsuffix "}, %0\n\t" \ -+ : "=Q"(result) \ -+ : "Q"(*(const rettype *)ptr) \ -+ : "memory", "v16", "v17", "v18", "v19"); \ -+ return result; \ -+ } -+ -+#define __LD4_64x1_FUNC(rettype, ptrtype, funcsuffix) \ -+ __extension__ static __inline rettype \ -+ __attribute__ ((__always_inline__)) \ -+ vld4_ ## funcsuffix (const ptrtype *ptr) \ -+ { \ -+ rettype result; \ -+ __asm__ ("ld1 {v16.1d - v19.1d}, %1\n\t" \ -+ "st1 {v16.1d - v19.1d}, %0\n\t" \ -+ : "=Q"(result) \ -+ : "Q"(*(const rettype *)ptr) \ -+ : "memory", "v16", "v17", "v18", "v19"); \ -+ return result; \ -+ } -+ -+__LD4_FUNC (float32x2x4_t, float32_t, 2s, f32,) -+__LD4_64x1_FUNC (float64x1x4_t, float64_t, f64) -+__LD4_FUNC (poly8x8x4_t, poly8_t, 8b, p8,) -+__LD4_FUNC (poly16x4x4_t, poly16_t, 4h, p16,) -+__LD4_FUNC (int8x8x4_t, int8_t, 8b, s8,) -+__LD4_FUNC (int16x4x4_t, int16_t, 4h, s16,) -+__LD4_FUNC (int32x2x4_t, int32_t, 2s, s32,) -+__LD4_64x1_FUNC (int64x1x4_t, int64_t, s64) -+__LD4_FUNC (uint8x8x4_t, uint8_t, 8b, u8,) -+__LD4_FUNC (uint16x4x4_t, uint16_t, 4h, u16,) -+__LD4_FUNC (uint32x2x4_t, uint32_t, 2s, u32,) -+__LD4_64x1_FUNC (uint64x1x4_t, uint64_t, u64) -+__LD4_FUNC (float32x4x4_t, float32_t, 4s, f32, q) -+__LD4_FUNC (float64x2x4_t, float64_t, 2d, f64, q) -+__LD4_FUNC (poly8x16x4_t, poly8_t, 16b, p8, q) -+__LD4_FUNC (poly16x8x4_t, poly16_t, 8h, p16, q) -+__LD4_FUNC (int8x16x4_t, int8_t, 16b, s8, q) -+__LD4_FUNC (int16x8x4_t, int16_t, 8h, s16, q) -+__LD4_FUNC (int32x4x4_t, int32_t, 4s, s32, q) -+__LD4_FUNC (int64x2x4_t, int64_t, 2d, s64, q) -+__LD4_FUNC (uint8x16x4_t, uint8_t, 16b, u8, q) -+__LD4_FUNC (uint16x8x4_t, uint16_t, 8h, u16, q) -+__LD4_FUNC (uint32x4x4_t, uint32_t, 4s, u32, q) -+__LD4_FUNC (uint64x2x4_t, uint64_t, 2d, u64, q) -+ -+/* Create struct element types for duplicating loads. -+ -+ Create 2 element structures of: -+ -+ +------+----+----+----+----+ -+ | | 8 | 16 | 32 | 64 | -+ +------+----+----+----+----+ -+ |int | Y | Y | N | N | -+ +------+----+----+----+----+ -+ |uint | Y | Y | N | N | -+ +------+----+----+----+----+ -+ |float | - | - | N | N | -+ +------+----+----+----+----+ -+ |poly | Y | Y | - | - | -+ +------+----+----+----+----+ -+ -+ Create 3 element structures of: -+ -+ +------+----+----+----+----+ -+ | | 8 | 16 | 32 | 64 | -+ +------+----+----+----+----+ -+ |int | Y | Y | Y | Y | -+ +------+----+----+----+----+ -+ |uint | Y | Y | Y | Y | -+ +------+----+----+----+----+ -+ |float | - | - | Y | Y | -+ +------+----+----+----+----+ -+ |poly | Y | Y | - | - | -+ +------+----+----+----+----+ -+ -+ Create 4 element structures of: -+ -+ +------+----+----+----+----+ -+ | | 8 | 16 | 32 | 64 | -+ +------+----+----+----+----+ -+ |int | Y | N | N | Y | -+ +------+----+----+----+----+ -+ |uint | Y | N | N | Y | -+ +------+----+----+----+----+ -+ |float | - | - | N | Y | -+ +------+----+----+----+----+ -+ |poly | Y | N | - | - | -+ +------+----+----+----+----+ -+ -+ This is required for casting memory reference. */ -+#define __STRUCTN(t, sz, nelem) \ -+ typedef struct t ## sz ## x ## nelem ## _t { \ -+ t ## sz ## _t val[nelem]; \ -+ } t ## sz ## x ## nelem ## _t; -+ -+/* 2-element structs. */ -+__STRUCTN (int, 8, 2) -+__STRUCTN (int, 16, 2) -+__STRUCTN (uint, 8, 2) -+__STRUCTN (uint, 16, 2) -+__STRUCTN (poly, 8, 2) -+__STRUCTN (poly, 16, 2) -+/* 3-element structs. */ -+__STRUCTN (int, 8, 3) -+__STRUCTN (int, 16, 3) -+__STRUCTN (int, 32, 3) -+__STRUCTN (int, 64, 3) -+__STRUCTN (uint, 8, 3) -+__STRUCTN (uint, 16, 3) -+__STRUCTN (uint, 32, 3) -+__STRUCTN (uint, 64, 3) -+__STRUCTN (float, 32, 3) -+__STRUCTN (float, 64, 3) -+__STRUCTN (poly, 8, 3) -+__STRUCTN (poly, 16, 3) -+/* 4-element structs. */ -+__STRUCTN (int, 8, 4) -+__STRUCTN (int, 64, 4) -+__STRUCTN (uint, 8, 4) -+__STRUCTN (uint, 64, 4) -+__STRUCTN (poly, 8, 4) -+__STRUCTN (float, 64, 4) -+#undef __STRUCTN -+ -+#define __LD2R_FUNC(rettype, structtype, ptrtype, \ -+ regsuffix, funcsuffix, Q) \ -+ __extension__ static __inline rettype \ -+ __attribute__ ((__always_inline__)) \ -+ vld2 ## Q ## _dup_ ## funcsuffix (const ptrtype *ptr) \ -+ { \ -+ rettype result; \ -+ __asm__ ("ld2r {v16." #regsuffix ", v17." #regsuffix "}, %1\n\t" \ -+ "st1 {v16." #regsuffix ", v17." #regsuffix "}, %0\n\t" \ -+ : "=Q"(result) \ -+ : "Q"(*(const structtype *)ptr) \ -+ : "memory", "v16", "v17"); \ -+ return result; \ -+ } -+ -+__LD2R_FUNC (float32x2x2_t, float32x2_t, float32_t, 2s, f32,) -+__LD2R_FUNC (float64x1x2_t, float64x2_t, float64_t, 1d, f64,) -+__LD2R_FUNC (poly8x8x2_t, poly8x2_t, poly8_t, 8b, p8,) -+__LD2R_FUNC (poly16x4x2_t, poly16x2_t, poly16_t, 4h, p16,) -+__LD2R_FUNC (int8x8x2_t, int8x2_t, int8_t, 8b, s8,) -+__LD2R_FUNC (int16x4x2_t, int16x2_t, int16_t, 4h, s16,) -+__LD2R_FUNC (int32x2x2_t, int32x2_t, int32_t, 2s, s32,) -+__LD2R_FUNC (int64x1x2_t, int64x2_t, int64_t, 1d, s64,) -+__LD2R_FUNC (uint8x8x2_t, uint8x2_t, uint8_t, 8b, u8,) -+__LD2R_FUNC (uint16x4x2_t, uint16x2_t, uint16_t, 4h, u16,) -+__LD2R_FUNC (uint32x2x2_t, uint32x2_t, uint32_t, 2s, u32,) -+__LD2R_FUNC (uint64x1x2_t, uint64x2_t, uint64_t, 1d, u64,) -+__LD2R_FUNC (float32x4x2_t, float32x2_t, float32_t, 4s, f32, q) -+__LD2R_FUNC (float64x2x2_t, float64x2_t, float64_t, 2d, f64, q) -+__LD2R_FUNC (poly8x16x2_t, poly8x2_t, poly8_t, 16b, p8, q) -+__LD2R_FUNC (poly16x8x2_t, poly16x2_t, poly16_t, 8h, p16, q) -+__LD2R_FUNC (int8x16x2_t, int8x2_t, int8_t, 16b, s8, q) -+__LD2R_FUNC (int16x8x2_t, int16x2_t, int16_t, 8h, s16, q) -+__LD2R_FUNC (int32x4x2_t, int32x2_t, int32_t, 4s, s32, q) -+__LD2R_FUNC (int64x2x2_t, int64x2_t, int64_t, 2d, s64, q) -+__LD2R_FUNC (uint8x16x2_t, uint8x2_t, uint8_t, 16b, u8, q) -+__LD2R_FUNC (uint16x8x2_t, uint16x2_t, uint16_t, 8h, u16, q) -+__LD2R_FUNC (uint32x4x2_t, uint32x2_t, uint32_t, 4s, u32, q) -+__LD2R_FUNC (uint64x2x2_t, uint64x2_t, uint64_t, 2d, u64, q) -+ -+#define __LD2_LANE_FUNC(rettype, ptrtype, regsuffix, \ -+ lnsuffix, funcsuffix, Q) \ -+ __extension__ static __inline rettype \ -+ __attribute__ ((__always_inline__)) \ -+ vld2 ## Q ## _lane_ ## funcsuffix (const ptrtype *ptr, \ -+ rettype b, const int c) \ -+ { \ -+ rettype result; \ -+ __asm__ ("ld1 {v16." #regsuffix ", v17." #regsuffix "}, %1\n\t" \ -+ "ld2 {v16." #lnsuffix ", v17." #lnsuffix "}[%3], %2\n\t" \ -+ "st1 {v16." #regsuffix ", v17." #regsuffix "}, %0\n\t" \ -+ : "=Q"(result) \ -+ : "Q"(b), "Q"(*(const rettype *)ptr), "i"(c) \ -+ : "memory", "v16", "v17"); \ -+ return result; \ -+ } -+ -+__LD2_LANE_FUNC (int8x8x2_t, uint8_t, 8b, b, s8,) -+__LD2_LANE_FUNC (float32x2x2_t, float32_t, 2s, s, f32,) -+__LD2_LANE_FUNC (float64x1x2_t, float64_t, 1d, d, f64,) -+__LD2_LANE_FUNC (poly8x8x2_t, poly8_t, 8b, b, p8,) -+__LD2_LANE_FUNC (poly16x4x2_t, poly16_t, 4h, h, p16,) -+__LD2_LANE_FUNC (int16x4x2_t, int16_t, 4h, h, s16,) -+__LD2_LANE_FUNC (int32x2x2_t, int32_t, 2s, s, s32,) -+__LD2_LANE_FUNC (int64x1x2_t, int64_t, 1d, d, s64,) -+__LD2_LANE_FUNC (uint8x8x2_t, uint8_t, 8b, b, u8,) -+__LD2_LANE_FUNC (uint16x4x2_t, uint16_t, 4h, h, u16,) -+__LD2_LANE_FUNC (uint32x2x2_t, uint32_t, 2s, s, u32,) -+__LD2_LANE_FUNC (uint64x1x2_t, uint64_t, 1d, d, u64,) -+__LD2_LANE_FUNC (float32x4x2_t, float32_t, 4s, s, f32, q) -+__LD2_LANE_FUNC (float64x2x2_t, float64_t, 2d, d, f64, q) -+__LD2_LANE_FUNC (poly8x16x2_t, poly8_t, 16b, b, p8, q) -+__LD2_LANE_FUNC (poly16x8x2_t, poly16_t, 8h, h, p16, q) -+__LD2_LANE_FUNC (int8x16x2_t, int8_t, 16b, b, s8, q) -+__LD2_LANE_FUNC (int16x8x2_t, int16_t, 8h, h, s16, q) -+__LD2_LANE_FUNC (int32x4x2_t, int32_t, 4s, s, s32, q) -+__LD2_LANE_FUNC (int64x2x2_t, int64_t, 2d, d, s64, q) -+__LD2_LANE_FUNC (uint8x16x2_t, uint8_t, 16b, b, u8, q) -+__LD2_LANE_FUNC (uint16x8x2_t, uint16_t, 8h, h, u16, q) -+__LD2_LANE_FUNC (uint32x4x2_t, uint32_t, 4s, s, u32, q) -+__LD2_LANE_FUNC (uint64x2x2_t, uint64_t, 2d, d, u64, q) -+ -+#define __LD3R_FUNC(rettype, structtype, ptrtype, \ -+ regsuffix, funcsuffix, Q) \ -+ __extension__ static __inline rettype \ -+ __attribute__ ((__always_inline__)) \ -+ vld3 ## Q ## _dup_ ## funcsuffix (const ptrtype *ptr) \ -+ { \ -+ rettype result; \ -+ __asm__ ("ld3r {v16." #regsuffix " - v18." #regsuffix "}, %1\n\t" \ -+ "st1 {v16." #regsuffix " - v18." #regsuffix "}, %0\n\t" \ -+ : "=Q"(result) \ -+ : "Q"(*(const structtype *)ptr) \ -+ : "memory", "v16", "v17", "v18"); \ -+ return result; \ -+ } -+ -+__LD3R_FUNC (float32x2x3_t, float32x3_t, float32_t, 2s, f32,) -+__LD3R_FUNC (float64x1x3_t, float64x3_t, float64_t, 1d, f64,) -+__LD3R_FUNC (poly8x8x3_t, poly8x3_t, poly8_t, 8b, p8,) -+__LD3R_FUNC (poly16x4x3_t, poly16x3_t, poly16_t, 4h, p16,) -+__LD3R_FUNC (int8x8x3_t, int8x3_t, int8_t, 8b, s8,) -+__LD3R_FUNC (int16x4x3_t, int16x3_t, int16_t, 4h, s16,) -+__LD3R_FUNC (int32x2x3_t, int32x3_t, int32_t, 2s, s32,) -+__LD3R_FUNC (int64x1x3_t, int64x3_t, int64_t, 1d, s64,) -+__LD3R_FUNC (uint8x8x3_t, uint8x3_t, uint8_t, 8b, u8,) -+__LD3R_FUNC (uint16x4x3_t, uint16x3_t, uint16_t, 4h, u16,) -+__LD3R_FUNC (uint32x2x3_t, uint32x3_t, uint32_t, 2s, u32,) -+__LD3R_FUNC (uint64x1x3_t, uint64x3_t, uint64_t, 1d, u64,) -+__LD3R_FUNC (float32x4x3_t, float32x3_t, float32_t, 4s, f32, q) -+__LD3R_FUNC (float64x2x3_t, float64x3_t, float64_t, 2d, f64, q) -+__LD3R_FUNC (poly8x16x3_t, poly8x3_t, poly8_t, 16b, p8, q) -+__LD3R_FUNC (poly16x8x3_t, poly16x3_t, poly16_t, 8h, p16, q) -+__LD3R_FUNC (int8x16x3_t, int8x3_t, int8_t, 16b, s8, q) -+__LD3R_FUNC (int16x8x3_t, int16x3_t, int16_t, 8h, s16, q) -+__LD3R_FUNC (int32x4x3_t, int32x3_t, int32_t, 4s, s32, q) -+__LD3R_FUNC (int64x2x3_t, int64x3_t, int64_t, 2d, s64, q) -+__LD3R_FUNC (uint8x16x3_t, uint8x3_t, uint8_t, 16b, u8, q) -+__LD3R_FUNC (uint16x8x3_t, uint16x3_t, uint16_t, 8h, u16, q) -+__LD3R_FUNC (uint32x4x3_t, uint32x3_t, uint32_t, 4s, u32, q) -+__LD3R_FUNC (uint64x2x3_t, uint64x3_t, uint64_t, 2d, u64, q) -+ -+#define __LD3_LANE_FUNC(rettype, ptrtype, regsuffix, \ -+ lnsuffix, funcsuffix, Q) \ -+ __extension__ static __inline rettype \ -+ __attribute__ ((__always_inline__)) \ -+ vld3 ## Q ## _lane_ ## funcsuffix (const ptrtype *ptr, \ -+ rettype b, const int c) \ -+ { \ -+ rettype result; \ -+ __asm__ ("ld1 {v16." #regsuffix " - v18." #regsuffix "}, %1\n\t" \ -+ "ld3 {v16." #lnsuffix " - v18." #lnsuffix "}[%3], %2\n\t" \ -+ "st1 {v16." #regsuffix " - v18." #regsuffix "}, %0\n\t" \ -+ : "=Q"(result) \ -+ : "Q"(b), "Q"(*(const rettype *)ptr), "i"(c) \ -+ : "memory", "v16", "v17", "v18"); \ -+ return result; \ -+ } -+ -+__LD3_LANE_FUNC (int8x8x3_t, uint8_t, 8b, b, s8,) -+__LD3_LANE_FUNC (float32x2x3_t, float32_t, 2s, s, f32,) -+__LD3_LANE_FUNC (float64x1x3_t, float64_t, 1d, d, f64,) -+__LD3_LANE_FUNC (poly8x8x3_t, poly8_t, 8b, b, p8,) -+__LD3_LANE_FUNC (poly16x4x3_t, poly16_t, 4h, h, p16,) -+__LD3_LANE_FUNC (int16x4x3_t, int16_t, 4h, h, s16,) -+__LD3_LANE_FUNC (int32x2x3_t, int32_t, 2s, s, s32,) -+__LD3_LANE_FUNC (int64x1x3_t, int64_t, 1d, d, s64,) -+__LD3_LANE_FUNC (uint8x8x3_t, uint8_t, 8b, b, u8,) -+__LD3_LANE_FUNC (uint16x4x3_t, uint16_t, 4h, h, u16,) -+__LD3_LANE_FUNC (uint32x2x3_t, uint32_t, 2s, s, u32,) -+__LD3_LANE_FUNC (uint64x1x3_t, uint64_t, 1d, d, u64,) -+__LD3_LANE_FUNC (float32x4x3_t, float32_t, 4s, s, f32, q) -+__LD3_LANE_FUNC (float64x2x3_t, float64_t, 2d, d, f64, q) -+__LD3_LANE_FUNC (poly8x16x3_t, poly8_t, 16b, b, p8, q) -+__LD3_LANE_FUNC (poly16x8x3_t, poly16_t, 8h, h, p16, q) -+__LD3_LANE_FUNC (int8x16x3_t, int8_t, 16b, b, s8, q) -+__LD3_LANE_FUNC (int16x8x3_t, int16_t, 8h, h, s16, q) -+__LD3_LANE_FUNC (int32x4x3_t, int32_t, 4s, s, s32, q) -+__LD3_LANE_FUNC (int64x2x3_t, int64_t, 2d, d, s64, q) -+__LD3_LANE_FUNC (uint8x16x3_t, uint8_t, 16b, b, u8, q) -+__LD3_LANE_FUNC (uint16x8x3_t, uint16_t, 8h, h, u16, q) -+__LD3_LANE_FUNC (uint32x4x3_t, uint32_t, 4s, s, u32, q) -+__LD3_LANE_FUNC (uint64x2x3_t, uint64_t, 2d, d, u64, q) -+ -+#define __LD4R_FUNC(rettype, structtype, ptrtype, \ -+ regsuffix, funcsuffix, Q) \ -+ __extension__ static __inline rettype \ -+ __attribute__ ((__always_inline__)) \ -+ vld4 ## Q ## _dup_ ## funcsuffix (const ptrtype *ptr) \ -+ { \ -+ rettype result; \ -+ __asm__ ("ld4r {v16." #regsuffix " - v19." #regsuffix "}, %1\n\t" \ -+ "st1 {v16." #regsuffix " - v19." #regsuffix "}, %0\n\t" \ -+ : "=Q"(result) \ -+ : "Q"(*(const structtype *)ptr) \ -+ : "memory", "v16", "v17", "v18", "v19"); \ -+ return result; \ -+ } -+ -+__LD4R_FUNC (float32x2x4_t, float32x4_t, float32_t, 2s, f32,) -+__LD4R_FUNC (float64x1x4_t, float64x4_t, float64_t, 1d, f64,) -+__LD4R_FUNC (poly8x8x4_t, poly8x4_t, poly8_t, 8b, p8,) -+__LD4R_FUNC (poly16x4x4_t, poly16x4_t, poly16_t, 4h, p16,) -+__LD4R_FUNC (int8x8x4_t, int8x4_t, int8_t, 8b, s8,) -+__LD4R_FUNC (int16x4x4_t, int16x4_t, int16_t, 4h, s16,) -+__LD4R_FUNC (int32x2x4_t, int32x4_t, int32_t, 2s, s32,) -+__LD4R_FUNC (int64x1x4_t, int64x4_t, int64_t, 1d, s64,) -+__LD4R_FUNC (uint8x8x4_t, uint8x4_t, uint8_t, 8b, u8,) -+__LD4R_FUNC (uint16x4x4_t, uint16x4_t, uint16_t, 4h, u16,) -+__LD4R_FUNC (uint32x2x4_t, uint32x4_t, uint32_t, 2s, u32,) -+__LD4R_FUNC (uint64x1x4_t, uint64x4_t, uint64_t, 1d, u64,) -+__LD4R_FUNC (float32x4x4_t, float32x4_t, float32_t, 4s, f32, q) -+__LD4R_FUNC (float64x2x4_t, float64x4_t, float64_t, 2d, f64, q) -+__LD4R_FUNC (poly8x16x4_t, poly8x4_t, poly8_t, 16b, p8, q) -+__LD4R_FUNC (poly16x8x4_t, poly16x4_t, poly16_t, 8h, p16, q) -+__LD4R_FUNC (int8x16x4_t, int8x4_t, int8_t, 16b, s8, q) -+__LD4R_FUNC (int16x8x4_t, int16x4_t, int16_t, 8h, s16, q) -+__LD4R_FUNC (int32x4x4_t, int32x4_t, int32_t, 4s, s32, q) -+__LD4R_FUNC (int64x2x4_t, int64x4_t, int64_t, 2d, s64, q) -+__LD4R_FUNC (uint8x16x4_t, uint8x4_t, uint8_t, 16b, u8, q) -+__LD4R_FUNC (uint16x8x4_t, uint16x4_t, uint16_t, 8h, u16, q) -+__LD4R_FUNC (uint32x4x4_t, uint32x4_t, uint32_t, 4s, u32, q) -+__LD4R_FUNC (uint64x2x4_t, uint64x4_t, uint64_t, 2d, u64, q) -+ -+#define __LD4_LANE_FUNC(rettype, ptrtype, regsuffix, \ -+ lnsuffix, funcsuffix, Q) \ -+ __extension__ static __inline rettype \ -+ __attribute__ ((__always_inline__)) \ -+ vld4 ## Q ## _lane_ ## funcsuffix (const ptrtype *ptr, \ -+ rettype b, const int c) \ -+ { \ -+ rettype result; \ -+ __asm__ ("ld1 {v16." #regsuffix " - v19." #regsuffix "}, %1\n\t" \ -+ "ld4 {v16." #lnsuffix " - v19." #lnsuffix "}[%3], %2\n\t" \ -+ "st1 {v16." #regsuffix " - v19." #regsuffix "}, %0\n\t" \ -+ : "=Q"(result) \ -+ : "Q"(b), "Q"(*(const rettype *)ptr), "i"(c) \ -+ : "memory", "v16", "v17", "v18", "v19"); \ -+ return result; \ -+ } -+ -+__LD4_LANE_FUNC (int8x8x4_t, uint8_t, 8b, b, s8,) -+__LD4_LANE_FUNC (float32x2x4_t, float32_t, 2s, s, f32,) -+__LD4_LANE_FUNC (float64x1x4_t, float64_t, 1d, d, f64,) -+__LD4_LANE_FUNC (poly8x8x4_t, poly8_t, 8b, b, p8,) -+__LD4_LANE_FUNC (poly16x4x4_t, poly16_t, 4h, h, p16,) -+__LD4_LANE_FUNC (int16x4x4_t, int16_t, 4h, h, s16,) -+__LD4_LANE_FUNC (int32x2x4_t, int32_t, 2s, s, s32,) -+__LD4_LANE_FUNC (int64x1x4_t, int64_t, 1d, d, s64,) -+__LD4_LANE_FUNC (uint8x8x4_t, uint8_t, 8b, b, u8,) -+__LD4_LANE_FUNC (uint16x4x4_t, uint16_t, 4h, h, u16,) -+__LD4_LANE_FUNC (uint32x2x4_t, uint32_t, 2s, s, u32,) -+__LD4_LANE_FUNC (uint64x1x4_t, uint64_t, 1d, d, u64,) -+__LD4_LANE_FUNC (float32x4x4_t, float32_t, 4s, s, f32, q) -+__LD4_LANE_FUNC (float64x2x4_t, float64_t, 2d, d, f64, q) -+__LD4_LANE_FUNC (poly8x16x4_t, poly8_t, 16b, b, p8, q) -+__LD4_LANE_FUNC (poly16x8x4_t, poly16_t, 8h, h, p16, q) -+__LD4_LANE_FUNC (int8x16x4_t, int8_t, 16b, b, s8, q) -+__LD4_LANE_FUNC (int16x8x4_t, int16_t, 8h, h, s16, q) -+__LD4_LANE_FUNC (int32x4x4_t, int32_t, 4s, s, s32, q) -+__LD4_LANE_FUNC (int64x2x4_t, int64_t, 2d, d, s64, q) -+__LD4_LANE_FUNC (uint8x16x4_t, uint8_t, 16b, b, u8, q) -+__LD4_LANE_FUNC (uint16x8x4_t, uint16_t, 8h, h, u16, q) -+__LD4_LANE_FUNC (uint32x4x4_t, uint32_t, 4s, s, u32, q) -+__LD4_LANE_FUNC (uint64x2x4_t, uint64_t, 2d, d, u64, q) -+ -+#define __ST2_FUNC(intype, ptrtype, regsuffix, funcsuffix, Q) \ -+ __extension__ static __inline void \ -+ __attribute__ ((__always_inline__)) \ -+ vst2 ## Q ## _ ## funcsuffix (ptrtype *ptr, intype b) \ -+ { \ -+ __asm__ ("ld1 {v16." #regsuffix ", v17." #regsuffix "}, %1\n\t" \ -+ "st2 {v16." #regsuffix ", v17." #regsuffix "}, %0\n\t" \ -+ :"=Q"(*(intype *)ptr) \ -+ :"Q"(b) \ -+ :"v16", "v17", "memory"); \ -+ } -+#define __ST2_64x1_FUNC(intype, ptrtype, funcsuffix) \ -+ __extension__ static __inline void \ -+ __attribute__ ((__always_inline__)) \ -+ vst2_ ## funcsuffix (ptrtype *ptr, intype b) \ -+ { \ -+ __asm__ ("ld1 {v16.1d - v17.1d}, %1\n\t" \ -+ "st1 {v16.1d - v17.1d}, %0\n\t" \ -+ :"=Q"(*(intype *)ptr) \ -+ :"Q"(b) \ -+ :"v16", "v17", "memory"); \ -+ } -+ -+__ST2_FUNC (float32x2x2_t, float32_t, 2s, f32,) -+__ST2_64x1_FUNC (float64x1x2_t, float64_t, f64) -+__ST2_FUNC (poly8x8x2_t, poly8_t, 8b, p8,) -+__ST2_FUNC (poly16x4x2_t, poly16_t, 4h, p16,) -+__ST2_FUNC (int8x8x2_t, int8_t, 8b, s8,) -+__ST2_FUNC (int16x4x2_t, int16_t, 4h, s16,) -+__ST2_FUNC (int32x2x2_t, int32_t, 2s, s32,) -+__ST2_64x1_FUNC (int64x1x2_t, int64_t, s64) -+__ST2_FUNC (uint8x8x2_t, uint8_t, 8b, u8,) -+__ST2_FUNC (uint16x4x2_t, uint16_t, 4h, u16,) -+__ST2_FUNC (uint32x2x2_t, uint32_t, 2s, u32,) -+__ST2_64x1_FUNC (uint64x1x2_t, uint64_t, u64) -+__ST2_FUNC (float32x4x2_t, float32_t, 4s, f32, q) -+__ST2_FUNC (float64x2x2_t, float64_t, 2d, f64, q) -+__ST2_FUNC (poly8x16x2_t, poly8_t, 16b, p8, q) -+__ST2_FUNC (poly16x8x2_t, poly16_t, 8h, p16, q) -+__ST2_FUNC (int8x16x2_t, int8_t, 16b, s8, q) -+__ST2_FUNC (int16x8x2_t, int16_t, 8h, s16, q) -+__ST2_FUNC (int32x4x2_t, int32_t, 4s, s32, q) -+__ST2_FUNC (int64x2x2_t, int64_t, 2d, s64, q) -+__ST2_FUNC (uint8x16x2_t, uint8_t, 16b, u8, q) -+__ST2_FUNC (uint16x8x2_t, uint16_t, 8h, u16, q) -+__ST2_FUNC (uint32x4x2_t, uint32_t, 4s, u32, q) -+__ST2_FUNC (uint64x2x2_t, uint64_t, 2d, u64, q) -+ -+#define __ST2_LANE_FUNC(intype, ptrtype, regsuffix, \ -+ lnsuffix, funcsuffix, Q) \ -+ __extension__ static __inline void \ -+ __attribute__ ((__always_inline__)) \ -+ vst2 ## Q ## _lane_ ## funcsuffix (const ptrtype *ptr, \ -+ intype b, const int c) \ -+ { \ -+ __asm__ ("ld1 {v16." #regsuffix ", v17." #regsuffix "}, %1\n\t" \ -+ "st2 {v16." #lnsuffix ", v17." #lnsuffix "}[%2], %0\n\t" \ -+ : "=Q"(*(intype *) ptr) \ -+ : "Q"(b), "i"(c) \ -+ : "memory", "v16", "v17"); \ -+ } -+ -+__ST2_LANE_FUNC (int8x8x2_t, int8_t, 8b, b, s8,) -+__ST2_LANE_FUNC (float32x2x2_t, float32_t, 2s, s, f32,) -+__ST2_LANE_FUNC (float64x1x2_t, float64_t, 1d, d, f64,) -+__ST2_LANE_FUNC (poly8x8x2_t, poly8_t, 8b, b, p8,) -+__ST2_LANE_FUNC (poly16x4x2_t, poly16_t, 4h, h, p16,) -+__ST2_LANE_FUNC (int16x4x2_t, int16_t, 4h, h, s16,) -+__ST2_LANE_FUNC (int32x2x2_t, int32_t, 2s, s, s32,) -+__ST2_LANE_FUNC (int64x1x2_t, int64_t, 1d, d, s64,) -+__ST2_LANE_FUNC (uint8x8x2_t, uint8_t, 8b, b, u8,) -+__ST2_LANE_FUNC (uint16x4x2_t, uint16_t, 4h, h, u16,) -+__ST2_LANE_FUNC (uint32x2x2_t, uint32_t, 2s, s, u32,) -+__ST2_LANE_FUNC (uint64x1x2_t, uint64_t, 1d, d, u64,) -+__ST2_LANE_FUNC (float32x4x2_t, float32_t, 4s, s, f32, q) -+__ST2_LANE_FUNC (float64x2x2_t, float64_t, 2d, d, f64, q) -+__ST2_LANE_FUNC (poly8x16x2_t, poly8_t, 16b, b, p8, q) -+__ST2_LANE_FUNC (poly16x8x2_t, poly16_t, 8h, h, p16, q) -+__ST2_LANE_FUNC (int8x16x2_t, int8_t, 16b, b, s8, q) -+__ST2_LANE_FUNC (int16x8x2_t, int16_t, 8h, h, s16, q) -+__ST2_LANE_FUNC (int32x4x2_t, int32_t, 4s, s, s32, q) -+__ST2_LANE_FUNC (int64x2x2_t, int64_t, 2d, d, s64, q) -+__ST2_LANE_FUNC (uint8x16x2_t, uint8_t, 16b, b, u8, q) -+__ST2_LANE_FUNC (uint16x8x2_t, uint16_t, 8h, h, u16, q) -+__ST2_LANE_FUNC (uint32x4x2_t, uint32_t, 4s, s, u32, q) -+__ST2_LANE_FUNC (uint64x2x2_t, uint64_t, 2d, d, u64, q) -+ -+#define __ST3_FUNC(intype, ptrtype, regsuffix, funcsuffix, Q) \ -+ __extension__ static __inline void \ -+ __attribute__ ((__always_inline__)) \ -+ vst3 ## Q ## _ ## funcsuffix (ptrtype *ptr, intype b) \ -+ { \ -+ __asm__ ("ld1 {v16." #regsuffix " - v18." #regsuffix "}, %1\n\t" \ -+ "st3 {v16." #regsuffix " - v18." #regsuffix "}, %0\n\t" \ -+ :"=Q"(*(intype *)ptr) \ -+ :"Q"(b) \ -+ :"v16", "v17", "v18", "memory"); \ -+ } -+#define __ST3_64x1_FUNC(intype, ptrtype, funcsuffix) \ -+ __extension__ static __inline void \ -+ __attribute__ ((__always_inline__)) \ -+ vst3_ ## funcsuffix (ptrtype *ptr, intype b) \ -+ { \ -+ __asm__ ("ld1 {v16.1d - v18.1d}, %1\n\t" \ -+ "st1 {v16.1d - v18.1d}, %0\n\t" \ -+ :"=Q"(*(intype *)ptr) \ -+ :"Q"(b) \ -+ :"v16", "v17", "v18", "memory"); \ -+ } -+ -+__ST3_FUNC (float32x2x3_t, float32_t, 2s, f32,) -+__ST3_64x1_FUNC (float64x1x3_t, float64_t, f64) -+__ST3_FUNC (poly8x8x3_t, poly8_t, 8b, p8,) -+__ST3_FUNC (poly16x4x3_t, poly16_t, 4h, p16,) -+__ST3_FUNC (int8x8x3_t, int8_t, 8b, s8,) -+__ST3_FUNC (int16x4x3_t, int16_t, 4h, s16,) -+__ST3_FUNC (int32x2x3_t, int32_t, 2s, s32,) -+__ST3_64x1_FUNC (int64x1x3_t, int64_t, s64) -+__ST3_FUNC (uint8x8x3_t, uint8_t, 8b, u8,) -+__ST3_FUNC (uint16x4x3_t, uint16_t, 4h, u16,) -+__ST3_FUNC (uint32x2x3_t, uint32_t, 2s, u32,) -+__ST3_64x1_FUNC (uint64x1x3_t, uint64_t, u64) -+__ST3_FUNC (float32x4x3_t, float32_t, 4s, f32, q) -+__ST3_FUNC (float64x2x3_t, float64_t, 2d, f64, q) -+__ST3_FUNC (poly8x16x3_t, poly8_t, 16b, p8, q) -+__ST3_FUNC (poly16x8x3_t, poly16_t, 8h, p16, q) -+__ST3_FUNC (int8x16x3_t, int8_t, 16b, s8, q) -+__ST3_FUNC (int16x8x3_t, int16_t, 8h, s16, q) -+__ST3_FUNC (int32x4x3_t, int32_t, 4s, s32, q) -+__ST3_FUNC (int64x2x3_t, int64_t, 2d, s64, q) -+__ST3_FUNC (uint8x16x3_t, uint8_t, 16b, u8, q) -+__ST3_FUNC (uint16x8x3_t, uint16_t, 8h, u16, q) -+__ST3_FUNC (uint32x4x3_t, uint32_t, 4s, u32, q) -+__ST3_FUNC (uint64x2x3_t, uint64_t, 2d, u64, q) -+ -+#define __ST3_LANE_FUNC(intype, ptrtype, regsuffix, \ -+ lnsuffix, funcsuffix, Q) \ -+ __extension__ static __inline void \ -+ __attribute__ ((__always_inline__)) \ -+ vst3 ## Q ## _lane_ ## funcsuffix (const ptrtype *ptr, \ -+ intype b, const int c) \ -+ { \ -+ __asm__ ("ld1 {v16." #regsuffix " - v18." #regsuffix "}, %1\n\t" \ -+ "st3 {v16." #lnsuffix " - v18." #lnsuffix "}[%2], %0\n\t" \ -+ : "=Q"(*(intype *) ptr) \ -+ : "Q"(b), "i"(c) \ -+ : "memory", "v16", "v17", "v18"); \ -+ } -+ -+__ST3_LANE_FUNC (int8x8x3_t, int8_t, 8b, b, s8,) -+__ST3_LANE_FUNC (float32x2x3_t, float32_t, 2s, s, f32,) -+__ST3_LANE_FUNC (float64x1x3_t, float64_t, 1d, d, f64,) -+__ST3_LANE_FUNC (poly8x8x3_t, poly8_t, 8b, b, p8,) -+__ST3_LANE_FUNC (poly16x4x3_t, poly16_t, 4h, h, p16,) -+__ST3_LANE_FUNC (int16x4x3_t, int16_t, 4h, h, s16,) -+__ST3_LANE_FUNC (int32x2x3_t, int32_t, 2s, s, s32,) -+__ST3_LANE_FUNC (int64x1x3_t, int64_t, 1d, d, s64,) -+__ST3_LANE_FUNC (uint8x8x3_t, uint8_t, 8b, b, u8,) -+__ST3_LANE_FUNC (uint16x4x3_t, uint16_t, 4h, h, u16,) -+__ST3_LANE_FUNC (uint32x2x3_t, uint32_t, 2s, s, u32,) -+__ST3_LANE_FUNC (uint64x1x3_t, uint64_t, 1d, d, u64,) -+__ST3_LANE_FUNC (float32x4x3_t, float32_t, 4s, s, f32, q) -+__ST3_LANE_FUNC (float64x2x3_t, float64_t, 2d, d, f64, q) -+__ST3_LANE_FUNC (poly8x16x3_t, poly8_t, 16b, b, p8, q) -+__ST3_LANE_FUNC (poly16x8x3_t, poly16_t, 8h, h, p16, q) -+__ST3_LANE_FUNC (int8x16x3_t, int8_t, 16b, b, s8, q) -+__ST3_LANE_FUNC (int16x8x3_t, int16_t, 8h, h, s16, q) -+__ST3_LANE_FUNC (int32x4x3_t, int32_t, 4s, s, s32, q) -+__ST3_LANE_FUNC (int64x2x3_t, int64_t, 2d, d, s64, q) -+__ST3_LANE_FUNC (uint8x16x3_t, uint8_t, 16b, b, u8, q) -+__ST3_LANE_FUNC (uint16x8x3_t, uint16_t, 8h, h, u16, q) -+__ST3_LANE_FUNC (uint32x4x3_t, uint32_t, 4s, s, u32, q) -+__ST3_LANE_FUNC (uint64x2x3_t, uint64_t, 2d, d, u64, q) -+ -+#define __ST4_FUNC(intype, ptrtype, regsuffix, funcsuffix, Q) \ -+ __extension__ static __inline void \ -+ __attribute__ ((__always_inline__)) \ -+ vst4 ## Q ## _ ## funcsuffix (ptrtype *ptr, intype b) \ -+ { \ -+ __asm__ ("ld1 {v16." #regsuffix " - v19." #regsuffix "}, %1\n\t" \ -+ "st4 {v16." #regsuffix " - v19." #regsuffix "}, %0\n\t" \ -+ :"=Q"(*(intype *)ptr) \ -+ :"Q"(b) \ -+ :"v16", "v17", "v18", "v19", "memory"); \ -+ } -+#define __ST4_64x1_FUNC(intype, ptrtype, funcsuffix) \ -+ __extension__ static __inline void \ -+ __attribute__ ((__always_inline__)) \ -+ vst4_ ## funcsuffix (ptrtype *ptr, intype b) \ -+ { \ -+ __asm__ ("ld1 {v16.1d - v19.1d}, %1\n\t" \ -+ "st1 {v16.1d - v19.1d}, %0\n\t" \ -+ :"=Q"(*(intype *)ptr) \ -+ :"Q"(b) \ -+ :"v16", "v17", "v18", "v19", "memory"); \ -+ } -+ -+__ST4_FUNC (float32x2x4_t, float32_t, 2s, f32,) -+__ST4_64x1_FUNC (float64x1x4_t, float64_t, f64) -+__ST4_FUNC (poly8x8x4_t, poly8_t, 8b, p8,) -+__ST4_FUNC (poly16x4x4_t, poly16_t, 4h, p16,) -+__ST4_FUNC (int8x8x4_t, int8_t, 8b, s8,) -+__ST4_FUNC (int16x4x4_t, int16_t, 4h, s16,) -+__ST4_FUNC (int32x2x4_t, int32_t, 2s, s32,) -+__ST4_64x1_FUNC (int64x1x4_t, int64_t, s64) -+__ST4_FUNC (uint8x8x4_t, uint8_t, 8b, u8,) -+__ST4_FUNC (uint16x4x4_t, uint16_t, 4h, u16,) -+__ST4_FUNC (uint32x2x4_t, uint32_t, 2s, u32,) -+__ST4_64x1_FUNC (uint64x1x4_t, uint64_t, u64) -+__ST4_FUNC (float32x4x4_t, float32_t, 4s, f32, q) -+__ST4_FUNC (float64x2x4_t, float64_t, 2d, f64, q) -+__ST4_FUNC (poly8x16x4_t, poly8_t, 16b, p8, q) -+__ST4_FUNC (poly16x8x4_t, poly16_t, 8h, p16, q) -+__ST4_FUNC (int8x16x4_t, int8_t, 16b, s8, q) -+__ST4_FUNC (int16x8x4_t, int16_t, 8h, s16, q) -+__ST4_FUNC (int32x4x4_t, int32_t, 4s, s32, q) -+__ST4_FUNC (int64x2x4_t, int64_t, 2d, s64, q) -+__ST4_FUNC (uint8x16x4_t, uint8_t, 16b, u8, q) -+__ST4_FUNC (uint16x8x4_t, uint16_t, 8h, u16, q) -+__ST4_FUNC (uint32x4x4_t, uint32_t, 4s, u32, q) -+__ST4_FUNC (uint64x2x4_t, uint64_t, 2d, u64, q) -+ -+#define __ST4_LANE_FUNC(intype, ptrtype, regsuffix, \ -+ lnsuffix, funcsuffix, Q) \ -+ __extension__ static __inline void \ -+ __attribute__ ((__always_inline__)) \ -+ vst4 ## Q ## _lane_ ## funcsuffix (const ptrtype *ptr, \ -+ intype b, const int c) \ -+ { \ -+ __asm__ ("ld1 {v16." #regsuffix " - v19." #regsuffix "}, %1\n\t" \ -+ "st4 {v16." #lnsuffix " - v19." #lnsuffix "}[%2], %0\n\t" \ -+ : "=Q"(*(intype *) ptr) \ -+ : "Q"(b), "i"(c) \ -+ : "memory", "v16", "v17", "v18", "v19"); \ -+ } -+ -+__ST4_LANE_FUNC (int8x8x4_t, int8_t, 8b, b, s8,) -+__ST4_LANE_FUNC (float32x2x4_t, float32_t, 2s, s, f32,) -+__ST4_LANE_FUNC (float64x1x4_t, float64_t, 1d, d, f64,) -+__ST4_LANE_FUNC (poly8x8x4_t, poly8_t, 8b, b, p8,) -+__ST4_LANE_FUNC (poly16x4x4_t, poly16_t, 4h, h, p16,) -+__ST4_LANE_FUNC (int16x4x4_t, int16_t, 4h, h, s16,) -+__ST4_LANE_FUNC (int32x2x4_t, int32_t, 2s, s, s32,) -+__ST4_LANE_FUNC (int64x1x4_t, int64_t, 1d, d, s64,) -+__ST4_LANE_FUNC (uint8x8x4_t, uint8_t, 8b, b, u8,) -+__ST4_LANE_FUNC (uint16x4x4_t, uint16_t, 4h, h, u16,) -+__ST4_LANE_FUNC (uint32x2x4_t, uint32_t, 2s, s, u32,) -+__ST4_LANE_FUNC (uint64x1x4_t, uint64_t, 1d, d, u64,) -+__ST4_LANE_FUNC (float32x4x4_t, float32_t, 4s, s, f32, q) -+__ST4_LANE_FUNC (float64x2x4_t, float64_t, 2d, d, f64, q) -+__ST4_LANE_FUNC (poly8x16x4_t, poly8_t, 16b, b, p8, q) -+__ST4_LANE_FUNC (poly16x8x4_t, poly16_t, 8h, h, p16, q) -+__ST4_LANE_FUNC (int8x16x4_t, int8_t, 16b, b, s8, q) -+__ST4_LANE_FUNC (int16x8x4_t, int16_t, 8h, h, s16, q) -+__ST4_LANE_FUNC (int32x4x4_t, int32_t, 4s, s, s32, q) -+__ST4_LANE_FUNC (int64x2x4_t, int64_t, 2d, d, s64, q) -+__ST4_LANE_FUNC (uint8x16x4_t, uint8_t, 16b, b, u8, q) -+__ST4_LANE_FUNC (uint16x8x4_t, uint16_t, 8h, h, u16, q) -+__ST4_LANE_FUNC (uint32x4x4_t, uint32_t, 4s, s, u32, q) -+__ST4_LANE_FUNC (uint64x2x4_t, uint64_t, 2d, d, u64, q) -+ -+__extension__ static __inline int64_t __attribute__ ((__always_inline__)) -+vaddlv_s32 (int32x2_t a) -+{ -+ int64_t result; -+ __asm__ ("saddlp %0.1d, %1.2s" : "=w"(result) : "w"(a) : ); -+ return result; -+} -+ -+__extension__ static __inline uint64_t __attribute__ ((__always_inline__)) -+vaddlv_u32 (uint32x2_t a) -+{ -+ uint64_t result; -+ __asm__ ("uaddlp %0.1d, %1.2s" : "=w"(result) : "w"(a) : ); -+ return result; -+} -+ -+__extension__ static __inline int32_t __attribute__ ((__always_inline__)) -+vaddv_s32 (int32x2_t a) -+{ -+ int32_t result; -+ __asm__ ("addp %0.2s, %1.2s, %1.2s" : "=w"(result) : "w"(a) : ); -+ return result; -+} -+ -+__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) -+vaddv_u32 (uint32x2_t a) -+{ -+ uint32_t result; -+ __asm__ ("addp %0.2s, %1.2s, %1.2s" : "=w"(result) : "w"(a) : ); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vmaxnmv_f32 (float32x2_t a) -+{ -+ float32_t result; -+ __asm__ ("fmaxnmp %0.2s, %1.2s, %1.2s" : "=w"(result) : "w"(a) : ); -+ return result; -+} -+ -+__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -+vminnmv_f32 (float32x2_t a) -+{ -+ float32_t result; -+ __asm__ ("fminnmp %0.2s, %1.2s, %1.2s" : "=w"(result) : "w"(a) : ); -+ return result; -+} -+ -+__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -+vmaxnmvq_f64 (float64x2_t a) -+{ -+ float64_t result; -+ __asm__ ("fmaxnmp %0.2d, %1.2d, %1.2d" : "=w"(result) : "w"(a) : ); -+ return result; -+} -+ -+__extension__ static __inline int32_t __attribute__ ((__always_inline__)) -+vmaxv_s32 (int32x2_t a) -+{ -+ int32_t result; -+ __asm__ ("smaxp %0.2s, %1.2s, %1.2s" : "=w"(result) : "w"(a) : ); -+ return result; -+} -+ -+__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) -+vmaxv_u32 (uint32x2_t a) -+{ -+ uint32_t result; -+ __asm__ ("umaxp %0.2s, %1.2s, %1.2s" : "=w"(result) : "w"(a) : ); -+ return result; -+} -+ -+__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -+vminnmvq_f64 (float64x2_t a) -+{ -+ float64_t result; -+ __asm__ ("fminnmp %0.2d, %1.2d, %1.2d" : "=w"(result) : "w"(a) : ); -+ return result; -+} -+ -+__extension__ static __inline int32_t __attribute__ ((__always_inline__)) -+vminv_s32 (int32x2_t a) -+{ -+ int32_t result; -+ __asm__ ("sminp %0.2s, %1.2s, %1.2s" : "=w"(result) : "w"(a) : ); -+ return result; -+} -+ -+__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) -+vminv_u32 (uint32x2_t a) -+{ -+ uint32_t result; -+ __asm__ ("uminp %0.2s, %1.2s, %1.2s" : "=w"(result) : "w"(a) : ); -+ return result; -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vpaddd_s64 (int64x2_t __a) -+{ -+ return __builtin_aarch64_addpdi (__a); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vqdmulh_laneq_s16 (int16x4_t __a, int16x8_t __b, const int __c) -+{ -+ return __builtin_aarch64_sqdmulh_lanev4hi (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vqdmulh_laneq_s32 (int32x2_t __a, int32x4_t __b, const int __c) -+{ -+ return __builtin_aarch64_sqdmulh_lanev2si (__a, __b, __c); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vqdmulhq_laneq_s16 (int16x8_t __a, int16x8_t __b, const int __c) -+{ -+ return __builtin_aarch64_sqdmulh_lanev8hi (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqdmulhq_laneq_s32 (int32x4_t __a, int32x4_t __b, const int __c) -+{ -+ return __builtin_aarch64_sqdmulh_lanev4si (__a, __b, __c); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vqrdmulh_laneq_s16 (int16x4_t __a, int16x8_t __b, const int __c) -+{ -+ return __builtin_aarch64_sqrdmulh_lanev4hi (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vqrdmulh_laneq_s32 (int32x2_t __a, int32x4_t __b, const int __c) -+{ -+ return __builtin_aarch64_sqrdmulh_lanev2si (__a, __b, __c); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vqrdmulhq_laneq_s16 (int16x8_t __a, int16x8_t __b, const int __c) -+{ -+ return __builtin_aarch64_sqrdmulh_lanev8hi (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqrdmulhq_laneq_s32 (int32x4_t __a, int32x4_t __b, const int __c) -+{ -+ return __builtin_aarch64_sqrdmulh_lanev4si (__a, __b, __c); -+} -+ -+/* Table intrinsics. */ -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vqtbl1_p8 (poly8x16_t a, uint8x8_t b) -+{ -+ poly8x8_t result; -+ __asm__ ("tbl %0.8b, {%1.16b}, %2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vqtbl1_s8 (int8x16_t a, int8x8_t b) -+{ -+ int8x8_t result; -+ __asm__ ("tbl %0.8b, {%1.16b}, %2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vqtbl1_u8 (uint8x16_t a, uint8x8_t b) -+{ -+ uint8x8_t result; -+ __asm__ ("tbl %0.8b, {%1.16b}, %2.8b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vqtbl1q_p8 (poly8x16_t a, uint8x16_t b) -+{ -+ poly8x16_t result; -+ __asm__ ("tbl %0.16b, {%1.16b}, %2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vqtbl1q_s8 (int8x16_t a, int8x16_t b) -+{ -+ int8x16_t result; -+ __asm__ ("tbl %0.16b, {%1.16b}, %2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vqtbl1q_u8 (uint8x16_t a, uint8x16_t b) -+{ -+ uint8x16_t result; -+ __asm__ ("tbl %0.16b, {%1.16b}, %2.16b" -+ : "=w"(result) -+ : "w"(a), "w"(b) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vqtbl2_s8 (int8x16x2_t tab, int8x8_t idx) -+{ -+ int8x8_t result; -+ __asm__ ("ld1 {v16.16b, v17.16b}, %1\n\t" -+ "tbl %0.8b, {v16.16b, v17.16b}, %2.8b\n\t" -+ :"=w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17"); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vqtbl2_u8 (uint8x16x2_t tab, uint8x8_t idx) -+{ -+ uint8x8_t result; -+ __asm__ ("ld1 {v16.16b, v17.16b}, %1\n\t" -+ "tbl %0.8b, {v16.16b, v17.16b}, %2.8b\n\t" -+ :"=w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17"); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vqtbl2_p8 (poly8x16x2_t tab, uint8x8_t idx) -+{ -+ poly8x8_t result; -+ __asm__ ("ld1 {v16.16b, v17.16b}, %1\n\t" -+ "tbl %0.8b, {v16.16b, v17.16b}, %2.8b\n\t" -+ :"=w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17"); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vqtbl2q_s8 (int8x16x2_t tab, int8x16_t idx) -+{ -+ int8x16_t result; -+ __asm__ ("ld1 {v16.16b, v17.16b}, %1\n\t" -+ "tbl %0.16b, {v16.16b, v17.16b}, %2.16b\n\t" -+ :"=w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17"); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vqtbl2q_u8 (uint8x16x2_t tab, uint8x16_t idx) -+{ -+ uint8x16_t result; -+ __asm__ ("ld1 {v16.16b, v17.16b}, %1\n\t" -+ "tbl %0.16b, {v16.16b, v17.16b}, %2.16b\n\t" -+ :"=w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17"); -+ return result; -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vqtbl2q_p8 (poly8x16x2_t tab, uint8x16_t idx) -+{ -+ poly8x16_t result; -+ __asm__ ("ld1 {v16.16b, v17.16b}, %1\n\t" -+ "tbl %0.16b, {v16.16b, v17.16b}, %2.16b\n\t" -+ :"=w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17"); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vqtbl3_s8 (int8x16x3_t tab, int8x8_t idx) -+{ -+ int8x8_t result; -+ __asm__ ("ld1 {v16.16b - v18.16b}, %1\n\t" -+ "tbl %0.8b, {v16.16b - v18.16b}, %2.8b\n\t" -+ :"=w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17", "v18"); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vqtbl3_u8 (uint8x16x3_t tab, uint8x8_t idx) -+{ -+ uint8x8_t result; -+ __asm__ ("ld1 {v16.16b - v18.16b}, %1\n\t" -+ "tbl %0.8b, {v16.16b - v18.16b}, %2.8b\n\t" -+ :"=w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17", "v18"); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vqtbl3_p8 (poly8x16x3_t tab, uint8x8_t idx) -+{ -+ poly8x8_t result; -+ __asm__ ("ld1 {v16.16b - v18.16b}, %1\n\t" -+ "tbl %0.8b, {v16.16b - v18.16b}, %2.8b\n\t" -+ :"=w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17", "v18"); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vqtbl3q_s8 (int8x16x3_t tab, int8x16_t idx) -+{ -+ int8x16_t result; -+ __asm__ ("ld1 {v16.16b - v18.16b}, %1\n\t" -+ "tbl %0.16b, {v16.16b - v18.16b}, %2.16b\n\t" -+ :"=w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17", "v18"); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vqtbl3q_u8 (uint8x16x3_t tab, uint8x16_t idx) -+{ -+ uint8x16_t result; -+ __asm__ ("ld1 {v16.16b - v18.16b}, %1\n\t" -+ "tbl %0.16b, {v16.16b - v18.16b}, %2.16b\n\t" -+ :"=w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17", "v18"); -+ return result; -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vqtbl3q_p8 (poly8x16x3_t tab, uint8x16_t idx) -+{ -+ poly8x16_t result; -+ __asm__ ("ld1 {v16.16b - v18.16b}, %1\n\t" -+ "tbl %0.16b, {v16.16b - v18.16b}, %2.16b\n\t" -+ :"=w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17", "v18"); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vqtbl4_s8 (int8x16x4_t tab, int8x8_t idx) -+{ -+ int8x8_t result; -+ __asm__ ("ld1 {v16.16b - v19.16b}, %1\n\t" -+ "tbl %0.8b, {v16.16b - v19.16b}, %2.8b\n\t" -+ :"=w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17", "v18", "v19"); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vqtbl4_u8 (uint8x16x4_t tab, uint8x8_t idx) -+{ -+ uint8x8_t result; -+ __asm__ ("ld1 {v16.16b - v19.16b}, %1\n\t" -+ "tbl %0.8b, {v16.16b - v19.16b}, %2.8b\n\t" -+ :"=w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17", "v18", "v19"); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vqtbl4_p8 (poly8x16x4_t tab, uint8x8_t idx) -+{ -+ poly8x8_t result; -+ __asm__ ("ld1 {v16.16b - v19.16b}, %1\n\t" -+ "tbl %0.8b, {v16.16b - v19.16b}, %2.8b\n\t" -+ :"=w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17", "v18", "v19"); -+ return result; -+} -+ -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vqtbl4q_s8 (int8x16x4_t tab, int8x16_t idx) -+{ -+ int8x16_t result; -+ __asm__ ("ld1 {v16.16b - v19.16b}, %1\n\t" -+ "tbl %0.16b, {v16.16b - v19.16b}, %2.16b\n\t" -+ :"=w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17", "v18", "v19"); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vqtbl4q_u8 (uint8x16x4_t tab, uint8x16_t idx) -+{ -+ uint8x16_t result; -+ __asm__ ("ld1 {v16.16b - v19.16b}, %1\n\t" -+ "tbl %0.16b, {v16.16b - v19.16b}, %2.16b\n\t" -+ :"=w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17", "v18", "v19"); -+ return result; -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vqtbl4q_p8 (poly8x16x4_t tab, uint8x16_t idx) -+{ -+ poly8x16_t result; -+ __asm__ ("ld1 {v16.16b - v19.16b}, %1\n\t" -+ "tbl %0.16b, {v16.16b - v19.16b}, %2.16b\n\t" -+ :"=w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17", "v18", "v19"); -+ return result; -+} -+ -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vqtbx1_s8 (int8x8_t r, int8x16_t tab, int8x8_t idx) -+{ -+ int8x8_t result = r; -+ __asm__ ("tbx %0.8b,{%1.16b},%2.8b" -+ : "+w"(result) -+ : "w"(tab), "w"(idx) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vqtbx1_u8 (uint8x8_t r, uint8x16_t tab, uint8x8_t idx) -+{ -+ uint8x8_t result = r; -+ __asm__ ("tbx %0.8b,{%1.16b},%2.8b" -+ : "+w"(result) -+ : "w"(tab), "w"(idx) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vqtbx1_p8 (poly8x8_t r, poly8x16_t tab, uint8x8_t idx) -+{ -+ poly8x8_t result = r; -+ __asm__ ("tbx %0.8b,{%1.16b},%2.8b" -+ : "+w"(result) -+ : "w"(tab), "w"(idx) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vqtbx1q_s8 (int8x16_t r, int8x16_t tab, int8x16_t idx) -+{ -+ int8x16_t result = r; -+ __asm__ ("tbx %0.16b,{%1.16b},%2.16b" -+ : "+w"(result) -+ : "w"(tab), "w"(idx) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vqtbx1q_u8 (uint8x16_t r, uint8x16_t tab, uint8x16_t idx) -+{ -+ uint8x16_t result = r; -+ __asm__ ("tbx %0.16b,{%1.16b},%2.16b" -+ : "+w"(result) -+ : "w"(tab), "w"(idx) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vqtbx1q_p8 (poly8x16_t r, poly8x16_t tab, uint8x16_t idx) -+{ -+ poly8x16_t result = r; -+ __asm__ ("tbx %0.16b,{%1.16b},%2.16b" -+ : "+w"(result) -+ : "w"(tab), "w"(idx) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vqtbx2_s8 (int8x8_t r, int8x16x2_t tab, int8x8_t idx) -+{ -+ int8x8_t result = r; -+ __asm__ ("ld1 {v16.16b, v17.16b}, %1\n\t" -+ "tbx %0.8b, {v16.16b, v17.16b}, %2.8b\n\t" -+ :"+w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17"); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vqtbx2_u8 (uint8x8_t r, uint8x16x2_t tab, uint8x8_t idx) -+{ -+ uint8x8_t result = r; -+ __asm__ ("ld1 {v16.16b, v17.16b}, %1\n\t" -+ "tbx %0.8b, {v16.16b, v17.16b}, %2.8b\n\t" -+ :"+w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17"); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vqtbx2_p8 (poly8x8_t r, poly8x16x2_t tab, uint8x8_t idx) -+{ -+ poly8x8_t result = r; -+ __asm__ ("ld1 {v16.16b, v17.16b}, %1\n\t" -+ "tbx %0.8b, {v16.16b, v17.16b}, %2.8b\n\t" -+ :"+w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17"); -+ return result; -+} -+ -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vqtbx2q_s8 (int8x16_t r, int8x16x2_t tab, int8x16_t idx) -+{ -+ int8x16_t result = r; -+ __asm__ ("ld1 {v16.16b, v17.16b}, %1\n\t" -+ "tbx %0.16b, {v16.16b, v17.16b}, %2.16b\n\t" -+ :"+w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17"); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vqtbx2q_u8 (uint8x16_t r, uint8x16x2_t tab, uint8x16_t idx) -+{ -+ uint8x16_t result = r; -+ __asm__ ("ld1 {v16.16b, v17.16b}, %1\n\t" -+ "tbx %0.16b, {v16.16b, v17.16b}, %2.16b\n\t" -+ :"+w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17"); -+ return result; -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vqtbx2q_p8 (poly8x16_t r, poly8x16x2_t tab, uint8x16_t idx) -+{ -+ poly8x16_t result = r; -+ __asm__ ("ld1 {v16.16b, v17.16b}, %1\n\t" -+ "tbx %0.16b, {v16.16b, v17.16b}, %2.16b\n\t" -+ :"+w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17"); -+ return result; -+} -+ -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vqtbx3_s8 (int8x8_t r, int8x16x3_t tab, int8x8_t idx) -+{ -+ int8x8_t result = r; -+ __asm__ ("ld1 {v16.16b - v18.16b}, %1\n\t" -+ "tbx %0.8b, {v16.16b - v18.16b}, %2.8b\n\t" -+ :"+w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17", "v18"); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vqtbx3_u8 (uint8x8_t r, uint8x16x3_t tab, uint8x8_t idx) -+{ -+ uint8x8_t result = r; -+ __asm__ ("ld1 {v16.16b - v18.16b}, %1\n\t" -+ "tbx %0.8b, {v16.16b - v18.16b}, %2.8b\n\t" -+ :"+w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17", "v18"); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vqtbx3_p8 (poly8x8_t r, poly8x16x3_t tab, uint8x8_t idx) -+{ -+ poly8x8_t result = r; -+ __asm__ ("ld1 {v16.16b - v18.16b}, %1\n\t" -+ "tbx %0.8b, {v16.16b - v18.16b}, %2.8b\n\t" -+ :"+w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17", "v18"); -+ return result; -+} -+ -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vqtbx3q_s8 (int8x16_t r, int8x16x3_t tab, int8x16_t idx) -+{ -+ int8x16_t result = r; -+ __asm__ ("ld1 {v16.16b - v18.16b}, %1\n\t" -+ "tbx %0.16b, {v16.16b - v18.16b}, %2.16b\n\t" -+ :"+w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17", "v18"); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vqtbx3q_u8 (uint8x16_t r, uint8x16x3_t tab, uint8x16_t idx) -+{ -+ uint8x16_t result = r; -+ __asm__ ("ld1 {v16.16b - v18.16b}, %1\n\t" -+ "tbx %0.16b, {v16.16b - v18.16b}, %2.16b\n\t" -+ :"+w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17", "v18"); -+ return result; -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vqtbx3q_p8 (poly8x16_t r, poly8x16x3_t tab, uint8x16_t idx) -+{ -+ poly8x16_t result = r; -+ __asm__ ("ld1 {v16.16b - v18.16b}, %1\n\t" -+ "tbx %0.16b, {v16.16b - v18.16b}, %2.16b\n\t" -+ :"+w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17", "v18"); -+ return result; -+} -+ -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vqtbx4_s8 (int8x8_t r, int8x16x4_t tab, int8x8_t idx) -+{ -+ int8x8_t result = r; -+ __asm__ ("ld1 {v16.16b - v19.16b}, %1\n\t" -+ "tbx %0.8b, {v16.16b - v19.16b}, %2.8b\n\t" -+ :"+w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17", "v18", "v19"); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vqtbx4_u8 (uint8x8_t r, uint8x16x4_t tab, uint8x8_t idx) -+{ -+ uint8x8_t result = r; -+ __asm__ ("ld1 {v16.16b - v19.16b}, %1\n\t" -+ "tbx %0.8b, {v16.16b - v19.16b}, %2.8b\n\t" -+ :"+w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17", "v18", "v19"); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vqtbx4_p8 (poly8x8_t r, poly8x16x4_t tab, uint8x8_t idx) -+{ -+ poly8x8_t result = r; -+ __asm__ ("ld1 {v16.16b - v19.16b}, %1\n\t" -+ "tbx %0.8b, {v16.16b - v19.16b}, %2.8b\n\t" -+ :"+w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17", "v18", "v19"); -+ return result; -+} -+ -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vqtbx4q_s8 (int8x16_t r, int8x16x4_t tab, int8x16_t idx) -+{ -+ int8x16_t result = r; -+ __asm__ ("ld1 {v16.16b - v19.16b}, %1\n\t" -+ "tbx %0.16b, {v16.16b - v19.16b}, %2.16b\n\t" -+ :"+w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17", "v18", "v19"); -+ return result; -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vqtbx4q_u8 (uint8x16_t r, uint8x16x4_t tab, uint8x16_t idx) -+{ -+ uint8x16_t result = r; -+ __asm__ ("ld1 {v16.16b - v19.16b}, %1\n\t" -+ "tbx %0.16b, {v16.16b - v19.16b}, %2.16b\n\t" -+ :"+w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17", "v18", "v19"); -+ return result; -+} -+ -+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -+vqtbx4q_p8 (poly8x16_t r, poly8x16x4_t tab, uint8x16_t idx) -+{ -+ poly8x16_t result = r; -+ __asm__ ("ld1 {v16.16b - v19.16b}, %1\n\t" -+ "tbx %0.16b, {v16.16b - v19.16b}, %2.16b\n\t" -+ :"+w"(result) -+ :"Q"(tab),"w"(idx) -+ :"memory", "v16", "v17", "v18", "v19"); -+ return result; -+} -+ -+/* V7 legacy table intrinsics. */ -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vtbl1_s8 (int8x8_t tab, int8x8_t idx) -+{ -+ int8x8_t result; -+ int8x16_t temp = vcombine_s8 (tab, vcreate_s8 (UINT64_C (0x0))); -+ __asm__ ("tbl %0.8b, {%1.16b}, %2.8b" -+ : "=w"(result) -+ : "w"(temp), "w"(idx) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vtbl1_u8 (uint8x8_t tab, uint8x8_t idx) -+{ -+ uint8x8_t result; -+ uint8x16_t temp = vcombine_u8 (tab, vcreate_u8 (UINT64_C (0x0))); -+ __asm__ ("tbl %0.8b, {%1.16b}, %2.8b" -+ : "=w"(result) -+ : "w"(temp), "w"(idx) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vtbl1_p8 (poly8x8_t tab, uint8x8_t idx) -+{ -+ poly8x8_t result; -+ poly8x16_t temp = vcombine_p8 (tab, vcreate_p8 (UINT64_C (0x0))); -+ __asm__ ("tbl %0.8b, {%1.16b}, %2.8b" -+ : "=w"(result) -+ : "w"(temp), "w"(idx) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vtbl2_s8 (int8x8x2_t tab, int8x8_t idx) -+{ -+ int8x8_t result; -+ int8x16_t temp = vcombine_s8 (tab.val[0], tab.val[1]); -+ __asm__ ("tbl %0.8b, {%1.16b}, %2.8b" -+ : "=w"(result) -+ : "w"(temp), "w"(idx) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vtbl2_u8 (uint8x8x2_t tab, uint8x8_t idx) -+{ -+ uint8x8_t result; -+ uint8x16_t temp = vcombine_u8 (tab.val[0], tab.val[1]); -+ __asm__ ("tbl %0.8b, {%1.16b}, %2.8b" -+ : "=w"(result) -+ : "w"(temp), "w"(idx) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vtbl2_p8 (poly8x8x2_t tab, uint8x8_t idx) -+{ -+ poly8x8_t result; -+ poly8x16_t temp = vcombine_p8 (tab.val[0], tab.val[1]); -+ __asm__ ("tbl %0.8b, {%1.16b}, %2.8b" -+ : "=w"(result) -+ : "w"(temp), "w"(idx) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vtbl3_s8 (int8x8x3_t tab, int8x8_t idx) -+{ -+ int8x8_t result; -+ int8x16x2_t temp; -+ temp.val[0] = vcombine_s8 (tab.val[0], tab.val[1]); -+ temp.val[1] = vcombine_s8 (tab.val[2], vcreate_s8 (UINT64_C (0x0))); -+ __asm__ ("ld1 {v16.16b - v17.16b }, %1\n\t" -+ "tbl %0.8b, {v16.16b - v17.16b}, %2.8b\n\t" -+ : "=w"(result) -+ : "Q"(temp), "w"(idx) -+ : "v16", "v17", "memory"); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vtbl3_u8 (uint8x8x3_t tab, uint8x8_t idx) -+{ -+ uint8x8_t result; -+ uint8x16x2_t temp; -+ temp.val[0] = vcombine_u8 (tab.val[0], tab.val[1]); -+ temp.val[1] = vcombine_u8 (tab.val[2], vcreate_u8 (UINT64_C (0x0))); -+ __asm__ ("ld1 {v16.16b - v17.16b }, %1\n\t" -+ "tbl %0.8b, {v16.16b - v17.16b}, %2.8b\n\t" -+ : "=w"(result) -+ : "Q"(temp), "w"(idx) -+ : "v16", "v17", "memory"); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vtbl3_p8 (poly8x8x3_t tab, uint8x8_t idx) -+{ -+ poly8x8_t result; -+ poly8x16x2_t temp; -+ temp.val[0] = vcombine_p8 (tab.val[0], tab.val[1]); -+ temp.val[1] = vcombine_p8 (tab.val[2], vcreate_p8 (UINT64_C (0x0))); -+ __asm__ ("ld1 {v16.16b - v17.16b }, %1\n\t" -+ "tbl %0.8b, {v16.16b - v17.16b}, %2.8b\n\t" -+ : "=w"(result) -+ : "Q"(temp), "w"(idx) -+ : "v16", "v17", "memory"); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vtbl4_s8 (int8x8x4_t tab, int8x8_t idx) -+{ -+ int8x8_t result; -+ int8x16x2_t temp; -+ temp.val[0] = vcombine_s8 (tab.val[0], tab.val[1]); -+ temp.val[1] = vcombine_s8 (tab.val[2], tab.val[3]); -+ __asm__ ("ld1 {v16.16b - v17.16b }, %1\n\t" -+ "tbl %0.8b, {v16.16b - v17.16b}, %2.8b\n\t" -+ : "=w"(result) -+ : "Q"(temp), "w"(idx) -+ : "v16", "v17", "memory"); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vtbl4_u8 (uint8x8x4_t tab, uint8x8_t idx) -+{ -+ uint8x8_t result; -+ uint8x16x2_t temp; -+ temp.val[0] = vcombine_u8 (tab.val[0], tab.val[1]); -+ temp.val[1] = vcombine_u8 (tab.val[2], tab.val[3]); -+ __asm__ ("ld1 {v16.16b - v17.16b }, %1\n\t" -+ "tbl %0.8b, {v16.16b - v17.16b}, %2.8b\n\t" -+ : "=w"(result) -+ : "Q"(temp), "w"(idx) -+ : "v16", "v17", "memory"); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vtbl4_p8 (poly8x8x4_t tab, uint8x8_t idx) -+{ -+ poly8x8_t result; -+ poly8x16x2_t temp; -+ temp.val[0] = vcombine_p8 (tab.val[0], tab.val[1]); -+ temp.val[1] = vcombine_p8 (tab.val[2], tab.val[3]); -+ __asm__ ("ld1 {v16.16b - v17.16b }, %1\n\t" -+ "tbl %0.8b, {v16.16b - v17.16b}, %2.8b\n\t" -+ : "=w"(result) -+ : "Q"(temp), "w"(idx) -+ : "v16", "v17", "memory"); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vtbx1_s8 (int8x8_t r, int8x8_t tab, int8x8_t idx) -+{ -+ int8x8_t result; -+ int8x8_t tmp1; -+ int8x16_t temp = vcombine_s8 (tab, vcreate_s8 (UINT64_C (0x0))); -+ __asm__ ("movi %0.8b, 8\n\t" -+ "cmhs %0.8b, %3.8b, %0.8b\n\t" -+ "tbl %1.8b, {%2.16b}, %3.8b\n\t" -+ "bsl %0.8b, %4.8b, %1.8b\n\t" -+ : "+w"(result), "=w"(tmp1) -+ : "w"(temp), "w"(idx), "w"(r) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vtbx1_u8 (uint8x8_t r, uint8x8_t tab, uint8x8_t idx) -+{ -+ uint8x8_t result; -+ uint8x8_t tmp1; -+ uint8x16_t temp = vcombine_u8 (tab, vcreate_u8 (UINT64_C (0x0))); -+ __asm__ ("movi %0.8b, 8\n\t" -+ "cmhs %0.8b, %3.8b, %0.8b\n\t" -+ "tbl %1.8b, {%2.16b}, %3.8b\n\t" -+ "bsl %0.8b, %4.8b, %1.8b\n\t" -+ : "+w"(result), "=w"(tmp1) -+ : "w"(temp), "w"(idx), "w"(r) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vtbx1_p8 (poly8x8_t r, poly8x8_t tab, uint8x8_t idx) -+{ -+ poly8x8_t result; -+ poly8x8_t tmp1; -+ poly8x16_t temp = vcombine_p8 (tab, vcreate_p8 (UINT64_C (0x0))); -+ __asm__ ("movi %0.8b, 8\n\t" -+ "cmhs %0.8b, %3.8b, %0.8b\n\t" -+ "tbl %1.8b, {%2.16b}, %3.8b\n\t" -+ "bsl %0.8b, %4.8b, %1.8b\n\t" -+ : "+w"(result), "=w"(tmp1) -+ : "w"(temp), "w"(idx), "w"(r) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vtbx2_s8 (int8x8_t r, int8x8x2_t tab, int8x8_t idx) -+{ -+ int8x8_t result = r; -+ int8x16_t temp = vcombine_s8 (tab.val[0], tab.val[1]); -+ __asm__ ("tbx %0.8b, {%1.16b}, %2.8b" -+ : "+w"(result) -+ : "w"(temp), "w"(idx) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vtbx2_u8 (uint8x8_t r, uint8x8x2_t tab, uint8x8_t idx) -+{ -+ uint8x8_t result = r; -+ uint8x16_t temp = vcombine_u8 (tab.val[0], tab.val[1]); -+ __asm__ ("tbx %0.8b, {%1.16b}, %2.8b" -+ : "+w"(result) -+ : "w"(temp), "w"(idx) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vtbx2_p8 (poly8x8_t r, poly8x8x2_t tab, uint8x8_t idx) -+{ -+ poly8x8_t result = r; -+ poly8x16_t temp = vcombine_p8 (tab.val[0], tab.val[1]); -+ __asm__ ("tbx %0.8b, {%1.16b}, %2.8b" -+ : "+w"(result) -+ : "w"(temp), "w"(idx) -+ : /* No clobbers */); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vtbx3_s8 (int8x8_t r, int8x8x3_t tab, int8x8_t idx) -+{ -+ int8x8_t result; -+ int8x8_t tmp1; -+ int8x16x2_t temp; -+ temp.val[0] = vcombine_s8 (tab.val[0], tab.val[1]); -+ temp.val[1] = vcombine_s8 (tab.val[2], vcreate_s8 (UINT64_C (0x0))); -+ __asm__ ("ld1 {v16.16b - v17.16b}, %2\n\t" -+ "movi %0.8b, 24\n\t" -+ "cmhs %0.8b, %3.8b, %0.8b\n\t" -+ "tbl %1.8b, {v16.16b - v17.16b}, %3.8b\n\t" -+ "bsl %0.8b, %4.8b, %1.8b\n\t" -+ : "+w"(result), "=w"(tmp1) -+ : "Q"(temp), "w"(idx), "w"(r) -+ : "v16", "v17", "memory"); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vtbx3_u8 (uint8x8_t r, uint8x8x3_t tab, uint8x8_t idx) -+{ -+ uint8x8_t result; -+ uint8x8_t tmp1; -+ uint8x16x2_t temp; -+ temp.val[0] = vcombine_u8 (tab.val[0], tab.val[1]); -+ temp.val[1] = vcombine_u8 (tab.val[2], vcreate_u8 (UINT64_C (0x0))); -+ __asm__ ("ld1 {v16.16b - v17.16b}, %2\n\t" -+ "movi %0.8b, 24\n\t" -+ "cmhs %0.8b, %3.8b, %0.8b\n\t" -+ "tbl %1.8b, {v16.16b - v17.16b}, %3.8b\n\t" -+ "bsl %0.8b, %4.8b, %1.8b\n\t" -+ : "+w"(result), "=w"(tmp1) -+ : "Q"(temp), "w"(idx), "w"(r) -+ : "v16", "v17", "memory"); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vtbx3_p8 (poly8x8_t r, poly8x8x3_t tab, uint8x8_t idx) -+{ -+ poly8x8_t result; -+ poly8x8_t tmp1; -+ poly8x16x2_t temp; -+ temp.val[0] = vcombine_p8 (tab.val[0], tab.val[1]); -+ temp.val[1] = vcombine_p8 (tab.val[2], vcreate_p8 (UINT64_C (0x0))); -+ __asm__ ("ld1 {v16.16b - v17.16b}, %2\n\t" -+ "movi %0.8b, 24\n\t" -+ "cmhs %0.8b, %3.8b, %0.8b\n\t" -+ "tbl %1.8b, {v16.16b - v17.16b}, %3.8b\n\t" -+ "bsl %0.8b, %4.8b, %1.8b\n\t" -+ : "+w"(result), "=w"(tmp1) -+ : "Q"(temp), "w"(idx), "w"(r) -+ : "v16", "v17", "memory"); -+ return result; -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vtbx4_s8 (int8x8_t r, int8x8x4_t tab, int8x8_t idx) -+{ -+ int8x8_t result = r; -+ int8x16x2_t temp; -+ temp.val[0] = vcombine_s8 (tab.val[0], tab.val[1]); -+ temp.val[1] = vcombine_s8 (tab.val[2], tab.val[3]); -+ __asm__ ("ld1 {v16.16b - v17.16b }, %1\n\t" -+ "tbx %0.8b, {v16.16b - v17.16b}, %2.8b\n\t" -+ : "+w"(result) -+ : "Q"(temp), "w"(idx) -+ : "v16", "v17", "memory"); -+ return result; -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vtbx4_u8 (uint8x8_t r, uint8x8x4_t tab, uint8x8_t idx) -+{ -+ uint8x8_t result = r; -+ uint8x16x2_t temp; -+ temp.val[0] = vcombine_u8 (tab.val[0], tab.val[1]); -+ temp.val[1] = vcombine_u8 (tab.val[2], tab.val[3]); -+ __asm__ ("ld1 {v16.16b - v17.16b }, %1\n\t" -+ "tbx %0.8b, {v16.16b - v17.16b}, %2.8b\n\t" -+ : "+w"(result) -+ : "Q"(temp), "w"(idx) -+ : "v16", "v17", "memory"); -+ return result; -+} -+ -+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -+vtbx4_p8 (poly8x8_t r, poly8x8x4_t tab, uint8x8_t idx) -+{ -+ poly8x8_t result = r; -+ poly8x16x2_t temp; -+ temp.val[0] = vcombine_p8 (tab.val[0], tab.val[1]); -+ temp.val[1] = vcombine_p8 (tab.val[2], tab.val[3]); -+ __asm__ ("ld1 {v16.16b - v17.16b }, %1\n\t" -+ "tbx %0.8b, {v16.16b - v17.16b}, %2.8b\n\t" -+ : "+w"(result) -+ : "Q"(temp), "w"(idx) -+ : "v16", "v17", "memory"); -+ return result; -+} -+ -+/* End of temporary inline asm. */ -+ -+/* Start of optimal implementations in approved order. */ -+ -+/* vadd */ -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vaddd_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return __a + __b; -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vaddd_u64 (uint64x1_t __a, uint64x1_t __b) -+{ -+ return __a + __b; -+} -+ -+/* vceq */ -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vceq_p8 (poly8x8_t __a, poly8x8_t __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_cmeqv8qi ((int8x8_t) __a, -+ (int8x8_t) __b); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vceq_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_cmeqv8qi (__a, __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vceq_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_cmeqv4hi (__a, __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vceq_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_cmeqv2si (__a, __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vceq_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_cmeqdi (__a, __b); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vceq_u8 (uint8x8_t __a, uint8x8_t __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_cmeqv8qi ((int8x8_t) __a, -+ (int8x8_t) __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vceq_u16 (uint16x4_t __a, uint16x4_t __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_cmeqv4hi ((int16x4_t) __a, -+ (int16x4_t) __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vceq_u32 (uint32x2_t __a, uint32x2_t __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_cmeqv2si ((int32x2_t) __a, -+ (int32x2_t) __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vceq_u64 (uint64x1_t __a, uint64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_cmeqdi ((int64x1_t) __a, -+ (int64x1_t) __b); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vceqq_p8 (poly8x16_t __a, poly8x16_t __b) -+{ -+ return (uint8x16_t) __builtin_aarch64_cmeqv16qi ((int8x16_t) __a, -+ (int8x16_t) __b); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vceqq_s8 (int8x16_t __a, int8x16_t __b) -+{ -+ return (uint8x16_t) __builtin_aarch64_cmeqv16qi (__a, __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vceqq_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_cmeqv8hi (__a, __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vceqq_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_cmeqv4si (__a, __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vceqq_s64 (int64x2_t __a, int64x2_t __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_cmeqv2di (__a, __b); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vceqq_u8 (uint8x16_t __a, uint8x16_t __b) -+{ -+ return (uint8x16_t) __builtin_aarch64_cmeqv16qi ((int8x16_t) __a, -+ (int8x16_t) __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vceqq_u16 (uint16x8_t __a, uint16x8_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_cmeqv8hi ((int16x8_t) __a, -+ (int16x8_t) __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vceqq_u32 (uint32x4_t __a, uint32x4_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_cmeqv4si ((int32x4_t) __a, -+ (int32x4_t) __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vceqq_u64 (uint64x2_t __a, uint64x2_t __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_cmeqv2di ((int64x2_t) __a, -+ (int64x2_t) __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vceqd_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_cmeqdi (__a, __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vceqd_u64 (uint64x1_t __a, uint64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_cmeqdi (__a, __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vceqzd_s64 (int64x1_t __a) -+{ -+ return (uint64x1_t) __builtin_aarch64_cmeqdi (__a, 0); -+} -+ -+/* vcge */ -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vcge_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_cmgev8qi (__a, __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vcge_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_cmgev4hi (__a, __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vcge_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_cmgev2si (__a, __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vcge_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_cmgedi (__a, __b); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vcge_u8 (uint8x8_t __a, uint8x8_t __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_cmhsv8qi ((int8x8_t) __a, -+ (int8x8_t) __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vcge_u16 (uint16x4_t __a, uint16x4_t __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_cmhsv4hi ((int16x4_t) __a, -+ (int16x4_t) __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vcge_u32 (uint32x2_t __a, uint32x2_t __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_cmhsv2si ((int32x2_t) __a, -+ (int32x2_t) __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vcge_u64 (uint64x1_t __a, uint64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_cmhsdi ((int64x1_t) __a, -+ (int64x1_t) __b); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vcgeq_s8 (int8x16_t __a, int8x16_t __b) -+{ -+ return (uint8x16_t) __builtin_aarch64_cmgev16qi (__a, __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vcgeq_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_cmgev8hi (__a, __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vcgeq_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_cmgev4si (__a, __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vcgeq_s64 (int64x2_t __a, int64x2_t __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_cmgev2di (__a, __b); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vcgeq_u8 (uint8x16_t __a, uint8x16_t __b) -+{ -+ return (uint8x16_t) __builtin_aarch64_cmhsv16qi ((int8x16_t) __a, -+ (int8x16_t) __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vcgeq_u16 (uint16x8_t __a, uint16x8_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_cmhsv8hi ((int16x8_t) __a, -+ (int16x8_t) __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vcgeq_u32 (uint32x4_t __a, uint32x4_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_cmhsv4si ((int32x4_t) __a, -+ (int32x4_t) __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vcgeq_u64 (uint64x2_t __a, uint64x2_t __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_cmhsv2di ((int64x2_t) __a, -+ (int64x2_t) __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vcged_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_cmgedi (__a, __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vcged_u64 (uint64x1_t __a, uint64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_cmhsdi ((int64x1_t) __a, -+ (int64x1_t) __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vcgezd_s64 (int64x1_t __a) -+{ -+ return (uint64x1_t) __builtin_aarch64_cmgedi (__a, 0); -+} -+ -+/* vcgt */ -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vcgt_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_cmgtv8qi (__a, __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vcgt_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_cmgtv4hi (__a, __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vcgt_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_cmgtv2si (__a, __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vcgt_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_cmgtdi (__a, __b); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vcgt_u8 (uint8x8_t __a, uint8x8_t __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_cmhiv8qi ((int8x8_t) __a, -+ (int8x8_t) __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vcgt_u16 (uint16x4_t __a, uint16x4_t __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_cmhiv4hi ((int16x4_t) __a, -+ (int16x4_t) __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vcgt_u32 (uint32x2_t __a, uint32x2_t __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_cmhiv2si ((int32x2_t) __a, -+ (int32x2_t) __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vcgt_u64 (uint64x1_t __a, uint64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_cmhidi ((int64x1_t) __a, -+ (int64x1_t) __b); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vcgtq_s8 (int8x16_t __a, int8x16_t __b) -+{ -+ return (uint8x16_t) __builtin_aarch64_cmgtv16qi (__a, __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vcgtq_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_cmgtv8hi (__a, __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vcgtq_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_cmgtv4si (__a, __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vcgtq_s64 (int64x2_t __a, int64x2_t __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_cmgtv2di (__a, __b); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vcgtq_u8 (uint8x16_t __a, uint8x16_t __b) -+{ -+ return (uint8x16_t) __builtin_aarch64_cmhiv16qi ((int8x16_t) __a, -+ (int8x16_t) __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vcgtq_u16 (uint16x8_t __a, uint16x8_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_cmhiv8hi ((int16x8_t) __a, -+ (int16x8_t) __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vcgtq_u32 (uint32x4_t __a, uint32x4_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_cmhiv4si ((int32x4_t) __a, -+ (int32x4_t) __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vcgtq_u64 (uint64x2_t __a, uint64x2_t __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_cmhiv2di ((int64x2_t) __a, -+ (int64x2_t) __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vcgtd_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_cmgtdi (__a, __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vcgtd_u64 (uint64x1_t __a, uint64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_cmhidi ((int64x1_t) __a, -+ (int64x1_t) __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vcgtzd_s64 (int64x1_t __a) -+{ -+ return (uint64x1_t) __builtin_aarch64_cmgtdi (__a, 0); -+} -+ -+/* vcle */ -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vcle_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_cmgev8qi (__b, __a); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vcle_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_cmgev4hi (__b, __a); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vcle_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_cmgev2si (__b, __a); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vcle_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_cmgedi (__b, __a); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vcle_u8 (uint8x8_t __a, uint8x8_t __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_cmhsv8qi ((int8x8_t) __b, -+ (int8x8_t) __a); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vcle_u16 (uint16x4_t __a, uint16x4_t __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_cmhsv4hi ((int16x4_t) __b, -+ (int16x4_t) __a); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vcle_u32 (uint32x2_t __a, uint32x2_t __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_cmhsv2si ((int32x2_t) __b, -+ (int32x2_t) __a); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vcle_u64 (uint64x1_t __a, uint64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_cmhsdi ((int64x1_t) __b, -+ (int64x1_t) __a); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vcleq_s8 (int8x16_t __a, int8x16_t __b) -+{ -+ return (uint8x16_t) __builtin_aarch64_cmgev16qi (__b, __a); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vcleq_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_cmgev8hi (__b, __a); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vcleq_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_cmgev4si (__b, __a); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vcleq_s64 (int64x2_t __a, int64x2_t __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_cmgev2di (__b, __a); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vcleq_u8 (uint8x16_t __a, uint8x16_t __b) -+{ -+ return (uint8x16_t) __builtin_aarch64_cmhsv16qi ((int8x16_t) __b, -+ (int8x16_t) __a); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vcleq_u16 (uint16x8_t __a, uint16x8_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_cmhsv8hi ((int16x8_t) __b, -+ (int16x8_t) __a); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vcleq_u32 (uint32x4_t __a, uint32x4_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_cmhsv4si ((int32x4_t) __b, -+ (int32x4_t) __a); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vcleq_u64 (uint64x2_t __a, uint64x2_t __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_cmhsv2di ((int64x2_t) __b, -+ (int64x2_t) __a); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vcled_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_cmgedi (__b, __a); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vclezd_s64 (int64x1_t __a) -+{ -+ return (uint64x1_t) __builtin_aarch64_cmledi (__a, 0); -+} -+ -+/* vclt */ -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vclt_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_cmgtv8qi (__b, __a); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vclt_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_cmgtv4hi (__b, __a); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vclt_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_cmgtv2si (__b, __a); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vclt_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_cmgtdi (__b, __a); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vclt_u8 (uint8x8_t __a, uint8x8_t __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_cmhiv8qi ((int8x8_t) __b, -+ (int8x8_t) __a); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vclt_u16 (uint16x4_t __a, uint16x4_t __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_cmhiv4hi ((int16x4_t) __b, -+ (int16x4_t) __a); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vclt_u32 (uint32x2_t __a, uint32x2_t __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_cmhiv2si ((int32x2_t) __b, -+ (int32x2_t) __a); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vclt_u64 (uint64x1_t __a, uint64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_cmhidi ((int64x1_t) __b, -+ (int64x1_t) __a); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vcltq_s8 (int8x16_t __a, int8x16_t __b) -+{ -+ return (uint8x16_t) __builtin_aarch64_cmgtv16qi (__b, __a); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vcltq_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_cmgtv8hi (__b, __a); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vcltq_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_cmgtv4si (__b, __a); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vcltq_s64 (int64x2_t __a, int64x2_t __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_cmgtv2di (__b, __a); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vcltq_u8 (uint8x16_t __a, uint8x16_t __b) -+{ -+ return (uint8x16_t) __builtin_aarch64_cmhiv16qi ((int8x16_t) __b, -+ (int8x16_t) __a); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vcltq_u16 (uint16x8_t __a, uint16x8_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_cmhiv8hi ((int16x8_t) __b, -+ (int16x8_t) __a); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vcltq_u32 (uint32x4_t __a, uint32x4_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_cmhiv4si ((int32x4_t) __b, -+ (int32x4_t) __a); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vcltq_u64 (uint64x2_t __a, uint64x2_t __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_cmhiv2di ((int64x2_t) __b, -+ (int64x2_t) __a); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vcltd_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_cmgtdi (__b, __a); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vcltzd_s64 (int64x1_t __a) -+{ -+ return (uint64x1_t) __builtin_aarch64_cmltdi (__a, 0); -+} -+ -+/* vdup */ -+ -+__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -+vdupb_lane_s8 (int8x16_t a, int const b) -+{ -+ return __builtin_aarch64_dup_laneqi (a, b); -+} -+ -+__extension__ static __inline uint8x1_t __attribute__ ((__always_inline__)) -+vdupb_lane_u8 (uint8x16_t a, int const b) -+{ -+ return (uint8x1_t) __builtin_aarch64_dup_laneqi ((int8x16_t) a, b); -+} -+ -+__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -+vduph_lane_s16 (int16x8_t a, int const b) -+{ -+ return __builtin_aarch64_dup_lanehi (a, b); -+} -+ -+__extension__ static __inline uint16x1_t __attribute__ ((__always_inline__)) -+vduph_lane_u16 (uint16x8_t a, int const b) -+{ -+ return (uint16x1_t) __builtin_aarch64_dup_lanehi ((int16x8_t) a, b); -+} -+ -+__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -+vdups_lane_s32 (int32x4_t a, int const b) -+{ -+ return __builtin_aarch64_dup_lanesi (a, b); -+} -+ -+__extension__ static __inline uint32x1_t __attribute__ ((__always_inline__)) -+vdups_lane_u32 (uint32x4_t a, int const b) -+{ -+ return (uint32x1_t) __builtin_aarch64_dup_lanesi ((int32x4_t) a, b); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vdupd_lane_s64 (int64x2_t a, int const b) -+{ -+ return __builtin_aarch64_dup_lanedi (a, b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vdupd_lane_u64 (uint64x2_t a, int const b) -+{ -+ return (uint64x1_t) __builtin_aarch64_dup_lanedi ((int64x2_t) a, b); -+} -+ -+/* vmax */ -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vmax_f32 (float32x2_t __a, float32x2_t __b) -+{ -+ return __builtin_aarch64_fmaxv2sf (__a, __b); -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vmax_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return __builtin_aarch64_smaxv8qi (__a, __b); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vmax_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return __builtin_aarch64_smaxv4hi (__a, __b); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vmax_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return __builtin_aarch64_smaxv2si (__a, __b); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vmax_u8 (uint8x8_t __a, uint8x8_t __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_umaxv8qi ((int8x8_t) __a, -+ (int8x8_t) __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vmax_u16 (uint16x4_t __a, uint16x4_t __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_umaxv4hi ((int16x4_t) __a, -+ (int16x4_t) __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vmax_u32 (uint32x2_t __a, uint32x2_t __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_umaxv2si ((int32x2_t) __a, -+ (int32x2_t) __b); -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vmaxq_f32 (float32x4_t __a, float32x4_t __b) -+{ -+ return __builtin_aarch64_fmaxv4sf (__a, __b); -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vmaxq_f64 (float64x2_t __a, float64x2_t __b) -+{ -+ return __builtin_aarch64_fmaxv2df (__a, __b); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vmaxq_s8 (int8x16_t __a, int8x16_t __b) -+{ -+ return __builtin_aarch64_smaxv16qi (__a, __b); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vmaxq_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return __builtin_aarch64_smaxv8hi (__a, __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vmaxq_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return __builtin_aarch64_smaxv4si (__a, __b); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vmaxq_u8 (uint8x16_t __a, uint8x16_t __b) -+{ -+ return (uint8x16_t) __builtin_aarch64_umaxv16qi ((int8x16_t) __a, -+ (int8x16_t) __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vmaxq_u16 (uint16x8_t __a, uint16x8_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_umaxv8hi ((int16x8_t) __a, -+ (int16x8_t) __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vmaxq_u32 (uint32x4_t __a, uint32x4_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_umaxv4si ((int32x4_t) __a, -+ (int32x4_t) __b); -+} -+ -+/* vmin */ -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vmin_f32 (float32x2_t __a, float32x2_t __b) -+{ -+ return __builtin_aarch64_fminv2sf (__a, __b); -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vmin_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return __builtin_aarch64_sminv8qi (__a, __b); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vmin_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return __builtin_aarch64_sminv4hi (__a, __b); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vmin_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return __builtin_aarch64_sminv2si (__a, __b); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vmin_u8 (uint8x8_t __a, uint8x8_t __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_uminv8qi ((int8x8_t) __a, -+ (int8x8_t) __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vmin_u16 (uint16x4_t __a, uint16x4_t __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_uminv4hi ((int16x4_t) __a, -+ (int16x4_t) __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vmin_u32 (uint32x2_t __a, uint32x2_t __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_uminv2si ((int32x2_t) __a, -+ (int32x2_t) __b); -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vminq_f32 (float32x4_t __a, float32x4_t __b) -+{ -+ return __builtin_aarch64_fminv4sf (__a, __b); -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vminq_f64 (float64x2_t __a, float64x2_t __b) -+{ -+ return __builtin_aarch64_fminv2df (__a, __b); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vminq_s8 (int8x16_t __a, int8x16_t __b) -+{ -+ return __builtin_aarch64_sminv16qi (__a, __b); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vminq_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return __builtin_aarch64_sminv8hi (__a, __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vminq_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return __builtin_aarch64_sminv4si (__a, __b); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vminq_u8 (uint8x16_t __a, uint8x16_t __b) -+{ -+ return (uint8x16_t) __builtin_aarch64_uminv16qi ((int8x16_t) __a, -+ (int8x16_t) __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vminq_u16 (uint16x8_t __a, uint16x8_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_uminv8hi ((int16x8_t) __a, -+ (int16x8_t) __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vminq_u32 (uint32x4_t __a, uint32x4_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_uminv4si ((int32x4_t) __a, -+ (int32x4_t) __b); -+} -+ -+/* vmla */ -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vmla_f32 (float32x2_t a, float32x2_t b, float32x2_t c) -+{ -+ return a + b * c; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vmlaq_f32 (float32x4_t a, float32x4_t b, float32x4_t c) -+{ -+ return a + b * c; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vmlaq_f64 (float64x2_t a, float64x2_t b, float64x2_t c) -+{ -+ return a + b * c; -+} -+ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vmls_f32 (float32x2_t a, float32x2_t b, float32x2_t c) -+{ -+ return a - b * c; -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vmlsq_f32 (float32x4_t a, float32x4_t b, float32x4_t c) -+{ -+ return a - b * c; -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vmlsq_f64 (float64x2_t a, float64x2_t b, float64x2_t c) -+{ -+ return a - b * c; -+} -+ -+/* vqabs */ -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqabsq_s64 (int64x2_t __a) -+{ -+ return (int64x2_t) __builtin_aarch64_sqabsv2di (__a); -+} -+ -+__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -+vqabsb_s8 (int8x1_t __a) -+{ -+ return (int8x1_t) __builtin_aarch64_sqabsqi (__a); -+} -+ -+__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -+vqabsh_s16 (int16x1_t __a) -+{ -+ return (int16x1_t) __builtin_aarch64_sqabshi (__a); -+} -+ -+__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -+vqabss_s32 (int32x1_t __a) -+{ -+ return (int32x1_t) __builtin_aarch64_sqabssi (__a); -+} -+ -+/* vqadd */ -+ -+__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -+vqaddb_s8 (int8x1_t __a, int8x1_t __b) -+{ -+ return (int8x1_t) __builtin_aarch64_sqaddqi (__a, __b); -+} -+ -+__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -+vqaddh_s16 (int16x1_t __a, int16x1_t __b) -+{ -+ return (int16x1_t) __builtin_aarch64_sqaddhi (__a, __b); -+} -+ -+__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -+vqadds_s32 (int32x1_t __a, int32x1_t __b) -+{ -+ return (int32x1_t) __builtin_aarch64_sqaddsi (__a, __b); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vqaddd_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return (int64x1_t) __builtin_aarch64_sqadddi (__a, __b); -+} -+ -+__extension__ static __inline uint8x1_t __attribute__ ((__always_inline__)) -+vqaddb_u8 (uint8x1_t __a, uint8x1_t __b) -+{ -+ return (uint8x1_t) __builtin_aarch64_uqaddqi (__a, __b); -+} -+ -+__extension__ static __inline uint16x1_t __attribute__ ((__always_inline__)) -+vqaddh_u16 (uint16x1_t __a, uint16x1_t __b) -+{ -+ return (uint16x1_t) __builtin_aarch64_uqaddhi (__a, __b); -+} -+ -+__extension__ static __inline uint32x1_t __attribute__ ((__always_inline__)) -+vqadds_u32 (uint32x1_t __a, uint32x1_t __b) -+{ -+ return (uint32x1_t) __builtin_aarch64_uqaddsi (__a, __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vqaddd_u64 (uint64x1_t __a, uint64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_uqadddi (__a, __b); -+} -+ -+/* vqdmlal */ -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqdmlal_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c) -+{ -+ return __builtin_aarch64_sqdmlalv4hi (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqdmlal_high_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c) -+{ -+ return __builtin_aarch64_sqdmlal2v8hi (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqdmlal_high_lane_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c, -+ int const __d) -+{ -+ return __builtin_aarch64_sqdmlal2_lanev8hi (__a, __b, __c, __d); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqdmlal_high_laneq_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c, -+ int const __d) -+{ -+ return __builtin_aarch64_sqdmlal2_laneqv8hi (__a, __b, __c, __d); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqdmlal_high_n_s16 (int32x4_t __a, int16x8_t __b, int16_t __c) -+{ -+ return __builtin_aarch64_sqdmlal2_nv8hi (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqdmlal_lane_s16 (int32x4_t __a, int16x4_t __b, int16x8_t __c, int const __d) -+{ -+ return __builtin_aarch64_sqdmlal_lanev4hi (__a, __b, __c, __d); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqdmlal_laneq_s16 (int32x4_t __a, int16x4_t __b, int16x8_t __c, int const __d) -+{ -+ return __builtin_aarch64_sqdmlal_laneqv4hi (__a, __b, __c, __d); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqdmlal_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c) -+{ -+ return __builtin_aarch64_sqdmlal_nv4hi (__a, __b, __c); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqdmlal_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c) -+{ -+ return __builtin_aarch64_sqdmlalv2si (__a, __b, __c); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqdmlal_high_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c) -+{ -+ return __builtin_aarch64_sqdmlal2v4si (__a, __b, __c); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqdmlal_high_lane_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c, -+ int const __d) -+{ -+ return __builtin_aarch64_sqdmlal2_lanev4si (__a, __b, __c, __d); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqdmlal_high_laneq_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c, -+ int const __d) -+{ -+ return __builtin_aarch64_sqdmlal2_laneqv4si (__a, __b, __c, __d); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqdmlal_high_n_s32 (int64x2_t __a, int32x4_t __b, int32_t __c) -+{ -+ return __builtin_aarch64_sqdmlal2_nv4si (__a, __b, __c); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqdmlal_lane_s32 (int64x2_t __a, int32x2_t __b, int32x4_t __c, int const __d) -+{ -+ return __builtin_aarch64_sqdmlal_lanev2si (__a, __b, __c, __d); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqdmlal_laneq_s32 (int64x2_t __a, int32x2_t __b, int32x4_t __c, int const __d) -+{ -+ return __builtin_aarch64_sqdmlal_laneqv2si (__a, __b, __c, __d); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqdmlal_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c) -+{ -+ return __builtin_aarch64_sqdmlal_nv2si (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -+vqdmlalh_s16 (int32x1_t __a, int16x1_t __b, int16x1_t __c) -+{ -+ return __builtin_aarch64_sqdmlalhi (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -+vqdmlalh_lane_s16 (int32x1_t __a, int16x1_t __b, int16x8_t __c, const int __d) -+{ -+ return __builtin_aarch64_sqdmlal_lanehi (__a, __b, __c, __d); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vqdmlals_s32 (int64x1_t __a, int32x1_t __b, int32x1_t __c) -+{ -+ return __builtin_aarch64_sqdmlalsi (__a, __b, __c); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vqdmlals_lane_s32 (int64x1_t __a, int32x1_t __b, int32x4_t __c, const int __d) -+{ -+ return __builtin_aarch64_sqdmlal_lanesi (__a, __b, __c, __d); -+} -+ -+/* vqdmlsl */ -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqdmlsl_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c) -+{ -+ return __builtin_aarch64_sqdmlslv4hi (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqdmlsl_high_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c) -+{ -+ return __builtin_aarch64_sqdmlsl2v8hi (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqdmlsl_high_lane_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c, -+ int const __d) -+{ -+ return __builtin_aarch64_sqdmlsl2_lanev8hi (__a, __b, __c, __d); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqdmlsl_high_laneq_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c, -+ int const __d) -+{ -+ return __builtin_aarch64_sqdmlsl2_laneqv8hi (__a, __b, __c, __d); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqdmlsl_high_n_s16 (int32x4_t __a, int16x8_t __b, int16_t __c) -+{ -+ return __builtin_aarch64_sqdmlsl2_nv8hi (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqdmlsl_lane_s16 (int32x4_t __a, int16x4_t __b, int16x8_t __c, int const __d) -+{ -+ return __builtin_aarch64_sqdmlsl_lanev4hi (__a, __b, __c, __d); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqdmlsl_laneq_s16 (int32x4_t __a, int16x4_t __b, int16x8_t __c, int const __d) -+{ -+ return __builtin_aarch64_sqdmlsl_laneqv4hi (__a, __b, __c, __d); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqdmlsl_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c) -+{ -+ return __builtin_aarch64_sqdmlsl_nv4hi (__a, __b, __c); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqdmlsl_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c) -+{ -+ return __builtin_aarch64_sqdmlslv2si (__a, __b, __c); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqdmlsl_high_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c) -+{ -+ return __builtin_aarch64_sqdmlsl2v4si (__a, __b, __c); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqdmlsl_high_lane_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c, -+ int const __d) -+{ -+ return __builtin_aarch64_sqdmlsl2_lanev4si (__a, __b, __c, __d); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqdmlsl_high_laneq_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c, -+ int const __d) -+{ -+ return __builtin_aarch64_sqdmlsl2_laneqv4si (__a, __b, __c, __d); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqdmlsl_high_n_s32 (int64x2_t __a, int32x4_t __b, int32_t __c) -+{ -+ return __builtin_aarch64_sqdmlsl2_nv4si (__a, __b, __c); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqdmlsl_lane_s32 (int64x2_t __a, int32x2_t __b, int32x4_t __c, int const __d) -+{ -+ return __builtin_aarch64_sqdmlsl_lanev2si (__a, __b, __c, __d); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqdmlsl_laneq_s32 (int64x2_t __a, int32x2_t __b, int32x4_t __c, int const __d) -+{ -+ return __builtin_aarch64_sqdmlsl_laneqv2si (__a, __b, __c, __d); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqdmlsl_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c) -+{ -+ return __builtin_aarch64_sqdmlsl_nv2si (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -+vqdmlslh_s16 (int32x1_t __a, int16x1_t __b, int16x1_t __c) -+{ -+ return __builtin_aarch64_sqdmlslhi (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -+vqdmlslh_lane_s16 (int32x1_t __a, int16x1_t __b, int16x8_t __c, const int __d) -+{ -+ return __builtin_aarch64_sqdmlsl_lanehi (__a, __b, __c, __d); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vqdmlsls_s32 (int64x1_t __a, int32x1_t __b, int32x1_t __c) -+{ -+ return __builtin_aarch64_sqdmlslsi (__a, __b, __c); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vqdmlsls_lane_s32 (int64x1_t __a, int32x1_t __b, int32x4_t __c, const int __d) -+{ -+ return __builtin_aarch64_sqdmlsl_lanesi (__a, __b, __c, __d); -+} -+ -+/* vqdmulh */ -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vqdmulh_lane_s16 (int16x4_t __a, int16x8_t __b, const int __c) -+{ -+ return __builtin_aarch64_sqdmulh_lanev4hi (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vqdmulh_lane_s32 (int32x2_t __a, int32x4_t __b, const int __c) -+{ -+ return __builtin_aarch64_sqdmulh_lanev2si (__a, __b, __c); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vqdmulhq_lane_s16 (int16x8_t __a, int16x8_t __b, const int __c) -+{ -+ return __builtin_aarch64_sqdmulh_lanev8hi (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqdmulhq_lane_s32 (int32x4_t __a, int32x4_t __b, const int __c) -+{ -+ return __builtin_aarch64_sqdmulh_lanev4si (__a, __b, __c); -+} -+ -+__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -+vqdmulhh_s16 (int16x1_t __a, int16x1_t __b) -+{ -+ return (int16x1_t) __builtin_aarch64_sqdmulhhi (__a, __b); -+} -+ -+__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -+vqdmulhh_lane_s16 (int16x1_t __a, int16x8_t __b, const int __c) -+{ -+ return __builtin_aarch64_sqdmulh_lanehi (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -+vqdmulhs_s32 (int32x1_t __a, int32x1_t __b) -+{ -+ return (int32x1_t) __builtin_aarch64_sqdmulhsi (__a, __b); -+} -+ -+__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -+vqdmulhs_lane_s32 (int32x1_t __a, int32x4_t __b, const int __c) -+{ -+ return __builtin_aarch64_sqdmulh_lanesi (__a, __b, __c); -+} -+ -+/* vqdmull */ -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqdmull_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return __builtin_aarch64_sqdmullv4hi (__a, __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqdmull_high_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return __builtin_aarch64_sqdmull2v8hi (__a, __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqdmull_high_lane_s16 (int16x8_t __a, int16x8_t __b, int const __c) -+{ -+ return __builtin_aarch64_sqdmull2_lanev8hi (__a, __b,__c); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqdmull_high_laneq_s16 (int16x8_t __a, int16x8_t __b, int const __c) -+{ -+ return __builtin_aarch64_sqdmull2_laneqv8hi (__a, __b,__c); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqdmull_high_n_s16 (int16x8_t __a, int16_t __b) -+{ -+ return __builtin_aarch64_sqdmull2_nv8hi (__a, __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqdmull_lane_s16 (int16x4_t __a, int16x8_t __b, int const __c) -+{ -+ return __builtin_aarch64_sqdmull_lanev4hi (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqdmull_laneq_s16 (int16x4_t __a, int16x8_t __b, int const __c) -+{ -+ return __builtin_aarch64_sqdmull_laneqv4hi (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqdmull_n_s16 (int16x4_t __a, int16_t __b) -+{ -+ return __builtin_aarch64_sqdmull_nv4hi (__a, __b); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqdmull_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return __builtin_aarch64_sqdmullv2si (__a, __b); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqdmull_high_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return __builtin_aarch64_sqdmull2v4si (__a, __b); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqdmull_high_lane_s32 (int32x4_t __a, int32x4_t __b, int const __c) -+{ -+ return __builtin_aarch64_sqdmull2_lanev4si (__a, __b, __c); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqdmull_high_laneq_s32 (int32x4_t __a, int32x4_t __b, int const __c) -+{ -+ return __builtin_aarch64_sqdmull2_laneqv4si (__a, __b, __c); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqdmull_high_n_s32 (int32x4_t __a, int32_t __b) -+{ -+ return __builtin_aarch64_sqdmull2_nv4si (__a, __b); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqdmull_lane_s32 (int32x2_t __a, int32x4_t __b, int const __c) -+{ -+ return __builtin_aarch64_sqdmull_lanev2si (__a, __b, __c); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqdmull_laneq_s32 (int32x2_t __a, int32x4_t __b, int const __c) -+{ -+ return __builtin_aarch64_sqdmull_laneqv2si (__a, __b, __c); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqdmull_n_s32 (int32x2_t __a, int32_t __b) -+{ -+ return __builtin_aarch64_sqdmull_nv2si (__a, __b); -+} -+ -+__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -+vqdmullh_s16 (int16x1_t __a, int16x1_t __b) -+{ -+ return (int32x1_t) __builtin_aarch64_sqdmullhi (__a, __b); -+} -+ -+__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -+vqdmullh_lane_s16 (int16x1_t __a, int16x8_t __b, const int __c) -+{ -+ return __builtin_aarch64_sqdmull_lanehi (__a, __b, __c); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vqdmulls_s32 (int32x1_t __a, int32x1_t __b) -+{ -+ return (int64x1_t) __builtin_aarch64_sqdmullsi (__a, __b); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vqdmulls_lane_s32 (int32x1_t __a, int32x4_t __b, const int __c) -+{ -+ return __builtin_aarch64_sqdmull_lanesi (__a, __b, __c); -+} -+ -+/* vqmovn */ -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vqmovn_s16 (int16x8_t __a) -+{ -+ return (int8x8_t) __builtin_aarch64_sqmovnv8hi (__a); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vqmovn_s32 (int32x4_t __a) -+{ -+ return (int16x4_t) __builtin_aarch64_sqmovnv4si (__a); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vqmovn_s64 (int64x2_t __a) -+{ -+ return (int32x2_t) __builtin_aarch64_sqmovnv2di (__a); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vqmovn_u16 (uint16x8_t __a) -+{ -+ return (uint8x8_t) __builtin_aarch64_uqmovnv8hi ((int16x8_t) __a); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vqmovn_u32 (uint32x4_t __a) -+{ -+ return (uint16x4_t) __builtin_aarch64_uqmovnv4si ((int32x4_t) __a); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vqmovn_u64 (uint64x2_t __a) -+{ -+ return (uint32x2_t) __builtin_aarch64_uqmovnv2di ((int64x2_t) __a); -+} -+ -+__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -+vqmovnh_s16 (int16x1_t __a) -+{ -+ return (int8x1_t) __builtin_aarch64_sqmovnhi (__a); -+} -+ -+__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -+vqmovns_s32 (int32x1_t __a) -+{ -+ return (int16x1_t) __builtin_aarch64_sqmovnsi (__a); -+} -+ -+__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -+vqmovnd_s64 (int64x1_t __a) -+{ -+ return (int32x1_t) __builtin_aarch64_sqmovndi (__a); -+} -+ -+__extension__ static __inline uint8x1_t __attribute__ ((__always_inline__)) -+vqmovnh_u16 (uint16x1_t __a) -+{ -+ return (uint8x1_t) __builtin_aarch64_uqmovnhi (__a); -+} -+ -+__extension__ static __inline uint16x1_t __attribute__ ((__always_inline__)) -+vqmovns_u32 (uint32x1_t __a) -+{ -+ return (uint16x1_t) __builtin_aarch64_uqmovnsi (__a); -+} -+ -+__extension__ static __inline uint32x1_t __attribute__ ((__always_inline__)) -+vqmovnd_u64 (uint64x1_t __a) -+{ -+ return (uint32x1_t) __builtin_aarch64_uqmovndi (__a); -+} -+ -+/* vqmovun */ -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vqmovun_s16 (int16x8_t __a) -+{ -+ return (uint8x8_t) __builtin_aarch64_sqmovunv8hi (__a); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vqmovun_s32 (int32x4_t __a) -+{ -+ return (uint16x4_t) __builtin_aarch64_sqmovunv4si (__a); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vqmovun_s64 (int64x2_t __a) -+{ -+ return (uint32x2_t) __builtin_aarch64_sqmovunv2di (__a); -+} -+ -+__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -+vqmovunh_s16 (int16x1_t __a) -+{ -+ return (int8x1_t) __builtin_aarch64_sqmovunhi (__a); -+} -+ -+__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -+vqmovuns_s32 (int32x1_t __a) -+{ -+ return (int16x1_t) __builtin_aarch64_sqmovunsi (__a); -+} -+ -+__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -+vqmovund_s64 (int64x1_t __a) -+{ -+ return (int32x1_t) __builtin_aarch64_sqmovundi (__a); -+} -+ -+/* vqneg */ -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqnegq_s64 (int64x2_t __a) -+{ -+ return (int64x2_t) __builtin_aarch64_sqnegv2di (__a); -+} -+ -+__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -+vqnegb_s8 (int8x1_t __a) -+{ -+ return (int8x1_t) __builtin_aarch64_sqnegqi (__a); -+} -+ -+__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -+vqnegh_s16 (int16x1_t __a) -+{ -+ return (int16x1_t) __builtin_aarch64_sqneghi (__a); -+} -+ -+__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -+vqnegs_s32 (int32x1_t __a) -+{ -+ return (int32x1_t) __builtin_aarch64_sqnegsi (__a); -+} -+ -+/* vqrdmulh */ -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vqrdmulh_lane_s16 (int16x4_t __a, int16x8_t __b, const int __c) -+{ -+ return __builtin_aarch64_sqrdmulh_lanev4hi (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vqrdmulh_lane_s32 (int32x2_t __a, int32x4_t __b, const int __c) -+{ -+ return __builtin_aarch64_sqrdmulh_lanev2si (__a, __b, __c); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vqrdmulhq_lane_s16 (int16x8_t __a, int16x8_t __b, const int __c) -+{ -+ return __builtin_aarch64_sqrdmulh_lanev8hi (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqrdmulhq_lane_s32 (int32x4_t __a, int32x4_t __b, const int __c) -+{ -+ return __builtin_aarch64_sqrdmulh_lanev4si (__a, __b, __c); -+} -+ -+__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -+vqrdmulhh_s16 (int16x1_t __a, int16x1_t __b) -+{ -+ return (int16x1_t) __builtin_aarch64_sqrdmulhhi (__a, __b); -+} -+ -+__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -+vqrdmulhh_lane_s16 (int16x1_t __a, int16x8_t __b, const int __c) -+{ -+ return __builtin_aarch64_sqrdmulh_lanehi (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -+vqrdmulhs_s32 (int32x1_t __a, int32x1_t __b) -+{ -+ return (int32x1_t) __builtin_aarch64_sqrdmulhsi (__a, __b); -+} -+ -+__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -+vqrdmulhs_lane_s32 (int32x1_t __a, int32x4_t __b, const int __c) -+{ -+ return __builtin_aarch64_sqrdmulh_lanesi (__a, __b, __c); -+} -+ -+/* vqrshl */ -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vqrshl_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return __builtin_aarch64_sqrshlv8qi (__a, __b); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vqrshl_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return __builtin_aarch64_sqrshlv4hi (__a, __b); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vqrshl_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return __builtin_aarch64_sqrshlv2si (__a, __b); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vqrshl_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return __builtin_aarch64_sqrshldi (__a, __b); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vqrshl_u8 (uint8x8_t __a, int8x8_t __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_uqrshlv8qi ((int8x8_t) __a, __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vqrshl_u16 (uint16x4_t __a, int16x4_t __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_uqrshlv4hi ((int16x4_t) __a, __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vqrshl_u32 (uint32x2_t __a, int32x2_t __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_uqrshlv2si ((int32x2_t) __a, __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vqrshl_u64 (uint64x1_t __a, int64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_uqrshldi ((int64x1_t) __a, __b); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vqrshlq_s8 (int8x16_t __a, int8x16_t __b) -+{ -+ return __builtin_aarch64_sqrshlv16qi (__a, __b); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vqrshlq_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return __builtin_aarch64_sqrshlv8hi (__a, __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqrshlq_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return __builtin_aarch64_sqrshlv4si (__a, __b); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqrshlq_s64 (int64x2_t __a, int64x2_t __b) -+{ -+ return __builtin_aarch64_sqrshlv2di (__a, __b); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vqrshlq_u8 (uint8x16_t __a, int8x16_t __b) -+{ -+ return (uint8x16_t) __builtin_aarch64_uqrshlv16qi ((int8x16_t) __a, __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vqrshlq_u16 (uint16x8_t __a, int16x8_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_uqrshlv8hi ((int16x8_t) __a, __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vqrshlq_u32 (uint32x4_t __a, int32x4_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_uqrshlv4si ((int32x4_t) __a, __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vqrshlq_u64 (uint64x2_t __a, int64x2_t __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_uqrshlv2di ((int64x2_t) __a, __b); -+} -+ -+__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -+vqrshlb_s8 (int8x1_t __a, int8x1_t __b) -+{ -+ return __builtin_aarch64_sqrshlqi (__a, __b); -+} -+ -+__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -+vqrshlh_s16 (int16x1_t __a, int16x1_t __b) -+{ -+ return __builtin_aarch64_sqrshlhi (__a, __b); -+} -+ -+__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -+vqrshls_s32 (int32x1_t __a, int32x1_t __b) -+{ -+ return __builtin_aarch64_sqrshlsi (__a, __b); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vqrshld_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return __builtin_aarch64_sqrshldi (__a, __b); -+} -+ -+__extension__ static __inline uint8x1_t __attribute__ ((__always_inline__)) -+vqrshlb_u8 (uint8x1_t __a, uint8x1_t __b) -+{ -+ return (uint8x1_t) __builtin_aarch64_uqrshlqi (__a, __b); -+} -+ -+__extension__ static __inline uint16x1_t __attribute__ ((__always_inline__)) -+vqrshlh_u16 (uint16x1_t __a, uint16x1_t __b) -+{ -+ return (uint16x1_t) __builtin_aarch64_uqrshlhi (__a, __b); -+} -+ -+__extension__ static __inline uint32x1_t __attribute__ ((__always_inline__)) -+vqrshls_u32 (uint32x1_t __a, uint32x1_t __b) -+{ -+ return (uint32x1_t) __builtin_aarch64_uqrshlsi (__a, __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vqrshld_u64 (uint64x1_t __a, uint64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_uqrshldi (__a, __b); -+} -+ -+/* vqrshrn */ -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vqrshrn_n_s16 (int16x8_t __a, const int __b) -+{ -+ return (int8x8_t) __builtin_aarch64_sqrshrn_nv8hi (__a, __b); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vqrshrn_n_s32 (int32x4_t __a, const int __b) -+{ -+ return (int16x4_t) __builtin_aarch64_sqrshrn_nv4si (__a, __b); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vqrshrn_n_s64 (int64x2_t __a, const int __b) -+{ -+ return (int32x2_t) __builtin_aarch64_sqrshrn_nv2di (__a, __b); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vqrshrn_n_u16 (uint16x8_t __a, const int __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_uqrshrn_nv8hi ((int16x8_t) __a, __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vqrshrn_n_u32 (uint32x4_t __a, const int __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_uqrshrn_nv4si ((int32x4_t) __a, __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vqrshrn_n_u64 (uint64x2_t __a, const int __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_uqrshrn_nv2di ((int64x2_t) __a, __b); -+} -+ -+__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -+vqrshrnh_n_s16 (int16x1_t __a, const int __b) -+{ -+ return (int8x1_t) __builtin_aarch64_sqrshrn_nhi (__a, __b); -+} -+ -+__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -+vqrshrns_n_s32 (int32x1_t __a, const int __b) -+{ -+ return (int16x1_t) __builtin_aarch64_sqrshrn_nsi (__a, __b); -+} -+ -+__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -+vqrshrnd_n_s64 (int64x1_t __a, const int __b) -+{ -+ return (int32x1_t) __builtin_aarch64_sqrshrn_ndi (__a, __b); -+} -+ -+__extension__ static __inline uint8x1_t __attribute__ ((__always_inline__)) -+vqrshrnh_n_u16 (uint16x1_t __a, const int __b) -+{ -+ return (uint8x1_t) __builtin_aarch64_uqrshrn_nhi (__a, __b); -+} -+ -+__extension__ static __inline uint16x1_t __attribute__ ((__always_inline__)) -+vqrshrns_n_u32 (uint32x1_t __a, const int __b) -+{ -+ return (uint16x1_t) __builtin_aarch64_uqrshrn_nsi (__a, __b); -+} -+ -+__extension__ static __inline uint32x1_t __attribute__ ((__always_inline__)) -+vqrshrnd_n_u64 (uint64x1_t __a, const int __b) -+{ -+ return (uint32x1_t) __builtin_aarch64_uqrshrn_ndi (__a, __b); -+} -+ -+/* vqrshrun */ -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vqrshrun_n_s16 (int16x8_t __a, const int __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_sqrshrun_nv8hi (__a, __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vqrshrun_n_s32 (int32x4_t __a, const int __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_sqrshrun_nv4si (__a, __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vqrshrun_n_s64 (int64x2_t __a, const int __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_sqrshrun_nv2di (__a, __b); -+} -+ -+__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -+vqrshrunh_n_s16 (int16x1_t __a, const int __b) -+{ -+ return (int8x1_t) __builtin_aarch64_sqrshrun_nhi (__a, __b); -+} -+ -+__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -+vqrshruns_n_s32 (int32x1_t __a, const int __b) -+{ -+ return (int16x1_t) __builtin_aarch64_sqrshrun_nsi (__a, __b); -+} -+ -+__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -+vqrshrund_n_s64 (int64x1_t __a, const int __b) -+{ -+ return (int32x1_t) __builtin_aarch64_sqrshrun_ndi (__a, __b); -+} -+ -+/* vqshl */ -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vqshl_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return __builtin_aarch64_sqshlv8qi (__a, __b); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vqshl_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return __builtin_aarch64_sqshlv4hi (__a, __b); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vqshl_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return __builtin_aarch64_sqshlv2si (__a, __b); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vqshl_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return __builtin_aarch64_sqshldi (__a, __b); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vqshl_u8 (uint8x8_t __a, int8x8_t __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_uqshlv8qi ((int8x8_t) __a, __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vqshl_u16 (uint16x4_t __a, int16x4_t __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_uqshlv4hi ((int16x4_t) __a, __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vqshl_u32 (uint32x2_t __a, int32x2_t __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_uqshlv2si ((int32x2_t) __a, __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vqshl_u64 (uint64x1_t __a, int64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_uqshldi ((int64x1_t) __a, __b); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vqshlq_s8 (int8x16_t __a, int8x16_t __b) -+{ -+ return __builtin_aarch64_sqshlv16qi (__a, __b); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vqshlq_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return __builtin_aarch64_sqshlv8hi (__a, __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqshlq_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return __builtin_aarch64_sqshlv4si (__a, __b); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqshlq_s64 (int64x2_t __a, int64x2_t __b) -+{ -+ return __builtin_aarch64_sqshlv2di (__a, __b); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vqshlq_u8 (uint8x16_t __a, int8x16_t __b) -+{ -+ return (uint8x16_t) __builtin_aarch64_uqshlv16qi ((int8x16_t) __a, __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vqshlq_u16 (uint16x8_t __a, int16x8_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_uqshlv8hi ((int16x8_t) __a, __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vqshlq_u32 (uint32x4_t __a, int32x4_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_uqshlv4si ((int32x4_t) __a, __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vqshlq_u64 (uint64x2_t __a, int64x2_t __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_uqshlv2di ((int64x2_t) __a, __b); -+} -+ -+__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -+vqshlb_s8 (int8x1_t __a, int8x1_t __b) -+{ -+ return __builtin_aarch64_sqshlqi (__a, __b); -+} -+ -+__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -+vqshlh_s16 (int16x1_t __a, int16x1_t __b) -+{ -+ return __builtin_aarch64_sqshlhi (__a, __b); -+} -+ -+__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -+vqshls_s32 (int32x1_t __a, int32x1_t __b) -+{ -+ return __builtin_aarch64_sqshlsi (__a, __b); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vqshld_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return __builtin_aarch64_sqshldi (__a, __b); -+} -+ -+__extension__ static __inline uint8x1_t __attribute__ ((__always_inline__)) -+vqshlb_u8 (uint8x1_t __a, uint8x1_t __b) -+{ -+ return (uint8x1_t) __builtin_aarch64_uqshlqi (__a, __b); -+} -+ -+__extension__ static __inline uint16x1_t __attribute__ ((__always_inline__)) -+vqshlh_u16 (uint16x1_t __a, uint16x1_t __b) -+{ -+ return (uint16x1_t) __builtin_aarch64_uqshlhi (__a, __b); -+} -+ -+__extension__ static __inline uint32x1_t __attribute__ ((__always_inline__)) -+vqshls_u32 (uint32x1_t __a, uint32x1_t __b) -+{ -+ return (uint32x1_t) __builtin_aarch64_uqshlsi (__a, __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vqshld_u64 (uint64x1_t __a, uint64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_uqshldi (__a, __b); -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vqshl_n_s8 (int8x8_t __a, const int __b) -+{ -+ return (int8x8_t) __builtin_aarch64_sqshl_nv8qi (__a, __b); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vqshl_n_s16 (int16x4_t __a, const int __b) -+{ -+ return (int16x4_t) __builtin_aarch64_sqshl_nv4hi (__a, __b); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vqshl_n_s32 (int32x2_t __a, const int __b) -+{ -+ return (int32x2_t) __builtin_aarch64_sqshl_nv2si (__a, __b); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vqshl_n_s64 (int64x1_t __a, const int __b) -+{ -+ return (int64x1_t) __builtin_aarch64_sqshl_ndi (__a, __b); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vqshl_n_u8 (uint8x8_t __a, const int __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_uqshl_nv8qi ((int8x8_t) __a, __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vqshl_n_u16 (uint16x4_t __a, const int __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_uqshl_nv4hi ((int16x4_t) __a, __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vqshl_n_u32 (uint32x2_t __a, const int __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_uqshl_nv2si ((int32x2_t) __a, __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vqshl_n_u64 (uint64x1_t __a, const int __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_uqshl_ndi ((int64x1_t) __a, __b); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vqshlq_n_s8 (int8x16_t __a, const int __b) -+{ -+ return (int8x16_t) __builtin_aarch64_sqshl_nv16qi (__a, __b); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vqshlq_n_s16 (int16x8_t __a, const int __b) -+{ -+ return (int16x8_t) __builtin_aarch64_sqshl_nv8hi (__a, __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vqshlq_n_s32 (int32x4_t __a, const int __b) -+{ -+ return (int32x4_t) __builtin_aarch64_sqshl_nv4si (__a, __b); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vqshlq_n_s64 (int64x2_t __a, const int __b) -+{ -+ return (int64x2_t) __builtin_aarch64_sqshl_nv2di (__a, __b); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vqshlq_n_u8 (uint8x16_t __a, const int __b) -+{ -+ return (uint8x16_t) __builtin_aarch64_uqshl_nv16qi ((int8x16_t) __a, __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vqshlq_n_u16 (uint16x8_t __a, const int __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_uqshl_nv8hi ((int16x8_t) __a, __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vqshlq_n_u32 (uint32x4_t __a, const int __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_uqshl_nv4si ((int32x4_t) __a, __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vqshlq_n_u64 (uint64x2_t __a, const int __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_uqshl_nv2di ((int64x2_t) __a, __b); -+} -+ -+__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -+vqshlb_n_s8 (int8x1_t __a, const int __b) -+{ -+ return (int8x1_t) __builtin_aarch64_sqshl_nqi (__a, __b); -+} -+ -+__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -+vqshlh_n_s16 (int16x1_t __a, const int __b) -+{ -+ return (int16x1_t) __builtin_aarch64_sqshl_nhi (__a, __b); -+} -+ -+__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -+vqshls_n_s32 (int32x1_t __a, const int __b) -+{ -+ return (int32x1_t) __builtin_aarch64_sqshl_nsi (__a, __b); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vqshld_n_s64 (int64x1_t __a, const int __b) -+{ -+ return (int64x1_t) __builtin_aarch64_sqshl_ndi (__a, __b); -+} -+ -+__extension__ static __inline uint8x1_t __attribute__ ((__always_inline__)) -+vqshlb_n_u8 (uint8x1_t __a, const int __b) -+{ -+ return (uint8x1_t) __builtin_aarch64_uqshl_nqi (__a, __b); -+} -+ -+__extension__ static __inline uint16x1_t __attribute__ ((__always_inline__)) -+vqshlh_n_u16 (uint16x1_t __a, const int __b) -+{ -+ return (uint16x1_t) __builtin_aarch64_uqshl_nhi (__a, __b); -+} -+ -+__extension__ static __inline uint32x1_t __attribute__ ((__always_inline__)) -+vqshls_n_u32 (uint32x1_t __a, const int __b) -+{ -+ return (uint32x1_t) __builtin_aarch64_uqshl_nsi (__a, __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vqshld_n_u64 (uint64x1_t __a, const int __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_uqshl_ndi (__a, __b); -+} -+ -+/* vqshlu */ -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vqshlu_n_s8 (int8x8_t __a, const int __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_sqshlu_nv8qi (__a, __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vqshlu_n_s16 (int16x4_t __a, const int __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_sqshlu_nv4hi (__a, __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vqshlu_n_s32 (int32x2_t __a, const int __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_sqshlu_nv2si (__a, __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vqshlu_n_s64 (int64x1_t __a, const int __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_sqshlu_ndi (__a, __b); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vqshluq_n_s8 (int8x16_t __a, const int __b) -+{ -+ return (uint8x16_t) __builtin_aarch64_sqshlu_nv16qi (__a, __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vqshluq_n_s16 (int16x8_t __a, const int __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_sqshlu_nv8hi (__a, __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vqshluq_n_s32 (int32x4_t __a, const int __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_sqshlu_nv4si (__a, __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vqshluq_n_s64 (int64x2_t __a, const int __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_sqshlu_nv2di (__a, __b); -+} -+ -+__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -+vqshlub_n_s8 (int8x1_t __a, const int __b) -+{ -+ return (int8x1_t) __builtin_aarch64_sqshlu_nqi (__a, __b); -+} -+ -+__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -+vqshluh_n_s16 (int16x1_t __a, const int __b) -+{ -+ return (int16x1_t) __builtin_aarch64_sqshlu_nhi (__a, __b); -+} -+ -+__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -+vqshlus_n_s32 (int32x1_t __a, const int __b) -+{ -+ return (int32x1_t) __builtin_aarch64_sqshlu_nsi (__a, __b); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vqshlud_n_s64 (int64x1_t __a, const int __b) -+{ -+ return (int64x1_t) __builtin_aarch64_sqshlu_ndi (__a, __b); -+} -+ -+/* vqshrn */ -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vqshrn_n_s16 (int16x8_t __a, const int __b) -+{ -+ return (int8x8_t) __builtin_aarch64_sqshrn_nv8hi (__a, __b); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vqshrn_n_s32 (int32x4_t __a, const int __b) -+{ -+ return (int16x4_t) __builtin_aarch64_sqshrn_nv4si (__a, __b); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vqshrn_n_s64 (int64x2_t __a, const int __b) -+{ -+ return (int32x2_t) __builtin_aarch64_sqshrn_nv2di (__a, __b); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vqshrn_n_u16 (uint16x8_t __a, const int __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_uqshrn_nv8hi ((int16x8_t) __a, __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vqshrn_n_u32 (uint32x4_t __a, const int __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_uqshrn_nv4si ((int32x4_t) __a, __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vqshrn_n_u64 (uint64x2_t __a, const int __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_uqshrn_nv2di ((int64x2_t) __a, __b); -+} -+ -+__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -+vqshrnh_n_s16 (int16x1_t __a, const int __b) -+{ -+ return (int8x1_t) __builtin_aarch64_sqshrn_nhi (__a, __b); -+} -+ -+__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -+vqshrns_n_s32 (int32x1_t __a, const int __b) -+{ -+ return (int16x1_t) __builtin_aarch64_sqshrn_nsi (__a, __b); -+} -+ -+__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -+vqshrnd_n_s64 (int64x1_t __a, const int __b) -+{ -+ return (int32x1_t) __builtin_aarch64_sqshrn_ndi (__a, __b); -+} -+ -+__extension__ static __inline uint8x1_t __attribute__ ((__always_inline__)) -+vqshrnh_n_u16 (uint16x1_t __a, const int __b) -+{ -+ return (uint8x1_t) __builtin_aarch64_uqshrn_nhi (__a, __b); -+} -+ -+__extension__ static __inline uint16x1_t __attribute__ ((__always_inline__)) -+vqshrns_n_u32 (uint32x1_t __a, const int __b) -+{ -+ return (uint16x1_t) __builtin_aarch64_uqshrn_nsi (__a, __b); -+} -+ -+__extension__ static __inline uint32x1_t __attribute__ ((__always_inline__)) -+vqshrnd_n_u64 (uint64x1_t __a, const int __b) -+{ -+ return (uint32x1_t) __builtin_aarch64_uqshrn_ndi (__a, __b); -+} -+ -+/* vqshrun */ -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vqshrun_n_s16 (int16x8_t __a, const int __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_sqshrun_nv8hi (__a, __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vqshrun_n_s32 (int32x4_t __a, const int __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_sqshrun_nv4si (__a, __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vqshrun_n_s64 (int64x2_t __a, const int __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_sqshrun_nv2di (__a, __b); -+} -+ -+__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -+vqshrunh_n_s16 (int16x1_t __a, const int __b) -+{ -+ return (int8x1_t) __builtin_aarch64_sqshrun_nhi (__a, __b); -+} -+ -+__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -+vqshruns_n_s32 (int32x1_t __a, const int __b) -+{ -+ return (int16x1_t) __builtin_aarch64_sqshrun_nsi (__a, __b); -+} -+ -+__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -+vqshrund_n_s64 (int64x1_t __a, const int __b) -+{ -+ return (int32x1_t) __builtin_aarch64_sqshrun_ndi (__a, __b); -+} -+ -+/* vqsub */ -+ -+__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -+vqsubb_s8 (int8x1_t __a, int8x1_t __b) -+{ -+ return (int8x1_t) __builtin_aarch64_sqsubqi (__a, __b); -+} -+ -+__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -+vqsubh_s16 (int16x1_t __a, int16x1_t __b) -+{ -+ return (int16x1_t) __builtin_aarch64_sqsubhi (__a, __b); -+} -+ -+__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -+vqsubs_s32 (int32x1_t __a, int32x1_t __b) -+{ -+ return (int32x1_t) __builtin_aarch64_sqsubsi (__a, __b); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vqsubd_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return (int64x1_t) __builtin_aarch64_sqsubdi (__a, __b); -+} -+ -+__extension__ static __inline uint8x1_t __attribute__ ((__always_inline__)) -+vqsubb_u8 (uint8x1_t __a, uint8x1_t __b) -+{ -+ return (uint8x1_t) __builtin_aarch64_uqsubqi (__a, __b); -+} -+ -+__extension__ static __inline uint16x1_t __attribute__ ((__always_inline__)) -+vqsubh_u16 (uint16x1_t __a, uint16x1_t __b) -+{ -+ return (uint16x1_t) __builtin_aarch64_uqsubhi (__a, __b); -+} -+ -+__extension__ static __inline uint32x1_t __attribute__ ((__always_inline__)) -+vqsubs_u32 (uint32x1_t __a, uint32x1_t __b) -+{ -+ return (uint32x1_t) __builtin_aarch64_uqsubsi (__a, __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vqsubd_u64 (uint64x1_t __a, uint64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_uqsubdi (__a, __b); -+} -+ -+/* vrshl */ -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vrshl_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return (int8x8_t) __builtin_aarch64_srshlv8qi (__a, __b); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vrshl_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return (int16x4_t) __builtin_aarch64_srshlv4hi (__a, __b); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vrshl_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return (int32x2_t) __builtin_aarch64_srshlv2si (__a, __b); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vrshl_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return (int64x1_t) __builtin_aarch64_srshldi (__a, __b); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vrshl_u8 (uint8x8_t __a, int8x8_t __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_urshlv8qi ((int8x8_t) __a, __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vrshl_u16 (uint16x4_t __a, int16x4_t __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_urshlv4hi ((int16x4_t) __a, __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vrshl_u32 (uint32x2_t __a, int32x2_t __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_urshlv2si ((int32x2_t) __a, __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vrshl_u64 (uint64x1_t __a, int64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_urshldi ((int64x1_t) __a, __b); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vrshlq_s8 (int8x16_t __a, int8x16_t __b) -+{ -+ return (int8x16_t) __builtin_aarch64_srshlv16qi (__a, __b); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vrshlq_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return (int16x8_t) __builtin_aarch64_srshlv8hi (__a, __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vrshlq_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return (int32x4_t) __builtin_aarch64_srshlv4si (__a, __b); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vrshlq_s64 (int64x2_t __a, int64x2_t __b) -+{ -+ return (int64x2_t) __builtin_aarch64_srshlv2di (__a, __b); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vrshlq_u8 (uint8x16_t __a, int8x16_t __b) -+{ -+ return (uint8x16_t) __builtin_aarch64_urshlv16qi ((int8x16_t) __a, __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vrshlq_u16 (uint16x8_t __a, int16x8_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_urshlv8hi ((int16x8_t) __a, __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vrshlq_u32 (uint32x4_t __a, int32x4_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_urshlv4si ((int32x4_t) __a, __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vrshlq_u64 (uint64x2_t __a, int64x2_t __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_urshlv2di ((int64x2_t) __a, __b); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vrshld_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return (int64x1_t) __builtin_aarch64_srshldi (__a, __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vrshld_u64 (uint64x1_t __a, uint64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_urshldi (__a, __b); -+} -+ -+/* vrshr */ -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vrshr_n_s8 (int8x8_t __a, const int __b) -+{ -+ return (int8x8_t) __builtin_aarch64_srshr_nv8qi (__a, __b); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vrshr_n_s16 (int16x4_t __a, const int __b) -+{ -+ return (int16x4_t) __builtin_aarch64_srshr_nv4hi (__a, __b); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vrshr_n_s32 (int32x2_t __a, const int __b) -+{ -+ return (int32x2_t) __builtin_aarch64_srshr_nv2si (__a, __b); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vrshr_n_s64 (int64x1_t __a, const int __b) -+{ -+ return (int64x1_t) __builtin_aarch64_srshr_ndi (__a, __b); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vrshr_n_u8 (uint8x8_t __a, const int __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_urshr_nv8qi ((int8x8_t) __a, __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vrshr_n_u16 (uint16x4_t __a, const int __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_urshr_nv4hi ((int16x4_t) __a, __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vrshr_n_u32 (uint32x2_t __a, const int __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_urshr_nv2si ((int32x2_t) __a, __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vrshr_n_u64 (uint64x1_t __a, const int __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_urshr_ndi ((int64x1_t) __a, __b); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vrshrq_n_s8 (int8x16_t __a, const int __b) -+{ -+ return (int8x16_t) __builtin_aarch64_srshr_nv16qi (__a, __b); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vrshrq_n_s16 (int16x8_t __a, const int __b) -+{ -+ return (int16x8_t) __builtin_aarch64_srshr_nv8hi (__a, __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vrshrq_n_s32 (int32x4_t __a, const int __b) -+{ -+ return (int32x4_t) __builtin_aarch64_srshr_nv4si (__a, __b); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vrshrq_n_s64 (int64x2_t __a, const int __b) -+{ -+ return (int64x2_t) __builtin_aarch64_srshr_nv2di (__a, __b); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vrshrq_n_u8 (uint8x16_t __a, const int __b) -+{ -+ return (uint8x16_t) __builtin_aarch64_urshr_nv16qi ((int8x16_t) __a, __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vrshrq_n_u16 (uint16x8_t __a, const int __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_urshr_nv8hi ((int16x8_t) __a, __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vrshrq_n_u32 (uint32x4_t __a, const int __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_urshr_nv4si ((int32x4_t) __a, __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vrshrq_n_u64 (uint64x2_t __a, const int __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_urshr_nv2di ((int64x2_t) __a, __b); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vrshrd_n_s64 (int64x1_t __a, const int __b) -+{ -+ return (int64x1_t) __builtin_aarch64_srshr_ndi (__a, __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vrshrd_n_u64 (uint64x1_t __a, const int __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_urshr_ndi (__a, __b); -+} -+ -+/* vrsra */ -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vrsra_n_s8 (int8x8_t __a, int8x8_t __b, const int __c) -+{ -+ return (int8x8_t) __builtin_aarch64_srsra_nv8qi (__a, __b, __c); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vrsra_n_s16 (int16x4_t __a, int16x4_t __b, const int __c) -+{ -+ return (int16x4_t) __builtin_aarch64_srsra_nv4hi (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vrsra_n_s32 (int32x2_t __a, int32x2_t __b, const int __c) -+{ -+ return (int32x2_t) __builtin_aarch64_srsra_nv2si (__a, __b, __c); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vrsra_n_s64 (int64x1_t __a, int64x1_t __b, const int __c) -+{ -+ return (int64x1_t) __builtin_aarch64_srsra_ndi (__a, __b, __c); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vrsra_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c) -+{ -+ return (uint8x8_t) __builtin_aarch64_ursra_nv8qi ((int8x8_t) __a, -+ (int8x8_t) __b, __c); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vrsra_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c) -+{ -+ return (uint16x4_t) __builtin_aarch64_ursra_nv4hi ((int16x4_t) __a, -+ (int16x4_t) __b, __c); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vrsra_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c) -+{ -+ return (uint32x2_t) __builtin_aarch64_ursra_nv2si ((int32x2_t) __a, -+ (int32x2_t) __b, __c); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vrsra_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c) -+{ -+ return (uint64x1_t) __builtin_aarch64_ursra_ndi ((int64x1_t) __a, -+ (int64x1_t) __b, __c); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vrsraq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c) -+{ -+ return (int8x16_t) __builtin_aarch64_srsra_nv16qi (__a, __b, __c); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vrsraq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c) -+{ -+ return (int16x8_t) __builtin_aarch64_srsra_nv8hi (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vrsraq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c) -+{ -+ return (int32x4_t) __builtin_aarch64_srsra_nv4si (__a, __b, __c); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vrsraq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c) -+{ -+ return (int64x2_t) __builtin_aarch64_srsra_nv2di (__a, __b, __c); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vrsraq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c) -+{ -+ return (uint8x16_t) __builtin_aarch64_ursra_nv16qi ((int8x16_t) __a, -+ (int8x16_t) __b, __c); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vrsraq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c) -+{ -+ return (uint16x8_t) __builtin_aarch64_ursra_nv8hi ((int16x8_t) __a, -+ (int16x8_t) __b, __c); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vrsraq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c) -+{ -+ return (uint32x4_t) __builtin_aarch64_ursra_nv4si ((int32x4_t) __a, -+ (int32x4_t) __b, __c); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vrsraq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c) -+{ -+ return (uint64x2_t) __builtin_aarch64_ursra_nv2di ((int64x2_t) __a, -+ (int64x2_t) __b, __c); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vrsrad_n_s64 (int64x1_t __a, int64x1_t __b, const int __c) -+{ -+ return (int64x1_t) __builtin_aarch64_srsra_ndi (__a, __b, __c); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vrsrad_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c) -+{ -+ return (uint64x1_t) __builtin_aarch64_ursra_ndi (__a, __b, __c); -+} -+ -+/* vshl */ -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vshl_n_s8 (int8x8_t __a, const int __b) -+{ -+ return (int8x8_t) __builtin_aarch64_sshl_nv8qi (__a, __b); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vshl_n_s16 (int16x4_t __a, const int __b) -+{ -+ return (int16x4_t) __builtin_aarch64_sshl_nv4hi (__a, __b); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vshl_n_s32 (int32x2_t __a, const int __b) -+{ -+ return (int32x2_t) __builtin_aarch64_sshl_nv2si (__a, __b); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vshl_n_s64 (int64x1_t __a, const int __b) -+{ -+ return (int64x1_t) __builtin_aarch64_sshl_ndi (__a, __b); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vshl_n_u8 (uint8x8_t __a, const int __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_ushl_nv8qi ((int8x8_t) __a, __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vshl_n_u16 (uint16x4_t __a, const int __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_ushl_nv4hi ((int16x4_t) __a, __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vshl_n_u32 (uint32x2_t __a, const int __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_ushl_nv2si ((int32x2_t) __a, __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vshl_n_u64 (uint64x1_t __a, const int __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_ushl_ndi ((int64x1_t) __a, __b); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vshlq_n_s8 (int8x16_t __a, const int __b) -+{ -+ return (int8x16_t) __builtin_aarch64_sshl_nv16qi (__a, __b); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vshlq_n_s16 (int16x8_t __a, const int __b) -+{ -+ return (int16x8_t) __builtin_aarch64_sshl_nv8hi (__a, __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vshlq_n_s32 (int32x4_t __a, const int __b) -+{ -+ return (int32x4_t) __builtin_aarch64_sshl_nv4si (__a, __b); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vshlq_n_s64 (int64x2_t __a, const int __b) -+{ -+ return (int64x2_t) __builtin_aarch64_sshl_nv2di (__a, __b); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vshlq_n_u8 (uint8x16_t __a, const int __b) -+{ -+ return (uint8x16_t) __builtin_aarch64_ushl_nv16qi ((int8x16_t) __a, __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vshlq_n_u16 (uint16x8_t __a, const int __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_ushl_nv8hi ((int16x8_t) __a, __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vshlq_n_u32 (uint32x4_t __a, const int __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_ushl_nv4si ((int32x4_t) __a, __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vshlq_n_u64 (uint64x2_t __a, const int __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_ushl_nv2di ((int64x2_t) __a, __b); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vshld_n_s64 (int64x1_t __a, const int __b) -+{ -+ return (int64x1_t) __builtin_aarch64_sshl_ndi (__a, __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vshld_n_u64 (uint64x1_t __a, const int __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_ushl_ndi (__a, __b); -+} -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vshl_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return (int8x8_t) __builtin_aarch64_sshlv8qi (__a, __b); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vshl_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return (int16x4_t) __builtin_aarch64_sshlv4hi (__a, __b); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vshl_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return (int32x2_t) __builtin_aarch64_sshlv2si (__a, __b); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vshl_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return (int64x1_t) __builtin_aarch64_sshldi (__a, __b); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vshl_u8 (uint8x8_t __a, int8x8_t __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_ushlv8qi ((int8x8_t) __a, __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vshl_u16 (uint16x4_t __a, int16x4_t __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_ushlv4hi ((int16x4_t) __a, __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vshl_u32 (uint32x2_t __a, int32x2_t __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_ushlv2si ((int32x2_t) __a, __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vshl_u64 (uint64x1_t __a, int64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_ushldi ((int64x1_t) __a, __b); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vshlq_s8 (int8x16_t __a, int8x16_t __b) -+{ -+ return (int8x16_t) __builtin_aarch64_sshlv16qi (__a, __b); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vshlq_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return (int16x8_t) __builtin_aarch64_sshlv8hi (__a, __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vshlq_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return (int32x4_t) __builtin_aarch64_sshlv4si (__a, __b); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vshlq_s64 (int64x2_t __a, int64x2_t __b) -+{ -+ return (int64x2_t) __builtin_aarch64_sshlv2di (__a, __b); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vshlq_u8 (uint8x16_t __a, int8x16_t __b) -+{ -+ return (uint8x16_t) __builtin_aarch64_ushlv16qi ((int8x16_t) __a, __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vshlq_u16 (uint16x8_t __a, int16x8_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_ushlv8hi ((int16x8_t) __a, __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vshlq_u32 (uint32x4_t __a, int32x4_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_ushlv4si ((int32x4_t) __a, __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vshlq_u64 (uint64x2_t __a, int64x2_t __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_ushlv2di ((int64x2_t) __a, __b); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vshld_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return (int64x1_t) __builtin_aarch64_sshldi (__a, __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vshld_u64 (uint64x1_t __a, uint64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_ushldi (__a, __b); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vshll_high_n_s8 (int8x16_t __a, const int __b) -+{ -+ return __builtin_aarch64_sshll2_nv16qi (__a, __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vshll_high_n_s16 (int16x8_t __a, const int __b) -+{ -+ return __builtin_aarch64_sshll2_nv8hi (__a, __b); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vshll_high_n_s32 (int32x4_t __a, const int __b) -+{ -+ return __builtin_aarch64_sshll2_nv4si (__a, __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vshll_high_n_u8 (uint8x16_t __a, const int __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_ushll2_nv16qi ((int8x16_t) __a, __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vshll_high_n_u16 (uint16x8_t __a, const int __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_ushll2_nv8hi ((int16x8_t) __a, __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vshll_high_n_u32 (uint32x4_t __a, const int __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_ushll2_nv4si ((int32x4_t) __a, __b); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vshll_n_s8 (int8x8_t __a, const int __b) -+{ -+ return __builtin_aarch64_sshll_nv8qi (__a, __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vshll_n_s16 (int16x4_t __a, const int __b) -+{ -+ return __builtin_aarch64_sshll_nv4hi (__a, __b); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vshll_n_s32 (int32x2_t __a, const int __b) -+{ -+ return __builtin_aarch64_sshll_nv2si (__a, __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vshll_n_u8 (uint8x8_t __a, const int __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_ushll_nv8qi ((int8x8_t) __a, __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vshll_n_u16 (uint16x4_t __a, const int __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_ushll_nv4hi ((int16x4_t) __a, __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vshll_n_u32 (uint32x2_t __a, const int __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_ushll_nv2si ((int32x2_t) __a, __b); -+} -+ -+/* vshr */ -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vshr_n_s8 (int8x8_t __a, const int __b) -+{ -+ return (int8x8_t) __builtin_aarch64_sshr_nv8qi (__a, __b); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vshr_n_s16 (int16x4_t __a, const int __b) -+{ -+ return (int16x4_t) __builtin_aarch64_sshr_nv4hi (__a, __b); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vshr_n_s32 (int32x2_t __a, const int __b) -+{ -+ return (int32x2_t) __builtin_aarch64_sshr_nv2si (__a, __b); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vshr_n_s64 (int64x1_t __a, const int __b) -+{ -+ return (int64x1_t) __builtin_aarch64_sshr_ndi (__a, __b); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vshr_n_u8 (uint8x8_t __a, const int __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_ushr_nv8qi ((int8x8_t) __a, __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vshr_n_u16 (uint16x4_t __a, const int __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_ushr_nv4hi ((int16x4_t) __a, __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vshr_n_u32 (uint32x2_t __a, const int __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_ushr_nv2si ((int32x2_t) __a, __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vshr_n_u64 (uint64x1_t __a, const int __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_ushr_ndi ((int64x1_t) __a, __b); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vshrq_n_s8 (int8x16_t __a, const int __b) -+{ -+ return (int8x16_t) __builtin_aarch64_sshr_nv16qi (__a, __b); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vshrq_n_s16 (int16x8_t __a, const int __b) -+{ -+ return (int16x8_t) __builtin_aarch64_sshr_nv8hi (__a, __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vshrq_n_s32 (int32x4_t __a, const int __b) -+{ -+ return (int32x4_t) __builtin_aarch64_sshr_nv4si (__a, __b); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vshrq_n_s64 (int64x2_t __a, const int __b) -+{ -+ return (int64x2_t) __builtin_aarch64_sshr_nv2di (__a, __b); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vshrq_n_u8 (uint8x16_t __a, const int __b) -+{ -+ return (uint8x16_t) __builtin_aarch64_ushr_nv16qi ((int8x16_t) __a, __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vshrq_n_u16 (uint16x8_t __a, const int __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_ushr_nv8hi ((int16x8_t) __a, __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vshrq_n_u32 (uint32x4_t __a, const int __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_ushr_nv4si ((int32x4_t) __a, __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vshrq_n_u64 (uint64x2_t __a, const int __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_ushr_nv2di ((int64x2_t) __a, __b); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vshrd_n_s64 (int64x1_t __a, const int __b) -+{ -+ return (int64x1_t) __builtin_aarch64_sshr_ndi (__a, __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vshrd_n_u64 (uint64x1_t __a, const int __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_ushr_ndi (__a, __b); -+} -+ -+/* vsli */ -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vsli_n_s8 (int8x8_t __a, int8x8_t __b, const int __c) -+{ -+ return (int8x8_t) __builtin_aarch64_ssli_nv8qi (__a, __b, __c); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vsli_n_s16 (int16x4_t __a, int16x4_t __b, const int __c) -+{ -+ return (int16x4_t) __builtin_aarch64_ssli_nv4hi (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vsli_n_s32 (int32x2_t __a, int32x2_t __b, const int __c) -+{ -+ return (int32x2_t) __builtin_aarch64_ssli_nv2si (__a, __b, __c); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vsli_n_s64 (int64x1_t __a, int64x1_t __b, const int __c) -+{ -+ return (int64x1_t) __builtin_aarch64_ssli_ndi (__a, __b, __c); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vsli_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c) -+{ -+ return (uint8x8_t) __builtin_aarch64_usli_nv8qi ((int8x8_t) __a, -+ (int8x8_t) __b, __c); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vsli_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c) -+{ -+ return (uint16x4_t) __builtin_aarch64_usli_nv4hi ((int16x4_t) __a, -+ (int16x4_t) __b, __c); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vsli_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c) -+{ -+ return (uint32x2_t) __builtin_aarch64_usli_nv2si ((int32x2_t) __a, -+ (int32x2_t) __b, __c); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vsli_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c) -+{ -+ return (uint64x1_t) __builtin_aarch64_usli_ndi ((int64x1_t) __a, -+ (int64x1_t) __b, __c); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vsliq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c) -+{ -+ return (int8x16_t) __builtin_aarch64_ssli_nv16qi (__a, __b, __c); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vsliq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c) -+{ -+ return (int16x8_t) __builtin_aarch64_ssli_nv8hi (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vsliq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c) -+{ -+ return (int32x4_t) __builtin_aarch64_ssli_nv4si (__a, __b, __c); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vsliq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c) -+{ -+ return (int64x2_t) __builtin_aarch64_ssli_nv2di (__a, __b, __c); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vsliq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c) -+{ -+ return (uint8x16_t) __builtin_aarch64_usli_nv16qi ((int8x16_t) __a, -+ (int8x16_t) __b, __c); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vsliq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c) -+{ -+ return (uint16x8_t) __builtin_aarch64_usli_nv8hi ((int16x8_t) __a, -+ (int16x8_t) __b, __c); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vsliq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c) -+{ -+ return (uint32x4_t) __builtin_aarch64_usli_nv4si ((int32x4_t) __a, -+ (int32x4_t) __b, __c); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vsliq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c) -+{ -+ return (uint64x2_t) __builtin_aarch64_usli_nv2di ((int64x2_t) __a, -+ (int64x2_t) __b, __c); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vslid_n_s64 (int64x1_t __a, int64x1_t __b, const int __c) -+{ -+ return (int64x1_t) __builtin_aarch64_ssli_ndi (__a, __b, __c); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vslid_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c) -+{ -+ return (uint64x1_t) __builtin_aarch64_usli_ndi (__a, __b, __c); -+} -+ -+/* vsqadd */ -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vsqadd_u8 (uint8x8_t __a, int8x8_t __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_usqaddv8qi ((int8x8_t) __a, -+ (int8x8_t) __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vsqadd_u16 (uint16x4_t __a, int16x4_t __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_usqaddv4hi ((int16x4_t) __a, -+ (int16x4_t) __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vsqadd_u32 (uint32x2_t __a, int32x2_t __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_usqaddv2si ((int32x2_t) __a, -+ (int32x2_t) __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vsqadd_u64 (uint64x1_t __a, int64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_usqadddi ((int64x1_t) __a, __b); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vsqaddq_u8 (uint8x16_t __a, int8x16_t __b) -+{ -+ return (uint8x16_t) __builtin_aarch64_usqaddv16qi ((int8x16_t) __a, -+ (int8x16_t) __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vsqaddq_u16 (uint16x8_t __a, int16x8_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_usqaddv8hi ((int16x8_t) __a, -+ (int16x8_t) __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vsqaddq_u32 (uint32x4_t __a, int32x4_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_usqaddv4si ((int32x4_t) __a, -+ (int32x4_t) __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vsqaddq_u64 (uint64x2_t __a, int64x2_t __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_usqaddv2di ((int64x2_t) __a, -+ (int64x2_t) __b); -+} -+ -+__extension__ static __inline uint8x1_t __attribute__ ((__always_inline__)) -+vsqaddb_u8 (uint8x1_t __a, int8x1_t __b) -+{ -+ return (uint8x1_t) __builtin_aarch64_usqaddqi ((int8x1_t) __a, __b); -+} -+ -+__extension__ static __inline uint16x1_t __attribute__ ((__always_inline__)) -+vsqaddh_u16 (uint16x1_t __a, int16x1_t __b) -+{ -+ return (uint16x1_t) __builtin_aarch64_usqaddhi ((int16x1_t) __a, __b); -+} -+ -+__extension__ static __inline uint32x1_t __attribute__ ((__always_inline__)) -+vsqadds_u32 (uint32x1_t __a, int32x1_t __b) -+{ -+ return (uint32x1_t) __builtin_aarch64_usqaddsi ((int32x1_t) __a, __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vsqaddd_u64 (uint64x1_t __a, int64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_usqadddi ((int64x1_t) __a, __b); -+} -+ -+/* vsqrt */ -+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -+vsqrt_f32 (float32x2_t a) -+{ -+ return __builtin_aarch64_sqrtv2sf (a); -+} -+ -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vsqrtq_f32 (float32x4_t a) -+{ -+ return __builtin_aarch64_sqrtv4sf (a); -+} -+ -+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -+vsqrtq_f64 (float64x2_t a) -+{ -+ return __builtin_aarch64_sqrtv2df (a); -+} -+ -+/* vsra */ -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vsra_n_s8 (int8x8_t __a, int8x8_t __b, const int __c) -+{ -+ return (int8x8_t) __builtin_aarch64_ssra_nv8qi (__a, __b, __c); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vsra_n_s16 (int16x4_t __a, int16x4_t __b, const int __c) -+{ -+ return (int16x4_t) __builtin_aarch64_ssra_nv4hi (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vsra_n_s32 (int32x2_t __a, int32x2_t __b, const int __c) -+{ -+ return (int32x2_t) __builtin_aarch64_ssra_nv2si (__a, __b, __c); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vsra_n_s64 (int64x1_t __a, int64x1_t __b, const int __c) -+{ -+ return (int64x1_t) __builtin_aarch64_ssra_ndi (__a, __b, __c); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vsra_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c) -+{ -+ return (uint8x8_t) __builtin_aarch64_usra_nv8qi ((int8x8_t) __a, -+ (int8x8_t) __b, __c); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vsra_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c) -+{ -+ return (uint16x4_t) __builtin_aarch64_usra_nv4hi ((int16x4_t) __a, -+ (int16x4_t) __b, __c); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vsra_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c) -+{ -+ return (uint32x2_t) __builtin_aarch64_usra_nv2si ((int32x2_t) __a, -+ (int32x2_t) __b, __c); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vsra_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c) -+{ -+ return (uint64x1_t) __builtin_aarch64_usra_ndi ((int64x1_t) __a, -+ (int64x1_t) __b, __c); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vsraq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c) -+{ -+ return (int8x16_t) __builtin_aarch64_ssra_nv16qi (__a, __b, __c); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vsraq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c) -+{ -+ return (int16x8_t) __builtin_aarch64_ssra_nv8hi (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vsraq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c) -+{ -+ return (int32x4_t) __builtin_aarch64_ssra_nv4si (__a, __b, __c); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vsraq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c) -+{ -+ return (int64x2_t) __builtin_aarch64_ssra_nv2di (__a, __b, __c); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vsraq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c) -+{ -+ return (uint8x16_t) __builtin_aarch64_usra_nv16qi ((int8x16_t) __a, -+ (int8x16_t) __b, __c); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vsraq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c) -+{ -+ return (uint16x8_t) __builtin_aarch64_usra_nv8hi ((int16x8_t) __a, -+ (int16x8_t) __b, __c); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vsraq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c) -+{ -+ return (uint32x4_t) __builtin_aarch64_usra_nv4si ((int32x4_t) __a, -+ (int32x4_t) __b, __c); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vsraq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c) -+{ -+ return (uint64x2_t) __builtin_aarch64_usra_nv2di ((int64x2_t) __a, -+ (int64x2_t) __b, __c); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vsrad_n_s64 (int64x1_t __a, int64x1_t __b, const int __c) -+{ -+ return (int64x1_t) __builtin_aarch64_ssra_ndi (__a, __b, __c); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vsrad_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c) -+{ -+ return (uint64x1_t) __builtin_aarch64_usra_ndi (__a, __b, __c); -+} -+ -+/* vsri */ -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vsri_n_s8 (int8x8_t __a, int8x8_t __b, const int __c) -+{ -+ return (int8x8_t) __builtin_aarch64_ssri_nv8qi (__a, __b, __c); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vsri_n_s16 (int16x4_t __a, int16x4_t __b, const int __c) -+{ -+ return (int16x4_t) __builtin_aarch64_ssri_nv4hi (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vsri_n_s32 (int32x2_t __a, int32x2_t __b, const int __c) -+{ -+ return (int32x2_t) __builtin_aarch64_ssri_nv2si (__a, __b, __c); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vsri_n_s64 (int64x1_t __a, int64x1_t __b, const int __c) -+{ -+ return (int64x1_t) __builtin_aarch64_ssri_ndi (__a, __b, __c); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vsri_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c) -+{ -+ return (uint8x8_t) __builtin_aarch64_usri_nv8qi ((int8x8_t) __a, -+ (int8x8_t) __b, __c); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vsri_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c) -+{ -+ return (uint16x4_t) __builtin_aarch64_usri_nv4hi ((int16x4_t) __a, -+ (int16x4_t) __b, __c); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vsri_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c) -+{ -+ return (uint32x2_t) __builtin_aarch64_usri_nv2si ((int32x2_t) __a, -+ (int32x2_t) __b, __c); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vsri_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c) -+{ -+ return (uint64x1_t) __builtin_aarch64_usri_ndi ((int64x1_t) __a, -+ (int64x1_t) __b, __c); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vsriq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c) -+{ -+ return (int8x16_t) __builtin_aarch64_ssri_nv16qi (__a, __b, __c); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vsriq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c) -+{ -+ return (int16x8_t) __builtin_aarch64_ssri_nv8hi (__a, __b, __c); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vsriq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c) -+{ -+ return (int32x4_t) __builtin_aarch64_ssri_nv4si (__a, __b, __c); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vsriq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c) -+{ -+ return (int64x2_t) __builtin_aarch64_ssri_nv2di (__a, __b, __c); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vsriq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c) -+{ -+ return (uint8x16_t) __builtin_aarch64_usri_nv16qi ((int8x16_t) __a, -+ (int8x16_t) __b, __c); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vsriq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c) -+{ -+ return (uint16x8_t) __builtin_aarch64_usri_nv8hi ((int16x8_t) __a, -+ (int16x8_t) __b, __c); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vsriq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c) -+{ -+ return (uint32x4_t) __builtin_aarch64_usri_nv4si ((int32x4_t) __a, -+ (int32x4_t) __b, __c); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vsriq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c) -+{ -+ return (uint64x2_t) __builtin_aarch64_usri_nv2di ((int64x2_t) __a, -+ (int64x2_t) __b, __c); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vsrid_n_s64 (int64x1_t __a, int64x1_t __b, const int __c) -+{ -+ return (int64x1_t) __builtin_aarch64_ssri_ndi (__a, __b, __c); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vsrid_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c) -+{ -+ return (uint64x1_t) __builtin_aarch64_usri_ndi (__a, __b, __c); -+} -+ -+/* vsub */ -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vsubd_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return __a - __b; -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vsubd_u64 (uint64x1_t __a, uint64x1_t __b) -+{ -+ return __a - __b; -+} -+ -+/* vtrn */ -+ -+__extension__ static __inline float32x2x2_t __attribute__ ((__always_inline__)) -+vtrn_f32 (float32x2_t a, float32x2_t b) -+{ -+ return (float32x2x2_t) {vtrn1_f32 (a, b), vtrn2_f32 (a, b)}; -+} -+ -+__extension__ static __inline poly8x8x2_t __attribute__ ((__always_inline__)) -+vtrn_p8 (poly8x8_t a, poly8x8_t b) -+{ -+ return (poly8x8x2_t) {vtrn1_p8 (a, b), vtrn2_p8 (a, b)}; -+} -+ -+__extension__ static __inline poly16x4x2_t __attribute__ ((__always_inline__)) -+vtrn_p16 (poly16x4_t a, poly16x4_t b) -+{ -+ return (poly16x4x2_t) {vtrn1_p16 (a, b), vtrn2_p16 (a, b)}; -+} -+ -+__extension__ static __inline int8x8x2_t __attribute__ ((__always_inline__)) -+vtrn_s8 (int8x8_t a, int8x8_t b) -+{ -+ return (int8x8x2_t) {vtrn1_s8 (a, b), vtrn2_s8 (a, b)}; -+} -+ -+__extension__ static __inline int16x4x2_t __attribute__ ((__always_inline__)) -+vtrn_s16 (int16x4_t a, int16x4_t b) -+{ -+ return (int16x4x2_t) {vtrn1_s16 (a, b), vtrn2_s16 (a, b)}; -+} -+ -+__extension__ static __inline int32x2x2_t __attribute__ ((__always_inline__)) -+vtrn_s32 (int32x2_t a, int32x2_t b) -+{ -+ return (int32x2x2_t) {vtrn1_s32 (a, b), vtrn2_s32 (a, b)}; -+} -+ -+__extension__ static __inline uint8x8x2_t __attribute__ ((__always_inline__)) -+vtrn_u8 (uint8x8_t a, uint8x8_t b) -+{ -+ return (uint8x8x2_t) {vtrn1_u8 (a, b), vtrn2_u8 (a, b)}; -+} -+ -+__extension__ static __inline uint16x4x2_t __attribute__ ((__always_inline__)) -+vtrn_u16 (uint16x4_t a, uint16x4_t b) -+{ -+ return (uint16x4x2_t) {vtrn1_u16 (a, b), vtrn2_u16 (a, b)}; -+} -+ -+__extension__ static __inline uint32x2x2_t __attribute__ ((__always_inline__)) -+vtrn_u32 (uint32x2_t a, uint32x2_t b) -+{ -+ return (uint32x2x2_t) {vtrn1_u32 (a, b), vtrn2_u32 (a, b)}; -+} -+ -+__extension__ static __inline float32x4x2_t __attribute__ ((__always_inline__)) -+vtrnq_f32 (float32x4_t a, float32x4_t b) -+{ -+ return (float32x4x2_t) {vtrn1q_f32 (a, b), vtrn2q_f32 (a, b)}; -+} -+ -+__extension__ static __inline poly8x16x2_t __attribute__ ((__always_inline__)) -+vtrnq_p8 (poly8x16_t a, poly8x16_t b) -+{ -+ return (poly8x16x2_t) {vtrn1q_p8 (a, b), vtrn2q_p8 (a, b)}; -+} -+ -+__extension__ static __inline poly16x8x2_t __attribute__ ((__always_inline__)) -+vtrnq_p16 (poly16x8_t a, poly16x8_t b) -+{ -+ return (poly16x8x2_t) {vtrn1q_p16 (a, b), vtrn2q_p16 (a, b)}; -+} -+ -+__extension__ static __inline int8x16x2_t __attribute__ ((__always_inline__)) -+vtrnq_s8 (int8x16_t a, int8x16_t b) -+{ -+ return (int8x16x2_t) {vtrn1q_s8 (a, b), vtrn2q_s8 (a, b)}; -+} -+ -+__extension__ static __inline int16x8x2_t __attribute__ ((__always_inline__)) -+vtrnq_s16 (int16x8_t a, int16x8_t b) -+{ -+ return (int16x8x2_t) {vtrn1q_s16 (a, b), vtrn2q_s16 (a, b)}; -+} -+ -+__extension__ static __inline int32x4x2_t __attribute__ ((__always_inline__)) -+vtrnq_s32 (int32x4_t a, int32x4_t b) -+{ -+ return (int32x4x2_t) {vtrn1q_s32 (a, b), vtrn2q_s32 (a, b)}; -+} -+ -+__extension__ static __inline uint8x16x2_t __attribute__ ((__always_inline__)) -+vtrnq_u8 (uint8x16_t a, uint8x16_t b) -+{ -+ return (uint8x16x2_t) {vtrn1q_u8 (a, b), vtrn2q_u8 (a, b)}; -+} -+ -+__extension__ static __inline uint16x8x2_t __attribute__ ((__always_inline__)) -+vtrnq_u16 (uint16x8_t a, uint16x8_t b) -+{ -+ return (uint16x8x2_t) {vtrn1q_u16 (a, b), vtrn2q_u16 (a, b)}; -+} -+ -+__extension__ static __inline uint32x4x2_t __attribute__ ((__always_inline__)) -+vtrnq_u32 (uint32x4_t a, uint32x4_t b) -+{ -+ return (uint32x4x2_t) {vtrn1q_u32 (a, b), vtrn2q_u32 (a, b)}; -+} -+ -+/* vtst */ -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vtst_s8 (int8x8_t __a, int8x8_t __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_cmtstv8qi (__a, __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vtst_s16 (int16x4_t __a, int16x4_t __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_cmtstv4hi (__a, __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vtst_s32 (int32x2_t __a, int32x2_t __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_cmtstv2si (__a, __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vtst_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_cmtstdi (__a, __b); -+} -+ -+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -+vtst_u8 (uint8x8_t __a, uint8x8_t __b) -+{ -+ return (uint8x8_t) __builtin_aarch64_cmtstv8qi ((int8x8_t) __a, -+ (int8x8_t) __b); -+} -+ -+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -+vtst_u16 (uint16x4_t __a, uint16x4_t __b) -+{ -+ return (uint16x4_t) __builtin_aarch64_cmtstv4hi ((int16x4_t) __a, -+ (int16x4_t) __b); -+} -+ -+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -+vtst_u32 (uint32x2_t __a, uint32x2_t __b) -+{ -+ return (uint32x2_t) __builtin_aarch64_cmtstv2si ((int32x2_t) __a, -+ (int32x2_t) __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vtst_u64 (uint64x1_t __a, uint64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_cmtstdi ((int64x1_t) __a, -+ (int64x1_t) __b); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vtstq_s8 (int8x16_t __a, int8x16_t __b) -+{ -+ return (uint8x16_t) __builtin_aarch64_cmtstv16qi (__a, __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vtstq_s16 (int16x8_t __a, int16x8_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_cmtstv8hi (__a, __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vtstq_s32 (int32x4_t __a, int32x4_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_cmtstv4si (__a, __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vtstq_s64 (int64x2_t __a, int64x2_t __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_cmtstv2di (__a, __b); -+} -+ -+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -+vtstq_u8 (uint8x16_t __a, uint8x16_t __b) -+{ -+ return (uint8x16_t) __builtin_aarch64_cmtstv16qi ((int8x16_t) __a, -+ (int8x16_t) __b); -+} -+ -+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -+vtstq_u16 (uint16x8_t __a, uint16x8_t __b) -+{ -+ return (uint16x8_t) __builtin_aarch64_cmtstv8hi ((int16x8_t) __a, -+ (int16x8_t) __b); -+} -+ -+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -+vtstq_u32 (uint32x4_t __a, uint32x4_t __b) -+{ -+ return (uint32x4_t) __builtin_aarch64_cmtstv4si ((int32x4_t) __a, -+ (int32x4_t) __b); -+} -+ -+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -+vtstq_u64 (uint64x2_t __a, uint64x2_t __b) -+{ -+ return (uint64x2_t) __builtin_aarch64_cmtstv2di ((int64x2_t) __a, -+ (int64x2_t) __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vtstd_s64 (int64x1_t __a, int64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_cmtstdi (__a, __b); -+} -+ -+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -+vtstd_u64 (uint64x1_t __a, uint64x1_t __b) -+{ -+ return (uint64x1_t) __builtin_aarch64_cmtstdi ((int64x1_t) __a, -+ (int64x1_t) __b); -+} -+ -+/* vuqadd */ -+ -+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -+vuqadd_s8 (int8x8_t __a, uint8x8_t __b) -+{ -+ return (int8x8_t) __builtin_aarch64_suqaddv8qi (__a, (int8x8_t) __b); -+} -+ -+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -+vuqadd_s16 (int16x4_t __a, uint16x4_t __b) -+{ -+ return (int16x4_t) __builtin_aarch64_suqaddv4hi (__a, (int16x4_t) __b); -+} -+ -+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -+vuqadd_s32 (int32x2_t __a, uint32x2_t __b) -+{ -+ return (int32x2_t) __builtin_aarch64_suqaddv2si (__a, (int32x2_t) __b); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vuqadd_s64 (int64x1_t __a, uint64x1_t __b) -+{ -+ return (int64x1_t) __builtin_aarch64_suqadddi (__a, (int64x1_t) __b); -+} -+ -+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -+vuqaddq_s8 (int8x16_t __a, uint8x16_t __b) -+{ -+ return (int8x16_t) __builtin_aarch64_suqaddv16qi (__a, (int8x16_t) __b); -+} -+ -+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -+vuqaddq_s16 (int16x8_t __a, uint16x8_t __b) -+{ -+ return (int16x8_t) __builtin_aarch64_suqaddv8hi (__a, (int16x8_t) __b); -+} -+ -+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -+vuqaddq_s32 (int32x4_t __a, uint32x4_t __b) -+{ -+ return (int32x4_t) __builtin_aarch64_suqaddv4si (__a, (int32x4_t) __b); -+} -+ -+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -+vuqaddq_s64 (int64x2_t __a, uint64x2_t __b) -+{ -+ return (int64x2_t) __builtin_aarch64_suqaddv2di (__a, (int64x2_t) __b); -+} -+ -+__extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) -+vuqaddb_s8 (int8x1_t __a, uint8x1_t __b) -+{ -+ return (int8x1_t) __builtin_aarch64_suqaddqi (__a, (int8x1_t) __b); -+} -+ -+__extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) -+vuqaddh_s16 (int16x1_t __a, uint16x1_t __b) -+{ -+ return (int16x1_t) __builtin_aarch64_suqaddhi (__a, (int16x1_t) __b); -+} -+ -+__extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) -+vuqadds_s32 (int32x1_t __a, uint32x1_t __b) -+{ -+ return (int32x1_t) __builtin_aarch64_suqaddsi (__a, (int32x1_t) __b); -+} -+ -+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -+vuqaddd_s64 (int64x1_t __a, uint64x1_t __b) -+{ -+ return (int64x1_t) __builtin_aarch64_suqadddi (__a, (int64x1_t) __b); -+} -+ -+#define __DEFINTERLEAVE(op, rettype, intype, funcsuffix, Q) \ -+ __extension__ static __inline rettype \ -+ __attribute__ ((__always_inline__)) \ -+ v ## op ## Q ## _ ## funcsuffix (intype a, intype b) \ -+ { \ -+ return (rettype) {v ## op ## 1 ## Q ## _ ## funcsuffix (a, b), \ -+ v ## op ## 2 ## Q ## _ ## funcsuffix (a, b)}; \ -+ } -+ -+#define __INTERLEAVE_LIST(op) \ -+ __DEFINTERLEAVE (op, float32x2x2_t, float32x2_t, f32,) \ -+ __DEFINTERLEAVE (op, poly8x8x2_t, poly8x8_t, p8,) \ -+ __DEFINTERLEAVE (op, poly16x4x2_t, poly16x4_t, p16,) \ -+ __DEFINTERLEAVE (op, int8x8x2_t, int8x8_t, s8,) \ -+ __DEFINTERLEAVE (op, int16x4x2_t, int16x4_t, s16,) \ -+ __DEFINTERLEAVE (op, int32x2x2_t, int32x2_t, s32,) \ -+ __DEFINTERLEAVE (op, uint8x8x2_t, uint8x8_t, u8,) \ -+ __DEFINTERLEAVE (op, uint16x4x2_t, uint16x4_t, u16,) \ -+ __DEFINTERLEAVE (op, uint32x2x2_t, uint32x2_t, u32,) \ -+ __DEFINTERLEAVE (op, float32x4x2_t, float32x4_t, f32, q) \ -+ __DEFINTERLEAVE (op, poly8x16x2_t, poly8x16_t, p8, q) \ -+ __DEFINTERLEAVE (op, poly16x8x2_t, poly16x8_t, p16, q) \ -+ __DEFINTERLEAVE (op, int8x16x2_t, int8x16_t, s8, q) \ -+ __DEFINTERLEAVE (op, int16x8x2_t, int16x8_t, s16, q) \ -+ __DEFINTERLEAVE (op, int32x4x2_t, int32x4_t, s32, q) \ -+ __DEFINTERLEAVE (op, uint8x16x2_t, uint8x16_t, u8, q) \ -+ __DEFINTERLEAVE (op, uint16x8x2_t, uint16x8_t, u16, q) \ -+ __DEFINTERLEAVE (op, uint32x4x2_t, uint32x4_t, u32, q) -+ -+/* vuzp */ -+ -+__INTERLEAVE_LIST (uzp) -+ -+/* vzip */ -+ -+__INTERLEAVE_LIST (zip) -+ -+#undef __INTERLEAVE_LIST -+#undef __DEFINTERLEAVE -+ -+/* End of optimal implementations in approved order. */ -+ -+#endif - -Property changes on: gcc/config/aarch64/arm_neon.h -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/config/aarch64/t-aarch64-linux -=================================================================== ---- a/src/gcc/config/aarch64/t-aarch64-linux (.../gcc-4_7-branch) -+++ b/src/gcc/config/aarch64/t-aarch64-linux (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,22 @@ -+# Machine description for AArch64 architecture. -+# Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. -+# Contributed by ARM Ltd. -+# -+# This file is part of GCC. -+# -+# GCC is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License as published by -+# the Free Software Foundation; either version 3, or (at your option) -+# any later version. -+# -+# GCC is distributed in the hope that it will be useful, but -+# WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+# General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with GCC; see the file COPYING3. If not see -+# . -+ -+LIB1ASMSRC = aarch64/lib1funcs.asm -+LIB1ASMFUNCS = _aarch64_sync_cache_range -Index: gcc/config/aarch64/aarch64.md -=================================================================== ---- a/src/gcc/config/aarch64/aarch64.md (.../gcc-4_7-branch) -+++ b/src/gcc/config/aarch64/aarch64.md (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,2994 @@ -+;; Machine description for AArch64 architecture. -+;; Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. -+;; Contributed by ARM Ltd. -+;; -+;; This file is part of GCC. -+;; -+;; GCC is free software; you can redistribute it and/or modify it -+;; under the terms of the GNU General Public License as published by -+;; the Free Software Foundation; either version 3, or (at your option) -+;; any later version. -+;; -+;; GCC is distributed in the hope that it will be useful, but -+;; WITHOUT ANY WARRANTY; without even the implied warranty of -+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+;; General Public License for more details. -+;; -+;; You should have received a copy of the GNU General Public License -+;; along with GCC; see the file COPYING3. If not see -+;; . -+ -+;; Register numbers -+(define_constants -+ [ -+ (R0_REGNUM 0) -+ (R1_REGNUM 1) -+ (R2_REGNUM 2) -+ (R3_REGNUM 3) -+ (R4_REGNUM 4) -+ (R5_REGNUM 5) -+ (R6_REGNUM 6) -+ (R7_REGNUM 7) -+ (R8_REGNUM 8) -+ (R9_REGNUM 9) -+ (R10_REGNUM 10) -+ (R11_REGNUM 11) -+ (R12_REGNUM 12) -+ (R13_REGNUM 13) -+ (R14_REGNUM 14) -+ (R15_REGNUM 15) -+ (R16_REGNUM 16) -+ (IP0_REGNUM 16) -+ (R17_REGNUM 17) -+ (IP1_REGNUM 17) -+ (R18_REGNUM 18) -+ (R19_REGNUM 19) -+ (R20_REGNUM 20) -+ (R21_REGNUM 21) -+ (R22_REGNUM 22) -+ (R23_REGNUM 23) -+ (R24_REGNUM 24) -+ (R25_REGNUM 25) -+ (R26_REGNUM 26) -+ (R27_REGNUM 27) -+ (R28_REGNUM 28) -+ (R29_REGNUM 29) -+ (R30_REGNUM 30) -+ (LR_REGNUM 30) -+ (SP_REGNUM 31) -+ (V0_REGNUM 32) -+ (V15_REGNUM 47) -+ (V31_REGNUM 63) -+ (SFP_REGNUM 64) -+ (AP_REGNUM 65) -+ (CC_REGNUM 66) -+ ] -+) -+ -+(define_constants -+ [ -+ (UNSPEC_NOP 0) -+ (UNSPEC_TLS 1) -+ (UNSPEC_CASESI 2) -+ (UNSPEC_GOTSMALLPIC 3) -+ (UNSPEC_GOTSMALLTLS 4) -+ (UNSPEC_PRLG_STK 5) -+ (UNSPEC_MB 6) -+ (UNSPEC_ASHIFT_SIGNED 7) ; Used in aarch64-simd.md. -+ (UNSPEC_ASHIFT_UNSIGNED 8) ; Used in aarch64-simd.md. -+ (UNSPEC_FRINTZ 9) -+ (UNSPEC_FRINTP 10) -+ (UNSPEC_FRINTM 11) -+ (UNSPEC_FRINTA 12) -+ (UNSPEC_FRINTI 13) -+ (UNSPEC_TLSDESC 14) -+ (UNSPEC_FRINTX 15) -+ (UNSPEC_FMAXV 16) ; Used in aarch64-simd.md. -+ (UNSPEC_FMINV 17) ; Used in aarch64-simd.md. -+ (UNSPEC_FADDV 18) ; Used in aarch64-simd.md. -+ (UNSPEC_ADDV 19) ; Used in aarch64-simd.md. -+ (UNSPEC_SMAXV 20) ; Used in aarch64-simd.md. -+ (UNSPEC_SMINV 21) ; Used in aarch64-simd.md. -+ (UNSPEC_UMAXV 22) ; Used in aarch64-simd.md. -+ (UNSPEC_UMINV 23) ; Used in aarch64-simd.md. -+ (UNSPEC_SHADD 24) ; Used in aarch64-simd.md. -+ (UNSPEC_UHADD 25) ; Used in aarch64-simd.md. -+ (UNSPEC_SRHADD 26) ; Used in aarch64-simd.md. -+ (UNSPEC_URHADD 27) ; Used in aarch64-simd.md. -+ (UNSPEC_SHSUB 28) ; Used in aarch64-simd.md. -+ (UNSPEC_UHSUB 29) ; Used in aarch64-simd.md. -+ (UNSPEC_SRHSUB 30) ; Used in aarch64-simd.md. -+ (UNSPEC_URHSUB 31) ; Used in aarch64-simd.md. -+ (UNSPEC_ADDHN 32) ; Used in aarch64-simd.md. -+ (UNSPEC_RADDHN 33) ; Used in aarch64-simd.md. -+ (UNSPEC_SUBHN 34) ; Used in aarch64-simd.md. -+ (UNSPEC_RSUBHN 35) ; Used in aarch64-simd.md. -+ (UNSPEC_ADDHN2 36) ; Used in aarch64-simd.md. -+ (UNSPEC_RADDHN2 37) ; Used in aarch64-simd.md. -+ (UNSPEC_SUBHN2 38) ; Used in aarch64-simd.md. -+ (UNSPEC_RSUBHN2 39) ; Used in aarch64-simd.md. -+ (UNSPEC_SQDMULH 40) ; Used in aarch64-simd.md. -+ (UNSPEC_SQRDMULH 41) ; Used in aarch64-simd.md. -+ (UNSPEC_PMUL 42) ; Used in aarch64-simd.md. -+ (UNSPEC_USQADD 43) ; Used in aarch64-simd.md. -+ (UNSPEC_SUQADD 44) ; Used in aarch64-simd.md. -+ (UNSPEC_SQXTUN 45) ; Used in aarch64-simd.md. -+ (UNSPEC_SQXTN 46) ; Used in aarch64-simd.md. -+ (UNSPEC_UQXTN 47) ; Used in aarch64-simd.md. -+ (UNSPEC_SSRA 48) ; Used in aarch64-simd.md. -+ (UNSPEC_USRA 49) ; Used in aarch64-simd.md. -+ (UNSPEC_SRSRA 50) ; Used in aarch64-simd.md. -+ (UNSPEC_URSRA 51) ; Used in aarch64-simd.md. -+ (UNSPEC_SRSHR 52) ; Used in aarch64-simd.md. -+ (UNSPEC_URSHR 53) ; Used in aarch64-simd.md. -+ (UNSPEC_SQSHLU 54) ; Used in aarch64-simd.md. -+ (UNSPEC_SQSHL 55) ; Used in aarch64-simd.md. -+ (UNSPEC_UQSHL 56) ; Used in aarch64-simd.md. -+ (UNSPEC_SQSHRUN 57) ; Used in aarch64-simd.md. -+ (UNSPEC_SQRSHRUN 58) ; Used in aarch64-simd.md. -+ (UNSPEC_SQSHRN 59) ; Used in aarch64-simd.md. -+ (UNSPEC_UQSHRN 60) ; Used in aarch64-simd.md. -+ (UNSPEC_SQRSHRN 61) ; Used in aarch64-simd.md. -+ (UNSPEC_UQRSHRN 62) ; Used in aarch64-simd.md. -+ (UNSPEC_SSHL 63) ; Used in aarch64-simd.md. -+ (UNSPEC_USHL 64) ; Used in aarch64-simd.md. -+ (UNSPEC_SRSHL 65) ; Used in aarch64-simd.md. -+ (UNSPEC_URSHL 66) ; Used in aarch64-simd.md. -+ (UNSPEC_SQRSHL 67) ; Used in aarch64-simd.md. -+ (UNSPEC_UQRSHL 68) ; Used in aarch64-simd.md. -+ (UNSPEC_CMEQ 69) ; Used in aarch64-simd.md. -+ (UNSPEC_CMLE 70) ; Used in aarch64-simd.md. -+ (UNSPEC_CMLT 71) ; Used in aarch64-simd.md. -+ (UNSPEC_CMGE 72) ; Used in aarch64-simd.md. -+ (UNSPEC_CMGT 73) ; Used in aarch64-simd.md. -+ (UNSPEC_CMHS 74) ; Used in aarch64-simd.md. -+ (UNSPEC_CMHI 75) ; Used in aarch64-simd.md. -+ (UNSPEC_SSLI 76) ; Used in aarch64-simd.md. -+ (UNSPEC_USLI 77) ; Used in aarch64-simd.md. -+ (UNSPEC_SSRI 78) ; Used in aarch64-simd.md. -+ (UNSPEC_USRI 79) ; Used in aarch64-simd.md. -+ (UNSPEC_SSHLL 80) ; Used in aarch64-simd.md. -+ (UNSPEC_USHLL 81) ; Used in aarch64-simd.md. -+ (UNSPEC_ADDP 82) ; Used in aarch64-simd.md. -+ (UNSPEC_CMTST 83) ; Used in aarch64-simd.md. -+ (UNSPEC_FMAX 83) ; Used in aarch64-simd.md. -+ (UNSPEC_FMIN 84) ; Used in aarch64-simd.md. -+ (UNSPEC_CLS 85) ; Used in aarch64.md. -+ (UNSPEC_RBIT 86) ; Used in aarch64.md. -+ ] -+) -+ -+(define_constants -+ [ -+ (UNSPECV_EH_RETURN 0) -+ (UNSPECV_SYNC_COMPARE_AND_SWAP 1) ; Represent a sync_compare_and_swap. -+ (UNSPECV_SYNC_LOCK 2) ; Represent a sync_lock_test_and_set. -+ (UNSPECV_SYNC_LOCK_RELEASE 3) ; Represent a sync_lock_release. -+ (UNSPECV_SYNC_OP 4) ; Represent a sync_ -+ (UNSPECV_SYNC_NEW_OP 5) ; Represent a sync_new_ -+ (UNSPECV_SYNC_OLD_OP 6) ; Represent a sync_old_ -+ ] -+) -+ -+;; If further include files are added the defintion of MD_INCLUDES -+;; must be updated. -+ -+(include "constraints.md") -+(include "predicates.md") -+(include "iterators.md") -+ -+;; ------------------------------------------------------------------- -+;; Synchronization Builtins -+;; ------------------------------------------------------------------- -+ -+;; The following sync_* attributes are applied to sychronization -+;; instruction patterns to control the way in which the -+;; synchronization loop is expanded. -+;; All instruction patterns that call aarch64_output_sync_insn () -+;; should define these attributes. Refer to the comment above -+;; aarch64.c:aarch64_output_sync_loop () for more detail on the use of -+;; these attributes. -+ -+;; Attribute specifies the operand number which contains the -+;; result of a synchronization operation. The result is the old value -+;; loaded from SYNC_MEMORY. -+(define_attr "sync_result" "none,0,1,2,3,4,5" (const_string "none")) -+ -+;; Attribute specifies the operand number which contains the memory -+;; address to which the synchronization operation is being applied. -+(define_attr "sync_memory" "none,0,1,2,3,4,5" (const_string "none")) -+ -+;; Attribute specifies the operand number which contains the required -+;; old value expected in the memory location. This attribute may be -+;; none if no required value test should be performed in the expanded -+;; code. -+(define_attr "sync_required_value" "none,0,1,2,3,4,5" (const_string "none")) -+ -+;; Attribute specifies the operand number of the new value to be stored -+;; into the memory location identitifed by the sync_memory attribute. -+(define_attr "sync_new_value" "none,0,1,2,3,4,5" (const_string "none")) -+ -+;; Attribute specifies the operand number of a temporary register -+;; which can be clobbered by the synchronization instruction sequence. -+;; The register provided byn SYNC_T1 may be the same as SYNC_RESULT is -+;; which case the result value will be clobbered and not available -+;; after the synchronization loop exits. -+(define_attr "sync_t1" "none,0,1,2,3,4,5" (const_string "none")) -+ -+;; Attribute specifies the operand number of a temporary register -+;; which can be clobbered by the synchronization instruction sequence. -+;; This register is used to collect the result of a store exclusive -+;; instruction. -+(define_attr "sync_t2" "none,0,1,2,3,4,5" (const_string "none")) -+ -+;; Attribute that specifies whether or not the emitted synchronization -+;; loop must contain a release barrier. -+(define_attr "sync_release_barrier" "yes,no" (const_string "yes")) -+ -+;; Attribute that specifies the operation that the synchronization -+;; loop should apply to the old and new values to generate the value -+;; written back to memory. -+(define_attr "sync_op" "none,add,sub,ior,xor,and,nand" -+ (const_string "none")) -+ -+;; ------------------------------------------------------------------- -+;; Instruction types and attributes -+;; ------------------------------------------------------------------- -+ -+;; Main data types used by the insntructions -+ -+(define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF" -+ (const_string "unknown")) -+ -+(define_attr "mode2" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF" -+ (const_string "unknown")) -+ -+; The "v8type" attribute is used to for fine grained classification of -+; AArch64 instructions. This table briefly explains the meaning of each type. -+ -+; adc add/subtract with carry. -+; adcs add/subtract with carry (setting condition flags). -+; adr calculate address. -+; alu simple alu instruction (no memory or fp regs access). -+; alu_ext simple alu instruction (sign/zero-extended register). -+; alu_shift simple alu instruction, with a source operand shifted by a constant. -+; alus simple alu instruction (setting condition flags). -+; alus_ext simple alu instruction (sign/zero-extended register, setting condition flags). -+; alus_shift simple alu instruction, with a source operand shifted by a constant (setting condition flags). -+; bfm bitfield move operation. -+; branch branch. -+; call subroutine call. -+; ccmp conditional compare. -+; clz count leading zeros/sign bits. -+; csel conditional select. -+; dmb data memory barrier. -+; extend sign/zero-extend (specialised bitfield move). -+; extr extract register-sized bitfield encoding. -+; fpsimd_load load single floating point / simd scalar register from memory. -+; fpsimd_load2 load pair of floating point / simd scalar registers from memory. -+; fpsimd_store store single floating point / simd scalar register to memory. -+; fpsimd_store2 store pair floating point / simd scalar registers to memory. -+; fadd floating point add/sub. -+; fccmp floating point conditional compare. -+; fcmp floating point comparison. -+; fconst floating point load immediate. -+; fcsel floating point conditional select. -+; fcvt floating point convert (float to float). -+; fcvtf2i floating point convert (float to integer). -+; fcvti2f floating point convert (integer to float). -+; fdiv floating point division operation. -+; ffarith floating point abs, neg or cpy. -+; fmadd floating point multiply-add/sub. -+; fminmax floating point min/max. -+; fmov floating point move (float to float). -+; fmovf2i floating point move (float to integer). -+; fmovi2f floating point move (integer to float). -+; fmul floating point multiply. -+; frint floating point round to integral. -+; fsqrt floating point square root. -+; load_acq load-acquire. -+; load load single general register from memory -+; load2 load pair of general registers from memory -+; logic logical operation (register). -+; logic_imm and/or/xor operation (immediate). -+; logic_shift logical operation with shift. -+; logics logical operation (register, setting condition flags). -+; logics_imm and/or/xor operation (immediate, setting condition flags). -+; logics_shift logical operation with shift (setting condition flags). -+; madd integer multiply-add/sub. -+; maddl widening integer multiply-add/sub. -+; misc miscellaneous - any type that doesn't fit into the rest. -+; move integer move operation. -+; move2 double integer move operation. -+; movk move 16-bit immediate with keep. -+; movz move 16-bit immmediate with zero/one. -+; mrs system/special register move. -+; mulh 64x64 to 128-bit multiply (high part). -+; mull widening multiply. -+; mult integer multiply instruction. -+; prefetch memory prefetch. -+; rbit reverse bits. -+; rev reverse bytes. -+; sdiv integer division operation (signed). -+; shift variable shift operation. -+; shift_imm immediate shift operation (specialised bitfield move). -+; store_rel store-release. -+; store store single general register to memory. -+; store2 store pair of general registers to memory. -+; udiv integer division operation (unsigned). -+ -+(define_attr "v8type" -+ "adc,\ -+ adcs,\ -+ adr,\ -+ alu,\ -+ alu_ext,\ -+ alu_shift,\ -+ alus,\ -+ alus_ext,\ -+ alus_shift,\ -+ bfm,\ -+ branch,\ -+ call,\ -+ ccmp,\ -+ clz,\ -+ csel,\ -+ dmb,\ -+ div,\ -+ div64,\ -+ extend,\ -+ extr,\ -+ fpsimd_load,\ -+ fpsimd_load2,\ -+ fpsimd_store2,\ -+ fpsimd_store,\ -+ fadd,\ -+ fccmp,\ -+ fcvt,\ -+ fcvtf2i,\ -+ fcvti2f,\ -+ fcmp,\ -+ fconst,\ -+ fcsel,\ -+ fdiv,\ -+ ffarith,\ -+ fmadd,\ -+ fminmax,\ -+ fmov,\ -+ fmovf2i,\ -+ fmovi2f,\ -+ fmul,\ -+ frint,\ -+ fsqrt,\ -+ load_acq,\ -+ load1,\ -+ load2,\ -+ logic,\ -+ logic_imm,\ -+ logic_shift,\ -+ logics,\ -+ logics_imm,\ -+ logics_shift,\ -+ madd,\ -+ maddl,\ -+ misc,\ -+ move,\ -+ move2,\ -+ movk,\ -+ movz,\ -+ mrs,\ -+ mulh,\ -+ mull,\ -+ mult,\ -+ prefetch,\ -+ rbit,\ -+ rev,\ -+ sdiv,\ -+ shift,\ -+ shift_imm,\ -+ store_rel,\ -+ store1,\ -+ store2,\ -+ udiv" -+ (const_string "alu")) -+ -+ -+; The "type" attribute is used by the AArch32 backend. Below is a mapping -+; from "v8type" to "type". -+ -+(define_attr "type" -+ "alu,alu_shift,block,branch,call,f_2_r,f_cvt,f_flag,f_loads, -+ f_loadd,f_stored,f_stores,faddd,fadds,fcmpd,fcmps,fconstd,fconsts, -+ fcpys,fdivd,fdivs,ffarithd,ffariths,fmacd,fmacs,fmuld,fmuls,load_byte, -+ load1,load2,mult,r_2_f,store1,store2" -+ (cond [ -+ (eq_attr "v8type" "alu_shift,alus_shift,logic_shift,logics_shift") (const_string "alu_shift") -+ (eq_attr "v8type" "branch") (const_string "branch") -+ (eq_attr "v8type" "call") (const_string "call") -+ (eq_attr "v8type" "fmovf2i") (const_string "f_2_r") -+ (eq_attr "v8type" "fcvt,fcvtf2i,fcvti2f") (const_string "f_cvt") -+ (and (eq_attr "v8type" "fpsimd_load") (eq_attr "mode" "SF")) (const_string "f_loads") -+ (and (eq_attr "v8type" "fpsimd_load") (eq_attr "mode" "DF")) (const_string "f_loadd") -+ (and (eq_attr "v8type" "fpsimd_store") (eq_attr "mode" "SF")) (const_string "f_stores") -+ (and (eq_attr "v8type" "fpsimd_store") (eq_attr "mode" "DF")) (const_string "f_stored") -+ (and (eq_attr "v8type" "fadd,fminmax") (eq_attr "mode" "DF")) (const_string "faddd") -+ (and (eq_attr "v8type" "fadd,fminmax") (eq_attr "mode" "SF")) (const_string "fadds") -+ (and (eq_attr "v8type" "fcmp,fccmp") (eq_attr "mode" "DF")) (const_string "fcmpd") -+ (and (eq_attr "v8type" "fcmp,fccmp") (eq_attr "mode" "SF")) (const_string "fcmps") -+ (and (eq_attr "v8type" "fconst") (eq_attr "mode" "DF")) (const_string "fconstd") -+ (and (eq_attr "v8type" "fconst") (eq_attr "mode" "SF")) (const_string "fconsts") -+ (and (eq_attr "v8type" "fdiv,fsqrt") (eq_attr "mode" "DF")) (const_string "fdivd") -+ (and (eq_attr "v8type" "fdiv,fsqrt") (eq_attr "mode" "SF")) (const_string "fdivs") -+ (and (eq_attr "v8type" "ffarith") (eq_attr "mode" "DF")) (const_string "ffarithd") -+ (and (eq_attr "v8type" "ffarith") (eq_attr "mode" "SF")) (const_string "ffariths") -+ (and (eq_attr "v8type" "fmadd") (eq_attr "mode" "DF")) (const_string "fmacd") -+ (and (eq_attr "v8type" "fmadd") (eq_attr "mode" "SF")) (const_string "fmacs") -+ (and (eq_attr "v8type" "fmul") (eq_attr "mode" "DF")) (const_string "fmuld") -+ (and (eq_attr "v8type" "fmul") (eq_attr "mode" "SF")) (const_string "fmuls") -+ (and (eq_attr "v8type" "load1") (eq_attr "mode" "QI,HI")) (const_string "load_byte") -+ (and (eq_attr "v8type" "load1") (eq_attr "mode" "SI,DI,TI")) (const_string "load1") -+ (eq_attr "v8type" "load2") (const_string "load2") -+ (and (eq_attr "v8type" "mulh,mult,mull,madd,sdiv,udiv") (eq_attr "mode" "SI")) (const_string "mult") -+ (eq_attr "v8type" "fmovi2f") (const_string "r_2_f") -+ (eq_attr "v8type" "store1") (const_string "store1") -+ (eq_attr "v8type" "store2") (const_string "store2") -+ ] -+ (const_string "alu"))) -+ -+;; Attribute that specifies whether or not the instruction touches fp -+;; registers. -+(define_attr "fp" "no,yes" (const_string "no")) -+ -+;; Attribute that specifies whether or not the instruction touches simd -+;; registers. -+(define_attr "simd" "no,yes" (const_string "no")) -+ -+(define_attr "length" "" -+ (cond [(not (eq_attr "sync_memory" "none")) -+ (symbol_ref "aarch64_sync_loop_insns (insn, operands) * 4") -+ ] (const_int 4))) -+ -+;; Attribute that controls whether an alternative is enabled or not. -+;; Currently it is only used to disable alternatives which touch fp or simd -+;; registers when -mgeneral-regs-only is specified. -+(define_attr "enabled" "no,yes" -+ (cond [(ior -+ (and (eq_attr "fp" "yes") -+ (eq (symbol_ref "TARGET_FLOAT") (const_int 0))) -+ (and (eq_attr "simd" "yes") -+ (eq (symbol_ref "TARGET_SIMD") (const_int 0)))) -+ (const_string "no") -+ ] (const_string "yes"))) -+ -+;; ------------------------------------------------------------------- -+;; Pipeline descriptions and scheduling -+;; ------------------------------------------------------------------- -+ -+;; Processor types. -+(include "aarch64-tune.md") -+ -+;; Scheduling -+(include "aarch64-generic.md") -+(include "large.md") -+(include "small.md") -+ -+;; ------------------------------------------------------------------- -+;; Jumps and other miscellaneous insns -+;; ------------------------------------------------------------------- -+ -+(define_insn "indirect_jump" -+ [(set (pc) (match_operand:DI 0 "register_operand" "r"))] -+ "" -+ "br\\t%0" -+ [(set_attr "v8type" "branch")] -+) -+ -+(define_insn "jump" -+ [(set (pc) (label_ref (match_operand 0 "" "")))] -+ "" -+ "b\\t%l0" -+ [(set_attr "v8type" "branch")] -+) -+ -+(define_expand "cbranch4" -+ [(set (pc) (if_then_else (match_operator 0 "aarch64_comparison_operator" -+ [(match_operand:GPI 1 "register_operand" "") -+ (match_operand:GPI 2 "aarch64_plus_operand" "")]) -+ (label_ref (match_operand 3 "" "")) -+ (pc)))] -+ "" -+ " -+ operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[0]), operands[1], -+ operands[2]); -+ operands[2] = const0_rtx; -+ " -+) -+ -+(define_expand "cbranch4" -+ [(set (pc) (if_then_else (match_operator 0 "aarch64_comparison_operator" -+ [(match_operand:GPF 1 "register_operand" "") -+ (match_operand:GPF 2 "aarch64_reg_or_zero" "")]) -+ (label_ref (match_operand 3 "" "")) -+ (pc)))] -+ "" -+ " -+ operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[0]), operands[1], -+ operands[2]); -+ operands[2] = const0_rtx; -+ " -+) -+ -+(define_insn "*condjump" -+ [(set (pc) (if_then_else (match_operator 0 "aarch64_comparison_operator" -+ [(match_operand 1 "cc_register" "") (const_int 0)]) -+ (label_ref (match_operand 2 "" "")) -+ (pc)))] -+ "" -+ "b%m0\\t%l2" -+ [(set_attr "v8type" "branch")] -+) -+ -+(define_expand "casesi" -+ [(match_operand:SI 0 "register_operand" "") ; Index -+ (match_operand:SI 1 "const_int_operand" "") ; Lower bound -+ (match_operand:SI 2 "const_int_operand" "") ; Total range -+ (match_operand:DI 3 "" "") ; Table label -+ (match_operand:DI 4 "" "")] ; Out of range label -+ "" -+ { -+ if (operands[1] != const0_rtx) -+ { -+ rtx reg = gen_reg_rtx (SImode); -+ -+ /* Canonical RTL says that if you have: -+ -+ (minus (X) (CONST)) -+ -+ then this should be emitted as: -+ -+ (plus (X) (-CONST)) -+ -+ The use of trunc_int_for_mode ensures that the resulting -+ constant can be represented in SImode, this is important -+ for the corner case where operand[1] is INT_MIN. */ -+ -+ operands[1] = GEN_INT (trunc_int_for_mode (-INTVAL (operands[1]), SImode)); -+ -+ if (!(*insn_data[CODE_FOR_addsi3].operand[2].predicate) -+ (operands[1], SImode)) -+ operands[1] = force_reg (SImode, operands[1]); -+ emit_insn (gen_addsi3 (reg, operands[0], operands[1])); -+ operands[0] = reg; -+ } -+ -+ if (!aarch64_plus_operand (operands[2], SImode)) -+ operands[2] = force_reg (SImode, operands[2]); -+ emit_jump_insn (gen_cbranchsi4 (gen_rtx_GTU (SImode, const0_rtx, -+ const0_rtx), -+ operands[0], operands[2], operands[4])); -+ -+ operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (VOIDmode, operands[3])); -+ emit_jump_insn (gen_casesi_dispatch (operands[2], operands[0], -+ operands[3])); -+ DONE; -+ } -+) -+ -+(define_insn "casesi_dispatch" -+ [(parallel -+ [(set (pc) -+ (mem:DI (unspec [(match_operand:DI 0 "register_operand" "r") -+ (match_operand:SI 1 "register_operand" "r")] -+ UNSPEC_CASESI))) -+ (clobber (reg:CC CC_REGNUM)) -+ (clobber (match_scratch:DI 3 "=r")) -+ (clobber (match_scratch:DI 4 "=r")) -+ (use (label_ref (match_operand 2 "" "")))])] -+ "" -+ "* -+ return aarch64_output_casesi (operands); -+ " -+ [(set_attr "length" "16") -+ (set_attr "v8type" "branch")] -+) -+ -+(define_insn "nop" -+ [(unspec[(const_int 0)] UNSPEC_NOP)] -+ "" -+ "nop" -+ [(set_attr "v8type" "misc")] -+) -+ -+(define_expand "prologue" -+ [(clobber (const_int 0))] -+ "" -+ " -+ aarch64_expand_prologue (); -+ DONE; -+ " -+) -+ -+(define_expand "epilogue" -+ [(clobber (const_int 0))] -+ "" -+ " -+ aarch64_expand_epilogue (false); -+ DONE; -+ " -+) -+ -+(define_expand "sibcall_epilogue" -+ [(clobber (const_int 0))] -+ "" -+ " -+ aarch64_expand_epilogue (true); -+ DONE; -+ " -+) -+ -+(define_insn "*do_return" -+ [(return)] -+ "" -+ "ret" -+ [(set_attr "v8type" "branch")] -+) -+ -+(define_insn "eh_return" -+ [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] -+ UNSPECV_EH_RETURN)] -+ "" -+ "#" -+ [(set_attr "v8type" "branch")] -+) -+ -+(define_split -+ [(unspec_volatile [(match_operand:DI 0 "register_operand" "")] -+ UNSPECV_EH_RETURN)] -+ "reload_completed" -+ [(set (match_dup 1) (match_dup 0))] -+ { -+ operands[1] = aarch64_final_eh_return_addr (); -+ } -+) -+ -+(define_insn "*cb1" -+ [(set (pc) (if_then_else (EQL (match_operand:GPI 0 "register_operand" "r") -+ (const_int 0)) -+ (label_ref (match_operand 1 "" "")) -+ (pc)))] -+ "" -+ "\\t%0, %l1" -+ [(set_attr "v8type" "branch")] -+) -+ -+(define_insn "*tb1" -+ [(set (pc) (if_then_else -+ (EQL (zero_extract:DI (match_operand:GPI 0 "register_operand" "r") -+ (const_int 1) -+ (match_operand 1 "const_int_operand" "n")) -+ (const_int 0)) -+ (label_ref (match_operand 2 "" "")) -+ (pc))) -+ (clobber (match_scratch:DI 3 "=r"))] -+ "" -+ "* -+ if (get_attr_length (insn) == 8) -+ return \"ubfx\\t%3, %0, %1, #1\;\\t%3, %l2\"; -+ return \"\\t%0, %1, %l2\"; -+ " -+ [(set_attr "v8type" "branch") -+ (set_attr "mode" "") -+ (set (attr "length") -+ (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -32768)) -+ (lt (minus (match_dup 2) (pc)) (const_int 32764))) -+ (const_int 4) -+ (const_int 8)))] -+) -+ -+(define_insn "*cb1" -+ [(set (pc) (if_then_else (LTGE (match_operand:ALLI 0 "register_operand" "r") -+ (const_int 0)) -+ (label_ref (match_operand 1 "" "")) -+ (pc))) -+ (clobber (match_scratch:DI 2 "=r"))] -+ "" -+ "* -+ if (get_attr_length (insn) == 8) -+ return \"ubfx\\t%2, %0, , #1\;\\t%2, %l1\"; -+ return \"\\t%0, , %l1\"; -+ " -+ [(set_attr "v8type" "branch") -+ (set_attr "mode" "") -+ (set (attr "length") -+ (if_then_else (and (ge (minus (match_dup 1) (pc)) (const_int -32768)) -+ (lt (minus (match_dup 1) (pc)) (const_int 32764))) -+ (const_int 4) -+ (const_int 8)))] -+) -+ -+;; ------------------------------------------------------------------- -+;; Subroutine calls and sibcalls -+;; ------------------------------------------------------------------- -+ -+(define_expand "call" -+ [(parallel [(call (match_operand 0 "memory_operand" "") -+ (match_operand 1 "general_operand" "")) -+ (use (match_operand 2 "" "")) -+ (clobber (reg:DI LR_REGNUM))])] -+ "" -+ " -+ { -+ rtx callee; -+ -+ /* In an untyped call, we can get NULL for operand 2. */ -+ if (operands[2] == NULL) -+ operands[2] = const0_rtx; -+ -+ /* Decide if we should generate indirect calls by loading the -+ 64-bit address of the callee into a register before performing -+ the branch-and-link. */ -+ callee = XEXP (operands[0], 0); -+ if (GET_CODE (callee) == SYMBOL_REF -+ ? aarch64_is_long_call_p (callee) -+ : !REG_P (callee)) -+ XEXP (operands[0], 0) = force_reg (Pmode, callee); -+ }" -+) -+ -+(define_insn "*call_reg" -+ [(call (mem:DI (match_operand:DI 0 "register_operand" "r")) -+ (match_operand 1 "" "")) -+ (use (match_operand 2 "" "")) -+ (clobber (reg:DI LR_REGNUM))] -+ "" -+ "blr\\t%0" -+ [(set_attr "v8type" "call")] -+) -+ -+(define_insn "*call_symbol" -+ [(call (mem:DI (match_operand:DI 0 "" "")) -+ (match_operand 1 "" "")) -+ (use (match_operand 2 "" "")) -+ (clobber (reg:DI LR_REGNUM))] -+ "GET_CODE (operands[0]) == SYMBOL_REF -+ && !aarch64_is_long_call_p (operands[0])" -+ "bl\\t%a0" -+ [(set_attr "v8type" "call")] -+) -+ -+(define_expand "call_value" -+ [(parallel [(set (match_operand 0 "" "") -+ (call (match_operand 1 "memory_operand" "") -+ (match_operand 2 "general_operand" ""))) -+ (use (match_operand 3 "" "")) -+ (clobber (reg:DI LR_REGNUM))])] -+ "" -+ " -+ { -+ rtx callee; -+ -+ /* In an untyped call, we can get NULL for operand 3. */ -+ if (operands[3] == NULL) -+ operands[3] = const0_rtx; -+ -+ /* Decide if we should generate indirect calls by loading the -+ 64-bit address of the callee into a register before performing -+ the branch-and-link. */ -+ callee = XEXP (operands[1], 0); -+ if (GET_CODE (callee) == SYMBOL_REF -+ ? aarch64_is_long_call_p (callee) -+ : !REG_P (callee)) -+ XEXP (operands[1], 0) = force_reg (Pmode, callee); -+ }" -+) -+ -+(define_insn "*call_value_reg" -+ [(set (match_operand 0 "" "") -+ (call (mem:DI (match_operand:DI 1 "register_operand" "r")) -+ (match_operand 2 "" ""))) -+ (use (match_operand 3 "" "")) -+ (clobber (reg:DI LR_REGNUM))] -+ "" -+ "blr\\t%1" -+ [(set_attr "v8type" "call")] -+) -+ -+(define_insn "*call_value_symbol" -+ [(set (match_operand 0 "" "") -+ (call (mem:DI (match_operand:DI 1 "" "")) -+ (match_operand 2 "" ""))) -+ (use (match_operand 3 "" "")) -+ (clobber (reg:DI LR_REGNUM))] -+ "GET_CODE (operands[1]) == SYMBOL_REF -+ && !aarch64_is_long_call_p (operands[1])" -+ "bl\\t%a1" -+ [(set_attr "v8type" "call")] -+) -+ -+(define_expand "sibcall" -+ [(parallel [(call (match_operand 0 "memory_operand" "") -+ (match_operand 1 "general_operand" "")) -+ (return) -+ (use (match_operand 2 "" ""))])] -+ "" -+ { -+ if (operands[2] == NULL_RTX) -+ operands[2] = const0_rtx; -+ } -+) -+ -+(define_expand "sibcall_value" -+ [(parallel [(set (match_operand 0 "" "") -+ (call (match_operand 1 "memory_operand" "") -+ (match_operand 2 "general_operand" ""))) -+ (return) -+ (use (match_operand 3 "" ""))])] -+ "" -+ { -+ if (operands[3] == NULL_RTX) -+ operands[3] = const0_rtx; -+ } -+) -+ -+(define_insn "*sibcall_insn" -+ [(call (mem:DI (match_operand:DI 0 "" "X")) -+ (match_operand 1 "" "")) -+ (return) -+ (use (match_operand 2 "" ""))] -+ "GET_CODE (operands[0]) == SYMBOL_REF" -+ "b\\t%a0" -+ [(set_attr "v8type" "branch")] -+) -+ -+(define_insn "*sibcall_value_insn" -+ [(set (match_operand 0 "" "") -+ (call (mem:DI (match_operand 1 "" "X")) -+ (match_operand 2 "" ""))) -+ (return) -+ (use (match_operand 3 "" ""))] -+ "GET_CODE (operands[1]) == SYMBOL_REF" -+ "b\\t%a1" -+ [(set_attr "v8type" "branch")] -+) -+ -+;; Call subroutine returning any type. -+ -+(define_expand "untyped_call" -+ [(parallel [(call (match_operand 0 "") -+ (const_int 0)) -+ (match_operand 1 "") -+ (match_operand 2 "")])] -+ "" -+{ -+ int i; -+ -+ emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx)); -+ -+ for (i = 0; i < XVECLEN (operands[2], 0); i++) -+ { -+ rtx set = XVECEXP (operands[2], 0, i); -+ emit_move_insn (SET_DEST (set), SET_SRC (set)); -+ } -+ -+ /* The optimizer does not know that the call sets the function value -+ registers we stored in the result block. We avoid problems by -+ claiming that all hard registers are used and clobbered at this -+ point. */ -+ emit_insn (gen_blockage ()); -+ DONE; -+}) -+ -+;; ------------------------------------------------------------------- -+;; Moves -+;; ------------------------------------------------------------------- -+ -+(define_expand "mov" -+ [(set (match_operand:SHORT 0 "nonimmediate_operand" "") -+ (match_operand:SHORT 1 "general_operand" ""))] -+ "" -+ " -+ if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx) -+ operands[1] = force_reg (mode, operands[1]); -+ " -+) -+ -+(define_insn "*mov_aarch64" -+ [(set (match_operand:SHORT 0 "nonimmediate_operand" "=r,r,r,m, r,*w") -+ (match_operand:SHORT 1 "general_operand" " r,M,m,rZ,*w,r"))] -+ "(register_operand (operands[0], mode) -+ || aarch64_reg_or_zero (operands[1], mode))" -+ "@ -+ mov\\t%w0, %w1 -+ mov\\t%w0, %1 -+ ldr\\t%w0, %1 -+ str\\t%w1, %0 -+ umov\\t%w0, %1.[0] -+ dup\\t%0., %w1" -+ [(set_attr "v8type" "move,alu,load1,store1,*,*") -+ (set_attr "simd_type" "*,*,*,*,simd_movgp,simd_dupgp") -+ (set_attr "mode" "") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_expand "mov" -+ [(set (match_operand:GPI 0 "nonimmediate_operand" "") -+ (match_operand:GPI 1 "general_operand" ""))] -+ "" -+ " -+ if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx) -+ operands[1] = force_reg (mode, operands[1]); -+ -+ if (CONSTANT_P (operands[1])) -+ { -+ aarch64_expand_mov_immediate (operands[0], operands[1]); -+ DONE; -+ } -+ " -+) -+ -+(define_insn "*movsi_aarch64" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m, *w, r,*w") -+ (match_operand:SI 1 "aarch64_mov_operand" " r,M,m,rZ,rZ,*w,*w"))] -+ "(register_operand (operands[0], SImode) -+ || aarch64_reg_or_zero (operands[1], SImode))" -+ "@ -+ mov\\t%w0, %w1 -+ mov\\t%w0, %1 -+ ldr\\t%w0, %1 -+ str\\t%w1, %0 -+ fmov\\t%s0, %w1 -+ fmov\\t%w0, %s1 -+ fmov\\t%s0, %s1" -+ [(set_attr "v8type" "move,alu,load1,store1,fmov,fmov,fmov") -+ (set_attr "mode" "SI") -+ (set_attr "fp" "*,*,*,*,yes,yes,yes")] -+) -+ -+(define_insn "*movdi_aarch64" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,k,r,r,r,m, r, r, *w, r,*w") -+ (match_operand:DI 1 "aarch64_mov_operand" " r,r,k,N,m,rZ,Usa,Ush,rZ,*w,*w"))] -+ "(register_operand (operands[0], DImode) -+ || aarch64_reg_or_zero (operands[1], DImode))" -+ "@ -+ mov\\t%x0, %x1 -+ mov\\t%0, %x1 -+ mov\\t%x0, %1 -+ mov\\t%x0, %1 -+ ldr\\t%x0, %1 -+ str\\t%x1, %0 -+ adr\\t%x0, %a1 -+ adrp\\t%x0, %A1 -+ fmov\\t%d0, %x1 -+ fmov\\t%x0, %d1 -+ fmov\\t%d0, %d1" -+ [(set_attr "v8type" "move,move,move,alu,load1,store1,adr,adr,fmov,fmov,fmov") -+ (set_attr "mode" "DI") -+ (set_attr "fp" "*,*,*,*,*,*,*,*,yes,yes,yes")] -+) -+ -+(define_insn "insv_imm" -+ [(set (zero_extract:GPI (match_operand:GPI 0 "register_operand" "+r") -+ (const_int 16) -+ (match_operand 1 "const_int_operand" "n")) -+ (match_operand 2 "const_int_operand" "n"))] -+ "INTVAL (operands[1]) < GET_MODE_BITSIZE (mode) -+ && INTVAL (operands[1]) % 16 == 0 -+ && INTVAL (operands[2]) <= 0xffff" -+ "movk\\t%0, %2, lsl %1" -+ [(set_attr "v8type" "movk") -+ (set_attr "mode" "")] -+) -+ -+(define_expand "movti" -+ [(set (match_operand:TI 0 "nonimmediate_operand" "") -+ (match_operand:TI 1 "general_operand" ""))] -+ "" -+ " -+ if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx) -+ operands[1] = force_reg (TImode, operands[1]); -+ " -+) -+ -+(define_insn "*movti_aarch64" -+ [(set (match_operand:TI 0 -+ "nonimmediate_operand" "=r, *w,r ,*w,r ,Ump,Ump,*w,m") -+ (match_operand:TI 1 -+ "aarch64_movti_operand" " rn,r ,*w,*w,Ump,r ,Z , m,*w"))] -+ "(register_operand (operands[0], TImode) -+ || aarch64_reg_or_zero (operands[1], TImode))" -+ "@ -+ # -+ # -+ # -+ orr\\t%0.16b, %1.16b, %1.16b -+ ldp\\t%0, %H0, %1 -+ stp\\t%1, %H1, %0 -+ stp\\txzr, xzr, %0 -+ ldr\\t%q0, %1 -+ str\\t%q1, %0" -+ [(set_attr "v8type" "move2,fmovi2f,fmovf2i,*, \ -+ load2,store2,store2,fpsimd_load,fpsimd_store") -+ (set_attr "simd_type" "*,*,*,simd_move,*,*,*,*,*") -+ (set_attr "mode" "DI,DI,DI,TI,DI,DI,DI,TI,TI") -+ (set_attr "length" "8,8,8,4,4,4,4,4,4") -+ (set_attr "fp" "*,*,*,*,*,*,*,yes,yes") -+ (set_attr "simd" "*,*,*,yes,*,*,*,*,*")]) -+ -+;; Split a TImode register-register or register-immediate move into -+;; its component DImode pieces, taking care to handle overlapping -+;; source and dest registers. -+(define_split -+ [(set (match_operand:TI 0 "register_operand" "") -+ (match_operand:TI 1 "aarch64_reg_or_imm" ""))] -+ "reload_completed" -+ [(const_int 0)] -+{ -+ aarch64_split_doubleword_move (operands[0], operands[1]); -+ DONE; -+}) -+ -+(define_expand "mov" -+ [(set (match_operand:GPF 0 "nonimmediate_operand" "") -+ (match_operand:GPF 1 "general_operand" ""))] -+ "" -+ " -+ if (!TARGET_FLOAT) -+ { -+ sorry (\"%qs and floating point code\", \"-mgeneral-regs-only\"); -+ FAIL; -+ } -+ -+ if (GET_CODE (operands[0]) == MEM) -+ operands[1] = force_reg (mode, operands[1]); -+ " -+) -+ -+(define_insn "*movsf_aarch64" -+ [(set (match_operand:SF 0 "nonimmediate_operand" "= w,?r,w,w,m,r,m ,r") -+ (match_operand:SF 1 "general_operand" "?rY, w,w,m,w,m,rY,r"))] -+ "TARGET_FLOAT && (register_operand (operands[0], SFmode) -+ || register_operand (operands[1], SFmode))" -+ "@ -+ fmov\\t%s0, %w1 -+ fmov\\t%w0, %s1 -+ fmov\\t%s0, %s1 -+ ldr\\t%s0, %1 -+ str\\t%s1, %0 -+ ldr\\t%w0, %1 -+ str\\t%w1, %0 -+ mov\\t%w0, %w1" -+ [(set_attr "v8type" "fmovi2f,fmovf2i,fmov,fpsimd_load,fpsimd_store,fpsimd_load,fpsimd_store,fmov") -+ (set_attr "mode" "SF")] -+) -+ -+(define_insn "*movdf_aarch64" -+ [(set (match_operand:DF 0 "nonimmediate_operand" "= w,?r,w,w,m,r,m ,r") -+ (match_operand:DF 1 "general_operand" "?rY, w,w,m,w,m,rY,r"))] -+ "TARGET_FLOAT && (register_operand (operands[0], DFmode) -+ || register_operand (operands[1], DFmode))" -+ "@ -+ fmov\\t%d0, %x1 -+ fmov\\t%x0, %d1 -+ fmov\\t%d0, %d1 -+ ldr\\t%d0, %1 -+ str\\t%d1, %0 -+ ldr\\t%x0, %1 -+ str\\t%x1, %0 -+ mov\\t%x0, %x1" -+ [(set_attr "v8type" "fmovi2f,fmovf2i,fmov,fpsimd_load,fpsimd_store,fpsimd_load,fpsimd_store,move") -+ (set_attr "mode" "DF")] -+) -+ -+(define_expand "movtf" -+ [(set (match_operand:TF 0 "nonimmediate_operand" "") -+ (match_operand:TF 1 "general_operand" ""))] -+ "" -+ " -+ if (!TARGET_FLOAT) -+ { -+ sorry (\"%qs and floating point code\", \"-mgeneral-regs-only\"); -+ FAIL; -+ } -+ -+ if (GET_CODE (operands[0]) == MEM) -+ operands[1] = force_reg (TFmode, operands[1]); -+ " -+) -+ -+(define_insn "*movtf_aarch64" -+ [(set (match_operand:TF 0 -+ "nonimmediate_operand" "=w,?&r,w ,?r,w,?w,w,m,?r ,Ump") -+ (match_operand:TF 1 -+ "general_operand" " w,?r, ?r,w ,Y,Y ,m,w,Ump,?rY"))] -+ "TARGET_FLOAT && (register_operand (operands[0], TFmode) -+ || register_operand (operands[1], TFmode))" -+ "@ -+ orr\\t%0.16b, %1.16b, %1.16b -+ mov\\t%0, %1\;mov\\t%H0, %H1 -+ fmov\\t%d0, %Q1\;fmov\\t%0.d[1], %R1 -+ fmov\\t%Q0, %d1\;fmov\\t%R0, %1.d[1] -+ movi\\t%0.2d, #0 -+ fmov\\t%s0, wzr -+ ldr\\t%q0, %1 -+ str\\t%q1, %0 -+ ldp\\t%0, %H0, %1 -+ stp\\t%1, %H1, %0" -+ [(set_attr "v8type" "logic,move2,fmovi2f,fmovf2i,fconst,fconst,fpsimd_load,fpsimd_store,fpsimd_load2,fpsimd_store2") -+ (set_attr "mode" "DF,DF,DF,DF,DF,DF,TF,TF,DF,DF") -+ (set_attr "length" "4,8,8,8,4,4,4,4,4,4") -+ (set_attr "fp" "*,*,yes,yes,*,yes,yes,yes,*,*") -+ (set_attr "simd" "yes,*,*,*,yes,*,*,*,*,*")] -+) -+ -+ -+;; Operands 1 and 3 are tied together by the final condition; so we allow -+;; fairly lax checking on the second memory operation. -+(define_insn "load_pair" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (match_operand:GPI 1 "aarch64_mem_pair_operand" "Ump")) -+ (set (match_operand:GPI 2 "register_operand" "=r") -+ (match_operand:GPI 3 "memory_operand" "m"))] -+ "rtx_equal_p (XEXP (operands[3], 0), -+ plus_constant (XEXP (operands[1], 0), -+ GET_MODE_SIZE (mode)))" -+ "ldp\\t%0, %2, %1" -+ [(set_attr "v8type" "load2") -+ (set_attr "mode" "")] -+) -+ -+;; Operands 0 and 2 are tied together by the final condition; so we allow -+;; fairly lax checking on the second memory operation. -+(define_insn "store_pair" -+ [(set (match_operand:GPI 0 "aarch64_mem_pair_operand" "=Ump") -+ (match_operand:GPI 1 "register_operand" "r")) -+ (set (match_operand:GPI 2 "memory_operand" "=m") -+ (match_operand:GPI 3 "register_operand" "r"))] -+ "rtx_equal_p (XEXP (operands[2], 0), -+ plus_constant (XEXP (operands[0], 0), -+ GET_MODE_SIZE (mode)))" -+ "stp\\t%1, %3, %0" -+ [(set_attr "v8type" "store2") -+ (set_attr "mode" "")] -+) -+ -+;; Operands 1 and 3 are tied together by the final condition; so we allow -+;; fairly lax checking on the second memory operation. -+(define_insn "load_pair" -+ [(set (match_operand:GPF 0 "register_operand" "=w") -+ (match_operand:GPF 1 "aarch64_mem_pair_operand" "Ump")) -+ (set (match_operand:GPF 2 "register_operand" "=w") -+ (match_operand:GPF 3 "memory_operand" "m"))] -+ "rtx_equal_p (XEXP (operands[3], 0), -+ plus_constant (XEXP (operands[1], 0), -+ GET_MODE_SIZE (mode)))" -+ "ldp\\t%0, %2, %1" -+ [(set_attr "v8type" "fpsimd_load2") -+ (set_attr "mode" "")] -+) -+ -+;; Operands 0 and 2 are tied together by the final condition; so we allow -+;; fairly lax checking on the second memory operation. -+(define_insn "store_pair" -+ [(set (match_operand:GPF 0 "aarch64_mem_pair_operand" "=Ump") -+ (match_operand:GPF 1 "register_operand" "w")) -+ (set (match_operand:GPF 2 "memory_operand" "=m") -+ (match_operand:GPF 3 "register_operand" "w"))] -+ "rtx_equal_p (XEXP (operands[2], 0), -+ plus_constant (XEXP (operands[0], 0), -+ GET_MODE_SIZE (mode)))" -+ "stp\\t%1, %3, %0" -+ [(set_attr "v8type" "fpsimd_load2") -+ (set_attr "mode" "")] -+) -+ -+;; Load pair with writeback. This is primarily used in function epilogues -+;; when restoring [fp,lr] -+(define_insn "loadwb_pair_" -+ [(parallel -+ [(set (match_operand:PTR 0 "register_operand" "=k") -+ (plus:PTR (match_operand:PTR 1 "register_operand" "0") -+ (match_operand:PTR 4 "const_int_operand" "n"))) -+ (set (match_operand:GPI 2 "register_operand" "=r") -+ (mem:GPI (plus:PTR (match_dup 1) -+ (match_dup 4)))) -+ (set (match_operand:GPI 3 "register_operand" "=r") -+ (mem:GPI (plus:PTR (match_dup 1) -+ (match_operand:PTR 5 "const_int_operand" "n"))))])] -+ "INTVAL (operands[5]) == INTVAL (operands[4]) + GET_MODE_SIZE (mode)" -+ "ldp\\t%2, %3, [%1], %4" -+ [(set_attr "v8type" "load2") -+ (set_attr "mode" "")] -+) -+ -+;; Store pair with writeback. This is primarily used in function prologues -+;; when saving [fp,lr] -+(define_insn "storewb_pair_" -+ [(parallel -+ [(set (match_operand:PTR 0 "register_operand" "=&k") -+ (plus:PTR (match_operand:PTR 1 "register_operand" "0") -+ (match_operand:PTR 4 "const_int_operand" "n"))) -+ (set (mem:GPI (plus:PTR (match_dup 0) -+ (match_dup 4))) -+ (match_operand:GPI 2 "register_operand" "r")) -+ (set (mem:GPI (plus:PTR (match_dup 0) -+ (match_operand:PTR 5 "const_int_operand" "n"))) -+ (match_operand:GPI 3 "register_operand" "r"))])] -+ "INTVAL (operands[5]) == INTVAL (operands[4]) + GET_MODE_SIZE (mode)" -+ "stp\\t%2, %3, [%0, %4]!" -+ [(set_attr "v8type" "store2") -+ (set_attr "mode" "")] -+) -+ -+;; ------------------------------------------------------------------- -+;; Sign/Zero extension -+;; ------------------------------------------------------------------- -+ -+(define_expand "sidi2" -+ [(set (match_operand:DI 0 "register_operand") -+ (ANY_EXTEND:DI (match_operand:SI 1 "nonimmediate_operand")))] -+ "" -+) -+ -+(define_insn "*extendsidi2_aarch64" -+ [(set (match_operand:DI 0 "register_operand" "=r,r") -+ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))] -+ "" -+ "@ -+ sxtw\t%0, %w1 -+ ldrsw\t%0, %1" -+ [(set_attr "v8type" "extend,load1") -+ (set_attr "mode" "DI")] -+) -+ -+(define_insn "*zero_extendsidi2_aarch64" -+ [(set (match_operand:DI 0 "register_operand" "=r,r") -+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))] -+ "" -+ "@ -+ uxtw\t%0, %w1 -+ ldr\t%w0, %1" -+ [(set_attr "v8type" "extend,load1") -+ (set_attr "mode" "DI")] -+) -+ -+(define_expand "2" -+ [(set (match_operand:GPI 0 "register_operand") -+ (ANY_EXTEND:GPI (match_operand:SHORT 1 "nonimmediate_operand")))] -+ "" -+) -+ -+(define_insn "*extend2_aarch64" -+ [(set (match_operand:GPI 0 "register_operand" "=r,r") -+ (sign_extend:GPI (match_operand:SHORT 1 "nonimmediate_operand" "r,m")))] -+ "" -+ "@ -+ sxt\t%0, %w1 -+ ldrs\t%0, %1" -+ [(set_attr "v8type" "extend,load1") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*zero_extend2_aarch64" -+ [(set (match_operand:GPI 0 "register_operand" "=r,r") -+ (zero_extend:GPI (match_operand:SHORT 1 "nonimmediate_operand" "r,m")))] -+ "" -+ "@ -+ uxt\t%0, %w1 -+ ldr\t%w0, %1" -+ [(set_attr "v8type" "extend,load1") -+ (set_attr "mode" "")] -+) -+ -+(define_expand "qihi2" -+ [(set (match_operand:HI 0 "register_operand") -+ (ANY_EXTEND:HI (match_operand:QI 1 "nonimmediate_operand")))] -+ "" -+) -+ -+(define_insn "*qihi2_aarch64" -+ [(set (match_operand:HI 0 "register_operand" "=r,r") -+ (ANY_EXTEND:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))] -+ "" -+ "@ -+ xtb\t%w0, %w1 -+ b\t%w0, %1" -+ [(set_attr "v8type" "extend,load1") -+ (set_attr "mode" "HI")] -+) -+ -+;; ------------------------------------------------------------------- -+;; Simple arithmetic -+;; ------------------------------------------------------------------- -+ -+(define_expand "add3" -+ [(set -+ (match_operand:GPI 0 "register_operand" "") -+ (plus:GPI (match_operand:GPI 1 "register_operand" "") -+ (match_operand:GPI 2 "aarch64_pluslong_operand" "")))] -+ "" -+ " -+ if (! aarch64_plus_operand (operands[2], VOIDmode)) -+ { -+ rtx subtarget = ((optimize && can_create_pseudo_p ()) -+ ? gen_reg_rtx (mode) : operands[0]); -+ HOST_WIDE_INT imm = INTVAL (operands[2]); -+ -+ if (imm < 0) -+ imm = -(-imm & ~0xfff); -+ else -+ imm &= ~0xfff; -+ -+ emit_insn (gen_add3 (subtarget, operands[1], GEN_INT (imm))); -+ operands[1] = subtarget; -+ operands[2] = GEN_INT (INTVAL (operands[2]) - imm); -+ } -+ " -+) -+ -+(define_insn "*addsi3_aarch64" -+ [(set -+ (match_operand:SI 0 "register_operand" "=rk,rk,rk") -+ (plus:SI -+ (match_operand:SI 1 "register_operand" "%rk,rk,rk") -+ (match_operand:SI 2 "aarch64_plus_operand" "I,r,J")))] -+ "" -+ "@ -+ add\\t%w0, %w1, %2 -+ add\\t%w0, %w1, %w2 -+ sub\\t%w0, %w1, #%n2" -+ [(set_attr "v8type" "alu") -+ (set_attr "mode" "SI")] -+) -+ -+(define_insn "*adddi3_aarch64" -+ [(set -+ (match_operand:DI 0 "register_operand" "=rk,rk,rk,!w") -+ (plus:DI -+ (match_operand:DI 1 "register_operand" "%rk,rk,rk,!w") -+ (match_operand:DI 2 "aarch64_plus_operand" "I,r,J,!w")))] -+ "" -+ "@ -+ add\\t%x0, %x1, %2 -+ add\\t%x0, %x1, %x2 -+ sub\\t%x0, %x1, #%n2 -+ add\\t%d0, %d1, %d2" -+ [(set_attr "v8type" "alu") -+ (set_attr "mode" "DI") -+ (set_attr "simd" "*,*,*,yes")] -+) -+ -+(define_insn "*add3_compare0" -+ [(set (reg:CC_NZ CC_REGNUM) -+ (compare:CC_NZ -+ (plus:GPI (match_operand:GPI 1 "register_operand" "%r,r") -+ (match_operand:GPI 2 "aarch64_plus_operand" "rI,J")) -+ (const_int 0))) -+ (set (match_operand:GPI 0 "register_operand" "=r,r") -+ (plus:GPI (match_dup 1) (match_dup 2)))] -+ "" -+ "@ -+ adds\\t%0, %1, %2 -+ subs\\t%0, %1, #%n2" -+ [(set_attr "v8type" "alus") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*add3nr_compare0" -+ [(set (reg:CC_NZ CC_REGNUM) -+ (compare:CC_NZ -+ (plus:GPI (match_operand:GPI 0 "register_operand" "%r,r") -+ (match_operand:GPI 1 "aarch64_plus_operand" "rI,J")) -+ (const_int 0)))] -+ "" -+ "@ -+ cmn\\t%0, %1 -+ cmp\\t%0, #%n1" -+ [(set_attr "v8type" "alus") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*add__" -+ [(set (match_operand:GPI 0 "register_operand" "=rk") -+ (plus:GPI (ASHIFT:GPI (match_operand:GPI 1 "register_operand" "r") -+ (match_operand:QI 2 "aarch64_shift_imm_" "n")) -+ (match_operand:GPI 3 "register_operand" "r")))] -+ "" -+ "add\\t%0, %3, %1, %2" -+ [(set_attr "v8type" "alu_shift") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*add_mul_imm_" -+ [(set (match_operand:GPI 0 "register_operand" "=rk") -+ (plus:GPI (mult:GPI (match_operand:GPI 1 "register_operand" "r") -+ (match_operand:QI 2 "aarch64_pwr_2_" "n")) -+ (match_operand:GPI 3 "register_operand" "r")))] -+ "" -+ "add\\t%0, %3, %1, lsl %p2" -+ [(set_attr "v8type" "alu_shift") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*add__" -+ [(set (match_operand:GPI 0 "register_operand" "=rk") -+ (plus:GPI (ANY_EXTEND:GPI (match_operand:ALLX 1 "register_operand" "r")) -+ (match_operand:GPI 2 "register_operand" "r")))] -+ "" -+ "add\\t%0, %2, %1, xt" -+ [(set_attr "v8type" "alu_ext") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*add__shft_" -+ [(set (match_operand:GPI 0 "register_operand" "=rk") -+ (plus:GPI (ashift:GPI (ANY_EXTEND:GPI -+ (match_operand:ALLX 1 "register_operand" "r")) -+ (match_operand 2 "aarch64_imm3" "Ui3")) -+ (match_operand:GPI 3 "register_operand" "r")))] -+ "" -+ "add\\t%0, %3, %1, xt %2" -+ [(set_attr "v8type" "alu_ext") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*add__mult_" -+ [(set (match_operand:GPI 0 "register_operand" "=rk") -+ (plus:GPI (mult:GPI (ANY_EXTEND:GPI -+ (match_operand:ALLX 1 "register_operand" "r")) -+ (match_operand 2 "aarch64_pwr_imm3" "Up3")) -+ (match_operand:GPI 3 "register_operand" "r")))] -+ "" -+ "add\\t%0, %3, %1, xt %p2" -+ [(set_attr "v8type" "alu_ext") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*add__multp2" -+ [(set (match_operand:GPI 0 "register_operand" "=rk") -+ (plus:GPI (ANY_EXTRACT:GPI -+ (mult:GPI (match_operand:GPI 1 "register_operand" "r") -+ (match_operand 2 "aarch64_pwr_imm3" "Up3")) -+ (match_operand 3 "const_int_operand" "n") -+ (const_int 0)) -+ (match_operand:GPI 4 "register_operand" "r")))] -+ "aarch64_is_extend_from_extract (mode, operands[2], operands[3])" -+ "add\\t%0, %4, %1, xt%e3 %p2" -+ [(set_attr "v8type" "alu_ext") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*add3_carryin" -+ [(set -+ (match_operand:GPI 0 "register_operand" "=r") -+ (plus:GPI (geu:GPI (reg:CC CC_REGNUM) (const_int 0)) -+ (plus:GPI -+ (match_operand:GPI 1 "register_operand" "r") -+ (match_operand:GPI 2 "register_operand" "r"))))] -+ "" -+ "adc\\t%0, %1, %2" -+ [(set_attr "v8type" "adc") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*add3_carryin_alt1" -+ [(set -+ (match_operand:GPI 0 "register_operand" "=r") -+ (plus:GPI (plus:GPI -+ (match_operand:GPI 1 "register_operand" "r") -+ (match_operand:GPI 2 "register_operand" "r")) -+ (geu:GPI (reg:CC CC_REGNUM) (const_int 0))))] -+ "" -+ "adc\\t%0, %1, %2" -+ [(set_attr "v8type" "adc") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*add3_carryin_alt2" -+ [(set -+ (match_operand:GPI 0 "register_operand" "=r") -+ (plus:GPI (plus:GPI -+ (geu:GPI (reg:CC CC_REGNUM) (const_int 0)) -+ (match_operand:GPI 1 "register_operand" "r")) -+ (match_operand:GPI 2 "register_operand" "r")))] -+ "" -+ "adc\\t%0, %1, %2" -+ [(set_attr "v8type" "adc") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*add3_carryin_alt3" -+ [(set -+ (match_operand:GPI 0 "register_operand" "=r") -+ (plus:GPI (plus:GPI -+ (geu:GPI (reg:CC CC_REGNUM) (const_int 0)) -+ (match_operand:GPI 2 "register_operand" "r")) -+ (match_operand:GPI 1 "register_operand" "r")))] -+ "" -+ "adc\\t%0, %1, %2" -+ [(set_attr "v8type" "adc") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*add_uxt_multp2" -+ [(set (match_operand:GPI 0 "register_operand" "=rk") -+ (plus:GPI (and:GPI -+ (mult:GPI (match_operand:GPI 1 "register_operand" "r") -+ (match_operand 2 "aarch64_pwr_imm3" "Up3")) -+ (match_operand 3 "const_int_operand" "n")) -+ (match_operand:GPI 4 "register_operand" "r")))] -+ "aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), INTVAL (operands[3])) != 0" -+ "* -+ operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), -+ INTVAL (operands[3]))); -+ return \"add\t%0, %4, %1, uxt%e3 %p2\";" -+ [(set_attr "v8type" "alu_ext") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "subsi3" -+ [(set (match_operand:SI 0 "register_operand" "=rk") -+ (minus:SI (match_operand:SI 1 "register_operand" "r") -+ (match_operand:SI 2 "register_operand" "r")))] -+ "" -+ "sub\\t%w0, %w1, %w2" -+ [(set_attr "v8type" "alu") -+ (set_attr "mode" "SI")] -+) -+ -+(define_insn "subdi3" -+ [(set (match_operand:DI 0 "register_operand" "=rk,!w") -+ (minus:DI (match_operand:DI 1 "register_operand" "r,!w") -+ (match_operand:DI 2 "register_operand" "r,!w")))] -+ "" -+ "@ -+ sub\\t%x0, %x1, %x2 -+ sub\\t%d0, %d1, %d2" -+ [(set_attr "v8type" "alu") -+ (set_attr "mode" "DI") -+ (set_attr "simd" "*,yes")] -+) -+ -+ -+(define_insn "*sub3_compare0" -+ [(set (reg:CC_NZ CC_REGNUM) -+ (compare:CC_NZ (minus:GPI (match_operand:GPI 1 "register_operand" "r") -+ (match_operand:GPI 2 "register_operand" "r")) -+ (const_int 0))) -+ (set (match_operand:GPI 0 "register_operand" "=r") -+ (minus:GPI (match_dup 1) (match_dup 2)))] -+ "" -+ "subs\\t%0, %1, %2" -+ [(set_attr "v8type" "alus") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*sub__" -+ [(set (match_operand:GPI 0 "register_operand" "=rk") -+ (minus:GPI (match_operand:GPI 3 "register_operand" "r") -+ (ASHIFT:GPI -+ (match_operand:GPI 1 "register_operand" "r") -+ (match_operand:QI 2 "aarch64_shift_imm_" "n"))))] -+ "" -+ "sub\\t%0, %3, %1, %2" -+ [(set_attr "v8type" "alu_shift") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*sub_mul_imm_" -+ [(set (match_operand:GPI 0 "register_operand" "=rk") -+ (minus:GPI (match_operand:GPI 3 "register_operand" "r") -+ (mult:GPI -+ (match_operand:GPI 1 "register_operand" "r") -+ (match_operand:QI 2 "aarch64_pwr_2_" "n"))))] -+ "" -+ "sub\\t%0, %3, %1, lsl %p2" -+ [(set_attr "v8type" "alu_shift") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*sub__" -+ [(set (match_operand:GPI 0 "register_operand" "=rk") -+ (minus:GPI (match_operand:GPI 1 "register_operand" "r") -+ (ANY_EXTEND:GPI -+ (match_operand:ALLX 2 "register_operand" "r"))))] -+ "" -+ "sub\\t%0, %1, %2, xt" -+ [(set_attr "v8type" "alu_ext") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*sub__shft_" -+ [(set (match_operand:GPI 0 "register_operand" "=rk") -+ (minus:GPI (match_operand:GPI 1 "register_operand" "r") -+ (ashift:GPI (ANY_EXTEND:GPI -+ (match_operand:ALLX 2 "register_operand" "r")) -+ (match_operand 3 "aarch64_imm3" "Ui3"))))] -+ "" -+ "sub\\t%0, %1, %2, xt %3" -+ [(set_attr "v8type" "alu_ext") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*sub__multp2" -+ [(set (match_operand:GPI 0 "register_operand" "=rk") -+ (minus:GPI (match_operand:GPI 4 "register_operand" "r") -+ (ANY_EXTRACT:GPI -+ (mult:GPI (match_operand:GPI 1 "register_operand" "r") -+ (match_operand 2 "aarch64_pwr_imm3" "Up3")) -+ (match_operand 3 "const_int_operand" "n") -+ (const_int 0))))] -+ "aarch64_is_extend_from_extract (mode, operands[2], operands[3])" -+ "sub\\t%0, %4, %1, xt%e3 %p2" -+ [(set_attr "v8type" "alu_ext") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*sub_uxt_multp2" -+ [(set (match_operand:GPI 0 "register_operand" "=rk") -+ (minus:GPI (match_operand:GPI 4 "register_operand" "r") -+ (and:GPI -+ (mult:GPI (match_operand:GPI 1 "register_operand" "r") -+ (match_operand 2 "aarch64_pwr_imm3" "Up3")) -+ (match_operand 3 "const_int_operand" "n"))))] -+ "aarch64_uxt_size (exact_log2 (INTVAL (operands[2])),INTVAL (operands[3])) != 0" -+ "* -+ operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), -+ INTVAL (operands[3]))); -+ return \"sub\t%0, %4, %1, uxt%e3 %p2\";" -+ [(set_attr "v8type" "alu_ext") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "neg2" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (neg:GPI (match_operand:GPI 1 "register_operand" "r")))] -+ "" -+ "neg\\t%0, %1" -+ [(set_attr "v8type" "alu") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*neg2_compare0" -+ [(set (reg:CC_NZ CC_REGNUM) -+ (compare:CC_NZ (neg:GPI (match_operand:GPI 1 "register_operand" "r")) -+ (const_int 0))) -+ (set (match_operand:GPI 0 "register_operand" "=r") -+ (neg:GPI (match_dup 1)))] -+ "" -+ "negs\\t%0, %1" -+ [(set_attr "v8type" "alus") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*neg__2" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (neg:GPI (ASHIFT:GPI -+ (match_operand:GPI 1 "register_operand" "r") -+ (match_operand:QI 2 "aarch64_shift_imm_" "n"))))] -+ "" -+ "neg\\t%0, %1, %2" -+ [(set_attr "v8type" "alu_shift") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*neg_mul_imm_2" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (neg:GPI (mult:GPI -+ (match_operand:GPI 1 "register_operand" "r") -+ (match_operand:QI 2 "aarch64_pwr_2_" "n"))))] -+ "" -+ "neg\\t%0, %1, lsl %p2" -+ [(set_attr "v8type" "alu_shift") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "mul3" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (mult:GPI (match_operand:GPI 1 "register_operand" "r") -+ (match_operand:GPI 2 "register_operand" "r")))] -+ "" -+ "mul\\t%0, %1, %2" -+ [(set_attr "v8type" "mult") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*madd" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (plus:GPI (mult:GPI (match_operand:GPI 1 "register_operand" "r") -+ (match_operand:GPI 2 "register_operand" "r")) -+ (match_operand:GPI 3 "register_operand" "r")))] -+ "" -+ "madd\\t%0, %1, %2, %3" -+ [(set_attr "v8type" "madd") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*msub" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (minus:GPI (match_operand:GPI 3 "register_operand" "r") -+ (mult:GPI (match_operand:GPI 1 "register_operand" "r") -+ (match_operand:GPI 2 "register_operand" "r"))))] -+ -+ "" -+ "msub\\t%0, %1, %2, %3" -+ [(set_attr "v8type" "madd") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*mul_neg" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (mult:GPI (neg:GPI (match_operand:GPI 1 "register_operand" "r")) -+ (match_operand:GPI 2 "register_operand" "r")))] -+ -+ "" -+ "mneg\\t%0, %1, %2" -+ [(set_attr "v8type" "mult") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "mulsidi3" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (mult:DI (ANY_EXTEND:DI (match_operand:SI 1 "register_operand" "r")) -+ (ANY_EXTEND:DI (match_operand:SI 2 "register_operand" "r"))))] -+ "" -+ "mull\\t%0, %w1, %w2" -+ [(set_attr "v8type" "mull") -+ (set_attr "mode" "DI")] -+) -+ -+(define_insn "maddsidi4" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (plus:DI (mult:DI -+ (ANY_EXTEND:DI (match_operand:SI 1 "register_operand" "r")) -+ (ANY_EXTEND:DI (match_operand:SI 2 "register_operand" "r"))) -+ (match_operand:DI 3 "register_operand" "r")))] -+ "" -+ "maddl\\t%0, %w1, %w2, %3" -+ [(set_attr "v8type" "maddl") -+ (set_attr "mode" "DI")] -+) -+ -+(define_insn "msubsidi4" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (minus:DI -+ (match_operand:DI 3 "register_operand" "r") -+ (mult:DI (ANY_EXTEND:DI (match_operand:SI 1 "register_operand" "r")) -+ (ANY_EXTEND:DI -+ (match_operand:SI 2 "register_operand" "r")))))] -+ "" -+ "msubl\\t%0, %w1, %w2, %3" -+ [(set_attr "v8type" "maddl") -+ (set_attr "mode" "DI")] -+) -+ -+(define_insn "*mulsidi_neg" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (mult:DI (neg:DI -+ (ANY_EXTEND:DI (match_operand:SI 1 "register_operand" "r"))) -+ (ANY_EXTEND:DI (match_operand:SI 2 "register_operand" "r"))))] -+ "" -+ "mnegl\\t%0, %w1, %w2" -+ [(set_attr "v8type" "mull") -+ (set_attr "mode" "DI")] -+) -+ -+(define_insn "muldi3_highpart" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (truncate:DI -+ (lshiftrt:TI -+ (mult:TI -+ (ANY_EXTEND:TI (match_operand:DI 1 "register_operand" "r")) -+ (ANY_EXTEND:TI (match_operand:DI 2 "register_operand" "r"))) -+ (const_int 64))))] -+ "" -+ "mulh\\t%0, %1, %2" -+ [(set_attr "v8type" "mulh") -+ (set_attr "mode" "DI")] -+) -+ -+(define_insn "div3" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (ANY_DIV:GPI (match_operand:GPI 1 "register_operand" "r") -+ (match_operand:GPI 2 "register_operand" "r")))] -+ "" -+ "div\\t%0, %1, %2" -+ [(set_attr "v8type" "div") -+ (set_attr "mode" "")] -+) -+ -+;; ------------------------------------------------------------------- -+;; Comparison insns -+;; ------------------------------------------------------------------- -+ -+(define_insn "*cmp" -+ [(set (reg:CC CC_REGNUM) -+ (compare:CC (match_operand:GPI 0 "register_operand" "r,r") -+ (match_operand:GPI 1 "aarch64_plus_operand" "rI,J")))] -+ "" -+ "@ -+ cmp\\t%0, %1 -+ cmn\\t%0, #%n1" -+ [(set_attr "v8type" "alus") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*cmp" -+ [(set (reg:CCFP CC_REGNUM) -+ (compare:CCFP (match_operand:GPF 0 "register_operand" "w,w") -+ (match_operand:GPF 1 "aarch64_fp_compare_operand" "Y,w")))] -+ "TARGET_FLOAT" -+ "@ -+ fcmp\\t%0, #0.0 -+ fcmp\\t%0, %1" -+ [(set_attr "v8type" "fcmp") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*cmpe" -+ [(set (reg:CCFPE CC_REGNUM) -+ (compare:CCFPE (match_operand:GPF 0 "register_operand" "w,w") -+ (match_operand:GPF 1 "aarch64_fp_compare_operand" "Y,w")))] -+ "TARGET_FLOAT" -+ "@ -+ fcmpe\\t%0, #0.0 -+ fcmpe\\t%0, %1" -+ [(set_attr "v8type" "fcmp") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*cmp_swp__reg" -+ [(set (reg:CC_SWP CC_REGNUM) -+ (compare:CC_SWP (ASHIFT:GPI -+ (match_operand:GPI 0 "register_operand" "r") -+ (match_operand:QI 1 "aarch64_shift_imm_" "n")) -+ (match_operand:GPI 2 "aarch64_reg_or_zero" "rZ")))] -+ "" -+ "cmp\\t%2, %0, %1" -+ [(set_attr "v8type" "alus_shift") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*cmp_swp__reg" -+ [(set (reg:CC_SWP CC_REGNUM) -+ (compare:CC_SWP (ANY_EXTEND:GPI -+ (match_operand:ALLX 0 "register_operand" "r")) -+ (match_operand:GPI 1 "register_operand" "r")))] -+ "" -+ "cmp\\t%1, %0, xt" -+ [(set_attr "v8type" "alus_ext") -+ (set_attr "mode" "")] -+) -+ -+ -+;; ------------------------------------------------------------------- -+;; Store-flag and conditional select insns -+;; ------------------------------------------------------------------- -+ -+(define_expand "cstore4" -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operator:SI 1 "aarch64_comparison_operator" -+ [(match_operand:GPI 2 "register_operand" "") -+ (match_operand:GPI 3 "aarch64_plus_operand" "")]))] -+ "" -+ " -+ operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2], -+ operands[3]); -+ operands[3] = const0_rtx; -+ " -+) -+ -+(define_expand "cstore4" -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operator:SI 1 "aarch64_comparison_operator" -+ [(match_operand:GPF 2 "register_operand" "") -+ (match_operand:GPF 3 "register_operand" "")]))] -+ "" -+ " -+ operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2], -+ operands[3]); -+ operands[3] = const0_rtx; -+ " -+) -+ -+(define_insn "*cstore_insn" -+ [(set (match_operand:ALLI 0 "register_operand" "=r") -+ (match_operator:ALLI 1 "aarch64_comparison_operator" -+ [(match_operand 2 "cc_register" "") (const_int 0)]))] -+ "" -+ "cset\\t%0, %m1" -+ [(set_attr "v8type" "csel") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*cstore_neg" -+ [(set (match_operand:ALLI 0 "register_operand" "=r") -+ (neg:ALLI (match_operator:ALLI 1 "aarch64_comparison_operator" -+ [(match_operand 2 "cc_register" "") (const_int 0)])))] -+ "" -+ "csetm\\t%0, %m1" -+ [(set_attr "v8type" "csel") -+ (set_attr "mode" "")] -+) -+ -+(define_expand "cmov6" -+ [(set (match_operand:GPI 0 "register_operand" "") -+ (if_then_else:GPI -+ (match_operator 1 "aarch64_comparison_operator" -+ [(match_operand:GPI 2 "register_operand" "") -+ (match_operand:GPI 3 "aarch64_plus_operand" "")]) -+ (match_operand:GPI 4 "register_operand" "") -+ (match_operand:GPI 5 "register_operand" "")))] -+ "" -+ " -+ operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2], -+ operands[3]); -+ operands[3] = const0_rtx; -+ " -+) -+ -+(define_expand "cmov6" -+ [(set (match_operand:GPF 0 "register_operand" "") -+ (if_then_else:GPF -+ (match_operator 1 "aarch64_comparison_operator" -+ [(match_operand:GPF 2 "register_operand" "") -+ (match_operand:GPF 3 "register_operand" "")]) -+ (match_operand:GPF 4 "register_operand" "") -+ (match_operand:GPF 5 "register_operand" "")))] -+ "" -+ " -+ operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2], -+ operands[3]); -+ operands[3] = const0_rtx; -+ " -+) -+ -+(define_insn "*cmov_insn" -+ [(set (match_operand:ALLI 0 "register_operand" "=r,r,r,r") -+ (if_then_else:ALLI -+ (match_operator 1 "aarch64_comparison_operator" -+ [(match_operand 2 "cc_register" "") (const_int 0)]) -+ (match_operand:ALLI 3 "aarch64_reg_zero_or_m1" "rZ,rZ,UsM,UsM") -+ (match_operand:ALLI 4 "aarch64_reg_zero_or_m1" "rZ,UsM,rZ,UsM")))] -+ "" -+ ;; Final alternative should be unreachable, but included for completeness -+ "@ -+ csel\\t%0, %3, %4, %m1 -+ csinv\\t%0, %3, zr, %m1 -+ csinv\\t%0, %4, zr, %M1 -+ mov\\t%0, -1" -+ [(set_attr "v8type" "csel") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*cmov_insn" -+ [(set (match_operand:GPF 0 "register_operand" "=w") -+ (if_then_else:GPF -+ (match_operator 1 "aarch64_comparison_operator" -+ [(match_operand 2 "cc_register" "") (const_int 0)]) -+ (match_operand:GPF 3 "register_operand" "w") -+ (match_operand:GPF 4 "register_operand" "w")))] -+ "TARGET_FLOAT" -+ "fcsel\\t%0, %3, %4, %m1" -+ [(set_attr "v8type" "fcsel") -+ (set_attr "mode" "")] -+) -+ -+(define_expand "movcc" -+ [(set (match_operand:ALLI 0 "register_operand" "") -+ (if_then_else:ALLI (match_operand 1 "aarch64_comparison_operator" "") -+ (match_operand:ALLI 2 "register_operand" "") -+ (match_operand:ALLI 3 "register_operand" "")))] -+ "" -+ { -+ rtx ccreg; -+ enum rtx_code code = GET_CODE (operands[1]); -+ -+ if (code == UNEQ || code == LTGT) -+ FAIL; -+ -+ ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0), -+ XEXP (operands[1], 1)); -+ operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx); -+ } -+) -+ -+(define_expand "movcc" -+ [(set (match_operand:GPI 0 "register_operand" "") -+ (if_then_else:GPI (match_operand 1 "aarch64_comparison_operator" "") -+ (match_operand:GPF 2 "register_operand" "") -+ (match_operand:GPF 3 "register_operand" "")))] -+ "" -+ { -+ rtx ccreg; -+ enum rtx_code code = GET_CODE (operands[1]); -+ -+ if (code == UNEQ || code == LTGT) -+ FAIL; -+ -+ ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0), -+ XEXP (operands[1], 1)); -+ operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx); -+ } -+) -+ -+(define_insn "*csinc2_insn" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (plus:GPI (match_operator:GPI 2 "aarch64_comparison_operator" -+ [(match_operand:CC 3 "cc_register" "") (const_int 0)]) -+ (match_operand:GPI 1 "register_operand" "r")))] -+ "" -+ "csinc\\t%0, %1, %1, %M2" -+ [(set_attr "v8type" "csel") -+ (set_attr "mode" "")]) -+ -+(define_insn "csinc3_insn" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (if_then_else:GPI -+ (match_operator:GPI 1 "aarch64_comparison_operator" -+ [(match_operand:CC 2 "cc_register" "") (const_int 0)]) -+ (plus:GPI (match_operand:GPI 3 "register_operand" "r") -+ (const_int 1)) -+ (match_operand:GPI 4 "aarch64_reg_or_zero" "rZ")))] -+ "" -+ "csinc\\t%0, %4, %3, %M1" -+ [(set_attr "v8type" "csel") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*csinv3_insn" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (if_then_else:GPI -+ (match_operator:GPI 1 "aarch64_comparison_operator" -+ [(match_operand:CC 2 "cc_register" "") (const_int 0)]) -+ (not:GPI (match_operand:GPI 3 "register_operand" "r")) -+ (match_operand:GPI 4 "aarch64_reg_or_zero" "rZ")))] -+ "" -+ "csinv\\t%0, %4, %3, %M1" -+ [(set_attr "v8type" "csel") -+ (set_attr "mode" "")]) -+ -+(define_insn "*csneg3_insn" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (if_then_else:GPI -+ (match_operator:GPI 1 "aarch64_comparison_operator" -+ [(match_operand:CC 2 "cc_register" "") (const_int 0)]) -+ (neg:GPI (match_operand:GPI 3 "register_operand" "r")) -+ (match_operand:GPI 4 "aarch64_reg_or_zero" "rZ")))] -+ "" -+ "csneg\\t%0, %4, %3, %M1" -+ [(set_attr "v8type" "csel") -+ (set_attr "mode" "")]) -+ -+;; ------------------------------------------------------------------- -+;; Logical operations -+;; ------------------------------------------------------------------- -+ -+(define_insn "3" -+ [(set (match_operand:GPI 0 "register_operand" "=r,r") -+ (LOGICAL:GPI (match_operand:GPI 1 "register_operand" "%r,r") -+ (match_operand:GPI 2 "aarch64_logical_operand" "r,")))] -+ "" -+ "\\t%0, %1, %2" -+ [(set_attr "v8type" "logic") -+ (set_attr "mode" "")]) -+ -+(define_insn "*_3" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (LOGICAL:GPI (SHIFT:GPI -+ (match_operand:GPI 1 "register_operand" "r") -+ (match_operand:QI 2 "aarch64_shift_imm_" "n")) -+ (match_operand:GPI 3 "register_operand" "r")))] -+ "" -+ "\\t%0, %3, %1, %2" -+ [(set_attr "v8type" "logic_shift") -+ (set_attr "mode" "")]) -+ -+(define_insn "one_cmpl2" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (not:GPI (match_operand:GPI 1 "register_operand" "r")))] -+ "" -+ "mvn\\t%0, %1" -+ [(set_attr "v8type" "logic") -+ (set_attr "mode" "")]) -+ -+(define_insn "*one_cmpl_2" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (not:GPI (SHIFT:GPI (match_operand:GPI 1 "register_operand" "r") -+ (match_operand:QI 2 "aarch64_shift_imm_" "n"))))] -+ "" -+ "mvn\\t%0, %1, %2" -+ [(set_attr "v8type" "logic_shift") -+ (set_attr "mode" "")]) -+ -+(define_insn "*_one_cmpl3" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (LOGICAL:GPI (not:GPI -+ (match_operand:GPI 1 "register_operand" "r")) -+ (match_operand:GPI 2 "register_operand" "r")))] -+ "" -+ "\\t%0, %2, %1" -+ [(set_attr "v8type" "logic") -+ (set_attr "mode" "")]) -+ -+(define_insn "*_one_cmpl_3" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (LOGICAL:GPI (not:GPI -+ (SHIFT:GPI -+ (match_operand:GPI 1 "register_operand" "r") -+ (match_operand:QI 2 "aarch64_shift_imm_" "n"))) -+ (match_operand:GPI 3 "register_operand" "r")))] -+ "" -+ "\\t%0, %3, %1, %2" -+ [(set_attr "v8type" "logic_shift") -+ (set_attr "mode" "")]) -+ -+(define_insn "clz2" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (clz:GPI (match_operand:GPI 1 "register_operand" "r")))] -+ "" -+ "clz\\t%0, %1" -+ [(set_attr "v8type" "clz") -+ (set_attr "mode" "")]) -+ -+(define_expand "ffs2" -+ [(match_operand:GPI 0 "register_operand") -+ (match_operand:GPI 1 "register_operand")] -+ "" -+ { -+ rtx ccreg = aarch64_gen_compare_reg (EQ, operands[1], const0_rtx); -+ rtx x = gen_rtx_NE (VOIDmode, ccreg, const0_rtx); -+ -+ emit_insn (gen_rbit2 (operands[0], operands[1])); -+ emit_insn (gen_clz2 (operands[0], operands[0])); -+ emit_insn (gen_csinc3_insn (operands[0], x, ccreg, operands[0], const0_rtx)); -+ DONE; -+ } -+) -+ -+(define_insn "clrsb2" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (unspec:GPI [(match_operand:GPI 1 "register_operand" "r")] UNSPEC_CLS))] -+ "" -+ "cls\\t%0, %1" -+ [(set_attr "v8type" "clz") -+ (set_attr "mode" "")]) -+ -+(define_insn "rbit2" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (unspec:GPI [(match_operand:GPI 1 "register_operand" "r")] UNSPEC_RBIT))] -+ "" -+ "rbit\\t%0, %1" -+ [(set_attr "v8type" "rbit") -+ (set_attr "mode" "")]) -+ -+(define_expand "ctz2" -+ [(match_operand:GPI 0 "register_operand") -+ (match_operand:GPI 1 "register_operand")] -+ "" -+ { -+ emit_insn (gen_rbit2 (operands[0], operands[1])); -+ emit_insn (gen_clz2 (operands[0], operands[0])); -+ DONE; -+ } -+) -+ -+(define_insn "*and3nr_compare0" -+ [(set (reg:CC CC_REGNUM) -+ (compare:CC -+ (and:GPI (match_operand:GPI 0 "register_operand" "%r,r") -+ (match_operand:GPI 1 "aarch64_logical_operand" "r,")) -+ (const_int 0)))] -+ "" -+ "tst\\t%0, %1" -+ [(set_attr "v8type" "logics") -+ (set_attr "mode" "")]) -+ -+(define_insn "*and_3nr_compare0" -+ [(set (reg:CC CC_REGNUM) -+ (compare:CC -+ (and:GPI (SHIFT:GPI -+ (match_operand:GPI 0 "register_operand" "r") -+ (match_operand:QI 1 "aarch64_shift_imm_" "n")) -+ (match_operand:GPI 2 "register_operand" "r")) -+ (const_int 0)))] -+ "" -+ "tst\\t%2, %0, %1" -+ [(set_attr "v8type" "logics_shift") -+ (set_attr "mode" "")]) -+ -+;; ------------------------------------------------------------------- -+;; Shifts -+;; ------------------------------------------------------------------- -+ -+(define_expand "3" -+ [(set (match_operand:GPI 0 "register_operand") -+ (ASHIFT:GPI (match_operand:GPI 1 "register_operand") -+ (match_operand:QI 2 "nonmemory_operand")))] -+ "" -+ { -+ if (CONST_INT_P (operands[2])) -+ { -+ operands[2] = GEN_INT (INTVAL (operands[2]) -+ & (GET_MODE_BITSIZE (mode) - 1)); -+ -+ if (operands[2] == const0_rtx) -+ { -+ emit_insn (gen_mov (operands[0], operands[1])); -+ DONE; -+ } -+ } -+ } -+) -+ -+(define_expand "ashl3" -+ [(set (match_operand:SHORT 0 "register_operand") -+ (ashift:SHORT (match_operand:SHORT 1 "register_operand") -+ (match_operand:QI 2 "nonmemory_operand")))] -+ "" -+ { -+ if (CONST_INT_P (operands[2])) -+ { -+ operands[2] = GEN_INT (INTVAL (operands[2]) -+ & (GET_MODE_BITSIZE (mode) - 1)); -+ -+ if (operands[2] == const0_rtx) -+ { -+ emit_insn (gen_mov (operands[0], operands[1])); -+ DONE; -+ } -+ } -+ } -+) -+ -+(define_expand "rotr3" -+ [(set (match_operand:GPI 0 "register_operand") -+ (rotatert:GPI (match_operand:GPI 1 "register_operand") -+ (match_operand:QI 2 "nonmemory_operand")))] -+ "" -+ { -+ if (CONST_INT_P (operands[2])) -+ { -+ operands[2] = GEN_INT (INTVAL (operands[2]) -+ & (GET_MODE_BITSIZE (mode) - 1)); -+ -+ if (operands[2] == const0_rtx) -+ { -+ emit_insn (gen_mov (operands[0], operands[1])); -+ DONE; -+ } -+ } -+ } -+) -+ -+(define_expand "rotl3" -+ [(set (match_operand:GPI 0 "register_operand") -+ (rotatert:GPI (match_operand:GPI 1 "register_operand") -+ (match_operand:QI 2 "nonmemory_operand")))] -+ "" -+ { -+ /* (SZ - cnt) % SZ == -cnt % SZ */ -+ if (CONST_INT_P (operands[2])) -+ { -+ operands[2] = GEN_INT ((-INTVAL (operands[2])) -+ & (GET_MODE_BITSIZE (mode) - 1)); -+ if (operands[2] == const0_rtx) -+ { -+ emit_insn (gen_mov (operands[0], operands[1])); -+ DONE; -+ } -+ } -+ else -+ operands[2] = expand_simple_unop (QImode, NEG, operands[2], -+ NULL_RTX, 1); -+ } -+) -+ -+(define_insn "*3_insn" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (SHIFT:GPI -+ (match_operand:GPI 1 "register_operand" "r") -+ (match_operand:QI 2 "aarch64_reg_or_shift_imm_" "rUs")))] -+ "" -+ "\\t%0, %1, %2" -+ [(set_attr "v8type" "shift") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*ashl3_insn" -+ [(set (match_operand:SHORT 0 "register_operand" "=r") -+ (ashift:SHORT (match_operand:SHORT 1 "register_operand" "r") -+ (match_operand:QI 2 "aarch64_reg_or_shift_imm_si" "rUss")))] -+ "" -+ "lsl\\t%0, %1, %2" -+ [(set_attr "v8type" "shift") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*3_insn" -+ [(set (match_operand:SHORT 0 "register_operand" "=r") -+ (ASHIFT:SHORT (match_operand:SHORT 1 "register_operand" "r") -+ (match_operand 2 "const_int_operand" "n")))] -+ "UINTVAL (operands[2]) < GET_MODE_BITSIZE (mode)" -+{ -+ operands[3] = GEN_INT ( - UINTVAL (operands[2])); -+ return "\t%w0, %w1, %2, %3"; -+} -+ [(set_attr "v8type" "bfm") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*_ashl" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (ANY_EXTEND:GPI -+ (ashift:SHORT (match_operand:SHORT 1 "register_operand" "r") -+ (match_operand 2 "const_int_operand" "n"))))] -+ "UINTVAL (operands[2]) < GET_MODE_BITSIZE (mode)" -+{ -+ operands[3] = GEN_INT ( - UINTVAL (operands[2])); -+ return "bfiz\t%0, %1, %2, %3"; -+} -+ [(set_attr "v8type" "bfm") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*zero_extend_lshr" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (zero_extend:GPI -+ (lshiftrt:SHORT (match_operand:SHORT 1 "register_operand" "r") -+ (match_operand 2 "const_int_operand" "n"))))] -+ "UINTVAL (operands[2]) < GET_MODE_BITSIZE (mode)" -+{ -+ operands[3] = GEN_INT ( - UINTVAL (operands[2])); -+ return "ubfx\t%0, %1, %2, %3"; -+} -+ [(set_attr "v8type" "bfm") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*extend_ashr" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (sign_extend:GPI -+ (ashiftrt:SHORT (match_operand:SHORT 1 "register_operand" "r") -+ (match_operand 2 "const_int_operand" "n"))))] -+ "UINTVAL (operands[2]) < GET_MODE_BITSIZE (mode)" -+{ -+ operands[3] = GEN_INT ( - UINTVAL (operands[2])); -+ return "sbfx\\t%0, %1, %2, %3"; -+} -+ [(set_attr "v8type" "bfm") -+ (set_attr "mode" "")] -+) -+ -+;; ------------------------------------------------------------------- -+;; Bitfields -+;; ------------------------------------------------------------------- -+ -+(define_expand "" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (ANY_EXTRACT:DI (match_operand:DI 1 "register_operand" "r") -+ (match_operand 2 "const_int_operand" "n") -+ (match_operand 3 "const_int_operand" "n")))] -+ "" -+ "" -+) -+ -+(define_insn "*" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (ANY_EXTRACT:GPI (match_operand:GPI 1 "register_operand" "r") -+ (match_operand 2 "const_int_operand" "n") -+ (match_operand 3 "const_int_operand" "n")))] -+ "" -+ "bfx\\t%0, %1, %3, %2" -+ [(set_attr "v8type" "bfm") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*_shft_" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (ashift:GPI (ANY_EXTEND:GPI -+ (match_operand:ALLX 1 "register_operand" "r")) -+ (match_operand 2 "const_int_operand" "n")))] -+ "" -+ "bfiz\\t%0, %1, %2, #" -+ [(set_attr "v8type" "bfm") -+ (set_attr "mode" "")] -+) -+ -+;; XXX We should match (any_extend (ashift)) here, like (and (ashift)) below -+ -+(define_insn "*andim_ashift_bfiz" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (and:GPI (ashift:GPI (match_operand:GPI 1 "register_operand" "r") -+ (match_operand 2 "const_int_operand" "n")) -+ (match_operand 3 "const_int_operand" "n")))] -+ "exact_log2 ((INTVAL (operands[3]) >> INTVAL (operands[2])) + 1) >= 0 -+ && (INTVAL (operands[3]) & ((1 << INTVAL (operands[2])) - 1)) == 0" -+ "ubfiz\\t%0, %1, %2, %P3" -+ [(set_attr "v8type" "bfm") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "bswap2" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (bswap:GPI (match_operand:GPI 1 "register_operand" "r")))] -+ "" -+ "rev\\t%0, %1" -+ [(set_attr "v8type" "rev") -+ (set_attr "mode" "")] -+) -+ -+;; ------------------------------------------------------------------- -+;; Floating-point intrinsics -+;; ------------------------------------------------------------------- -+ -+;; trunc - nothrow -+ -+(define_insn "btrunc2" -+ [(set (match_operand:GPF 0 "register_operand" "=w") -+ (unspec:GPF [(match_operand:GPF 1 "register_operand" "w")] -+ UNSPEC_FRINTZ))] -+ "TARGET_FLOAT" -+ "frintz\\t%0, %1" -+ [(set_attr "v8type" "frint") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*lbtrunc2" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (FIXUORS:GPI (unspec:GPF [(match_operand:GPF 1 "register_operand" "w")] -+ UNSPEC_FRINTZ)))] -+ "TARGET_FLOAT" -+ "fcvtz\\t%0, %1" -+ [(set_attr "v8type" "fcvtf2i") -+ (set_attr "mode" "") -+ (set_attr "mode2" "")] -+) -+ -+;; ceil - nothrow -+ -+(define_insn "ceil2" -+ [(set (match_operand:GPF 0 "register_operand" "=w") -+ (unspec:GPF [(match_operand:GPF 1 "register_operand" "w")] -+ UNSPEC_FRINTP))] -+ "TARGET_FLOAT" -+ "frintp\\t%0, %1" -+ [(set_attr "v8type" "frint") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "lceil2" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (FIXUORS:GPI (unspec:GPF [(match_operand:GPF 1 "register_operand" "w")] -+ UNSPEC_FRINTP)))] -+ "TARGET_FLOAT" -+ "fcvtp\\t%0, %1" -+ [(set_attr "v8type" "fcvtf2i") -+ (set_attr "mode" "") -+ (set_attr "mode2" "")] -+) -+ -+;; floor - nothrow -+ -+(define_insn "floor2" -+ [(set (match_operand:GPF 0 "register_operand" "=w") -+ (unspec:GPF [(match_operand:GPF 1 "register_operand" "w")] -+ UNSPEC_FRINTM))] -+ "TARGET_FLOAT" -+ "frintm\\t%0, %1" -+ [(set_attr "v8type" "frint") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "lfloor2" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (FIXUORS:GPI (unspec:GPF [(match_operand:GPF 1 "register_operand" "w")] -+ UNSPEC_FRINTM)))] -+ "TARGET_FLOAT" -+ "fcvtm\\t%0, %1" -+ [(set_attr "v8type" "fcvtf2i") -+ (set_attr "mode" "") -+ (set_attr "mode2" "")] -+) -+ -+;; nearbyint - nothrow -+ -+(define_insn "nearbyint2" -+ [(set (match_operand:GPF 0 "register_operand" "=w") -+ (unspec:GPF [(match_operand:GPF 1 "register_operand" "w")] -+ UNSPEC_FRINTI))] -+ "TARGET_FLOAT" -+ "frinti\\t%0, %1" -+ [(set_attr "v8type" "frint") -+ (set_attr "mode" "")] -+) -+ -+;; rint -+ -+(define_insn "rint2" -+ [(set (match_operand:GPF 0 "register_operand" "=w") -+ (unspec:GPF [(match_operand:GPF 1 "register_operand" "w")] -+ UNSPEC_FRINTX))] -+ "TARGET_FLOAT" -+ "frintx\\t%0, %1" -+ [(set_attr "v8type" "frint") -+ (set_attr "mode" "")] -+) -+ -+;; round - nothrow -+ -+(define_insn "round2" -+ [(set (match_operand:GPF 0 "register_operand" "=w") -+ (unspec:GPF [(match_operand:GPF 1 "register_operand" "w")] -+ UNSPEC_FRINTA))] -+ "TARGET_FLOAT" -+ "frinta\\t%0, %1" -+ [(set_attr "v8type" "frint") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "lround2" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (FIXUORS:GPI (unspec:GPF [(match_operand:GPF 1 "register_operand" "w")] -+ UNSPEC_FRINTA)))] -+ "TARGET_FLOAT" -+ "fcvta\\t%0, %1" -+ [(set_attr "v8type" "fcvtf2i") -+ (set_attr "mode" "") -+ (set_attr "mode2" "")] -+) -+ -+;; fma - no throw -+ -+(define_insn "fma4" -+ [(set (match_operand:GPF 0 "register_operand" "=w") -+ (fma:GPF (match_operand:GPF 1 "register_operand" "w") -+ (match_operand:GPF 2 "register_operand" "w") -+ (match_operand:GPF 3 "register_operand" "w")))] -+ "TARGET_FLOAT" -+ "fmadd\\t%0, %1, %2, %3" -+ [(set_attr "v8type" "fmadd") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "fnma4" -+ [(set (match_operand:GPF 0 "register_operand" "=w") -+ (fma:GPF (neg:GPF (match_operand:GPF 1 "register_operand" "w")) -+ (match_operand:GPF 2 "register_operand" "w") -+ (match_operand:GPF 3 "register_operand" "w")))] -+ "TARGET_FLOAT" -+ "fmsub\\t%0, %1, %2, %3" -+ [(set_attr "v8type" "fmadd") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "fms4" -+ [(set (match_operand:GPF 0 "register_operand" "=w") -+ (fma:GPF (match_operand:GPF 1 "register_operand" "w") -+ (match_operand:GPF 2 "register_operand" "w") -+ (neg:GPF (match_operand:GPF 3 "register_operand" "w"))))] -+ "TARGET_FLOAT" -+ "fnmsub\\t%0, %1, %2, %3" -+ [(set_attr "v8type" "fmadd") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "fnms4" -+ [(set (match_operand:GPF 0 "register_operand" "=w") -+ (fma:GPF (neg:GPF (match_operand:GPF 1 "register_operand" "w")) -+ (match_operand:GPF 2 "register_operand" "w") -+ (neg:GPF (match_operand:GPF 3 "register_operand" "w"))))] -+ "TARGET_FLOAT" -+ "fnmadd\\t%0, %1, %2, %3" -+ [(set_attr "v8type" "fmadd") -+ (set_attr "mode" "")] -+) -+ -+;; If signed zeros are ignored, -(a * b + c) = -a * b - c. -+(define_insn "*fnmadd4" -+ [(set (match_operand:GPF 0 "register_operand") -+ (neg:GPF (fma:GPF (match_operand:GPF 1 "register_operand") -+ (match_operand:GPF 2 "register_operand") -+ (match_operand:GPF 3 "register_operand"))))] -+ "!HONOR_SIGNED_ZEROS (mode) && TARGET_FLOAT" -+ "fnmadd\\t%0, %1, %2, %3" -+ [(set_attr "v8type" "fmadd") -+ (set_attr "mode" "")] -+) -+ -+;; ------------------------------------------------------------------- -+;; Floating-point conversions -+;; ------------------------------------------------------------------- -+ -+(define_insn "extendsfdf2" -+ [(set (match_operand:DF 0 "register_operand" "=w") -+ (float_extend:DF (match_operand:SF 1 "register_operand" "w")))] -+ "TARGET_FLOAT" -+ "fcvt\\t%d0, %s1" -+ [(set_attr "v8type" "fcvt") -+ (set_attr "mode" "DF") -+ (set_attr "mode2" "SF")] -+) -+ -+(define_insn "truncdfsf2" -+ [(set (match_operand:SF 0 "register_operand" "=w") -+ (float_truncate:SF (match_operand:DF 1 "register_operand" "w")))] -+ "TARGET_FLOAT" -+ "fcvt\\t%s0, %d1" -+ [(set_attr "v8type" "fcvt") -+ (set_attr "mode" "SF") -+ (set_attr "mode2" "DF")] -+) -+ -+(define_insn "fix_trunc2" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (fix:GPI (match_operand:GPF 1 "register_operand" "w")))] -+ "TARGET_FLOAT" -+ "fcvtzs\\t%0, %1" -+ [(set_attr "v8type" "fcvtf2i") -+ (set_attr "mode" "") -+ (set_attr "mode2" "")] -+) -+ -+(define_insn "fixuns_trunc2" -+ [(set (match_operand:GPI 0 "register_operand" "=r") -+ (unsigned_fix:GPI (match_operand:GPF 1 "register_operand" "w")))] -+ "TARGET_FLOAT" -+ "fcvtzu\\t%0, %1" -+ [(set_attr "v8type" "fcvtf2i") -+ (set_attr "mode" "") -+ (set_attr "mode2" "")] -+) -+ -+(define_insn "float2" -+ [(set (match_operand:GPF 0 "register_operand" "=w") -+ (float:GPF (match_operand:GPI 1 "register_operand" "r")))] -+ "TARGET_FLOAT" -+ "scvtf\\t%0, %1" -+ [(set_attr "v8type" "fcvti2f") -+ (set_attr "mode" "") -+ (set_attr "mode2" "")] -+) -+ -+(define_insn "floatuns2" -+ [(set (match_operand:GPF 0 "register_operand" "=w") -+ (unsigned_float:GPF (match_operand:GPI 1 "register_operand" "r")))] -+ "TARGET_FLOAT" -+ "ucvtf\\t%0, %1" -+ [(set_attr "v8type" "fcvt") -+ (set_attr "mode" "") -+ (set_attr "mode2" "")] -+) -+ -+;; ------------------------------------------------------------------- -+;; Floating-point arithmetic -+;; ------------------------------------------------------------------- -+ -+(define_insn "add3" -+ [(set (match_operand:GPF 0 "register_operand" "=w") -+ (plus:GPF -+ (match_operand:GPF 1 "register_operand" "w") -+ (match_operand:GPF 2 "register_operand" "w")))] -+ "TARGET_FLOAT" -+ "fadd\\t%0, %1, %2" -+ [(set_attr "v8type" "fadd") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "sub3" -+ [(set (match_operand:GPF 0 "register_operand" "=w") -+ (minus:GPF -+ (match_operand:GPF 1 "register_operand" "w") -+ (match_operand:GPF 2 "register_operand" "w")))] -+ "TARGET_FLOAT" -+ "fsub\\t%0, %1, %2" -+ [(set_attr "v8type" "fadd") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "mul3" -+ [(set (match_operand:GPF 0 "register_operand" "=w") -+ (mult:GPF -+ (match_operand:GPF 1 "register_operand" "w") -+ (match_operand:GPF 2 "register_operand" "w")))] -+ "TARGET_FLOAT" -+ "fmul\\t%0, %1, %2" -+ [(set_attr "v8type" "fmul") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "*fnmul3" -+ [(set (match_operand:GPF 0 "register_operand" "=w") -+ (mult:GPF -+ (neg:GPF (match_operand:GPF 1 "register_operand" "w")) -+ (match_operand:GPF 2 "register_operand" "w")))] -+ "TARGET_FLOAT" -+ "fnmul\\t%0, %1, %2" -+ [(set_attr "v8type" "fmul") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "div3" -+ [(set (match_operand:GPF 0 "register_operand" "=w") -+ (div:GPF -+ (match_operand:GPF 1 "register_operand" "w") -+ (match_operand:GPF 2 "register_operand" "w")))] -+ "TARGET_FLOAT" -+ "fdiv\\t%0, %1, %2" -+ [(set_attr "v8type" "fdiv") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "neg2" -+ [(set (match_operand:GPF 0 "register_operand" "=w") -+ (neg:GPF (match_operand:GPF 1 "register_operand" "w")))] -+ "TARGET_FLOAT" -+ "fneg\\t%0, %1" -+ [(set_attr "v8type" "ffarith") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "sqrt2" -+ [(set (match_operand:GPF 0 "register_operand" "=w") -+ (sqrt:GPF (match_operand:GPF 1 "register_operand" "w")))] -+ "TARGET_FLOAT" -+ "fsqrt\\t%0, %1" -+ [(set_attr "v8type" "fsqrt") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "abs2" -+ [(set (match_operand:GPF 0 "register_operand" "=w") -+ (abs:GPF (match_operand:GPF 1 "register_operand" "w")))] -+ "TARGET_FLOAT" -+ "fabs\\t%0, %1" -+ [(set_attr "v8type" "ffarith") -+ (set_attr "mode" "")] -+) -+ -+;; Given that smax/smin do not specify the result when either input is NaN, -+;; we could use either FMAXNM or FMAX for smax, and either FMINNM or FMIN -+;; for smin. -+ -+(define_insn "smax3" -+ [(set (match_operand:GPF 0 "register_operand" "=w") -+ (smax:GPF (match_operand:GPF 1 "register_operand" "w") -+ (match_operand:GPF 2 "register_operand" "w")))] -+ "TARGET_FLOAT" -+ "fmaxnm\\t%0, %1, %2" -+ [(set_attr "v8type" "fminmax") -+ (set_attr "mode" "")] -+) -+ -+(define_insn "smin3" -+ [(set (match_operand:GPF 0 "register_operand" "=w") -+ (smin:GPF (match_operand:GPF 1 "register_operand" "w") -+ (match_operand:GPF 2 "register_operand" "w")))] -+ "TARGET_FLOAT" -+ "fminnm\\t%0, %1, %2" -+ [(set_attr "v8type" "fminmax") -+ (set_attr "mode" "")] -+) -+ -+;; ------------------------------------------------------------------- -+;; Reload support -+;; ------------------------------------------------------------------- -+ -+;; Reload SP+imm where imm cannot be handled by a single ADD instruction. -+;; Must load imm into a scratch register and copy SP to the dest reg before -+;; adding, since SP cannot be used as a source register in an ADD -+;; instruction. -+(define_expand "reload_sp_immediate" -+ [(parallel [(set (match_operand:DI 0 "register_operand" "=r") -+ (match_operand:DI 1 "" "")) -+ (clobber (match_operand:TI 2 "register_operand" "=&r"))])] -+ "" -+ { -+ rtx sp = XEXP (operands[1], 0); -+ rtx val = XEXP (operands[1], 1); -+ unsigned regno = REGNO (operands[2]); -+ rtx scratch = operands[1]; -+ gcc_assert (GET_CODE (operands[1]) == PLUS); -+ gcc_assert (sp == stack_pointer_rtx); -+ gcc_assert (CONST_INT_P (val)); -+ -+ /* It is possible that one of the registers we got for operands[2] -+ might coincide with that of operands[0] (which is why we made -+ it TImode). Pick the other one to use as our scratch. */ -+ if (regno == REGNO (operands[0])) -+ regno++; -+ scratch = gen_rtx_REG (DImode, regno); -+ -+ emit_move_insn (scratch, val); -+ emit_move_insn (operands[0], sp); -+ emit_insn (gen_adddi3 (operands[0], operands[0], scratch)); -+ DONE; -+ } -+) -+ -+(define_expand "aarch64_reload_mov" -+ [(set (match_operand:TX 0 "register_operand" "=w") -+ (match_operand:TX 1 "register_operand" "w")) -+ (clobber (match_operand:DI 2 "register_operand" "=&r")) -+ ] -+ "" -+ { -+ rtx op0 = simplify_gen_subreg (TImode, operands[0], mode, 0); -+ rtx op1 = simplify_gen_subreg (TImode, operands[1], mode, 0); -+ gen_aarch64_movtilow_tilow (op0, op1); -+ gen_aarch64_movdi_tihigh (operands[2], op1); -+ gen_aarch64_movtihigh_di (op0, operands[2]); -+ DONE; -+ } -+) -+ -+;; The following secondary reload helpers patterns are invoked -+;; after or during reload as we don't want these patterns to start -+;; kicking in during the combiner. -+ -+(define_insn "aarch64_movdi_tilow" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (truncate:DI (match_operand:TI 1 "register_operand" "w")))] -+ "reload_completed || reload_in_progress" -+ "fmov\\t%x0, %d1" -+ [(set_attr "v8type" "fmovf2i") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4") -+ ]) -+ -+(define_insn "aarch64_movdi_tihigh" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (truncate:DI -+ (lshiftrt:TI (match_operand:TI 1 "register_operand" "w") -+ (const_int 64))))] -+ "reload_completed || reload_in_progress" -+ "fmov\\t%x0, %1.d[1]" -+ [(set_attr "v8type" "fmovf2i") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4") -+ ]) -+ -+(define_insn "aarch64_movtihigh_di" -+ [(set (zero_extract:TI (match_operand:TI 0 "register_operand" "+w") -+ (const_int 64) (const_int 64)) -+ (zero_extend:TI (match_operand:DI 1 "register_operand" "r")))] -+ "reload_completed || reload_in_progress" -+ "fmov\\t%0.d[1], %x1" -+ -+ [(set_attr "v8type" "fmovi2f") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4") -+ ]) -+ -+(define_insn "aarch64_movtilow_di" -+ [(set (match_operand:TI 0 "register_operand" "=w") -+ (zero_extend:TI (match_operand:DI 1 "register_operand" "r")))] -+ "reload_completed || reload_in_progress" -+ "fmov\\t%d0, %x1" -+ -+ [(set_attr "v8type" "fmovi2f") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4") -+ ]) -+ -+(define_insn "aarch64_movtilow_tilow" -+ [(set (match_operand:TI 0 "register_operand" "=w") -+ (zero_extend:TI -+ (truncate:DI (match_operand:TI 1 "register_operand" "w"))))] -+ "reload_completed || reload_in_progress" -+ "fmov\\t%d0, %d1" -+ -+ [(set_attr "v8type" "fmovi2f") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4") -+ ]) -+ -+;; There is a deliberate reason why the parameters of high and lo_sum's -+;; don't have modes for ADRP and ADD instructions. This is to allow high -+;; and lo_sum's to be used with the labels defining the jump tables in -+;; rodata section. -+ -+(define_insn "add_losym" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (lo_sum:DI (match_operand:DI 1 "register_operand" "r") -+ (match_operand 2 "aarch64_valid_symref" "S")))] -+ "" -+ "add\\t%0, %1, :lo12:%2" -+ [(set_attr "v8type" "alu") -+ (set_attr "mode" "DI")] -+ -+) -+ -+(define_insn "ldr_got_small" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (unspec:DI [(mem:DI (lo_sum:DI -+ (match_operand:DI 1 "register_operand" "r") -+ (match_operand:DI 2 "aarch64_valid_symref" "S")))] -+ UNSPEC_GOTSMALLPIC))] -+ "" -+ "ldr\\t%0, [%1, #:got_lo12:%a2]" -+ [(set_attr "v8type" "load1") -+ (set_attr "mode" "DI")] -+) -+ -+(define_insn "aarch64_load_tp_hard" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (unspec:DI [(const_int 0)] UNSPEC_TLS))] -+ "" -+ "mrs\\t%0, tpidr_el0" -+ [(set_attr "v8type" "mrs") -+ (set_attr "mode" "DI")] -+) -+ -+;; The TLS ABI specifically requires that the compiler does not schedule -+;; instructions in the TLS stubs, in order to enable linker relaxation. -+;; Therefore we treat the stubs as an atomic sequence. -+(define_expand "tlsgd_small" -+ [(parallel [(set (match_operand 0 "register_operand" "") -+ (call (mem:DI (match_dup 2)) (const_int 1))) -+ (unspec:DI [(match_operand:DI 1 "aarch64_valid_symref" "")] UNSPEC_GOTSMALLTLS) -+ (clobber (reg:DI LR_REGNUM))])] -+ "" -+{ -+ operands[2] = aarch64_tls_get_addr (); -+}) -+ -+(define_insn "*tlsgd_small" -+ [(set (match_operand 0 "register_operand" "") -+ (call (mem:DI (match_operand:DI 2 "" "")) (const_int 1))) -+ (unspec:DI [(match_operand:DI 1 "aarch64_valid_symref" "S")] UNSPEC_GOTSMALLTLS) -+ (clobber (reg:DI LR_REGNUM)) -+ ] -+ "" -+ "adrp\\tx0, %A1\;add\\tx0, x0, %L1\;bl\\t%2\;nop" -+ [(set_attr "v8type" "call") -+ (set_attr "length" "16")]) -+ -+(define_insn "tlsie_small" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (unspec:DI [(match_operand:DI 1 "aarch64_tls_ie_symref" "S")] -+ UNSPEC_GOTSMALLTLS))] -+ "" -+ "adrp\\t%0, %A1\;ldr\\t%0, [%0, #%L1]" -+ [(set_attr "v8type" "load1") -+ (set_attr "mode" "DI") -+ (set_attr "length" "8")] -+) -+ -+(define_insn "tlsle_small" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (unspec:DI [(match_operand:DI 1 "register_operand" "r") -+ (match_operand:DI 2 "aarch64_tls_le_symref" "S")] -+ UNSPEC_GOTSMALLTLS))] -+ "" -+ "add\\t%0, %1, #%G2\;add\\t%0, %0, #%L2" -+ [(set_attr "v8type" "alu") -+ (set_attr "mode" "DI") -+ (set_attr "length" "8")] -+) -+ -+(define_insn "tlsdesc_small" -+ [(set (reg:DI R0_REGNUM) -+ (unspec:DI [(match_operand:DI 0 "aarch64_valid_symref" "S")] -+ UNSPEC_TLSDESC)) -+ (clobber (reg:DI LR_REGNUM)) -+ (clobber (match_scratch:DI 1 "=r"))] -+ "TARGET_TLS_DESC" -+ "adrp\\tx0, %A0\;ldr\\t%1, [x0, #%L0]\;add\\tx0, x0, %L0\;.tlsdesccall\\t%0\;blr\\t%1" -+ [(set_attr "v8type" "call") -+ (set_attr "length" "16")]) -+ -+(define_insn "stack_tie" -+ [(set (mem:BLK (scratch)) -+ (unspec:BLK [(match_operand:DI 0 "register_operand" "rk") -+ (match_operand:DI 1 "register_operand" "rk")] -+ UNSPEC_PRLG_STK))] -+ "" -+ "" -+ [(set_attr "length" "0")] -+) -+ -+;; AdvSIMD Stuff -+(include "aarch64-simd.md") -+ -+;; Synchronization Builtins -+(include "sync.md") -Index: gcc/config/aarch64/aarch64-arches.def -=================================================================== ---- a/src/gcc/config/aarch64/aarch64-arches.def (.../gcc-4_7-branch) -+++ b/src/gcc/config/aarch64/aarch64-arches.def (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,29 @@ -+/* Copyright (C) 2011, 2012 Free Software Foundation, Inc. -+ Contributed by ARM Ltd. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+/* Before using #include to read this file, define a macro: -+ -+ AARCH64_ARCH(NAME, CORE, ARCH, FLAGS) -+ -+ The NAME is the name of the architecture, represented as a string -+ constant. The CORE is the identifier for a core representative of -+ this architecture. ARCH is the architecture revision. FLAGS are -+ the flags implied by the architecture. */ -+ -+AARCH64_ARCH("armv8-a", generic, 8, AARCH64_FL_FOR_ARCH8) -Index: gcc/config/aarch64/aarch64-option-extensions.def -=================================================================== ---- a/src/gcc/config/aarch64/aarch64-option-extensions.def (.../gcc-4_7-branch) -+++ b/src/gcc/config/aarch64/aarch64-option-extensions.def (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,37 @@ -+/* Copyright (C) 2012 Free Software Foundation, Inc. -+ Contributed by ARM Ltd. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3, or (at your option) -+ any later version. -+ -+ GCC is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+/* This is a list of ISA extentsions in AArch64. -+ -+ Before using #include to read this file, define a macro: -+ -+ AARCH64_OPT_EXTENSION(EXT_NAME, FLAGS_ON, FLAGS_OFF) -+ -+ EXT_NAME is the name of the extension, represented as a string constant. -+ FLAGS_ON are the bitwise-or of the features that the extension adds. -+ FLAGS_OFF are the bitwise-or of the features that the extension removes. */ -+ -+/* V8 Architecture Extensions. -+ This list currently contains example extensions for CPUs that implement -+ AArch64, and therefore serves as a template for adding more CPUs in the -+ future. */ -+ -+AARCH64_OPT_EXTENSION("fp", AARCH64_FL_FP, AARCH64_FL_FPSIMD | AARCH64_FL_CRYPTO) -+AARCH64_OPT_EXTENSION("simd", AARCH64_FL_FPSIMD, AARCH64_FL_SIMD | AARCH64_FL_CRYPTO) -+AARCH64_OPT_EXTENSION("crypto", AARCH64_FL_CRYPTO | AARCH64_FL_FPSIMD, AARCH64_FL_CRYPTO) -Index: gcc/config/aarch64/t-aarch64 -=================================================================== ---- a/src/gcc/config/aarch64/t-aarch64 (.../gcc-4_7-branch) -+++ b/src/gcc/config/aarch64/t-aarch64 (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,32 @@ -+# Machine description for AArch64 architecture. -+# Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. -+# Contributed by ARM Ltd. -+# -+# This file is part of GCC. -+# -+# GCC is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License as published by -+# the Free Software Foundation; either version 3, or (at your option) -+# any later version. -+# -+# GCC is distributed in the hope that it will be useful, but -+# WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+# General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with GCC; see the file COPYING3. If not see -+# . -+ -+$(srcdir)/config/aarch64/aarch64-tune.md: $(srcdir)/config/aarch64/gentune.sh \ -+ $(srcdir)/config/aarch64/aarch64-cores.def -+ $(SHELL) $(srcdir)/config/aarch64/gentune.sh \ -+ $(srcdir)/config/aarch64/aarch64-cores.def > \ -+ $(srcdir)/config/aarch64/aarch64-tune.md -+ -+aarch64-builtins.o: $(srcdir)/config/aarch64/aarch64-builtins.c $(CONFIG_H) \ -+ $(SYSTEM_H) coretypes.h $(TM_H) \ -+ $(RTL_H) $(TREE_H) expr.h $(TM_P_H) $(RECOG_H) langhooks.h \ -+ $(DIAGNOSTIC_CORE_H) $(OPTABS_H) -+ $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ -+ $(srcdir)/config/aarch64/aarch64-builtins.c -Index: gcc/config/aarch64/large.md -=================================================================== ---- a/src/gcc/config/aarch64/large.md (.../gcc-4_7-branch) -+++ b/src/gcc/config/aarch64/large.md (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,312 @@ -+;; Copyright (C) 2012 Free Software Foundation, Inc. -+;; -+;; Contributed by ARM Ltd. -+;; -+;; This file is part of GCC. -+;; -+;; GCC is free software; you can redistribute it and/or modify it -+;; under the terms of the GNU General Public License as published by -+;; the Free Software Foundation; either version 3, or (at your option) -+;; any later version. -+;; -+;; GCC is distributed in the hope that it will be useful, but -+;; WITHOUT ANY WARRANTY; without even the implied warranty of -+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+;; General Public License for more details. -+;; -+;; You should have received a copy of the GNU General Public License -+;; along with GCC; see the file COPYING3. If not see -+;; . -+ -+;; In the absence of any ARMv8-A implementations, two examples derived -+;; from ARM's most recent ARMv7-A cores (Cortex-A7 and Cortex-A15) are -+;; included by way of example. This is a temporary measure. -+ -+;; Example pipeline description for an example 'large' core -+;; implementing AArch64 -+ -+;;------------------------------------------------------- -+;; General Description -+;;------------------------------------------------------- -+ -+(define_automaton "large_cpu") -+ -+;; The core is modelled as a triple issue pipeline that has -+;; the following dispatch units. -+;; 1. Two pipelines for simple integer operations: int1, int2 -+;; 2. Two pipelines for SIMD and FP data-processing operations: fpsimd1, fpsimd2 -+;; 3. One pipeline for branch operations: br -+;; 4. One pipeline for integer multiply and divide operations: multdiv -+;; 5. Two pipelines for load and store operations: ls1, ls2 -+;; -+;; We can issue into three pipelines per-cycle. -+;; -+;; We assume that where we have unit pairs xxx1 is always filled before xxx2. -+ -+;;------------------------------------------------------- -+;; CPU Units and Reservations -+;;------------------------------------------------------- -+ -+;; The three issue units -+(define_cpu_unit "large_cpu_unit_i1, large_cpu_unit_i2, large_cpu_unit_i3" "large_cpu") -+ -+(define_reservation "large_cpu_resv_i1" -+ "(large_cpu_unit_i1 | large_cpu_unit_i2 | large_cpu_unit_i3)") -+ -+(define_reservation "large_cpu_resv_i2" -+ "((large_cpu_unit_i1 + large_cpu_unit_i2) | (large_cpu_unit_i2 + large_cpu_unit_i3))") -+ -+(define_reservation "large_cpu_resv_i3" -+ "(large_cpu_unit_i1 + large_cpu_unit_i2 + large_cpu_unit_i3)") -+ -+(final_presence_set "large_cpu_unit_i2" "large_cpu_unit_i1") -+(final_presence_set "large_cpu_unit_i3" "large_cpu_unit_i2") -+ -+;; The main dispatch units -+(define_cpu_unit "large_cpu_unit_int1, large_cpu_unit_int2" "large_cpu") -+(define_cpu_unit "large_cpu_unit_fpsimd1, large_cpu_unit_fpsimd2" "large_cpu") -+(define_cpu_unit "large_cpu_unit_ls1, large_cpu_unit_ls2" "large_cpu") -+(define_cpu_unit "large_cpu_unit_br" "large_cpu") -+(define_cpu_unit "large_cpu_unit_multdiv" "large_cpu") -+ -+(define_reservation "large_cpu_resv_ls" "(large_cpu_unit_ls1 | large_cpu_unit_ls2)") -+ -+;; The extended load-store pipeline -+(define_cpu_unit "large_cpu_unit_load, large_cpu_unit_store" "large_cpu") -+ -+;; The extended ALU pipeline -+(define_cpu_unit "large_cpu_unit_int1_alu, large_cpu_unit_int2_alu" "large_cpu") -+(define_cpu_unit "large_cpu_unit_int1_shf, large_cpu_unit_int2_shf" "large_cpu") -+(define_cpu_unit "large_cpu_unit_int1_sat, large_cpu_unit_int2_sat" "large_cpu") -+ -+ -+;;------------------------------------------------------- -+;; Simple ALU Instructions -+;;------------------------------------------------------- -+ -+;; Simple ALU operations without shift -+(define_insn_reservation "large_cpu_alu" 2 -+ (and (eq_attr "tune" "large") (eq_attr "v8type" "adc,alu,alu_ext")) -+ "large_cpu_resv_i1, \ -+ (large_cpu_unit_int1, large_cpu_unit_int1_alu) |\ -+ (large_cpu_unit_int2, large_cpu_unit_int2_alu)") -+ -+(define_insn_reservation "large_cpu_logic" 2 -+ (and (eq_attr "tune" "large") (eq_attr "v8type" "logic,logic_imm")) -+ "large_cpu_resv_i1, \ -+ (large_cpu_unit_int1, large_cpu_unit_int1_alu) |\ -+ (large_cpu_unit_int2, large_cpu_unit_int2_alu)") -+ -+(define_insn_reservation "large_cpu_shift" 2 -+ (and (eq_attr "tune" "large") (eq_attr "v8type" "shift,shift_imm")) -+ "large_cpu_resv_i1, \ -+ (large_cpu_unit_int1, large_cpu_unit_int1_shf) |\ -+ (large_cpu_unit_int2, large_cpu_unit_int2_shf)") -+ -+;; Simple ALU operations with immediate shift -+(define_insn_reservation "large_cpu_alu_shift" 3 -+ (and (eq_attr "tune" "large") (eq_attr "v8type" "alu_shift")) -+ "large_cpu_resv_i1, \ -+ (large_cpu_unit_int1, -+ large_cpu_unit_int1 + large_cpu_unit_int1_shf, large_cpu_unit_int1_alu) | \ -+ (large_cpu_unit_int2, -+ large_cpu_unit_int2 + large_cpu_unit_int2_shf, large_cpu_unit_int2_alu)") -+ -+(define_insn_reservation "large_cpu_logic_shift" 3 -+ (and (eq_attr "tune" "large") (eq_attr "v8type" "logic_shift")) -+ "large_cpu_resv_i1, \ -+ (large_cpu_unit_int1, large_cpu_unit_int1_alu) |\ -+ (large_cpu_unit_int2, large_cpu_unit_int2_alu)") -+ -+ -+;;------------------------------------------------------- -+;; Multiplication/Division -+;;------------------------------------------------------- -+ -+;; Simple multiplication -+(define_insn_reservation "large_cpu_mult_single" 3 -+ (and (eq_attr "tune" "large") -+ (and (eq_attr "v8type" "mult,madd") (eq_attr "mode" "SI"))) -+ "large_cpu_resv_i1, large_cpu_unit_multdiv") -+ -+(define_insn_reservation "large_cpu_mult_double" 4 -+ (and (eq_attr "tune" "large") -+ (and (eq_attr "v8type" "mult,madd") (eq_attr "mode" "DI"))) -+ "large_cpu_resv_i1, large_cpu_unit_multdiv") -+ -+;; 64-bit multiplication -+(define_insn_reservation "large_cpu_mull" 4 -+ (and (eq_attr "tune" "large") (eq_attr "v8type" "mull,mulh,maddl")) -+ "large_cpu_resv_i1, large_cpu_unit_multdiv * 2") -+ -+;; Division -+(define_insn_reservation "large_cpu_udiv_single" 9 -+ (and (eq_attr "tune" "large") -+ (and (eq_attr "v8type" "udiv") (eq_attr "mode" "SI"))) -+ "large_cpu_resv_i1, large_cpu_unit_multdiv") -+ -+(define_insn_reservation "large_cpu_udiv_double" 18 -+ (and (eq_attr "tune" "large") -+ (and (eq_attr "v8type" "udiv") (eq_attr "mode" "DI"))) -+ "large_cpu_resv_i1, large_cpu_unit_multdiv") -+ -+(define_insn_reservation "large_cpu_sdiv_single" 10 -+ (and (eq_attr "tune" "large") -+ (and (eq_attr "v8type" "sdiv") (eq_attr "mode" "SI"))) -+ "large_cpu_resv_i1, large_cpu_unit_multdiv") -+ -+(define_insn_reservation "large_cpu_sdiv_double" 20 -+ (and (eq_attr "tune" "large") -+ (and (eq_attr "v8type" "sdiv") (eq_attr "mode" "DI"))) -+ "large_cpu_resv_i1, large_cpu_unit_multdiv") -+ -+ -+;;------------------------------------------------------- -+;; Branches -+;;------------------------------------------------------- -+ -+;; Branches take one issue slot. -+;; No latency as there is no result -+(define_insn_reservation "large_cpu_branch" 0 -+ (and (eq_attr "tune" "large") (eq_attr "v8type" "branch")) -+ "large_cpu_resv_i1, large_cpu_unit_br") -+ -+ -+;; Calls take up all issue slots, and form a block in the -+;; pipeline. The result however is available the next cycle. -+;; Addition of new units requires this to be updated. -+(define_insn_reservation "large_cpu_call" 1 -+ (and (eq_attr "tune" "large") (eq_attr "v8type" "call")) -+ "large_cpu_resv_i3 | large_cpu_resv_i2, \ -+ large_cpu_unit_int1 + large_cpu_unit_int2 + large_cpu_unit_br + \ -+ large_cpu_unit_multdiv + large_cpu_unit_fpsimd1 + large_cpu_unit_fpsimd2 + \ -+ large_cpu_unit_ls1 + large_cpu_unit_ls2,\ -+ large_cpu_unit_int1_alu + large_cpu_unit_int1_shf + large_cpu_unit_int1_sat + \ -+ large_cpu_unit_int2_alu + large_cpu_unit_int2_shf + \ -+ large_cpu_unit_int2_sat + large_cpu_unit_load + large_cpu_unit_store") -+ -+ -+;;------------------------------------------------------- -+;; Load/Store Instructions -+;;------------------------------------------------------- -+ -+;; Loads of up to two words. -+(define_insn_reservation "large_cpu_load1" 4 -+ (and (eq_attr "tune" "large") (eq_attr "v8type" "load_acq,load1,load2")) -+ "large_cpu_resv_i1, large_cpu_resv_ls, large_cpu_unit_load, nothing") -+ -+;; Stores of up to two words. -+(define_insn_reservation "large_cpu_store1" 0 -+ (and (eq_attr "tune" "large") (eq_attr "v8type" "store_rel,store1,store2")) -+ "large_cpu_resv_i1, large_cpu_resv_ls, large_cpu_unit_store") -+ -+ -+;;------------------------------------------------------- -+;; Floating-point arithmetic. -+;;------------------------------------------------------- -+ -+(define_insn_reservation "large_cpu_fpalu" 4 -+ (and (eq_attr "tune" "large") -+ (eq_attr "v8type" "ffarith,fadd,fccmp,fcvt,fcmp")) -+ "large_cpu_resv_i1 + large_cpu_unit_fpsimd1") -+ -+(define_insn_reservation "large_cpu_fconst" 3 -+ (and (eq_attr "tune" "large") -+ (eq_attr "v8type" "fconst")) -+ "large_cpu_resv_i1 + large_cpu_unit_fpsimd1") -+ -+(define_insn_reservation "large_cpu_fpmuls" 4 -+ (and (eq_attr "tune" "large") -+ (and (eq_attr "v8type" "fmul,fmadd") (eq_attr "mode" "SF"))) -+ "large_cpu_resv_i1 + large_cpu_unit_fpsimd1") -+ -+(define_insn_reservation "large_cpu_fpmuld" 7 -+ (and (eq_attr "tune" "large") -+ (and (eq_attr "v8type" "fmul,fmadd") (eq_attr "mode" "DF"))) -+ "large_cpu_resv_i1 + large_cpu_unit_fpsimd1, large_cpu_unit_fpsimd1 * 2,\ -+ large_cpu_resv_i1 + large_cpu_unit_fpsimd1") -+ -+ -+;;------------------------------------------------------- -+;; Floating-point Division -+;;------------------------------------------------------- -+ -+;; Single-precision divide takes 14 cycles to complete, and this -+;; includes the time taken for the special instruction used to collect the -+;; result to travel down the multiply pipeline. -+ -+(define_insn_reservation "large_cpu_fdivs" 14 -+ (and (eq_attr "tune" "large") -+ (and (eq_attr "v8type" "fdiv,fsqrt") (eq_attr "mode" "SF"))) -+ "large_cpu_resv_i1, large_cpu_unit_fpsimd1 * 13") -+ -+(define_insn_reservation "large_cpu_fdivd" 29 -+ (and (eq_attr "tune" "large") -+ (and (eq_attr "v8type" "fdiv,fsqrt") (eq_attr "mode" "DF"))) -+ "large_cpu_resv_i1, large_cpu_unit_fpsimd1 * 28") -+ -+ -+ -+;;------------------------------------------------------- -+;; Floating-point Transfers -+;;------------------------------------------------------- -+ -+(define_insn_reservation "large_cpu_i2f" 4 -+ (and (eq_attr "tune" "large") -+ (eq_attr "v8type" "fmovi2f")) -+ "large_cpu_resv_i1") -+ -+(define_insn_reservation "large_cpu_f2i" 2 -+ (and (eq_attr "tune" "large") -+ (eq_attr "v8type" "fmovf2i")) -+ "large_cpu_resv_i1") -+ -+ -+;;------------------------------------------------------- -+;; Floating-point Load/Store -+;;------------------------------------------------------- -+ -+(define_insn_reservation "large_cpu_floads" 4 -+ (and (eq_attr "tune" "large") -+ (and (eq_attr "v8type" "fpsimd_load,fpsimd_load2") (eq_attr "mode" "SF"))) -+ "large_cpu_resv_i1") -+ -+(define_insn_reservation "large_cpu_floadd" 5 -+ (and (eq_attr "tune" "large") -+ (and (eq_attr "v8type" "fpsimd_load,fpsimd_load2") (eq_attr "mode" "DF"))) -+ "large_cpu_resv_i1 + large_cpu_unit_br, large_cpu_resv_i1") -+ -+(define_insn_reservation "large_cpu_fstores" 0 -+ (and (eq_attr "tune" "large") -+ (and (eq_attr "v8type" "fpsimd_store,fpsimd_store2") (eq_attr "mode" "SF"))) -+ "large_cpu_resv_i1") -+ -+(define_insn_reservation "large_cpu_fstored" 0 -+ (and (eq_attr "tune" "large") -+ (and (eq_attr "v8type" "fpsimd_store,fpsimd_store2") (eq_attr "mode" "DF"))) -+ "large_cpu_resv_i1 + large_cpu_unit_br, large_cpu_resv_i1") -+ -+ -+;;------------------------------------------------------- -+;; Bypasses -+;;------------------------------------------------------- -+ -+(define_bypass 1 "large_cpu_alu, large_cpu_logic, large_cpu_shift" -+ "large_cpu_alu, large_cpu_alu_shift, large_cpu_logic, large_cpu_logic_shift, large_cpu_shift") -+ -+(define_bypass 2 "large_cpu_alu_shift, large_cpu_logic_shift" -+ "large_cpu_alu, large_cpu_alu_shift, large_cpu_logic, large_cpu_logic_shift, large_cpu_shift") -+ -+(define_bypass 1 "large_cpu_alu, large_cpu_logic, large_cpu_shift" "large_cpu_load1") -+ -+(define_bypass 2 "large_cpu_alu_shift, large_cpu_logic_shift" "large_cpu_load1") -+ -+(define_bypass 2 "large_cpu_floads" -+ "large_cpu_fpalu, large_cpu_fpmuld,\ -+ large_cpu_fdivs, large_cpu_fdivd,\ -+ large_cpu_f2i") -+ -+(define_bypass 3 "large_cpu_floadd" -+ "large_cpu_fpalu, large_cpu_fpmuld,\ -+ large_cpu_fdivs, large_cpu_fdivd,\ -+ large_cpu_f2i") -Index: gcc/config/aarch64/aarch64.opt -=================================================================== ---- a/src/gcc/config/aarch64/aarch64.opt (.../gcc-4_7-branch) -+++ b/src/gcc/config/aarch64/aarch64.opt (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,100 @@ -+; Machine description for AArch64 architecture. -+; Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. -+; Contributed by ARM Ltd. -+; -+; This file is part of GCC. -+; -+; GCC is free software; you can redistribute it and/or modify it -+; under the terms of the GNU General Public License as published by -+; the Free Software Foundation; either version 3, or (at your option) -+; any later version. -+; -+; GCC is distributed in the hope that it will be useful, but -+; WITHOUT ANY WARRANTY; without even the implied warranty of -+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+; General Public License for more details. -+; -+; You should have received a copy of the GNU General Public License -+; along with GCC; see the file COPYING3. If not see -+; . -+ -+HeaderInclude -+config/aarch64/aarch64-opts.h -+ -+; The cpu/arch option names to use in cpu/arch selection. -+ -+Variable -+const char *aarch64_arch_string -+ -+Variable -+const char *aarch64_cpu_string -+ -+Variable -+const char *aarch64_tune_string -+ -+; The TLS dialect names to use with -mtls-dialect. -+ -+Enum -+Name(tls_type) Type(enum aarch64_tls_type) -+The possible TLS dialects: -+ -+EnumValue -+Enum(tls_type) String(trad) Value(TLS_TRADITIONAL) -+ -+EnumValue -+Enum(tls_type) String(desc) Value(TLS_DESCRIPTORS) -+ -+; The code model option names for -mcmodel. -+ -+Enum -+Name(cmodel) Type(enum aarch64_code_model) -+The code model option names for -mcmodel: -+ -+EnumValue -+Enum(cmodel) String(tiny) Value(AARCH64_CMODEL_TINY) -+ -+EnumValue -+Enum(cmodel) String(small) Value(AARCH64_CMODEL_SMALL) -+ -+EnumValue -+Enum(cmodel) String(large) Value(AARCH64_CMODEL_LARGE) -+ -+mbig-endian -+Target Report RejectNegative Mask(BIG_END) -+Assume target CPU is configured as big endian -+ -+mgeneral-regs-only -+Target Report RejectNegative Mask(GENERAL_REGS_ONLY) -+Generate code which uses only the general registers -+ -+mlittle-endian -+Target Report RejectNegative InverseMask(BIG_END) -+Assume target CPU is configured as little endian -+ -+mcmodel= -+Target RejectNegative Joined Enum(cmodel) Var(aarch64_cmodel_var) Init(AARCH64_CMODEL_SMALL) -+Specify the code model -+ -+mstrict-align -+Target Report RejectNegative Mask(STRICT_ALIGN) -+Don't assume that unaligned accesses are handled by the system -+ -+momit-leaf-frame-pointer -+Target Report Save Var(flag_omit_leaf_frame_pointer) Init(1) -+Omit the frame pointer in leaf functions -+ -+mtls-dialect= -+Target RejectNegative Joined Enum(tls_type) Var(aarch64_tls_dialect) Init(TLS_DESCRIPTORS) -+Specify TLS dialect -+ -+march= -+Target RejectNegative Joined Var(aarch64_arch_string) -+-march=ARCH Use features of architecture ARCH -+ -+mcpu= -+Target RejectNegative Joined Var(aarch64_cpu_string) -+-mcpu=CPU Use features of and optimize for CPU -+ -+mtune= -+Target RejectNegative Joined Var(aarch64_tune_string) -+-mtune=CPU Optimize for CPU -Index: gcc/config/aarch64/aarch64-modes.def -=================================================================== ---- a/src/gcc/config/aarch64/aarch64-modes.def (.../gcc-4_7-branch) -+++ b/src/gcc/config/aarch64/aarch64-modes.def (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,44 @@ -+/* Machine description for AArch64 architecture. -+ Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. -+ Contributed by ARM Ltd. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3, or (at your option) -+ any later version. -+ -+ GCC is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+CC_MODE (CCFP); -+CC_MODE (CCFPE); -+CC_MODE (CC_SWP); -+CC_MODE (CC_ZESWP); /* zero-extend LHS (but swap to make it RHS). */ -+CC_MODE (CC_SESWP); /* sign-extend LHS (but swap to make it RHS). */ -+CC_MODE (CC_NZ); /* Only N and Z bits of condition flags are valid. */ -+ -+/* Vector modes. */ -+VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI. */ -+VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI. */ -+VECTOR_MODES (FLOAT, 8); /* V2SF. */ -+VECTOR_MODES (FLOAT, 16); /* V4SF V2DF. */ -+ -+/* Oct Int: 256-bit integer mode needed for 32-byte vector arguments. */ -+INT_MODE (OI, 32); -+ -+/* Opaque integer modes for 3, 6 or 8 Neon double registers (2 is -+ TImode). */ -+INT_MODE (EI, 24); -+INT_MODE (CI, 48); -+INT_MODE (XI, 64); -+ -+/* Quad float: 128-bit floating mode for long doubles. */ -+FLOAT_MODE (TF, 16, ieee_quad_format); -Index: gcc/config/aarch64/aarch64-cores.def -=================================================================== ---- a/src/gcc/config/aarch64/aarch64-cores.def (.../gcc-4_7-branch) -+++ b/src/gcc/config/aarch64/aarch64-cores.def (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,38 @@ -+/* Copyright (C) 2011, 2012 Free Software Foundation, Inc. -+ Contributed by ARM Ltd. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3, or (at your option) -+ any later version. -+ -+ GCC is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+/* This is a list of cores that implement AArch64. -+ -+ Before using #include to read this file, define a macro: -+ -+ AARCH64_CORE(CORE_NAME, CORE_IDENT, ARCH, FLAGS, COSTS) -+ -+ The CORE_NAME is the name of the core, represented as a string constant. -+ The CORE_IDENT is the name of the core, represented as an identifier. -+ ARCH is the architecture revision implemented by the chip. -+ FLAGS are the bitwise-or of the traits that apply to that core. -+ This need not include flags implied by the architecture. -+ COSTS is the name of the rtx_costs routine to use. */ -+ -+/* V8 Architecture Processors. -+ This list currently contains example CPUs that implement AArch64, and -+ therefore serves as a template for adding more CPUs in the future. */ -+ -+AARCH64_CORE("example-1", large, 8, AARCH64_FL_FPSIMD, generic) -+AARCH64_CORE("example-2", small, 8, AARCH64_FL_FPSIMD, generic) -Index: gcc/config/aarch64/aarch64-builtins.c -=================================================================== ---- a/src/gcc/config/aarch64/aarch64-builtins.c (.../gcc-4_7-branch) -+++ b/src/gcc/config/aarch64/aarch64-builtins.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,1279 @@ -+/* Builtins' description for AArch64 SIMD architecture. -+ Copyright (C) 2011, 2012 Free Software Foundation, Inc. -+ Contributed by ARM Ltd. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3, or (at your option) -+ any later version. -+ -+ GCC is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+#include "config.h" -+#include "system.h" -+#include "coretypes.h" -+#include "tm.h" -+#include "rtl.h" -+#include "tree.h" -+#include "expr.h" -+#include "tm_p.h" -+#include "recog.h" -+#include "langhooks.h" -+#include "diagnostic-core.h" -+#include "optabs.h" -+ -+enum aarch64_simd_builtin_type_bits -+{ -+ T_V8QI = 0x0001, -+ T_V4HI = 0x0002, -+ T_V2SI = 0x0004, -+ T_V2SF = 0x0008, -+ T_DI = 0x0010, -+ T_DF = 0x0020, -+ T_V16QI = 0x0040, -+ T_V8HI = 0x0080, -+ T_V4SI = 0x0100, -+ T_V4SF = 0x0200, -+ T_V2DI = 0x0400, -+ T_V2DF = 0x0800, -+ T_TI = 0x1000, -+ T_EI = 0x2000, -+ T_OI = 0x4000, -+ T_XI = 0x8000, -+ T_SI = 0x10000, -+ T_HI = 0x20000, -+ T_QI = 0x40000 -+}; -+ -+#define v8qi_UP T_V8QI -+#define v4hi_UP T_V4HI -+#define v2si_UP T_V2SI -+#define v2sf_UP T_V2SF -+#define di_UP T_DI -+#define df_UP T_DF -+#define v16qi_UP T_V16QI -+#define v8hi_UP T_V8HI -+#define v4si_UP T_V4SI -+#define v4sf_UP T_V4SF -+#define v2di_UP T_V2DI -+#define v2df_UP T_V2DF -+#define ti_UP T_TI -+#define ei_UP T_EI -+#define oi_UP T_OI -+#define xi_UP T_XI -+#define si_UP T_SI -+#define hi_UP T_HI -+#define qi_UP T_QI -+ -+#define UP(X) X##_UP -+ -+#define T_MAX 19 -+ -+typedef enum -+{ -+ AARCH64_SIMD_BINOP, -+ AARCH64_SIMD_TERNOP, -+ AARCH64_SIMD_QUADOP, -+ AARCH64_SIMD_UNOP, -+ AARCH64_SIMD_GETLANE, -+ AARCH64_SIMD_SETLANE, -+ AARCH64_SIMD_CREATE, -+ AARCH64_SIMD_DUP, -+ AARCH64_SIMD_DUPLANE, -+ AARCH64_SIMD_COMBINE, -+ AARCH64_SIMD_SPLIT, -+ AARCH64_SIMD_LANEMUL, -+ AARCH64_SIMD_LANEMULL, -+ AARCH64_SIMD_LANEMULH, -+ AARCH64_SIMD_LANEMAC, -+ AARCH64_SIMD_SCALARMUL, -+ AARCH64_SIMD_SCALARMULL, -+ AARCH64_SIMD_SCALARMULH, -+ AARCH64_SIMD_SCALARMAC, -+ AARCH64_SIMD_CONVERT, -+ AARCH64_SIMD_FIXCONV, -+ AARCH64_SIMD_SELECT, -+ AARCH64_SIMD_RESULTPAIR, -+ AARCH64_SIMD_REINTERP, -+ AARCH64_SIMD_VTBL, -+ AARCH64_SIMD_VTBX, -+ AARCH64_SIMD_LOAD1, -+ AARCH64_SIMD_LOAD1LANE, -+ AARCH64_SIMD_STORE1, -+ AARCH64_SIMD_STORE1LANE, -+ AARCH64_SIMD_LOADSTRUCT, -+ AARCH64_SIMD_LOADSTRUCTLANE, -+ AARCH64_SIMD_STORESTRUCT, -+ AARCH64_SIMD_STORESTRUCTLANE, -+ AARCH64_SIMD_LOGICBINOP, -+ AARCH64_SIMD_SHIFTINSERT, -+ AARCH64_SIMD_SHIFTIMM, -+ AARCH64_SIMD_SHIFTACC -+} aarch64_simd_itype; -+ -+typedef struct -+{ -+ const char *name; -+ const aarch64_simd_itype itype; -+ const int bits; -+ const enum insn_code codes[T_MAX]; -+ const unsigned int num_vars; -+ unsigned int base_fcode; -+} aarch64_simd_builtin_datum; -+ -+#define CF(N, X) CODE_FOR_aarch64_##N##X -+ -+#define VAR1(T, N, A) \ -+ #N, AARCH64_SIMD_##T, UP (A), { CF (N, A) }, 1, 0 -+#define VAR2(T, N, A, B) \ -+ #N, AARCH64_SIMD_##T, UP (A) | UP (B), { CF (N, A), CF (N, B) }, 2, 0 -+#define VAR3(T, N, A, B, C) \ -+ #N, AARCH64_SIMD_##T, UP (A) | UP (B) | UP (C), \ -+ { CF (N, A), CF (N, B), CF (N, C) }, 3, 0 -+#define VAR4(T, N, A, B, C, D) \ -+ #N, AARCH64_SIMD_##T, UP (A) | UP (B) | UP (C) | UP (D), \ -+ { CF (N, A), CF (N, B), CF (N, C), CF (N, D) }, 4, 0 -+#define VAR5(T, N, A, B, C, D, E) \ -+ #N, AARCH64_SIMD_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E), \ -+ { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E) }, 5, 0 -+#define VAR6(T, N, A, B, C, D, E, F) \ -+ #N, AARCH64_SIMD_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F), \ -+ { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F) }, 6, 0 -+#define VAR7(T, N, A, B, C, D, E, F, G) \ -+ #N, AARCH64_SIMD_##T, UP (A) | UP (B) | UP (C) | UP (D) \ -+ | UP (E) | UP (F) | UP (G), \ -+ { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ -+ CF (N, G) }, 7, 0 -+#define VAR8(T, N, A, B, C, D, E, F, G, H) \ -+ #N, AARCH64_SIMD_##T, UP (A) | UP (B) | UP (C) | UP (D) \ -+ | UP (E) | UP (F) | UP (G) \ -+ | UP (H), \ -+ { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ -+ CF (N, G), CF (N, H) }, 8, 0 -+#define VAR9(T, N, A, B, C, D, E, F, G, H, I) \ -+ #N, AARCH64_SIMD_##T, UP (A) | UP (B) | UP (C) | UP (D) \ -+ | UP (E) | UP (F) | UP (G) \ -+ | UP (H) | UP (I), \ -+ { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ -+ CF (N, G), CF (N, H), CF (N, I) }, 9, 0 -+#define VAR10(T, N, A, B, C, D, E, F, G, H, I, J) \ -+ #N, AARCH64_SIMD_##T, UP (A) | UP (B) | UP (C) | UP (D) \ -+ | UP (E) | UP (F) | UP (G) \ -+ | UP (H) | UP (I) | UP (J), \ -+ { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ -+ CF (N, G), CF (N, H), CF (N, I), CF (N, J) }, 10, 0 -+ -+#define VAR11(T, N, A, B, C, D, E, F, G, H, I, J, K) \ -+ #N, AARCH64_SIMD_##T, UP (A) | UP (B) | UP (C) | UP (D) \ -+ | UP (E) | UP (F) | UP (G) \ -+ | UP (H) | UP (I) | UP (J) | UP (K), \ -+ { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ -+ CF (N, G), CF (N, H), CF (N, I), CF (N, J), CF (N, K) }, 11, 0 -+ -+ -+/* The mode entries in the following table correspond to the "key" type of the -+ instruction variant, i.e. equivalent to that which would be specified after -+ the assembler mnemonic, which usually refers to the last vector operand. -+ (Signed/unsigned/polynomial types are not differentiated between though, and -+ are all mapped onto the same mode for a given element size.) The modes -+ listed per instruction should be the same as those defined for that -+ instruction's pattern in aarch64_simd.md. -+ WARNING: Variants should be listed in the same increasing order as -+ aarch64_simd_builtin_type_bits. */ -+ -+static aarch64_simd_builtin_datum aarch64_simd_builtin_data[] = { -+ {VAR6 (CREATE, create, v8qi, v4hi, v2si, v2sf, di, df)}, -+ {VAR6 (GETLANE, get_lane_signed, -+ v8qi, v4hi, v2si, v16qi, v8hi, v4si)}, -+ {VAR7 (GETLANE, get_lane_unsigned, -+ v8qi, v4hi, v2si, v16qi, v8hi, v4si, v2di)}, -+ {VAR4 (GETLANE, get_lane, v2sf, di, v4sf, v2df)}, -+ -+ {VAR5 (REINTERP, reinterpretv8qi, v8qi, v4hi, v2si, v2sf, di)}, -+ {VAR5 (REINTERP, reinterpretv4hi, v8qi, v4hi, v2si, v2sf, di)}, -+ {VAR5 (REINTERP, reinterpretv2si, v8qi, v4hi, v2si, v2sf, di)}, -+ {VAR5 (REINTERP, reinterpretv2sf, v8qi, v4hi, v2si, v2sf, di)}, -+ {VAR5 (REINTERP, reinterpretdi, v8qi, v4hi, v2si, v2sf, di)}, -+ {VAR6 (REINTERP, reinterpretv16qi, v16qi, v8hi, v4si, v4sf, v2di, v2df)}, -+ {VAR6 (REINTERP, reinterpretv8hi, v16qi, v8hi, v4si, v4sf, v2di, v2df)}, -+ {VAR6 (REINTERP, reinterpretv4si, v16qi, v8hi, v4si, v4sf, v2di, v2df)}, -+ {VAR6 (REINTERP, reinterpretv4sf, v16qi, v8hi, v4si, v4sf, v2di, v2df)}, -+ {VAR6 (REINTERP, reinterpretv2di, v16qi, v8hi, v4si, v4sf, v2di, v2df)}, -+ {VAR6 (COMBINE, combine, v8qi, v4hi, v2si, v2sf, di, df)}, -+ -+ {VAR3 (BINOP, saddl, v8qi, v4hi, v2si)}, -+ {VAR3 (BINOP, uaddl, v8qi, v4hi, v2si)}, -+ {VAR3 (BINOP, saddl2, v16qi, v8hi, v4si)}, -+ {VAR3 (BINOP, uaddl2, v16qi, v8hi, v4si)}, -+ {VAR3 (BINOP, saddw, v8qi, v4hi, v2si)}, -+ {VAR3 (BINOP, uaddw, v8qi, v4hi, v2si)}, -+ {VAR3 (BINOP, saddw2, v16qi, v8hi, v4si)}, -+ {VAR3 (BINOP, uaddw2, v16qi, v8hi, v4si)}, -+ {VAR6 (BINOP, shadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si)}, -+ {VAR6 (BINOP, uhadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si)}, -+ {VAR6 (BINOP, srhadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si)}, -+ {VAR6 (BINOP, urhadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si)}, -+ {VAR3 (BINOP, addhn, v8hi, v4si, v2di)}, -+ {VAR3 (BINOP, raddhn, v8hi, v4si, v2di)}, -+ {VAR3 (TERNOP, addhn2, v8hi, v4si, v2di)}, -+ {VAR3 (TERNOP, raddhn2, v8hi, v4si, v2di)}, -+ {VAR3 (BINOP, ssubl, v8qi, v4hi, v2si)}, -+ {VAR3 (BINOP, usubl, v8qi, v4hi, v2si)}, -+ {VAR3 (BINOP, ssubl2, v16qi, v8hi, v4si) }, -+ {VAR3 (BINOP, usubl2, v16qi, v8hi, v4si) }, -+ {VAR3 (BINOP, ssubw, v8qi, v4hi, v2si) }, -+ {VAR3 (BINOP, usubw, v8qi, v4hi, v2si) }, -+ {VAR3 (BINOP, ssubw2, v16qi, v8hi, v4si) }, -+ {VAR3 (BINOP, usubw2, v16qi, v8hi, v4si) }, -+ {VAR11 (BINOP, sqadd, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di, -+ si, hi, qi)}, -+ {VAR11 (BINOP, uqadd, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di, -+ si, hi, qi)}, -+ {VAR11 (BINOP, sqsub, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di, -+ si, hi, qi)}, -+ {VAR11 (BINOP, uqsub, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di, -+ si, hi, qi)}, -+ {VAR11 (BINOP, suqadd, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di, -+ si, hi, qi)}, -+ {VAR11 (BINOP, usqadd, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di, -+ si, hi, qi)}, -+ {VAR6 (UNOP, sqmovun, di, v8hi, v4si, v2di, si, hi)}, -+ {VAR6 (UNOP, sqmovn, di, v8hi, v4si, v2di, si, hi)}, -+ {VAR6 (UNOP, uqmovn, di, v8hi, v4si, v2di, si, hi)}, -+ {VAR10 (UNOP, sqabs, v8qi, v4hi, v2si, v16qi, v8hi, v4si, v2di, si, hi, qi)}, -+ {VAR10 (UNOP, sqneg, v8qi, v4hi, v2si, v16qi, v8hi, v4si, v2di, si, hi, qi)}, -+ {VAR2 (BINOP, pmul, v8qi, v16qi)}, -+ {VAR4 (TERNOP, sqdmlal, v4hi, v2si, si, hi)}, -+ {VAR4 (QUADOP, sqdmlal_lane, v4hi, v2si, si, hi) }, -+ {VAR2 (QUADOP, sqdmlal_laneq, v4hi, v2si) }, -+ {VAR2 (TERNOP, sqdmlal_n, v4hi, v2si) }, -+ {VAR2 (TERNOP, sqdmlal2, v8hi, v4si)}, -+ {VAR2 (QUADOP, sqdmlal2_lane, v8hi, v4si) }, -+ {VAR2 (QUADOP, sqdmlal2_laneq, v8hi, v4si) }, -+ {VAR2 (TERNOP, sqdmlal2_n, v8hi, v4si) }, -+ {VAR4 (TERNOP, sqdmlsl, v4hi, v2si, si, hi)}, -+ {VAR4 (QUADOP, sqdmlsl_lane, v4hi, v2si, si, hi) }, -+ {VAR2 (QUADOP, sqdmlsl_laneq, v4hi, v2si) }, -+ {VAR2 (TERNOP, sqdmlsl_n, v4hi, v2si) }, -+ {VAR2 (TERNOP, sqdmlsl2, v8hi, v4si)}, -+ {VAR2 (QUADOP, sqdmlsl2_lane, v8hi, v4si) }, -+ {VAR2 (QUADOP, sqdmlsl2_laneq, v8hi, v4si) }, -+ {VAR2 (TERNOP, sqdmlsl2_n, v8hi, v4si) }, -+ {VAR4 (BINOP, sqdmull, v4hi, v2si, si, hi)}, -+ {VAR4 (TERNOP, sqdmull_lane, v4hi, v2si, si, hi) }, -+ {VAR2 (TERNOP, sqdmull_laneq, v4hi, v2si) }, -+ {VAR2 (BINOP, sqdmull_n, v4hi, v2si) }, -+ {VAR2 (BINOP, sqdmull2, v8hi, v4si) }, -+ {VAR2 (TERNOP, sqdmull2_lane, v8hi, v4si) }, -+ {VAR2 (TERNOP, sqdmull2_laneq, v8hi, v4si) }, -+ {VAR2 (BINOP, sqdmull2_n, v8hi, v4si) }, -+ {VAR6 (BINOP, sqdmulh, v4hi, v2si, v8hi, v4si, si, hi)}, -+ {VAR6 (BINOP, sqrdmulh, v4hi, v2si, v8hi, v4si, si, hi)}, -+ {VAR8 (BINOP, sshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR3 (SHIFTIMM, sshll_n, v8qi, v4hi, v2si) }, -+ {VAR3 (SHIFTIMM, ushll_n, v8qi, v4hi, v2si) }, -+ {VAR3 (SHIFTIMM, sshll2_n, v16qi, v8hi, v4si) }, -+ {VAR3 (SHIFTIMM, ushll2_n, v16qi, v8hi, v4si) }, -+ {VAR8 (BINOP, ushl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR8 (BINOP, sshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR8 (BINOP, ushl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR11 (BINOP, sqshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di, -+ si, hi, qi) }, -+ {VAR11 (BINOP, uqshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di, -+ si, hi, qi) }, -+ {VAR8 (BINOP, srshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR8 (BINOP, urshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR11 (BINOP, sqrshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di, -+ si, hi, qi) }, -+ {VAR11 (BINOP, uqrshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di, -+ si, hi, qi) }, -+ {VAR8 (SHIFTIMM, sshr_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR8 (SHIFTIMM, ushr_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR8 (SHIFTIMM, srshr_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR8 (SHIFTIMM, urshr_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR8 (SHIFTACC, ssra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR8 (SHIFTACC, usra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR8 (SHIFTACC, srsra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR8 (SHIFTACC, ursra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR8 (SHIFTINSERT, ssri_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR8 (SHIFTINSERT, usri_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR8 (SHIFTINSERT, ssli_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR8 (SHIFTINSERT, usli_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ {VAR11 (SHIFTIMM, sqshlu_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di, -+ si, hi, qi) }, -+ {VAR11 (SHIFTIMM, sqshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di, -+ si, hi, qi) }, -+ {VAR11 (SHIFTIMM, uqshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di, -+ si, hi, qi) }, -+ { VAR6 (SHIFTIMM, sqshrun_n, di, v8hi, v4si, v2di, si, hi) }, -+ { VAR6 (SHIFTIMM, sqrshrun_n, di, v8hi, v4si, v2di, si, hi) }, -+ { VAR6 (SHIFTIMM, sqshrn_n, di, v8hi, v4si, v2di, si, hi) }, -+ { VAR6 (SHIFTIMM, uqshrn_n, di, v8hi, v4si, v2di, si, hi) }, -+ { VAR6 (SHIFTIMM, sqrshrn_n, di, v8hi, v4si, v2di, si, hi) }, -+ { VAR6 (SHIFTIMM, uqrshrn_n, di, v8hi, v4si, v2di, si, hi) }, -+ { VAR8 (BINOP, cmeq, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ { VAR8 (BINOP, cmge, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ { VAR8 (BINOP, cmgt, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ { VAR8 (BINOP, cmle, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ { VAR8 (BINOP, cmlt, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ { VAR8 (BINOP, cmhs, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ { VAR8 (BINOP, cmhi, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ { VAR8 (BINOP, cmtst, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, -+ { VAR6 (TERNOP, sqdmulh_lane, v4hi, v2si, v8hi, v4si, si, hi) }, -+ { VAR6 (TERNOP, sqrdmulh_lane, v4hi, v2si, v8hi, v4si, si, hi) }, -+ { VAR3 (BINOP, addp, v8qi, v4hi, v2si) }, -+ { VAR1 (UNOP, addp, di) }, -+ { VAR11 (BINOP, dup_lane, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di, -+ si, hi, qi) }, -+ { VAR3 (BINOP, fmax, v2sf, v4sf, v2df) }, -+ { VAR3 (BINOP, fmin, v2sf, v4sf, v2df) }, -+ { VAR6 (BINOP, smax, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, -+ { VAR6 (BINOP, smin, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, -+ { VAR6 (BINOP, umax, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, -+ { VAR6 (BINOP, umin, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, -+ { VAR3 (UNOP, sqrt, v2sf, v4sf, v2df) }, -+}; -+ -+#undef CF -+#undef VAR1 -+#undef VAR2 -+#undef VAR3 -+#undef VAR4 -+#undef VAR5 -+#undef VAR6 -+#undef VAR7 -+#undef VAR8 -+#undef VAR9 -+#undef VAR10 -+#undef VAR11 -+ -+#define NUM_DREG_TYPES 6 -+#define NUM_QREG_TYPES 6 -+ -+void -+init_aarch64_simd_builtins (void) -+{ -+ unsigned int i, fcode = AARCH64_SIMD_BUILTIN_BASE; -+ -+ /* Scalar type nodes. */ -+ tree aarch64_simd_intQI_type_node; -+ tree aarch64_simd_intHI_type_node; -+ tree aarch64_simd_polyQI_type_node; -+ tree aarch64_simd_polyHI_type_node; -+ tree aarch64_simd_intSI_type_node; -+ tree aarch64_simd_intDI_type_node; -+ tree aarch64_simd_float_type_node; -+ tree aarch64_simd_double_type_node; -+ -+ /* Pointer to scalar type nodes. */ -+ tree intQI_pointer_node; -+ tree intHI_pointer_node; -+ tree intSI_pointer_node; -+ tree intDI_pointer_node; -+ tree float_pointer_node; -+ tree double_pointer_node; -+ -+ /* Const scalar type nodes. */ -+ tree const_intQI_node; -+ tree const_intHI_node; -+ tree const_intSI_node; -+ tree const_intDI_node; -+ tree const_float_node; -+ tree const_double_node; -+ -+ /* Pointer to const scalar type nodes. */ -+ tree const_intQI_pointer_node; -+ tree const_intHI_pointer_node; -+ tree const_intSI_pointer_node; -+ tree const_intDI_pointer_node; -+ tree const_float_pointer_node; -+ tree const_double_pointer_node; -+ -+ /* Vector type nodes. */ -+ tree V8QI_type_node; -+ tree V4HI_type_node; -+ tree V2SI_type_node; -+ tree V2SF_type_node; -+ tree V16QI_type_node; -+ tree V8HI_type_node; -+ tree V4SI_type_node; -+ tree V4SF_type_node; -+ tree V2DI_type_node; -+ tree V2DF_type_node; -+ -+ /* Scalar unsigned type nodes. */ -+ tree intUQI_type_node; -+ tree intUHI_type_node; -+ tree intUSI_type_node; -+ tree intUDI_type_node; -+ -+ /* Opaque integer types for structures of vectors. */ -+ tree intEI_type_node; -+ tree intOI_type_node; -+ tree intCI_type_node; -+ tree intXI_type_node; -+ -+ /* Pointer to vector type nodes. */ -+ tree V8QI_pointer_node; -+ tree V4HI_pointer_node; -+ tree V2SI_pointer_node; -+ tree V2SF_pointer_node; -+ tree V16QI_pointer_node; -+ tree V8HI_pointer_node; -+ tree V4SI_pointer_node; -+ tree V4SF_pointer_node; -+ tree V2DI_pointer_node; -+ tree V2DF_pointer_node; -+ -+ /* Operations which return results as pairs. */ -+ tree void_ftype_pv8qi_v8qi_v8qi; -+ tree void_ftype_pv4hi_v4hi_v4hi; -+ tree void_ftype_pv2si_v2si_v2si; -+ tree void_ftype_pv2sf_v2sf_v2sf; -+ tree void_ftype_pdi_di_di; -+ tree void_ftype_pv16qi_v16qi_v16qi; -+ tree void_ftype_pv8hi_v8hi_v8hi; -+ tree void_ftype_pv4si_v4si_v4si; -+ tree void_ftype_pv4sf_v4sf_v4sf; -+ tree void_ftype_pv2di_v2di_v2di; -+ tree void_ftype_pv2df_v2df_v2df; -+ -+ tree reinterp_ftype_dreg[NUM_DREG_TYPES][NUM_DREG_TYPES]; -+ tree reinterp_ftype_qreg[NUM_QREG_TYPES][NUM_QREG_TYPES]; -+ tree dreg_types[NUM_DREG_TYPES], qreg_types[NUM_QREG_TYPES]; -+ -+ /* Create distinguished type nodes for AARCH64_SIMD vector element types, -+ and pointers to values of such types, so we can detect them later. */ -+ aarch64_simd_intQI_type_node = -+ make_signed_type (GET_MODE_PRECISION (QImode)); -+ aarch64_simd_intHI_type_node = -+ make_signed_type (GET_MODE_PRECISION (HImode)); -+ aarch64_simd_polyQI_type_node = -+ make_signed_type (GET_MODE_PRECISION (QImode)); -+ aarch64_simd_polyHI_type_node = -+ make_signed_type (GET_MODE_PRECISION (HImode)); -+ aarch64_simd_intSI_type_node = -+ make_signed_type (GET_MODE_PRECISION (SImode)); -+ aarch64_simd_intDI_type_node = -+ make_signed_type (GET_MODE_PRECISION (DImode)); -+ aarch64_simd_float_type_node = make_node (REAL_TYPE); -+ aarch64_simd_double_type_node = make_node (REAL_TYPE); -+ TYPE_PRECISION (aarch64_simd_float_type_node) = FLOAT_TYPE_SIZE; -+ TYPE_PRECISION (aarch64_simd_double_type_node) = DOUBLE_TYPE_SIZE; -+ layout_type (aarch64_simd_float_type_node); -+ layout_type (aarch64_simd_double_type_node); -+ -+ /* Define typedefs which exactly correspond to the modes we are basing vector -+ types on. If you change these names you'll need to change -+ the table used by aarch64_mangle_type too. */ -+ (*lang_hooks.types.register_builtin_type) (aarch64_simd_intQI_type_node, -+ "__builtin_aarch64_simd_qi"); -+ (*lang_hooks.types.register_builtin_type) (aarch64_simd_intHI_type_node, -+ "__builtin_aarch64_simd_hi"); -+ (*lang_hooks.types.register_builtin_type) (aarch64_simd_intSI_type_node, -+ "__builtin_aarch64_simd_si"); -+ (*lang_hooks.types.register_builtin_type) (aarch64_simd_float_type_node, -+ "__builtin_aarch64_simd_sf"); -+ (*lang_hooks.types.register_builtin_type) (aarch64_simd_intDI_type_node, -+ "__builtin_aarch64_simd_di"); -+ (*lang_hooks.types.register_builtin_type) (aarch64_simd_double_type_node, -+ "__builtin_aarch64_simd_df"); -+ (*lang_hooks.types.register_builtin_type) (aarch64_simd_polyQI_type_node, -+ "__builtin_aarch64_simd_poly8"); -+ (*lang_hooks.types.register_builtin_type) (aarch64_simd_polyHI_type_node, -+ "__builtin_aarch64_simd_poly16"); -+ -+ intQI_pointer_node = build_pointer_type (aarch64_simd_intQI_type_node); -+ intHI_pointer_node = build_pointer_type (aarch64_simd_intHI_type_node); -+ intSI_pointer_node = build_pointer_type (aarch64_simd_intSI_type_node); -+ intDI_pointer_node = build_pointer_type (aarch64_simd_intDI_type_node); -+ float_pointer_node = build_pointer_type (aarch64_simd_float_type_node); -+ double_pointer_node = build_pointer_type (aarch64_simd_double_type_node); -+ -+ /* Next create constant-qualified versions of the above types. */ -+ const_intQI_node = build_qualified_type (aarch64_simd_intQI_type_node, -+ TYPE_QUAL_CONST); -+ const_intHI_node = build_qualified_type (aarch64_simd_intHI_type_node, -+ TYPE_QUAL_CONST); -+ const_intSI_node = build_qualified_type (aarch64_simd_intSI_type_node, -+ TYPE_QUAL_CONST); -+ const_intDI_node = build_qualified_type (aarch64_simd_intDI_type_node, -+ TYPE_QUAL_CONST); -+ const_float_node = build_qualified_type (aarch64_simd_float_type_node, -+ TYPE_QUAL_CONST); -+ const_double_node = build_qualified_type (aarch64_simd_double_type_node, -+ TYPE_QUAL_CONST); -+ -+ const_intQI_pointer_node = build_pointer_type (const_intQI_node); -+ const_intHI_pointer_node = build_pointer_type (const_intHI_node); -+ const_intSI_pointer_node = build_pointer_type (const_intSI_node); -+ const_intDI_pointer_node = build_pointer_type (const_intDI_node); -+ const_float_pointer_node = build_pointer_type (const_float_node); -+ const_double_pointer_node = build_pointer_type (const_double_node); -+ -+ /* Now create vector types based on our AARCH64 SIMD element types. */ -+ /* 64-bit vectors. */ -+ V8QI_type_node = -+ build_vector_type_for_mode (aarch64_simd_intQI_type_node, V8QImode); -+ V4HI_type_node = -+ build_vector_type_for_mode (aarch64_simd_intHI_type_node, V4HImode); -+ V2SI_type_node = -+ build_vector_type_for_mode (aarch64_simd_intSI_type_node, V2SImode); -+ V2SF_type_node = -+ build_vector_type_for_mode (aarch64_simd_float_type_node, V2SFmode); -+ /* 128-bit vectors. */ -+ V16QI_type_node = -+ build_vector_type_for_mode (aarch64_simd_intQI_type_node, V16QImode); -+ V8HI_type_node = -+ build_vector_type_for_mode (aarch64_simd_intHI_type_node, V8HImode); -+ V4SI_type_node = -+ build_vector_type_for_mode (aarch64_simd_intSI_type_node, V4SImode); -+ V4SF_type_node = -+ build_vector_type_for_mode (aarch64_simd_float_type_node, V4SFmode); -+ V2DI_type_node = -+ build_vector_type_for_mode (aarch64_simd_intDI_type_node, V2DImode); -+ V2DF_type_node = -+ build_vector_type_for_mode (aarch64_simd_double_type_node, V2DFmode); -+ -+ /* Unsigned integer types for various mode sizes. */ -+ intUQI_type_node = make_unsigned_type (GET_MODE_PRECISION (QImode)); -+ intUHI_type_node = make_unsigned_type (GET_MODE_PRECISION (HImode)); -+ intUSI_type_node = make_unsigned_type (GET_MODE_PRECISION (SImode)); -+ intUDI_type_node = make_unsigned_type (GET_MODE_PRECISION (DImode)); -+ -+ (*lang_hooks.types.register_builtin_type) (intUQI_type_node, -+ "__builtin_aarch64_simd_uqi"); -+ (*lang_hooks.types.register_builtin_type) (intUHI_type_node, -+ "__builtin_aarch64_simd_uhi"); -+ (*lang_hooks.types.register_builtin_type) (intUSI_type_node, -+ "__builtin_aarch64_simd_usi"); -+ (*lang_hooks.types.register_builtin_type) (intUDI_type_node, -+ "__builtin_aarch64_simd_udi"); -+ -+ /* Opaque integer types for structures of vectors. */ -+ intEI_type_node = make_signed_type (GET_MODE_PRECISION (EImode)); -+ intOI_type_node = make_signed_type (GET_MODE_PRECISION (OImode)); -+ intCI_type_node = make_signed_type (GET_MODE_PRECISION (CImode)); -+ intXI_type_node = make_signed_type (GET_MODE_PRECISION (XImode)); -+ -+ (*lang_hooks.types.register_builtin_type) (intTI_type_node, -+ "__builtin_aarch64_simd_ti"); -+ (*lang_hooks.types.register_builtin_type) (intEI_type_node, -+ "__builtin_aarch64_simd_ei"); -+ (*lang_hooks.types.register_builtin_type) (intOI_type_node, -+ "__builtin_aarch64_simd_oi"); -+ (*lang_hooks.types.register_builtin_type) (intCI_type_node, -+ "__builtin_aarch64_simd_ci"); -+ (*lang_hooks.types.register_builtin_type) (intXI_type_node, -+ "__builtin_aarch64_simd_xi"); -+ -+ /* Pointers to vector types. */ -+ V8QI_pointer_node = build_pointer_type (V8QI_type_node); -+ V4HI_pointer_node = build_pointer_type (V4HI_type_node); -+ V2SI_pointer_node = build_pointer_type (V2SI_type_node); -+ V2SF_pointer_node = build_pointer_type (V2SF_type_node); -+ V16QI_pointer_node = build_pointer_type (V16QI_type_node); -+ V8HI_pointer_node = build_pointer_type (V8HI_type_node); -+ V4SI_pointer_node = build_pointer_type (V4SI_type_node); -+ V4SF_pointer_node = build_pointer_type (V4SF_type_node); -+ V2DI_pointer_node = build_pointer_type (V2DI_type_node); -+ V2DF_pointer_node = build_pointer_type (V2DF_type_node); -+ -+ /* Operations which return results as pairs. */ -+ void_ftype_pv8qi_v8qi_v8qi = -+ build_function_type_list (void_type_node, V8QI_pointer_node, -+ V8QI_type_node, V8QI_type_node, NULL); -+ void_ftype_pv4hi_v4hi_v4hi = -+ build_function_type_list (void_type_node, V4HI_pointer_node, -+ V4HI_type_node, V4HI_type_node, NULL); -+ void_ftype_pv2si_v2si_v2si = -+ build_function_type_list (void_type_node, V2SI_pointer_node, -+ V2SI_type_node, V2SI_type_node, NULL); -+ void_ftype_pv2sf_v2sf_v2sf = -+ build_function_type_list (void_type_node, V2SF_pointer_node, -+ V2SF_type_node, V2SF_type_node, NULL); -+ void_ftype_pdi_di_di = -+ build_function_type_list (void_type_node, intDI_pointer_node, -+ aarch64_simd_intDI_type_node, -+ aarch64_simd_intDI_type_node, NULL); -+ void_ftype_pv16qi_v16qi_v16qi = -+ build_function_type_list (void_type_node, V16QI_pointer_node, -+ V16QI_type_node, V16QI_type_node, NULL); -+ void_ftype_pv8hi_v8hi_v8hi = -+ build_function_type_list (void_type_node, V8HI_pointer_node, -+ V8HI_type_node, V8HI_type_node, NULL); -+ void_ftype_pv4si_v4si_v4si = -+ build_function_type_list (void_type_node, V4SI_pointer_node, -+ V4SI_type_node, V4SI_type_node, NULL); -+ void_ftype_pv4sf_v4sf_v4sf = -+ build_function_type_list (void_type_node, V4SF_pointer_node, -+ V4SF_type_node, V4SF_type_node, NULL); -+ void_ftype_pv2di_v2di_v2di = -+ build_function_type_list (void_type_node, V2DI_pointer_node, -+ V2DI_type_node, V2DI_type_node, NULL); -+ void_ftype_pv2df_v2df_v2df = -+ build_function_type_list (void_type_node, V2DF_pointer_node, -+ V2DF_type_node, V2DF_type_node, NULL); -+ -+ dreg_types[0] = V8QI_type_node; -+ dreg_types[1] = V4HI_type_node; -+ dreg_types[2] = V2SI_type_node; -+ dreg_types[3] = V2SF_type_node; -+ dreg_types[4] = aarch64_simd_intDI_type_node; -+ dreg_types[5] = aarch64_simd_double_type_node; -+ -+ qreg_types[0] = V16QI_type_node; -+ qreg_types[1] = V8HI_type_node; -+ qreg_types[2] = V4SI_type_node; -+ qreg_types[3] = V4SF_type_node; -+ qreg_types[4] = V2DI_type_node; -+ qreg_types[5] = V2DF_type_node; -+ -+ /* If NUM_DREG_TYPES != NUM_QREG_TYPES, we will need separate nested loops -+ for qreg and dreg reinterp inits. */ -+ for (i = 0; i < NUM_DREG_TYPES; i++) -+ { -+ int j; -+ for (j = 0; j < NUM_DREG_TYPES; j++) -+ { -+ reinterp_ftype_dreg[i][j] -+ = build_function_type_list (dreg_types[i], dreg_types[j], NULL); -+ reinterp_ftype_qreg[i][j] -+ = build_function_type_list (qreg_types[i], qreg_types[j], NULL); -+ } -+ } -+ -+ for (i = 0; i < ARRAY_SIZE (aarch64_simd_builtin_data); i++) -+ { -+ aarch64_simd_builtin_datum *d = &aarch64_simd_builtin_data[i]; -+ unsigned int j, codeidx = 0; -+ -+ d->base_fcode = fcode; -+ -+ for (j = 0; j < T_MAX; j++) -+ { -+ const char *const modenames[] = { -+ "v8qi", "v4hi", "v2si", "v2sf", "di", "df", -+ "v16qi", "v8hi", "v4si", "v4sf", "v2di", "v2df", -+ "ti", "ei", "oi", "xi", "si", "hi", "qi" -+ }; -+ char namebuf[60]; -+ tree ftype = NULL; -+ enum insn_code icode; -+ int is_load = 0, is_struct_load = 0; -+ int is_store = 0, is_struct_store = 0; -+ -+ /* Skip if particular mode not supported. */ -+ if ((d->bits & (1 << j)) == 0) -+ continue; -+ -+ icode = d->codes[codeidx++]; -+ -+ switch (d->itype) -+ { -+ case AARCH64_SIMD_LOAD1: -+ case AARCH64_SIMD_LOAD1LANE: -+ case AARCH64_SIMD_LOADSTRUCTLANE: -+ is_load = 1; -+ /* Fall through. */ -+ case AARCH64_SIMD_LOADSTRUCT: -+ if (!is_load) -+ is_struct_load = 1; -+ /* Fall through. */ -+ case AARCH64_SIMD_STORE1: -+ case AARCH64_SIMD_STORE1LANE: -+ case AARCH64_SIMD_STORESTRUCTLANE: -+ if (!is_load && !is_struct_load) -+ is_store = 1; -+ /* Fall through. */ -+ case AARCH64_SIMD_STORESTRUCT: -+ if (!is_load && !is_struct_load && !is_store) -+ is_struct_store = 1; -+ /* Fall through. */ -+ case AARCH64_SIMD_UNOP: -+ case AARCH64_SIMD_BINOP: -+ case AARCH64_SIMD_LOGICBINOP: -+ case AARCH64_SIMD_SHIFTINSERT: -+ case AARCH64_SIMD_TERNOP: -+ case AARCH64_SIMD_QUADOP: -+ case AARCH64_SIMD_GETLANE: -+ case AARCH64_SIMD_SETLANE: -+ case AARCH64_SIMD_CREATE: -+ case AARCH64_SIMD_DUP: -+ case AARCH64_SIMD_DUPLANE: -+ case AARCH64_SIMD_SHIFTIMM: -+ case AARCH64_SIMD_SHIFTACC: -+ case AARCH64_SIMD_COMBINE: -+ case AARCH64_SIMD_SPLIT: -+ case AARCH64_SIMD_CONVERT: -+ case AARCH64_SIMD_FIXCONV: -+ case AARCH64_SIMD_LANEMUL: -+ case AARCH64_SIMD_LANEMULL: -+ case AARCH64_SIMD_LANEMULH: -+ case AARCH64_SIMD_LANEMAC: -+ case AARCH64_SIMD_SCALARMUL: -+ case AARCH64_SIMD_SCALARMULL: -+ case AARCH64_SIMD_SCALARMULH: -+ case AARCH64_SIMD_SCALARMAC: -+ case AARCH64_SIMD_SELECT: -+ case AARCH64_SIMD_VTBL: -+ case AARCH64_SIMD_VTBX: -+ { -+ int k; -+ tree return_type = void_type_node, args = void_list_node; -+ -+ /* Build a function type directly from the insn_data for this -+ builtin. The build_function_type() function takes care of -+ removing duplicates for us. */ -+ for (k = insn_data[icode].n_operands - 1; k >= 0; k--) -+ { -+ tree eltype; -+ -+ /* Skip an internal operand for vget_{low, high}. */ -+ if (k == 2 && d->itype == AARCH64_SIMD_SPLIT) -+ continue; -+ -+ if (is_struct_load || (is_load && k == 1)) -+ { -+ /* AdvSIMD load patterns always have the memory operand -+ (a DImode pointer) in the operand 1 position. We -+ want a const pointer to the element type in that -+ position. */ -+ gcc_assert (insn_data[icode].operand[k].mode == -+ DImode); -+ -+ switch (1 << j) -+ { -+ case T_V8QI: -+ case T_V16QI: -+ eltype = const_intQI_pointer_node; -+ break; -+ -+ case T_V4HI: -+ case T_V8HI: -+ eltype = const_intHI_pointer_node; -+ break; -+ -+ case T_V2SI: -+ case T_V4SI: -+ eltype = const_intSI_pointer_node; -+ break; -+ -+ case T_V2SF: -+ case T_V4SF: -+ eltype = const_float_pointer_node; -+ break; -+ -+ case T_DI: -+ case T_V2DI: -+ eltype = const_intDI_pointer_node; -+ break; -+ -+ case T_V2DF: -+ eltype = const_double_pointer_node; -+ break; -+ -+ default: -+ gcc_unreachable (); -+ } -+ } -+ else if (is_struct_store || (is_store && k == 0)) -+ { -+ /* Similarly, AdvSIMD store patterns use operand 0 as -+ the memory location to store to (a DImode pointer). -+ Use a pointer to the element type of the store in -+ that position. */ -+ gcc_assert (insn_data[icode].operand[k].mode == -+ DImode); -+ -+ switch (1 << j) -+ { -+ case T_V8QI: -+ case T_V16QI: -+ eltype = intQI_pointer_node; -+ break; -+ -+ case T_V4HI: -+ case T_V8HI: -+ eltype = intHI_pointer_node; -+ break; -+ -+ case T_V2SI: -+ case T_V4SI: -+ eltype = intSI_pointer_node; -+ break; -+ -+ case T_V2SF: -+ case T_V4SF: -+ eltype = float_pointer_node; -+ break; -+ -+ case T_DI: -+ case T_V2DI: -+ eltype = intDI_pointer_node; -+ break; -+ -+ case T_V2DF: -+ eltype = double_pointer_node; -+ break; -+ -+ default: -+ gcc_unreachable (); -+ } -+ } -+ else -+ { -+ switch (insn_data[icode].operand[k].mode) -+ { -+ case VOIDmode: -+ eltype = void_type_node; -+ break; -+ /* Scalars. */ -+ case QImode: -+ eltype = aarch64_simd_intQI_type_node; -+ break; -+ case HImode: -+ eltype = aarch64_simd_intHI_type_node; -+ break; -+ case SImode: -+ eltype = aarch64_simd_intSI_type_node; -+ break; -+ case SFmode: -+ eltype = aarch64_simd_float_type_node; -+ break; -+ case DFmode: -+ eltype = aarch64_simd_double_type_node; -+ break; -+ case DImode: -+ eltype = aarch64_simd_intDI_type_node; -+ break; -+ case TImode: -+ eltype = intTI_type_node; -+ break; -+ case EImode: -+ eltype = intEI_type_node; -+ break; -+ case OImode: -+ eltype = intOI_type_node; -+ break; -+ case CImode: -+ eltype = intCI_type_node; -+ break; -+ case XImode: -+ eltype = intXI_type_node; -+ break; -+ /* 64-bit vectors. */ -+ case V8QImode: -+ eltype = V8QI_type_node; -+ break; -+ case V4HImode: -+ eltype = V4HI_type_node; -+ break; -+ case V2SImode: -+ eltype = V2SI_type_node; -+ break; -+ case V2SFmode: -+ eltype = V2SF_type_node; -+ break; -+ /* 128-bit vectors. */ -+ case V16QImode: -+ eltype = V16QI_type_node; -+ break; -+ case V8HImode: -+ eltype = V8HI_type_node; -+ break; -+ case V4SImode: -+ eltype = V4SI_type_node; -+ break; -+ case V4SFmode: -+ eltype = V4SF_type_node; -+ break; -+ case V2DImode: -+ eltype = V2DI_type_node; -+ break; -+ case V2DFmode: -+ eltype = V2DF_type_node; -+ break; -+ default: -+ gcc_unreachable (); -+ } -+ } -+ -+ if (k == 0 && !is_store && !is_struct_load -+ && !is_struct_store) -+ return_type = eltype; -+ else -+ args = tree_cons (NULL_TREE, eltype, args); -+ } -+ -+ ftype = build_function_type (return_type, args); -+ } -+ break; -+ -+ case AARCH64_SIMD_RESULTPAIR: -+ { -+ switch (insn_data[icode].operand[1].mode) -+ { -+ case V8QImode: -+ ftype = void_ftype_pv8qi_v8qi_v8qi; -+ break; -+ case V4HImode: -+ ftype = void_ftype_pv4hi_v4hi_v4hi; -+ break; -+ case V2SImode: -+ ftype = void_ftype_pv2si_v2si_v2si; -+ break; -+ case V2SFmode: -+ ftype = void_ftype_pv2sf_v2sf_v2sf; -+ break; -+ case DImode: -+ ftype = void_ftype_pdi_di_di; -+ break; -+ case V16QImode: -+ ftype = void_ftype_pv16qi_v16qi_v16qi; -+ break; -+ case V8HImode: -+ ftype = void_ftype_pv8hi_v8hi_v8hi; -+ break; -+ case V4SImode: -+ ftype = void_ftype_pv4si_v4si_v4si; -+ break; -+ case V4SFmode: -+ ftype = void_ftype_pv4sf_v4sf_v4sf; -+ break; -+ case V2DImode: -+ ftype = void_ftype_pv2di_v2di_v2di; -+ break; -+ case V2DFmode: -+ ftype = void_ftype_pv2df_v2df_v2df; -+ break; -+ default: -+ gcc_unreachable (); -+ } -+ } -+ break; -+ -+ case AARCH64_SIMD_REINTERP: -+ { -+ /* We iterate over 6 doubleword types, then 6 quadword -+ types. */ -+ int rhs_d = j % NUM_DREG_TYPES; -+ int rhs_q = (j - NUM_DREG_TYPES) % NUM_QREG_TYPES; -+ switch (insn_data[icode].operand[0].mode) -+ { -+ case V8QImode: -+ ftype = reinterp_ftype_dreg[0][rhs_d]; -+ break; -+ case V4HImode: -+ ftype = reinterp_ftype_dreg[1][rhs_d]; -+ break; -+ case V2SImode: -+ ftype = reinterp_ftype_dreg[2][rhs_d]; -+ break; -+ case V2SFmode: -+ ftype = reinterp_ftype_dreg[3][rhs_d]; -+ break; -+ case DImode: -+ ftype = reinterp_ftype_dreg[4][rhs_d]; -+ break; -+ case DFmode: -+ ftype = reinterp_ftype_dreg[5][rhs_d]; -+ break; -+ case V16QImode: -+ ftype = reinterp_ftype_qreg[0][rhs_q]; -+ break; -+ case V8HImode: -+ ftype = reinterp_ftype_qreg[1][rhs_q]; -+ break; -+ case V4SImode: -+ ftype = reinterp_ftype_qreg[2][rhs_q]; -+ break; -+ case V4SFmode: -+ ftype = reinterp_ftype_qreg[3][rhs_q]; -+ break; -+ case V2DImode: -+ ftype = reinterp_ftype_qreg[4][rhs_q]; -+ break; -+ case V2DFmode: -+ ftype = reinterp_ftype_qreg[5][rhs_q]; -+ break; -+ default: -+ gcc_unreachable (); -+ } -+ } -+ break; -+ -+ default: -+ gcc_unreachable (); -+ } -+ -+ gcc_assert (ftype != NULL); -+ -+ snprintf (namebuf, sizeof (namebuf), "__builtin_aarch64_%s%s", -+ d->name, modenames[j]); -+ -+ add_builtin_function (namebuf, ftype, fcode++, BUILT_IN_MD, NULL, -+ NULL_TREE); -+ } -+ } -+} -+ -+static int -+aarch64_simd_builtin_compare (const void *a, const void *b) -+{ -+ const aarch64_simd_builtin_datum *const key = -+ (const aarch64_simd_builtin_datum *) a; -+ const aarch64_simd_builtin_datum *const memb = -+ (const aarch64_simd_builtin_datum *) b; -+ unsigned int soughtcode = key->base_fcode; -+ -+ if (soughtcode >= memb->base_fcode -+ && soughtcode < memb->base_fcode + memb->num_vars) -+ return 0; -+ else if (soughtcode < memb->base_fcode) -+ return -1; -+ else -+ return 1; -+} -+ -+ -+static enum insn_code -+locate_simd_builtin_icode (int fcode, aarch64_simd_itype * itype) -+{ -+ aarch64_simd_builtin_datum key -+ = { NULL, (aarch64_simd_itype) 0, 0, {CODE_FOR_nothing}, 0, 0}; -+ aarch64_simd_builtin_datum *found; -+ int idx; -+ -+ key.base_fcode = fcode; -+ found = (aarch64_simd_builtin_datum *) -+ bsearch (&key, &aarch64_simd_builtin_data[0], -+ ARRAY_SIZE (aarch64_simd_builtin_data), -+ sizeof (aarch64_simd_builtin_data[0]), -+ aarch64_simd_builtin_compare); -+ gcc_assert (found); -+ idx = fcode - (int) found->base_fcode; -+ gcc_assert (idx >= 0 && idx < T_MAX && idx < (int) found->num_vars); -+ -+ if (itype) -+ *itype = found->itype; -+ -+ return found->codes[idx]; -+} -+ -+typedef enum -+{ -+ SIMD_ARG_COPY_TO_REG, -+ SIMD_ARG_CONSTANT, -+ SIMD_ARG_STOP -+} builtin_simd_arg; -+ -+#define SIMD_MAX_BUILTIN_ARGS 5 -+ -+static rtx -+aarch64_simd_expand_args (rtx target, int icode, int have_retval, -+ tree exp, ...) -+{ -+ va_list ap; -+ rtx pat; -+ tree arg[SIMD_MAX_BUILTIN_ARGS]; -+ rtx op[SIMD_MAX_BUILTIN_ARGS]; -+ enum machine_mode tmode = insn_data[icode].operand[0].mode; -+ enum machine_mode mode[SIMD_MAX_BUILTIN_ARGS]; -+ int argc = 0; -+ -+ if (have_retval -+ && (!target -+ || GET_MODE (target) != tmode -+ || !(*insn_data[icode].operand[0].predicate) (target, tmode))) -+ target = gen_reg_rtx (tmode); -+ -+ va_start (ap, exp); -+ -+ for (;;) -+ { -+ builtin_simd_arg thisarg = (builtin_simd_arg) va_arg (ap, int); -+ -+ if (thisarg == SIMD_ARG_STOP) -+ break; -+ else -+ { -+ arg[argc] = CALL_EXPR_ARG (exp, argc); -+ op[argc] = expand_normal (arg[argc]); -+ mode[argc] = insn_data[icode].operand[argc + have_retval].mode; -+ -+ switch (thisarg) -+ { -+ case SIMD_ARG_COPY_TO_REG: -+ /*gcc_assert (GET_MODE (op[argc]) == mode[argc]); */ -+ if (!(*insn_data[icode].operand[argc + have_retval].predicate) -+ (op[argc], mode[argc])) -+ op[argc] = copy_to_mode_reg (mode[argc], op[argc]); -+ break; -+ -+ case SIMD_ARG_CONSTANT: -+ if (!(*insn_data[icode].operand[argc + have_retval].predicate) -+ (op[argc], mode[argc])) -+ error_at (EXPR_LOCATION (exp), "incompatible type for argument %d, " -+ "expected %", argc + 1); -+ break; -+ -+ case SIMD_ARG_STOP: -+ gcc_unreachable (); -+ } -+ -+ argc++; -+ } -+ } -+ -+ va_end (ap); -+ -+ if (have_retval) -+ switch (argc) -+ { -+ case 1: -+ pat = GEN_FCN (icode) (target, op[0]); -+ break; -+ -+ case 2: -+ pat = GEN_FCN (icode) (target, op[0], op[1]); -+ break; -+ -+ case 3: -+ pat = GEN_FCN (icode) (target, op[0], op[1], op[2]); -+ break; -+ -+ case 4: -+ pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3]); -+ break; -+ -+ case 5: -+ pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3], op[4]); -+ break; -+ -+ default: -+ gcc_unreachable (); -+ } -+ else -+ switch (argc) -+ { -+ case 1: -+ pat = GEN_FCN (icode) (op[0]); -+ break; -+ -+ case 2: -+ pat = GEN_FCN (icode) (op[0], op[1]); -+ break; -+ -+ case 3: -+ pat = GEN_FCN (icode) (op[0], op[1], op[2]); -+ break; -+ -+ case 4: -+ pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]); -+ break; -+ -+ case 5: -+ pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]); -+ break; -+ -+ default: -+ gcc_unreachable (); -+ } -+ -+ if (!pat) -+ return 0; -+ -+ emit_insn (pat); -+ -+ return target; -+} -+ -+/* Expand an AArch64 AdvSIMD builtin(intrinsic). */ -+rtx -+aarch64_simd_expand_builtin (int fcode, tree exp, rtx target) -+{ -+ aarch64_simd_itype itype; -+ enum insn_code icode = locate_simd_builtin_icode (fcode, &itype); -+ -+ switch (itype) -+ { -+ case AARCH64_SIMD_UNOP: -+ return aarch64_simd_expand_args (target, icode, 1, exp, -+ SIMD_ARG_COPY_TO_REG, -+ SIMD_ARG_STOP); -+ -+ case AARCH64_SIMD_BINOP: -+ { -+ bool op1_const_int_p -+ = CONST_INT_P (expand_normal (CALL_EXPR_ARG (exp, 1))); -+ return aarch64_simd_expand_args (target, icode, 1, exp, -+ SIMD_ARG_COPY_TO_REG, -+ op1_const_int_p ? SIMD_ARG_CONSTANT -+ : SIMD_ARG_COPY_TO_REG, -+ SIMD_ARG_STOP); -+ } -+ -+ case AARCH64_SIMD_TERNOP: -+ return aarch64_simd_expand_args (target, icode, 1, exp, -+ SIMD_ARG_COPY_TO_REG, -+ SIMD_ARG_COPY_TO_REG, -+ SIMD_ARG_COPY_TO_REG, -+ SIMD_ARG_STOP); -+ -+ case AARCH64_SIMD_QUADOP: -+ return aarch64_simd_expand_args (target, icode, 1, exp, -+ SIMD_ARG_COPY_TO_REG, -+ SIMD_ARG_COPY_TO_REG, -+ SIMD_ARG_COPY_TO_REG, -+ SIMD_ARG_COPY_TO_REG, -+ SIMD_ARG_STOP); -+ case AARCH64_SIMD_LOAD1: -+ return aarch64_simd_expand_args (target, icode, 1, exp, -+ SIMD_ARG_COPY_TO_REG, SIMD_ARG_STOP); -+ -+ case AARCH64_SIMD_REINTERP: -+ return aarch64_simd_expand_args (target, icode, 1, exp, -+ SIMD_ARG_COPY_TO_REG, SIMD_ARG_STOP); -+ -+ case AARCH64_SIMD_CREATE: -+ return aarch64_simd_expand_args (target, icode, 1, exp, -+ SIMD_ARG_COPY_TO_REG, SIMD_ARG_STOP); -+ -+ case AARCH64_SIMD_COMBINE: -+ return aarch64_simd_expand_args (target, icode, 1, exp, -+ SIMD_ARG_COPY_TO_REG, -+ SIMD_ARG_COPY_TO_REG, SIMD_ARG_STOP); -+ -+ case AARCH64_SIMD_GETLANE: -+ return aarch64_simd_expand_args (target, icode, 1, exp, -+ SIMD_ARG_COPY_TO_REG, -+ SIMD_ARG_CONSTANT, -+ SIMD_ARG_STOP); -+ case AARCH64_SIMD_SHIFTIMM: -+ return aarch64_simd_expand_args (target, icode, 1, exp, -+ SIMD_ARG_COPY_TO_REG, -+ SIMD_ARG_CONSTANT, -+ SIMD_ARG_STOP); -+ -+ case AARCH64_SIMD_SHIFTACC: -+ case AARCH64_SIMD_SHIFTINSERT: -+ return aarch64_simd_expand_args (target, icode, 1, exp, -+ SIMD_ARG_COPY_TO_REG, -+ SIMD_ARG_COPY_TO_REG, -+ SIMD_ARG_CONSTANT, -+ SIMD_ARG_STOP); -+ -+ default: -+ gcc_unreachable (); -+ } -+} - -Property changes on: gcc/config/aarch64/aarch64-builtins.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/config/aarch64/aarch64-tune.md -=================================================================== ---- a/src/gcc/config/aarch64/aarch64-tune.md (.../gcc-4_7-branch) -+++ b/src/gcc/config/aarch64/aarch64-tune.md (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,5 @@ -+;; -*- buffer-read-only: t -*- -+;; Generated automatically by gentune.sh from aarch64-cores.def -+(define_attr "tune" -+ "large,small" -+ (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) -Index: gcc/config/aarch64/aarch64-opts.h -=================================================================== ---- a/src/gcc/config/aarch64/aarch64-opts.h (.../gcc-4_7-branch) -+++ b/src/gcc/config/aarch64/aarch64-opts.h (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,64 @@ -+/* Copyright (C) 2011, 2012 Free Software Foundation, Inc. -+ Contributed by ARM Ltd. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+/* Definitions for option handling for AArch64. */ -+ -+#ifndef GCC_AARCH64_OPTS_H -+#define GCC_AARCH64_OPTS_H -+ -+/* The various cores that implement AArch64. */ -+enum aarch64_processor -+{ -+#define AARCH64_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ -+ IDENT, -+#include "aarch64-cores.def" -+#undef AARCH64_CORE -+ /* Used to indicate that no processor has been specified. */ -+ generic, -+ /* Used to mark the end of the processor table. */ -+ aarch64_none -+}; -+ -+/* TLS types. */ -+enum aarch64_tls_type { -+ TLS_TRADITIONAL, -+ TLS_DESCRIPTORS -+}; -+ -+/* The code model defines the address generation strategy. -+ Most have a PIC and non-PIC variant. */ -+enum aarch64_code_model { -+ /* Static code and data fit within a 1MB region. -+ Not fully implemented, mostly treated as SMALL. */ -+ AARCH64_CMODEL_TINY, -+ /* Static code, data and GOT/PLT fit within a 1MB region. -+ Not fully implemented, mostly treated as SMALL_PIC. */ -+ AARCH64_CMODEL_TINY_PIC, -+ /* Static code and data fit within a 4GB region. -+ The default non-PIC code model. */ -+ AARCH64_CMODEL_SMALL, -+ /* Static code, data and GOT/PLT fit within a 4GB region. -+ The default PIC code model. */ -+ AARCH64_CMODEL_SMALL_PIC, -+ /* No assumptions about addresses of code and data. -+ The PIC variant is not yet implemented. */ -+ AARCH64_CMODEL_LARGE -+}; -+ -+#endif - -Property changes on: gcc/config/aarch64/aarch64-opts.h -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/config/aarch64/aarch64-generic.md -=================================================================== ---- a/src/gcc/config/aarch64/aarch64-generic.md (.../gcc-4_7-branch) -+++ b/src/gcc/config/aarch64/aarch64-generic.md (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,38 @@ -+;; Machine description for AArch64 architecture. -+;; Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. -+;; Contributed by ARM Ltd. -+;; -+;; This file is part of GCC. -+;; -+;; GCC is free software; you can redistribute it and/or modify it -+;; under the terms of the GNU General Public License as published by -+;; the Free Software Foundation; either version 3, or (at your option) -+;; any later version. -+;; -+;; GCC is distributed in the hope that it will be useful, but -+;; WITHOUT ANY WARRANTY; without even the implied warranty of -+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+;; General Public License for more details. -+;; -+;; You should have received a copy of the GNU General Public License -+;; along with GCC; see the file COPYING3. If not see -+;; . -+ -+;; Generic scheduler -+ -+(define_automaton "aarch64") -+ -+(define_cpu_unit "core" "aarch64") -+ -+(define_attr "is_load" "yes,no" -+ (if_then_else (eq_attr "v8type" "fpsimd_load,fpsimd_load2,load1,load2") -+ (const_string "yes") -+ (const_string "no"))) -+ -+(define_insn_reservation "load" 2 -+ (eq_attr "is_load" "yes") -+ "core") -+ -+(define_insn_reservation "nonload" 1 -+ (eq_attr "is_load" "no") -+ "core") -Index: gcc/config/aarch64/aarch64-protos.h -=================================================================== ---- a/src/gcc/config/aarch64/aarch64-protos.h (.../gcc-4_7-branch) -+++ b/src/gcc/config/aarch64/aarch64-protos.h (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,253 @@ -+/* Machine description for AArch64 architecture. -+ Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. -+ Contributed by ARM Ltd. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3, or (at your option) -+ any later version. -+ -+ GCC is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+ -+#ifndef GCC_AARCH64_PROTOS_H -+#define GCC_AARCH64_PROTOS_H -+ -+ /* This generator struct and enum is used to wrap a function pointer -+ to a function that generates an RTX fragment but takes either 3 or -+ 4 operands. -+ -+ The omn flavour, wraps a function that generates a synchronization -+ instruction from 3 operands: old value, memory and new value. -+ -+ The omrn flavour, wraps a function that generates a synchronization -+ instruction from 4 operands: old value, memory, required value and -+ new value. */ -+ -+enum aarch64_sync_generator_tag -+{ -+ aarch64_sync_generator_omn, -+ aarch64_sync_generator_omrn -+}; -+ -+ /* Wrapper to pass around a polymorphic pointer to a sync instruction -+ generator and. */ -+struct aarch64_sync_generator -+{ -+ enum aarch64_sync_generator_tag op; -+ union -+ { -+ rtx (*omn) (rtx, rtx, rtx); -+ rtx (*omrn) (rtx, rtx, rtx, rtx); -+ } u; -+}; -+ -+/* -+ SYMBOL_CONTEXT_ADR -+ The symbol is used in a load-address operation. -+ SYMBOL_CONTEXT_MEM -+ The symbol is used as the address in a MEM. -+ */ -+enum aarch64_symbol_context -+{ -+ SYMBOL_CONTEXT_MEM, -+ SYMBOL_CONTEXT_ADR -+}; -+ -+/* SYMBOL_SMALL_ABSOLUTE: Generate symbol accesses through -+ high and lo relocs that calculate the base address using a PC -+ relative reloc. -+ So to get the address of foo, we generate -+ adrp x0, foo -+ add x0, x0, :lo12:foo -+ -+ To load or store something to foo, we could use the corresponding -+ load store variants that generate an -+ ldr x0, [x0,:lo12:foo] -+ or -+ str x1, [x0, :lo12:foo] -+ -+ This corresponds to the small code model of the compiler. -+ -+ SYMBOL_SMALL_GOT: Similar to the one above but this -+ gives us the GOT entry of the symbol being referred to : -+ Thus calculating the GOT entry for foo is done using the -+ following sequence of instructions. The ADRP instruction -+ gets us to the page containing the GOT entry of the symbol -+ and the got_lo12 gets us the actual offset in it. -+ -+ adrp x0, :got:foo -+ ldr x0, [x0, :gotoff_lo12:foo] -+ -+ This corresponds to the small PIC model of the compiler. -+ -+ SYMBOL_SMALL_TLSGD -+ SYMBOL_SMALL_TLSDESC -+ SYMBOL_SMALL_GOTTPREL -+ SYMBOL_SMALL_TPREL -+ Each of of these represents a thread-local symbol, and corresponds to the -+ thread local storage relocation operator for the symbol being referred to. -+ -+ SYMBOL_FORCE_TO_MEM : Global variables are addressed using -+ constant pool. All variable addresses are spilled into constant -+ pools. The constant pools themselves are addressed using PC -+ relative accesses. This only works for the large code model. -+ */ -+enum aarch64_symbol_type -+{ -+ SYMBOL_SMALL_ABSOLUTE, -+ SYMBOL_SMALL_GOT, -+ SYMBOL_SMALL_TLSGD, -+ SYMBOL_SMALL_TLSDESC, -+ SYMBOL_SMALL_GOTTPREL, -+ SYMBOL_SMALL_TPREL, -+ SYMBOL_FORCE_TO_MEM -+}; -+ -+/* A set of tuning parameters contains references to size and time -+ cost models and vectors for address cost calculations, register -+ move costs and memory move costs. */ -+ -+/* Extra costs for specific insns. Only records the cost above a -+ single insn. */ -+ -+struct cpu_rtx_cost_table -+{ -+ const int memory_load; -+ const int memory_store; -+ const int register_shift; -+ const int int_divide; -+ const int float_divide; -+ const int double_divide; -+ const int int_multiply; -+ const int int_multiply_extend; -+ const int int_multiply_add; -+ const int int_multiply_extend_add; -+ const int float_multiply; -+ const int double_multiply; -+}; -+ -+/* Additional cost for addresses. */ -+struct cpu_addrcost_table -+{ -+ const int pre_modify; -+ const int post_modify; -+ const int register_offset; -+ const int register_extend; -+ const int imm_offset; -+}; -+ -+/* Additional costs for register copies. Cost is for one register. */ -+struct cpu_regmove_cost -+{ -+ const int GP2GP; -+ const int GP2FP; -+ const int FP2GP; -+ const int FP2FP; -+}; -+ -+struct tune_params -+{ -+ const struct cpu_rtx_cost_table *const insn_extra_cost; -+ const struct cpu_addrcost_table *const addr_cost; -+ const struct cpu_regmove_cost *const regmove_cost; -+ const int memmov_cost; -+}; -+ -+HOST_WIDE_INT aarch64_initial_elimination_offset (unsigned, unsigned); -+bool aarch64_bitmask_imm (HOST_WIDE_INT val, enum machine_mode); -+bool aarch64_const_double_zero_rtx_p (rtx); -+bool aarch64_constant_address_p (rtx); -+bool aarch64_function_arg_regno_p (unsigned); -+bool aarch64_gen_movmemqi (rtx *); -+bool aarch64_is_extend_from_extract (enum machine_mode, rtx, rtx); -+bool aarch64_is_long_call_p (rtx); -+bool aarch64_label_mentioned_p (rtx); -+bool aarch64_legitimate_pic_operand_p (rtx); -+bool aarch64_move_imm (HOST_WIDE_INT, enum machine_mode); -+bool aarch64_pad_arg_upward (enum machine_mode, const_tree); -+bool aarch64_pad_reg_upward (enum machine_mode, const_tree, bool); -+bool aarch64_regno_ok_for_base_p (int, bool); -+bool aarch64_regno_ok_for_index_p (int, bool); -+bool aarch64_simd_shift_imm_p (rtx, enum machine_mode, bool); -+bool aarch64_symbolic_address_p (rtx); -+bool aarch64_symbolic_constant_p (rtx, enum aarch64_symbol_context, -+ enum aarch64_symbol_type *); -+bool aarch64_uimm12_shift (HOST_WIDE_INT); -+const char *aarch64_output_casesi (rtx *); -+const char *aarch64_output_sync_insn (rtx, rtx *); -+const char *aarch64_output_sync_lock_release (rtx, rtx); -+enum aarch64_symbol_type aarch64_classify_symbol (rtx, -+ enum aarch64_symbol_context); -+enum aarch64_symbol_type aarch64_classify_tls_symbol (rtx); -+int aarch64_asm_preferred_eh_data_format (int, int); -+int aarch64_hard_regno_mode_ok (unsigned, enum machine_mode); -+int aarch64_hard_regno_nregs (unsigned, enum machine_mode); -+int aarch64_simd_immediate_valid_for_move (rtx, enum machine_mode, rtx *, -+ int *, unsigned char *, int *, -+ int *); -+int aarch64_uxt_size (int, HOST_WIDE_INT); -+rtx aarch64_final_eh_return_addr (void); -+rtx aarch64_legitimize_reload_address (rtx *, enum machine_mode, int, int, -+ int); -+rtx aarch64_return_addr (int, rtx); -+rtx aarch64_simd_gen_const_vector_dup (enum machine_mode, int); -+rtx aarch64_simd_vect_par_cnst_half (enum machine_mode, bool); -+rtx aarch64_tls_get_addr (void); -+unsigned aarch64_dbx_register_number (unsigned); -+unsigned aarch64_regno_regclass (unsigned); -+unsigned aarch64_trampoline_size (void); -+unsigned aarch64_sync_loop_insns (rtx, rtx *); -+void aarch64_asm_output_labelref (FILE *, const char *); -+void aarch64_elf_asm_named_section (const char *, unsigned, tree); -+void aarch64_expand_epilogue (bool); -+void aarch64_expand_mov_immediate (rtx, rtx); -+void aarch64_expand_prologue (void); -+void aarch64_expand_sync (enum machine_mode, struct aarch64_sync_generator *, -+ rtx, rtx, rtx, rtx); -+void aarch64_function_profiler (FILE *, int); -+void aarch64_init_cumulative_args (CUMULATIVE_ARGS *, const_tree, rtx, -+ const_tree, unsigned); -+void aarch64_init_expanders (void); -+void aarch64_print_operand (FILE *, rtx, char); -+void aarch64_print_operand_address (FILE *, rtx); -+ -+/* Initialize builtins for SIMD intrinsics. */ -+void init_aarch64_simd_builtins (void); -+ -+void aarch64_simd_const_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT); -+ -+/* Emit code to place a AdvSIMD pair result in memory locations (with equal -+ registers). */ -+void aarch64_simd_emit_pair_result_insn (enum machine_mode, -+ rtx (*intfn) (rtx, rtx, rtx), rtx, -+ rtx); -+ -+/* Expand builtins for SIMD intrinsics. */ -+rtx aarch64_simd_expand_builtin (int, tree, rtx); -+ -+void aarch64_simd_lane_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT); -+ -+/* Emit code for reinterprets. */ -+void aarch64_simd_reinterpret (rtx, rtx); -+ -+void aarch64_split_doubleword_move (rtx, rtx); -+ -+#if defined (RTX_CODE) -+ -+bool aarch64_legitimate_address_p (enum machine_mode, rtx, RTX_CODE, bool); -+enum machine_mode aarch64_select_cc_mode (RTX_CODE, rtx, rtx); -+rtx aarch64_gen_compare_reg (RTX_CODE, rtx, rtx); -+ -+#endif /* RTX_CODE */ -+ -+#endif /* GCC_AARCH64_PROTOS_H */ - -Property changes on: gcc/config/aarch64/aarch64-protos.h -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/config/aarch64/constraints.md -=================================================================== ---- a/src/gcc/config/aarch64/constraints.md (.../gcc-4_7-branch) -+++ b/src/gcc/config/aarch64/constraints.md (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,149 @@ -+;; Machine description for AArch64 architecture. -+;; Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. -+;; Contributed by ARM Ltd. -+;; -+;; This file is part of GCC. -+;; -+;; GCC is free software; you can redistribute it and/or modify it -+;; under the terms of the GNU General Public License as published by -+;; the Free Software Foundation; either version 3, or (at your option) -+;; any later version. -+;; -+;; GCC is distributed in the hope that it will be useful, but -+;; WITHOUT ANY WARRANTY; without even the implied warranty of -+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+;; General Public License for more details. -+;; -+;; You should have received a copy of the GNU General Public License -+;; along with GCC; see the file COPYING3. If not see -+;; . -+ -+(define_register_constraint "k" "STACK_REG" -+ "@internal The stack register.") -+ -+(define_register_constraint "w" "FP_REGS" -+ "Floating point and SIMD vector registers.") -+ -+(define_register_constraint "x" "FP_LO_REGS" -+ "Floating point and SIMD vector registers V0 - V15.") -+ -+(define_constraint "I" -+ "A constant that can be used with an ADD operation." -+ (and (match_code "const_int") -+ (match_test "aarch64_uimm12_shift (ival)"))) -+ -+(define_constraint "J" -+ "A constant that can be used with a SUB operation (once negated)." -+ (and (match_code "const_int") -+ (match_test "aarch64_uimm12_shift (-ival)"))) -+ -+;; We can't use the mode of a CONST_INT to determine the context in -+;; which it is being used, so we must have a separate constraint for -+;; each context. -+ -+(define_constraint "K" -+ "A constant that can be used with a 32-bit logical operation." -+ (and (match_code "const_int") -+ (match_test "aarch64_bitmask_imm (ival, SImode)"))) -+ -+(define_constraint "L" -+ "A constant that can be used with a 64-bit logical operation." -+ (and (match_code "const_int") -+ (match_test "aarch64_bitmask_imm (ival, DImode)"))) -+ -+(define_constraint "M" -+ "A constant that can be used with a 32-bit MOV immediate operation." -+ (and (match_code "const_int") -+ (match_test "aarch64_move_imm (ival, SImode)"))) -+ -+(define_constraint "N" -+ "A constant that can be used with a 64-bit MOV immediate operation." -+ (and (match_code "const_int") -+ (match_test "aarch64_move_imm (ival, DImode)"))) -+ -+(define_constraint "S" -+ "A constraint that matches an absolute symbolic address." -+ (and (match_code "const,symbol_ref,label_ref") -+ (match_test "aarch64_symbolic_address_p (op)"))) -+ -+(define_constraint "Y" -+ "Floating point constant zero." -+ (and (match_code "const_double") -+ (match_test "aarch64_const_double_zero_rtx_p (op)"))) -+ -+(define_constraint "Z" -+ "Integer constant zero." -+ (match_test "op == const0_rtx")) -+ -+(define_constraint "Usa" -+ "A constraint that matches an absolute symbolic address." -+ (and (match_code "const,symbol_ref") -+ (match_test "aarch64_symbolic_address_p (op)"))) -+ -+(define_constraint "Ush" -+ "A constraint that matches an absolute symbolic address high part." -+ (and (match_code "high") -+ (match_test "aarch64_valid_symref (XEXP (op, 0), GET_MODE (XEXP (op, 0)))"))) -+ -+(define_constraint "Uss" -+ "@internal -+ A constraint that matches an immediate shift constant in SImode." -+ (and (match_code "const_int") -+ (match_test "(unsigned HOST_WIDE_INT) ival < 32"))) -+ -+(define_constraint "Usd" -+ "@internal -+ A constraint that matches an immediate shift constant in DImode." -+ (and (match_code "const_int") -+ (match_test "(unsigned HOST_WIDE_INT) ival < 64"))) -+ -+(define_constraint "UsM" -+ "@internal -+ A constraint that matches the immediate constant -1." -+ (match_test "op == constm1_rtx")) -+ -+(define_constraint "Ui3" -+ "@internal -+ A constraint that matches the integers 0...4." -+ (and (match_code "const_int") -+ (match_test "(unsigned HOST_WIDE_INT) ival <= 4"))) -+ -+(define_constraint "Up3" -+ "@internal -+ A constraint that matches the integers 2^(0...4)." -+ (and (match_code "const_int") -+ (match_test "(unsigned) exact_log2 (ival) <= 4"))) -+ -+(define_memory_constraint "Q" -+ "A memory address which uses a single base register with no offset." -+ (and (match_code "mem") -+ (match_test "REG_P (XEXP (op, 0))"))) -+ -+(define_memory_constraint "Ump" -+ "@internal -+ A memory address suitable for a load/store pair operation." -+ (and (match_code "mem") -+ (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0), -+ PARALLEL, 1)"))) -+ -+(define_constraint "Dn" -+ "@internal -+ A constraint that matches vector of immediates." -+ (and (match_code "const_vector") -+ (match_test "aarch64_simd_immediate_valid_for_move (op, GET_MODE (op), -+ NULL, NULL, NULL, -+ NULL, NULL) != 0"))) -+ -+(define_constraint "Dl" -+ "@internal -+ A constraint that matches vector of immediates for left shifts." -+ (and (match_code "const_vector") -+ (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op), -+ true)"))) -+ -+(define_constraint "Dr" -+ "@internal -+ A constraint that matches vector of immediates for right shifts." -+ (and (match_code "const_vector") -+ (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op), -+ false)"))) -Index: gcc/config/aarch64/small.md -=================================================================== ---- a/src/gcc/config/aarch64/small.md (.../gcc-4_7-branch) -+++ b/src/gcc/config/aarch64/small.md (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,287 @@ -+;; Copyright (C) 2012 Free Software Foundation, Inc. -+;; -+;; Contributed by ARM Ltd. -+;; -+;; This file is part of GCC. -+;; -+;; GCC is free software; you can redistribute it and/or modify it -+;; under the terms of the GNU General Public License as published by -+;; the Free Software Foundation; either version 3, or (at your option) -+;; any later version. -+;; -+;; GCC is distributed in the hope that it will be useful, but -+;; WITHOUT ANY WARRANTY; without even the implied warranty of -+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+;; General Public License for more details. -+;; -+;; You should have received a copy of the GNU General Public License -+;; along with GCC; see the file COPYING3. If not see -+;; . -+ -+;; In the absence of any ARMv8-A implementations, two examples derived -+;; from ARM's most recent ARMv7-A cores (Cortex-A7 and Cortex-A15) are -+;; included by way of example. This is a temporary measure. -+ -+;; Example pipeline description for an example 'small' core -+;; implementing AArch64 -+ -+;;------------------------------------------------------- -+;; General Description -+;;------------------------------------------------------- -+ -+(define_automaton "small_cpu") -+ -+;; The core is modelled as a single issue pipeline with the following -+;; dispatch units. -+;; 1. One pipeline for simple intructions. -+;; 2. One pipeline for branch intructions. -+;; -+;; There are five pipeline stages. -+;; The decode/issue stages operate the same for all instructions. -+;; Instructions always advance one stage per cycle in order. -+;; Only branch instructions may dual-issue with other instructions, except -+;; when those instructions take multiple cycles to issue. -+ -+ -+;;------------------------------------------------------- -+;; CPU Units and Reservations -+;;------------------------------------------------------- -+ -+(define_cpu_unit "small_cpu_unit_i" "small_cpu") -+(define_cpu_unit "small_cpu_unit_br" "small_cpu") -+ -+;; Pseudo-unit for blocking the multiply pipeline when a double-precision -+;; multiply is in progress. -+(define_cpu_unit "small_cpu_unit_fpmul_pipe" "small_cpu") -+ -+;; The floating-point add pipeline, used to model the usage -+;; of the add pipeline by fp alu instructions. -+(define_cpu_unit "small_cpu_unit_fpadd_pipe" "small_cpu") -+ -+;; Floating-point division pipeline (long latency, out-of-order completion). -+(define_cpu_unit "small_cpu_unit_fpdiv" "small_cpu") -+ -+ -+;;------------------------------------------------------- -+;; Simple ALU Instructions -+;;------------------------------------------------------- -+ -+;; Simple ALU operations without shift -+(define_insn_reservation "small_cpu_alu" 2 -+ (and (eq_attr "tune" "small") -+ (eq_attr "v8type" "adc,alu,alu_ext")) -+ "small_cpu_unit_i") -+ -+(define_insn_reservation "small_cpu_logic" 2 -+ (and (eq_attr "tune" "small") -+ (eq_attr "v8type" "logic,logic_imm")) -+ "small_cpu_unit_i") -+ -+(define_insn_reservation "small_cpu_shift" 2 -+ (and (eq_attr "tune" "small") -+ (eq_attr "v8type" "shift,shift_imm")) -+ "small_cpu_unit_i") -+ -+;; Simple ALU operations with immediate shift -+(define_insn_reservation "small_cpu_alu_shift" 2 -+ (and (eq_attr "tune" "small") -+ (eq_attr "v8type" "alu_shift")) -+ "small_cpu_unit_i") -+ -+(define_insn_reservation "small_cpu_logic_shift" 2 -+ (and (eq_attr "tune" "small") -+ (eq_attr "v8type" "logic_shift")) -+ "small_cpu_unit_i") -+ -+ -+;;------------------------------------------------------- -+;; Multiplication/Division -+;;------------------------------------------------------- -+ -+;; Simple multiplication -+(define_insn_reservation "small_cpu_mult_single" 2 -+ (and (eq_attr "tune" "small") -+ (and (eq_attr "v8type" "mult,madd") (eq_attr "mode" "SI"))) -+ "small_cpu_unit_i") -+ -+(define_insn_reservation "small_cpu_mult_double" 3 -+ (and (eq_attr "tune" "small") -+ (and (eq_attr "v8type" "mult,madd") (eq_attr "mode" "DI"))) -+ "small_cpu_unit_i") -+ -+;; 64-bit multiplication -+(define_insn_reservation "small_cpu_mull" 3 -+ (and (eq_attr "tune" "small") (eq_attr "v8type" "mull,mulh,maddl")) -+ "small_cpu_unit_i * 2") -+ -+;; Division -+(define_insn_reservation "small_cpu_udiv_single" 5 -+ (and (eq_attr "tune" "small") -+ (and (eq_attr "v8type" "udiv") (eq_attr "mode" "SI"))) -+ "small_cpu_unit_i") -+ -+(define_insn_reservation "small_cpu_udiv_double" 10 -+ (and (eq_attr "tune" "small") -+ (and (eq_attr "v8type" "udiv") (eq_attr "mode" "DI"))) -+ "small_cpu_unit_i") -+ -+(define_insn_reservation "small_cpu_sdiv_single" 6 -+ (and (eq_attr "tune" "small") -+ (and (eq_attr "v8type" "sdiv") (eq_attr "mode" "SI"))) -+ "small_cpu_unit_i") -+ -+(define_insn_reservation "small_cpu_sdiv_double" 12 -+ (and (eq_attr "tune" "small") -+ (and (eq_attr "v8type" "sdiv") (eq_attr "mode" "DI"))) -+ "small_cpu_unit_i") -+ -+ -+;;------------------------------------------------------- -+;; Load/Store Instructions -+;;------------------------------------------------------- -+ -+(define_insn_reservation "small_cpu_load1" 2 -+ (and (eq_attr "tune" "small") -+ (eq_attr "v8type" "load_acq,load1")) -+ "small_cpu_unit_i") -+ -+(define_insn_reservation "small_cpu_store1" 0 -+ (and (eq_attr "tune" "small") -+ (eq_attr "v8type" "store_rel,store1")) -+ "small_cpu_unit_i") -+ -+(define_insn_reservation "small_cpu_load2" 3 -+ (and (eq_attr "tune" "small") -+ (eq_attr "v8type" "load2")) -+ "small_cpu_unit_i + small_cpu_unit_br, small_cpu_unit_i") -+ -+(define_insn_reservation "small_cpu_store2" 0 -+ (and (eq_attr "tune" "small") -+ (eq_attr "v8type" "store2")) -+ "small_cpu_unit_i + small_cpu_unit_br, small_cpu_unit_i") -+ -+ -+;;------------------------------------------------------- -+;; Branches -+;;------------------------------------------------------- -+ -+;; Direct branches are the only instructions that can dual-issue. -+;; The latency here represents when the branch actually takes place. -+ -+(define_insn_reservation "small_cpu_unit_br" 3 -+ (and (eq_attr "tune" "small") -+ (eq_attr "v8type" "branch,call")) -+ "small_cpu_unit_br") -+ -+ -+;;------------------------------------------------------- -+;; Floating-point arithmetic. -+;;------------------------------------------------------- -+ -+(define_insn_reservation "small_cpu_fpalu" 4 -+ (and (eq_attr "tune" "small") -+ (eq_attr "v8type" "ffarith,fadd,fccmp,fcvt,fcmp")) -+ "small_cpu_unit_i + small_cpu_unit_fpadd_pipe") -+ -+(define_insn_reservation "small_cpu_fconst" 3 -+ (and (eq_attr "tune" "small") -+ (eq_attr "v8type" "fconst")) -+ "small_cpu_unit_i + small_cpu_unit_fpadd_pipe") -+ -+(define_insn_reservation "small_cpu_fpmuls" 4 -+ (and (eq_attr "tune" "small") -+ (and (eq_attr "v8type" "fmul") (eq_attr "mode" "SF"))) -+ "small_cpu_unit_i + small_cpu_unit_fpmul_pipe") -+ -+(define_insn_reservation "small_cpu_fpmuld" 7 -+ (and (eq_attr "tune" "small") -+ (and (eq_attr "v8type" "fmul") (eq_attr "mode" "DF"))) -+ "small_cpu_unit_i + small_cpu_unit_fpmul_pipe, small_cpu_unit_fpmul_pipe * 2,\ -+ small_cpu_unit_i + small_cpu_unit_fpmul_pipe") -+ -+ -+;;------------------------------------------------------- -+;; Floating-point Division -+;;------------------------------------------------------- -+ -+;; Single-precision divide takes 14 cycles to complete, and this -+;; includes the time taken for the special instruction used to collect the -+;; result to travel down the multiply pipeline. -+ -+(define_insn_reservation "small_cpu_fdivs" 14 -+ (and (eq_attr "tune" "small") -+ (and (eq_attr "v8type" "fdiv,fsqrt") (eq_attr "mode" "SF"))) -+ "small_cpu_unit_i, small_cpu_unit_fpdiv * 13") -+ -+(define_insn_reservation "small_cpu_fdivd" 29 -+ (and (eq_attr "tune" "small") -+ (and (eq_attr "v8type" "fdiv,fsqrt") (eq_attr "mode" "DF"))) -+ "small_cpu_unit_i, small_cpu_unit_fpdiv * 28") -+ -+ -+;;------------------------------------------------------- -+;; Floating-point Transfers -+;;------------------------------------------------------- -+ -+(define_insn_reservation "small_cpu_i2f" 4 -+ (and (eq_attr "tune" "small") -+ (eq_attr "v8type" "fmovi2f")) -+ "small_cpu_unit_i") -+ -+(define_insn_reservation "small_cpu_f2i" 2 -+ (and (eq_attr "tune" "small") -+ (eq_attr "v8type" "fmovf2i")) -+ "small_cpu_unit_i") -+ -+ -+;;------------------------------------------------------- -+;; Floating-point Load/Store -+;;------------------------------------------------------- -+ -+(define_insn_reservation "small_cpu_floads" 4 -+ (and (eq_attr "tune" "small") -+ (and (eq_attr "v8type" "fpsimd_load") (eq_attr "mode" "SF"))) -+ "small_cpu_unit_i") -+ -+(define_insn_reservation "small_cpu_floadd" 5 -+ (and (eq_attr "tune" "small") -+ (and (eq_attr "v8type" "fpsimd_load") (eq_attr "mode" "DF"))) -+ "small_cpu_unit_i + small_cpu_unit_br, small_cpu_unit_i") -+ -+(define_insn_reservation "small_cpu_fstores" 0 -+ (and (eq_attr "tune" "small") -+ (and (eq_attr "v8type" "fpsimd_store") (eq_attr "mode" "SF"))) -+ "small_cpu_unit_i") -+ -+(define_insn_reservation "small_cpu_fstored" 0 -+ (and (eq_attr "tune" "small") -+ (and (eq_attr "v8type" "fpsimd_store") (eq_attr "mode" "DF"))) -+ "small_cpu_unit_i + small_cpu_unit_br, small_cpu_unit_i") -+ -+ -+;;------------------------------------------------------- -+;; Bypasses -+;;------------------------------------------------------- -+ -+;; Forwarding path for unshifted operands. -+ -+(define_bypass 1 "small_cpu_alu, small_cpu_alu_shift" -+ "small_cpu_alu, small_cpu_alu_shift, small_cpu_logic, small_cpu_logic_shift, small_cpu_shift") -+ -+(define_bypass 1 "small_cpu_logic, small_cpu_logic_shift" -+ "small_cpu_alu, small_cpu_alu_shift, small_cpu_logic, small_cpu_logic_shift, small_cpu_shift") -+ -+(define_bypass 1 "small_cpu_shift" -+ "small_cpu_alu, small_cpu_alu_shift, small_cpu_logic, small_cpu_logic_shift, small_cpu_shift") -+ -+;; Load-to-use for floating-point values has a penalty of one cycle. -+ -+(define_bypass 2 "small_cpu_floads" -+ "small_cpu_fpalu, small_cpu_fpmuld,\ -+ small_cpu_fdivs, small_cpu_fdivd,\ -+ small_cpu_f2i") -+ -+(define_bypass 3 "small_cpu_floadd" -+ "small_cpu_fpalu, small_cpu_fpmuld,\ -+ small_cpu_fdivs, small_cpu_fdivd,\ -+ small_cpu_f2i") -Index: gcc/config/aarch64/aarch64.c -=================================================================== ---- a/src/gcc/config/aarch64/aarch64.c (.../gcc-4_7-branch) -+++ b/src/gcc/config/aarch64/aarch64.c (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,6802 @@ -+/* Machine description for AArch64 architecture. -+ Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. -+ Contributed by ARM Ltd. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3, or (at your option) -+ any later version. -+ -+ GCC is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+#include "config.h" -+#include "system.h" -+#include "coretypes.h" -+#include "tm.h" -+#include "insn-codes.h" -+#include "rtl.h" -+#include "insn-attr.h" -+#include "tree.h" -+#include "regs.h" -+#include "df.h" -+#include "hard-reg-set.h" -+#include "output.h" -+#include "expr.h" -+#include "reload.h" -+#include "toplev.h" -+#include "target.h" -+#include "target-def.h" -+#include "targhooks.h" -+#include "ggc.h" -+#include "integrate.h" -+#include "tm_p.h" -+#include "recog.h" -+#include "langhooks.h" -+#include "diagnostic-core.h" -+#include "gimple.h" -+#include "optabs.h" -+#include "dwarf2.h" -+ -+/* Classifies an address. -+ -+ ADDRESS_REG_IMM -+ A simple base register plus immediate offset. -+ -+ ADDRESS_REG_WB -+ A base register indexed by immediate offset with writeback. -+ -+ ADDRESS_REG_REG -+ A base register indexed by (optionally scaled) register. -+ -+ ADDRESS_REG_UXTW -+ A base register indexed by (optionally scaled) zero-extended register. -+ -+ ADDRESS_REG_SXTW -+ A base register indexed by (optionally scaled) sign-extended register. -+ -+ ADDRESS_LO_SUM -+ A LO_SUM rtx with a base register and "LO12" symbol relocation. -+ -+ ADDRESS_SYMBOLIC: -+ A constant symbolic address, in pc-relative literal pool. */ -+ -+enum aarch64_address_type { -+ ADDRESS_REG_IMM, -+ ADDRESS_REG_WB, -+ ADDRESS_REG_REG, -+ ADDRESS_REG_UXTW, -+ ADDRESS_REG_SXTW, -+ ADDRESS_LO_SUM, -+ ADDRESS_SYMBOLIC -+}; -+ -+struct aarch64_address_info { -+ enum aarch64_address_type type; -+ rtx base; -+ rtx offset; -+ int shift; -+ enum aarch64_symbol_type symbol_type; -+}; -+ -+/* The current code model. */ -+enum aarch64_code_model aarch64_cmodel; -+ -+#ifdef HAVE_AS_TLS -+#undef TARGET_HAVE_TLS -+#define TARGET_HAVE_TLS 1 -+#endif -+ -+static bool aarch64_composite_type_p (const_tree, enum machine_mode); -+static bool aarch64_vfp_is_call_or_return_candidate (enum machine_mode, -+ const_tree, -+ enum machine_mode *, int *, -+ bool *); -+static void aarch64_elf_asm_constructor (rtx, int) ATTRIBUTE_UNUSED; -+static void aarch64_elf_asm_destructor (rtx, int) ATTRIBUTE_UNUSED; -+static rtx aarch64_load_tp (rtx); -+static void aarch64_override_options_after_change (void); -+static int aarch64_simd_valid_immediate (rtx, enum machine_mode, int, rtx *, -+ int *, unsigned char *, int *, int *); -+static bool aarch64_vector_mode_supported_p (enum machine_mode); -+static unsigned bit_count (unsigned HOST_WIDE_INT); -+static bool aarch64_const_vec_all_same_int_p (rtx, -+ HOST_WIDE_INT, HOST_WIDE_INT); -+ -+/* The processor for which instructions should be scheduled. */ -+enum aarch64_processor aarch64_tune = generic; -+ -+/* The current tuning set. */ -+const struct tune_params *aarch64_tune_params; -+ -+/* Mask to specify which instructions we are allowed to generate. */ -+unsigned long aarch64_isa_flags = 0; -+ -+/* Mask to specify which instruction scheduling options should be used. */ -+unsigned long aarch64_tune_flags = 0; -+ -+/* Tuning models. */ -+static const struct tune_params generic_tunings; -+ -+/* A processor implementing AArch64. */ -+struct processor -+{ -+ const char *const name; -+ enum aarch64_processor core; -+ const char *arch; -+ const unsigned long flags; -+ const struct tune_params *const tune; -+}; -+ -+/* Processor cores implementing AArch64. */ -+static const struct processor all_cores[] = -+{ -+#define AARCH64_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ -+ {NAME, IDENT, #ARCH, FLAGS | AARCH64_FL_FOR_ARCH##ARCH, &COSTS##_tunings}, -+#include "aarch64-cores.def" -+#undef AARCH64_CORE -+ {"generic", generic, "8", AARCH64_FL_FPSIMD | AARCH64_FL_FOR_ARCH8, &generic_tunings}, -+ {NULL, aarch64_none, NULL, 0, NULL} -+}; -+ -+/* Architectures implementing AArch64. */ -+static const struct processor all_architectures[] = -+{ -+#define AARCH64_ARCH(NAME, CORE, ARCH, FLAGS) \ -+ {NAME, CORE, #ARCH, FLAGS, NULL}, -+#include "aarch64-arches.def" -+#undef AARCH64_ARCH -+ {"generic", generic, "8", AARCH64_FL_FOR_ARCH8, NULL}, -+ {NULL, aarch64_none, NULL, 0, NULL} -+}; -+ -+/* Target specification. These are populated as commandline arguments -+ are processed, or NULL if not specified. */ -+static const struct processor *selected_arch; -+static const struct processor *selected_cpu; -+static const struct processor *selected_tune; -+ -+#define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0) -+ -+/* An ISA extension in the co-processor and main instruction set space. */ -+struct aarch64_option_extension -+{ -+ const char *const name; -+ const unsigned long flags_on; -+ const unsigned long flags_off; -+}; -+ -+/* ISA extensions in AArch64. */ -+static const struct aarch64_option_extension all_extensions[] = -+{ -+#define AARCH64_OPT_EXTENSION(NAME, FLAGS_ON, FLAGS_OFF) \ -+ {NAME, FLAGS_ON, FLAGS_OFF}, -+#include "aarch64-option-extensions.def" -+#undef AARCH64_OPT_EXTENSION -+ {NULL, 0, 0} -+}; -+ -+/* Used to track the size of an address when generating a pre/post -+ increment address. */ -+static enum machine_mode aarch64_memory_reference_mode; -+ -+/* Used to force GTY into this file. */ -+static GTY(()) int gty_dummy; -+ -+/* A table of valid AArch64 "bitmask immediate" values for -+ logical instructions. */ -+ -+#define AARCH64_NUM_BITMASKS 5334 -+static unsigned HOST_WIDE_INT aarch64_bitmasks[AARCH64_NUM_BITMASKS]; -+ -+/* Did we set flag_omit_frame_pointer just so -+ aarch64_frame_pointer_required would be called? */ -+static bool faked_omit_frame_pointer; -+ -+typedef enum aarch64_cond_code -+{ -+ AARCH64_EQ = 0, AARCH64_NE, AARCH64_CS, AARCH64_CC, AARCH64_MI, AARCH64_PL, -+ AARCH64_VS, AARCH64_VC, AARCH64_HI, AARCH64_LS, AARCH64_GE, AARCH64_LT, -+ AARCH64_GT, AARCH64_LE, AARCH64_AL, AARCH64_NV -+} -+aarch64_cc; -+ -+#define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1)) -+ -+/* The condition codes of the processor, and the inverse function. */ -+static const char * const aarch64_condition_codes[] = -+{ -+ "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", -+ "hi", "ls", "ge", "lt", "gt", "le", "al", "nv" -+}; -+ -+/* Provide a mapping from gcc register numbers to dwarf register numbers. */ -+unsigned -+aarch64_dbx_register_number (unsigned regno) -+{ -+ if (GP_REGNUM_P (regno)) -+ return AARCH64_DWARF_R0 + regno - R0_REGNUM; -+ else if (regno == SP_REGNUM) -+ return AARCH64_DWARF_SP; -+ else if (FP_REGNUM_P (regno)) -+ return AARCH64_DWARF_V0 + regno - V0_REGNUM; -+ -+ /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no -+ equivalent DWARF register. */ -+ return DWARF_FRAME_REGISTERS; -+} -+ -+/* Implement HARD_REGNO_NREGS. */ -+ -+int -+aarch64_hard_regno_nregs (unsigned regno, enum machine_mode mode) -+{ -+ switch (aarch64_regno_regclass (regno)) -+ { -+ case FP_REGS: -+ case FP_LO_REGS: -+ return (GET_MODE_SIZE (mode) + UNITS_PER_VREG - 1) / UNITS_PER_VREG; -+ default: -+ return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; -+ } -+ gcc_unreachable (); -+} -+ -+/* Implement HARD_REGNO_MODE_OK. */ -+ -+int -+aarch64_hard_regno_mode_ok (unsigned regno, enum machine_mode mode) -+{ -+ if (GET_MODE_CLASS (mode) == MODE_CC) -+ return regno == CC_REGNUM; -+ -+ if (regno == SP_REGNUM || regno == FRAME_POINTER_REGNUM -+ || regno == ARG_POINTER_REGNUM) -+ return mode == Pmode; -+ -+ if (GP_REGNUM_P (regno)) -+ return 1; -+ -+ if (FP_REGNUM_P (regno)) -+ return 1; -+ -+ return 0; -+} -+ -+/* Return true if calls to DECL should be treated as -+ long-calls (ie called via a register). */ -+static bool -+aarch64_decl_is_long_call_p (const_tree decl ATTRIBUTE_UNUSED) -+{ -+ return false; -+} -+ -+/* Return true if calls to symbol-ref SYM should be treated as -+ long-calls (ie called via a register). */ -+bool -+aarch64_is_long_call_p (rtx sym) -+{ -+ return aarch64_decl_is_long_call_p (SYMBOL_REF_DECL (sym)); -+} -+ -+/* Return true if the offsets to a zero/sign-extract operation -+ represent an expression that matches an extend operation. The -+ operands represent the paramters from -+ -+ (extract (mult (reg) (mult_imm)) (extract_imm) (const_int 0)). */ -+bool -+aarch64_is_extend_from_extract (enum machine_mode mode, rtx mult_imm, -+ rtx extract_imm) -+{ -+ HOST_WIDE_INT mult_val, extract_val; -+ -+ if (! CONST_INT_P (mult_imm) || ! CONST_INT_P (extract_imm)) -+ return false; -+ -+ mult_val = INTVAL (mult_imm); -+ extract_val = INTVAL (extract_imm); -+ -+ if (extract_val > 8 -+ && extract_val < GET_MODE_BITSIZE (mode) -+ && exact_log2 (extract_val & ~7) > 0 -+ && (extract_val & 7) <= 4 -+ && mult_val == (1 << (extract_val & 7))) -+ return true; -+ -+ return false; -+} -+ -+/* Emit an insn that's a simple single-set. Both the operands must be -+ known to be valid. */ -+inline static rtx -+emit_set_insn (rtx x, rtx y) -+{ -+ return emit_insn (gen_rtx_SET (VOIDmode, x, y)); -+} -+ -+/* X and Y are two things to compare using CODE. Emit the compare insn and -+ return the rtx for register 0 in the proper mode. */ -+rtx -+aarch64_gen_compare_reg (RTX_CODE code, rtx x, rtx y) -+{ -+ enum machine_mode mode = SELECT_CC_MODE (code, x, y); -+ rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM); -+ -+ emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y)); -+ return cc_reg; -+} -+ -+/* Build the SYMBOL_REF for __tls_get_addr. */ -+ -+static GTY(()) rtx tls_get_addr_libfunc; -+ -+rtx -+aarch64_tls_get_addr (void) -+{ -+ if (!tls_get_addr_libfunc) -+ tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr"); -+ return tls_get_addr_libfunc; -+} -+ -+/* Return the TLS model to use for ADDR. */ -+ -+static enum tls_model -+tls_symbolic_operand_type (rtx addr) -+{ -+ enum tls_model tls_kind = TLS_MODEL_NONE; -+ rtx sym, addend; -+ -+ if (GET_CODE (addr) == CONST) -+ { -+ split_const (addr, &sym, &addend); -+ if (GET_CODE (sym) == SYMBOL_REF) -+ tls_kind = SYMBOL_REF_TLS_MODEL (sym); -+ } -+ else if (GET_CODE (addr) == SYMBOL_REF) -+ tls_kind = SYMBOL_REF_TLS_MODEL (addr); -+ -+ return tls_kind; -+} -+ -+/* We'll allow lo_sum's in addresses in our legitimate addresses -+ so that combine would take care of combining addresses where -+ necessary, but for generation purposes, we'll generate the address -+ as : -+ RTL Absolute -+ tmp = hi (symbol_ref); adrp x1, foo -+ dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo -+ nop -+ -+ PIC TLS -+ adrp x1, :got:foo adrp tmp, :tlsgd:foo -+ ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo -+ bl __tls_get_addr -+ nop -+ -+ Load TLS symbol, depending on TLS mechanism and TLS access model. -+ -+ Global Dynamic - Traditional TLS: -+ adrp tmp, :tlsgd:imm -+ add dest, tmp, #:tlsgd_lo12:imm -+ bl __tls_get_addr -+ -+ Global Dynamic - TLS Descriptors: -+ adrp dest, :tlsdesc:imm -+ ldr tmp, [dest, #:tlsdesc_lo12:imm] -+ add dest, dest, #:tlsdesc_lo12:imm -+ blr tmp -+ mrs tp, tpidr_el0 -+ add dest, dest, tp -+ -+ Initial Exec: -+ mrs tp, tpidr_el0 -+ adrp tmp, :gottprel:imm -+ ldr dest, [tmp, #:gottprel_lo12:imm] -+ add dest, dest, tp -+ -+ Local Exec: -+ mrs tp, tpidr_el0 -+ add t0, tp, #:tprel_hi12:imm -+ add t0, #:tprel_lo12_nc:imm -+*/ -+ -+static void -+aarch64_load_symref_appropriately (rtx dest, rtx imm, -+ enum aarch64_symbol_type type) -+{ -+ switch (type) -+ { -+ case SYMBOL_SMALL_ABSOLUTE: -+ { -+ rtx tmp_reg = dest; -+ if (can_create_pseudo_p ()) -+ { -+ tmp_reg = gen_reg_rtx (Pmode); -+ } -+ -+ emit_move_insn (tmp_reg, gen_rtx_HIGH (Pmode, imm)); -+ emit_insn (gen_add_losym (dest, tmp_reg, imm)); -+ return; -+ } -+ -+ case SYMBOL_SMALL_GOT: -+ { -+ rtx tmp_reg = dest; -+ if (can_create_pseudo_p ()) -+ { -+ tmp_reg = gen_reg_rtx (Pmode); -+ } -+ emit_move_insn (tmp_reg, gen_rtx_HIGH (Pmode, imm)); -+ emit_insn (gen_ldr_got_small (dest, tmp_reg, imm)); -+ return; -+ } -+ -+ case SYMBOL_SMALL_TLSGD: -+ { -+ rtx insns; -+ rtx result = gen_rtx_REG (Pmode, R0_REGNUM); -+ -+ start_sequence (); -+ emit_call_insn (gen_tlsgd_small (result, imm)); -+ insns = get_insns (); -+ end_sequence (); -+ -+ RTL_CONST_CALL_P (insns) = 1; -+ emit_libcall_block (insns, dest, result, imm); -+ return; -+ } -+ -+ case SYMBOL_SMALL_TLSDESC: -+ { -+ rtx x0 = gen_rtx_REG (Pmode, R0_REGNUM); -+ rtx tp; -+ -+ emit_insn (gen_tlsdesc_small (imm)); -+ tp = aarch64_load_tp (NULL); -+ emit_insn (gen_rtx_SET (Pmode, dest, gen_rtx_PLUS (Pmode, tp, x0))); -+ set_unique_reg_note (get_last_insn (), REG_EQUIV, imm); -+ return; -+ } -+ -+ case SYMBOL_SMALL_GOTTPREL: -+ { -+ rtx tmp_reg = gen_reg_rtx (Pmode); -+ rtx tp = aarch64_load_tp (NULL); -+ emit_insn (gen_tlsie_small (tmp_reg, imm)); -+ emit_insn (gen_rtx_SET (Pmode, dest, gen_rtx_PLUS (Pmode, tp, tmp_reg))); -+ set_unique_reg_note (get_last_insn (), REG_EQUIV, imm); -+ return; -+ } -+ -+ case SYMBOL_SMALL_TPREL: -+ { -+ rtx tp = aarch64_load_tp (NULL); -+ emit_insn (gen_tlsle_small (dest, tp, imm)); -+ set_unique_reg_note (get_last_insn (), REG_EQUIV, imm); -+ return; -+ } -+ -+ default: -+ gcc_unreachable (); -+ } -+} -+ -+/* Emit a move from SRC to DEST. Assume that the move expanders can -+ handle all moves if !can_create_pseudo_p (). The distinction is -+ important because, unlike emit_move_insn, the move expanders know -+ how to force Pmode objects into the constant pool even when the -+ constant pool address is not itself legitimate. */ -+static rtx -+aarch64_emit_move (rtx dest, rtx src) -+{ -+ return (can_create_pseudo_p () -+ ? emit_move_insn (dest, src) -+ : emit_move_insn_1 (dest, src)); -+} -+ -+void -+aarch64_split_doubleword_move (rtx dst, rtx src) -+{ -+ rtx low_dst; -+ -+ gcc_assert (GET_MODE (dst) == TImode); -+ -+ if (REG_P (dst) && REG_P (src)) -+ { -+ int src_regno = REGNO (src); -+ int dst_regno = REGNO (dst); -+ -+ gcc_assert (GET_MODE (src) == TImode); -+ -+ /* Handle r -> w, w -> r. */ -+ if (FP_REGNUM_P (dst_regno) && GP_REGNUM_P (src_regno)) -+ { -+ emit_insn (gen_aarch64_movtilow_di (dst, -+ gen_lowpart (word_mode, src))); -+ emit_insn (gen_aarch64_movtihigh_di (dst, -+ gen_highpart (word_mode, src))); -+ return; -+ } -+ else if (GP_REGNUM_P (dst_regno) && FP_REGNUM_P (src_regno)) -+ { -+ emit_insn (gen_aarch64_movdi_tilow (gen_lowpart (word_mode, dst), -+ src)); -+ emit_insn (gen_aarch64_movdi_tihigh (gen_highpart (word_mode, dst), -+ src)); -+ return; -+ } -+ /* Fall through to r -> r cases. */ -+ } -+ -+ low_dst = gen_lowpart (word_mode, dst); -+ if (REG_P (low_dst) -+ && reg_overlap_mentioned_p (low_dst, src)) -+ { -+ aarch64_emit_move (gen_highpart (word_mode, dst), -+ gen_highpart_mode (word_mode, TImode, src)); -+ aarch64_emit_move (low_dst, gen_lowpart (word_mode, src)); -+ } -+ else -+ { -+ aarch64_emit_move (low_dst, gen_lowpart (word_mode, src)); -+ aarch64_emit_move (gen_highpart (word_mode, dst), -+ gen_highpart_mode (word_mode, TImode, src)); -+ } -+} -+ -+static rtx -+aarch64_force_temporary (rtx x, rtx value) -+{ -+ if (can_create_pseudo_p ()) -+ return force_reg (Pmode, value); -+ else -+ { -+ x = aarch64_emit_move (x, value); -+ return x; -+ } -+} -+ -+ -+static rtx -+aarch64_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset) -+{ -+ if (!aarch64_plus_immediate (GEN_INT (offset), DImode)) -+ { -+ rtx high; -+ /* Load the full offset into a register. This -+ might be improvable in the future. */ -+ high = GEN_INT (offset); -+ offset = 0; -+ high = aarch64_force_temporary (temp, high); -+ reg = aarch64_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg)); -+ } -+ return plus_constant (reg, offset); -+} -+ -+void -+aarch64_expand_mov_immediate (rtx dest, rtx imm) -+{ -+ enum machine_mode mode = GET_MODE (dest); -+ unsigned HOST_WIDE_INT mask; -+ int i; -+ bool first; -+ unsigned HOST_WIDE_INT val; -+ bool subtargets; -+ rtx subtarget; -+ rtx base, offset; -+ int one_match, zero_match; -+ -+ gcc_assert (mode == SImode || mode == DImode); -+ -+ /* If we have (const (plus symbol offset)), and that expression cannot -+ be forced into memory, load the symbol first and add in the offset. */ -+ split_const (imm, &base, &offset); -+ if (offset != const0_rtx -+ && (targetm.cannot_force_const_mem (mode, imm) -+ || (can_create_pseudo_p ()))) -+ { -+ base = aarch64_force_temporary (dest, base); -+ aarch64_emit_move (dest, aarch64_add_offset (NULL, base, INTVAL (offset))); -+ return; -+ } -+ -+ /* Check on what type of symbol it is. */ -+ if (GET_CODE (base) == SYMBOL_REF || GET_CODE (base) == LABEL_REF) -+ { -+ rtx mem; -+ switch (aarch64_classify_symbol (base, SYMBOL_CONTEXT_ADR)) -+ { -+ case SYMBOL_FORCE_TO_MEM: -+ mem = force_const_mem (mode, imm); -+ gcc_assert (mem); -+ emit_insn (gen_rtx_SET (VOIDmode, dest, mem)); -+ return; -+ -+ case SYMBOL_SMALL_TLSGD: -+ case SYMBOL_SMALL_TLSDESC: -+ case SYMBOL_SMALL_GOTTPREL: -+ case SYMBOL_SMALL_TPREL: -+ case SYMBOL_SMALL_GOT: -+ case SYMBOL_SMALL_ABSOLUTE: -+ aarch64_load_symref_appropriately -+ (dest, imm, aarch64_classify_symbol (base, SYMBOL_CONTEXT_ADR)); -+ return; -+ -+ default: -+ gcc_unreachable (); -+ } -+ } -+ -+ if ((CONST_INT_P (imm) && aarch64_move_imm (INTVAL (imm), mode))) -+ { -+ emit_insn (gen_rtx_SET (VOIDmode, dest, imm)); -+ return; -+ } -+ -+ if (!CONST_INT_P (imm)) -+ { -+ if (GET_CODE (imm) == HIGH) -+ emit_insn (gen_rtx_SET (VOIDmode, dest, imm)); -+ else -+ { -+ rtx mem = force_const_mem (mode, imm); -+ gcc_assert (mem); -+ emit_insn (gen_rtx_SET (VOIDmode, dest, mem)); -+ } -+ -+ return; -+ } -+ -+ if (mode == SImode) -+ { -+ /* We know we can't do this in 1 insn, and we must be able to do it -+ in two; so don't mess around looking for sequences that don't buy -+ us anything. */ -+ emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_INT (INTVAL (imm) & 0xffff))); -+ emit_insn (gen_insv_immsi (dest, GEN_INT (16), -+ GEN_INT ((INTVAL (imm) >> 16) & 0xffff))); -+ return; -+ } -+ -+ /* Remaining cases are all for DImode. */ -+ -+ val = INTVAL (imm); -+ subtargets = optimize && can_create_pseudo_p (); -+ -+ one_match = 0; -+ zero_match = 0; -+ mask = 0xffff; -+ -+ for (i = 0; i < 64; i += 16, mask <<= 16) -+ { -+ if ((val & mask) == 0) -+ zero_match++; -+ else if ((val & mask) == mask) -+ one_match++; -+ } -+ -+ if (one_match == 2) -+ { -+ mask = 0xffff; -+ for (i = 0; i < 64; i += 16, mask <<= 16) -+ { -+ if ((val & mask) != mask) -+ { -+ emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_INT (val | mask))); -+ emit_insn (gen_insv_immdi (dest, GEN_INT (i), -+ GEN_INT ((val >> i) & 0xffff))); -+ return; -+ } -+ } -+ gcc_unreachable (); -+ } -+ -+ if (zero_match == 2) -+ goto simple_sequence; -+ -+ mask = 0x0ffff0000UL; -+ for (i = 16; i < 64; i += 16, mask <<= 16) -+ { -+ HOST_WIDE_INT comp = mask & ~(mask - 1); -+ -+ if (aarch64_uimm12_shift (val - (val & mask))) -+ { -+ subtarget = subtargets ? gen_reg_rtx (DImode) : dest; -+ -+ emit_insn (gen_rtx_SET (VOIDmode, subtarget, GEN_INT (val & mask))); -+ emit_insn (gen_adddi3 (dest, subtarget, -+ GEN_INT (val - (val & mask)))); -+ return; -+ } -+ else if (aarch64_uimm12_shift (-(val - ((val + comp) & mask)))) -+ { -+ subtarget = subtargets ? gen_reg_rtx (DImode) : dest; -+ -+ emit_insn (gen_rtx_SET (VOIDmode, subtarget, -+ GEN_INT ((val + comp) & mask))); -+ emit_insn (gen_adddi3 (dest, subtarget, -+ GEN_INT (val - ((val + comp) & mask)))); -+ return; -+ } -+ else if (aarch64_uimm12_shift (val - ((val - comp) | ~mask))) -+ { -+ subtarget = subtargets ? gen_reg_rtx (DImode) : dest; -+ -+ emit_insn (gen_rtx_SET (VOIDmode, subtarget, -+ GEN_INT ((val - comp) | ~mask))); -+ emit_insn (gen_adddi3 (dest, subtarget, -+ GEN_INT (val - ((val - comp) | ~mask)))); -+ return; -+ } -+ else if (aarch64_uimm12_shift (-(val - (val | ~mask)))) -+ { -+ subtarget = subtargets ? gen_reg_rtx (DImode) : dest; -+ -+ emit_insn (gen_rtx_SET (VOIDmode, subtarget, -+ GEN_INT (val | ~mask))); -+ emit_insn (gen_adddi3 (dest, subtarget, -+ GEN_INT (val - (val | ~mask)))); -+ return; -+ } -+ } -+ -+ /* See if we can do it by arithmetically combining two -+ immediates. */ -+ for (i = 0; i < AARCH64_NUM_BITMASKS; i++) -+ { -+ int j; -+ mask = 0xffff; -+ -+ if (aarch64_uimm12_shift (val - aarch64_bitmasks[i]) -+ || aarch64_uimm12_shift (-val + aarch64_bitmasks[i])) -+ { -+ subtarget = subtargets ? gen_reg_rtx (DImode) : dest; -+ emit_insn (gen_rtx_SET (VOIDmode, subtarget, -+ GEN_INT (aarch64_bitmasks[i]))); -+ emit_insn (gen_adddi3 (dest, subtarget, -+ GEN_INT (val - aarch64_bitmasks[i]))); -+ return; -+ } -+ -+ for (j = 0; j < 64; j += 16, mask <<= 16) -+ { -+ if ((aarch64_bitmasks[i] & ~mask) == (val & ~mask)) -+ { -+ emit_insn (gen_rtx_SET (VOIDmode, dest, -+ GEN_INT (aarch64_bitmasks[i]))); -+ emit_insn (gen_insv_immdi (dest, GEN_INT (j), -+ GEN_INT ((val >> j) & 0xffff))); -+ return; -+ } -+ } -+ } -+ -+ /* See if we can do it by logically combining two immediates. */ -+ for (i = 0; i < AARCH64_NUM_BITMASKS; i++) -+ { -+ if ((aarch64_bitmasks[i] & val) == aarch64_bitmasks[i]) -+ { -+ int j; -+ -+ for (j = i + 1; j < AARCH64_NUM_BITMASKS; j++) -+ if (val == (aarch64_bitmasks[i] | aarch64_bitmasks[j])) -+ { -+ subtarget = subtargets ? gen_reg_rtx (mode) : dest; -+ emit_insn (gen_rtx_SET (VOIDmode, subtarget, -+ GEN_INT (aarch64_bitmasks[i]))); -+ emit_insn (gen_iordi3 (dest, subtarget, -+ GEN_INT (aarch64_bitmasks[j]))); -+ return; -+ } -+ } -+ else if ((val & aarch64_bitmasks[i]) == val) -+ { -+ int j; -+ -+ for (j = i + 1; j < AARCH64_NUM_BITMASKS; j++) -+ if (val == (aarch64_bitmasks[j] & aarch64_bitmasks[i])) -+ { -+ -+ subtarget = subtargets ? gen_reg_rtx (mode) : dest; -+ emit_insn (gen_rtx_SET (VOIDmode, subtarget, -+ GEN_INT (aarch64_bitmasks[j]))); -+ emit_insn (gen_anddi3 (dest, subtarget, -+ GEN_INT (aarch64_bitmasks[i]))); -+ return; -+ } -+ } -+ } -+ -+ simple_sequence: -+ first = true; -+ mask = 0xffff; -+ for (i = 0; i < 64; i += 16, mask <<= 16) -+ { -+ if ((val & mask) != 0) -+ { -+ if (first) -+ { -+ emit_insn (gen_rtx_SET (VOIDmode, dest, -+ GEN_INT (val & mask))); -+ first = false; -+ } -+ else -+ emit_insn (gen_insv_immdi (dest, GEN_INT (i), -+ GEN_INT ((val >> i) & 0xffff))); -+ } -+ } -+} -+ -+static bool -+aarch64_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) -+{ -+ /* Indirect calls are not currently supported. */ -+ if (decl == NULL) -+ return false; -+ -+ /* Cannot tail-call to long-calls, since these are outside of the -+ range of a branch instruction (we could handle this if we added -+ support for indirect tail-calls. */ -+ if (aarch64_decl_is_long_call_p (decl)) -+ return false; -+ -+ return true; -+} -+ -+/* Implement TARGET_PASS_BY_REFERENCE. */ -+ -+static bool -+aarch64_pass_by_reference (cumulative_args_t pcum ATTRIBUTE_UNUSED, -+ enum machine_mode mode, -+ const_tree type, -+ bool named ATTRIBUTE_UNUSED) -+{ -+ HOST_WIDE_INT size; -+ enum machine_mode dummymode; -+ int nregs; -+ -+ /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */ -+ size = (mode == BLKmode && type) -+ ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode); -+ -+ if (type) -+ { -+ /* Arrays always passed by reference. */ -+ if (TREE_CODE (type) == ARRAY_TYPE) -+ return true; -+ /* Other aggregates based on their size. */ -+ if (AGGREGATE_TYPE_P (type)) -+ size = int_size_in_bytes (type); -+ } -+ -+ /* Variable sized arguments are always returned by reference. */ -+ if (size < 0) -+ return true; -+ -+ /* Can this be a candidate to be passed in fp/simd register(s)? */ -+ if (aarch64_vfp_is_call_or_return_candidate (mode, type, -+ &dummymode, &nregs, -+ NULL)) -+ return false; -+ -+ /* Arguments which are variable sized or larger than 2 registers are -+ passed by reference unless they are a homogenous floating point -+ aggregate. */ -+ return size > 2 * UNITS_PER_WORD; -+} -+ -+/* Return TRUE if VALTYPE is padded to its least significant bits. */ -+static bool -+aarch64_return_in_msb (const_tree valtype) -+{ -+ enum machine_mode dummy_mode; -+ int dummy_int; -+ -+ /* Never happens in little-endian mode. */ -+ if (!BYTES_BIG_ENDIAN) -+ return false; -+ -+ /* Only composite types smaller than or equal to 16 bytes can -+ be potentially returned in registers. */ -+ if (!aarch64_composite_type_p (valtype, TYPE_MODE (valtype)) -+ || int_size_in_bytes (valtype) <= 0 -+ || int_size_in_bytes (valtype) > 16) -+ return false; -+ -+ /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate) -+ or an HVA (Homogeneous Short-Vector Aggregate); such a special composite -+ is always passed/returned in the least significant bits of fp/simd -+ register(s). */ -+ if (aarch64_vfp_is_call_or_return_candidate (TYPE_MODE (valtype), valtype, -+ &dummy_mode, &dummy_int, NULL)) -+ return false; -+ -+ return true; -+} -+ -+/* Implement TARGET_FUNCTION_VALUE. -+ Define how to find the value returned by a function. */ -+ -+static rtx -+aarch64_function_value (const_tree type, const_tree func, -+ bool outgoing ATTRIBUTE_UNUSED) -+{ -+ enum machine_mode mode; -+ int unsignedp; -+ int count; -+ enum machine_mode ag_mode; -+ -+ mode = TYPE_MODE (type); -+ if (INTEGRAL_TYPE_P (type)) -+ mode = promote_function_mode (type, mode, &unsignedp, func, 1); -+ -+ if (aarch64_return_in_msb (type)) -+ { -+ HOST_WIDE_INT size = int_size_in_bytes (type); -+ -+ if (size % UNITS_PER_WORD != 0) -+ { -+ size += UNITS_PER_WORD - size % UNITS_PER_WORD; -+ mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0); -+ } -+ } -+ -+ if (aarch64_vfp_is_call_or_return_candidate (mode, type, -+ &ag_mode, &count, NULL)) -+ { -+ if (!aarch64_composite_type_p (type, mode)) -+ { -+ gcc_assert (count == 1 && mode == ag_mode); -+ return gen_rtx_REG (mode, V0_REGNUM); -+ } -+ else -+ { -+ int i; -+ rtx par; -+ -+ par = gen_rtx_PARALLEL (mode, rtvec_alloc (count)); -+ for (i = 0; i < count; i++) -+ { -+ rtx tmp = gen_rtx_REG (ag_mode, V0_REGNUM + i); -+ tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, -+ GEN_INT (i * GET_MODE_SIZE (ag_mode))); -+ XVECEXP (par, 0, i) = tmp; -+ } -+ return par; -+ } -+ } -+ else -+ return gen_rtx_REG (mode, R0_REGNUM); -+} -+ -+/* Implements TARGET_FUNCTION_VALUE_REGNO_P. -+ Return true if REGNO is the number of a hard register in which the values -+ of called function may come back. */ -+ -+static bool -+aarch64_function_value_regno_p (const unsigned int regno) -+{ -+ /* Maximum of 16 bytes can be returned in the general registers. Examples -+ of 16-byte return values are: 128-bit integers and 16-byte small -+ structures (excluding homogeneous floating-point aggregates). */ -+ if (regno == R0_REGNUM || regno == R1_REGNUM) -+ return true; -+ -+ /* Up to four fp/simd registers can return a function value, e.g. a -+ homogeneous floating-point aggregate having four members. */ -+ if (regno >= V0_REGNUM && regno < V0_REGNUM + HA_MAX_NUM_FLDS) -+ return !TARGET_GENERAL_REGS_ONLY; -+ -+ return false; -+} -+ -+/* Implement TARGET_RETURN_IN_MEMORY. -+ -+ If the type T of the result of a function is such that -+ void func (T arg) -+ would require that arg be passed as a value in a register (or set of -+ registers) according to the parameter passing rules, then the result -+ is returned in the same registers as would be used for such an -+ argument. */ -+ -+static bool -+aarch64_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED) -+{ -+ HOST_WIDE_INT size; -+ enum machine_mode ag_mode; -+ int count; -+ -+ if (!AGGREGATE_TYPE_P (type) -+ && TREE_CODE (type) != COMPLEX_TYPE -+ && TREE_CODE (type) != VECTOR_TYPE) -+ /* Simple scalar types always returned in registers. */ -+ return false; -+ -+ if (aarch64_vfp_is_call_or_return_candidate (TYPE_MODE (type), -+ type, -+ &ag_mode, -+ &count, -+ NULL)) -+ return false; -+ -+ /* Types larger than 2 registers returned in memory. */ -+ size = int_size_in_bytes (type); -+ return (size < 0 || size > 2 * UNITS_PER_WORD); -+} -+ -+static bool -+aarch64_vfp_is_call_candidate (cumulative_args_t pcum_v, enum machine_mode mode, -+ const_tree type, int *nregs) -+{ -+ CUMULATIVE_ARGS *pcum = get_cumulative_args (pcum_v); -+ return aarch64_vfp_is_call_or_return_candidate (mode, -+ type, -+ &pcum->aapcs_vfp_rmode, -+ nregs, -+ NULL); -+} -+ -+/* Given MODE and TYPE of a function argument, return the alignment in -+ bits. The idea is to suppress any stronger alignment requested by -+ the user and opt for the natural alignment (specified in AAPCS64 \S 4.1). -+ This is a helper function for local use only. */ -+ -+static unsigned int -+aarch64_function_arg_alignment (enum machine_mode mode, const_tree type) -+{ -+ unsigned int alignment; -+ -+ if (type) -+ { -+ if (!integer_zerop (TYPE_SIZE (type))) -+ { -+ if (TYPE_MODE (type) == mode) -+ alignment = TYPE_ALIGN (type); -+ else -+ alignment = GET_MODE_ALIGNMENT (mode); -+ } -+ else -+ alignment = 0; -+ } -+ else -+ alignment = GET_MODE_ALIGNMENT (mode); -+ -+ return alignment; -+} -+ -+/* Layout a function argument according to the AAPCS64 rules. The rule -+ numbers refer to the rule numbers in the AAPCS64. */ -+ -+static void -+aarch64_layout_arg (cumulative_args_t pcum_v, enum machine_mode mode, -+ const_tree type, -+ bool named ATTRIBUTE_UNUSED) -+{ -+ CUMULATIVE_ARGS *pcum = get_cumulative_args (pcum_v); -+ int ncrn, nvrn, nregs; -+ bool allocate_ncrn, allocate_nvrn; -+ -+ /* We need to do this once per argument. */ -+ if (pcum->aapcs_arg_processed) -+ return; -+ -+ pcum->aapcs_arg_processed = true; -+ -+ allocate_ncrn = (type) ? !(FLOAT_TYPE_P (type)) : !FLOAT_MODE_P (mode); -+ allocate_nvrn = aarch64_vfp_is_call_candidate (pcum_v, -+ mode, -+ type, -+ &nregs); -+ -+ /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable. -+ The following code thus handles passing by SIMD/FP registers first. */ -+ -+ nvrn = pcum->aapcs_nvrn; -+ -+ /* C1 - C5 for floating point, homogenous floating point aggregates (HFA) -+ and homogenous short-vector aggregates (HVA). */ -+ if (allocate_nvrn) -+ { -+ if (nvrn + nregs <= NUM_FP_ARG_REGS) -+ { -+ pcum->aapcs_nextnvrn = nvrn + nregs; -+ if (!aarch64_composite_type_p (type, mode)) -+ { -+ gcc_assert (nregs == 1); -+ pcum->aapcs_reg = gen_rtx_REG (mode, V0_REGNUM + nvrn); -+ } -+ else -+ { -+ rtx par; -+ int i; -+ par = gen_rtx_PARALLEL (mode, rtvec_alloc (nregs)); -+ for (i = 0; i < nregs; i++) -+ { -+ rtx tmp = gen_rtx_REG (pcum->aapcs_vfp_rmode, -+ V0_REGNUM + nvrn + i); -+ tmp = gen_rtx_EXPR_LIST -+ (VOIDmode, tmp, -+ GEN_INT (i * GET_MODE_SIZE (pcum->aapcs_vfp_rmode))); -+ XVECEXP (par, 0, i) = tmp; -+ } -+ pcum->aapcs_reg = par; -+ } -+ return; -+ } -+ else -+ { -+ /* C.3 NSRN is set to 8. */ -+ pcum->aapcs_nextnvrn = NUM_FP_ARG_REGS; -+ goto on_stack; -+ } -+ } -+ -+ ncrn = pcum->aapcs_ncrn; -+ nregs = ((type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode)) -+ + UNITS_PER_WORD - 1) / UNITS_PER_WORD; -+ -+ -+ /* C6 - C9. though the sign and zero extension semantics are -+ handled elsewhere. This is the case where the argument fits -+ entirely general registers. */ -+ if (allocate_ncrn && (ncrn + nregs <= NUM_ARG_REGS)) -+ { -+ unsigned int alignment = aarch64_function_arg_alignment (mode, type); -+ -+ gcc_assert (nregs == 0 || nregs == 1 || nregs == 2); -+ -+ /* C.8 if the argument has an alignment of 16 then the NGRN is -+ rounded up to the next even number. */ -+ if (nregs == 2 && alignment == 16 * BITS_PER_UNIT && ncrn % 2) -+ { -+ ++ncrn; -+ gcc_assert (ncrn + nregs <= NUM_ARG_REGS); -+ } -+ /* NREGS can be 0 when e.g. an empty structure is to be passed. -+ A reg is still generated for it, but the caller should be smart -+ enough not to use it. */ -+ if (nregs == 0 || nregs == 1 || GET_MODE_CLASS (mode) == MODE_INT) -+ { -+ pcum->aapcs_reg = gen_rtx_REG (mode, R0_REGNUM + ncrn); -+ } -+ else -+ { -+ rtx par; -+ int i; -+ -+ par = gen_rtx_PARALLEL (mode, rtvec_alloc (nregs)); -+ for (i = 0; i < nregs; i++) -+ { -+ rtx tmp = gen_rtx_REG (word_mode, R0_REGNUM + ncrn + i); -+ tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, -+ GEN_INT (i * UNITS_PER_WORD)); -+ XVECEXP (par, 0, i) = tmp; -+ } -+ pcum->aapcs_reg = par; -+ } -+ -+ pcum->aapcs_nextncrn = ncrn + nregs; -+ return; -+ } -+ -+ /* C.11 */ -+ pcum->aapcs_nextncrn = NUM_ARG_REGS; -+ -+ /* The argument is passed on stack; record the needed number of words for -+ this argument (we can re-use NREGS) and align the total size if -+ necessary. */ -+on_stack: -+ pcum->aapcs_stack_words = nregs; -+ if (aarch64_function_arg_alignment (mode, type) == 16 * BITS_PER_UNIT) -+ pcum->aapcs_stack_size = AARCH64_ROUND_UP (pcum->aapcs_stack_size, -+ 16 / UNITS_PER_WORD) + 1; -+ return; -+} -+ -+/* Implement TARGET_FUNCTION_ARG. */ -+ -+static rtx -+aarch64_function_arg (cumulative_args_t pcum_v, enum machine_mode mode, -+ const_tree type, bool named) -+{ -+ CUMULATIVE_ARGS *pcum = get_cumulative_args (pcum_v); -+ gcc_assert (pcum->pcs_variant == ARM_PCS_AAPCS64); -+ -+ if (mode == VOIDmode) -+ return NULL_RTX; -+ -+ aarch64_layout_arg (pcum_v, mode, type, named); -+ return pcum->aapcs_reg; -+} -+ -+void -+aarch64_init_cumulative_args (CUMULATIVE_ARGS *pcum, -+ const_tree fntype ATTRIBUTE_UNUSED, -+ rtx libname ATTRIBUTE_UNUSED, -+ const_tree fndecl ATTRIBUTE_UNUSED, -+ unsigned n_named ATTRIBUTE_UNUSED) -+{ -+ pcum->aapcs_ncrn = 0; -+ pcum->aapcs_nvrn = 0; -+ pcum->aapcs_nextncrn = 0; -+ pcum->aapcs_nextnvrn = 0; -+ pcum->pcs_variant = ARM_PCS_AAPCS64; -+ pcum->aapcs_reg = NULL_RTX; -+ pcum->aapcs_arg_processed = false; -+ pcum->aapcs_stack_words = 0; -+ pcum->aapcs_stack_size = 0; -+ -+ return; -+} -+ -+static void -+aarch64_function_arg_advance (cumulative_args_t pcum_v, -+ enum machine_mode mode, -+ const_tree type, -+ bool named) -+{ -+ CUMULATIVE_ARGS *pcum = get_cumulative_args (pcum_v); -+ if (pcum->pcs_variant == ARM_PCS_AAPCS64) -+ { -+ aarch64_layout_arg (pcum_v, mode, type, named); -+ gcc_assert ((pcum->aapcs_reg != NULL_RTX) -+ != (pcum->aapcs_stack_words != 0)); -+ pcum->aapcs_arg_processed = false; -+ pcum->aapcs_ncrn = pcum->aapcs_nextncrn; -+ pcum->aapcs_nvrn = pcum->aapcs_nextnvrn; -+ pcum->aapcs_stack_size += pcum->aapcs_stack_words; -+ pcum->aapcs_stack_words = 0; -+ pcum->aapcs_reg = NULL_RTX; -+ } -+} -+ -+bool -+aarch64_function_arg_regno_p (unsigned regno) -+{ -+ return ((GP_REGNUM_P (regno) && regno < R0_REGNUM + NUM_ARG_REGS) -+ || (FP_REGNUM_P (regno) && regno < V0_REGNUM + NUM_FP_ARG_REGS)); -+} -+ -+/* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least -+ PARM_BOUNDARY bits of alignment, but will be given anything up -+ to STACK_BOUNDARY bits if the type requires it. This makes sure -+ that both before and after the layout of each argument, the Next -+ Stacked Argument Address (NSAA) will have a minimum alignment of -+ 8 bytes. */ -+ -+static unsigned int -+aarch64_function_arg_boundary (enum machine_mode mode, const_tree type) -+{ -+ unsigned int alignment = aarch64_function_arg_alignment (mode, type); -+ -+ if (alignment < PARM_BOUNDARY) -+ alignment = PARM_BOUNDARY; -+ if (alignment > STACK_BOUNDARY) -+ alignment = STACK_BOUNDARY; -+ return alignment; -+} -+ -+/* For use by FUNCTION_ARG_PADDING (MODE, TYPE). -+ -+ Return true if an argument passed on the stack should be padded upwards, -+ i.e. if the least-significant byte of the stack slot has useful data. -+ -+ Small aggregate types are placed in the lowest memory address. -+ -+ The related parameter passing rules are B.4, C.3, C.5 and C.14. */ -+ -+bool -+aarch64_pad_arg_upward (enum machine_mode mode, const_tree type) -+{ -+ /* On little-endian targets, the least significant byte of every stack -+ argument is passed at the lowest byte address of the stack slot. */ -+ if (!BYTES_BIG_ENDIAN) -+ return true; -+ -+ /* Otherwise, integral types and floating point types are padded downward: -+ the least significant byte of a stack argument is passed at the highest -+ byte address of the stack slot. */ -+ if (type -+ ? (INTEGRAL_TYPE_P (type) || SCALAR_FLOAT_TYPE_P (type)) -+ : (SCALAR_INT_MODE_P (mode) || SCALAR_FLOAT_MODE_P (mode))) -+ return false; -+ -+ /* Everything else padded upward, i.e. data in first byte of stack slot. */ -+ return true; -+} -+ -+/* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST). -+ -+ It specifies padding for the last (may also be the only) -+ element of a block move between registers and memory. If -+ assuming the block is in the memory, padding upward means that -+ the last element is padded after its highest significant byte, -+ while in downward padding, the last element is padded at the -+ its least significant byte side. -+ -+ Small aggregates and small complex types are always padded -+ upwards. -+ -+ We don't need to worry about homogeneous floating-point or -+ short-vector aggregates; their move is not affected by the -+ padding direction determined here. Regardless of endianness, -+ each element of such an aggregate is put in the least -+ significant bits of a fp/simd register. -+ -+ Return !BYTES_BIG_ENDIAN if the least significant byte of the -+ register has useful data, and return the opposite if the most -+ significant byte does. */ -+ -+bool -+aarch64_pad_reg_upward (enum machine_mode mode, const_tree type, -+ bool first ATTRIBUTE_UNUSED) -+{ -+ -+ /* Small composite types are always padded upward. */ -+ if (BYTES_BIG_ENDIAN && aarch64_composite_type_p (type, mode)) -+ { -+ HOST_WIDE_INT size = (type ? int_size_in_bytes (type) -+ : GET_MODE_SIZE (mode)); -+ if (size < 2 * UNITS_PER_WORD) -+ return true; -+ } -+ -+ /* Otherwise, use the default padding. */ -+ return !BYTES_BIG_ENDIAN; -+} -+ -+static enum machine_mode -+aarch64_libgcc_cmp_return_mode (void) -+{ -+ return SImode; -+} -+ -+static bool -+aarch64_frame_pointer_required (void) -+{ -+ /* If the function contains dynamic stack allocations, we need to -+ use the frame pointer to access the static parts of the frame. */ -+ if (cfun->calls_alloca) -+ return true; -+ -+ /* We may have turned flag_omit_frame_pointer on in order to have this -+ function called; if we did, we also set the 'faked_omit_frame_pointer' flag -+ and we'll check it here. -+ If we really did set flag_omit_frame_pointer normally, then we return false -+ (no frame pointer required) in all cases. */ -+ -+ if (flag_omit_frame_pointer && !faked_omit_frame_pointer) -+ return false; -+ else if (flag_omit_leaf_frame_pointer) -+ return !current_function_is_leaf; -+ return true; -+} -+ -+/* Mark the registers that need to be saved by the callee and calculate -+ the size of the callee-saved registers area and frame record (both FP -+ and LR may be omitted). */ -+static void -+aarch64_layout_frame (void) -+{ -+ HOST_WIDE_INT offset = 0; -+ int regno; -+ -+ if (reload_completed && cfun->machine->frame.laid_out) -+ return; -+ -+ cfun->machine->frame.fp_lr_offset = 0; -+ -+ /* First mark all the registers that really need to be saved... */ -+ for (regno = R0_REGNUM; regno <= R30_REGNUM; regno++) -+ cfun->machine->frame.reg_offset[regno] = -1; -+ -+ for (regno = V0_REGNUM; regno <= V31_REGNUM; regno++) -+ cfun->machine->frame.reg_offset[regno] = -1; -+ -+ /* ... that includes the eh data registers (if needed)... */ -+ if (crtl->calls_eh_return) -+ for (regno = 0; EH_RETURN_DATA_REGNO (regno) != INVALID_REGNUM; regno++) -+ cfun->machine->frame.reg_offset[EH_RETURN_DATA_REGNO (regno)] = 0; -+ -+ /* ... and any callee saved register that dataflow says is live. */ -+ for (regno = R0_REGNUM; regno <= R30_REGNUM; regno++) -+ if (df_regs_ever_live_p (regno) -+ && !call_used_regs[regno]) -+ cfun->machine->frame.reg_offset[regno] = 0; -+ -+ for (regno = V0_REGNUM; regno <= V31_REGNUM; regno++) -+ if (df_regs_ever_live_p (regno) -+ && !call_used_regs[regno]) -+ cfun->machine->frame.reg_offset[regno] = 0; -+ -+ if (frame_pointer_needed) -+ { -+ cfun->machine->frame.reg_offset[R30_REGNUM] = 0; -+ cfun->machine->frame.reg_offset[R29_REGNUM] = 0; -+ cfun->machine->frame.hardfp_offset = 2 * UNITS_PER_WORD; -+ } -+ -+ /* Now assign stack slots for them. */ -+ for (regno = R0_REGNUM; regno <= R28_REGNUM; regno++) -+ if (cfun->machine->frame.reg_offset[regno] != -1) -+ { -+ cfun->machine->frame.reg_offset[regno] = offset; -+ offset += UNITS_PER_WORD; -+ } -+ -+ for (regno = V0_REGNUM; regno <= V31_REGNUM; regno++) -+ if (cfun->machine->frame.reg_offset[regno] != -1) -+ { -+ cfun->machine->frame.reg_offset[regno] = offset; -+ offset += UNITS_PER_WORD; -+ } -+ -+ if (frame_pointer_needed) -+ { -+ cfun->machine->frame.reg_offset[R29_REGNUM] = offset; -+ offset += UNITS_PER_WORD; -+ cfun->machine->frame.fp_lr_offset = UNITS_PER_WORD; -+ } -+ -+ if (cfun->machine->frame.reg_offset[R30_REGNUM] != -1) -+ { -+ cfun->machine->frame.reg_offset[R30_REGNUM] = offset; -+ offset += UNITS_PER_WORD; -+ cfun->machine->frame.fp_lr_offset += UNITS_PER_WORD; -+ } -+ -+ cfun->machine->frame.padding0 = -+ (AARCH64_ROUND_UP (offset, STACK_BOUNDARY / BITS_PER_UNIT) - offset); -+ offset = AARCH64_ROUND_UP (offset, STACK_BOUNDARY / BITS_PER_UNIT); -+ -+ cfun->machine->frame.saved_regs_size = offset; -+ cfun->machine->frame.laid_out = true; -+} -+ -+/* Make the last instruction frame-related and note that it performs -+ the operation described by FRAME_PATTERN. */ -+ -+static void -+aarch64_set_frame_expr (rtx frame_pattern) -+{ -+ rtx insn; -+ -+ insn = get_last_insn (); -+ RTX_FRAME_RELATED_P (insn) = 1; -+ RTX_FRAME_RELATED_P (frame_pattern) = 1; -+ REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR, -+ frame_pattern, -+ REG_NOTES (insn)); -+} -+ -+static bool -+aarch64_register_saved_on_entry (int regno) -+{ -+ return cfun->machine->frame.reg_offset[regno] != -1; -+} -+ -+ -+static void -+aarch64_save_or_restore_fprs (int start_offset, int increment, -+ bool restore, rtx base_rtx) -+ -+{ -+ unsigned regno; -+ unsigned regno2; -+ rtx insn; -+ rtx (*gen_mem_ref)(enum machine_mode, rtx) = (frame_pointer_needed)? gen_frame_mem : gen_rtx_MEM; -+ -+ -+ for (regno = V0_REGNUM; regno <= V31_REGNUM; regno++) -+ { -+ if (aarch64_register_saved_on_entry (regno)) -+ { -+ rtx mem; -+ mem = gen_mem_ref (DFmode, -+ plus_constant (base_rtx, -+ start_offset)); -+ -+ for (regno2 = regno + 1; -+ regno2 <= V31_REGNUM -+ && !aarch64_register_saved_on_entry (regno2); -+ regno2++) -+ { -+ /* Empty loop. */ -+ } -+ if (regno2 <= V31_REGNUM && -+ aarch64_register_saved_on_entry (regno2)) -+ { -+ rtx mem2; -+ /* Next highest register to be saved. */ -+ mem2 = gen_mem_ref (DFmode, -+ plus_constant -+ (base_rtx, -+ start_offset + increment)); -+ if (restore == false) -+ { -+ insn = emit_insn -+ ( gen_store_pairdf (mem, gen_rtx_REG (DFmode, regno), -+ mem2, gen_rtx_REG (DFmode, regno2))); -+ -+ } -+ else -+ { -+ insn = emit_insn -+ ( gen_load_pairdf (gen_rtx_REG (DFmode, regno), mem, -+ gen_rtx_REG (DFmode, regno2), mem2)); -+ -+ add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (DFmode, regno)); -+ add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (DFmode, regno2)); -+ } -+ -+ /* The first part of a frame-related parallel insn -+ is always assumed to be relevant to the frame -+ calculations; subsequent parts, are only -+ frame-related if explicitly marked. */ -+ RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, -+ 1)) = 1; -+ regno = regno2; -+ start_offset += increment * 2; -+ } -+ else -+ { -+ if (restore == false) -+ insn = emit_move_insn (mem, gen_rtx_REG (DFmode, regno)); -+ else -+ { -+ insn = emit_move_insn (gen_rtx_REG (DFmode, regno), mem); -+ add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (DImode, regno)); -+ } -+ start_offset += increment; -+ } -+ RTX_FRAME_RELATED_P (insn) = 1; -+ } -+ } -+ -+} -+ -+ -+/* offset from the stack pointer of where the saves and -+ restore's have to happen. */ -+static void -+aarch64_save_or_restore_callee_save_registers (HOST_WIDE_INT offset, -+ bool restore) -+{ -+ rtx insn; -+ rtx base_rtx = stack_pointer_rtx; -+ HOST_WIDE_INT start_offset = offset; -+ HOST_WIDE_INT increment = UNITS_PER_WORD; -+ rtx (*gen_mem_ref)(enum machine_mode, rtx) = (frame_pointer_needed)? gen_frame_mem : gen_rtx_MEM; -+ unsigned limit = (frame_pointer_needed)? R28_REGNUM: R30_REGNUM; -+ unsigned regno; -+ unsigned regno2; -+ -+ for (regno = R0_REGNUM; regno <= limit; regno++) -+ { -+ if (aarch64_register_saved_on_entry (regno)) -+ { -+ rtx mem; -+ mem = gen_mem_ref (Pmode, -+ plus_constant (base_rtx, -+ start_offset)); -+ -+ for (regno2 = regno + 1; -+ regno2 <= limit -+ && !aarch64_register_saved_on_entry (regno2); -+ regno2++) -+ { -+ /* Empty loop. */ -+ } -+ if (regno2 <= limit && -+ aarch64_register_saved_on_entry (regno2)) -+ { -+ rtx mem2; -+ /* Next highest register to be saved. */ -+ mem2 = gen_mem_ref (Pmode, -+ plus_constant -+ (base_rtx, -+ start_offset + increment)); -+ if (restore == false) -+ { -+ insn = emit_insn -+ ( gen_store_pairdi (mem, gen_rtx_REG (DImode, regno), -+ mem2, gen_rtx_REG (DImode, regno2))); -+ -+ } -+ else -+ { -+ insn = emit_insn -+ ( gen_load_pairdi (gen_rtx_REG (DImode, regno), mem, -+ gen_rtx_REG (DImode, regno2), mem2)); -+ -+ add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (DImode, regno)); -+ add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (DImode, regno2)); -+ } -+ -+ /* The first part of a frame-related parallel insn -+ is always assumed to be relevant to the frame -+ calculations; subsequent parts, are only -+ frame-related if explicitly marked. */ -+ RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, -+ 1)) = 1; -+ regno = regno2; -+ start_offset += increment * 2; -+ } -+ else -+ { -+ if (restore == false) -+ insn = emit_move_insn (mem, gen_rtx_REG (DImode, regno)); -+ else -+ { -+ insn = emit_move_insn (gen_rtx_REG (DImode, regno), mem); -+ add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (DImode, regno)); -+ } -+ start_offset += increment; -+ } -+ RTX_FRAME_RELATED_P (insn) = 1; -+ } -+ } -+ -+ aarch64_save_or_restore_fprs (start_offset, increment, restore, base_rtx); -+ -+} -+ -+/* AArch64 stack frames generated by this compiler look like: -+ -+ +-------------------------------+ -+ | | -+ | incoming stack arguments | -+ | | -+ +-------------------------------+ <-- arg_pointer_rtx -+ | | -+ | callee-allocated save area | -+ | for register varargs | -+ | | -+ +-------------------------------+ -+ | | -+ | local variables | -+ | | -+ +-------------------------------+ <-- frame_pointer_rtx -+ | | -+ | callee-saved registers | -+ | | -+ +-------------------------------+ -+ | LR' | -+ +-------------------------------+ -+ | FP' | -+ P +-------------------------------+ <-- hard_frame_pointer_rtx -+ | dynamic allocation | -+ +-------------------------------+ -+ | | -+ | outgoing stack arguments | -+ | | -+ +-------------------------------+ <-- stack_pointer_rtx -+ -+ Dynamic stack allocations such as alloca insert data at point P. -+ They decrease stack_pointer_rtx but leave frame_pointer_rtx and -+ hard_frame_pointer_rtx unchanged. */ -+ -+/* Generate the prologue instructions for entry into a function. -+ Establish the stack frame by decreasing the stack pointer with a -+ properly calculated size and, if necessary, create a frame record -+ filled with the values of LR and previous frame pointer. The -+ current FP is also set up is it is in use. */ -+ -+void -+aarch64_expand_prologue (void) -+{ -+ /* sub sp, sp, # -+ stp {fp, lr}, [sp, # - 16] -+ add fp, sp, # - hardfp_offset -+ stp {cs_reg}, [fp, #-16] etc. -+ -+ sub sp, sp, -+ */ -+ HOST_WIDE_INT original_frame_size; /* local variables + vararg save */ -+ HOST_WIDE_INT frame_size, offset; -+ HOST_WIDE_INT fp_offset; /* FP offset from SP */ -+ rtx insn; -+ -+ aarch64_layout_frame (); -+ original_frame_size = get_frame_size () + cfun->machine->saved_varargs_size; -+ gcc_assert ((!cfun->machine->saved_varargs_size || cfun->stdarg) -+ && (cfun->stdarg || !cfun->machine->saved_varargs_size)); -+ frame_size = (original_frame_size + cfun->machine->frame.saved_regs_size -+ + crtl->outgoing_args_size); -+ offset = frame_size = AARCH64_ROUND_UP (frame_size, -+ STACK_BOUNDARY / BITS_PER_UNIT); -+ -+ if (flag_stack_usage_info) -+ current_function_static_stack_size = frame_size; -+ -+ fp_offset = (offset -+ - original_frame_size -+ - cfun->machine->frame.saved_regs_size); -+ -+ /* Store pairs and load pairs have a range only of +/- 512. */ -+ if (offset >= 512) -+ { -+ /* When the frame has a large size, an initial decrease is done on -+ the stack pointer to jump over the callee-allocated save area for -+ register varargs, the local variable area and/or the callee-saved -+ register area. This will allow the pre-index write-back -+ store pair instructions to be used for setting up the stack frame -+ efficiently. */ -+ offset = original_frame_size + cfun->machine->frame.saved_regs_size; -+ if (offset >= 512) -+ offset = cfun->machine->frame.saved_regs_size; -+ -+ frame_size -= (offset + crtl->outgoing_args_size); -+ fp_offset = 0; -+ -+ if (frame_size >= 0x1000000) -+ { -+ rtx op0 = gen_rtx_REG (Pmode, IP0_REGNUM); -+ emit_move_insn (op0, GEN_INT (-frame_size)); -+ emit_insn (gen_add2_insn (stack_pointer_rtx, op0)); -+ aarch64_set_frame_expr (gen_rtx_SET -+ (Pmode, stack_pointer_rtx, -+ gen_rtx_PLUS (Pmode, -+ stack_pointer_rtx, -+ GEN_INT (-frame_size)))); -+ } -+ else if (frame_size > 0) -+ { -+ if ((frame_size & 0xfff) != frame_size) -+ { -+ insn = emit_insn (gen_add2_insn -+ (stack_pointer_rtx, -+ GEN_INT (-(frame_size -+ & ~(HOST_WIDE_INT)0xfff)))); -+ RTX_FRAME_RELATED_P (insn) = 1; -+ } -+ if ((frame_size & 0xfff) != 0) -+ { -+ insn = emit_insn (gen_add2_insn -+ (stack_pointer_rtx, -+ GEN_INT (-(frame_size -+ & (HOST_WIDE_INT)0xfff)))); -+ RTX_FRAME_RELATED_P (insn) = 1; -+ } -+ } -+ } -+ else -+ frame_size = -1; -+ -+ if (offset > 0) -+ { -+ /* Save the frame pointer and lr if the frame pointer is needed -+ first. Make the frame pointer point to the location of the -+ old frame pointer on the stack. */ -+ if (frame_pointer_needed) -+ { -+ rtx mem_fp, mem_lr; -+ -+ if (fp_offset) -+ { -+ insn = emit_insn (gen_add2_insn (stack_pointer_rtx, -+ GEN_INT (-offset))); -+ RTX_FRAME_RELATED_P (insn) = 1; -+ aarch64_set_frame_expr (gen_rtx_SET -+ (Pmode, stack_pointer_rtx, -+ gen_rtx_MINUS (Pmode, -+ stack_pointer_rtx, -+ GEN_INT (offset)))); -+ mem_fp = gen_frame_mem (DImode, -+ plus_constant (stack_pointer_rtx, -+ fp_offset)); -+ mem_lr = gen_frame_mem (DImode, -+ plus_constant (stack_pointer_rtx, -+ fp_offset -+ + UNITS_PER_WORD)); -+ insn = emit_insn (gen_store_pairdi (mem_fp, -+ hard_frame_pointer_rtx, -+ mem_lr, -+ gen_rtx_REG (DImode, -+ LR_REGNUM))); -+ } -+ else -+ { -+ insn = emit_insn (gen_storewb_pairdi_di -+ (stack_pointer_rtx, stack_pointer_rtx, -+ hard_frame_pointer_rtx, -+ gen_rtx_REG (DImode, LR_REGNUM), -+ GEN_INT (-offset), -+ GEN_INT (GET_MODE_SIZE (DImode) - offset))); -+ RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 2)) = 1; -+ } -+ -+ /* The first part of a frame-related parallel insn is always -+ assumed to be relevant to the frame calculations; -+ subsequent parts, are only frame-related if explicitly -+ marked. */ -+ RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1; -+ RTX_FRAME_RELATED_P (insn) = 1; -+ -+ /* Set up frame pointer to point to the location of the -+ previous frame pointer on the stack. */ -+ insn = emit_insn (gen_add3_insn (hard_frame_pointer_rtx, -+ stack_pointer_rtx, -+ GEN_INT (fp_offset))); -+ aarch64_set_frame_expr (gen_rtx_SET -+ (Pmode, hard_frame_pointer_rtx, -+ gen_rtx_PLUS (Pmode, -+ stack_pointer_rtx, -+ GEN_INT (fp_offset)))); -+ RTX_FRAME_RELATED_P (insn) = 1; -+ insn = emit_insn (gen_stack_tie (stack_pointer_rtx, -+ hard_frame_pointer_rtx)); -+ } -+ else -+ { -+ insn = emit_insn (gen_add2_insn (stack_pointer_rtx, -+ GEN_INT (-offset))); -+ RTX_FRAME_RELATED_P (insn) = 1; -+ } -+ -+ aarch64_save_or_restore_callee_save_registers -+ (fp_offset + cfun->machine->frame.hardfp_offset, 0); -+ } -+ -+ /* when offset >= 512, -+ sub sp, sp, # */ -+ if (frame_size > -1) -+ { -+ if (crtl->outgoing_args_size > 0) -+ { -+ insn = emit_insn (gen_add2_insn -+ (stack_pointer_rtx, -+ GEN_INT (- crtl->outgoing_args_size))); -+ RTX_FRAME_RELATED_P (insn) = 1; -+ } -+ } -+} -+ -+/* Generate the epilogue instructions for returning from a function. */ -+void -+aarch64_expand_epilogue (bool for_sibcall) -+{ -+ HOST_WIDE_INT original_frame_size, frame_size, offset; -+ HOST_WIDE_INT fp_offset; -+ rtx insn; -+ -+ aarch64_layout_frame (); -+ original_frame_size = get_frame_size () + cfun->machine->saved_varargs_size; -+ frame_size = (original_frame_size + cfun->machine->frame.saved_regs_size -+ + crtl->outgoing_args_size); -+ offset = frame_size = AARCH64_ROUND_UP (frame_size, -+ STACK_BOUNDARY / BITS_PER_UNIT); -+ -+ fp_offset = (offset -+ - original_frame_size -+ - cfun->machine->frame.saved_regs_size); -+ -+ /* Store pairs and load pairs have a range only of +/- 512. */ -+ if (offset >= 512) -+ { -+ offset = original_frame_size + cfun->machine->frame.saved_regs_size; -+ if (offset >= 512) -+ offset = cfun->machine->frame.saved_regs_size; -+ -+ frame_size -= (offset + crtl->outgoing_args_size); -+ fp_offset = 0; -+ if (!frame_pointer_needed && crtl->outgoing_args_size > 0) -+ { -+ insn = emit_insn (gen_add2_insn -+ (stack_pointer_rtx, -+ GEN_INT (crtl->outgoing_args_size))); -+ RTX_FRAME_RELATED_P (insn) = 1; -+ } -+ } -+ else -+ frame_size = -1; -+ -+ /* If there were outgoing arguments or we've done dynamic stack -+ allocation, then restore the stack pointer from the frame -+ pointer. This is at most one insn and more efficient than using -+ GCC's internal mechanism. */ -+ if (frame_pointer_needed -+ && (crtl->outgoing_args_size || cfun->calls_alloca)) -+ { -+ insn = emit_insn (gen_add3_insn (stack_pointer_rtx, -+ hard_frame_pointer_rtx, -+ GEN_INT (- fp_offset))); -+ RTX_FRAME_RELATED_P (insn) = 1; -+ } -+ -+ aarch64_save_or_restore_callee_save_registers -+ (fp_offset + cfun->machine->frame.hardfp_offset, 1); -+ -+ /* Restore the frame pointer and lr if the frame pointer is needed. */ -+ if (offset > 0) -+ { -+ if (frame_pointer_needed) -+ { -+ rtx mem_fp, mem_lr; -+ -+ if (fp_offset) -+ { -+ mem_fp = gen_frame_mem (DImode, -+ plus_constant (stack_pointer_rtx, -+ fp_offset)); -+ mem_lr = gen_frame_mem (DImode, -+ plus_constant (stack_pointer_rtx, -+ fp_offset -+ + UNITS_PER_WORD)); -+ insn = emit_insn (gen_load_pairdi (hard_frame_pointer_rtx, -+ mem_fp, -+ gen_rtx_REG (DImode, -+ LR_REGNUM), -+ mem_lr)); -+ } -+ else -+ { -+ insn = emit_insn (gen_loadwb_pairdi_di -+ (stack_pointer_rtx, -+ stack_pointer_rtx, -+ hard_frame_pointer_rtx, -+ gen_rtx_REG (DImode, LR_REGNUM), -+ GEN_INT (offset), -+ GEN_INT (GET_MODE_SIZE (DImode) + offset))); -+ RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 2)) = 1; -+ aarch64_set_frame_expr (gen_rtx_SET -+ (Pmode, -+ stack_pointer_rtx, -+ gen_rtx_PLUS (Pmode, stack_pointer_rtx, -+ GEN_INT (offset)))); -+ } -+ -+ /* The first part of a frame-related parallel insn -+ is always assumed to be relevant to the frame -+ calculations; subsequent parts, are only -+ frame-related if explicitly marked. */ -+ RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1; -+ RTX_FRAME_RELATED_P (insn) = 1; -+ add_reg_note (insn, REG_CFA_RESTORE, hard_frame_pointer_rtx); -+ add_reg_note (insn, REG_CFA_RESTORE, -+ gen_rtx_REG (DImode, LR_REGNUM)); -+ -+ if (fp_offset) -+ { -+ insn = emit_insn (gen_add2_insn (stack_pointer_rtx, -+ GEN_INT (offset))); -+ RTX_FRAME_RELATED_P (insn) = 1; -+ } -+ } -+ -+ else -+ { -+ insn = emit_insn (gen_add2_insn (stack_pointer_rtx, -+ GEN_INT (offset))); -+ RTX_FRAME_RELATED_P (insn) = 1; -+ } -+ } -+ -+ /* Stack adjustment for exception handler. */ -+ if (crtl->calls_eh_return) -+ { -+ /* We need to unwind the stack by the offset computed by -+ EH_RETURN_STACKADJ_RTX. However, at this point the CFA is -+ based on SP. Ideally we would update the SP and define the -+ CFA along the lines of: -+ -+ SP = SP + EH_RETURN_STACKADJ_RTX -+ (regnote CFA = SP - EH_RETURN_STACKADJ_RTX) -+ -+ However the dwarf emitter only understands a constant -+ register offset. -+ -+ The solution choosen here is to use the otherwise unused IP0 -+ as a temporary register to hold the current SP value. The -+ CFA is described using IP0 then SP is modified. */ -+ -+ rtx ip0 = gen_rtx_REG (DImode, IP0_REGNUM); -+ -+ insn = emit_move_insn (ip0, stack_pointer_rtx); -+ add_reg_note (insn, REG_CFA_DEF_CFA, ip0); -+ RTX_FRAME_RELATED_P (insn) = 1; -+ -+ emit_insn (gen_add2_insn (stack_pointer_rtx, EH_RETURN_STACKADJ_RTX)); -+ -+ /* Ensure the assignment to IP0 does not get optimized away. */ -+ emit_use (ip0); -+ } -+ -+ if (frame_size > -1) -+ { -+ if (frame_size >= 0x1000000) -+ { -+ rtx op0 = gen_rtx_REG (Pmode, IP0_REGNUM); -+ emit_move_insn (op0, GEN_INT (frame_size)); -+ emit_insn (gen_add2_insn (stack_pointer_rtx, op0)); -+ aarch64_set_frame_expr (gen_rtx_SET -+ (Pmode, stack_pointer_rtx, -+ gen_rtx_PLUS (Pmode, -+ stack_pointer_rtx, -+ GEN_INT (frame_size)))); -+ } -+ else if (frame_size > 0) -+ { -+ if ((frame_size & 0xfff) != 0) -+ { -+ insn = emit_insn (gen_add2_insn -+ (stack_pointer_rtx, -+ GEN_INT ((frame_size -+ & (HOST_WIDE_INT) 0xfff)))); -+ RTX_FRAME_RELATED_P (insn) = 1; -+ } -+ if ((frame_size & 0xfff) != frame_size) -+ { -+ insn = emit_insn (gen_add2_insn -+ (stack_pointer_rtx, -+ GEN_INT ((frame_size -+ & ~ (HOST_WIDE_INT) 0xfff)))); -+ RTX_FRAME_RELATED_P (insn) = 1; -+ } -+ } -+ -+ aarch64_set_frame_expr (gen_rtx_SET (Pmode, stack_pointer_rtx, -+ gen_rtx_PLUS (Pmode, -+ stack_pointer_rtx, -+ GEN_INT (offset)))); -+ } -+ -+ emit_use (gen_rtx_REG (DImode, LR_REGNUM)); -+ if (!for_sibcall) -+ emit_jump_insn (ret_rtx); -+} -+ -+/* Return the place to copy the exception unwinding return address to. -+ This will probably be a stack slot, but could (in theory be the -+ return register). */ -+rtx -+aarch64_final_eh_return_addr (void) -+{ -+ HOST_WIDE_INT original_frame_size, frame_size, offset, fp_offset; -+ aarch64_layout_frame (); -+ original_frame_size = get_frame_size () + cfun->machine->saved_varargs_size; -+ frame_size = (original_frame_size + cfun->machine->frame.saved_regs_size -+ + crtl->outgoing_args_size); -+ offset = frame_size = AARCH64_ROUND_UP (frame_size, -+ STACK_BOUNDARY / BITS_PER_UNIT); -+ fp_offset = offset -+ - original_frame_size -+ - cfun->machine->frame.saved_regs_size; -+ -+ if (cfun->machine->frame.reg_offset[LR_REGNUM] < 0) -+ return gen_rtx_REG (DImode, LR_REGNUM); -+ -+ /* DSE and CSELIB do not detect an alias between sp+k1 and fp+k2. This can -+ result in a store to save LR introduced by builtin_eh_return () being -+ incorrectly deleted because the alias is not detected. -+ So in the calculation of the address to copy the exception unwinding -+ return address to, we note 2 cases. -+ If FP is needed and the fp_offset is 0, it means that SP = FP and hence -+ we return a SP-relative location since all the addresses are SP-relative -+ in this case. This prevents the store from being optimized away. -+ If the fp_offset is not 0, then the addresses will be FP-relative and -+ therefore we return a FP-relative location. */ -+ -+ if (frame_pointer_needed) -+ { -+ if (fp_offset) -+ return gen_frame_mem (DImode, -+ plus_constant (hard_frame_pointer_rtx, UNITS_PER_WORD)); -+ else -+ return gen_frame_mem (DImode, -+ plus_constant (stack_pointer_rtx, UNITS_PER_WORD)); -+ } -+ -+ /* If FP is not needed, we calculate the location of LR, which would be -+ at the top of the saved registers block. */ -+ -+ return gen_frame_mem (DImode, -+ plus_constant (stack_pointer_rtx, -+ fp_offset -+ + cfun->machine->frame.saved_regs_size -+ - 2 * UNITS_PER_WORD)); -+} -+ -+/* Output code to build up a constant in a register. */ -+static void -+aarch64_build_constant (FILE *file, -+ int regnum, -+ HOST_WIDE_INT val) -+{ -+ if (aarch64_bitmask_imm (val, DImode)) -+ asm_fprintf (file, "\tmovi\t%r, %wd\n", regnum, val); -+ else -+ { -+ int i; -+ int ncount = 0; -+ int zcount = 0; -+ HOST_WIDE_INT valp = val >> 16; -+ HOST_WIDE_INT valm; -+ HOST_WIDE_INT tval; -+ -+ for (i = 16; i < 64; i += 16) -+ { -+ valm = (valp & 0xffff); -+ -+ if (valm != 0) -+ ++ zcount; -+ -+ if (valm != 0xffff) -+ ++ ncount; -+ -+ valp >>= 16; -+ } -+ -+ /* zcount contains the number of additional MOVK instructions -+ required if the constant is built up with an initial MOVZ instruction, -+ while ncount is the number of MOVK instructions required if starting -+ with a MOVN instruction. Choose the sequence that yields the fewest -+ number of instructions, preferring MOVZ instructions when they are both -+ the same. */ -+ if (ncount < zcount) -+ { -+ asm_fprintf (file, "\tmovn\t%r, %wd\n", regnum, (~val) & 0xffff); -+ tval = 0xffff; -+ } -+ else -+ { -+ asm_fprintf (file, "\tmovz\t%r, %wd\n", regnum, val & 0xffff); -+ tval = 0; -+ } -+ -+ val >>= 16; -+ -+ for (i = 16; i < 64; i += 16) -+ { -+ if ((val & 0xffff) != tval) -+ asm_fprintf (file, "\tmovk\t%r, %wd, lsl %d\n", -+ regnum, val & 0xffff, i); -+ val >>= 16; -+ } -+ } -+} -+ -+static void -+aarch64_add_constant (FILE *file, int regnum, int scratchreg, -+ HOST_WIDE_INT delta) -+{ -+ HOST_WIDE_INT mdelta = delta; -+ -+ if (mdelta < 0) -+ mdelta = -mdelta; -+ -+ if (mdelta >= 4096 * 4096) -+ { -+ aarch64_build_constant (file, scratchreg, delta); -+ asm_fprintf (file, "\tadd\t%r, %r, %r\n", regnum, regnum, -+ scratchreg); -+ } -+ else if (mdelta > 0) -+ { -+ const char *const mi_op = delta < 0 ? "sub" : "add"; -+ -+ if (mdelta >= 4096) -+ asm_fprintf (file, "\t%s\t%r, %r, %wd, lsl 12\n", mi_op, regnum, regnum, -+ mdelta / 4096); -+ -+ if (mdelta % 4096 != 0) -+ asm_fprintf (file, "\t%s\t%r, %r, %wd\n", mi_op, regnum, regnum, -+ mdelta % 4096); -+ } -+} -+ -+/* Output code to add DELTA to the first argument, and then jump -+ to FUNCTION. Used for C++ multiple inheritance. */ -+static void -+aarch64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, -+ HOST_WIDE_INT delta, -+ HOST_WIDE_INT vcall_offset, -+ tree function) -+{ -+ /* The this pointer is always in x0. Note that this differs from -+ Arm where the this pointer maybe bumped to r1 if r0 is required -+ to return a pointer to an aggregate. On AArch64 a result value -+ pointer will be in x8. */ -+ int this_regno = R0_REGNUM; -+ -+ /* Make sure unwind info is emitted for the thunk if needed. */ -+ final_start_function (emit_barrier (), file, 1); -+ -+ if (vcall_offset == 0) -+ aarch64_add_constant (file, this_regno, IP1_REGNUM, delta); -+ else -+ { -+ gcc_assert ((vcall_offset & 0x7) == 0); -+ -+ if (delta == 0) -+ asm_fprintf (file, "\tldr\t%r, [%r]\n", IP0_REGNUM, this_regno); -+ else if (delta >= -256 && delta < 256) -+ asm_fprintf (file, "\tldr\t%r, [%r,%wd]!\n", IP0_REGNUM, this_regno, -+ delta); -+ else -+ { -+ aarch64_add_constant (file, this_regno, IP1_REGNUM, delta); -+ -+ asm_fprintf (file, "\tldr\t%r, [%r]\n", IP0_REGNUM, this_regno); -+ } -+ -+ if (vcall_offset >= -256 && vcall_offset < 32768) -+ asm_fprintf (file, "\tldr\t%r, [%r,%wd]\n", IP1_REGNUM, IP0_REGNUM, -+ vcall_offset); -+ else -+ { -+ aarch64_build_constant (file, IP1_REGNUM, vcall_offset); -+ asm_fprintf (file, "\tldr\t%r, [%r,%r]\n", IP1_REGNUM, IP0_REGNUM, -+ IP1_REGNUM); -+ } -+ -+ asm_fprintf (file, "\tadd\t%r, %r, %r\n", this_regno, this_regno, -+ IP1_REGNUM); -+ } -+ -+ output_asm_insn ("b\t%a0", &XEXP (DECL_RTL (function), 0)); -+ final_end_function (); -+} -+ -+ -+static int -+aarch64_tls_operand_p_1 (rtx *x, void *data ATTRIBUTE_UNUSED) -+{ -+ if (GET_CODE (*x) == SYMBOL_REF) -+ return SYMBOL_REF_TLS_MODEL (*x) != 0; -+ -+ /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are -+ TLS offsets, not real symbol references. */ -+ if (GET_CODE (*x) == UNSPEC -+ && XINT (*x, 1) == UNSPEC_TLS) -+ return -1; -+ -+ return 0; -+} -+ -+static bool -+aarch64_tls_referenced_p (rtx x) -+{ -+ if (!TARGET_HAVE_TLS) -+ return false; -+ -+ return for_each_rtx (&x, aarch64_tls_operand_p_1, NULL); -+} -+ -+ -+static int -+aarch64_bitmasks_cmp (const void *i1, const void *i2) -+{ -+ const unsigned HOST_WIDE_INT *imm1 = (const unsigned HOST_WIDE_INT *) i1; -+ const unsigned HOST_WIDE_INT *imm2 = (const unsigned HOST_WIDE_INT *) i2; -+ -+ if (*imm1 < *imm2) -+ return -1; -+ if (*imm1 > *imm2) -+ return +1; -+ return 0; -+} -+ -+ -+static void -+aarch64_build_bitmask_table (void) -+{ -+ unsigned HOST_WIDE_INT mask, imm; -+ unsigned int log_e, e, s, r; -+ unsigned int nimms = 0; -+ -+ for (log_e = 1; log_e <= 6; log_e++) -+ { -+ e = 1 << log_e; -+ if (e == 64) -+ mask = ~(HOST_WIDE_INT) 0; -+ else -+ mask = ((HOST_WIDE_INT) 1 << e) - 1; -+ for (s = 1; s < e; s++) -+ { -+ for (r = 0; r < e; r++) -+ { -+ /* set s consecutive bits to 1 (s < 64) */ -+ imm = ((unsigned HOST_WIDE_INT)1 << s) - 1; -+ /* rotate right by r */ -+ if (r != 0) -+ imm = ((imm >> r) | (imm << (e - r))) & mask; -+ /* replicate the constant depending on SIMD size */ -+ switch (log_e) { -+ case 1: imm |= (imm << 2); -+ case 2: imm |= (imm << 4); -+ case 3: imm |= (imm << 8); -+ case 4: imm |= (imm << 16); -+ case 5: imm |= (imm << 32); -+ case 6: -+ break; -+ default: -+ gcc_unreachable (); -+ } -+ gcc_assert (nimms < AARCH64_NUM_BITMASKS); -+ aarch64_bitmasks[nimms++] = imm; -+ } -+ } -+ } -+ -+ gcc_assert (nimms == AARCH64_NUM_BITMASKS); -+ qsort (aarch64_bitmasks, nimms, sizeof (aarch64_bitmasks[0]), -+ aarch64_bitmasks_cmp); -+} -+ -+ -+/* Return true if val can be encoded as a 12-bit unsigned immediate with -+ a left shift of 0 or 12 bits. */ -+bool -+aarch64_uimm12_shift (HOST_WIDE_INT val) -+{ -+ return ((val & (((HOST_WIDE_INT) 0xfff) << 0)) == val -+ || (val & (((HOST_WIDE_INT) 0xfff) << 12)) == val -+ ); -+} -+ -+ -+/* Return true if val is an immediate that can be loaded into a -+ register by a MOVZ instruction. */ -+static bool -+aarch64_movw_imm (HOST_WIDE_INT val, enum machine_mode mode) -+{ -+ if (GET_MODE_SIZE (mode) > 4) -+ { -+ if ((val & (((HOST_WIDE_INT) 0xffff) << 32)) == val -+ || (val & (((HOST_WIDE_INT) 0xffff) << 48)) == val) -+ return 1; -+ } -+ else -+ { -+ /* Ignore sign extension. */ -+ val &= (HOST_WIDE_INT) 0xffffffff; -+ } -+ return ((val & (((HOST_WIDE_INT) 0xffff) << 0)) == val -+ || (val & (((HOST_WIDE_INT) 0xffff) << 16)) == val); -+} -+ -+ -+/* Return true if val is a valid bitmask immediate. */ -+bool -+aarch64_bitmask_imm (HOST_WIDE_INT val, enum machine_mode mode) -+{ -+ if (GET_MODE_SIZE (mode) < 8) -+ { -+ /* Replicate bit pattern. */ -+ val &= (HOST_WIDE_INT) 0xffffffff; -+ val |= val << 32; -+ } -+ return bsearch (&val, aarch64_bitmasks, AARCH64_NUM_BITMASKS, -+ sizeof (aarch64_bitmasks[0]), aarch64_bitmasks_cmp) != NULL; -+} -+ -+ -+/* Return true if val is an immediate that can be loaded into a -+ register in a single instruction. */ -+bool -+aarch64_move_imm (HOST_WIDE_INT val, enum machine_mode mode) -+{ -+ if (aarch64_movw_imm (val, mode) || aarch64_movw_imm (~val, mode)) -+ return 1; -+ return aarch64_bitmask_imm (val, mode); -+} -+ -+static bool -+aarch64_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x) -+{ -+ rtx base, offset; -+ if (GET_CODE (x) == HIGH) -+ return true; -+ -+ split_const (x, &base, &offset); -+ if (GET_CODE (base) == SYMBOL_REF || GET_CODE (base) == LABEL_REF) -+ return (aarch64_classify_symbol (base, SYMBOL_CONTEXT_ADR) != SYMBOL_FORCE_TO_MEM); -+ -+ return aarch64_tls_referenced_p (x); -+} -+ -+/* Return true if register REGNO is a valid index register. -+ STRICT_P is true if REG_OK_STRICT is in effect. */ -+ -+bool -+aarch64_regno_ok_for_index_p (int regno, bool strict_p) -+{ -+ if (!HARD_REGISTER_NUM_P (regno)) -+ { -+ if (!strict_p) -+ return true; -+ -+ if (!reg_renumber) -+ return false; -+ -+ regno = reg_renumber[regno]; -+ } -+ return GP_REGNUM_P (regno); -+} -+ -+/* Return true if register REGNO is a valid base register for mode MODE. -+ STRICT_P is true if REG_OK_STRICT is in effect. */ -+ -+bool -+aarch64_regno_ok_for_base_p (int regno, bool strict_p) -+{ -+ if (!HARD_REGISTER_NUM_P (regno)) -+ { -+ if (!strict_p) -+ return true; -+ -+ if (!reg_renumber) -+ return false; -+ -+ regno = reg_renumber[regno]; -+ } -+ -+ /* The fake registers will be eliminated to either the stack or -+ hard frame pointer, both of which are usually valid base registers. -+ Reload deals with the cases where the eliminated form isn't valid. */ -+ return (GP_REGNUM_P (regno) -+ || regno == SP_REGNUM -+ || regno == FRAME_POINTER_REGNUM -+ || regno == ARG_POINTER_REGNUM); -+} -+ -+/* Return true if X is a valid base register for mode MODE. -+ STRICT_P is true if REG_OK_STRICT is in effect. */ -+ -+static bool -+aarch64_base_register_rtx_p (rtx x, bool strict_p) -+{ -+ if (!strict_p && GET_CODE (x) == SUBREG) -+ x = SUBREG_REG (x); -+ -+ return (REG_P (x) && aarch64_regno_ok_for_base_p (REGNO (x), strict_p)); -+} -+ -+/* Return true if address offset is a valid index. If it is, fill in INFO -+ appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */ -+ -+static bool -+aarch64_classify_index (struct aarch64_address_info *info, rtx x, -+ enum machine_mode mode, bool strict_p) -+{ -+ enum aarch64_address_type type; -+ rtx index; -+ int shift; -+ -+ /* (reg:P) */ -+ if ((REG_P (x) || GET_CODE (x) == SUBREG) -+ && GET_MODE (x) == Pmode) -+ { -+ type = ADDRESS_REG_REG; -+ index = x; -+ shift = 0; -+ } -+ /* (sign_extend:DI (reg:SI)) */ -+ else if ((GET_CODE (x) == SIGN_EXTEND -+ || GET_CODE (x) == ZERO_EXTEND) -+ && GET_MODE (x) == DImode -+ && GET_MODE (XEXP (x, 0)) == SImode) -+ { -+ type = (GET_CODE (x) == SIGN_EXTEND) -+ ? ADDRESS_REG_SXTW : ADDRESS_REG_UXTW; -+ index = XEXP (x, 0); -+ shift = 0; -+ } -+ /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */ -+ else if (GET_CODE (x) == MULT -+ && (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND -+ || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND) -+ && GET_MODE (XEXP (x, 0)) == DImode -+ && GET_MODE (XEXP (XEXP (x, 0), 0)) == SImode -+ && CONST_INT_P (XEXP (x, 1))) -+ { -+ type = (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND) -+ ? ADDRESS_REG_SXTW : ADDRESS_REG_UXTW; -+ index = XEXP (XEXP (x, 0), 0); -+ shift = exact_log2 (INTVAL (XEXP (x, 1))); -+ } -+ /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */ -+ else if (GET_CODE (x) == ASHIFT -+ && (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND -+ || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND) -+ && GET_MODE (XEXP (x, 0)) == DImode -+ && GET_MODE (XEXP (XEXP (x, 0), 0)) == SImode -+ && CONST_INT_P (XEXP (x, 1))) -+ { -+ type = (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND) -+ ? ADDRESS_REG_SXTW : ADDRESS_REG_UXTW; -+ index = XEXP (XEXP (x, 0), 0); -+ shift = INTVAL (XEXP (x, 1)); -+ } -+ /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */ -+ else if ((GET_CODE (x) == SIGN_EXTRACT -+ || GET_CODE (x) == ZERO_EXTRACT) -+ && GET_MODE (x) == DImode -+ && GET_CODE (XEXP (x, 0)) == MULT -+ && GET_MODE (XEXP (XEXP (x, 0), 0)) == DImode -+ && CONST_INT_P (XEXP (XEXP (x, 0), 1))) -+ { -+ type = (GET_CODE (x) == SIGN_EXTRACT) -+ ? ADDRESS_REG_SXTW : ADDRESS_REG_UXTW; -+ index = XEXP (XEXP (x, 0), 0); -+ shift = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1))); -+ if (INTVAL (XEXP (x, 1)) != 32 + shift -+ || INTVAL (XEXP (x, 2)) != 0) -+ shift = -1; -+ } -+ /* (and:DI (mult:DI (reg:DI) (const_int scale)) -+ (const_int 0xffffffff< 0 && shift <= 3 -+ && (1 << shift) == GET_MODE_SIZE (mode))) -+ && REG_P (index) -+ && aarch64_regno_ok_for_index_p (REGNO (index), strict_p)) -+ { -+ info->type = type; -+ info->offset = index; -+ info->shift = shift; -+ return true; -+ } -+ -+ return false; -+} -+ -+static inline bool -+offset_7bit_signed_scaled_p (enum machine_mode mode, HOST_WIDE_INT offset) -+{ -+ return (offset >= -64 * GET_MODE_SIZE (mode) -+ && offset < 64 * GET_MODE_SIZE (mode) -+ && offset % GET_MODE_SIZE (mode) == 0); -+} -+ -+static inline bool -+offset_9bit_signed_unscaled_p (enum machine_mode mode ATTRIBUTE_UNUSED, -+ HOST_WIDE_INT offset) -+{ -+ return offset >= -256 && offset < 256; -+} -+ -+static inline bool -+offset_12bit_unsigned_scaled_p (enum machine_mode mode, HOST_WIDE_INT offset) -+{ -+ return (offset >= 0 -+ && offset < 4096 * GET_MODE_SIZE (mode) -+ && offset % GET_MODE_SIZE (mode) == 0); -+} -+ -+/* Return true if X is a valid address for machine mode MODE. If it is, -+ fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in -+ effect. OUTER_CODE is PARALLEL for a load/store pair. */ -+ -+static bool -+aarch64_classify_address (struct aarch64_address_info *info, -+ rtx x, enum machine_mode mode, -+ RTX_CODE outer_code, bool strict_p) -+{ -+ enum rtx_code code = GET_CODE (x); -+ rtx op0, op1; -+ bool allow_reg_index_p = -+ outer_code != PARALLEL && GET_MODE_SIZE(mode) != 16; -+ -+ /* Don't support anything other than POST_INC or REG addressing for -+ AdvSIMD. */ -+ if (aarch64_vector_mode_supported_p (mode) -+ && (code != POST_INC && code != REG)) -+ return false; -+ -+ switch (code) -+ { -+ case REG: -+ case SUBREG: -+ info->type = ADDRESS_REG_IMM; -+ info->base = x; -+ info->offset = const0_rtx; -+ return aarch64_base_register_rtx_p (x, strict_p); -+ -+ case PLUS: -+ op0 = XEXP (x, 0); -+ op1 = XEXP (x, 1); -+ if (GET_MODE_SIZE (mode) != 0 -+ && CONST_INT_P (op1) -+ && aarch64_base_register_rtx_p (op0, strict_p)) -+ { -+ HOST_WIDE_INT offset = INTVAL (op1); -+ -+ info->type = ADDRESS_REG_IMM; -+ info->base = op0; -+ info->offset = op1; -+ -+ /* TImode and TFmode values are allowed in both pairs of X -+ registers and individual Q registers. The available -+ address modes are: -+ X,X: 7-bit signed scaled offset -+ Q: 9-bit signed offset -+ We conservatively require an offset representable in either mode. -+ */ -+ if (mode == TImode || mode == TFmode) -+ return (offset_7bit_signed_scaled_p (mode, offset) -+ && offset_9bit_signed_unscaled_p (mode, offset)); -+ -+ if (outer_code == PARALLEL) -+ return ((GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8) -+ && offset_7bit_signed_scaled_p (mode, offset)); -+ else -+ return (offset_9bit_signed_unscaled_p (mode, offset) -+ || offset_12bit_unsigned_scaled_p (mode, offset)); -+ } -+ -+ if (allow_reg_index_p) -+ { -+ /* Look for base + (scaled/extended) index register. */ -+ if (aarch64_base_register_rtx_p (op0, strict_p) -+ && aarch64_classify_index (info, op1, mode, strict_p)) -+ { -+ info->base = op0; -+ return true; -+ } -+ if (aarch64_base_register_rtx_p (op1, strict_p) -+ && aarch64_classify_index (info, op0, mode, strict_p)) -+ { -+ info->base = op1; -+ return true; -+ } -+ } -+ -+ return false; -+ -+ case POST_INC: -+ case POST_DEC: -+ case PRE_INC: -+ case PRE_DEC: -+ info->type = ADDRESS_REG_WB; -+ info->base = XEXP (x, 0); -+ info->offset = NULL_RTX; -+ return aarch64_base_register_rtx_p (info->base, strict_p); -+ -+ case POST_MODIFY: -+ case PRE_MODIFY: -+ info->type = ADDRESS_REG_WB; -+ info->base = XEXP (x, 0); -+ if (GET_CODE (XEXP (x, 1)) == PLUS -+ && CONST_INT_P (XEXP (XEXP (x, 1), 1)) -+ && rtx_equal_p (XEXP (XEXP (x, 1), 0), info->base) -+ && aarch64_base_register_rtx_p (info->base, strict_p)) -+ { -+ HOST_WIDE_INT offset; -+ info->offset = XEXP (XEXP (x, 1), 1); -+ offset = INTVAL (info->offset); -+ -+ /* TImode and TFmode values are allowed in both pairs of X -+ registers and individual Q registers. The available -+ address modes are: -+ X,X: 7-bit signed scaled offset -+ Q: 9-bit signed offset -+ We conservatively require an offset representable in either mode. -+ */ -+ if (mode == TImode || mode == TFmode) -+ return (offset_7bit_signed_scaled_p (mode, offset) -+ && offset_9bit_signed_unscaled_p (mode, offset)); -+ -+ if (outer_code == PARALLEL) -+ return ((GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8) -+ && offset_7bit_signed_scaled_p (mode, offset)); -+ else -+ return offset_9bit_signed_unscaled_p (mode, offset); -+ } -+ return false; -+ -+ case CONST: -+ case SYMBOL_REF: -+ case LABEL_REF: -+ /* load literal: pc-relative constant pool entry. */ -+ info->type = ADDRESS_SYMBOLIC; -+ if (outer_code != PARALLEL) -+ { -+ rtx sym, addend; -+ -+ split_const (x, &sym, &addend); -+ return (GET_CODE (sym) == LABEL_REF -+ || (GET_CODE (sym) == SYMBOL_REF -+ && CONSTANT_POOL_ADDRESS_P (sym))); -+ } -+ return false; -+ -+ case LO_SUM: -+ info->type = ADDRESS_LO_SUM; -+ info->base = XEXP (x, 0); -+ info->offset = XEXP (x, 1); -+ if (allow_reg_index_p -+ && aarch64_base_register_rtx_p (info->base, strict_p)) -+ { -+ rtx sym, offs; -+ split_const (info->offset, &sym, &offs); -+ if (GET_CODE (sym) == SYMBOL_REF -+ && (aarch64_classify_symbol (sym, SYMBOL_CONTEXT_MEM) -+ == SYMBOL_SMALL_ABSOLUTE)) -+ { -+ /* The symbol and offset must be aligned to the access size. */ -+ unsigned int align; -+ unsigned int ref_size; -+ -+ if (CONSTANT_POOL_ADDRESS_P (sym)) -+ align = GET_MODE_ALIGNMENT (get_pool_mode (sym)); -+ else if (TREE_CONSTANT_POOL_ADDRESS_P (sym)) -+ { -+ tree exp = SYMBOL_REF_DECL (sym); -+ align = TYPE_ALIGN (TREE_TYPE (exp)); -+ align = CONSTANT_ALIGNMENT (exp, align); -+ } -+ else if (SYMBOL_REF_DECL (sym)) -+ align = DECL_ALIGN (SYMBOL_REF_DECL (sym)); -+ else -+ align = BITS_PER_UNIT; -+ -+ ref_size = GET_MODE_SIZE (mode); -+ if (ref_size == 0) -+ ref_size = GET_MODE_SIZE (DImode); -+ -+ return ((INTVAL (offs) & (ref_size - 1)) == 0 -+ && ((align / BITS_PER_UNIT) & (ref_size - 1)) == 0); -+ } -+ } -+ return false; -+ -+ default: -+ return false; -+ } -+} -+ -+bool -+aarch64_symbolic_address_p (rtx x) -+{ -+ rtx offset; -+ -+ split_const (x, &x, &offset); -+ return GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF; -+} -+ -+/* Classify the base of symbolic expression X, given that X appears in -+ context CONTEXT. */ -+static enum aarch64_symbol_type -+aarch64_classify_symbolic_expression (rtx x, enum aarch64_symbol_context context) -+{ -+ rtx offset; -+ split_const (x, &x, &offset); -+ return aarch64_classify_symbol (x, context); -+} -+ -+ -+/* Return TRUE if X is a legitimate address for accessing memory in -+ mode MODE. */ -+static bool -+aarch64_legitimate_address_hook_p (enum machine_mode mode, rtx x, bool strict_p) -+{ -+ struct aarch64_address_info addr; -+ -+ return aarch64_classify_address (&addr, x, mode, MEM, strict_p); -+} -+ -+/* Return TRUE if X is a legitimate address for accessing memory in -+ mode MODE. OUTER_CODE will be PARALLEL if this is a load/store -+ pair operation. */ -+bool -+aarch64_legitimate_address_p (enum machine_mode mode, rtx x, -+ RTX_CODE outer_code, bool strict_p) -+{ -+ struct aarch64_address_info addr; -+ -+ return aarch64_classify_address (&addr, x, mode, outer_code, strict_p); -+} -+ -+/* Return TRUE if rtx X is immediate constant 0.0 */ -+bool -+aarch64_const_double_zero_rtx_p (rtx x) -+{ -+ REAL_VALUE_TYPE r; -+ -+ if (GET_MODE (x) == VOIDmode) -+ return false; -+ -+ REAL_VALUE_FROM_CONST_DOUBLE (r, x); -+ if (REAL_VALUE_MINUS_ZERO (r)) -+ return !HONOR_SIGNED_ZEROS (GET_MODE (x)); -+ return REAL_VALUES_EQUAL (r, dconst0); -+} -+ -+enum machine_mode -+aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y) -+{ -+ /* All floating point compares return CCFP if it is an equality -+ comparison, and CCFPE otherwise. */ -+ if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) -+ { -+ switch (code) -+ { -+ case EQ: -+ case NE: -+ case UNORDERED: -+ case ORDERED: -+ case UNLT: -+ case UNLE: -+ case UNGT: -+ case UNGE: -+ case UNEQ: -+ case LTGT: -+ return CCFPmode; -+ -+ case LT: -+ case LE: -+ case GT: -+ case GE: -+ return CCFPEmode; -+ -+ default: -+ gcc_unreachable (); -+ } -+ } -+ -+ if ((GET_MODE (x) == SImode || GET_MODE (x) == DImode) -+ && y == const0_rtx -+ && (code == EQ || code == NE || code == LT || code == GE) -+ && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS)) -+ return CC_NZmode; -+ -+ /* A compare with a shifted operand. Because of canonicalization, -+ the comparison will have to be swapped when we emit the assembly -+ code. */ -+ if ((GET_MODE (x) == SImode || GET_MODE (x) == DImode) -+ && (GET_CODE (y) == REG || GET_CODE (y) == SUBREG) -+ && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT -+ || GET_CODE (x) == LSHIFTRT -+ || GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)) -+ return CC_SWPmode; -+ -+ /* A compare of a mode narrower than SI mode against zero can be done -+ by extending the value in the comparison. */ -+ if ((GET_MODE (x) == QImode || GET_MODE (x) == HImode) -+ && y == const0_rtx) -+ /* Only use sign-extension if we really need it. */ -+ return ((code == GT || code == GE || code == LE || code == LT) -+ ? CC_SESWPmode : CC_ZESWPmode); -+ -+ /* For everything else, return CCmode. */ -+ return CCmode; -+} -+ -+static unsigned -+aarch64_get_condition_code (rtx x) -+{ -+ enum machine_mode mode = GET_MODE (XEXP (x, 0)); -+ enum rtx_code comp_code = GET_CODE (x); -+ -+ if (GET_MODE_CLASS (mode) != MODE_CC) -+ mode = SELECT_CC_MODE (comp_code, XEXP (x, 0), XEXP (x, 1)); -+ -+ switch (mode) -+ { -+ case CCFPmode: -+ case CCFPEmode: -+ switch (comp_code) -+ { -+ case GE: return AARCH64_GE; -+ case GT: return AARCH64_GT; -+ case LE: return AARCH64_LS; -+ case LT: return AARCH64_MI; -+ case NE: return AARCH64_NE; -+ case EQ: return AARCH64_EQ; -+ case ORDERED: return AARCH64_VC; -+ case UNORDERED: return AARCH64_VS; -+ case UNLT: return AARCH64_LT; -+ case UNLE: return AARCH64_LE; -+ case UNGT: return AARCH64_HI; -+ case UNGE: return AARCH64_PL; -+ default: gcc_unreachable (); -+ } -+ break; -+ -+ case CCmode: -+ switch (comp_code) -+ { -+ case NE: return AARCH64_NE; -+ case EQ: return AARCH64_EQ; -+ case GE: return AARCH64_GE; -+ case GT: return AARCH64_GT; -+ case LE: return AARCH64_LE; -+ case LT: return AARCH64_LT; -+ case GEU: return AARCH64_CS; -+ case GTU: return AARCH64_HI; -+ case LEU: return AARCH64_LS; -+ case LTU: return AARCH64_CC; -+ default: gcc_unreachable (); -+ } -+ break; -+ -+ case CC_SWPmode: -+ case CC_ZESWPmode: -+ case CC_SESWPmode: -+ switch (comp_code) -+ { -+ case NE: return AARCH64_NE; -+ case EQ: return AARCH64_EQ; -+ case GE: return AARCH64_LE; -+ case GT: return AARCH64_LT; -+ case LE: return AARCH64_GE; -+ case LT: return AARCH64_GT; -+ case GEU: return AARCH64_LS; -+ case GTU: return AARCH64_CC; -+ case LEU: return AARCH64_CS; -+ case LTU: return AARCH64_HI; -+ default: gcc_unreachable (); -+ } -+ break; -+ -+ case CC_NZmode: -+ switch (comp_code) -+ { -+ case NE: return AARCH64_NE; -+ case EQ: return AARCH64_EQ; -+ case GE: return AARCH64_PL; -+ case LT: return AARCH64_MI; -+ default: gcc_unreachable (); -+ } -+ break; -+ -+ default: -+ gcc_unreachable (); -+ break; -+ } -+} -+ -+static unsigned -+bit_count (unsigned HOST_WIDE_INT value) -+{ -+ unsigned count = 0; -+ -+ while (value) -+ { -+ count++; -+ value &= value - 1; -+ } -+ -+ return count; -+} -+ -+void -+aarch64_print_operand (FILE *f, rtx x, char code) -+{ -+ switch (code) -+ { -+ case 'e': -+ /* Print the sign/zero-extend size as a character 8->b, 16->h, 32->w. */ -+ { -+ int n; -+ -+ if (GET_CODE (x) != CONST_INT -+ || (n = exact_log2 (INTVAL (x) & ~7)) <= 0) -+ { -+ output_operand_lossage ("invalid operand for '%%%c'", code); -+ return; -+ } -+ -+ switch (n) -+ { -+ case 3: -+ fputc ('b', f); -+ break; -+ case 4: -+ fputc ('h', f); -+ break; -+ case 5: -+ fputc ('w', f); -+ break; -+ default: -+ output_operand_lossage ("invalid operand for '%%%c'", code); -+ return; -+ } -+ } -+ break; -+ -+ case 'p': -+ { -+ int n; -+ -+ /* Print N such that 2^N == X. */ -+ if (GET_CODE (x) != CONST_INT || (n = exact_log2 (INTVAL (x))) < 0) -+ { -+ output_operand_lossage ("invalid operand for '%%%c'", code); -+ return; -+ } -+ -+ asm_fprintf (f, "%d", n); -+ } -+ break; -+ -+ case 'P': -+ /* Print the number of non-zero bits in X (a const_int). */ -+ if (GET_CODE (x) != CONST_INT) -+ { -+ output_operand_lossage ("invalid operand for '%%%c'", code); -+ return; -+ } -+ -+ asm_fprintf (f, "%u", bit_count (INTVAL (x))); -+ break; -+ -+ case 'H': -+ /* Print the higher numbered register of a pair (TImode) of regs. */ -+ if (GET_CODE (x) != REG || !GP_REGNUM_P (REGNO (x) + 1)) -+ { -+ output_operand_lossage ("invalid operand for '%%%c'", code); -+ return; -+ } -+ -+ asm_fprintf (f, "%r", REGNO (x) + 1); -+ break; -+ -+ case 'Q': -+ /* Print the least significant register of a pair (TImode) of regs. */ -+ if (GET_CODE (x) != REG || !GP_REGNUM_P (REGNO (x) + 1)) -+ { -+ output_operand_lossage ("invalid operand for '%%%c'", code); -+ return; -+ } -+ asm_fprintf (f, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)); -+ break; -+ -+ case 'R': -+ /* Print the most significant register of a pair (TImode) of regs. */ -+ if (GET_CODE (x) != REG || !GP_REGNUM_P (REGNO (x) + 1)) -+ { -+ output_operand_lossage ("invalid operand for '%%%c'", code); -+ return; -+ } -+ asm_fprintf (f, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)); -+ break; -+ -+ case 'm': -+ /* Print a condition (eq, ne, etc). */ -+ -+ /* CONST_TRUE_RTX means always -- that's the default. */ -+ if (x == const_true_rtx) -+ return; -+ -+ if (!COMPARISON_P (x)) -+ { -+ output_operand_lossage ("invalid operand for '%%%c'", code); -+ return; -+ } -+ -+ fputs (aarch64_condition_codes[aarch64_get_condition_code (x)], f); -+ break; -+ -+ case 'M': -+ /* Print the inverse of a condition (eq <-> ne, etc). */ -+ -+ /* CONST_TRUE_RTX means never -- that's the default. */ -+ if (x == const_true_rtx) -+ { -+ fputs ("nv", f); -+ return; -+ } -+ -+ if (!COMPARISON_P (x)) -+ { -+ output_operand_lossage ("invalid operand for '%%%c'", code); -+ return; -+ } -+ -+ fputs (aarch64_condition_codes[AARCH64_INVERSE_CONDITION_CODE -+ (aarch64_get_condition_code (x))], f); -+ break; -+ -+ case 'b': -+ case 'h': -+ case 's': -+ case 'd': -+ case 'q': -+ /* Print a scalar FP/SIMD register name. */ -+ if (!REG_P (x) || !FP_REGNUM_P (REGNO (x))) -+ { -+ output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code); -+ return; -+ } -+ asm_fprintf (f, "%s%c%d", REGISTER_PREFIX, code, REGNO (x) - V0_REGNUM); -+ break; -+ -+ case 'w': -+ case 'x': -+ /* Print a general register name or the zero register (32-bit or -+ 64-bit). */ -+ if (x == const0_rtx) -+ { -+ asm_fprintf (f, "%s%czr", REGISTER_PREFIX, code); -+ break; -+ } -+ -+ if (REG_P (x) && GP_REGNUM_P (REGNO (x))) -+ { -+ asm_fprintf (f, "%s%c%d", REGISTER_PREFIX, code, -+ REGNO (x) - R0_REGNUM); -+ break; -+ } -+ -+ if (REG_P (x) && REGNO (x) == SP_REGNUM) -+ { -+ asm_fprintf (f, "%s%ssp", REGISTER_PREFIX, code == 'w' ? "w" : ""); -+ break; -+ } -+ -+ /* Fall through */ -+ -+ case 0: -+ /* Print a normal operand, if it's a general register, then we -+ assume DImode. */ -+ if (x == NULL) -+ { -+ output_operand_lossage ("missing operand"); -+ return; -+ } -+ -+ switch (GET_CODE (x)) -+ { -+ case REG: -+ asm_fprintf (f, "%r", REGNO (x)); -+ break; -+ -+ case MEM: -+ aarch64_memory_reference_mode = GET_MODE (x); -+ output_address (XEXP (x, 0)); -+ break; -+ -+ case LABEL_REF: -+ case SYMBOL_REF: -+ output_addr_const (asm_out_file, x); -+ break; -+ -+ case CONST_INT: -+ asm_fprintf (f, "%wd", INTVAL (x)); -+ break; -+ -+ case CONST_VECTOR: -+ gcc_assert (aarch64_const_vec_all_same_int_p (x, HOST_WIDE_INT_MIN, -+ HOST_WIDE_INT_MAX)); -+ asm_fprintf (f, "%wd", INTVAL (CONST_VECTOR_ELT (x, 0))); -+ break; -+ -+ default: -+ output_operand_lossage ("invalid operand"); -+ return; -+ } -+ break; -+ -+ case 'A': -+ if (GET_CODE (x) == HIGH) -+ x = XEXP (x, 0); -+ -+ switch (aarch64_classify_symbolic_expression (x, SYMBOL_CONTEXT_ADR)) -+ { -+ case SYMBOL_SMALL_GOT: -+ asm_fprintf (asm_out_file, ":got:"); -+ break; -+ -+ case SYMBOL_SMALL_TLSGD: -+ asm_fprintf (asm_out_file, ":tlsgd:"); -+ break; -+ -+ case SYMBOL_SMALL_TLSDESC: -+ asm_fprintf (asm_out_file, ":tlsdesc:"); -+ break; -+ -+ case SYMBOL_SMALL_GOTTPREL: -+ asm_fprintf (asm_out_file, ":gottprel:"); -+ break; -+ -+ case SYMBOL_SMALL_TPREL: -+ asm_fprintf (asm_out_file, ":tprel:"); -+ break; -+ -+ default: -+ break; -+ } -+ output_addr_const (asm_out_file, x); -+ break; -+ -+ case 'L': -+ switch (aarch64_classify_symbolic_expression (x, SYMBOL_CONTEXT_ADR)) -+ { -+ case SYMBOL_SMALL_GOT: -+ asm_fprintf (asm_out_file, ":lo12:"); -+ break; -+ -+ case SYMBOL_SMALL_TLSGD: -+ asm_fprintf (asm_out_file, ":tlsgd_lo12:"); -+ break; -+ -+ case SYMBOL_SMALL_TLSDESC: -+ asm_fprintf (asm_out_file, ":tlsdesc_lo12:"); -+ break; -+ -+ case SYMBOL_SMALL_GOTTPREL: -+ asm_fprintf (asm_out_file, ":gottprel_lo12:"); -+ break; -+ -+ case SYMBOL_SMALL_TPREL: -+ asm_fprintf (asm_out_file, ":tprel_lo12_nc:"); -+ break; -+ -+ default: -+ break; -+ } -+ output_addr_const (asm_out_file, x); -+ break; -+ -+ case 'G': -+ -+ switch (aarch64_classify_symbolic_expression (x, SYMBOL_CONTEXT_ADR)) -+ { -+ case SYMBOL_SMALL_TPREL: -+ asm_fprintf (asm_out_file, ":tprel_hi12:"); -+ break; -+ default: -+ break; -+ } -+ output_addr_const (asm_out_file, x); -+ break; -+ -+ default: -+ output_operand_lossage ("invalid operand prefix '%%%c'", code); -+ return; -+ } -+} -+ -+void -+aarch64_print_operand_address (FILE *f, rtx x) -+{ -+ struct aarch64_address_info addr; -+ -+ if (aarch64_classify_address (&addr, x, aarch64_memory_reference_mode, -+ MEM, true)) -+ switch (addr.type) -+ { -+ case ADDRESS_REG_IMM: -+ if (addr.offset == const0_rtx) -+ asm_fprintf (f, "[%r]", REGNO (addr.base)); -+ else -+ asm_fprintf (f, "[%r,%wd]", REGNO (addr.base), -+ INTVAL (addr.offset)); -+ return; -+ -+ case ADDRESS_REG_REG: -+ if (addr.shift == 0) -+ asm_fprintf (f, "[%r,%r]", REGNO (addr.base), -+ REGNO (addr.offset)); -+ else -+ asm_fprintf (f, "[%r,%r,lsl %u]", REGNO (addr.base), -+ REGNO (addr.offset), addr.shift); -+ return; -+ -+ case ADDRESS_REG_UXTW: -+ if (addr.shift == 0) -+ asm_fprintf (f, "[%r,w%d,uxtw]", REGNO (addr.base), -+ REGNO (addr.offset) - R0_REGNUM); -+ else -+ asm_fprintf (f, "[%r,w%d,uxtw %u]", REGNO (addr.base), -+ REGNO (addr.offset) - R0_REGNUM, addr.shift); -+ return; -+ -+ case ADDRESS_REG_SXTW: -+ if (addr.shift == 0) -+ asm_fprintf (f, "[%r,w%d,sxtw]", REGNO (addr.base), -+ REGNO (addr.offset) - R0_REGNUM); -+ else -+ asm_fprintf (f, "[%r,w%d,sxtw %u]", REGNO (addr.base), -+ REGNO (addr.offset) - R0_REGNUM, addr.shift); -+ return; -+ -+ case ADDRESS_REG_WB: -+ switch (GET_CODE (x)) -+ { -+ case PRE_INC: -+ asm_fprintf (f, "[%r,%d]!", REGNO (addr.base), -+ GET_MODE_SIZE (aarch64_memory_reference_mode)); -+ return; -+ case POST_INC: -+ asm_fprintf (f, "[%r],%d", REGNO (addr.base), -+ GET_MODE_SIZE (aarch64_memory_reference_mode)); -+ return; -+ case PRE_DEC: -+ asm_fprintf (f, "[%r,-%d]!", REGNO (addr.base), -+ GET_MODE_SIZE (aarch64_memory_reference_mode)); -+ return; -+ case POST_DEC: -+ asm_fprintf (f, "[%r],-%d", REGNO (addr.base), -+ GET_MODE_SIZE (aarch64_memory_reference_mode)); -+ return; -+ case PRE_MODIFY: -+ asm_fprintf (f, "[%r,%wd]!", REGNO (addr.base), -+ INTVAL (addr.offset)); -+ return; -+ case POST_MODIFY: -+ asm_fprintf (f, "[%r],%wd", REGNO (addr.base), -+ INTVAL (addr.offset)); -+ return; -+ default: -+ break; -+ } -+ break; -+ -+ case ADDRESS_LO_SUM: -+ asm_fprintf (f, "[%r,#:lo12:", REGNO (addr.base)); -+ output_addr_const (f, addr.offset); -+ asm_fprintf (f, "]"); -+ return; -+ -+ case ADDRESS_SYMBOLIC: -+ break; -+ } -+ -+ output_addr_const (f, x); -+} -+ -+void -+aarch64_function_profiler (FILE *f ATTRIBUTE_UNUSED, -+ int labelno ATTRIBUTE_UNUSED) -+{ -+ sorry ("function profiling"); -+} -+ -+bool -+aarch64_label_mentioned_p (rtx x) -+{ -+ const char *fmt; -+ int i; -+ -+ if (GET_CODE (x) == LABEL_REF) -+ return true; -+ -+ /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the -+ referencing instruction, but they are constant offsets, not -+ symbols. */ -+ if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS) -+ return false; -+ -+ fmt = GET_RTX_FORMAT (GET_CODE (x)); -+ for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) -+ { -+ if (fmt[i] == 'E') -+ { -+ int j; -+ -+ for (j = XVECLEN (x, i) - 1; j >= 0; j--) -+ if (aarch64_label_mentioned_p (XVECEXP (x, i, j))) -+ return 1; -+ } -+ else if (fmt[i] == 'e' && aarch64_label_mentioned_p (XEXP (x, i))) -+ return 1; -+ } -+ -+ return 0; -+} -+ -+/* Implement REGNO_REG_CLASS. */ -+ -+unsigned -+aarch64_regno_regclass (unsigned regno) -+{ -+ if (GP_REGNUM_P (regno)) -+ return CORE_REGS; -+ -+ if (regno == SP_REGNUM) -+ return STACK_REG; -+ -+ if (regno == FRAME_POINTER_REGNUM -+ || regno == ARG_POINTER_REGNUM) -+ return CORE_REGS; -+ -+ if (FP_REGNUM_P (regno)) -+ return FP_LO_REGNUM_P (regno) ? FP_LO_REGS : FP_REGS; -+ -+ return NO_REGS; -+} -+ -+/* Try a machine-dependent way of reloading an illegitimate address -+ operand. If we find one, push the reload and return the new rtx. */ -+ -+rtx -+aarch64_legitimize_reload_address (rtx *x_p, -+ enum machine_mode mode, -+ int opnum, int type, -+ int ind_levels ATTRIBUTE_UNUSED) -+{ -+ rtx x = *x_p; -+ -+ /* Do not allow mem (plus (reg, const)) if vector mode. */ -+ if (aarch64_vector_mode_supported_p (mode) -+ && GET_CODE (x) == PLUS -+ && REG_P (XEXP (x, 0)) -+ && CONST_INT_P (XEXP (x, 1))) -+ { -+ rtx orig_rtx = x; -+ x = copy_rtx (x); -+ push_reload (orig_rtx, NULL_RTX, x_p, NULL, -+ BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, -+ opnum, type); -+ return x; -+ } -+ -+ /* We must recognize output that we have already generated ourselves. */ -+ if (GET_CODE (x) == PLUS -+ && GET_CODE (XEXP (x, 0)) == PLUS -+ && REG_P (XEXP (XEXP (x, 0), 0)) -+ && CONST_INT_P (XEXP (XEXP (x, 0), 1)) -+ && CONST_INT_P (XEXP (x, 1))) -+ { -+ push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, -+ BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, -+ opnum, type); -+ return x; -+ } -+ -+ /* We wish to handle large displacements off a base register by splitting -+ the addend across an add and the mem insn. This can cut the number of -+ extra insns needed from 3 to 1. It is only useful for load/store of a -+ single register with 12 bit offset field. */ -+ if (GET_CODE (x) == PLUS -+ && REG_P (XEXP (x, 0)) -+ && CONST_INT_P (XEXP (x, 1)) -+ && HARD_REGISTER_P (XEXP (x, 0)) -+ && mode != TImode -+ && mode != TFmode -+ && aarch64_regno_ok_for_base_p (REGNO (XEXP (x, 0)), true)) -+ { -+ HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); -+ HOST_WIDE_INT low = val & 0xfff; -+ HOST_WIDE_INT high = val - low; -+ HOST_WIDE_INT offs; -+ rtx cst; -+ -+ /* Reload non-zero BLKmode offsets. This is because we cannot ascertain -+ BLKmode alignment. */ -+ if (GET_MODE_SIZE (mode) == 0) -+ return NULL_RTX; -+ -+ offs = low % GET_MODE_SIZE (mode); -+ -+ /* Align misaligned offset by adjusting high part to compensate. */ -+ if (offs != 0) -+ { -+ if (aarch64_uimm12_shift (high + offs)) -+ { -+ /* Align down. */ -+ low = low - offs; -+ high = high + offs; -+ } -+ else -+ { -+ /* Align up. */ -+ offs = GET_MODE_SIZE (mode) - offs; -+ low = low + offs; -+ high = high + (low & 0x1000) - offs; -+ low &= 0xfff; -+ } -+ } -+ -+ /* Check for overflow. */ -+ if (high + low != val) -+ return NULL_RTX; -+ -+ cst = GEN_INT (high); -+ if (!aarch64_uimm12_shift (high)) -+ cst = force_const_mem (Pmode, cst); -+ -+ /* Reload high part into base reg, leaving the low part -+ in the mem instruction. */ -+ x = gen_rtx_PLUS (Pmode, -+ gen_rtx_PLUS (Pmode, XEXP (x, 0), cst), -+ GEN_INT (low)); -+ -+ push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, -+ BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, -+ opnum, type); -+ return x; -+ } -+ -+ return NULL_RTX; -+} -+ -+ -+static reg_class_t -+aarch64_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x, -+ reg_class_t rclass, -+ enum machine_mode mode, -+ secondary_reload_info *sri) -+{ -+ /* Address expressions of the form PLUS (SP, large_offset) need two -+ scratch registers, one for the constant, and one for holding a -+ copy of SP, since SP cannot be used on the RHS of an add-reg -+ instruction. */ -+ if (mode == DImode -+ && GET_CODE (x) == PLUS -+ && XEXP (x, 0) == stack_pointer_rtx -+ && CONST_INT_P (XEXP (x, 1)) -+ && !aarch64_uimm12_shift (INTVAL (XEXP (x, 1)))) -+ { -+ sri->icode = CODE_FOR_reload_sp_immediate; -+ return NO_REGS; -+ } -+ -+ /* Without the TARGET_SIMD instructions we cannot move a Q register -+ to a Q register directly. We need a scratch. */ -+ if (REG_P (x) && (mode == TFmode || mode == TImode) && mode == GET_MODE (x) -+ && FP_REGNUM_P (REGNO (x)) && !TARGET_SIMD -+ && reg_class_subset_p (rclass, FP_REGS)) -+ { -+ if (mode == TFmode) -+ sri->icode = CODE_FOR_aarch64_reload_movtf; -+ else if (mode == TImode) -+ sri->icode = CODE_FOR_aarch64_reload_movti; -+ return NO_REGS; -+ } -+ -+ /* A TFmode or TImode memory access should be handled via an FP_REGS -+ because AArch64 has richer addressing modes for LDR/STR instructions -+ than LDP/STP instructions. */ -+ if (!TARGET_GENERAL_REGS_ONLY && rclass == CORE_REGS -+ && GET_MODE_SIZE (mode) == 16 && MEM_P (x)) -+ return FP_REGS; -+ -+ if ((mode == TImode || mode == TFmode) && CONSTANT_P(x) -+ && reg_class_subset_p (rclass, FP_REGS)) -+ return CORE_REGS; -+ -+ return NO_REGS; -+} -+ -+static bool -+aarch64_can_eliminate (const int from, const int to) -+{ -+ /* If we need a frame pointer, we must eliminate FRAME_POINTER_REGNUM into -+ HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */ -+ -+ if (frame_pointer_needed) -+ { -+ if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) -+ return true; -+ if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) -+ return false; -+ if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM -+ && !cfun->calls_alloca) -+ return true; -+ if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) -+ return true; -+ return false; -+ } -+ else -+ { -+ /* If we decided that we didn't need a frame pointer but then used -+ LR in the function, then we do need a frame pointer after all, so -+ prevent this elimination to ensure a frame pointer is used. */ -+ -+ if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM -+ && df_regs_ever_live_p (LR_REGNUM)) -+ return false; -+ } -+ return true; -+} -+ -+HOST_WIDE_INT -+aarch64_initial_elimination_offset (unsigned from, unsigned to) -+{ -+ HOST_WIDE_INT frame_size; -+ HOST_WIDE_INT offset; -+ -+ aarch64_layout_frame (); -+ frame_size = (get_frame_size () + cfun->machine->frame.saved_regs_size -+ + crtl->outgoing_args_size -+ + cfun->machine->saved_varargs_size); -+ -+ frame_size = AARCH64_ROUND_UP (frame_size, STACK_BOUNDARY / BITS_PER_UNIT); -+ offset = frame_size; -+ -+ if (to == HARD_FRAME_POINTER_REGNUM) -+ { -+ if (from == ARG_POINTER_REGNUM) -+ return offset - crtl->outgoing_args_size; -+ -+ if (from == FRAME_POINTER_REGNUM) -+ return cfun->machine->frame.saved_regs_size; -+ } -+ -+ if (to == STACK_POINTER_REGNUM) -+ { -+ if (from == FRAME_POINTER_REGNUM) -+ { -+ HOST_WIDE_INT elim = crtl->outgoing_args_size -+ + cfun->machine->frame.saved_regs_size -+ - cfun->machine->frame.fp_lr_offset; -+ elim = AARCH64_ROUND_UP (elim, STACK_BOUNDARY / BITS_PER_UNIT); -+ return elim; -+ } -+ } -+ -+ return offset; -+} -+ -+ -+/* Implement RETURN_ADDR_RTX. We do not support moving back to a -+ previous frame. */ -+ -+rtx -+aarch64_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) -+{ -+ if (count != 0) -+ return const0_rtx; -+ return get_hard_reg_initial_val (Pmode, LR_REGNUM); -+} -+ -+ -+static void -+aarch64_asm_trampoline_template (FILE *f) -+{ -+ asm_fprintf (f, "\tldr\t%r, .+16\n", IP1_REGNUM); -+ asm_fprintf (f, "\tldr\t%r, .+20\n", STATIC_CHAIN_REGNUM); -+ asm_fprintf (f, "\tbr\t%r\n", IP1_REGNUM); -+ assemble_aligned_integer (4, const0_rtx); -+ assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); -+ assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); -+} -+ -+unsigned -+aarch64_trampoline_size (void) -+{ -+ return 32; /* 3 insns + padding + 2 dwords. */ -+} -+ -+static void -+aarch64_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) -+{ -+ rtx fnaddr, mem, a_tramp; -+ -+ /* Don't need to copy the trailing D-words, we fill those in below. */ -+ emit_block_move (m_tramp, assemble_trampoline_template (), -+ GEN_INT (TRAMPOLINE_SIZE - 16), BLOCK_OP_NORMAL); -+ mem = adjust_address (m_tramp, DImode, 16); -+ fnaddr = XEXP (DECL_RTL (fndecl), 0); -+ emit_move_insn (mem, fnaddr); -+ -+ mem = adjust_address (m_tramp, DImode, 24); -+ emit_move_insn (mem, chain_value); -+ -+ /* XXX We should really define a "clear_cache" pattern and use -+ gen_clear_cache(). */ -+ a_tramp = XEXP (m_tramp, 0); -+ emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), -+ 0, VOIDmode, 2, a_tramp, Pmode, -+ plus_constant (a_tramp, TRAMPOLINE_SIZE), Pmode); -+} -+ -+static unsigned char -+aarch64_class_max_nregs (reg_class_t regclass, enum machine_mode mode) -+{ -+ switch (regclass) -+ { -+ case CORE_REGS: -+ case POINTER_REGS: -+ case GENERAL_REGS: -+ case ALL_REGS: -+ case FP_REGS: -+ case FP_LO_REGS: -+ return (GET_MODE_SIZE (mode) + 7) / 8; -+ -+ case STACK_REG: -+ return 1; -+ -+ case NO_REGS: -+ return 0; -+ -+ default: -+ break; -+ } -+ gcc_unreachable (); -+} -+ -+static reg_class_t -+aarch64_preferred_reload_class (rtx x ATTRIBUTE_UNUSED, reg_class_t regclass) -+{ -+ return ((regclass == POINTER_REGS || regclass == STACK_REG) -+ ? GENERAL_REGS : regclass); -+} -+ -+void -+aarch64_asm_output_labelref (FILE* f, const char *name) -+{ -+ asm_fprintf (f, "%U%s", name); -+} -+ -+static void -+aarch64_elf_asm_constructor (rtx symbol, int priority) -+{ -+ if (priority == DEFAULT_INIT_PRIORITY) -+ default_ctor_section_asm_out_constructor (symbol, priority); -+ else -+ { -+ section *s; -+ char buf[18]; -+ snprintf (buf, sizeof (buf), ".init_array.%.5u", priority); -+ s = get_section (buf, SECTION_WRITE, NULL); -+ switch_to_section (s); -+ assemble_align (POINTER_SIZE); -+ fputs ("\t.dword\t", asm_out_file); -+ output_addr_const (asm_out_file, symbol); -+ fputc ('\n', asm_out_file); -+ } -+} -+ -+static void -+aarch64_elf_asm_destructor (rtx symbol, int priority) -+{ -+ if (priority == DEFAULT_INIT_PRIORITY) -+ default_dtor_section_asm_out_destructor (symbol, priority); -+ else -+ { -+ section *s; -+ char buf[18]; -+ snprintf (buf, sizeof (buf), ".fini_array.%.5u", priority); -+ s = get_section (buf, SECTION_WRITE, NULL); -+ switch_to_section (s); -+ assemble_align (POINTER_SIZE); -+ fputs ("\t.dword\t", asm_out_file); -+ output_addr_const (asm_out_file, symbol); -+ fputc ('\n', asm_out_file); -+ } -+} -+ -+const char* -+aarch64_output_casesi (rtx *operands) -+{ -+ char buf[100]; -+ char label[100]; -+ rtx diff_vec = PATTERN (next_real_insn (operands[2])); -+ int index; -+ static const char *const patterns[4][2] = -+ { -+ { -+ "ldrb\t%w3, [%0,%w1,uxtw]", -+ "add\t%3, %4, %w3, sxtb #2" -+ }, -+ { -+ "ldrh\t%w3, [%0,%w1,uxtw #1]", -+ "add\t%3, %4, %w3, sxth #2" -+ }, -+ { -+ "ldr\t%w3, [%0,%w1,uxtw #2]", -+ "add\t%3, %4, %w3, sxtw #2" -+ }, -+ /* We assume that DImode is only generated when not optimizing and -+ that we don't really need 64-bit address offsets. That would -+ imply an object file with 8GB of code in a single function! */ -+ { -+ "ldr\t%w3, [%0,%w1,uxtw #2]", -+ "add\t%3, %4, %w3, sxtw #2" -+ } -+ }; -+ -+ gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC); -+ -+ index = exact_log2 (GET_MODE_SIZE (GET_MODE (diff_vec))); -+ -+ gcc_assert (index >= 0 && index <= 3); -+ -+ /* Need to implement table size reduction, by chaning the code below. */ -+ output_asm_insn (patterns[index][0], operands); -+ ASM_GENERATE_INTERNAL_LABEL (label, "Lrtx", CODE_LABEL_NUMBER (operands[2])); -+ snprintf (buf, sizeof (buf), -+ "adr\t%%4, %s", targetm.strip_name_encoding (label)); -+ output_asm_insn (buf, operands); -+ output_asm_insn (patterns[index][1], operands); -+ output_asm_insn ("br\t%3", operands); -+ assemble_label (asm_out_file, label); -+ return ""; -+} -+ -+ -+/* Return size in bits of an arithmetic operand which is shifted/scaled and -+ masked such that it is suitable for a UXTB, UXTH, or UXTW extend -+ operator. */ -+ -+int -+aarch64_uxt_size (int shift, HOST_WIDE_INT mask) -+{ -+ if (shift >= 0 && shift <= 3) -+ { -+ int size; -+ for (size = 8; size <= 32; size *= 2) -+ { -+ HOST_WIDE_INT bits = ((HOST_WIDE_INT)1U << size) - 1; -+ if (mask == bits << shift) -+ return size; -+ } -+ } -+ return 0; -+} -+ -+static bool -+aarch64_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, -+ const_rtx x ATTRIBUTE_UNUSED) -+{ -+ /* We can't use blocks for constants when we're using a per-function -+ constant pool. */ -+ return false; -+} -+ -+static section * -+aarch64_select_rtx_section (enum machine_mode mode ATTRIBUTE_UNUSED, -+ rtx x ATTRIBUTE_UNUSED, -+ unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) -+{ -+ /* Force all constant pool entries into the current function section. */ -+ return function_section (current_function_decl); -+} -+ -+ -+/* Costs. */ -+ -+/* Helper function for rtx cost calculation. Strip a shift expression -+ from X. Returns the inner operand if successful, or the original -+ expression on failure. */ -+static rtx -+aarch64_strip_shift (rtx x) -+{ -+ rtx op = x; -+ -+ if ((GET_CODE (op) == ASHIFT -+ || GET_CODE (op) == ASHIFTRT -+ || GET_CODE (op) == LSHIFTRT) -+ && CONST_INT_P (XEXP (op, 1))) -+ return XEXP (op, 0); -+ -+ if (GET_CODE (op) == MULT -+ && CONST_INT_P (XEXP (op, 1)) -+ && ((unsigned) exact_log2 (INTVAL (XEXP (op, 1)))) < 64) -+ return XEXP (op, 0); -+ -+ return x; -+} -+ -+/* Helper function for rtx cost calculation. Strip a shift or extend -+ expression from X. Returns the inner operand if successful, or the -+ original expression on failure. We deal with a number of possible -+ canonicalization variations here. */ -+static rtx -+aarch64_strip_shift_or_extend (rtx x) -+{ -+ rtx op = x; -+ -+ /* Zero and sign extraction of a widened value. */ -+ if ((GET_CODE (op) == ZERO_EXTRACT || GET_CODE (op) == SIGN_EXTRACT) -+ && XEXP (op, 2) == const0_rtx -+ && aarch64_is_extend_from_extract (GET_MODE (op), XEXP (XEXP (op, 0), 1), -+ XEXP (op, 1))) -+ return XEXP (XEXP (op, 0), 0); -+ -+ /* It can also be represented (for zero-extend) as an AND with an -+ immediate. */ -+ if (GET_CODE (op) == AND -+ && GET_CODE (XEXP (op, 0)) == MULT -+ && CONST_INT_P (XEXP (XEXP (op, 0), 1)) -+ && CONST_INT_P (XEXP (op, 1)) -+ && aarch64_uxt_size (exact_log2 (INTVAL (XEXP (XEXP (op, 0), 1))), -+ INTVAL (XEXP (op, 1))) != 0) -+ return XEXP (XEXP (op, 0), 0); -+ -+ /* Now handle extended register, as this may also have an optional -+ left shift by 1..4. */ -+ if (GET_CODE (op) == ASHIFT -+ && CONST_INT_P (XEXP (op, 1)) -+ && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) <= 4) -+ op = XEXP (op, 0); -+ -+ if (GET_CODE (op) == ZERO_EXTEND -+ || GET_CODE (op) == SIGN_EXTEND) -+ op = XEXP (op, 0); -+ -+ if (op != x) -+ return op; -+ -+ return aarch64_strip_shift (x); -+} -+ -+/* Calculate the cost of calculating X, storing it in *COST. Result -+ is true if the total cost of the operation has now been calculated. */ -+static bool -+aarch64_rtx_costs (rtx x, int code, int outer ATTRIBUTE_UNUSED, -+ int param ATTRIBUTE_UNUSED, int *cost, bool speed) -+{ -+ rtx op0, op1; -+ const struct cpu_rtx_cost_table *extra_cost -+ = aarch64_tune_params->insn_extra_cost; -+ -+ switch (code) -+ { -+ case SET: -+ op0 = SET_DEST (x); -+ op1 = SET_SRC (x); -+ -+ switch (GET_CODE (op0)) -+ { -+ case MEM: -+ if (speed) -+ *cost += extra_cost->memory_store; -+ -+ if (op1 != const0_rtx) -+ *cost += rtx_cost (op1, SET, 1, speed); -+ return true; -+ -+ case SUBREG: -+ if (! REG_P (SUBREG_REG (op0))) -+ *cost += rtx_cost (SUBREG_REG (op0), SET, 0, speed); -+ /* Fall through. */ -+ case REG: -+ /* Cost is just the cost of the RHS of the set. */ -+ *cost += rtx_cost (op1, SET, 1, true); -+ return true; -+ -+ case ZERO_EXTRACT: /* Bit-field insertion. */ -+ case SIGN_EXTRACT: -+ /* Strip any redundant widening of the RHS to meet the width of -+ the target. */ -+ if (GET_CODE (op1) == SUBREG) -+ op1 = SUBREG_REG (op1); -+ if ((GET_CODE (op1) == ZERO_EXTEND -+ || GET_CODE (op1) == SIGN_EXTEND) -+ && GET_CODE (XEXP (op0, 1)) == CONST_INT -+ && (GET_MODE_BITSIZE (GET_MODE (XEXP (op1, 0))) -+ >= INTVAL (XEXP (op0, 1)))) -+ op1 = XEXP (op1, 0); -+ *cost += rtx_cost (op1, SET, 1, speed); -+ return true; -+ -+ default: -+ break; -+ } -+ return false; -+ -+ case MEM: -+ if (speed) -+ *cost += extra_cost->memory_load; -+ -+ return true; -+ -+ case NEG: -+ op0 = CONST0_RTX (GET_MODE (x)); -+ op1 = XEXP (x, 0); -+ goto cost_minus; -+ -+ case COMPARE: -+ op0 = XEXP (x, 0); -+ op1 = XEXP (x, 1); -+ -+ if (op1 == const0_rtx -+ && GET_CODE (op0) == AND) -+ { -+ x = op0; -+ goto cost_logic; -+ } -+ -+ /* Comparisons can work if the order is swapped. -+ Canonicalization puts the more complex operation first, but -+ we want it in op1. */ -+ if (! (REG_P (op0) -+ || (GET_CODE (op0) == SUBREG && REG_P (SUBREG_REG (op0))))) -+ { -+ op0 = XEXP (x, 1); -+ op1 = XEXP (x, 0); -+ } -+ goto cost_minus; -+ -+ case MINUS: -+ op0 = XEXP (x, 0); -+ op1 = XEXP (x, 1); -+ -+ cost_minus: -+ if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT -+ || (GET_MODE_CLASS (GET_MODE (x)) == MODE_CC -+ && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)) -+ { -+ if (op0 != const0_rtx) -+ *cost += rtx_cost (op0, MINUS, 0, speed); -+ -+ if (CONST_INT_P (op1)) -+ { -+ if (!aarch64_uimm12_shift (INTVAL (op1))) -+ *cost += rtx_cost (op1, MINUS, 1, speed); -+ } -+ else -+ { -+ op1 = aarch64_strip_shift_or_extend (op1); -+ *cost += rtx_cost (op1, MINUS, 1, speed); -+ } -+ return true; -+ } -+ -+ return false; -+ -+ case PLUS: -+ op0 = XEXP (x, 0); -+ op1 = XEXP (x, 1); -+ -+ if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT) -+ { -+ if (CONST_INT_P (op1) && aarch64_uimm12_shift (INTVAL (op1))) -+ { -+ *cost += rtx_cost (op0, PLUS, 0, speed); -+ } -+ else -+ { -+ rtx new_op0 = aarch64_strip_shift_or_extend (op0); -+ -+ if (new_op0 == op0 -+ && GET_CODE (op0) == MULT) -+ { -+ if ((GET_CODE (XEXP (op0, 0)) == ZERO_EXTEND -+ && GET_CODE (XEXP (op0, 1)) == ZERO_EXTEND) -+ || (GET_CODE (XEXP (op0, 0)) == SIGN_EXTEND -+ && GET_CODE (XEXP (op0, 1)) == SIGN_EXTEND)) -+ { -+ *cost += (rtx_cost (XEXP (XEXP (op0, 0), 0), MULT, 0, -+ speed) -+ + rtx_cost (XEXP (XEXP (op0, 1), 0), MULT, 1, -+ speed) -+ + rtx_cost (op1, PLUS, 1, speed)); -+ if (speed) -+ *cost += extra_cost->int_multiply_extend_add; -+ return true; -+ } -+ *cost += (rtx_cost (XEXP (op0, 0), MULT, 0, speed) -+ + rtx_cost (XEXP (op0, 1), MULT, 1, speed) -+ + rtx_cost (op1, PLUS, 1, speed)); -+ -+ if (speed) -+ *cost += extra_cost->int_multiply_add; -+ } -+ -+ *cost += (rtx_cost (new_op0, PLUS, 0, speed) -+ + rtx_cost (op1, PLUS, 1, speed)); -+ } -+ return true; -+ } -+ -+ return false; -+ -+ case IOR: -+ case XOR: -+ case AND: -+ cost_logic: -+ op0 = XEXP (x, 0); -+ op1 = XEXP (x, 1); -+ -+ if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT) -+ { -+ if (CONST_INT_P (op1) -+ && aarch64_bitmask_imm (INTVAL (op1), GET_MODE (x))) -+ { -+ *cost += rtx_cost (op0, AND, 0, speed); -+ } -+ else -+ { -+ if (GET_CODE (op0) == NOT) -+ op0 = XEXP (op0, 0); -+ op0 = aarch64_strip_shift (op0); -+ *cost += (rtx_cost (op0, AND, 0, speed) -+ + rtx_cost (op1, AND, 1, speed)); -+ } -+ return true; -+ } -+ return false; -+ -+ case ZERO_EXTEND: -+ if ((GET_MODE (x) == DImode -+ && GET_MODE (XEXP (x, 0)) == SImode) -+ || GET_CODE (XEXP (x, 0)) == MEM) -+ { -+ *cost += rtx_cost (XEXP (x, 0), ZERO_EXTEND, 0, speed); -+ return true; -+ } -+ return false; -+ -+ case SIGN_EXTEND: -+ if (GET_CODE (XEXP (x, 0)) == MEM) -+ { -+ *cost += rtx_cost (XEXP (x, 0), SIGN_EXTEND, 0, speed); -+ return true; -+ } -+ return false; -+ -+ case ROTATE: -+ if (!CONST_INT_P (XEXP (x, 1))) -+ *cost += COSTS_N_INSNS (2); -+ /* Fall through. */ -+ case ROTATERT: -+ case LSHIFTRT: -+ case ASHIFT: -+ case ASHIFTRT: -+ -+ /* Shifting by a register often takes an extra cycle. */ -+ if (speed && !CONST_INT_P (XEXP (x, 1))) -+ *cost += extra_cost->register_shift; -+ -+ *cost += rtx_cost (XEXP (x, 0), ASHIFT, 0, speed); -+ return true; -+ -+ case HIGH: -+ if (!CONSTANT_P (XEXP (x, 0))) -+ *cost += rtx_cost (XEXP (x, 0), HIGH, 0, speed); -+ return true; -+ -+ case LO_SUM: -+ if (!CONSTANT_P (XEXP (x, 1))) -+ *cost += rtx_cost (XEXP (x, 1), LO_SUM, 1, speed); -+ *cost += rtx_cost (XEXP (x, 0), LO_SUM, 0, speed); -+ return true; -+ -+ case ZERO_EXTRACT: -+ case SIGN_EXTRACT: -+ *cost += rtx_cost (XEXP (x, 0), ZERO_EXTRACT, 0, speed); -+ return true; -+ -+ case MULT: -+ op0 = XEXP (x, 0); -+ op1 = XEXP (x, 1); -+ -+ *cost = COSTS_N_INSNS (1); -+ if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT) -+ { -+ if (CONST_INT_P (op1) -+ && exact_log2 (INTVAL (op1)) > 0) -+ { -+ *cost += rtx_cost (op0, ASHIFT, 0, speed); -+ return true; -+ } -+ -+ if ((GET_CODE (op0) == ZERO_EXTEND -+ && GET_CODE (op1) == ZERO_EXTEND) -+ || (GET_CODE (op0) == SIGN_EXTEND -+ && GET_CODE (op1) == SIGN_EXTEND)) -+ { -+ *cost += (rtx_cost (XEXP (op0, 0), MULT, 0, speed) -+ + rtx_cost (XEXP (op1, 0), MULT, 1, speed)); -+ if (speed) -+ *cost += extra_cost->int_multiply_extend; -+ return true; -+ } -+ -+ if (speed) -+ *cost += extra_cost->int_multiply; -+ } -+ else if (speed) -+ { -+ if (GET_MODE (x) == DFmode) -+ *cost += extra_cost->double_multiply; -+ else if (GET_MODE (x) == SFmode) -+ *cost += extra_cost->float_multiply; -+ } -+ -+ return false; /* All arguments need to be in registers. */ -+ -+ case MOD: -+ case UMOD: -+ *cost = COSTS_N_INSNS (2); -+ if (speed) -+ { -+ if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT) -+ *cost += (extra_cost->int_multiply_add -+ + extra_cost->int_divide); -+ else if (GET_MODE (x) == DFmode) -+ *cost += (extra_cost->double_multiply -+ + extra_cost->double_divide); -+ else if (GET_MODE (x) == SFmode) -+ *cost += (extra_cost->float_multiply -+ + extra_cost->float_divide); -+ } -+ return false; /* All arguments need to be in registers. */ -+ -+ case DIV: -+ case UDIV: -+ *cost = COSTS_N_INSNS (1); -+ if (speed) -+ { -+ if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT) -+ *cost += extra_cost->int_divide; -+ else if (GET_MODE (x) == DFmode) -+ *cost += extra_cost->double_divide; -+ else if (GET_MODE (x) == SFmode) -+ *cost += extra_cost->float_divide; -+ } -+ return false; /* All arguments need to be in registers. */ -+ -+ default: -+ break; -+ } -+ return false; -+} -+ -+static int -+aarch64_address_cost (rtx x ATTRIBUTE_UNUSED, bool speed ATTRIBUTE_UNUSED) -+{ -+ enum rtx_code c = GET_CODE (x); -+ const struct cpu_addrcost_table *addr_cost = aarch64_tune_params->addr_cost; -+ -+ if (c == PRE_INC || c == PRE_DEC || c == PRE_MODIFY) -+ return addr_cost->pre_modify; -+ -+ if (c == POST_INC || c == POST_DEC || c == POST_MODIFY) -+ return addr_cost->post_modify; -+ -+ if (c == PLUS) -+ { -+ if (GET_CODE (XEXP (x, 1)) == CONST_INT) -+ return addr_cost->imm_offset; -+ else if (GET_CODE (XEXP (x, 0)) == MULT -+ || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND -+ || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND) -+ return addr_cost->register_extend; -+ -+ return addr_cost->register_offset; -+ } -+ else if (c == MEM || c == LABEL_REF || c == SYMBOL_REF) -+ return addr_cost->imm_offset; -+ -+ return 0; -+} -+ -+static int -+aarch64_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, -+ reg_class_t from, reg_class_t to) -+{ -+ const struct cpu_regmove_cost *regmove_cost -+ = aarch64_tune_params->regmove_cost; -+ -+ if (from == GENERAL_REGS && to == GENERAL_REGS) -+ return regmove_cost->GP2GP; -+ else if (from == GENERAL_REGS) -+ return regmove_cost->GP2FP; -+ else if (to == GENERAL_REGS) -+ return regmove_cost->FP2GP; -+ -+ /* When AdvSIMD instructions are disabled it is not possible to move -+ a 128-bit value directly between Q registers. This is handled in -+ secondary reload. A general register is used as a scratch to move -+ the upper DI value and the lower DI value is moved directly, -+ hence the cost is the sum of three moves. */ -+ -+ if (! TARGET_SIMD && GET_MODE_SIZE (from) == 128 && GET_MODE_SIZE (to) == 128) -+ return regmove_cost->GP2FP + regmove_cost->FP2GP + regmove_cost->FP2FP; -+ -+ return regmove_cost->FP2FP; -+} -+ -+static int -+aarch64_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, -+ reg_class_t rclass ATTRIBUTE_UNUSED, -+ bool in ATTRIBUTE_UNUSED) -+{ -+ return aarch64_tune_params->memmov_cost; -+} -+ -+static void initialize_aarch64_code_model (void); -+ -+/* Tuning parameters. */ -+ -+#if HAVE_DESIGNATED_INITIALIZERS -+#define NAMED_PARAM(NAME, VAL) .NAME = (VAL) -+#else -+#define NAMED_PARAM(NAME, VAL) (VAL) -+#endif -+ -+#if HAVE_DESIGNATED_INITIALIZERS && GCC_VERSION >= 2007 -+__extension__ -+#endif -+static const struct cpu_rtx_cost_table generic_rtx_cost_table = -+{ -+ NAMED_PARAM (memory_load, COSTS_N_INSNS (1)), -+ NAMED_PARAM (memory_store, COSTS_N_INSNS (0)), -+ NAMED_PARAM (register_shift, COSTS_N_INSNS (1)), -+ NAMED_PARAM (int_divide, COSTS_N_INSNS (6)), -+ NAMED_PARAM (float_divide, COSTS_N_INSNS (2)), -+ NAMED_PARAM (double_divide, COSTS_N_INSNS (6)), -+ NAMED_PARAM (int_multiply, COSTS_N_INSNS (1)), -+ NAMED_PARAM (int_multiply_extend, COSTS_N_INSNS (1)), -+ NAMED_PARAM (int_multiply_add, COSTS_N_INSNS (1)), -+ NAMED_PARAM (int_multiply_extend_add, COSTS_N_INSNS (1)), -+ NAMED_PARAM (float_multiply, COSTS_N_INSNS (0)), -+ NAMED_PARAM (double_multiply, COSTS_N_INSNS (1)) -+}; -+ -+#if HAVE_DESIGNATED_INITIALIZERS && GCC_VERSION >= 2007 -+__extension__ -+#endif -+static const struct cpu_addrcost_table generic_addrcost_table = -+{ -+ NAMED_PARAM (pre_modify, 0), -+ NAMED_PARAM (post_modify, 0), -+ NAMED_PARAM (register_offset, 0), -+ NAMED_PARAM (register_extend, 0), -+ NAMED_PARAM (imm_offset, 0) -+}; -+ -+#if HAVE_DESIGNATED_INITIALIZERS && GCC_VERSION >= 2007 -+__extension__ -+#endif -+static const struct cpu_regmove_cost generic_regmove_cost = -+{ -+ NAMED_PARAM (GP2GP, 1), -+ NAMED_PARAM (GP2FP, 2), -+ NAMED_PARAM (FP2GP, 2), -+ /* We currently do not provide direct support for TFmode Q->Q move. -+ Therefore we need to raise the cost above 2 in order to have -+ reload handle the situation. */ -+ NAMED_PARAM (FP2FP, 4) -+}; -+ -+#if HAVE_DESIGNATED_INITIALIZERS && GCC_VERSION >= 2007 -+__extension__ -+#endif -+static const struct tune_params generic_tunings = -+{ -+ &generic_rtx_cost_table, -+ &generic_addrcost_table, -+ &generic_regmove_cost, -+ NAMED_PARAM (memmov_cost, 4) -+}; -+ -+ -+/* Parse the architecture extension string. */ -+ -+static void -+aarch64_parse_extension (char *str) -+{ -+ /* The extension string is parsed left to right. */ -+ const struct aarch64_option_extension *opt = NULL; -+ -+ /* Flag to say whether we are adding or removing an extension. */ -+ int adding_ext = -1; -+ -+ while (str != NULL && *str != 0) -+ { -+ char *ext; -+ size_t len; -+ -+ str++; -+ ext = strchr (str, '+'); -+ -+ if (ext != NULL) -+ len = ext - str; -+ else -+ len = strlen (str); -+ -+ if (len >= 2 && strncmp (str, "no", 2) == 0) -+ { -+ adding_ext = 0; -+ len -= 2; -+ str += 2; -+ } -+ else if (len > 0) -+ adding_ext = 1; -+ -+ if (len == 0) -+ { -+ error ("missing feature modifier after %qs", "+no"); -+ return; -+ } -+ -+ /* Scan over the extensions table trying to find an exact match. */ -+ for (opt = all_extensions; opt->name != NULL; opt++) -+ { -+ if (strlen (opt->name) == len && strncmp (opt->name, str, len) == 0) -+ { -+ /* Add or remove the extension. */ -+ if (adding_ext) -+ aarch64_isa_flags |= opt->flags_on; -+ else -+ aarch64_isa_flags &= ~(opt->flags_off); -+ break; -+ } -+ } -+ -+ if (opt->name == NULL) -+ { -+ /* Extension not found in list. */ -+ error ("unknown feature modifier %qs", str); -+ return; -+ } -+ -+ str = ext; -+ }; -+ -+ return; -+} -+ -+/* Parse the ARCH string. */ -+ -+static void -+aarch64_parse_arch (void) -+{ -+ char *ext; -+ const struct processor *arch; -+ char *str = (char *) alloca (strlen (aarch64_arch_string) + 1); -+ size_t len; -+ -+ strcpy (str, aarch64_arch_string); -+ -+ ext = strchr (str, '+'); -+ -+ if (ext != NULL) -+ len = ext - str; -+ else -+ len = strlen (str); -+ -+ if (len == 0) -+ { -+ error ("missing arch name in -march=%qs", str); -+ return; -+ } -+ -+ /* Loop through the list of supported ARCHs to find a match. */ -+ for (arch = all_architectures; arch->name != NULL; arch++) -+ { -+ if (strlen (arch->name) == len && strncmp (arch->name, str, len) == 0) -+ { -+ selected_arch = arch; -+ aarch64_isa_flags = selected_arch->flags; -+ selected_cpu = &all_cores[selected_arch->core]; -+ -+ if (ext != NULL) -+ { -+ /* ARCH string contains at least one extension. */ -+ aarch64_parse_extension (ext); -+ } -+ -+ return; -+ } -+ } -+ -+ /* ARCH name not found in list. */ -+ error ("unknown value %qs for -march", str); -+ return; -+} -+ -+/* Parse the CPU string. */ -+ -+static void -+aarch64_parse_cpu (void) -+{ -+ char *ext; -+ const struct processor *cpu; -+ char *str = (char *) alloca (strlen (aarch64_cpu_string) + 1); -+ size_t len; -+ -+ strcpy (str, aarch64_cpu_string); -+ -+ ext = strchr (str, '+'); -+ -+ if (ext != NULL) -+ len = ext - str; -+ else -+ len = strlen (str); -+ -+ if (len == 0) -+ { -+ error ("missing cpu name in -mcpu=%qs", str); -+ return; -+ } -+ -+ /* Loop through the list of supported CPUs to find a match. */ -+ for (cpu = all_cores; cpu->name != NULL; cpu++) -+ { -+ if (strlen (cpu->name) == len && strncmp (cpu->name, str, len) == 0) -+ { -+ selected_cpu = cpu; -+ aarch64_isa_flags = selected_cpu->flags; -+ -+ if (ext != NULL) -+ { -+ /* CPU string contains at least one extension. */ -+ aarch64_parse_extension (ext); -+ } -+ -+ return; -+ } -+ } -+ -+ /* CPU name not found in list. */ -+ error ("unknown value %qs for -mcpu", str); -+ return; -+} -+ -+/* Parse the TUNE string. */ -+ -+static void -+aarch64_parse_tune (void) -+{ -+ const struct processor *cpu; -+ char *str = (char *) alloca (strlen (aarch64_tune_string) + 1); -+ strcpy (str, aarch64_tune_string); -+ -+ /* Loop through the list of supported CPUs to find a match. */ -+ for (cpu = all_cores; cpu->name != NULL; cpu++) -+ { -+ if (strcmp (cpu->name, str) == 0) -+ { -+ selected_tune = cpu; -+ return; -+ } -+ } -+ -+ /* CPU name not found in list. */ -+ error ("unknown value %qs for -mtune", str); -+ return; -+} -+ -+ -+/* Implement TARGET_OPTION_OVERRIDE. */ -+ -+static void -+aarch64_override_options (void) -+{ -+ /* march wins over mcpu, so when march is defined, mcpu takes the same value, -+ otherwise march remains undefined. mtune can be used with either march or -+ mcpu. */ -+ -+ if (aarch64_arch_string) -+ { -+ aarch64_parse_arch (); -+ aarch64_cpu_string = NULL; -+ } -+ -+ if (aarch64_cpu_string) -+ { -+ aarch64_parse_cpu (); -+ selected_arch = NULL; -+ } -+ -+ if (aarch64_tune_string) -+ { -+ aarch64_parse_tune (); -+ } -+ -+ initialize_aarch64_code_model (); -+ -+ aarch64_build_bitmask_table (); -+ -+ /* This target defaults to strict volatile bitfields. */ -+ if (flag_strict_volatile_bitfields < 0 && abi_version_at_least (2)) -+ flag_strict_volatile_bitfields = 1; -+ -+ /* If the user did not specify a processor, choose the default -+ one for them. This will be the CPU set during configuration using -+ --with-cpu, otherwise it is "generic". */ -+ if (!selected_cpu) -+ { -+ selected_cpu = &all_cores[TARGET_CPU_DEFAULT & 0x3f]; -+ aarch64_isa_flags = TARGET_CPU_DEFAULT >> 6; -+ } -+ -+ gcc_assert (selected_cpu); -+ -+ /* The selected cpu may be an architecture, so lookup tuning by core ID. */ -+ if (!selected_tune) -+ selected_tune = &all_cores[selected_cpu->core]; -+ -+ aarch64_tune_flags = selected_tune->flags; -+ aarch64_tune = selected_tune->core; -+ aarch64_tune_params = selected_tune->tune; -+ -+ aarch64_override_options_after_change (); -+} -+ -+/* Implement targetm.override_options_after_change. */ -+ -+static void -+aarch64_override_options_after_change (void) -+{ -+ faked_omit_frame_pointer = false; -+ -+ /* To omit leaf frame pointers, we need to turn flag_omit_frame_pointer on so -+ that aarch64_frame_pointer_required will be called. We need to remember -+ whether flag_omit_frame_pointer was turned on normally or just faked. */ -+ -+ if (flag_omit_leaf_frame_pointer && !flag_omit_frame_pointer) -+ { -+ flag_omit_frame_pointer = true; -+ faked_omit_frame_pointer = true; -+ } -+} -+ -+static struct machine_function * -+aarch64_init_machine_status (void) -+{ -+ struct machine_function *machine; -+ machine = ggc_alloc_cleared_machine_function (); -+ return machine; -+} -+ -+void -+aarch64_init_expanders (void) -+{ -+ init_machine_status = aarch64_init_machine_status; -+} -+ -+/* A checking mechanism for the implementation of the various code models. */ -+static void -+initialize_aarch64_code_model (void) -+{ -+ if (flag_pic) -+ { -+ switch (aarch64_cmodel_var) -+ { -+ case AARCH64_CMODEL_TINY: -+ aarch64_cmodel = AARCH64_CMODEL_TINY_PIC; -+ break; -+ case AARCH64_CMODEL_SMALL: -+ aarch64_cmodel = AARCH64_CMODEL_SMALL_PIC; -+ break; -+ case AARCH64_CMODEL_LARGE: -+ sorry ("code model %qs with -f%s", "large", -+ flag_pic > 1 ? "PIC" : "pic"); -+ default: -+ gcc_unreachable (); -+ } -+ } -+ else -+ aarch64_cmodel = aarch64_cmodel_var; -+} -+ -+/* Return true if SYMBOL_REF X binds locally. */ -+ -+static bool -+aarch64_symbol_binds_local_p (const_rtx x) -+{ -+ return (SYMBOL_REF_DECL (x) -+ ? targetm.binds_local_p (SYMBOL_REF_DECL (x)) -+ : SYMBOL_REF_LOCAL_P (x)); -+} -+ -+/* Return true if SYMBOL_REF X is thread local */ -+static bool -+aarch64_tls_symbol_p (rtx x) -+{ -+ if (! TARGET_HAVE_TLS) -+ return false; -+ -+ if (GET_CODE (x) != SYMBOL_REF) -+ return false; -+ -+ return SYMBOL_REF_TLS_MODEL (x) != 0; -+} -+ -+/* Classify a TLS symbol into one of the TLS kinds. */ -+enum aarch64_symbol_type -+aarch64_classify_tls_symbol (rtx x) -+{ -+ enum tls_model tls_kind = tls_symbolic_operand_type (x); -+ -+ switch (tls_kind) -+ { -+ case TLS_MODEL_GLOBAL_DYNAMIC: -+ case TLS_MODEL_LOCAL_DYNAMIC: -+ return TARGET_TLS_DESC ? SYMBOL_SMALL_TLSDESC : SYMBOL_SMALL_TLSGD; -+ -+ case TLS_MODEL_INITIAL_EXEC: -+ return SYMBOL_SMALL_GOTTPREL; -+ -+ case TLS_MODEL_LOCAL_EXEC: -+ return SYMBOL_SMALL_TPREL; -+ -+ case TLS_MODEL_EMULATED: -+ case TLS_MODEL_NONE: -+ return SYMBOL_FORCE_TO_MEM; -+ -+ default: -+ gcc_unreachable (); -+ } -+} -+ -+/* Return the method that should be used to access SYMBOL_REF or -+ LABEL_REF X in context CONTEXT. */ -+enum aarch64_symbol_type -+aarch64_classify_symbol (rtx x, -+ enum aarch64_symbol_context context ATTRIBUTE_UNUSED) -+{ -+ if (GET_CODE (x) == LABEL_REF) -+ { -+ switch (aarch64_cmodel) -+ { -+ case AARCH64_CMODEL_LARGE: -+ return SYMBOL_FORCE_TO_MEM; -+ -+ case AARCH64_CMODEL_TINY_PIC: -+ case AARCH64_CMODEL_TINY: -+ case AARCH64_CMODEL_SMALL_PIC: -+ case AARCH64_CMODEL_SMALL: -+ return SYMBOL_SMALL_ABSOLUTE; -+ -+ default: -+ gcc_unreachable (); -+ } -+ } -+ -+ gcc_assert (GET_CODE (x) == SYMBOL_REF); -+ -+ switch (aarch64_cmodel) -+ { -+ case AARCH64_CMODEL_LARGE: -+ return SYMBOL_FORCE_TO_MEM; -+ -+ case AARCH64_CMODEL_TINY: -+ case AARCH64_CMODEL_SMALL: -+ -+ /* This is needed to get DFmode, TImode constants to be loaded off -+ the constant pool. Is it necessary to dump TImode values into -+ the constant pool. We don't handle TImode constant loads properly -+ yet and hence need to use the constant pool. */ -+ if (CONSTANT_POOL_ADDRESS_P (x)) -+ return SYMBOL_FORCE_TO_MEM; -+ -+ if (aarch64_tls_symbol_p (x)) -+ return aarch64_classify_tls_symbol (x); -+ -+ if (SYMBOL_REF_WEAK (x)) -+ return SYMBOL_FORCE_TO_MEM; -+ -+ return SYMBOL_SMALL_ABSOLUTE; -+ -+ case AARCH64_CMODEL_TINY_PIC: -+ case AARCH64_CMODEL_SMALL_PIC: -+ -+ if (CONSTANT_POOL_ADDRESS_P (x)) -+ return SYMBOL_FORCE_TO_MEM; -+ -+ if (aarch64_tls_symbol_p (x)) -+ return aarch64_classify_tls_symbol (x); -+ -+ if (!aarch64_symbol_binds_local_p (x)) -+ return SYMBOL_SMALL_GOT; -+ -+ return SYMBOL_SMALL_ABSOLUTE; -+ -+ default: -+ gcc_unreachable (); -+ } -+ /* By default push everything into the constant pool. */ -+ return SYMBOL_FORCE_TO_MEM; -+} -+ -+/* Return true if X is a symbolic constant that can be used in context -+ CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */ -+ -+bool -+aarch64_symbolic_constant_p (rtx x, enum aarch64_symbol_context context, -+ enum aarch64_symbol_type *symbol_type) -+{ -+ rtx offset; -+ split_const (x, &x, &offset); -+ if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) -+ *symbol_type = aarch64_classify_symbol (x, context); -+ else -+ return false; -+ -+ /* No checking of offset at this point. */ -+ return true; -+} -+ -+bool -+aarch64_constant_address_p (rtx x) -+{ -+ return (CONSTANT_P (x) && memory_address_p (DImode, x)); -+} -+ -+bool -+aarch64_legitimate_pic_operand_p (rtx x) -+{ -+ if (GET_CODE (x) == SYMBOL_REF -+ || (GET_CODE (x) == CONST -+ && GET_CODE (XEXP (x, 0)) == PLUS -+ && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)) -+ return false; -+ -+ return true; -+} -+ -+static bool -+aarch64_legitimate_constant_p (enum machine_mode mode, rtx x) -+{ -+ /* This could probably go away because -+ we now decompose CONST_INTs according to expand_mov_immediate. */ -+ if ((GET_CODE (x) == CONST_VECTOR -+ && aarch64_simd_valid_immediate (x, mode, false, -+ NULL, NULL, NULL, NULL, NULL) != -1) -+ || CONST_INT_P (x)) -+ return !targetm.cannot_force_const_mem (mode, x); -+ -+ if (GET_CODE (x) == HIGH -+ && aarch64_valid_symref (XEXP (x, 0), GET_MODE (XEXP (x, 0)))) -+ return true; -+ -+ return aarch64_constant_address_p (x); -+} -+ -+static void -+aarch64_init_builtins (void) -+{ -+ tree ftype, decl = NULL; -+ -+ ftype = build_function_type (ptr_type_node, void_list_node); -+ decl = add_builtin_function ("__builtin_thread_pointer", ftype, -+ AARCH64_BUILTIN_THREAD_POINTER, BUILT_IN_MD, -+ NULL, NULL_TREE); -+ TREE_NOTHROW (decl) = 1; -+ TREE_READONLY (decl) = 1; -+ -+ if (TARGET_SIMD) -+ init_aarch64_simd_builtins (); -+} -+ -+static rtx -+aarch64_load_tp (rtx target) -+{ -+ if (!target -+ || GET_MODE (target) != Pmode -+ || !register_operand (target, Pmode)) -+ target = gen_reg_rtx (Pmode); -+ -+ /* Can return in any reg. */ -+ emit_insn (gen_aarch64_load_tp_hard (target)); -+ return target; -+} -+ -+/* Expand an expression EXP that calls a built-in function, -+ with result going to TARGET if that's convenient. */ -+static rtx -+aarch64_expand_builtin (tree exp, -+ rtx target, -+ rtx subtarget ATTRIBUTE_UNUSED, -+ enum machine_mode mode ATTRIBUTE_UNUSED, -+ int ignore ATTRIBUTE_UNUSED) -+{ -+ tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); -+ int fcode = DECL_FUNCTION_CODE (fndecl); -+ -+ if (fcode == AARCH64_BUILTIN_THREAD_POINTER) -+ return aarch64_load_tp (target); -+ -+ if (fcode >= AARCH64_SIMD_BUILTIN_BASE) -+ return aarch64_simd_expand_builtin (fcode, exp, target); -+ -+ return NULL_RTX; -+} -+ -+/* On AAPCS systems, this is the "struct __va_list". */ -+static GTY(()) tree va_list_type; -+ -+/* Implement TARGET_BUILD_BUILTIN_VA_LIST. -+ Return the type to use as __builtin_va_list. -+ -+ AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as: -+ -+ struct __va_list -+ { -+ void *__stack; -+ void *__gr_top; -+ void *__vr_top; -+ int __gr_offs; -+ int __vr_offs; -+ }; */ -+ -+static tree -+aarch64_build_builtin_va_list (void) -+{ -+ tree va_list_name; -+ tree f_stack, f_grtop, f_vrtop, f_groff, f_vroff; -+ -+ /* Create the type. */ -+ va_list_type = lang_hooks.types.make_type (RECORD_TYPE); -+ /* Give it the required name. */ -+ va_list_name = build_decl (BUILTINS_LOCATION, -+ TYPE_DECL, -+ get_identifier ("__va_list"), -+ va_list_type); -+ DECL_ARTIFICIAL (va_list_name) = 1; -+ TYPE_NAME (va_list_type) = va_list_name; -+ -+ /* Create the fields. */ -+ f_stack = build_decl (BUILTINS_LOCATION, -+ FIELD_DECL, get_identifier ("__stack"), -+ ptr_type_node); -+ f_grtop = build_decl (BUILTINS_LOCATION, -+ FIELD_DECL, get_identifier ("__gr_top"), -+ ptr_type_node); -+ f_vrtop = build_decl (BUILTINS_LOCATION, -+ FIELD_DECL, get_identifier ("__vr_top"), -+ ptr_type_node); -+ f_groff = build_decl (BUILTINS_LOCATION, -+ FIELD_DECL, get_identifier ("__gr_offs"), -+ integer_type_node); -+ f_vroff = build_decl (BUILTINS_LOCATION, -+ FIELD_DECL, get_identifier ("__vr_offs"), -+ integer_type_node); -+ -+ DECL_ARTIFICIAL (f_stack) = 1; -+ DECL_ARTIFICIAL (f_grtop) = 1; -+ DECL_ARTIFICIAL (f_vrtop) = 1; -+ DECL_ARTIFICIAL (f_groff) = 1; -+ DECL_ARTIFICIAL (f_vroff) = 1; -+ -+ DECL_FIELD_CONTEXT (f_stack) = va_list_type; -+ DECL_FIELD_CONTEXT (f_grtop) = va_list_type; -+ DECL_FIELD_CONTEXT (f_vrtop) = va_list_type; -+ DECL_FIELD_CONTEXT (f_groff) = va_list_type; -+ DECL_FIELD_CONTEXT (f_vroff) = va_list_type; -+ -+ TYPE_FIELDS (va_list_type) = f_stack; -+ DECL_CHAIN (f_stack) = f_grtop; -+ DECL_CHAIN (f_grtop) = f_vrtop; -+ DECL_CHAIN (f_vrtop) = f_groff; -+ DECL_CHAIN (f_groff) = f_vroff; -+ -+ /* Compute its layout. */ -+ layout_type (va_list_type); -+ -+ return va_list_type; -+} -+ -+/* Implement TARGET_EXPAND_BUILTIN_VA_START. */ -+static void -+aarch64_expand_builtin_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED) -+{ -+ const CUMULATIVE_ARGS *cum; -+ tree f_stack, f_grtop, f_vrtop, f_groff, f_vroff; -+ tree stack, grtop, vrtop, groff, vroff; -+ tree t; -+ int gr_save_area_size; -+ int vr_save_area_size; -+ int vr_offset; -+ -+ cum = &crtl->args.info; -+ gr_save_area_size -+ = (NUM_ARG_REGS - cum->aapcs_ncrn) * UNITS_PER_WORD; -+ vr_save_area_size -+ = (NUM_FP_ARG_REGS - cum->aapcs_nvrn) * UNITS_PER_VREG; -+ -+ if (TARGET_GENERAL_REGS_ONLY) -+ { -+ if (cum->aapcs_nvrn > 0) -+ sorry ("%qs and floating point or vector arguments", -+ "-mgeneral-regs-only"); -+ vr_save_area_size = 0; -+ } -+ -+ f_stack = TYPE_FIELDS (va_list_type_node); -+ f_grtop = DECL_CHAIN (f_stack); -+ f_vrtop = DECL_CHAIN (f_grtop); -+ f_groff = DECL_CHAIN (f_vrtop); -+ f_vroff = DECL_CHAIN (f_groff); -+ -+ stack = build3 (COMPONENT_REF, TREE_TYPE (f_stack), valist, f_stack, -+ NULL_TREE); -+ grtop = build3 (COMPONENT_REF, TREE_TYPE (f_grtop), valist, f_grtop, -+ NULL_TREE); -+ vrtop = build3 (COMPONENT_REF, TREE_TYPE (f_vrtop), valist, f_vrtop, -+ NULL_TREE); -+ groff = build3 (COMPONENT_REF, TREE_TYPE (f_groff), valist, f_groff, -+ NULL_TREE); -+ vroff = build3 (COMPONENT_REF, TREE_TYPE (f_vroff), valist, f_vroff, -+ NULL_TREE); -+ -+ /* Emit code to initialize STACK, which points to the next varargs stack -+ argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used -+ by named arguments. STACK is 8-byte aligned. */ -+ t = make_tree (TREE_TYPE (stack), virtual_incoming_args_rtx); -+ if (cum->aapcs_stack_size > 0) -+ t = fold_build_pointer_plus_hwi (t, cum->aapcs_stack_size * UNITS_PER_WORD); -+ t = build2 (MODIFY_EXPR, TREE_TYPE (stack), stack, t); -+ expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); -+ -+ /* Emit code to initialize GRTOP, the top of the GR save area. -+ virtual_incoming_args_rtx should have been 16 byte aligned. */ -+ t = make_tree (TREE_TYPE (grtop), virtual_incoming_args_rtx); -+ t = build2 (MODIFY_EXPR, TREE_TYPE (grtop), grtop, t); -+ expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); -+ -+ /* Emit code to initialize VRTOP, the top of the VR save area. -+ This address is gr_save_area_bytes below GRTOP, rounded -+ down to the next 16-byte boundary. */ -+ t = make_tree (TREE_TYPE (vrtop), virtual_incoming_args_rtx); -+ vr_offset = AARCH64_ROUND_UP (gr_save_area_size, -+ STACK_BOUNDARY / BITS_PER_UNIT); -+ -+ if (vr_offset) -+ t = fold_build_pointer_plus_hwi (t, -vr_offset); -+ t = build2 (MODIFY_EXPR, TREE_TYPE (vrtop), vrtop, t); -+ expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); -+ -+ /* Emit code to initialize GROFF, the offset from GRTOP of the -+ next GPR argument. */ -+ t = build2 (MODIFY_EXPR, TREE_TYPE (groff), groff, -+ build_int_cst (TREE_TYPE (groff), -gr_save_area_size)); -+ expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); -+ -+ /* Likewise emit code to initialize VROFF, the offset from FTOP -+ of the next VR argument. */ -+ t = build2 (MODIFY_EXPR, TREE_TYPE (vroff), vroff, -+ build_int_cst (TREE_TYPE (vroff), -vr_save_area_size)); -+ expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); -+} -+ -+/* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */ -+ -+static tree -+aarch64_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, -+ gimple_seq *post_p ATTRIBUTE_UNUSED) -+{ -+ tree addr; -+ bool indirect_p; -+ bool is_ha; /* is HFA or HVA. */ -+ bool dw_align; /* double-word align. */ -+ enum machine_mode ag_mode = VOIDmode; -+ int nregs; -+ enum machine_mode mode; -+ -+ tree f_stack, f_grtop, f_vrtop, f_groff, f_vroff; -+ tree stack, f_top, f_off, off, arg, roundup, on_stack; -+ HOST_WIDE_INT size, rsize, adjust, align; -+ tree t, u, cond1, cond2; -+ -+ indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false); -+ if (indirect_p) -+ type = build_pointer_type (type); -+ -+ mode = TYPE_MODE (type); -+ -+ f_stack = TYPE_FIELDS (va_list_type_node); -+ f_grtop = DECL_CHAIN (f_stack); -+ f_vrtop = DECL_CHAIN (f_grtop); -+ f_groff = DECL_CHAIN (f_vrtop); -+ f_vroff = DECL_CHAIN (f_groff); -+ -+ stack = build3 (COMPONENT_REF, TREE_TYPE (f_stack), unshare_expr (valist), -+ f_stack, NULL_TREE); -+ size = int_size_in_bytes (type); -+ align = aarch64_function_arg_alignment (mode, type) / BITS_PER_UNIT; -+ -+ dw_align = false; -+ adjust = 0; -+ if (aarch64_vfp_is_call_or_return_candidate (mode, -+ type, -+ &ag_mode, -+ &nregs, -+ &is_ha)) -+ { -+ /* TYPE passed in fp/simd registers. */ -+ if (TARGET_GENERAL_REGS_ONLY) -+ sorry ("%qs and floating point or vector arguments", -+ "-mgeneral-regs-only"); -+ -+ f_top = build3 (COMPONENT_REF, TREE_TYPE (f_vrtop), -+ unshare_expr (valist), f_vrtop, NULL_TREE); -+ f_off = build3 (COMPONENT_REF, TREE_TYPE (f_vroff), -+ unshare_expr (valist), f_vroff, NULL_TREE); -+ -+ rsize = nregs * UNITS_PER_VREG; -+ -+ if (is_ha) -+ { -+ if (BYTES_BIG_ENDIAN && GET_MODE_SIZE (ag_mode) < UNITS_PER_VREG) -+ adjust = UNITS_PER_VREG - GET_MODE_SIZE (ag_mode); -+ } -+ else if (BLOCK_REG_PADDING (mode, type, 1) == downward -+ && size < UNITS_PER_VREG) -+ { -+ adjust = UNITS_PER_VREG - size; -+ } -+ } -+ else -+ { -+ /* TYPE passed in general registers. */ -+ f_top = build3 (COMPONENT_REF, TREE_TYPE (f_grtop), -+ unshare_expr (valist), f_grtop, NULL_TREE); -+ f_off = build3 (COMPONENT_REF, TREE_TYPE (f_groff), -+ unshare_expr (valist), f_groff, NULL_TREE); -+ rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; -+ nregs = rsize / UNITS_PER_WORD; -+ -+ if (align > 8) -+ dw_align = true; -+ -+ if (BLOCK_REG_PADDING (mode, type, 1) == downward -+ && size < UNITS_PER_WORD) -+ { -+ adjust = UNITS_PER_WORD - size; -+ } -+ } -+ -+ /* Get a local temporary for the field value. */ -+ off = get_initialized_tmp_var (f_off, pre_p, NULL); -+ -+ /* Emit code to branch if off >= 0. */ -+ t = build2 (GE_EXPR, boolean_type_node, off, -+ build_int_cst (TREE_TYPE (off), 0)); -+ cond1 = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE); -+ -+ if (dw_align) -+ { -+ /* Emit: offs = (offs + 15) & -16. */ -+ t = build2 (PLUS_EXPR, TREE_TYPE (off), off, -+ build_int_cst (TREE_TYPE (off), 15)); -+ t = build2 (BIT_AND_EXPR, TREE_TYPE (off), t, -+ build_int_cst (TREE_TYPE (off), -16)); -+ roundup = build2 (MODIFY_EXPR, TREE_TYPE (off), off, t); -+ } -+ else -+ roundup = NULL; -+ -+ /* Update ap.__[g|v]r_offs */ -+ t = build2 (PLUS_EXPR, TREE_TYPE (off), off, -+ build_int_cst (TREE_TYPE (off), rsize)); -+ t = build2 (MODIFY_EXPR, TREE_TYPE (f_off), unshare_expr (f_off), t); -+ -+ /* String up. */ -+ if (roundup) -+ t = build2 (COMPOUND_EXPR, TREE_TYPE (t), roundup, t); -+ -+ /* [cond2] if (ap.__[g|v]r_offs > 0) */ -+ u = build2 (GT_EXPR, boolean_type_node, unshare_expr (f_off), -+ build_int_cst (TREE_TYPE (f_off), 0)); -+ cond2 = build3 (COND_EXPR, ptr_type_node, u, NULL_TREE, NULL_TREE); -+ -+ /* String up: make sure the assignment happens before the use. */ -+ t = build2 (COMPOUND_EXPR, TREE_TYPE (cond2), t, cond2); -+ COND_EXPR_ELSE (cond1) = t; -+ -+ /* Prepare the trees handling the argument that is passed on the stack; -+ the top level node will store in ON_STACK. */ -+ arg = get_initialized_tmp_var (stack, pre_p, NULL); -+ if (align > 8) -+ { -+ /* if (alignof(type) > 8) (arg = arg + 15) & -16; */ -+ t = fold_convert (intDI_type_node, arg); -+ t = build2 (PLUS_EXPR, TREE_TYPE (t), t, -+ build_int_cst (TREE_TYPE (t), 15)); -+ t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, -+ build_int_cst (TREE_TYPE (t), -16)); -+ t = fold_convert (TREE_TYPE (arg), t); -+ roundup = build2 (MODIFY_EXPR, TREE_TYPE (arg), arg, t); -+ } -+ else -+ roundup = NULL; -+ /* Advance ap.__stack */ -+ t = fold_convert (intDI_type_node, arg); -+ t = build2 (PLUS_EXPR, TREE_TYPE (t), t, -+ build_int_cst (TREE_TYPE (t), size + 7)); -+ t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, -+ build_int_cst (TREE_TYPE (t), -8)); -+ t = fold_convert (TREE_TYPE (arg), t); -+ t = build2 (MODIFY_EXPR, TREE_TYPE (stack), unshare_expr (stack), t); -+ /* String up roundup and advance. */ -+ if (roundup) -+ t = build2 (COMPOUND_EXPR, TREE_TYPE (t), roundup, t); -+ /* String up with arg */ -+ on_stack = build2 (COMPOUND_EXPR, TREE_TYPE (arg), t, arg); -+ /* Big-endianness related address adjustment. */ -+ if (BLOCK_REG_PADDING (mode, type, 1) == downward -+ && size < UNITS_PER_WORD) -+ { -+ t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (arg), arg, -+ size_int (UNITS_PER_WORD - size)); -+ on_stack = build2 (COMPOUND_EXPR, TREE_TYPE (arg), on_stack, t); -+ } -+ -+ COND_EXPR_THEN (cond1) = unshare_expr (on_stack); -+ COND_EXPR_THEN (cond2) = unshare_expr (on_stack); -+ -+ /* Adjustment to OFFSET in the case of BIG_ENDIAN. */ -+ t = off; -+ if (adjust) -+ t = build2 (PREINCREMENT_EXPR, TREE_TYPE (off), off, -+ build_int_cst (TREE_TYPE (off), adjust)); -+ -+ t = fold_convert (sizetype, t); -+ t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (f_top), f_top, t); -+ -+ if (is_ha) -+ { -+ /* type ha; // treat as "struct {ftype field[n];}" -+ ... [computing offs] -+ for (i = 0; i 0) -+ sorry ("%qs and floating point or vector arguments", -+ "-mgeneral-regs-only"); -+ vr_saved = 0; -+ } -+ -+ if (!no_rtl) -+ { -+ if (gr_saved > 0) -+ { -+ rtx ptr, mem; -+ -+ /* virtual_incoming_args_rtx should have been 16-byte aligned. */ -+ ptr = plus_constant (virtual_incoming_args_rtx, -+ - gr_saved * UNITS_PER_WORD); -+ mem = gen_frame_mem (BLKmode, ptr); -+ set_mem_alias_set (mem, get_varargs_alias_set ()); -+ -+ move_block_from_reg (local_cum.aapcs_ncrn + R0_REGNUM, -+ mem, gr_saved); -+ } -+ if (vr_saved > 0) -+ { -+ /* We can't use move_block_from_reg, because it will use -+ the wrong mode, storing D regs only. */ -+ enum machine_mode mode = TImode; -+ int off, i; -+ -+ /* Set OFF to the offset from virtual_incoming_args_rtx of -+ the first vector register. The VR save area lies below -+ the GR one, and is aligned to 16 bytes. */ -+ off = -AARCH64_ROUND_UP (gr_saved * UNITS_PER_WORD, -+ STACK_BOUNDARY / BITS_PER_UNIT); -+ off -= vr_saved * UNITS_PER_VREG; -+ -+ for (i = local_cum.aapcs_nvrn; i < NUM_FP_ARG_REGS; ++i) -+ { -+ rtx ptr, mem; -+ -+ ptr = plus_constant (virtual_incoming_args_rtx, off); -+ mem = gen_frame_mem (mode, ptr); -+ set_mem_alias_set (mem, get_varargs_alias_set ()); -+ aarch64_emit_move (mem, gen_rtx_REG (mode, V0_REGNUM + i)); -+ off += UNITS_PER_VREG; -+ } -+ } -+ } -+ -+ /* We don't save the size into *PRETEND_SIZE because we want to avoid -+ any complication of having crtl->args.pretend_args_size changed. */ -+ cfun->machine->saved_varargs_size -+ = (AARCH64_ROUND_UP (gr_saved * UNITS_PER_WORD, -+ STACK_BOUNDARY / BITS_PER_UNIT) -+ + vr_saved * UNITS_PER_VREG); -+} -+ -+static void -+aarch64_conditional_register_usage (void) -+{ -+ int i; -+ if (!TARGET_FLOAT) -+ { -+ for (i = V0_REGNUM; i <= V31_REGNUM; i++) -+ { -+ fixed_regs[i] = 1; -+ call_used_regs[i] = 1; -+ } -+ } -+} -+ -+/* Walk down the type tree of TYPE counting consecutive base elements. -+ If *MODEP is VOIDmode, then set it to the first valid floating point -+ type. If a non-floating point type is found, or if a floating point -+ type that doesn't match a non-VOIDmode *MODEP is found, then return -1, -+ otherwise return the count in the sub-tree. */ -+static int -+aapcs_vfp_sub_candidate (const_tree type, enum machine_mode *modep) -+{ -+ enum machine_mode mode; -+ HOST_WIDE_INT size; -+ -+ switch (TREE_CODE (type)) -+ { -+ case REAL_TYPE: -+ mode = TYPE_MODE (type); -+ if (mode != DFmode && mode != SFmode && mode != TFmode) -+ return -1; -+ -+ if (*modep == VOIDmode) -+ *modep = mode; -+ -+ if (*modep == mode) -+ return 1; -+ -+ break; -+ -+ case COMPLEX_TYPE: -+ mode = TYPE_MODE (TREE_TYPE (type)); -+ if (mode != DFmode && mode != SFmode && mode != TFmode) -+ return -1; -+ -+ if (*modep == VOIDmode) -+ *modep = mode; -+ -+ if (*modep == mode) -+ return 2; -+ -+ break; -+ -+ case VECTOR_TYPE: -+ /* Use V2SImode and V4SImode as representatives of all 64-bit -+ and 128-bit vector types. */ -+ size = int_size_in_bytes (type); -+ switch (size) -+ { -+ case 8: -+ mode = V2SImode; -+ break; -+ case 16: -+ mode = V4SImode; -+ break; -+ default: -+ return -1; -+ } -+ -+ if (*modep == VOIDmode) -+ *modep = mode; -+ -+ /* Vector modes are considered to be opaque: two vectors are -+ equivalent for the purposes of being homogeneous aggregates -+ if they are the same size. */ -+ if (*modep == mode) -+ return 1; -+ -+ break; -+ -+ case ARRAY_TYPE: -+ { -+ int count; -+ tree index = TYPE_DOMAIN (type); -+ -+ /* Can't handle incomplete types. */ -+ if (!COMPLETE_TYPE_P (type)) -+ return -1; -+ -+ count = aapcs_vfp_sub_candidate (TREE_TYPE (type), modep); -+ if (count == -1 -+ || !index -+ || !TYPE_MAX_VALUE (index) -+ || !host_integerp (TYPE_MAX_VALUE (index), 1) -+ || !TYPE_MIN_VALUE (index) -+ || !host_integerp (TYPE_MIN_VALUE (index), 1) -+ || count < 0) -+ return -1; -+ -+ count *= (1 + tree_low_cst (TYPE_MAX_VALUE (index), 1) -+ - tree_low_cst (TYPE_MIN_VALUE (index), 1)); -+ -+ /* There must be no padding. */ -+ if (!host_integerp (TYPE_SIZE (type), 1) -+ || (tree_low_cst (TYPE_SIZE (type), 1) -+ != count * GET_MODE_BITSIZE (*modep))) -+ return -1; -+ -+ return count; -+ } -+ -+ case RECORD_TYPE: -+ { -+ int count = 0; -+ int sub_count; -+ tree field; -+ -+ /* Can't handle incomplete types. */ -+ if (!COMPLETE_TYPE_P (type)) -+ return -1; -+ -+ for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) -+ { -+ if (TREE_CODE (field) != FIELD_DECL) -+ continue; -+ -+ sub_count = aapcs_vfp_sub_candidate (TREE_TYPE (field), modep); -+ if (sub_count < 0) -+ return -1; -+ count += sub_count; -+ } -+ -+ /* There must be no padding. */ -+ if (!host_integerp (TYPE_SIZE (type), 1) -+ || (tree_low_cst (TYPE_SIZE (type), 1) -+ != count * GET_MODE_BITSIZE (*modep))) -+ return -1; -+ -+ return count; -+ } -+ -+ case UNION_TYPE: -+ case QUAL_UNION_TYPE: -+ { -+ /* These aren't very interesting except in a degenerate case. */ -+ int count = 0; -+ int sub_count; -+ tree field; -+ -+ /* Can't handle incomplete types. */ -+ if (!COMPLETE_TYPE_P (type)) -+ return -1; -+ -+ for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) -+ { -+ if (TREE_CODE (field) != FIELD_DECL) -+ continue; -+ -+ sub_count = aapcs_vfp_sub_candidate (TREE_TYPE (field), modep); -+ if (sub_count < 0) -+ return -1; -+ count = count > sub_count ? count : sub_count; -+ } -+ -+ /* There must be no padding. */ -+ if (!host_integerp (TYPE_SIZE (type), 1) -+ || (tree_low_cst (TYPE_SIZE (type), 1) -+ != count * GET_MODE_BITSIZE (*modep))) -+ return -1; -+ -+ return count; -+ } -+ -+ default: -+ break; -+ } -+ -+ return -1; -+} -+ -+/* Return TRUE if the type, as described by TYPE and MODE, is a composite -+ type as described in AAPCS64 \S 4.3. This includes aggregate, union and -+ array types. The C99 floating-point complex types are also considered -+ as composite types, according to AAPCS64 \S 7.1.1. The complex integer -+ types, which are GCC extensions and out of the scope of AAPCS64, are -+ treated as composite types here as well. -+ -+ Note that MODE itself is not sufficient in determining whether a type -+ is such a composite type or not. This is because -+ stor-layout.c:compute_record_mode may have already changed the MODE -+ (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a -+ structure with only one field may have its MODE set to the mode of the -+ field. Also an integer mode whose size matches the size of the -+ RECORD_TYPE type may be used to substitute the original mode -+ (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be -+ solely relied on. */ -+ -+static bool -+aarch64_composite_type_p (const_tree type, -+ enum machine_mode mode) -+{ -+ if (type && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE)) -+ return true; -+ -+ if (mode == BLKmode -+ || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT -+ || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT) -+ return true; -+ -+ return false; -+} -+ -+/* Return TRUE if the type, as described by TYPE and MODE, is a short vector -+ type as described in AAPCS64 \S 4.1.2. -+ -+ See the comment above aarch64_composite_type_p for the notes on MODE. */ -+ -+static bool -+aarch64_short_vector_p (const_tree type, -+ enum machine_mode mode) -+{ -+ HOST_WIDE_INT size = -1; -+ -+ if (type && TREE_CODE (type) == VECTOR_TYPE) -+ size = int_size_in_bytes (type); -+ else if (!aarch64_composite_type_p (type, mode) -+ && (GET_MODE_CLASS (mode) == MODE_VECTOR_INT -+ || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)) -+ size = GET_MODE_SIZE (mode); -+ -+ return (size == 8 || size == 16) ? true : false; -+} -+ -+/* Return TRUE if an argument, whose type is described by TYPE and MODE, -+ shall be passed or returned in simd/fp register(s) (providing these -+ parameter passing registers are available). -+ -+ Upon successful return, *COUNT returns the number of needed registers, -+ *BASE_MODE returns the mode of the individual register and when IS_HAF -+ is not NULL, *IS_HA indicates whether or not the argument is a homogeneous -+ floating-point aggregate or a homogeneous short-vector aggregate. */ -+ -+static bool -+aarch64_vfp_is_call_or_return_candidate (enum machine_mode mode, -+ const_tree type, -+ enum machine_mode *base_mode, -+ int *count, -+ bool *is_ha) -+{ -+ enum machine_mode new_mode = VOIDmode; -+ bool composite_p = aarch64_composite_type_p (type, mode); -+ -+ if (is_ha != NULL) *is_ha = false; -+ -+ if ((!composite_p && GET_MODE_CLASS (mode) == MODE_FLOAT) -+ || aarch64_short_vector_p (type, mode)) -+ { -+ *count = 1; -+ new_mode = mode; -+ } -+ else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) -+ { -+ if (is_ha != NULL) *is_ha = true; -+ *count = 2; -+ new_mode = GET_MODE_INNER (mode); -+ } -+ else if (type && composite_p) -+ { -+ int ag_count = aapcs_vfp_sub_candidate (type, &new_mode); -+ -+ if (ag_count > 0 && ag_count <= HA_MAX_NUM_FLDS) -+ { -+ if (is_ha != NULL) *is_ha = true; -+ *count = ag_count; -+ } -+ else -+ return false; -+ } -+ else -+ return false; -+ -+ *base_mode = new_mode; -+ return true; -+} -+ -+/* Implement TARGET_STRUCT_VALUE_RTX. */ -+ -+static rtx -+aarch64_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED, -+ int incoming ATTRIBUTE_UNUSED) -+{ -+ return gen_rtx_REG (Pmode, AARCH64_STRUCT_VALUE_REGNUM); -+} -+ -+/* Implements target hook vector_mode_supported_p. */ -+static bool -+aarch64_vector_mode_supported_p (enum machine_mode mode) -+{ -+ if (TARGET_SIMD -+ && (mode == V4SImode || mode == V8HImode -+ || mode == V16QImode || mode == V2DImode -+ || mode == V2SImode || mode == V4HImode -+ || mode == V8QImode || mode == V2SFmode -+ || mode == V4SFmode || mode == V2DFmode)) -+ return true; -+ -+ return false; -+} -+ -+/* Return quad mode as the preferred SIMD mode. */ -+static enum machine_mode -+aarch64_preferred_simd_mode (enum machine_mode mode) -+{ -+ if (TARGET_SIMD) -+ switch (mode) -+ { -+ case DFmode: -+ return V2DFmode; -+ case SFmode: -+ return V4SFmode; -+ case SImode: -+ return V4SImode; -+ case HImode: -+ return V8HImode; -+ case QImode: -+ return V16QImode; -+ case DImode: -+ return V2DImode; -+ break; -+ -+ default:; -+ } -+ return word_mode; -+} -+ -+/* Legitimize a memory reference for sync primitive implemented using -+ LDXR/STXR instructions. We currently force the form of the reference -+ to be indirect without offset. */ -+static rtx -+aarch64_legitimize_sync_memory (rtx memory) -+{ -+ rtx addr = force_reg (Pmode, XEXP (memory, 0)); -+ rtx legitimate_memory = gen_rtx_MEM (GET_MODE (memory), addr); -+ -+ set_mem_alias_set (legitimate_memory, ALIAS_SET_MEMORY_BARRIER); -+ MEM_VOLATILE_P (legitimate_memory) = MEM_VOLATILE_P (memory); -+ return legitimate_memory; -+} -+ -+/* An instruction emitter. */ -+typedef void (* emit_f) (int label, const char *, rtx *); -+ -+/* An instruction emitter that emits via the conventional -+ output_asm_insn. */ -+static void -+aarch64_emit (int label ATTRIBUTE_UNUSED, const char *pattern, rtx *operands) -+{ -+ output_asm_insn (pattern, operands); -+} -+ -+/* Count the number of emitted synchronization instructions. */ -+static unsigned aarch64_insn_count; -+ -+/* An emitter that counts emitted instructions but does not actually -+ emit instruction into the the instruction stream. */ -+static void -+aarch64_count (int label, -+ const char *pattern ATTRIBUTE_UNUSED, -+ rtx *operands ATTRIBUTE_UNUSED) -+{ -+ if (! label) -+ ++ aarch64_insn_count; -+} -+ -+static void -+aarch64_output_asm_insn (emit_f, int, rtx *, -+ const char *, ...) ATTRIBUTE_PRINTF_4; -+ -+/* Construct a pattern using conventional output formatting and feed -+ it to output_asm_insn. Provides a mechanism to construct the -+ output pattern on the fly. Note the hard limit on the pattern -+ buffer size. */ -+static void -+aarch64_output_asm_insn (emit_f emit, int label, rtx *operands, -+ const char *pattern, ...) -+{ -+ va_list ap; -+ char buffer[256]; -+ -+ va_start (ap, pattern); -+ vsnprintf (buffer, sizeof (buffer), pattern, ap); -+ va_end (ap); -+ emit (label, buffer, operands); -+} -+ -+/* Helper to figure out the instruction suffix required on LDXR/STXR -+ instructions for operations on an object of the specified mode. */ -+static const char * -+aarch64_load_store_suffix (enum machine_mode mode) -+{ -+ switch (mode) -+ { -+ case QImode: return "b"; -+ case HImode: return "h"; -+ case SImode: return ""; -+ case DImode: return ""; -+ default: -+ gcc_unreachable (); -+ } -+ return ""; -+} -+ -+/* Emit an excluive load instruction appropriate for the specified -+ mode. */ -+static void -+aarch64_output_sync_load (emit_f emit, -+ enum machine_mode mode, -+ rtx target, -+ rtx memory, -+ bool with_barrier) -+{ -+ const char *suffix = aarch64_load_store_suffix (mode); -+ rtx operands[2]; -+ -+ operands[0] = target; -+ operands[1] = memory; -+ aarch64_output_asm_insn (emit, 0, operands, "ld%sxr%s\t%%%s0, %%1", -+ with_barrier ? "a" : "", suffix, -+ mode == DImode ? "x" : "w"); -+} -+ -+/* Emit an exclusive store instruction appropriate for the specified -+ mode. */ -+static void -+aarch64_output_sync_store (emit_f emit, -+ enum machine_mode mode, -+ rtx result, -+ rtx value, -+ rtx memory, -+ bool with_barrier) -+{ -+ const char *suffix = aarch64_load_store_suffix (mode); -+ rtx operands[3]; -+ -+ operands[0] = result; -+ operands[1] = value; -+ operands[2] = memory; -+ aarch64_output_asm_insn (emit, 0, operands, -+ "st%sxr%s\t%%w0, %%%s1, %%2", -+ with_barrier ? "l" : "", -+ suffix, -+ mode == DImode ? "x" : "w"); -+} -+ -+/* Helper to emit a two operand instruction. */ -+static void -+aarch64_output_op2 (emit_f emit, const char *mnemonic, rtx d, rtx s) -+{ -+ rtx operands[2]; -+ enum machine_mode mode; -+ const char *constraint; -+ -+ mode = GET_MODE (d); -+ operands[0] = d; -+ operands[1] = s; -+ constraint = mode == DImode ? "" : "w"; -+ aarch64_output_asm_insn (emit, 0, operands, "%s\t%%%s0, %%%s1", mnemonic, -+ constraint, constraint); -+} -+ -+/* Helper to emit a three operand instruction. */ -+static void -+aarch64_output_op3 (emit_f emit, const char *mnemonic, rtx d, rtx a, rtx b) -+{ -+ rtx operands[3]; -+ enum machine_mode mode; -+ const char *constraint; -+ -+ mode = GET_MODE (d); -+ operands[0] = d; -+ operands[1] = a; -+ operands[2] = b; -+ -+ constraint = mode == DImode ? "" : "w"; -+ aarch64_output_asm_insn (emit, 0, operands, "%s\t%%%s0, %%%s1, %%%s2", -+ mnemonic, constraint, constraint, constraint); -+} -+ -+/* Emit a load store exclusive synchronization loop. -+ -+ do -+ old_value = [mem] -+ if old_value != required_value -+ break; -+ t1 = sync_op (old_value, new_value) -+ [mem] = t1, t2 = [0|1] -+ while ! t2 -+ -+ Note: -+ t1 == t2 is not permitted -+ t1 == old_value is permitted -+ -+ required_value: -+ -+ RTX register or const_int representing the required old_value for -+ the modify to continue, if NULL no comparsion is performed. */ -+static void -+aarch64_output_sync_loop (emit_f emit, -+ enum machine_mode mode, -+ rtx old_value, -+ rtx memory, -+ rtx required_value, -+ rtx new_value, -+ rtx t1, -+ rtx t2, -+ enum attr_sync_op sync_op, -+ int acquire_barrier, -+ int release_barrier) -+{ -+ rtx operands[1]; -+ -+ gcc_assert (t1 != t2); -+ -+ aarch64_output_asm_insn (emit, 1, operands, "%sLSYT%%=:", LOCAL_LABEL_PREFIX); -+ -+ aarch64_output_sync_load (emit, mode, old_value, memory, acquire_barrier); -+ -+ if (required_value) -+ { -+ rtx operands[2]; -+ -+ operands[0] = old_value; -+ operands[1] = required_value; -+ aarch64_output_asm_insn (emit, 0, operands, "cmp\t%%0, %%1"); -+ aarch64_output_asm_insn (emit, 0, operands, "bne\t%sLSYB%%=", -+ LOCAL_LABEL_PREFIX); -+ } -+ -+ switch (sync_op) -+ { -+ case SYNC_OP_ADD: -+ aarch64_output_op3 (emit, "add", t1, old_value, new_value); -+ break; -+ -+ case SYNC_OP_SUB: -+ aarch64_output_op3 (emit, "sub", t1, old_value, new_value); -+ break; -+ -+ case SYNC_OP_IOR: -+ aarch64_output_op3 (emit, "orr", t1, old_value, new_value); -+ break; -+ -+ case SYNC_OP_XOR: -+ aarch64_output_op3 (emit, "eor", t1, old_value, new_value); -+ break; -+ -+ case SYNC_OP_AND: -+ aarch64_output_op3 (emit,"and", t1, old_value, new_value); -+ break; -+ -+ case SYNC_OP_NAND: -+ aarch64_output_op3 (emit, "and", t1, old_value, new_value); -+ aarch64_output_op2 (emit, "mvn", t1, t1); -+ break; -+ -+ case SYNC_OP_NONE: -+ t1 = new_value; -+ break; -+ } -+ -+ aarch64_output_sync_store (emit, mode, t2, t1, memory, release_barrier); -+ operands[0] = t2; -+ aarch64_output_asm_insn (emit, 0, operands, "cbnz\t%%w0, %sLSYT%%=", -+ LOCAL_LABEL_PREFIX); -+ -+ aarch64_output_asm_insn (emit, 1, operands, "%sLSYB%%=:", LOCAL_LABEL_PREFIX); -+} -+ -+static rtx -+aarch64_get_sync_operand (rtx *operands, int index, rtx default_value) -+{ -+ if (index > 0) -+ default_value = operands[index - 1]; -+ -+ return default_value; -+} -+ -+#define FETCH_SYNC_OPERAND(NAME, DEFAULT) \ -+ aarch64_get_sync_operand (operands, (int) get_attr_sync_##NAME (insn), \ -+ DEFAULT); -+ -+/* Extract the operands for a synchroniztion instruction from the -+ instructions attributes and emit the instruction. */ -+static void -+aarch64_process_output_sync_insn (emit_f emit, rtx insn, rtx *operands) -+{ -+ rtx result, memory, required_value, new_value, t1, t2; -+ int release_barrier; -+ int acquire_barrier = 1; -+ enum machine_mode mode; -+ enum attr_sync_op sync_op; -+ -+ result = FETCH_SYNC_OPERAND (result, 0); -+ memory = FETCH_SYNC_OPERAND (memory, 0); -+ required_value = FETCH_SYNC_OPERAND (required_value, 0); -+ new_value = FETCH_SYNC_OPERAND (new_value, 0); -+ t1 = FETCH_SYNC_OPERAND (t1, 0); -+ t2 = FETCH_SYNC_OPERAND (t2, 0); -+ release_barrier = -+ get_attr_sync_release_barrier (insn) == SYNC_RELEASE_BARRIER_YES; -+ sync_op = get_attr_sync_op (insn); -+ mode = GET_MODE (memory); -+ -+ aarch64_output_sync_loop (emit, mode, result, memory, required_value, -+ new_value, t1, t2, sync_op, acquire_barrier, -+ release_barrier); -+} -+ -+/* Emit a synchronization instruction loop. */ -+const char * -+aarch64_output_sync_insn (rtx insn, rtx *operands) -+{ -+ aarch64_process_output_sync_insn (aarch64_emit, insn, operands); -+ return ""; -+} -+ -+/* Emit a store release instruction appropriate for the specified -+ mode. */ -+const char * -+aarch64_output_sync_lock_release (rtx value, rtx memory) -+{ -+ const char *suffix; -+ enum machine_mode mode; -+ rtx operands[2]; -+ operands[0] = value; -+ operands[1] = memory; -+ mode = GET_MODE (memory); -+ suffix = aarch64_load_store_suffix (mode); -+ aarch64_output_asm_insn (aarch64_emit, 0, operands, -+ "stlr%s\t%%%s0, %%1", -+ suffix, -+ mode == DImode ? "x" : "w"); -+ return ""; -+} -+ -+/* Count the number of machine instruction that will be emitted for a -+ synchronization instruction. Note that the emitter used does not -+ emit instructions, it just counts instructions being careful not -+ to count labels. */ -+unsigned int -+aarch64_sync_loop_insns (rtx insn, rtx *operands) -+{ -+ aarch64_insn_count = 0; -+ aarch64_process_output_sync_insn (aarch64_count, insn, operands); -+ return aarch64_insn_count; -+} -+ -+/* Helper to call a target sync instruction generator, dealing with -+ the variation in operands required by the different generators. */ -+static rtx -+aarch64_call_generator (struct aarch64_sync_generator *generator, rtx old_value, -+ rtx memory, rtx required_value, rtx new_value) -+{ -+ switch (generator->op) -+ { -+ case aarch64_sync_generator_omn: -+ gcc_assert (! required_value); -+ return generator->u.omn (old_value, memory, new_value); -+ -+ case aarch64_sync_generator_omrn: -+ gcc_assert (required_value); -+ return generator->u.omrn (old_value, memory, required_value, new_value); -+ } -+ -+ return NULL; -+} -+ -+/* Expand a synchronization loop. The synchronization loop is -+ expanded as an opaque block of instructions in order to ensure that -+ we do not subsequently get extraneous memory accesses inserted -+ within the critical region. The exclusive access property of -+ LDXR/STXR instructions is only guaranteed if there are no intervening -+ memory accesses. */ -+void -+aarch64_expand_sync (enum machine_mode mode, -+ struct aarch64_sync_generator *generator, -+ rtx target, rtx memory, rtx required_value, rtx new_value) -+{ -+ if (target == NULL) -+ target = gen_reg_rtx (mode); -+ -+ memory = aarch64_legitimize_sync_memory (memory); -+ if (mode != SImode && mode != DImode) -+ { -+ rtx load_temp = gen_reg_rtx (SImode); -+ -+ if (required_value) -+ required_value = convert_modes (SImode, mode, required_value, true); -+ -+ new_value = convert_modes (SImode, mode, new_value, true); -+ emit_insn (aarch64_call_generator (generator, load_temp, memory, -+ required_value, new_value)); -+ emit_move_insn (target, gen_lowpart (mode, load_temp)); -+ } -+ else -+ { -+ emit_insn (aarch64_call_generator (generator, target, memory, -+ required_value, new_value)); -+ } -+} -+ -+/* Return the equivalent letter for size. */ -+static unsigned char -+sizetochar (int size) -+{ -+ switch (size) -+ { -+ case 64: return 'd'; -+ case 32: return 's'; -+ case 16: return 'h'; -+ case 8 : return 'b'; -+ default: gcc_unreachable (); -+ } -+} -+ -+static int -+aarch64_simd_valid_immediate (rtx op, enum machine_mode mode, int inverse, -+ rtx *modconst, int *elementwidth, -+ unsigned char *elementchar, -+ int *mvn, int *shift) -+{ -+#define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \ -+ matches = 1; \ -+ for (i = 0; i < idx; i += (STRIDE)) \ -+ if (!(TEST)) \ -+ matches = 0; \ -+ if (matches) \ -+ { \ -+ immtype = (CLASS); \ -+ elsize = (ELSIZE); \ -+ elchar = sizetochar (elsize); \ -+ eshift = (SHIFT); \ -+ emvn = (NEG); \ -+ break; \ -+ } -+ -+ unsigned int i, elsize = 0, idx = 0, n_elts = CONST_VECTOR_NUNITS (op); -+ unsigned int innersize = GET_MODE_SIZE (GET_MODE_INNER (mode)); -+ unsigned char bytes[16]; -+ unsigned char elchar = 0; -+ int immtype = -1, matches; -+ unsigned int invmask = inverse ? 0xff : 0; -+ int eshift, emvn; -+ -+ /* TODO: Vectors of float constants. */ -+ if (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) -+ return -1; -+ -+ /* Splat vector constant out into a byte vector. */ -+ for (i = 0; i < n_elts; i++) -+ { -+ rtx el = CONST_VECTOR_ELT (op, i); -+ unsigned HOST_WIDE_INT elpart; -+ unsigned int part, parts; -+ -+ if (GET_CODE (el) == CONST_INT) -+ { -+ elpart = INTVAL (el); -+ parts = 1; -+ } -+ else if (GET_CODE (el) == CONST_DOUBLE) -+ { -+ elpart = CONST_DOUBLE_LOW (el); -+ parts = 2; -+ } -+ else -+ gcc_unreachable (); -+ -+ for (part = 0; part < parts; part++) -+ { -+ unsigned int byte; -+ for (byte = 0; byte < innersize; byte++) -+ { -+ bytes[idx++] = (elpart & 0xff) ^ invmask; -+ elpart >>= BITS_PER_UNIT; -+ } -+ if (GET_CODE (el) == CONST_DOUBLE) -+ elpart = CONST_DOUBLE_HIGH (el); -+ } -+ } -+ -+ /* Sanity check. */ -+ gcc_assert (idx == GET_MODE_SIZE (mode)); -+ -+ do -+ { -+ CHECK (4, 32, 0, bytes[i] == bytes[0] && bytes[i + 1] == 0 -+ && bytes[i + 2] == 0 && bytes[i + 3] == 0, 0, 0); -+ -+ CHECK (4, 32, 1, bytes[i] == 0 && bytes[i + 1] == bytes[1] -+ && bytes[i + 2] == 0 && bytes[i + 3] == 0, 8, 0); -+ -+ CHECK (4, 32, 2, bytes[i] == 0 && bytes[i + 1] == 0 -+ && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0, 16, 0); -+ -+ CHECK (4, 32, 3, bytes[i] == 0 && bytes[i + 1] == 0 -+ && bytes[i + 2] == 0 && bytes[i + 3] == bytes[3], 24, 0); -+ -+ CHECK (2, 16, 4, bytes[i] == bytes[0] && bytes[i + 1] == 0, 0, 0); -+ -+ CHECK (2, 16, 5, bytes[i] == 0 && bytes[i + 1] == bytes[1], 8, 0); -+ -+ CHECK (4, 32, 6, bytes[i] == bytes[0] && bytes[i + 1] == 0xff -+ && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff, 0, 1); -+ -+ CHECK (4, 32, 7, bytes[i] == 0xff && bytes[i + 1] == bytes[1] -+ && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff, 8, 1); -+ -+ CHECK (4, 32, 8, bytes[i] == 0xff && bytes[i + 1] == 0xff -+ && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff, 16, 1); -+ -+ CHECK (4, 32, 9, bytes[i] == 0xff && bytes[i + 1] == 0xff -+ && bytes[i + 2] == 0xff && bytes[i + 3] == bytes[3], 24, 1); -+ -+ CHECK (2, 16, 10, bytes[i] == bytes[0] && bytes[i + 1] == 0xff, 0, 1); -+ -+ CHECK (2, 16, 11, bytes[i] == 0xff && bytes[i + 1] == bytes[1], 8, 1); -+ -+ CHECK (4, 32, 12, bytes[i] == 0xff && bytes[i + 1] == bytes[1] -+ && bytes[i + 2] == 0 && bytes[i + 3] == 0, 0, 0); -+ -+ CHECK (4, 32, 13, bytes[i] == 0 && bytes[i + 1] == bytes[1] -+ && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff, 0, 1); -+ -+ CHECK (4, 32, 14, bytes[i] == 0xff && bytes[i + 1] == 0xff -+ && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0, 0, 0); -+ -+ CHECK (4, 32, 15, bytes[i] == 0 && bytes[i + 1] == 0 -+ && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff, 0, 1); -+ -+ CHECK (1, 8, 16, bytes[i] == bytes[0], 0, 0); -+ -+ CHECK (1, 64, 17, (bytes[i] == 0 || bytes[i] == 0xff) -+ && bytes[i] == bytes[(i + 8) % idx], 0, 0); -+ } -+ while (0); -+ -+ /* TODO: Currently the assembler cannot handle types 12 to 15. -+ And there is no way to specify cmode through the compiler. -+ Disable them till there is support in the assembler. */ -+ if (immtype == -1 -+ || (immtype >= 12 && immtype <= 15) -+ || immtype == 18) -+ return -1; -+ -+ -+ if (elementwidth) -+ *elementwidth = elsize; -+ -+ if (elementchar) -+ *elementchar = elchar; -+ -+ if (mvn) -+ *mvn = emvn; -+ -+ if (shift) -+ *shift = eshift; -+ -+ if (modconst) -+ { -+ unsigned HOST_WIDE_INT imm = 0; -+ -+ /* Un-invert bytes of recognized vector, if necessary. */ -+ if (invmask != 0) -+ for (i = 0; i < idx; i++) -+ bytes[i] ^= invmask; -+ -+ if (immtype == 17) -+ { -+ /* FIXME: Broken on 32-bit H_W_I hosts. */ -+ gcc_assert (sizeof (HOST_WIDE_INT) == 8); -+ -+ for (i = 0; i < 8; i++) -+ imm |= (unsigned HOST_WIDE_INT) (bytes[i] ? 0xff : 0) -+ << (i * BITS_PER_UNIT); -+ -+ *modconst = GEN_INT (imm); -+ } -+ else -+ { -+ unsigned HOST_WIDE_INT imm = 0; -+ -+ for (i = 0; i < elsize / BITS_PER_UNIT; i++) -+ imm |= (unsigned HOST_WIDE_INT) bytes[i] << (i * BITS_PER_UNIT); -+ -+ /* Construct 'abcdefgh' because the assembler cannot handle -+ generic constants. */ -+ gcc_assert (shift != NULL && mvn != NULL); -+ if (*mvn) -+ imm = ~imm; -+ imm = (imm >> *shift) & 0xff; -+ *modconst = GEN_INT (imm); -+ } -+ } -+ -+ return immtype; -+#undef CHECK -+} -+ -+/* Return TRUE if rtx X is legal for use as either a AdvSIMD MOVI instruction -+ (or, implicitly, MVNI) immediate. Write back width per element -+ to *ELEMENTWIDTH (or zero for float elements), and a modified constant -+ (whatever should be output for a MOVI instruction) in *MODCONST. */ -+int -+aarch64_simd_immediate_valid_for_move (rtx op, enum machine_mode mode, -+ rtx *modconst, int *elementwidth, -+ unsigned char *elementchar, -+ int *mvn, int *shift) -+{ -+ rtx tmpconst; -+ int tmpwidth; -+ unsigned char tmpwidthc; -+ int tmpmvn = 0, tmpshift = 0; -+ int retval = aarch64_simd_valid_immediate (op, mode, 0, &tmpconst, -+ &tmpwidth, &tmpwidthc, -+ &tmpmvn, &tmpshift); -+ -+ if (retval == -1) -+ return 0; -+ -+ if (modconst) -+ *modconst = tmpconst; -+ -+ if (elementwidth) -+ *elementwidth = tmpwidth; -+ -+ if (elementchar) -+ *elementchar = tmpwidthc; -+ -+ if (mvn) -+ *mvn = tmpmvn; -+ -+ if (shift) -+ *shift = tmpshift; -+ -+ return 1; -+} -+ -+static bool -+aarch64_const_vec_all_same_int_p (rtx x, -+ HOST_WIDE_INT minval, -+ HOST_WIDE_INT maxval) -+{ -+ HOST_WIDE_INT firstval; -+ int count, i; -+ -+ if (GET_CODE (x) != CONST_VECTOR -+ || GET_MODE_CLASS (GET_MODE (x)) != MODE_VECTOR_INT) -+ return false; -+ -+ firstval = INTVAL (CONST_VECTOR_ELT (x, 0)); -+ if (firstval < minval || firstval > maxval) -+ return false; -+ -+ count = CONST_VECTOR_NUNITS (x); -+ for (i = 1; i < count; i++) -+ if (INTVAL (CONST_VECTOR_ELT (x, i)) != firstval) -+ return false; -+ -+ return true; -+} -+ -+/* Check of immediate shift constants are within range. */ -+bool -+aarch64_simd_shift_imm_p (rtx x, enum machine_mode mode, bool left) -+{ -+ int bit_width = GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT; -+ if (left) -+ return aarch64_const_vec_all_same_int_p (x, 0, bit_width - 1); -+ else -+ return aarch64_const_vec_all_same_int_p (x, 1, bit_width); -+} -+ -+/* Return a const_int vector of VAL. */ -+rtx -+aarch64_simd_gen_const_vector_dup (enum machine_mode mode, int val) -+{ -+ int nunits = GET_MODE_NUNITS (mode); -+ rtvec v = rtvec_alloc (nunits); -+ int i; -+ -+ for (i=0; i < nunits; i++) -+ RTVEC_ELT (v, i) = GEN_INT (val); -+ -+ return gen_rtx_CONST_VECTOR (mode, v); -+} -+ -+/* Construct and return a PARALLEL RTX vector. */ -+rtx -+aarch64_simd_vect_par_cnst_half (enum machine_mode mode, bool high) -+{ -+ int nunits = GET_MODE_NUNITS (mode); -+ rtvec v = rtvec_alloc (nunits / 2); -+ int base = high ? nunits / 2 : 0; -+ rtx t1; -+ int i; -+ -+ for (i=0; i < nunits / 2; i++) -+ RTVEC_ELT (v, i) = GEN_INT (base + i); -+ -+ t1 = gen_rtx_PARALLEL (mode, v); -+ return t1; -+} -+ -+/* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and -+ HIGH (exclusive). */ -+void -+aarch64_simd_lane_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high) -+{ -+ HOST_WIDE_INT lane; -+ gcc_assert (GET_CODE (operand) == CONST_INT); -+ lane = INTVAL (operand); -+ -+ if (lane < low || lane >= high) -+ error ("lane out of range"); -+} -+ -+void -+aarch64_simd_const_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high) -+{ -+ gcc_assert (GET_CODE (operand) == CONST_INT); -+ HOST_WIDE_INT lane = INTVAL (operand); -+ -+ if (lane < low || lane >= high) -+ error ("constant out of range"); -+} -+ -+/* Emit code to reinterpret one AdvSIMD type as another, -+ without altering bits. */ -+void -+aarch64_simd_reinterpret (rtx dest, rtx src) -+{ -+ emit_move_insn (dest, gen_lowpart (GET_MODE (dest), src)); -+} -+ -+/* Emit code to place a AdvSIMD pair result in memory locations (with equal -+ registers). */ -+void -+aarch64_simd_emit_pair_result_insn (enum machine_mode mode, -+ rtx (*intfn) (rtx, rtx, rtx), rtx destaddr, -+ rtx op1) -+{ -+ rtx mem = gen_rtx_MEM (mode, destaddr); -+ rtx tmp1 = gen_reg_rtx (mode); -+ rtx tmp2 = gen_reg_rtx (mode); -+ -+ emit_insn (intfn (tmp1, op1, tmp2)); -+ -+ emit_move_insn (mem, tmp1); -+ mem = adjust_address (mem, mode, GET_MODE_SIZE (mode)); -+ emit_move_insn (mem, tmp2); -+} -+ -+#ifndef TLS_SECTION_ASM_FLAG -+#define TLS_SECTION_ASM_FLAG 'T' -+#endif -+ -+void -+aarch64_elf_asm_named_section (const char *name, unsigned int flags, -+ tree decl ATTRIBUTE_UNUSED) -+{ -+ char flagchars[10], *f = flagchars; -+ -+ /* If we have already declared this section, we can use an -+ abbreviated form to switch back to it -- unless this section is -+ part of a COMDAT groups, in which case GAS requires the full -+ declaration every time. */ -+ if (!(HAVE_COMDAT_GROUP && (flags & SECTION_LINKONCE)) -+ && (flags & SECTION_DECLARED)) -+ { -+ fprintf (asm_out_file, "\t.section\t%s\n", name); -+ return; -+ } -+ -+ if (!(flags & SECTION_DEBUG)) -+ *f++ = 'a'; -+ if (flags & SECTION_WRITE) -+ *f++ = 'w'; -+ if (flags & SECTION_CODE) -+ *f++ = 'x'; -+ if (flags & SECTION_SMALL) -+ *f++ = 's'; -+ if (flags & SECTION_MERGE) -+ *f++ = 'M'; -+ if (flags & SECTION_STRINGS) -+ *f++ = 'S'; -+ if (flags & SECTION_TLS) -+ *f++ = TLS_SECTION_ASM_FLAG; -+ if (HAVE_COMDAT_GROUP && (flags & SECTION_LINKONCE)) -+ *f++ = 'G'; -+ *f = '\0'; -+ -+ fprintf (asm_out_file, "\t.section\t%s,\"%s\"", name, flagchars); -+ -+ if (!(flags & SECTION_NOTYPE)) -+ { -+ const char *type; -+ const char *format; -+ -+ if (flags & SECTION_BSS) -+ type = "nobits"; -+ else -+ type = "progbits"; -+ -+#ifdef TYPE_OPERAND_FMT -+ format = "," TYPE_OPERAND_FMT; -+#else -+ format = ",@%s"; -+#endif -+ -+ fprintf (asm_out_file, format, type); -+ -+ if (flags & SECTION_ENTSIZE) -+ fprintf (asm_out_file, ",%d", flags & SECTION_ENTSIZE); -+ if (HAVE_COMDAT_GROUP && (flags & SECTION_LINKONCE)) -+ { -+ if (TREE_CODE (decl) == IDENTIFIER_NODE) -+ fprintf (asm_out_file, ",%s,comdat", IDENTIFIER_POINTER (decl)); -+ else -+ fprintf (asm_out_file, ",%s,comdat", -+ IDENTIFIER_POINTER (DECL_COMDAT_GROUP (decl))); -+ } -+ } -+ -+ putc ('\n', asm_out_file); -+} -+ -+/* Select a format to encode pointers in exception handling data. */ -+int -+aarch64_asm_preferred_eh_data_format (int code ATTRIBUTE_UNUSED, int global) -+{ -+ int type; -+ switch (aarch64_cmodel) -+ { -+ case AARCH64_CMODEL_TINY: -+ case AARCH64_CMODEL_TINY_PIC: -+ case AARCH64_CMODEL_SMALL: -+ case AARCH64_CMODEL_SMALL_PIC: -+ /* text+got+data < 4Gb. 4-byte signed relocs are sufficient -+ for everything. */ -+ type = DW_EH_PE_sdata4; -+ break; -+ default: -+ /* No assumptions here. 8-byte relocs required. */ -+ type = DW_EH_PE_sdata8; -+ break; -+ } -+ return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type; -+} -+ -+static void -+aarch64_start_file (void) -+{ -+ if (selected_arch) -+ asm_fprintf (asm_out_file, "\t.arch %s\n", selected_arch->name); -+ else if (selected_cpu) -+ asm_fprintf (asm_out_file, "\t.cpu %s\n", selected_cpu->name); -+ default_file_start(); -+} -+ -+/* Target hook for c_mode_for_suffix. */ -+static enum machine_mode -+aarch64_c_mode_for_suffix (char suffix) -+{ -+ if (suffix == 'q') -+ return TFmode; -+ -+ return VOIDmode; -+} -+ -+#undef TARGET_ADDRESS_COST -+#define TARGET_ADDRESS_COST aarch64_address_cost -+ -+/* This hook will determines whether unnamed bitfields affect the alignment -+ of the containing structure. The hook returns true if the structure -+ should inherit the alignment requirements of an unnamed bitfield's -+ type. */ -+#undef TARGET_ALIGN_ANON_BITFIELD -+#define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true -+ -+#undef TARGET_ASM_ALIGNED_DI_OP -+#define TARGET_ASM_ALIGNED_DI_OP "\t.xword\t" -+ -+#undef TARGET_ASM_ALIGNED_HI_OP -+#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" -+ -+#undef TARGET_ASM_ALIGNED_SI_OP -+#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" -+ -+#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK -+#define TARGET_ASM_CAN_OUTPUT_MI_THUNK \ -+ hook_bool_const_tree_hwi_hwi_const_tree_true -+ -+#undef TARGET_ASM_FILE_START -+#define TARGET_ASM_FILE_START aarch64_start_file -+ -+#undef TARGET_ASM_OUTPUT_MI_THUNK -+#define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk -+ -+#undef TARGET_ASM_SELECT_RTX_SECTION -+#define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section -+ -+#undef TARGET_ASM_TRAMPOLINE_TEMPLATE -+#define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template -+ -+#undef TARGET_BUILD_BUILTIN_VA_LIST -+#define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list -+ -+#undef TARGET_CALLEE_COPIES -+#define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false -+ -+#undef TARGET_CAN_ELIMINATE -+#define TARGET_CAN_ELIMINATE aarch64_can_eliminate -+ -+#undef TARGET_CANNOT_FORCE_CONST_MEM -+#define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem -+ -+#undef TARGET_CONDITIONAL_REGISTER_USAGE -+#define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage -+ -+/* Only the least significant bit is used for initialization guard -+ variables. */ -+#undef TARGET_CXX_GUARD_MASK_BIT -+#define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true -+ -+#undef TARGET_C_MODE_FOR_SUFFIX -+#define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix -+ -+#ifdef TARGET_BIG_ENDIAN_DEFAULT -+#undef TARGET_DEFAULT_TARGET_FLAGS -+#define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END) -+#endif -+ -+#undef TARGET_CLASS_MAX_NREGS -+#define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs -+ -+#undef TARGET_EXPAND_BUILTIN -+#define TARGET_EXPAND_BUILTIN aarch64_expand_builtin -+ -+#undef TARGET_EXPAND_BUILTIN_VA_START -+#define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start -+ -+#undef TARGET_FUNCTION_ARG -+#define TARGET_FUNCTION_ARG aarch64_function_arg -+ -+#undef TARGET_FUNCTION_ARG_ADVANCE -+#define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance -+ -+#undef TARGET_FUNCTION_ARG_BOUNDARY -+#define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary -+ -+#undef TARGET_FUNCTION_OK_FOR_SIBCALL -+#define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall -+ -+#undef TARGET_FUNCTION_VALUE -+#define TARGET_FUNCTION_VALUE aarch64_function_value -+ -+#undef TARGET_FUNCTION_VALUE_REGNO_P -+#define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p -+ -+#undef TARGET_FRAME_POINTER_REQUIRED -+#define TARGET_FRAME_POINTER_REQUIRED aarch64_frame_pointer_required -+ -+#undef TARGET_GIMPLIFY_VA_ARG_EXPR -+#define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr -+ -+#undef TARGET_INIT_BUILTINS -+#define TARGET_INIT_BUILTINS aarch64_init_builtins -+ -+#undef TARGET_LEGITIMATE_ADDRESS_P -+#define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p -+ -+#undef TARGET_LEGITIMATE_CONSTANT_P -+#define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p -+ -+#undef TARGET_LIBGCC_CMP_RETURN_MODE -+#define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode -+ -+#undef TARGET_MEMORY_MOVE_COST -+#define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost -+ -+#undef TARGET_MUST_PASS_IN_STACK -+#define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size -+ -+/* This target hook should return true if accesses to volatile bitfields -+ should use the narrowest mode possible. It should return false if these -+ accesses should use the bitfield container type. */ -+#undef TARGET_NARROW_VOLATILE_BITFIELD -+#define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false -+ -+#undef TARGET_OPTION_OVERRIDE -+#define TARGET_OPTION_OVERRIDE aarch64_override_options -+ -+#undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE -+#define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \ -+ aarch64_override_options_after_change -+ -+#undef TARGET_PASS_BY_REFERENCE -+#define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference -+ -+#undef TARGET_PREFERRED_RELOAD_CLASS -+#define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class -+ -+#undef TARGET_SECONDARY_RELOAD -+#define TARGET_SECONDARY_RELOAD aarch64_secondary_reload -+ -+#undef TARGET_SETUP_INCOMING_VARARGS -+#define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs -+ -+#undef TARGET_STRUCT_VALUE_RTX -+#define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx -+ -+#undef TARGET_REGISTER_MOVE_COST -+#define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost -+ -+#undef TARGET_RETURN_IN_MEMORY -+#define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory -+ -+#undef TARGET_RETURN_IN_MSB -+#define TARGET_RETURN_IN_MSB aarch64_return_in_msb -+ -+#undef TARGET_RTX_COSTS -+#define TARGET_RTX_COSTS aarch64_rtx_costs -+ -+#undef TARGET_TRAMPOLINE_INIT -+#define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init -+ -+#undef TARGET_USE_BLOCKS_FOR_CONSTANT_P -+#define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p -+ -+#undef TARGET_VECTOR_MODE_SUPPORTED_P -+#define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p -+ -+#undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE -+#define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode -+ -+struct gcc_target targetm = TARGET_INITIALIZER; -+ -+#include "gt-aarch64.h" - -Property changes on: gcc/config/aarch64/aarch64.c -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/config/aarch64/aarch64-elf-raw.h -=================================================================== ---- a/src/gcc/config/aarch64/aarch64-elf-raw.h (.../gcc-4_7-branch) -+++ b/src/gcc/config/aarch64/aarch64-elf-raw.h (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,32 @@ -+/* Machine description for AArch64 architecture. -+ Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. -+ Contributed by ARM Ltd. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3, or (at your option) -+ any later version. -+ -+ GCC is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+/* Support for bare-metal builds. */ -+#ifndef GCC_AARCH64_ELF_RAW_H -+#define GCC_AARCH64_ELF_RAW_H -+ -+#define STARTFILE_SPEC " crti%O%s crtbegin%O%s crt0%O%s" -+#define ENDFILE_SPEC " crtend%O%s crtn%O%s" -+ -+#ifndef LINK_SPEC -+#define LINK_SPEC "%{mbig-endian:-EB} %{mlittle-endian:-EL} -X" -+#endif -+ -+#endif /* GCC_AARCH64_ELF_RAW_H */ - -Property changes on: gcc/config/aarch64/aarch64-elf-raw.h -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/config/aarch64/aarch64-linux.h -=================================================================== ---- a/src/gcc/config/aarch64/aarch64-linux.h (.../gcc-4_7-branch) -+++ b/src/gcc/config/aarch64/aarch64-linux.h (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,44 @@ -+/* Machine description for AArch64 architecture. -+ Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. -+ Contributed by ARM Ltd. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3, or (at your option) -+ any later version. -+ -+ GCC is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+#ifndef GCC_AARCH64_LINUX_H -+#define GCC_AARCH64_LINUX_H -+ -+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64.so.1" -+ -+#define LINUX_TARGET_LINK_SPEC "%{h*} \ -+ %{static:-Bstatic} \ -+ %{shared:-shared} \ -+ %{symbolic:-Bsymbolic} \ -+ %{rdynamic:-export-dynamic} \ -+ -dynamic-linker " GNU_USER_DYNAMIC_LINKER " \ -+ -X \ -+ %{mbig-endian:-EB} %{mlittle-endian:-EL}" -+ -+#define LINK_SPEC LINUX_TARGET_LINK_SPEC -+ -+#define TARGET_OS_CPP_BUILTINS() \ -+ do \ -+ { \ -+ GNU_USER_TARGET_OS_CPP_BUILTINS(); \ -+ } \ -+ while (0) -+ -+#endif /* GCC_AARCH64_LINUX_H */ - -Property changes on: gcc/config/aarch64/aarch64-linux.h -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/config/aarch64/iterators.md -=================================================================== ---- a/src/gcc/config/aarch64/iterators.md (.../gcc-4_7-branch) -+++ b/src/gcc/config/aarch64/iterators.md (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,598 @@ -+;; Machine description for AArch64 architecture. -+;; Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. -+;; Contributed by ARM Ltd. -+;; -+;; This file is part of GCC. -+;; -+;; GCC is free software; you can redistribute it and/or modify it -+;; under the terms of the GNU General Public License as published by -+;; the Free Software Foundation; either version 3, or (at your option) -+;; any later version. -+;; -+;; GCC is distributed in the hope that it will be useful, but -+;; WITHOUT ANY WARRANTY; without even the implied warranty of -+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+;; General Public License for more details. -+;; -+;; You should have received a copy of the GNU General Public License -+;; along with GCC; see the file COPYING3. If not see -+;; . -+ -+;; ------------------------------------------------------------------- -+;; Mode Iterators -+;; ------------------------------------------------------------------- -+ -+ -+;; Iterator for General Purpose Integer registers (32- and 64-bit modes) -+(define_mode_iterator GPI [SI DI]) -+ -+;; Iterator for QI and HI modes -+(define_mode_iterator SHORT [QI HI]) -+ -+;; Iterator for all integer modes (up to 64-bit) -+(define_mode_iterator ALLI [QI HI SI DI]) -+ -+;; Iterator scalar modes (up to 64-bit) -+(define_mode_iterator SDQ_I [QI HI SI DI]) -+ -+;; Iterator for all integer modes that can be extended (up to 64-bit) -+(define_mode_iterator ALLX [QI HI SI]) -+ -+;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes) -+(define_mode_iterator GPF [SF DF]) -+ -+;; Integer vector modes. -+(define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) -+ -+;; Integer vector modes. -+(define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) -+ -+;; vector and scalar, 64 & 128-bit container, all integer modes -+(define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI]) -+ -+;; vector and scalar, 64 & 128-bit container: all vector integer modes; -+;; 64-bit scalar integer mode -+(define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI]) -+ -+;; Double vector modes. -+(define_mode_iterator VD [V8QI V4HI V2SI V2SF]) -+ -+;; vector, 64-bit container, all integer modes -+(define_mode_iterator VD_BHSI [V8QI V4HI V2SI]) -+ -+;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes -+(define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI]) -+ -+;; Quad vector modes. -+(define_mode_iterator VQ [V16QI V8HI V4SI V2DI V4SF V2DF]) -+ -+;; All vector modes, except double. -+(define_mode_iterator VQ_S [V8QI V16QI V4HI V8HI V2SI V4SI]) -+ -+;; Vector and scalar, 64 & 128-bit container: all vector integer mode; -+;; 8, 16, 32-bit scalar integer modes -+(define_mode_iterator VSDQ_I_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI]) -+ -+;; Vector modes for moves. -+(define_mode_iterator VDQM [V8QI V16QI V4HI V8HI V2SI V4SI]) -+ -+;; This mode iterator allows :PTR to be used for patterns that operate on -+;; pointer-sized quantities. Exactly one of the two alternatives will match. -+(define_mode_iterator PTR [(SI "Pmode == SImode") (DI "Pmode == DImode")]) -+ -+;; Vector Float modes. -+(define_mode_iterator VDQF [V2SF V4SF V2DF]) -+ -+;; Vector Float modes with 2 elements. -+(define_mode_iterator V2F [V2SF V2DF]) -+ -+;; All modes. -+(define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF]) -+ -+;; Vector modes for Integer reduction across lanes. -+(define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI]) -+ -+;; All double integer narrow-able modes. -+(define_mode_iterator VDN [V4HI V2SI DI]) -+ -+;; All quad integer narrow-able modes. -+(define_mode_iterator VQN [V8HI V4SI V2DI]) -+ -+;; All double integer widen-able modes. -+(define_mode_iterator VDW [V8QI V4HI V2SI]) -+ -+;; Vector and scalar 128-bit container: narrowable 16, 32, 64-bit integer modes -+(define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI]) -+ -+;; All quad integer widen-able modes. -+(define_mode_iterator VQW [V16QI V8HI V4SI]) -+ -+;; Double vector modes for combines. -+(define_mode_iterator VDC [V8QI V4HI V2SI V2SF DI DF]) -+ -+;; Double vector modes. -+(define_mode_iterator VD_RE [V8QI V4HI V2SI DI DF V2SF]) -+ -+;; Vector modes except double int. -+(define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF]) -+ -+;; Vector modes for H and S types. -+(define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI]) -+ -+;; Vector and scalar integer modes for H and S -+(define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI]) -+ -+;; Vector and scalar 64-bit container: 16, 32-bit integer modes -+(define_mode_iterator VSD_HSI [V4HI V2SI HI SI]) -+ -+;; Vector 64-bit container: 16, 32-bit integer modes -+(define_mode_iterator VD_HSI [V4HI V2SI]) -+ -+;; Scalar 64-bit container: 16, 32-bit integer modes -+(define_mode_iterator SD_HSI [HI SI]) -+ -+;; Vector 64-bit container: 16, 32-bit integer modes -+(define_mode_iterator VQ_HSI [V8HI V4SI]) -+ -+;; All byte modes. -+(define_mode_iterator VB [V8QI V16QI]) -+ -+(define_mode_iterator TX [TI TF]) -+ -+;; ------------------------------------------------------------------- -+;; Mode attributes -+;; ------------------------------------------------------------------- -+ -+;; In GPI templates, a string like "%0" will expand to "%w0" in the -+;; 32-bit version and "%x0" in the 64-bit version. -+(define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")]) -+ -+;; For scalar usage of vector/FP registers -+(define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d") -+ (V8QI "") (V16QI "") -+ (V4HI "") (V8HI "") -+ (V2SI "") (V4SI "") -+ (V2DI "") (V2SF "") -+ (V4SF "") (V2DF "")]) -+ -+;; For scalar usage of vector/FP registers, narrowing -+(define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s") -+ (V8QI "") (V16QI "") -+ (V4HI "") (V8HI "") -+ (V2SI "") (V4SI "") -+ (V2DI "") (V2SF "") -+ (V4SF "") (V2DF "")]) -+ -+;; For scalar usage of vector/FP registers, widening -+(define_mode_attr vw2 [(DI "") (QI "h") (HI "s") (SI "d") -+ (V8QI "") (V16QI "") -+ (V4HI "") (V8HI "") -+ (V2SI "") (V4SI "") -+ (V2DI "") (V2SF "") -+ (V4SF "") (V2DF "")]) -+ -+;; Map a floating point mode to the appropriate register name prefix -+(define_mode_attr s [(SF "s") (DF "d")]) -+ -+;; Give the length suffix letter for a sign- or zero-extension. -+(define_mode_attr size [(QI "b") (HI "h") (SI "w")]) -+ -+;; Give the number of bits in the mode -+(define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")]) -+ -+;; Give the ordinal of the MSB in the mode -+(define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63")]) -+ -+;; Attribute to describe constants acceptable in logical operations -+(define_mode_attr lconst [(SI "K") (DI "L")]) -+ -+;; Map a mode to a specific constraint character. -+(define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")]) -+ -+(define_mode_attr Vtype [(V8QI "8b") (V16QI "16b") -+ (V4HI "4h") (V8HI "8h") -+ (V2SI "2s") (V4SI "4s") -+ (V2DI "2d") (V2SF "2s") -+ (V4SF "4s") (V2DF "2d")]) -+ -+(define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b") -+ (V4HI ".4h") (V8HI ".8h") -+ (V2SI ".2s") (V4SI ".4s") -+ (V2DI ".2d") (V2SF ".2s") -+ (V4SF ".4s") (V2DF ".2d") -+ (DI "") (SI "") -+ (HI "") (QI "") -+ (TI "")]) -+ -+;; Register suffix narrowed modes for VQN. -+(define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h") -+ (V2DI ".2s") -+ (DI "") (SI "") -+ (HI "")]) -+ -+;; Mode-to-individual element type mapping. -+(define_mode_attr Vetype [(V8QI "b") (V16QI "b") -+ (V4HI "h") (V8HI "h") -+ (V2SI "s") (V4SI "s") -+ (V2DI "d") (V2SF "s") -+ (V4SF "s") (V2DF "d") -+ (QI "b") (HI "h") -+ (SI "s") (DI "d")]) -+ -+;; Mode-to-bitwise operation type mapping. -+(define_mode_attr Vbtype [(V8QI "8b") (V16QI "16b") -+ (V4HI "8b") (V8HI "16b") -+ (V2SI "8b") (V4SI "16b") -+ (V2DI "16b") (V2SF "8b") -+ (V4SF "16b") (V2DF "16b")]) -+ -+;; Define element mode for each vector mode. -+(define_mode_attr VEL [(V8QI "QI") (V16QI "QI") -+ (V4HI "HI") (V8HI "HI") -+ (V2SI "SI") (V4SI "SI") -+ (DI "DI") (V2DI "DI") -+ (V2SF "SF") (V4SF "SF") -+ (V2DF "DF") -+ (SI "SI") (HI "HI") -+ (QI "QI")]) -+ -+;; Define container mode for lane selection. -+(define_mode_attr VCON [(V8QI "V16QI") (V16QI "V16QI") -+ (V4HI "V8HI") (V8HI "V8HI") -+ (V2SI "V4SI") (V4SI "V4SI") -+ (DI "V2DI") (V2DI "V2DI") -+ (V2SF "V2SF") (V4SF "V4SF") -+ (V2DF "V2DF") (SI "V4SI") -+ (HI "V8HI") (QI "V16QI")]) -+ -+;; Half modes of all vector modes. -+(define_mode_attr VHALF [(V8QI "V4QI") (V16QI "V8QI") -+ (V4HI "V2HI") (V8HI "V4HI") -+ (V2SI "SI") (V4SI "V2SI") -+ (V2DI "DI") (V2SF "SF") -+ (V4SF "V2SF") (V2DF "DF")]) -+ -+;; Double modes of vector modes. -+(define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI") -+ (V2SI "V4SI") (V2SF "V4SF") -+ (SI "V2SI") (DI "V2DI") -+ (DF "V2DF")]) -+ -+;; Double modes of vector modes (lower case). -+(define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi") -+ (V2SI "v4si") (V2SF "v4sf") -+ (SI "v2si") (DI "v2di")]) -+ -+;; Narrowed modes for VDN. -+(define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI") -+ (DI "V2SI")]) -+ -+;; Narrowed double-modes for VQN (Used for XTN). -+(define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI") -+ (V2DI "V2SI") -+ (DI "SI") (SI "HI") -+ (HI "QI")]) -+ -+;; Narrowed quad-modes for VQN (Used for XTN2). -+(define_mode_attr VNARROWQ2 [(V8HI "V16QI") (V4SI "V8HI") -+ (V2DI "V4SI")]) -+ -+;; Register suffix narrowed modes for VQN. -+(define_mode_attr Vntype [(V8HI "8b") (V4SI "4h") -+ (V2DI "2s")]) -+ -+;; Register suffix narrowed modes for VQN. -+(define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h") -+ (V2DI "4s")]) -+ -+;; Widened modes of vector modes. -+(define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI") -+ (V2SI "V2DI") (V16QI "V8HI") -+ (V8HI "V4SI") (V4SI "V2DI") -+ (HI "SI") (SI "DI")] -+ -+) -+ -+;; Widened mode register suffixes for VDW/VQW. -+(define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s") -+ (V2SI "2d") (V16QI "8h") -+ (V8HI "4s") (V4SI "2d")]) -+ -+;; Widened mode register suffixes for VDW/VQW. -+(define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s") -+ (V2SI ".2d") (V16QI ".8h") -+ (V8HI ".4s") (V4SI ".2d") -+ (SI "") (HI "")]) -+ -+;; Lower part register suffixes for VQW. -+(define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h") -+ (V4SI "2s")]) -+ -+;; Define corresponding core/FP element mode for each vector mode. -+(define_mode_attr vw [(V8QI "w") (V16QI "w") -+ (V4HI "w") (V8HI "w") -+ (V2SI "w") (V4SI "w") -+ (DI "x") (V2DI "x") -+ (V2SF "s") (V4SF "s") -+ (V2DF "d")]) -+ -+;; Double vector types for ALLX. -+(define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")]) -+ -+;; Mode of result of comparison operations. -+(define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI") -+ (V4HI "V4HI") (V8HI "V8HI") -+ (V2SI "V2SI") (V4SI "V4SI") -+ (V2SF "V2SI") (V4SF "V4SI") -+ (DI "DI") (V2DI "V2DI")]) -+ -+;; Vm for lane instructions is restricted to FP_LO_REGS. -+(define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x") -+ (V2SI "w") (V4SI "w") (SI "w")]) -+ -+;; ------------------------------------------------------------------- -+;; Code Iterators -+;; ------------------------------------------------------------------- -+ -+;; This code iterator allows the various shifts supported on the core -+(define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert]) -+ -+;; This code iterator allows the shifts supported in arithmetic instructions -+(define_code_iterator ASHIFT [ashift ashiftrt lshiftrt]) -+ -+;; Code iterator for logical operations -+(define_code_iterator LOGICAL [and ior xor]) -+ -+;; Code iterator for sign/zero extension -+(define_code_iterator ANY_EXTEND [sign_extend zero_extend]) -+ -+;; All division operations (signed/unsigned) -+(define_code_iterator ANY_DIV [div udiv]) -+ -+;; Code iterator for sign/zero extraction -+(define_code_iterator ANY_EXTRACT [sign_extract zero_extract]) -+ -+;; Code iterator for equality comparisons -+(define_code_iterator EQL [eq ne]) -+ -+;; Code iterator for less-than and greater/equal-to -+(define_code_iterator LTGE [lt ge]) -+ -+;; Iterator for __sync_ operations that where the operation can be -+;; represented directly RTL. This is all of the sync operations bar -+;; nand. -+(define_code_iterator syncop [plus minus ior xor and]) -+ -+;; Iterator for integer conversions -+(define_code_iterator FIXUORS [fix unsigned_fix]) -+ -+;; Code iterator for variants of vector max and min. -+(define_code_iterator MAXMIN [smax smin umax umin]) -+ -+;; Code iterator for variants of vector max and min. -+(define_code_iterator ADDSUB [plus minus]) -+ -+;; Code iterator for variants of vector saturating binary ops. -+(define_code_iterator BINQOPS [ss_plus us_plus ss_minus us_minus]) -+ -+;; Code iterator for variants of vector saturating unary ops. -+(define_code_iterator UNQOPS [ss_neg ss_abs]) -+ -+;; Code iterator for signed variants of vector saturating binary ops. -+(define_code_iterator SBINQOPS [ss_plus ss_minus]) -+ -+;; ------------------------------------------------------------------- -+;; Code Attributes -+;; ------------------------------------------------------------------- -+;; Map rtl objects to optab names -+(define_code_attr optab [(ashift "ashl") -+ (ashiftrt "ashr") -+ (lshiftrt "lshr") -+ (rotatert "rotr") -+ (sign_extend "extend") -+ (zero_extend "zero_extend") -+ (sign_extract "extv") -+ (zero_extract "extzv") -+ (and "and") -+ (ior "ior") -+ (xor "xor") -+ (not "one_cmpl") -+ (neg "neg") -+ (plus "add") -+ (minus "sub") -+ (ss_plus "qadd") -+ (us_plus "qadd") -+ (ss_minus "qsub") -+ (us_minus "qsub") -+ (ss_neg "qneg") -+ (ss_abs "qabs") -+ (eq "eq") -+ (ne "ne") -+ (lt "lt") -+ (ge "ge")]) -+ -+;; Optab prefix for sign/zero-extending operations -+(define_code_attr su_optab [(sign_extend "") (zero_extend "u") -+ (div "") (udiv "u") -+ (fix "") (unsigned_fix "u") -+ (ss_plus "s") (us_plus "u") -+ (ss_minus "s") (us_minus "u")]) -+ -+;; Similar for the instruction mnemonics -+(define_code_attr shift [(ashift "lsl") (ashiftrt "asr") -+ (lshiftrt "lsr") (rotatert "ror")]) -+ -+;; Map shift operators onto underlying bit-field instructions -+(define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx") -+ (lshiftrt "ubfx") (rotatert "extr")]) -+ -+;; Logical operator instruction mnemonics -+(define_code_attr logical [(and "and") (ior "orr") (xor "eor")]) -+ -+;; Similar, but when not(op) -+(define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")]) -+ -+;; Sign- or zero-extending load -+(define_code_attr ldrxt [(sign_extend "ldrs") (zero_extend "ldr")]) -+ -+;; Sign- or zero-extending data-op -+(define_code_attr su [(sign_extend "s") (zero_extend "u") -+ (sign_extract "s") (zero_extract "u") -+ (fix "s") (unsigned_fix "u") -+ (div "s") (udiv "u")]) -+ -+;; Emit cbz/cbnz depending on comparison type. -+(define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")]) -+ -+;; Emit tbz/tbnz depending on comparison type. -+(define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")]) -+ -+;; Max/min attributes. -+(define_code_attr maxmin [(smax "smax") -+ (smin "smin") -+ (umax "umax") -+ (umin "umin")]) -+ -+;; MLA/MLS attributes. -+(define_code_attr as [(ss_plus "a") (ss_minus "s")]) -+ -+ -+;; ------------------------------------------------------------------- -+;; Int Iterators. -+;; ------------------------------------------------------------------- -+(define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV -+ UNSPEC_SMAXV UNSPEC_SMINV]) -+ -+(define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV]) -+ -+(define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD -+ UNSPEC_SRHADD UNSPEC_URHADD -+ UNSPEC_SHSUB UNSPEC_UHSUB -+ UNSPEC_SRHSUB UNSPEC_URHSUB]) -+ -+ -+(define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN -+ UNSPEC_SUBHN UNSPEC_RSUBHN]) -+ -+(define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2 -+ UNSPEC_SUBHN2 UNSPEC_RSUBHN2]) -+ -+(define_int_iterator FMAXMIN [UNSPEC_FMAX UNSPEC_FMIN]) -+ -+(define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH]) -+ -+(define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD]) -+ -+(define_int_iterator SUQMOVN [UNSPEC_SQXTN UNSPEC_UQXTN]) -+ -+(define_int_iterator VSHL [UNSPEC_SSHL UNSPEC_USHL -+ UNSPEC_SRSHL UNSPEC_URSHL]) -+ -+(define_int_iterator VSHLL [UNSPEC_SSHLL UNSPEC_USHLL]) -+ -+(define_int_iterator VQSHL [UNSPEC_SQSHL UNSPEC_UQSHL -+ UNSPEC_SQRSHL UNSPEC_UQRSHL]) -+ -+(define_int_iterator VSRA [UNSPEC_SSRA UNSPEC_USRA -+ UNSPEC_SRSRA UNSPEC_URSRA]) -+ -+(define_int_iterator VSLRI [UNSPEC_SSLI UNSPEC_USLI -+ UNSPEC_SSRI UNSPEC_USRI]) -+ -+ -+(define_int_iterator VRSHR_N [UNSPEC_SRSHR UNSPEC_URSHR]) -+ -+(define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL]) -+ -+(define_int_iterator VQSHRN_N [UNSPEC_SQSHRUN UNSPEC_SQRSHRUN -+ UNSPEC_SQSHRN UNSPEC_UQSHRN -+ UNSPEC_SQRSHRN UNSPEC_UQRSHRN]) -+ -+(define_int_iterator VCMP_S [UNSPEC_CMEQ UNSPEC_CMGE UNSPEC_CMGT -+ UNSPEC_CMLE UNSPEC_CMLT]) -+ -+(define_int_iterator VCMP_U [UNSPEC_CMHS UNSPEC_CMHI UNSPEC_CMTST]) -+ -+ -+;; ------------------------------------------------------------------- -+;; Int Iterators Attributes. -+;; ------------------------------------------------------------------- -+(define_int_attr maxminv [(UNSPEC_UMAXV "umax") -+ (UNSPEC_UMINV "umin") -+ (UNSPEC_SMAXV "smax") -+ (UNSPEC_SMINV "smin")]) -+ -+(define_int_attr fmaxminv [(UNSPEC_FMAXV "max") -+ (UNSPEC_FMINV "min")]) -+ -+(define_int_attr fmaxmin [(UNSPEC_FMAX "fmax") -+ (UNSPEC_FMIN "fmin")]) -+ -+(define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u") -+ (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur") -+ (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u") -+ (UNSPEC_SRHSUB "sr") (UNSPEC_URHSUB "ur") -+ (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r") -+ (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r") -+ (UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r") -+ (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r") -+ (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u") -+ (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su") -+ (UNSPEC_SSLI "s") (UNSPEC_USLI "u") -+ (UNSPEC_SSRI "s") (UNSPEC_USRI "u") -+ (UNSPEC_USRA "u") (UNSPEC_SSRA "s") -+ (UNSPEC_URSRA "ur") (UNSPEC_SRSRA "sr") -+ (UNSPEC_URSHR "ur") (UNSPEC_SRSHR "sr") -+ (UNSPEC_SQSHLU "s") (UNSPEC_SQSHL "s") -+ (UNSPEC_UQSHL "u") -+ (UNSPEC_SQSHRUN "s") (UNSPEC_SQRSHRUN "s") -+ (UNSPEC_SQSHRN "s") (UNSPEC_UQSHRN "u") -+ (UNSPEC_SQRSHRN "s") (UNSPEC_UQRSHRN "u") -+ (UNSPEC_USHL "u") (UNSPEC_SSHL "s") -+ (UNSPEC_USHLL "u") (UNSPEC_SSHLL "s") -+ (UNSPEC_URSHL "ur") (UNSPEC_SRSHL "sr") -+ (UNSPEC_UQRSHL "u") (UNSPEC_SQRSHL "s") -+]) -+ -+(define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r") -+ (UNSPEC_SQSHRUN "") (UNSPEC_SQRSHRUN "r") -+ (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "") -+ (UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r") -+ (UNSPEC_SQSHL "") (UNSPEC_UQSHL "") -+ (UNSPEC_SQRSHL "r")(UNSPEC_UQRSHL "r") -+]) -+ -+(define_int_attr lr [(UNSPEC_SSLI "l") (UNSPEC_USLI "l") -+ (UNSPEC_SSRI "r") (UNSPEC_USRI "r")]) -+ -+(define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "") -+ (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u") -+ (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "") -+ (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "")]) -+ -+(define_int_attr addsub [(UNSPEC_SHADD "add") -+ (UNSPEC_UHADD "add") -+ (UNSPEC_SRHADD "add") -+ (UNSPEC_URHADD "add") -+ (UNSPEC_SHSUB "sub") -+ (UNSPEC_UHSUB "sub") -+ (UNSPEC_SRHSUB "sub") -+ (UNSPEC_URHSUB "sub") -+ (UNSPEC_ADDHN "add") -+ (UNSPEC_SUBHN "sub") -+ (UNSPEC_RADDHN "add") -+ (UNSPEC_RSUBHN "sub") -+ (UNSPEC_ADDHN2 "add") -+ (UNSPEC_SUBHN2 "sub") -+ (UNSPEC_RADDHN2 "add") -+ (UNSPEC_RSUBHN2 "sub")]) -+ -+(define_int_attr cmp [(UNSPEC_CMGE "ge") (UNSPEC_CMGT "gt") -+ (UNSPEC_CMLE "le") (UNSPEC_CMLT "lt") -+ (UNSPEC_CMEQ "eq") -+ (UNSPEC_CMHS "hs") (UNSPEC_CMHI "hi") -+ (UNSPEC_CMTST "tst")]) -+ -+(define_int_attr offsetlr [(UNSPEC_SSLI "1") (UNSPEC_USLI "1") -+ (UNSPEC_SSRI "0") (UNSPEC_USRI "0")]) -+ -Index: gcc/config/aarch64/sync.md -=================================================================== ---- a/src/gcc/config/aarch64/sync.md (.../gcc-4_7-branch) -+++ b/src/gcc/config/aarch64/sync.md (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,457 @@ -+;; Machine description for AArch64 processor synchronization primitives. -+;; Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. -+;; Contributed by ARM Ltd. -+;; -+;; This file is part of GCC. -+;; -+;; GCC is free software; you can redistribute it and/or modify it -+;; under the terms of the GNU General Public License as published by -+;; the Free Software Foundation; either version 3, or (at your option) -+;; any later version. -+;; -+;; GCC is distributed in the hope that it will be useful, but -+;; WITHOUT ANY WARRANTY; without even the implied warranty of -+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+;; General Public License for more details. -+;; -+;; You should have received a copy of the GNU General Public License -+;; along with GCC; see the file COPYING3. If not see -+;; . -+ -+(define_expand "sync_compare_and_swap" -+ [(set (match_operand:ALLI 0 "register_operand") -+ (unspec_volatile:ALLI [(match_operand:ALLI 1 "memory_operand") -+ (match_operand:ALLI 2 "register_operand") -+ (match_operand:ALLI 3 "register_operand")] -+ UNSPECV_SYNC_COMPARE_AND_SWAP))] -+ "" -+ { -+ struct aarch64_sync_generator generator; -+ generator.op = aarch64_sync_generator_omrn; -+ generator.u.omrn = gen_aarch64_sync_compare_and_swap; -+ aarch64_expand_sync (mode, &generator, operands[0], operands[1], -+ operands[2], operands[3]); -+ DONE; -+ }) -+ -+(define_expand "sync_lock_test_and_set" -+ [(match_operand:ALLI 0 "register_operand") -+ (match_operand:ALLI 1 "memory_operand") -+ (match_operand:ALLI 2 "register_operand")] -+ "" -+ { -+ struct aarch64_sync_generator generator; -+ generator.op = aarch64_sync_generator_omn; -+ generator.u.omn = gen_aarch64_sync_lock_test_and_set; -+ aarch64_expand_sync (mode, &generator, operands[0], operands[1], -+ NULL, operands[2]); -+ DONE; -+ }) -+ -+(define_expand "sync_" -+ [(match_operand:ALLI 0 "memory_operand") -+ (match_operand:ALLI 1 "register_operand") -+ (syncop:ALLI (match_dup 0) (match_dup 1))] -+ "" -+ { -+ struct aarch64_sync_generator generator; -+ generator.op = aarch64_sync_generator_omn; -+ generator.u.omn = gen_aarch64_sync_new_; -+ aarch64_expand_sync (mode, &generator, NULL, operands[0], NULL, -+ operands[1]); -+ DONE; -+ }) -+ -+(define_expand "sync_nand" -+ [(match_operand:ALLI 0 "memory_operand") -+ (match_operand:ALLI 1 "register_operand") -+ (not:ALLI (and:ALLI (match_dup 0) (match_dup 1)))] -+ "" -+ { -+ struct aarch64_sync_generator generator; -+ generator.op = aarch64_sync_generator_omn; -+ generator.u.omn = gen_aarch64_sync_new_nand; -+ aarch64_expand_sync (mode, &generator, NULL, operands[0], NULL, -+ operands[1]); -+ DONE; -+ }) -+ -+(define_expand "sync_new_" -+ [(match_operand:ALLI 0 "register_operand") -+ (match_operand:ALLI 1 "memory_operand") -+ (match_operand:ALLI 2 "register_operand") -+ (syncop:ALLI (match_dup 1) (match_dup 2))] -+ "" -+ { -+ struct aarch64_sync_generator generator; -+ generator.op = aarch64_sync_generator_omn; -+ generator.u.omn = gen_aarch64_sync_new_; -+ aarch64_expand_sync (mode, &generator, operands[0], operands[1], -+ NULL, operands[2]); -+ DONE; -+ }) -+ -+(define_expand "sync_new_nand" -+ [(match_operand:ALLI 0 "register_operand") -+ (match_operand:ALLI 1 "memory_operand") -+ (match_operand:ALLI 2 "register_operand") -+ (not:ALLI (and:ALLI (match_dup 1) (match_dup 2)))] -+ "" -+ { -+ struct aarch64_sync_generator generator; -+ generator.op = aarch64_sync_generator_omn; -+ generator.u.omn = gen_aarch64_sync_new_nand; -+ aarch64_expand_sync (mode, &generator, operands[0], operands[1], -+ NULL, operands[2]); -+ DONE; -+ }); -+ -+(define_expand "sync_old_" -+ [(match_operand:ALLI 0 "register_operand") -+ (match_operand:ALLI 1 "memory_operand") -+ (match_operand:ALLI 2 "register_operand") -+ (syncop:ALLI (match_dup 1) (match_dup 2))] -+ "" -+ { -+ struct aarch64_sync_generator generator; -+ generator.op = aarch64_sync_generator_omn; -+ generator.u.omn = gen_aarch64_sync_old_; -+ aarch64_expand_sync (mode, &generator, operands[0], operands[1], -+ NULL, operands[2]); -+ DONE; -+ }) -+ -+(define_expand "sync_old_nand" -+ [(match_operand:ALLI 0 "register_operand") -+ (match_operand:ALLI 1 "memory_operand") -+ (match_operand:ALLI 2 "register_operand") -+ (not:ALLI (and:ALLI (match_dup 1) (match_dup 2)))] -+ "" -+ { -+ struct aarch64_sync_generator generator; -+ generator.op = aarch64_sync_generator_omn; -+ generator.u.omn = gen_aarch64_sync_old_nand; -+ aarch64_expand_sync (mode, &generator, operands[0], operands[1], -+ NULL, operands[2]); -+ DONE; -+ }) -+ -+(define_expand "memory_barrier" -+ [(set (match_dup 0) (unspec:BLK [(match_dup 0)] UNSPEC_MB))] -+ "" -+{ -+ operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); -+ MEM_VOLATILE_P (operands[0]) = 1; -+}) -+ -+(define_insn "aarch64_sync_compare_and_swap" -+ [(set (match_operand:GPI 0 "register_operand" "=&r") -+ (unspec_volatile:GPI -+ [(match_operand:GPI 1 "aarch64_sync_memory_operand" "+Q") -+ (match_operand:GPI 2 "register_operand" "r") -+ (match_operand:GPI 3 "register_operand" "r")] -+ UNSPECV_SYNC_COMPARE_AND_SWAP)) -+ (set (match_dup 1) (unspec_volatile:GPI [(match_dup 2)] -+ UNSPECV_SYNC_COMPARE_AND_SWAP)) -+ (clobber:GPI (match_scratch:GPI 4 "=&r")) -+ (set (reg:CC CC_REGNUM) (unspec_volatile:CC [(match_dup 1)] -+ UNSPECV_SYNC_COMPARE_AND_SWAP)) -+ ] -+ "" -+ { -+ return aarch64_output_sync_insn (insn, operands); -+ } -+ [(set_attr "sync_result" "0") -+ (set_attr "sync_memory" "1") -+ (set_attr "sync_required_value" "2") -+ (set_attr "sync_new_value" "3") -+ (set_attr "sync_t1" "0") -+ (set_attr "sync_t2" "4") -+ ]) -+ -+(define_insn "aarch64_sync_compare_and_swap" -+ [(set (match_operand:SI 0 "register_operand" "=&r") -+ (zero_extend:SI -+ (unspec_volatile:SHORT -+ [(match_operand:SHORT 1 "aarch64_sync_memory_operand" "+Q") -+ (match_operand:SI 2 "register_operand" "r") -+ (match_operand:SI 3 "register_operand" "r")] -+ UNSPECV_SYNC_COMPARE_AND_SWAP))) -+ (set (match_dup 1) (unspec_volatile:SHORT [(match_dup 2)] -+ UNSPECV_SYNC_COMPARE_AND_SWAP)) -+ (clobber:SI (match_scratch:SI 4 "=&r")) -+ (set (reg:CC CC_REGNUM) (unspec_volatile:CC [(match_dup 1)] -+ UNSPECV_SYNC_COMPARE_AND_SWAP)) -+ ] -+ "" -+ { -+ return aarch64_output_sync_insn (insn, operands); -+ } -+ [(set_attr "sync_result" "0") -+ (set_attr "sync_memory" "1") -+ (set_attr "sync_required_value" "2") -+ (set_attr "sync_new_value" "3") -+ (set_attr "sync_t1" "0") -+ (set_attr "sync_t2" "4") -+ ]) -+ -+(define_insn "aarch64_sync_lock_test_and_set" -+ [(set (match_operand:GPI 0 "register_operand" "=&r") -+ (match_operand:GPI 1 "aarch64_sync_memory_operand" "+Q")) -+ (set (match_dup 1) -+ (unspec_volatile:GPI [(match_operand:GPI 2 "register_operand" "r")] -+ UNSPECV_SYNC_LOCK)) -+ (clobber (reg:CC CC_REGNUM)) -+ (clobber (match_scratch:GPI 3 "=&r"))] -+ "" -+ { -+ return aarch64_output_sync_insn (insn, operands); -+ } -+ [(set_attr "sync_release_barrier" "no") -+ (set_attr "sync_result" "0") -+ (set_attr "sync_memory" "1") -+ (set_attr "sync_new_value" "2") -+ (set_attr "sync_t1" "0") -+ (set_attr "sync_t2" "3") -+ ]) -+ -+(define_insn "aarch64_sync_lock_test_and_set" -+ [(set (match_operand:SI 0 "register_operand" "=&r") -+ (zero_extend:SI (match_operand:SHORT 1 -+ "aarch64_sync_memory_operand" "+Q"))) -+ (set (match_dup 1) -+ (unspec_volatile:SHORT [(match_operand:SI 2 "register_operand" "r")] -+ UNSPECV_SYNC_LOCK)) -+ (clobber (reg:CC CC_REGNUM)) -+ (clobber (match_scratch:SI 3 "=&r"))] -+ "" -+ { -+ return aarch64_output_sync_insn (insn, operands); -+ } -+ [(set_attr "sync_release_barrier" "no") -+ (set_attr "sync_result" "0") -+ (set_attr "sync_memory" "1") -+ (set_attr "sync_new_value" "2") -+ (set_attr "sync_t1" "0") -+ (set_attr "sync_t2" "3") -+ ]) -+ -+(define_insn "aarch64_sync_new_" -+ [(set (match_operand:GPI 0 "register_operand" "=&r") -+ (unspec_volatile:GPI -+ [(syncop:GPI -+ (match_operand:GPI 1 "aarch64_sync_memory_operand" "+Q") -+ (match_operand:GPI 2 "register_operand" "r"))] -+ UNSPECV_SYNC_NEW_OP)) -+ (set (match_dup 1) -+ (unspec_volatile:GPI [(match_dup 1) (match_dup 2)] -+ UNSPECV_SYNC_NEW_OP)) -+ (clobber (reg:CC CC_REGNUM)) -+ (clobber (match_scratch:GPI 3 "=&r"))] -+ "" -+ { -+ return aarch64_output_sync_insn (insn, operands); -+ } -+ [(set_attr "sync_result" "0") -+ (set_attr "sync_memory" "1") -+ (set_attr "sync_new_value" "2") -+ (set_attr "sync_t1" "0") -+ (set_attr "sync_t2" "3") -+ (set_attr "sync_op" "") -+ ]) -+ -+(define_insn "aarch64_sync_new_nand" -+ [(set (match_operand:GPI 0 "register_operand" "=&r") -+ (unspec_volatile:GPI -+ [(not:GPI (and:GPI -+ (match_operand:GPI 1 "aarch64_sync_memory_operand" "+Q") -+ (match_operand:GPI 2 "register_operand" "r")))] -+ UNSPECV_SYNC_NEW_OP)) -+ (set (match_dup 1) -+ (unspec_volatile:GPI [(match_dup 1) (match_dup 2)] -+ UNSPECV_SYNC_NEW_OP)) -+ (clobber (reg:CC CC_REGNUM)) -+ (clobber (match_scratch:GPI 3 "=&r"))] -+ "" -+ { -+ return aarch64_output_sync_insn (insn, operands); -+ } -+ [(set_attr "sync_result" "0") -+ (set_attr "sync_memory" "1") -+ (set_attr "sync_new_value" "2") -+ (set_attr "sync_t1" "0") -+ (set_attr "sync_t2" "3") -+ (set_attr "sync_op" "nand") -+ ]) -+ -+(define_insn "aarch64_sync_new_" -+ [(set (match_operand:SI 0 "register_operand" "=&r") -+ (unspec_volatile:SI -+ [(syncop:SI -+ (zero_extend:SI -+ (match_operand:SHORT 1 "aarch64_sync_memory_operand" "+Q")) -+ (match_operand:SI 2 "register_operand" "r"))] -+ UNSPECV_SYNC_NEW_OP)) -+ (set (match_dup 1) -+ (unspec_volatile:SHORT [(match_dup 1) (match_dup 2)] -+ UNSPECV_SYNC_NEW_OP)) -+ (clobber (reg:CC CC_REGNUM)) -+ (clobber (match_scratch:SI 3 "=&r"))] -+ "" -+ { -+ return aarch64_output_sync_insn (insn, operands); -+ } -+ [(set_attr "sync_result" "0") -+ (set_attr "sync_memory" "1") -+ (set_attr "sync_new_value" "2") -+ (set_attr "sync_t1" "0") -+ (set_attr "sync_t2" "3") -+ (set_attr "sync_op" "") -+ ]) -+ -+(define_insn "aarch64_sync_new_nand" -+ [(set (match_operand:SI 0 "register_operand" "=&r") -+ (unspec_volatile:SI -+ [(not:SI -+ (and:SI -+ (zero_extend:SI -+ (match_operand:SHORT 1 "aarch64_sync_memory_operand" "+Q")) -+ (match_operand:SI 2 "register_operand" "r"))) -+ ] UNSPECV_SYNC_NEW_OP)) -+ (set (match_dup 1) -+ (unspec_volatile:SHORT [(match_dup 1) (match_dup 2)] -+ UNSPECV_SYNC_NEW_OP)) -+ (clobber (reg:CC CC_REGNUM)) -+ (clobber (match_scratch:SI 3 "=&r"))] -+ "" -+ { -+ return aarch64_output_sync_insn (insn, operands); -+ } -+ [(set_attr "sync_result" "0") -+ (set_attr "sync_memory" "1") -+ (set_attr "sync_new_value" "2") -+ (set_attr "sync_t1" "0") -+ (set_attr "sync_t2" "3") -+ (set_attr "sync_op" "nand") -+ ]) -+ -+(define_insn "aarch64_sync_old_" -+ [(set (match_operand:GPI 0 "register_operand" "=&r") -+ (unspec_volatile:GPI -+ [(syncop:GPI -+ (match_operand:GPI 1 "aarch64_sync_memory_operand" "+Q") -+ (match_operand:GPI 2 "register_operand" "r"))] -+ UNSPECV_SYNC_OLD_OP)) -+ (set (match_dup 1) -+ (unspec_volatile:GPI [(match_dup 1) (match_dup 2)] -+ UNSPECV_SYNC_OLD_OP)) -+ (clobber (reg:CC CC_REGNUM)) -+ (clobber (match_scratch:GPI 3 "=&r")) -+ (clobber (match_scratch:GPI 4 "=&r"))] -+ "" -+ { -+ return aarch64_output_sync_insn (insn, operands); -+ } -+ [(set_attr "sync_result" "0") -+ (set_attr "sync_memory" "1") -+ (set_attr "sync_new_value" "2") -+ (set_attr "sync_t1" "3") -+ (set_attr "sync_t2" "4") -+ (set_attr "sync_op" "") -+ ]) -+ -+(define_insn "aarch64_sync_old_nand" -+ [(set (match_operand:GPI 0 "register_operand" "=&r") -+ (unspec_volatile:GPI -+ [(not:GPI (and:GPI -+ (match_operand:GPI 1 "aarch64_sync_memory_operand" "+Q") -+ (match_operand:GPI 2 "register_operand" "r")))] -+ UNSPECV_SYNC_OLD_OP)) -+ (set (match_dup 1) -+ (unspec_volatile:GPI [(match_dup 1) (match_dup 2)] -+ UNSPECV_SYNC_OLD_OP)) -+ (clobber (reg:CC CC_REGNUM)) -+ (clobber (match_scratch:GPI 3 "=&r")) -+ (clobber (match_scratch:GPI 4 "=&r"))] -+ "" -+ { -+ return aarch64_output_sync_insn (insn, operands); -+ } -+ [(set_attr "sync_result" "0") -+ (set_attr "sync_memory" "1") -+ (set_attr "sync_new_value" "2") -+ (set_attr "sync_t1" "3") -+ (set_attr "sync_t2" "4") -+ (set_attr "sync_op" "nand") -+ ]) -+ -+(define_insn "aarch64_sync_old_" -+ [(set (match_operand:SI 0 "register_operand" "=&r") -+ (unspec_volatile:SI -+ [(syncop:SI -+ (zero_extend:SI -+ (match_operand:SHORT 1 "aarch64_sync_memory_operand" "+Q")) -+ (match_operand:SI 2 "register_operand" "r"))] -+ UNSPECV_SYNC_OLD_OP)) -+ (set (match_dup 1) -+ (unspec_volatile:SHORT [(match_dup 1) (match_dup 2)] -+ UNSPECV_SYNC_OLD_OP)) -+ (clobber (reg:CC CC_REGNUM)) -+ (clobber (match_scratch:SI 3 "=&r")) -+ (clobber (match_scratch:SI 4 "=&r"))] -+ "" -+ { -+ return aarch64_output_sync_insn (insn, operands); -+ } -+ [(set_attr "sync_result" "0") -+ (set_attr "sync_memory" "1") -+ (set_attr "sync_new_value" "2") -+ (set_attr "sync_t1" "3") -+ (set_attr "sync_t2" "4") -+ (set_attr "sync_op" "") -+ ]) -+ -+(define_insn "aarch64_sync_old_nand" -+ [(set (match_operand:SI 0 "register_operand" "=&r") -+ (unspec_volatile:SI -+ [(not:SI -+ (and:SI -+ (zero_extend:SI -+ (match_operand:SHORT 1 "aarch64_sync_memory_operand" "+Q")) -+ (match_operand:SI 2 "register_operand" "r")))] -+ UNSPECV_SYNC_OLD_OP)) -+ (set (match_dup 1) -+ (unspec_volatile:SHORT [(match_dup 1) (match_dup 2)] -+ UNSPECV_SYNC_OLD_OP)) -+ (clobber (reg:CC CC_REGNUM)) -+ (clobber (match_scratch:SI 3 "=&r")) -+ (clobber (match_scratch:SI 4 "=&r"))] -+ "" -+ { -+ return aarch64_output_sync_insn (insn, operands); -+ } -+ [(set_attr "sync_result" "0") -+ (set_attr "sync_memory" "1") -+ (set_attr "sync_new_value" "2") -+ (set_attr "sync_t1" "3") -+ (set_attr "sync_t2" "4") -+ (set_attr "sync_op" "nand") -+ ]) -+ -+(define_insn "*memory_barrier" -+ [(set (match_operand:BLK 0 "" "") -+ (unspec:BLK [(match_dup 0)] UNSPEC_MB))] -+ "" -+ "dmb\\tish" -+) -+ -+(define_insn "sync_lock_release" -+ [(set (match_operand:ALLI 0 "memory_operand" "+Q") -+ (unspec_volatile:ALLI [(match_operand:ALLI 1 "register_operand" "r")] -+ UNSPECV_SYNC_LOCK_RELEASE))] -+ -+ "" -+ { -+ return aarch64_output_sync_lock_release (operands[1], operands[0]); -+ }) -+ -Index: gcc/config/aarch64/aarch64.h -=================================================================== ---- a/src/gcc/config/aarch64/aarch64.h (.../gcc-4_7-branch) -+++ b/src/gcc/config/aarch64/aarch64.h (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,819 @@ -+/* Machine description for AArch64 architecture. -+ Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. -+ Contributed by ARM Ltd. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3, or (at your option) -+ any later version. -+ -+ GCC is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+ -+#ifndef GCC_AARCH64_H -+#define GCC_AARCH64_H -+ -+/* Target CPU builtins. */ -+#define TARGET_CPU_CPP_BUILTINS() \ -+ do \ -+ { \ -+ builtin_define ("__aarch64__"); \ -+ if (TARGET_BIG_END) \ -+ builtin_define ("__AARCH64EB__"); \ -+ else \ -+ builtin_define ("__AARCH64EL__"); \ -+ } while (0) -+ -+ -+ -+/* Target machine storage layout. */ -+ -+#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ -+ if (GET_MODE_CLASS (MODE) == MODE_INT \ -+ && GET_MODE_SIZE (MODE) < 4) \ -+ { \ -+ if (MODE == QImode || MODE == HImode) \ -+ { \ -+ MODE = SImode; \ -+ } \ -+ } -+ -+/* Bits are always numbered from the LSBit. */ -+#define BITS_BIG_ENDIAN 0 -+ -+/* Big/little-endian flavour. */ -+#define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) -+#define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) -+ -+/* AdvSIMD is supported in the default configuration, unless disabled by -+ -mgeneral-regs-only. */ -+#define TARGET_SIMD !TARGET_GENERAL_REGS_ONLY -+#define TARGET_FLOAT !TARGET_GENERAL_REGS_ONLY -+ -+#define UNITS_PER_WORD 8 -+ -+#define UNITS_PER_VREG 16 -+ -+#define PARM_BOUNDARY 64 -+ -+#define STACK_BOUNDARY 128 -+ -+#define FUNCTION_BOUNDARY 32 -+ -+#define EMPTY_FIELD_BOUNDARY 32 -+ -+#define BIGGEST_ALIGNMENT 128 -+ -+#define SHORT_TYPE_SIZE 16 -+ -+#define INT_TYPE_SIZE 32 -+ -+#define LONG_TYPE_SIZE 64 /* XXX This should be an option */ -+ -+#define LONG_LONG_TYPE_SIZE 64 -+ -+#define FLOAT_TYPE_SIZE 32 -+ -+#define DOUBLE_TYPE_SIZE 64 -+ -+#define LONG_DOUBLE_TYPE_SIZE 128 -+ -+/* The architecture reserves all bits of the address for hardware use, -+ so the vbit must go into the delta field of pointers to member -+ functions. This is the same config as that in the AArch32 -+ port. */ -+#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta -+ -+/* Make strings word-aligned so that strcpy from constants will be -+ faster. */ -+#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ -+ ((TREE_CODE (EXP) == STRING_CST \ -+ && !optimize_size \ -+ && (ALIGN) < BITS_PER_WORD) \ -+ ? BITS_PER_WORD : ALIGN) -+ -+#define DATA_ALIGNMENT(EXP, ALIGN) \ -+ ((((ALIGN) < BITS_PER_WORD) \ -+ && (TREE_CODE (EXP) == ARRAY_TYPE \ -+ || TREE_CODE (EXP) == UNION_TYPE \ -+ || TREE_CODE (EXP) == RECORD_TYPE)) \ -+ ? BITS_PER_WORD : (ALIGN)) -+ -+#define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN) -+ -+#define STRUCTURE_SIZE_BOUNDARY 8 -+ -+/* Defined by the ABI */ -+#define WCHAR_TYPE "unsigned int" -+#define WCHAR_TYPE_SIZE 32 -+ -+/* Using long long breaks -ansi and -std=c90, so these will need to be -+ made conditional for an LLP64 ABI. */ -+ -+#define SIZE_TYPE "long unsigned int" -+ -+#define PTRDIFF_TYPE "long int" -+ -+#define PCC_BITFIELD_TYPE_MATTERS 1 -+ -+ -+/* Instruction tuning/selection flags. */ -+ -+/* Bit values used to identify processor capabilities. */ -+#define AARCH64_FL_SIMD (1 << 0) /* Has SIMD instructions. */ -+#define AARCH64_FL_FP (1 << 1) /* Has FP. */ -+#define AARCH64_FL_CRYPTO (1 << 2) /* Has crypto. */ -+#define AARCH64_FL_SLOWMUL (1 << 3) /* A slow multiply core. */ -+ -+/* Has FP and SIMD. */ -+#define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD) -+ -+/* Has FP without SIMD. */ -+#define AARCH64_FL_FPQ16 (AARCH64_FL_FP & ~AARCH64_FL_SIMD) -+ -+/* Architecture flags that effect instruction selection. */ -+#define AARCH64_FL_FOR_ARCH8 (AARCH64_FL_FPSIMD) -+ -+/* Macros to test ISA flags. */ -+extern unsigned long aarch64_isa_flags; -+#define AARCH64_ISA_CRYPTO (aarch64_isa_flags & AARCH64_FL_CRYPTO) -+#define AARCH64_ISA_FP (aarch64_isa_flags & AARCH64_FL_FP) -+#define AARCH64_ISA_SIMD (aarch64_isa_flags & AARCH64_FL_SIMD) -+ -+/* Macros to test tuning flags. */ -+extern unsigned long aarch64_tune_flags; -+#define AARCH64_TUNE_SLOWMUL (aarch64_tune_flags & AARCH64_FL_SLOWMUL) -+ -+ -+/* Standard register usage. */ -+ -+/* 31 64-bit general purpose registers R0-R30: -+ R30 LR (link register) -+ R29 FP (frame pointer) -+ R19-R28 Callee-saved registers -+ R18 The platform register; use as temporary register. -+ R17 IP1 The second intra-procedure-call temporary register -+ (can be used by call veneers and PLT code); otherwise use -+ as a temporary register -+ R16 IP0 The first intra-procedure-call temporary register (can -+ be used by call veneers and PLT code); otherwise use as a -+ temporary register -+ R9-R15 Temporary registers -+ R8 Structure value parameter / temporary register -+ R0-R7 Parameter/result registers -+ -+ SP stack pointer, encoded as X/R31 where permitted. -+ ZR zero register, encoded as X/R31 elsewhere -+ -+ 32 x 128-bit floating-point/vector registers -+ V16-V31 Caller-saved (temporary) registers -+ V8-V15 Callee-saved registers -+ V0-V7 Parameter/result registers -+ -+ The vector register V0 holds scalar B0, H0, S0 and D0 in its least -+ significant bits. Unlike AArch32 S1 is not packed into D0, -+ etc. */ -+ -+/* Note that we don't mark X30 as a call-clobbered register. The idea is -+ that it's really the call instructions themselves which clobber X30. -+ We don't care what the called function does with it afterwards. -+ -+ This approach makes it easier to implement sibcalls. Unlike normal -+ calls, sibcalls don't clobber X30, so the register reaches the -+ called function intact. EPILOGUE_USES says that X30 is useful -+ to the called function. */ -+ -+#define FIXED_REGISTERS \ -+ { \ -+ 0, 0, 0, 0, 0, 0, 0, 0, /* R0 - R7 */ \ -+ 0, 0, 0, 0, 0, 0, 0, 0, /* R8 - R15 */ \ -+ 0, 0, 0, 0, 0, 0, 0, 0, /* R16 - R23 */ \ -+ 0, 0, 0, 0, 0, 1, 0, 1, /* R24 - R30, SP */ \ -+ 0, 0, 0, 0, 0, 0, 0, 0, /* V0 - V7 */ \ -+ 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \ -+ 0, 0, 0, 0, 0, 0, 0, 0, /* V16 - V23 */ \ -+ 0, 0, 0, 0, 0, 0, 0, 0, /* V24 - V31 */ \ -+ 1, 1, 1, /* SFP, AP, CC */ \ -+ } -+ -+#define CALL_USED_REGISTERS \ -+ { \ -+ 1, 1, 1, 1, 1, 1, 1, 1, /* R0 - R7 */ \ -+ 1, 1, 1, 1, 1, 1, 1, 1, /* R8 - R15 */ \ -+ 1, 1, 1, 0, 0, 0, 0, 0, /* R16 - R23 */ \ -+ 0, 0, 0, 0, 0, 1, 0, 1, /* R24 - R30, SP */ \ -+ 1, 1, 1, 1, 1, 1, 1, 1, /* V0 - V7 */ \ -+ 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \ -+ 1, 1, 1, 1, 1, 1, 1, 1, /* V16 - V23 */ \ -+ 1, 1, 1, 1, 1, 1, 1, 1, /* V24 - V31 */ \ -+ 1, 1, 1, /* SFP, AP, CC */ \ -+ } -+ -+#define REGISTER_NAMES \ -+ { \ -+ "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", \ -+ "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", \ -+ "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", \ -+ "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", \ -+ "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \ -+ "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \ -+ "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \ -+ "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \ -+ "sfp", "ap", "cc", \ -+ } -+ -+/* Generate the register aliases for core register N */ -+#define R_ALIASES(N) {"r" # N, R0_REGNUM + (N)}, \ -+ {"w" # N, R0_REGNUM + (N)} -+ -+#define V_ALIASES(N) {"q" # N, V0_REGNUM + (N)}, \ -+ {"d" # N, V0_REGNUM + (N)}, \ -+ {"s" # N, V0_REGNUM + (N)}, \ -+ {"h" # N, V0_REGNUM + (N)}, \ -+ {"b" # N, V0_REGNUM + (N)} -+ -+/* Provide aliases for all of the ISA defined register name forms. -+ These aliases are convenient for use in the clobber lists of inline -+ asm statements. */ -+ -+#define ADDITIONAL_REGISTER_NAMES \ -+ { R_ALIASES(0), R_ALIASES(1), R_ALIASES(2), R_ALIASES(3), \ -+ R_ALIASES(4), R_ALIASES(5), R_ALIASES(6), R_ALIASES(7), \ -+ R_ALIASES(8), R_ALIASES(9), R_ALIASES(10), R_ALIASES(11), \ -+ R_ALIASES(12), R_ALIASES(13), R_ALIASES(14), R_ALIASES(15), \ -+ R_ALIASES(16), R_ALIASES(17), R_ALIASES(18), R_ALIASES(19), \ -+ R_ALIASES(20), R_ALIASES(21), R_ALIASES(22), R_ALIASES(23), \ -+ R_ALIASES(24), R_ALIASES(25), R_ALIASES(26), R_ALIASES(27), \ -+ R_ALIASES(28), R_ALIASES(29), R_ALIASES(30), /* 31 omitted */ \ -+ V_ALIASES(0), V_ALIASES(1), V_ALIASES(2), V_ALIASES(3), \ -+ V_ALIASES(4), V_ALIASES(5), V_ALIASES(6), V_ALIASES(7), \ -+ V_ALIASES(8), V_ALIASES(9), V_ALIASES(10), V_ALIASES(11), \ -+ V_ALIASES(12), V_ALIASES(13), V_ALIASES(14), V_ALIASES(15), \ -+ V_ALIASES(16), V_ALIASES(17), V_ALIASES(18), V_ALIASES(19), \ -+ V_ALIASES(20), V_ALIASES(21), V_ALIASES(22), V_ALIASES(23), \ -+ V_ALIASES(24), V_ALIASES(25), V_ALIASES(26), V_ALIASES(27), \ -+ V_ALIASES(28), V_ALIASES(29), V_ALIASES(30), V_ALIASES(31) \ -+ } -+ -+/* Say that the epilogue uses the return address register. Note that -+ in the case of sibcalls, the values "used by the epilogue" are -+ considered live at the start of the called function. */ -+ -+#define EPILOGUE_USES(REGNO) \ -+ ((REGNO) == LR_REGNUM) -+ -+/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, -+ the stack pointer does not matter. The value is tested only in -+ functions that have frame pointers. */ -+#define EXIT_IGNORE_STACK 1 -+ -+#define STATIC_CHAIN_REGNUM R18_REGNUM -+#define HARD_FRAME_POINTER_REGNUM R29_REGNUM -+#define FRAME_POINTER_REGNUM SFP_REGNUM -+#define STACK_POINTER_REGNUM SP_REGNUM -+#define ARG_POINTER_REGNUM AP_REGNUM -+#define FIRST_PSEUDO_REGISTER 67 -+ -+/* The number of (integer) argument register available. */ -+#define NUM_ARG_REGS 8 -+#define NUM_FP_ARG_REGS 8 -+ -+/* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most -+ four members. */ -+#define HA_MAX_NUM_FLDS 4 -+ -+/* External dwarf register number scheme. These number are used to -+ identify registers in dwarf debug information, the values are -+ defined by the AArch64 ABI. The numbering scheme is independent of -+ GCC's internal register numbering scheme. */ -+ -+#define AARCH64_DWARF_R0 0 -+ -+/* The number of R registers, note 31! not 32. */ -+#define AARCH64_DWARF_NUMBER_R 31 -+ -+#define AARCH64_DWARF_SP 31 -+#define AARCH64_DWARF_V0 64 -+ -+/* The number of V registers. */ -+#define AARCH64_DWARF_NUMBER_V 32 -+ -+/* For signal frames we need to use an alternative return column. This -+ value must not correspond to a hard register and must be out of the -+ range of DWARF_FRAME_REGNUM(). */ -+#define DWARF_ALT_FRAME_RETURN_COLUMN \ -+ (AARCH64_DWARF_V0 + AARCH64_DWARF_NUMBER_V) -+ -+/* We add 1 extra frame register for use as the -+ DWARF_ALT_FRAME_RETURN_COLUMN. */ -+#define DWARF_FRAME_REGISTERS (DWARF_ALT_FRAME_RETURN_COLUMN + 1) -+ -+ -+#define DBX_REGISTER_NUMBER(REGNO) aarch64_dbx_register_number (REGNO) -+/* Provide a definition of DWARF_FRAME_REGNUM here so that fallback unwinders -+ can use DWARF_ALT_FRAME_RETURN_COLUMN defined below. This is just the same -+ as the default definition in dwarf2out.c. */ -+#undef DWARF_FRAME_REGNUM -+#define DWARF_FRAME_REGNUM(REGNO) DBX_REGISTER_NUMBER (REGNO) -+ -+#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) -+ -+#define HARD_REGNO_NREGS(REGNO, MODE) aarch64_hard_regno_nregs (REGNO, MODE) -+ -+#define HARD_REGNO_MODE_OK(REGNO, MODE) aarch64_hard_regno_mode_ok (REGNO, MODE) -+ -+#define MODES_TIEABLE_P(MODE1, MODE2) \ -+ (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) -+ -+#define DWARF2_UNWIND_INFO 1 -+ -+/* Use R0 through R3 to pass exception handling information. */ -+#define EH_RETURN_DATA_REGNO(N) \ -+ ((N) < 4 ? ((unsigned int) R0_REGNUM + (N)) : INVALID_REGNUM) -+ -+/* Select a format to encode pointers in exception handling data. */ -+#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ -+ aarch64_asm_preferred_eh_data_format ((CODE), (GLOBAL)) -+ -+/* The register that holds the return address in exception handlers. */ -+#define AARCH64_EH_STACKADJ_REGNUM (R0_REGNUM + 4) -+#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, AARCH64_EH_STACKADJ_REGNUM) -+ -+/* Don't use __builtin_setjmp until we've defined it. */ -+#undef DONT_USE_BUILTIN_SETJMP -+#define DONT_USE_BUILTIN_SETJMP 1 -+ -+/* Register in which the structure value is to be returned. */ -+#define AARCH64_STRUCT_VALUE_REGNUM R8_REGNUM -+ -+/* Non-zero if REGNO is part of the Core register set. -+ -+ The rather unusual way of expressing this check is to avoid -+ warnings when building the compiler when R0_REGNUM is 0 and REGNO -+ is unsigned. */ -+#define GP_REGNUM_P(REGNO) \ -+ (((unsigned) (REGNO - R0_REGNUM)) <= (R30_REGNUM - R0_REGNUM)) -+ -+#define FP_REGNUM_P(REGNO) \ -+ (((unsigned) (REGNO - V0_REGNUM)) <= (V31_REGNUM - V0_REGNUM)) -+ -+#define FP_LO_REGNUM_P(REGNO) \ -+ (((unsigned) (REGNO - V0_REGNUM)) <= (V15_REGNUM - V0_REGNUM)) -+ -+ -+/* Register and constant classes. */ -+ -+enum reg_class -+{ -+ NO_REGS, -+ CORE_REGS, -+ GENERAL_REGS, -+ STACK_REG, -+ POINTER_REGS, -+ FP_LO_REGS, -+ FP_REGS, -+ ALL_REGS, -+ LIM_REG_CLASSES /* Last */ -+}; -+ -+#define N_REG_CLASSES ((int) LIM_REG_CLASSES) -+ -+#define REG_CLASS_NAMES \ -+{ \ -+ "NO_REGS", \ -+ "CORE_REGS", \ -+ "GENERAL_REGS", \ -+ "STACK_REG", \ -+ "POINTER_REGS", \ -+ "FP_LO_REGS", \ -+ "FP_REGS", \ -+ "ALL_REGS" \ -+} -+ -+#define REG_CLASS_CONTENTS \ -+{ \ -+ { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ -+ { 0x7fffffff, 0x00000000, 0x00000003 }, /* CORE_REGS */ \ -+ { 0x7fffffff, 0x00000000, 0x00000003 }, /* GENERAL_REGS */ \ -+ { 0x80000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ -+ { 0xffffffff, 0x00000000, 0x00000003 }, /* POINTER_REGS */ \ -+ { 0x00000000, 0x0000ffff, 0x00000000 }, /* FP_LO_REGS */ \ -+ { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \ -+ { 0xffffffff, 0xffffffff, 0x00000007 } /* ALL_REGS */ \ -+} -+ -+#define REGNO_REG_CLASS(REGNO) aarch64_regno_regclass (REGNO) -+ -+#define INDEX_REG_CLASS CORE_REGS -+#define BASE_REG_CLASS POINTER_REGS -+ -+/* Register pairs used to eliminate unneeded registers that point intoi -+ the stack frame. */ -+#define ELIMINABLE_REGS \ -+{ \ -+ { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ -+ { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ -+ { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ -+ { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ -+} -+ -+#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ -+ (OFFSET) = aarch64_initial_elimination_offset (FROM, TO) -+ -+/* CPU/ARCH option handling. */ -+#include "config/aarch64/aarch64-opts.h" -+ -+enum target_cpus -+{ -+#define AARCH64_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ -+ TARGET_CPU_##IDENT, -+#include "aarch64-cores.def" -+#undef AARCH64_CORE -+ TARGET_CPU_generic -+}; -+ -+/* If there is no CPU defined at configure, use "generic" as default. */ -+#ifndef TARGET_CPU_DEFAULT -+#define TARGET_CPU_DEFAULT \ -+ (TARGET_CPU_generic | (AARCH64_CPU_DEFAULT_FLAGS << 6)) -+#endif -+ -+/* The processor for which instructions should be scheduled. */ -+extern enum aarch64_processor aarch64_tune; -+ -+/* RTL generation support. */ -+#define INIT_EXPANDERS aarch64_init_expanders () -+ -+ -+/* Stack layout; function entry, exit and calling. */ -+#define STACK_GROWS_DOWNWARD 1 -+ -+#define FRAME_GROWS_DOWNWARD 0 -+ -+#define STARTING_FRAME_OFFSET 0 -+ -+#define ACCUMULATE_OUTGOING_ARGS 1 -+ -+#define FIRST_PARM_OFFSET(FNDECL) 0 -+ -+/* Fix for VFP */ -+#define LIBCALL_VALUE(MODE) \ -+ gen_rtx_REG (MODE, FLOAT_MODE_P (MODE) ? V0_REGNUM : R0_REGNUM) -+ -+#define DEFAULT_PCC_STRUCT_RETURN 0 -+ -+#define AARCH64_ROUND_UP(X, ALIGNMENT) \ -+ (((X) + ((ALIGNMENT) - 1)) & ~((ALIGNMENT) - 1)) -+ -+#define AARCH64_ROUND_DOWN(X, ALIGNMENT) \ -+ ((X) & ~((ALIGNMENT) - 1)) -+ -+#ifdef HOST_WIDE_INT -+struct GTY (()) aarch64_frame -+{ -+ HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; -+ HOST_WIDE_INT saved_regs_size; -+ /* Padding if needed after the all the callee save registers have -+ been saved. */ -+ HOST_WIDE_INT padding0; -+ HOST_WIDE_INT hardfp_offset; /* HARD_FRAME_POINTER_REGNUM */ -+ HOST_WIDE_INT fp_lr_offset; /* Space needed for saving fp and/or lr */ -+ -+ bool laid_out; -+}; -+ -+typedef struct GTY (()) machine_function -+{ -+ struct aarch64_frame frame; -+ -+ /* The number of extra stack bytes taken up by register varargs. -+ This area is allocated by the callee at the very top of the frame. */ -+ HOST_WIDE_INT saved_varargs_size; -+ -+} machine_function; -+#endif -+ -+ -+/* Which ABI to use. */ -+enum arm_abi_type -+{ -+ ARM_ABI_AAPCS64 -+}; -+ -+enum arm_pcs -+{ -+ ARM_PCS_AAPCS64, /* Base standard AAPCS for 64 bit. */ -+ ARM_PCS_UNKNOWN -+}; -+ -+ -+extern enum arm_abi_type arm_abi; -+extern enum arm_pcs arm_pcs_variant; -+#ifndef ARM_DEFAULT_ABI -+#define ARM_DEFAULT_ABI ARM_ABI_AAPCS64 -+#endif -+ -+#ifndef ARM_DEFAULT_PCS -+#define ARM_DEFAULT_PCS ARM_PCS_AAPCS64 -+#endif -+ -+/* We can't use enum machine_mode inside a generator file because it -+ hasn't been created yet; we shouldn't be using any code that -+ needs the real definition though, so this ought to be safe. */ -+#ifdef GENERATOR_FILE -+#define MACHMODE int -+#else -+#include "insn-modes.h" -+#define MACHMODE enum machine_mode -+#endif -+ -+ -+/* AAPCS related state tracking. */ -+typedef struct -+{ -+ enum arm_pcs pcs_variant; -+ int aapcs_arg_processed; /* No need to lay out this argument again. */ -+ int aapcs_ncrn; /* Next Core register number. */ -+ int aapcs_nextncrn; /* Next next core register number. */ -+ int aapcs_nvrn; /* Next Vector register number. */ -+ int aapcs_nextnvrn; /* Next Next Vector register number. */ -+ rtx aapcs_reg; /* Register assigned to this argument. This -+ is NULL_RTX if this parameter goes on -+ the stack. */ -+ MACHMODE aapcs_vfp_rmode; -+ int aapcs_stack_words; /* If the argument is passed on the stack, this -+ is the number of words needed, after rounding -+ up. Only meaningful when -+ aapcs_reg == NULL_RTX. */ -+ int aapcs_stack_size; /* The total size (in words, per 8 byte) of the -+ stack arg area so far. */ -+} CUMULATIVE_ARGS; -+ -+#define FUNCTION_ARG_PADDING(MODE, TYPE) \ -+ (aarch64_pad_arg_upward (MODE, TYPE) ? upward : downward) -+ -+#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ -+ (aarch64_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward) -+ -+#define PAD_VARARGS_DOWN 0 -+ -+#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ -+ aarch64_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) -+ -+#define FUNCTION_ARG_REGNO_P(REGNO) \ -+ aarch64_function_arg_regno_p(REGNO) -+ -+ -+/* ISA Features. */ -+ -+/* Addressing modes, etc. */ -+#define HAVE_POST_INCREMENT 1 -+#define HAVE_PRE_INCREMENT 1 -+#define HAVE_POST_DECREMENT 1 -+#define HAVE_PRE_DECREMENT 1 -+#define HAVE_POST_MODIFY_DISP 1 -+#define HAVE_PRE_MODIFY_DISP 1 -+ -+#define MAX_REGS_PER_ADDRESS 2 -+ -+#define CONSTANT_ADDRESS_P(X) aarch64_constant_address_p(X) -+ -+/* Try a machine-dependent way of reloading an illegitimate address -+ operand. If we find one, push the reload and jump to WIN. This -+ macro is used in only one place: `find_reloads_address' in reload.c. */ -+ -+#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \ -+do { \ -+ rtx new_x = aarch64_legitimize_reload_address (&(X), MODE, OPNUM, TYPE, \ -+ IND_L); \ -+ if (new_x) \ -+ { \ -+ X = new_x; \ -+ goto WIN; \ -+ } \ -+} while (0) -+ -+#define REGNO_OK_FOR_BASE_P(REGNO) \ -+ aarch64_regno_ok_for_base_p (REGNO, true) -+ -+#define REGNO_OK_FOR_INDEX_P(REGNO) \ -+ aarch64_regno_ok_for_index_p (REGNO, true) -+ -+#define LEGITIMATE_PIC_OPERAND_P(X) \ -+ aarch64_legitimate_pic_operand_p (X) -+ -+/* Go to LABEL if ADDR (a legitimate address expression) -+ has an effect that depends on the machine mode it is used for. -+ Post-inc/dec are now explicitly handled by recog.c. */ -+#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) -+ -+#define CASE_VECTOR_MODE Pmode -+ -+#define DEFAULT_SIGNED_CHAR 0 -+ -+/* An integer expression for the size in bits of the largest integer machine -+ mode that should actually be used. We allow pairs of registers. */ -+#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) -+ -+/* Maximum bytes moved by a single instruction (load/store pair). */ -+#define MOVE_MAX (UNITS_PER_WORD * 2) -+ -+/* The base cost overhead of a memcpy call, for MOVE_RATIO and friends. */ -+#define AARCH64_CALL_RATIO 8 -+ -+/* When optimizing for size, give a better estimate of the length of a memcpy -+ call, but use the default otherwise. But move_by_pieces_ninsns() counts -+ memory-to-memory moves, and we'll have to generate a load & store for each, -+ so halve the value to take that into account. */ -+#define MOVE_RATIO(speed) \ -+ (((speed) ? 15 : AARCH64_CALL_RATIO) / 2) -+ -+/* For CLEAR_RATIO, when optimizing for size, give a better estimate -+ of the length of a memset call, but use the default otherwise. */ -+#define CLEAR_RATIO(speed) \ -+ ((speed) ? 15 : AARCH64_CALL_RATIO) -+ -+/* SET_RATIO is similar to CLEAR_RATIO, but for a non-zero constant, so when -+ optimizing for size adjust the ratio to account for the overhead of loading -+ the constant. */ -+#define SET_RATIO(speed) \ -+ ((speed) ? 15 : AARCH64_CALL_RATIO - 2) -+ -+/* STORE_BY_PIECES_P can be used when copying a constant string, but -+ in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR). -+ For now we always fail this and let the move_by_pieces code copy -+ the string from read-only memory. */ -+#define STORE_BY_PIECES_P(SIZE, ALIGN) 0 -+ -+/* Disable auto-increment in move_by_pieces et al. Use of auto-increment is -+ rarely a good idea in straight-line code since it adds an extra address -+ dependency between each instruction. Better to use incrementing offsets. */ -+#define USE_LOAD_POST_INCREMENT(MODE) 0 -+#define USE_LOAD_POST_DECREMENT(MODE) 0 -+#define USE_LOAD_PRE_INCREMENT(MODE) 0 -+#define USE_LOAD_PRE_DECREMENT(MODE) 0 -+#define USE_STORE_POST_INCREMENT(MODE) 0 -+#define USE_STORE_POST_DECREMENT(MODE) 0 -+#define USE_STORE_PRE_INCREMENT(MODE) 0 -+#define USE_STORE_PRE_DECREMENT(MODE) 0 -+ -+/* ?? #define WORD_REGISTER_OPERATIONS */ -+ -+/* Define if loading from memory in MODE, an integral mode narrower than -+ BITS_PER_WORD will either zero-extend or sign-extend. The value of this -+ macro should be the code that says which one of the two operations is -+ implicitly done, or UNKNOWN if none. */ -+#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND -+ -+/* Define this macro to be non-zero if instructions will fail to work -+ if given data not on the nominal alignment. */ -+#define STRICT_ALIGNMENT TARGET_STRICT_ALIGN -+ -+/* Define this macro to be non-zero if accessing less than a word of -+ memory is no faster than accessing a word of memory, i.e., if such -+ accesses require more than one instruction or if there is no -+ difference in cost. -+ Although there's no difference in instruction count or cycles, -+ in AArch64 we don't want to expand to a sub-word to a 64-bit access -+ if we don't have to, for power-saving reasons. */ -+#define SLOW_BYTE_ACCESS 0 -+ -+#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 -+ -+#define NO_FUNCTION_CSE 1 -+ -+#define Pmode DImode -+#define FUNCTION_MODE Pmode -+ -+#define SELECT_CC_MODE(OP, X, Y) aarch64_select_cc_mode (OP, X, Y) -+ -+#define REVERSE_CONDITION(CODE, MODE) \ -+ (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ -+ ? reverse_condition_maybe_unordered (CODE) \ -+ : reverse_condition (CODE)) -+ -+#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ -+ ((VALUE) = ((MODE) == SImode ? 32 : 64), 2) -+#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ -+ ((VALUE) = ((MODE) == SImode ? 32 : 64), 2) -+ -+#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) -+ -+#define RETURN_ADDR_RTX aarch64_return_addr -+ -+#define TRAMPOLINE_SIZE aarch64_trampoline_size () -+ -+/* Trampolines contain dwords, so must be dword aligned. */ -+#define TRAMPOLINE_ALIGNMENT 64 -+ -+/* Put trampolines in the text section so that mapping symbols work -+ correctly. */ -+#define TRAMPOLINE_SECTION text_section -+ -+/* Costs, etc. */ -+#define MEMORY_MOVE_COST(M, CLASS, IN) \ -+ (GET_MODE_SIZE (M) < 8 ? 8 : GET_MODE_SIZE (M)) -+ -+/* To start with. */ -+#define BRANCH_COST(SPEED_P, PREDICTABLE_P) 2 -+ -+ -+/* Assembly output. */ -+ -+/* For now we'll make all jump tables pc-relative. */ -+#define CASE_VECTOR_PC_RELATIVE 1 -+ -+#define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ -+ ((min < -0x1fff0 || max > 0x1fff0) ? SImode \ -+ : (min < -0x1f0 || max > 0x1f0) ? HImode \ -+ : QImode) -+ -+/* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */ -+#define ADDR_VEC_ALIGN(JUMPTABLE) 0 -+ -+#define PRINT_OPERAND(STREAM, X, CODE) aarch64_print_operand (STREAM, X, CODE) -+ -+#define PRINT_OPERAND_ADDRESS(STREAM, X) \ -+ aarch64_print_operand_address (STREAM, X) -+ -+#define FUNCTION_PROFILER(STREAM, LABELNO) \ -+ aarch64_function_profiler (STREAM, LABELNO) -+ -+/* For some reason, the Linux headers think they know how to define -+ these macros. They don't!!! */ -+#undef ASM_APP_ON -+#undef ASM_APP_OFF -+#define ASM_APP_ON "\t" ASM_COMMENT_START " Start of user assembly\n" -+#define ASM_APP_OFF "\t" ASM_COMMENT_START " End of user assembly\n" -+ -+#define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ -+ case '@': \ -+ fputs (ASM_COMMENT_START, FILE); \ -+ break; \ -+ \ -+ case 'r': \ -+ fputs (REGISTER_PREFIX, FILE); \ -+ fputs (reg_names[va_arg (ARGS, int)], FILE); \ -+ break; -+ -+#define CONSTANT_POOL_BEFORE_FUNCTION 0 -+ -+/* This definition should be relocated to aarch64-elf-raw.h. This macro -+ should be undefined in aarch64-linux.h and a clear_cache pattern -+ implmented to emit either the call to __aarch64_sync_cache_range() -+ directly or preferably the appropriate sycall or cache clear -+ instructions inline. */ -+#define CLEAR_INSN_CACHE(beg, end) \ -+ extern void __aarch64_sync_cache_range (void *, void *); \ -+ __aarch64_sync_cache_range (beg, end) -+ -+/* This should be integrated with the equivalent in the 32 bit -+ world. */ -+enum aarch64_builtins -+{ -+ AARCH64_BUILTIN_MIN, -+ AARCH64_BUILTIN_THREAD_POINTER, -+ AARCH64_SIMD_BUILTIN_BASE -+}; -+ -+/* VFP registers may only be accessed in the mode they -+ were set. */ -+#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ -+ (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ -+ ? reg_classes_intersect_p (FP_REGS, (CLASS)) \ -+ : 0) -+ -+ -+#define SHIFT_COUNT_TRUNCATED 1 -+ -+/* Callee only saves lower 64-bits of a 128-bit register. Tell the -+ compiler the callee clobbers the top 64-bits when restoring the -+ bottom 64-bits. */ -+#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ -+ (FP_REGNUM_P (REGNO) && GET_MODE_SIZE (MODE) > 8) -+ -+/* Check TLS Descriptors mechanism is selected. */ -+#define TARGET_TLS_DESC (aarch64_tls_dialect == TLS_DESCRIPTORS) -+ -+extern enum aarch64_code_model aarch64_cmodel; -+ -+/* When using the tiny addressing model conditional and unconditional branches -+ can span the whole of the available address space (1MB). */ -+#define HAS_LONG_COND_BRANCH \ -+ (aarch64_cmodel == AARCH64_CMODEL_TINY \ -+ || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) -+ -+#define HAS_LONG_UNCOND_BRANCH \ -+ (aarch64_cmodel == AARCH64_CMODEL_TINY \ -+ || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) -+ -+#endif /* GCC_AARCH64_H */ - -Property changes on: gcc/config/aarch64/aarch64.h -___________________________________________________________________ -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: gcc/config/aarch64/gentune.sh -=================================================================== ---- a/src/gcc/config/aarch64/gentune.sh (.../gcc-4_7-branch) -+++ b/src/gcc/config/aarch64/gentune.sh (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,32 @@ -+#!/bin/sh -+# -+# Copyright (C) 2011, 2012 Free Software Foundation, Inc. -+# Contributed by ARM Ltd. -+# -+# This file is part of GCC. -+# -+# GCC is free software; you can redistribute it and/or modify -+# it under the terms of the GNU General Public License as published by -+# the Free Software Foundation; either version 3, or (at your option) -+# any later version. -+# -+# GCC is distributed in the hope that it will be useful, -+# but WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+# GNU General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with GCC; see the file COPYING3. If not see -+# . -+ -+# Generate aarch64-tune.md, a file containing the tune attribute from the list of -+# CPUs in aarch64-cores.def -+ -+echo ";; -*- buffer-read-only: t -*-" -+echo ";; Generated automatically by gentune.sh from aarch64-cores.def" -+ -+allcores=`awk -F'[(, ]+' '/^AARCH64_CORE/ { cores = cores$3"," } END { print cores } ' $1` -+ -+echo "(define_attr \"tune\"" -+echo " \"$allcores\"" | sed -e 's/,"$/"/' -+echo " (const (symbol_ref \"((enum attr_tune) aarch64_tune)\")))" - -Property changes on: gcc/config/aarch64/gentune.sh -___________________________________________________________________ -Added: svn:executable - + * -Added: svn:keywords - + Rev Date Author URL Id -Added: svn:eol-style - + native - -Index: config.sub -=================================================================== ---- a/src/config.sub (.../gcc-4_7-branch) -+++ b/src/config.sub (.../ARM/aarch64-4.7-branch) -@@ -2,9 +2,9 @@ - # Configuration validation subroutine script. - # Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - # 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, --# 2011 Free Software Foundation, Inc. -+# 2011, 2012 Free Software Foundation, Inc. - --timestamp='2011-10-29' -+timestamp='2012-08-18' - - # This file is (in principle) common to ALL GNU software. - # The presence of a machine in this file suggests that SOME GNU software -@@ -21,9 +21,7 @@ - # GNU General Public License for more details. - # - # You should have received a copy of the GNU General Public License --# along with this program; if not, write to the Free Software --# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA --# 02110-1301, USA. -+# along with this program; if not, see . - # - # As a special exception to the GNU General Public License, if you - # distribute this file as part of a program that contains a -@@ -76,8 +74,8 @@ - GNU config.sub ($timestamp) - - Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, --2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 Free --Software Foundation, Inc. -+2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012 -+Free Software Foundation, Inc. - - This is free software; see the source for copying conditions. There is NO - warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." -@@ -125,13 +123,17 @@ - maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'` - case $maybe_os in - nto-qnx* | linux-gnu* | linux-android* | linux-dietlibc | linux-newlib* | \ -- linux-uclibc* | uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | \ -+ linux-musl* | linux-uclibc* | uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | \ - knetbsd*-gnu* | netbsd*-gnu* | \ - kopensolaris*-gnu* | \ - storm-chaos* | os2-emx* | rtmk-nova*) - os=-$maybe_os - basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'` - ;; -+ android-linux) -+ os=-linux-android -+ basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'`-unknown -+ ;; - *) - basic_machine=`echo $1 | sed 's/-[^-]*$//'` - if [ $basic_machine != $1 ] -@@ -223,6 +225,12 @@ - -isc*) - basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` - ;; -+ -lynx*178) -+ os=-lynxos178 -+ ;; -+ -lynx*5) -+ os=-lynxos5 -+ ;; - -lynx*) - os=-lynxos - ;; -@@ -247,6 +255,7 @@ - # Some are omitted here because they have special meanings below. - 1750a | 580 \ - | a29k \ -+ | aarch64 | aarch64_be \ - | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \ - | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \ - | am33_2.0 \ -@@ -319,8 +328,7 @@ - c6x) - basic_machine=tic6x-unknown - ;; -- m6811 | m68hc11 | m6812 | m68hc12 | picochip) -- # Motorola 68HC11/12. -+ m6811 | m68hc11 | m6812 | m68hc12 | m68hcs12x | picochip) - basic_machine=$basic_machine-unknown - os=-none - ;; -@@ -333,7 +341,10 @@ - strongarm | thumb | xscale) - basic_machine=arm-unknown - ;; -- -+ xgate) -+ basic_machine=$basic_machine-unknown -+ os=-none -+ ;; - xscaleeb) - basic_machine=armeb-unknown - ;; -@@ -356,6 +367,7 @@ - # Recognize the basic CPU types with company name. - 580-* \ - | a29k-* \ -+ | aarch64-* | aarch64_be-* \ - | alpha-* | alphaev[4-8]-* | alphaev56-* | alphaev6[78]-* \ - | alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \ - | alphapca5[67]-* | alpha64pca5[67]-* | arc-* \ -@@ -719,7 +731,6 @@ - i370-ibm* | ibm*) - basic_machine=i370-ibm - ;; --# I'm not sure what "Sysv32" means. Should this be sysv3.2? - i*86v32) - basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` - os=-sysv32 -@@ -780,6 +791,10 @@ - microblaze) - basic_machine=microblaze-xilinx - ;; -+ mingw64) -+ basic_machine=x86_64-pc -+ os=-mingw64 -+ ;; - mingw32) - basic_machine=i386-pc - os=-mingw32 -@@ -816,6 +831,10 @@ - ms1-*) - basic_machine=`echo $basic_machine | sed -e 's/ms1-/mt-/'` - ;; -+ msys) -+ basic_machine=i386-pc -+ os=-msys -+ ;; - mvs) - basic_machine=i370-ibm - os=-mvs -@@ -1337,15 +1356,15 @@ - | -nindy* | -vxsim* | -vxworks* | -ebmon* | -hms* | -mvs* \ - | -clix* | -riscos* | -uniplus* | -iris* | -rtu* | -xenix* \ - | -hiux* | -386bsd* | -knetbsd* | -mirbsd* | -netbsd* \ -- | -openbsd* | -solidbsd* \ -+ | -bitrig* | -openbsd* | -solidbsd* \ - | -ekkobsd* | -kfreebsd* | -freebsd* | -riscix* | -lynxos* \ - | -bosx* | -nextstep* | -cxux* | -aout* | -elf* | -oabi* \ - | -ptx* | -coff* | -ecoff* | -winnt* | -domain* | -vsta* \ - | -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \ - | -chorusos* | -chorusrdb* | -cegcc* \ -- | -cygwin* | -pe* | -psos* | -moss* | -proelf* | -rtems* \ -- | -mingw32* | -linux-gnu* | -linux-android* \ -- | -linux-newlib* | -linux-uclibc* \ -+ | -cygwin* | -msys* | -pe* | -psos* | -moss* | -proelf* | -rtems* \ -+ | -mingw32* | -mingw64* | -linux-gnu* | -linux-android* \ -+ | -linux-newlib* | -linux-musl* | -linux-uclibc* \ - | -uxpv* | -beos* | -mpeix* | -udk* \ - | -interix* | -uwin* | -mks* | -rhapsody* | -darwin* | -opened* \ - | -openstep* | -oskit* | -conix* | -pw32* | -nonstopux* \ -@@ -1528,6 +1547,9 @@ - c4x-* | tic4x-*) - os=-coff - ;; -+ hexagon-*) -+ os=-elf -+ ;; - tic54x-*) - os=-coff - ;; -@@ -1555,9 +1577,6 @@ - ;; - m68000-sun) - os=-sunos3 -- # This also exists in the configure program, but was not the -- # default. -- # os=-sunos4 - ;; - m68*-cisco) - os=-aout -Index: libcpp/configure -=================================================================== ---- a/src/libcpp/configure (.../gcc-4_7-branch) -+++ b/src/libcpp/configure (.../ARM/aarch64-4.7-branch) -@@ -7368,6 +7368,7 @@ - - - case $target in -+ aarch64*-*-* | \ - alpha*-*-* | \ - arm*-*-*eabi* | \ - arm*-*-symbianelf* | \ -Index: libcpp/configure.ac -=================================================================== ---- a/src/libcpp/configure.ac (.../gcc-4_7-branch) -+++ b/src/libcpp/configure.ac (.../ARM/aarch64-4.7-branch) -@@ -148,6 +148,7 @@ - - m4_changequote(,) - case $target in -+ aarch64*-*-* | \ - alpha*-*-* | \ - arm*-*-*eabi* | \ - arm*-*-symbianelf* | \ -Index: libcpp/ChangeLog.aarch64 -=================================================================== ---- a/src/libcpp/ChangeLog.aarch64 (.../gcc-4_7-branch) -+++ b/src/libcpp/ChangeLog.aarch64 (.../ARM/aarch64-4.7-branch) -@@ -0,0 +1,13 @@ -+2012-05-25 Ian Bolton -+ Jim MacArthur -+ Marcus Shawcroft -+ Nigel Stephens -+ Ramana Radhakrishnan -+ Richard Earnshaw -+ Sofiane Naci -+ Stephen Thomas -+ Tejas Belagod -+ Yufeng Zhang -+ -+ * configure.ac: Enable AArch64. -+ * configure: Regenerate. diff -Nru gcc-4.7-4.7.2/debian/patches/aarch64-hash-style-gnu.diff gcc-4.7-4.7.3/debian/patches/aarch64-hash-style-gnu.diff --- gcc-4.7-4.7.2/debian/patches/aarch64-hash-style-gnu.diff 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/aarch64-hash-style-gnu.diff 2013-07-25 18:49:34.000000000 +0000 @@ -0,0 +1,18 @@ +# DP: Link using --hash-style=gnu (aarch64). + +2012-11-17 Matthias Klose + + * config/aarch64/aarch64-linux.h (LINK_SPEC): Add --hash-style=gnu. + +Index: b/src/gcc/config/aarch64/aarch64-linux.h +=================================================================== +--- a/src/gcc/config/aarch64/aarch64-linux.h ++++ b/src/gcc/config/aarch64/aarch64-linux.h +@@ -32,6 +32,7 @@ + #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64.so.1" + + #define LINUX_TARGET_LINK_SPEC "%{h*} \ ++ --hash-style=gnu \ + %{static:-Bstatic} \ + %{shared:-shared} \ + %{symbolic:-Bsymbolic} \ diff -Nru gcc-4.7-4.7.2/debian/patches/aarch64-libffi-testsuite.diff gcc-4.7-4.7.3/debian/patches/aarch64-libffi-testsuite.diff --- gcc-4.7-4.7.2/debian/patches/aarch64-libffi-testsuite.diff 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/aarch64-libffi-testsuite.diff 2013-07-25 18:49:34.000000000 +0000 @@ -0,0 +1,1109 @@ +Index: b/src/libffi/testsuite/lib/libffi.exp +=================================================================== +--- a/src/libffi/testsuite/lib/libffi.exp ++++ b/src/libffi/testsuite/lib/libffi.exp +@@ -209,6 +209,10 @@ + + lappend options "libs= -lffi" + ++ if { [string match "aarch64*-*-linux*" $target_triplet] } { ++ lappend options "libs= -lpthread" ++ } ++ + verbose "options: $options" + return [target_compile $source $dest $type $options] + } +Index: b/src/libffi/testsuite/libffi.call/cls_struct_va1.c +=================================================================== +--- /dev/null ++++ b/src/libffi/testsuite/libffi.call/cls_struct_va1.c +@@ -0,0 +1,114 @@ ++/* Area: ffi_call, closure_call ++ Purpose: Test doubles passed in variable argument lists. ++ Limitations: none. ++ PR: none. ++ Originator: Blake Chaffin 6/6/2007 */ ++ ++/* { dg-do run } */ ++/* { dg-output "" { xfail avr32*-*-* } } */ ++#include "ffitest.h" ++ ++struct small_tag ++{ ++ unsigned char a; ++ unsigned char b; ++}; ++ ++struct large_tag ++{ ++ unsigned a; ++ unsigned b; ++ unsigned c; ++ unsigned d; ++ unsigned e; ++}; ++ ++static void ++test_fn (ffi_cif* cif __UNUSED__, void* resp, ++ void** args, void* userdata __UNUSED__) ++{ ++ int n = *(int*)args[0]; ++ struct small_tag s1 = * (struct small_tag *) args[1]; ++ struct large_tag l1 = * (struct large_tag *) args[2]; ++ struct small_tag s2 = * (struct small_tag *) args[3]; ++ ++ printf ("%d %d %d %d %d %d %d %d %d %d\n", n, s1.a, s1.b, ++ l1.a, l1.b, l1.c, l1.d, l1.e, ++ s2.a, s2.b); ++ * (int*) resp = 42; ++} ++ ++int ++main (void) ++{ ++ ffi_cif cif; ++ void *code; ++ ffi_closure *pcl = ffi_closure_alloc (sizeof (ffi_closure), &code); ++ ffi_type* arg_types[5]; ++ ++ ffi_arg res = 0; ++ ++ ffi_type s_type; ++ ffi_type *s_type_elements[3]; ++ ++ ffi_type l_type; ++ ffi_type *l_type_elements[6]; ++ ++ struct small_tag s1; ++ struct small_tag s2; ++ struct large_tag l1; ++ ++ int si; ++ ++ s_type.size = 0; ++ s_type.alignment = 0; ++ s_type.type = FFI_TYPE_STRUCT; ++ s_type.elements = s_type_elements; ++ ++ s_type_elements[0] = &ffi_type_uchar; ++ s_type_elements[1] = &ffi_type_uchar; ++ s_type_elements[2] = NULL; ++ ++ l_type.size = 0; ++ l_type.alignment = 0; ++ l_type.type = FFI_TYPE_STRUCT; ++ l_type.elements = l_type_elements; ++ ++ l_type_elements[0] = &ffi_type_uint; ++ l_type_elements[1] = &ffi_type_uint; ++ l_type_elements[2] = &ffi_type_uint; ++ l_type_elements[3] = &ffi_type_uint; ++ l_type_elements[4] = &ffi_type_uint; ++ l_type_elements[5] = NULL; ++ ++ arg_types[0] = &ffi_type_sint; ++ arg_types[1] = &s_type; ++ arg_types[2] = &l_type; ++ arg_types[3] = &s_type; ++ arg_types[4] = NULL; ++ ++ CHECK(ffi_prep_cif_var(&cif, FFI_DEFAULT_ABI, 1, 4, &ffi_type_sint, ++ arg_types) == FFI_OK); ++ ++ si = 4; ++ s1.a = 5; ++ s1.b = 6; ++ ++ s2.a = 20; ++ s2.b = 21; ++ ++ l1.a = 10; ++ l1.b = 11; ++ l1.c = 12; ++ l1.d = 13; ++ l1.e = 14; ++ ++ CHECK(ffi_prep_closure_loc(pcl, &cif, test_fn, NULL, code) == FFI_OK); ++ ++ res = ((int (*)(int, ...))(code))(si, s1, l1, s2); ++ // { dg-output "4 5 6 10 11 12 13 14 20 21" } ++ printf("res: %d\n", (int) res); ++ // { dg-output "\nres: 42" } ++ ++ exit(0); ++} +Index: b/src/libffi/testsuite/libffi.call/cls_uchar_va.c +=================================================================== +--- /dev/null ++++ b/src/libffi/testsuite/libffi.call/cls_uchar_va.c +@@ -0,0 +1,44 @@ ++/* Area: closure_call ++ Purpose: Test anonymous unsigned char argument. ++ Limitations: none. ++ PR: none. ++ Originator: ARM Ltd. */ ++ ++/* { dg-do run } */ ++#include "ffitest.h" ++ ++typedef unsigned char T; ++ ++static void cls_ret_T_fn(ffi_cif* cif __UNUSED__, void* resp, void** args, ++ void* userdata __UNUSED__) ++ { ++ *(T *)resp = *(T *)args[0]; ++ ++ printf("%d: %d %d\n", *(T *)resp, *(T *)args[0], *(T *)args[1]); ++ } ++ ++typedef T (*cls_ret_T)(T, ...); ++ ++int main (void) ++{ ++ ffi_cif cif; ++ void *code; ++ ffi_closure *pcl = ffi_closure_alloc(sizeof(ffi_closure), &code); ++ ffi_type * cl_arg_types[3]; ++ T res; ++ ++ cl_arg_types[0] = &ffi_type_uchar; ++ cl_arg_types[1] = &ffi_type_uchar; ++ cl_arg_types[2] = NULL; ++ ++ /* Initialize the cif */ ++ CHECK(ffi_prep_cif_var(&cif, FFI_DEFAULT_ABI, 1, 2, ++ &ffi_type_uchar, cl_arg_types) == FFI_OK); ++ ++ CHECK(ffi_prep_closure_loc(pcl, &cif, cls_ret_T_fn, NULL, code) == FFI_OK); ++ res = ((((cls_ret_T)code)(67, 4))); ++ /* { dg-output "67: 67 4" } */ ++ printf("res: %d\n", res); ++ /* { dg-output "\nres: 67" } */ ++ exit(0); ++} +Index: b/src/libffi/testsuite/libffi.call/cls_uint_va.c +=================================================================== +--- /dev/null ++++ b/src/libffi/testsuite/libffi.call/cls_uint_va.c +@@ -0,0 +1,45 @@ ++/* Area: closure_call ++ Purpose: Test anonymous unsigned int argument. ++ Limitations: none. ++ PR: none. ++ Originator: ARM Ltd. */ ++ ++/* { dg-do run } */ ++ ++#include "ffitest.h" ++ ++typedef unsigned int T; ++ ++static void cls_ret_T_fn(ffi_cif* cif __UNUSED__, void* resp, void** args, ++ void* userdata __UNUSED__) ++ { ++ *(T *)resp = *(T *)args[0]; ++ ++ printf("%d: %d %d\n", *(T *)resp, *(T *)args[0], *(T *)args[1]); ++ } ++ ++typedef T (*cls_ret_T)(T, ...); ++ ++int main (void) ++{ ++ ffi_cif cif; ++ void *code; ++ ffi_closure *pcl = ffi_closure_alloc(sizeof(ffi_closure), &code); ++ ffi_type * cl_arg_types[3]; ++ T res; ++ ++ cl_arg_types[0] = &ffi_type_uint; ++ cl_arg_types[1] = &ffi_type_uint; ++ cl_arg_types[2] = NULL; ++ ++ /* Initialize the cif */ ++ CHECK(ffi_prep_cif_var(&cif, FFI_DEFAULT_ABI, 1, 2, ++ &ffi_type_uint, cl_arg_types) == FFI_OK); ++ ++ CHECK(ffi_prep_closure_loc(pcl, &cif, cls_ret_T_fn, NULL, code) == FFI_OK); ++ res = ((((cls_ret_T)code)(67, 4))); ++ /* { dg-output "67: 67 4" } */ ++ printf("res: %d\n", res); ++ /* { dg-output "\nres: 67" } */ ++ exit(0); ++} +Index: b/src/libffi/testsuite/libffi.call/cls_ulong_va.c +=================================================================== +--- /dev/null ++++ b/src/libffi/testsuite/libffi.call/cls_ulong_va.c +@@ -0,0 +1,45 @@ ++/* Area: closure_call ++ Purpose: Test anonymous unsigned long argument. ++ Limitations: none. ++ PR: none. ++ Originator: ARM Ltd. */ ++ ++/* { dg-do run } */ ++ ++#include "ffitest.h" ++ ++typedef unsigned long T; ++ ++static void cls_ret_T_fn(ffi_cif* cif __UNUSED__, void* resp, void** args, ++ void* userdata __UNUSED__) ++ { ++ *(T *)resp = *(T *)args[0]; ++ ++ printf("%ld: %ld %ld\n", *(T *)resp, *(T *)args[0], *(T *)args[1]); ++ } ++ ++typedef T (*cls_ret_T)(T, ...); ++ ++int main (void) ++{ ++ ffi_cif cif; ++ void *code; ++ ffi_closure *pcl = ffi_closure_alloc(sizeof(ffi_closure), &code); ++ ffi_type * cl_arg_types[3]; ++ T res; ++ ++ cl_arg_types[0] = &ffi_type_ulong; ++ cl_arg_types[1] = &ffi_type_ulong; ++ cl_arg_types[2] = NULL; ++ ++ /* Initialize the cif */ ++ CHECK(ffi_prep_cif_var(&cif, FFI_DEFAULT_ABI, 1, 2, ++ &ffi_type_ulong, cl_arg_types) == FFI_OK); ++ ++ CHECK(ffi_prep_closure_loc(pcl, &cif, cls_ret_T_fn, NULL, code) == FFI_OK); ++ res = ((((cls_ret_T)code)(67, 4))); ++ /* { dg-output "67: 67 4" } */ ++ printf("res: %ld\n", res); ++ /* { dg-output "\nres: 67" } */ ++ exit(0); ++} +Index: b/src/libffi/testsuite/libffi.call/cls_ushort_va.c +=================================================================== +--- /dev/null ++++ b/src/libffi/testsuite/libffi.call/cls_ushort_va.c +@@ -0,0 +1,44 @@ ++/* Area: closure_call ++ Purpose: Test anonymous unsigned short argument. ++ Limitations: none. ++ PR: none. ++ Originator: ARM Ltd. */ ++ ++/* { dg-do run } */ ++#include "ffitest.h" ++ ++typedef unsigned short T; ++ ++static void cls_ret_T_fn(ffi_cif* cif __UNUSED__, void* resp, void** args, ++ void* userdata __UNUSED__) ++ { ++ *(T *)resp = *(T *)args[0]; ++ ++ printf("%d: %d %d\n", *(T *)resp, *(T *)args[0], *(T *)args[1]); ++ } ++ ++typedef T (*cls_ret_T)(T, ...); ++ ++int main (void) ++{ ++ ffi_cif cif; ++ void *code; ++ ffi_closure *pcl = ffi_closure_alloc(sizeof(ffi_closure), &code); ++ ffi_type * cl_arg_types[3]; ++ T res; ++ ++ cl_arg_types[0] = &ffi_type_ushort; ++ cl_arg_types[1] = &ffi_type_ushort; ++ cl_arg_types[2] = NULL; ++ ++ /* Initialize the cif */ ++ CHECK(ffi_prep_cif_var(&cif, FFI_DEFAULT_ABI, 1, 2, ++ &ffi_type_ushort, cl_arg_types) == FFI_OK); ++ ++ CHECK(ffi_prep_closure_loc(pcl, &cif, cls_ret_T_fn, NULL, code) == FFI_OK); ++ res = ((((cls_ret_T)code)(67, 4))); ++ /* { dg-output "67: 67 4" } */ ++ printf("res: %d\n", res); ++ /* { dg-output "\nres: 67" } */ ++ exit(0); ++} +Index: b/src/libffi/testsuite/libffi.call/nested_struct11.c +=================================================================== +--- /dev/null ++++ b/src/libffi/testsuite/libffi.call/nested_struct11.c +@@ -0,0 +1,121 @@ ++/* Area: ffi_call, closure_call ++ Purpose: Check parameter passing with nested structs ++ of a single type. This tests the special cases ++ for homogenous floating-point aggregates in the ++ AArch64 PCS. ++ Limitations: none. ++ PR: none. ++ Originator: ARM Ltd. */ ++ ++/* { dg-do run } */ ++#include "ffitest.h" ++ ++typedef struct A { ++ float a_x; ++ float a_y; ++} A; ++ ++typedef struct B { ++ float b_x; ++ float b_y; ++} B; ++ ++typedef struct C { ++ A a; ++ B b; ++} C; ++ ++static C C_fn (int x, int y, int z, C source, int i, int j, int k) ++{ ++ C result; ++ result.a.a_x = source.a.a_x; ++ result.a.a_y = source.a.a_y; ++ result.b.b_x = source.b.b_x; ++ result.b.b_y = source.b.b_y; ++ ++ printf ("%d, %d, %d, %d, %d, %d\n", x, y, z, i, j, k); ++ ++ printf ("%.1f, %.1f, %.1f, %.1f, " ++ "%.1f, %.1f, %.1f, %.1f\n", ++ source.a.a_x, source.a.a_y, ++ source.b.b_x, source.b.b_y, ++ result.a.a_x, result.a.a_y, ++ result.b.b_x, result.b.b_y); ++ ++ return result; ++} ++ ++int main (void) ++{ ++ ffi_cif cif; ++ ++ ffi_type* struct_fields_source_a[3]; ++ ffi_type* struct_fields_source_b[3]; ++ ffi_type* struct_fields_source_c[3]; ++ ffi_type* arg_types[8]; ++ ++ ffi_type struct_type_a, struct_type_b, struct_type_c; ++ ++ struct A source_fld_a = {1.0, 2.0}; ++ struct B source_fld_b = {4.0, 8.0}; ++ int k = 1; ++ ++ struct C result; ++ struct C source = {source_fld_a, source_fld_b}; ++ ++ struct_type_a.size = 0; ++ struct_type_a.alignment = 0; ++ struct_type_a.type = FFI_TYPE_STRUCT; ++ struct_type_a.elements = struct_fields_source_a; ++ ++ struct_type_b.size = 0; ++ struct_type_b.alignment = 0; ++ struct_type_b.type = FFI_TYPE_STRUCT; ++ struct_type_b.elements = struct_fields_source_b; ++ ++ struct_type_c.size = 0; ++ struct_type_c.alignment = 0; ++ struct_type_c.type = FFI_TYPE_STRUCT; ++ struct_type_c.elements = struct_fields_source_c; ++ ++ struct_fields_source_a[0] = &ffi_type_float; ++ struct_fields_source_a[1] = &ffi_type_float; ++ struct_fields_source_a[2] = NULL; ++ ++ struct_fields_source_b[0] = &ffi_type_float; ++ struct_fields_source_b[1] = &ffi_type_float; ++ struct_fields_source_b[2] = NULL; ++ ++ struct_fields_source_c[0] = &struct_type_a; ++ struct_fields_source_c[1] = &struct_type_b; ++ struct_fields_source_c[2] = NULL; ++ ++ arg_types[0] = &ffi_type_sint32; ++ arg_types[1] = &ffi_type_sint32; ++ arg_types[2] = &ffi_type_sint32; ++ arg_types[3] = &struct_type_c; ++ arg_types[4] = &ffi_type_sint32; ++ arg_types[5] = &ffi_type_sint32; ++ arg_types[6] = &ffi_type_sint32; ++ arg_types[7] = NULL; ++ ++ void *args[7]; ++ args[0] = &k; ++ args[1] = &k; ++ args[2] = &k; ++ args[3] = &source; ++ args[4] = &k; ++ args[5] = &k; ++ args[6] = &k; ++ CHECK (ffi_prep_cif (&cif, FFI_DEFAULT_ABI, 7, &struct_type_c, ++ arg_types) == FFI_OK); ++ ++ ffi_call (&cif, FFI_FN (C_fn), &result, args); ++ /* { dg-output "1, 1, 1, 1, 1, 1\n" } */ ++ /* { dg-output "1.0, 2.0, 4.0, 8.0, 1.0, 2.0, 4.0, 8.0" } */ ++ CHECK (result.a.a_x == source.a.a_x); ++ CHECK (result.a.a_y == source.a.a_y); ++ CHECK (result.b.b_x == source.b.b_x); ++ CHECK (result.b.b_y == source.b.b_y); ++ exit (0); ++} +Index: b/src/libffi/testsuite/libffi.call/uninitialized.c +=================================================================== +--- /dev/null ++++ b/src/libffi/testsuite/libffi.call/uninitialized.c +@@ -0,0 +1,61 @@ ++/* { dg-do run } */ ++#include "ffitest.h" ++ ++typedef struct ++{ ++ unsigned char uc; ++ double d; ++ unsigned int ui; ++} test_structure_1; ++ ++static test_structure_1 struct1(test_structure_1 ts) ++{ ++ ts.uc++; ++ ts.d--; ++ ts.ui++; ++ ++ return ts; ++} ++ ++int main (void) ++{ ++ ffi_cif cif; ++ ffi_type *args[MAX_ARGS]; ++ void *values[MAX_ARGS]; ++ ffi_type ts1_type; ++ ffi_type *ts1_type_elements[4]; ++ ++ memset(&cif, 1, sizeof(cif)); ++ ts1_type.size = 0; ++ ts1_type.alignment = 0; ++ ts1_type.type = FFI_TYPE_STRUCT; ++ ts1_type.elements = ts1_type_elements; ++ ts1_type_elements[0] = &ffi_type_uchar; ++ ts1_type_elements[1] = &ffi_type_double; ++ ts1_type_elements[2] = &ffi_type_uint; ++ ts1_type_elements[3] = NULL; ++ ++ test_structure_1 ts1_arg; ++ /* This is a hack to get a properly aligned result buffer */ ++ test_structure_1 *ts1_result = ++ (test_structure_1 *) malloc (sizeof(test_structure_1)); ++ ++ args[0] = &ts1_type; ++ values[0] = &ts1_arg; ++ ++ /* Initialize the cif */ ++ CHECK(ffi_prep_cif(&cif, FFI_DEFAULT_ABI, 1, ++ &ts1_type, args) == FFI_OK); ++ ++ ts1_arg.uc = '\x01'; ++ ts1_arg.d = 3.14159; ++ ts1_arg.ui = 555; ++ ++ ffi_call(&cif, FFI_FN(struct1), ts1_result, values); ++ ++ CHECK(ts1_result->ui == 556); ++ CHECK(ts1_result->d == 3.14159 - 1); ++ ++ free (ts1_result); ++ exit(0); ++} +Index: b/src/libffi/testsuite/libffi.call/va_1.c +=================================================================== +--- /dev/null ++++ b/src/libffi/testsuite/libffi.call/va_1.c +@@ -0,0 +1,196 @@ ++/* Area: ffi_call ++ Purpose: Test passing struct in variable argument lists. ++ Limitations: none. ++ PR: none. ++ Originator: ARM Ltd. */ ++ ++/* { dg-do run } */ ++/* { dg-output "" { xfail avr32*-*-* x86_64-*-*-* } } */ ++ ++#include "ffitest.h" ++#include ++ ++struct small_tag ++{ ++ unsigned char a; ++ unsigned char b; ++}; ++ ++struct large_tag ++{ ++ unsigned a; ++ unsigned b; ++ unsigned c; ++ unsigned d; ++ unsigned e; ++}; ++ ++static int ++test_fn (int n, ...) ++{ ++ va_list ap; ++ struct small_tag s1; ++ struct small_tag s2; ++ struct large_tag l; ++ unsigned char uc; ++ signed char sc; ++ unsigned short us; ++ signed short ss; ++ unsigned int ui; ++ signed int si; ++ unsigned long ul; ++ signed long sl; ++ float f; ++ double d; ++ ++ va_start (ap, n); ++ s1 = va_arg (ap, struct small_tag); ++ l = va_arg (ap, struct large_tag); ++ s2 = va_arg (ap, struct small_tag); ++ ++ uc = va_arg (ap, unsigned); ++ sc = va_arg (ap, signed); ++ ++ us = va_arg (ap, unsigned); ++ ss = va_arg (ap, signed); ++ ++ ui = va_arg (ap, unsigned int); ++ si = va_arg (ap, signed int); ++ ++ ul = va_arg (ap, unsigned long); ++ sl = va_arg (ap, signed long); ++ ++ f = va_arg (ap, double); /* C standard promotes float->double ++ when anonymous */ ++ d = va_arg (ap, double); ++ ++ printf ("%u %u %u %u %u %u %u %u %u uc=%u sc=%d %u %d %u %d %lu %ld %f %f\n", ++ s1.a, s1.b, l.a, l.b, l.c, l.d, l.e, ++ s2.a, s2.b, ++ uc, sc, ++ us, ss, ++ ui, si, ++ ul, sl, ++ f, d); ++ va_end (ap); ++ return n + 1; ++} ++ ++int ++main (void) ++{ ++ ffi_cif cif; ++ void* args[15]; ++ ffi_type* arg_types[15]; ++ ++ ffi_type s_type; ++ ffi_type *s_type_elements[3]; ++ ++ ffi_type l_type; ++ ffi_type *l_type_elements[6]; ++ ++ struct small_tag s1; ++ struct small_tag s2; ++ struct large_tag l1; ++ ++ int n; ++ int res; ++ ++ unsigned char uc; ++ signed char sc; ++ unsigned short us; ++ signed short ss; ++ unsigned int ui; ++ signed int si; ++ unsigned long ul; ++ signed long sl; ++ double d1; ++ double f1; ++ ++ s_type.size = 0; ++ s_type.alignment = 0; ++ s_type.type = FFI_TYPE_STRUCT; ++ s_type.elements = s_type_elements; ++ ++ s_type_elements[0] = &ffi_type_uchar; ++ s_type_elements[1] = &ffi_type_uchar; ++ s_type_elements[2] = NULL; ++ ++ l_type.size = 0; ++ l_type.alignment = 0; ++ l_type.type = FFI_TYPE_STRUCT; ++ l_type.elements = l_type_elements; ++ ++ l_type_elements[0] = &ffi_type_uint; ++ l_type_elements[1] = &ffi_type_uint; ++ l_type_elements[2] = &ffi_type_uint; ++ l_type_elements[3] = &ffi_type_uint; ++ l_type_elements[4] = &ffi_type_uint; ++ l_type_elements[5] = NULL; ++ ++ arg_types[0] = &ffi_type_sint; ++ arg_types[1] = &s_type; ++ arg_types[2] = &l_type; ++ arg_types[3] = &s_type; ++ arg_types[4] = &ffi_type_uint; ++ arg_types[5] = &ffi_type_sint; ++ arg_types[6] = &ffi_type_uint; ++ arg_types[7] = &ffi_type_sint; ++ arg_types[8] = &ffi_type_uint; ++ arg_types[9] = &ffi_type_sint; ++ arg_types[10] = &ffi_type_ulong; ++ arg_types[11] = &ffi_type_slong; ++ arg_types[12] = &ffi_type_double; ++ arg_types[13] = &ffi_type_double; ++ arg_types[14] = NULL; ++ ++ CHECK(ffi_prep_cif_var(&cif, FFI_DEFAULT_ABI, 1, 14, &ffi_type_sint, arg_types) == FFI_OK); ++ ++ s1.a = 5; ++ s1.b = 6; ++ ++ l1.a = 10; ++ l1.b = 11; ++ l1.c = 12; ++ l1.d = 13; ++ l1.e = 14; ++ ++ s2.a = 7; ++ s2.b = 8; ++ ++ n = 41; ++ ++ uc = 9; ++ sc = 10; ++ us = 11; ++ ss = 12; ++ ui = 13; ++ si = 14; ++ ul = 15; ++ sl = 16; ++ f1 = 2.12; ++ d1 = 3.13; ++ ++ args[0] = &n; ++ args[1] = &s1; ++ args[2] = &l1; ++ args[3] = &s2; ++ args[4] = &uc; ++ args[5] = ≻ ++ args[6] = &us; ++ args[7] = &ss; ++ args[8] = &ui; ++ args[9] = &si; ++ args[10] = &ul; ++ args[11] = &sl; ++ args[12] = &f1; ++ args[13] = &d1; ++ args[14] = NULL; ++ ++ ffi_call(&cif, FFI_FN(test_fn), &res, args); ++ /* { dg-output "5 6 10 11 12 13 14 7 8 uc=9 sc=10 11 12 13 14 15 16 2.120000 3.130000" } */ ++ printf("res: %d\n", (int) res); ++ /* { dg-output "\nres: 42" } */ ++ ++ return 0; ++} +Index: b/src/libffi/testsuite/libffi.call/va_struct1.c +=================================================================== +--- /dev/null ++++ b/src/libffi/testsuite/libffi.call/va_struct1.c +@@ -0,0 +1,121 @@ ++/* Area: ffi_call ++ Purpose: Test passing struct in variable argument lists. ++ Limitations: none. ++ PR: none. ++ Originator: ARM Ltd. */ ++ ++/* { dg-do run } */ ++/* { dg-output "" { xfail avr32*-*-* } } */ ++ ++#include "ffitest.h" ++#include ++ ++struct small_tag ++{ ++ unsigned char a; ++ unsigned char b; ++}; ++ ++struct large_tag ++{ ++ unsigned a; ++ unsigned b; ++ unsigned c; ++ unsigned d; ++ unsigned e; ++}; ++ ++static int ++test_fn (int n, ...) ++{ ++ va_list ap; ++ struct small_tag s1; ++ struct small_tag s2; ++ struct large_tag l; ++ ++ va_start (ap, n); ++ s1 = va_arg (ap, struct small_tag); ++ l = va_arg (ap, struct large_tag); ++ s2 = va_arg (ap, struct small_tag); ++ printf ("%u %u %u %u %u %u %u %u %u\n", s1.a, s1.b, l.a, l.b, l.c, l.d, l.e, ++ s2.a, s2.b); ++ va_end (ap); ++ return n + 1; ++} ++ ++int ++main (void) ++{ ++ ffi_cif cif; ++ void* args[5]; ++ ffi_type* arg_types[5]; ++ ++ ffi_type s_type; ++ ffi_type *s_type_elements[3]; ++ ++ ffi_type l_type; ++ ffi_type *l_type_elements[6]; ++ ++ struct small_tag s1; ++ struct small_tag s2; ++ struct large_tag l1; ++ ++ int n; ++ int res; ++ ++ s_type.size = 0; ++ s_type.alignment = 0; ++ s_type.type = FFI_TYPE_STRUCT; ++ s_type.elements = s_type_elements; ++ ++ s_type_elements[0] = &ffi_type_uchar; ++ s_type_elements[1] = &ffi_type_uchar; ++ s_type_elements[2] = NULL; ++ ++ l_type.size = 0; ++ l_type.alignment = 0; ++ l_type.type = FFI_TYPE_STRUCT; ++ l_type.elements = l_type_elements; ++ ++ l_type_elements[0] = &ffi_type_uint; ++ l_type_elements[1] = &ffi_type_uint; ++ l_type_elements[2] = &ffi_type_uint; ++ l_type_elements[3] = &ffi_type_uint; ++ l_type_elements[4] = &ffi_type_uint; ++ l_type_elements[5] = NULL; ++ ++ arg_types[0] = &ffi_type_sint; ++ arg_types[1] = &s_type; ++ arg_types[2] = &l_type; ++ arg_types[3] = &s_type; ++ arg_types[4] = NULL; ++ ++ CHECK(ffi_prep_cif_var(&cif, FFI_DEFAULT_ABI, 1, 4, &ffi_type_sint, arg_types) == FFI_OK); ++ ++ s1.a = 5; ++ s1.b = 6; ++ ++ l1.a = 10; ++ l1.b = 11; ++ l1.c = 12; ++ l1.d = 13; ++ l1.e = 14; ++ ++ s2.a = 7; ++ s2.b = 8; ++ ++ n = 41; ++ ++ args[0] = &n; ++ args[1] = &s1; ++ args[2] = &l1; ++ args[3] = &s2; ++ args[4] = NULL; ++ ++ ffi_call(&cif, FFI_FN(test_fn), &res, args); ++ /* { dg-output "5 6 10 11 12 13 14 7 8" } */ ++ printf("res: %d\n", (int) res); ++ /* { dg-output "\nres: 42" } */ ++ ++ return 0; ++} +Index: b/src/libffi/testsuite/libffi.call/va_struct2.c +=================================================================== +--- /dev/null ++++ b/src/libffi/testsuite/libffi.call/va_struct2.c +@@ -0,0 +1,123 @@ ++/* Area: ffi_call ++ Purpose: Test passing struct in variable argument lists. ++ Limitations: none. ++ PR: none. ++ Originator: ARM Ltd. */ ++ ++/* { dg-do run } */ ++/* { dg-output "" { xfail avr32*-*-* } } */ ++ ++#include "ffitest.h" ++#include ++ ++struct small_tag ++{ ++ unsigned char a; ++ unsigned char b; ++}; ++ ++struct large_tag ++{ ++ unsigned a; ++ unsigned b; ++ unsigned c; ++ unsigned d; ++ unsigned e; ++}; ++ ++static struct small_tag ++test_fn (int n, ...) ++{ ++ va_list ap; ++ struct small_tag s1; ++ struct small_tag s2; ++ struct large_tag l; ++ ++ va_start (ap, n); ++ s1 = va_arg (ap, struct small_tag); ++ l = va_arg (ap, struct large_tag); ++ s2 = va_arg (ap, struct small_tag); ++ printf ("%u %u %u %u %u %u %u %u %u\n", s1.a, s1.b, l.a, l.b, l.c, l.d, l.e, ++ s2.a, s2.b); ++ va_end (ap); ++ s1.a += s2.a; ++ s1.b += s2.b; ++ return s1; ++} ++ ++int ++main (void) ++{ ++ ffi_cif cif; ++ void* args[5]; ++ ffi_type* arg_types[5]; ++ ++ ffi_type s_type; ++ ffi_type *s_type_elements[3]; ++ ++ ffi_type l_type; ++ ffi_type *l_type_elements[6]; ++ ++ struct small_tag s1; ++ struct small_tag s2; ++ struct large_tag l1; ++ ++ int n; ++ struct small_tag res; ++ ++ s_type.size = 0; ++ s_type.alignment = 0; ++ s_type.type = FFI_TYPE_STRUCT; ++ s_type.elements = s_type_elements; ++ ++ s_type_elements[0] = &ffi_type_uchar; ++ s_type_elements[1] = &ffi_type_uchar; ++ s_type_elements[2] = NULL; ++ ++ l_type.size = 0; ++ l_type.alignment = 0; ++ l_type.type = FFI_TYPE_STRUCT; ++ l_type.elements = l_type_elements; ++ ++ l_type_elements[0] = &ffi_type_uint; ++ l_type_elements[1] = &ffi_type_uint; ++ l_type_elements[2] = &ffi_type_uint; ++ l_type_elements[3] = &ffi_type_uint; ++ l_type_elements[4] = &ffi_type_uint; ++ l_type_elements[5] = NULL; ++ ++ arg_types[0] = &ffi_type_sint; ++ arg_types[1] = &s_type; ++ arg_types[2] = &l_type; ++ arg_types[3] = &s_type; ++ arg_types[4] = NULL; ++ ++ CHECK(ffi_prep_cif_var(&cif, FFI_DEFAULT_ABI, 1, 4, &s_type, arg_types) == FFI_OK); ++ ++ s1.a = 5; ++ s1.b = 6; ++ ++ l1.a = 10; ++ l1.b = 11; ++ l1.c = 12; ++ l1.d = 13; ++ l1.e = 14; ++ ++ s2.a = 7; ++ s2.b = 8; ++ ++ n = 41; ++ ++ args[0] = &n; ++ args[1] = &s1; ++ args[2] = &l1; ++ args[3] = &s2; ++ args[4] = NULL; ++ ++ ffi_call(&cif, FFI_FN(test_fn), &res, args); ++ /* { dg-output "5 6 10 11 12 13 14 7 8" } */ ++ printf("res: %d %d\n", res.a, res.b); ++ /* { dg-output "\nres: 12 14" } */ ++ ++ return 0; ++} +Index: b/src/libffi/testsuite/libffi.call/va_struct3.c +=================================================================== +--- /dev/null ++++ b/src/libffi/testsuite/libffi.call/va_struct3.c +@@ -0,0 +1,125 @@ ++/* Area: ffi_call ++ Purpose: Test passing struct in variable argument lists. ++ Limitations: none. ++ PR: none. ++ Originator: ARM Ltd. */ ++ ++/* { dg-do run } */ ++/* { dg-output "" { xfail avr32*-*-* } } */ ++ ++#include "ffitest.h" ++#include ++ ++struct small_tag ++{ ++ unsigned char a; ++ unsigned char b; ++}; ++ ++struct large_tag ++{ ++ unsigned a; ++ unsigned b; ++ unsigned c; ++ unsigned d; ++ unsigned e; ++}; ++ ++static struct large_tag ++test_fn (int n, ...) ++{ ++ va_list ap; ++ struct small_tag s1; ++ struct small_tag s2; ++ struct large_tag l; ++ ++ va_start (ap, n); ++ s1 = va_arg (ap, struct small_tag); ++ l = va_arg (ap, struct large_tag); ++ s2 = va_arg (ap, struct small_tag); ++ printf ("%u %u %u %u %u %u %u %u %u\n", s1.a, s1.b, l.a, l.b, l.c, l.d, l.e, ++ s2.a, s2.b); ++ va_end (ap); ++ l.a += s1.a; ++ l.b += s1.b; ++ l.c += s2.a; ++ l.d += s2.b; ++ return l; ++} ++ ++int ++main (void) ++{ ++ ffi_cif cif; ++ void* args[5]; ++ ffi_type* arg_types[5]; ++ ++ ffi_type s_type; ++ ffi_type *s_type_elements[3]; ++ ++ ffi_type l_type; ++ ffi_type *l_type_elements[6]; ++ ++ struct small_tag s1; ++ struct small_tag s2; ++ struct large_tag l1; ++ ++ int n; ++ struct large_tag res; ++ ++ s_type.size = 0; ++ s_type.alignment = 0; ++ s_type.type = FFI_TYPE_STRUCT; ++ s_type.elements = s_type_elements; ++ ++ s_type_elements[0] = &ffi_type_uchar; ++ s_type_elements[1] = &ffi_type_uchar; ++ s_type_elements[2] = NULL; ++ ++ l_type.size = 0; ++ l_type.alignment = 0; ++ l_type.type = FFI_TYPE_STRUCT; ++ l_type.elements = l_type_elements; ++ ++ l_type_elements[0] = &ffi_type_uint; ++ l_type_elements[1] = &ffi_type_uint; ++ l_type_elements[2] = &ffi_type_uint; ++ l_type_elements[3] = &ffi_type_uint; ++ l_type_elements[4] = &ffi_type_uint; ++ l_type_elements[5] = NULL; ++ ++ arg_types[0] = &ffi_type_sint; ++ arg_types[1] = &s_type; ++ arg_types[2] = &l_type; ++ arg_types[3] = &s_type; ++ arg_types[4] = NULL; ++ ++ CHECK(ffi_prep_cif_var(&cif, FFI_DEFAULT_ABI, 1, 4, &l_type, arg_types) == FFI_OK); ++ ++ s1.a = 5; ++ s1.b = 6; ++ ++ l1.a = 10; ++ l1.b = 11; ++ l1.c = 12; ++ l1.d = 13; ++ l1.e = 14; ++ ++ s2.a = 7; ++ s2.b = 8; ++ ++ n = 41; ++ ++ args[0] = &n; ++ args[1] = &s1; ++ args[2] = &l1; ++ args[3] = &s2; ++ args[4] = NULL; ++ ++ ffi_call(&cif, FFI_FN(test_fn), &res, args); ++ /* { dg-output "5 6 10 11 12 13 14 7 8" } */ ++ printf("res: %d %d %d %d %d\n", res.a, res.b, res.c, res.d, res.e); ++ /* { dg-output "\nres: 15 17 19 21 14" } */ ++ ++ return 0; ++} diff -Nru gcc-4.7-4.7.2/debian/patches/aarch64-libffi.diff gcc-4.7-4.7.3/debian/patches/aarch64-libffi.diff --- gcc-4.7-4.7.2/debian/patches/aarch64-libffi.diff 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/aarch64-libffi.diff 2013-07-25 18:49:34.000000000 +0000 @@ -0,0 +1,1705 @@ +Index: b/src/libffi/README +=================================================================== +--- a/src/libffi/README ++++ b/src/libffi/README +@@ -54,6 +54,7 @@ + |--------------+------------------| + | Architecture | Operating System | + |--------------+------------------| ++| AArch64 | Linux | + | Alpha | Linux | + | ARM | Linux | + | AVR32 | Linux | +@@ -284,6 +285,7 @@ + Major processor architecture ports were contributed by the following + developers: + ++aarch64 Marcus Shawcroft, James Greenhalgh + alpha Richard Henderson + arm Raffaele Sena + cris Simon Posnjak, Hans-Peter Nilsson +Index: b/src/libffi/src/aarch64/ffi.c +=================================================================== +--- /dev/null ++++ b/src/libffi/src/aarch64/ffi.c +@@ -0,0 +1,1076 @@ ++/* Copyright (c) 2009, 2010, 2011, 2012 ARM Ltd. ++ ++Permission is hereby granted, free of charge, to any person obtaining ++a copy of this software and associated documentation files (the ++``Software''), to deal in the Software without restriction, including ++without limitation the rights to use, copy, modify, merge, publish, ++distribute, sublicense, and/or sell copies of the Software, and to ++permit persons to whom the Software is furnished to do so, subject to ++the following conditions: ++ ++The above copyright notice and this permission notice shall be ++included in all copies or substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED ``AS IS'', WITHOUT WARRANTY OF ANY KIND, ++EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ++IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY ++CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE ++SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ ++ ++#include ++ ++#include ++#include ++ ++#include ++ ++/* Stack alignment requirement in bytes */ ++#define AARCH64_STACK_ALIGN 16 ++ ++#define N_X_ARG_REG 8 ++#define N_V_ARG_REG 8 ++ ++#define AARCH64_FFI_WITH_V (1 << AARCH64_FFI_WITH_V_BIT) ++ ++union _d ++{ ++ UINT64 d; ++ UINT32 s[2]; ++}; ++ ++struct call_context ++{ ++ UINT64 x [AARCH64_N_XREG]; ++ struct ++ { ++ union _d d[2]; ++ } v [AARCH64_N_VREG]; ++}; ++ ++static void * ++get_x_addr (struct call_context *context, unsigned n) ++{ ++ return &context->x[n]; ++} ++ ++static void * ++get_s_addr (struct call_context *context, unsigned n) ++{ ++#if defined __AARCH64EB__ ++ return &context->v[n].d[1].s[1]; ++#else ++ return &context->v[n].d[0].s[0]; ++#endif ++} ++ ++static void * ++get_d_addr (struct call_context *context, unsigned n) ++{ ++#if defined __AARCH64EB__ ++ return &context->v[n].d[1]; ++#else ++ return &context->v[n].d[0]; ++#endif ++} ++ ++static void * ++get_v_addr (struct call_context *context, unsigned n) ++{ ++ return &context->v[n]; ++} ++ ++/* Return the memory location at which a basic type would reside ++ were it to have been stored in register n. */ ++ ++static void * ++get_basic_type_addr (unsigned short type, struct call_context *context, ++ unsigned n) ++{ ++ switch (type) ++ { ++ case FFI_TYPE_FLOAT: ++ return get_s_addr (context, n); ++ case FFI_TYPE_DOUBLE: ++ return get_d_addr (context, n); ++ case FFI_TYPE_LONGDOUBLE: ++ return get_v_addr (context, n); ++ case FFI_TYPE_UINT8: ++ case FFI_TYPE_SINT8: ++ case FFI_TYPE_UINT16: ++ case FFI_TYPE_SINT16: ++ case FFI_TYPE_UINT32: ++ case FFI_TYPE_SINT32: ++ case FFI_TYPE_INT: ++ case FFI_TYPE_POINTER: ++ case FFI_TYPE_UINT64: ++ case FFI_TYPE_SINT64: ++ return get_x_addr (context, n); ++ default: ++ FFI_ASSERT (0); ++ return NULL; ++ } ++} ++ ++/* Return the alignment width for each of the basic types. */ ++ ++static size_t ++get_basic_type_alignment (unsigned short type) ++{ ++ switch (type) ++ { ++ case FFI_TYPE_FLOAT: ++ case FFI_TYPE_DOUBLE: ++ return sizeof (UINT64); ++ case FFI_TYPE_LONGDOUBLE: ++ return sizeof (long double); ++ case FFI_TYPE_UINT8: ++ case FFI_TYPE_SINT8: ++ case FFI_TYPE_UINT16: ++ case FFI_TYPE_SINT16: ++ case FFI_TYPE_UINT32: ++ case FFI_TYPE_INT: ++ case FFI_TYPE_SINT32: ++ case FFI_TYPE_POINTER: ++ case FFI_TYPE_UINT64: ++ case FFI_TYPE_SINT64: ++ return sizeof (UINT64); ++ ++ default: ++ FFI_ASSERT (0); ++ return 0; ++ } ++} ++ ++/* Return the size in bytes for each of the basic types. */ ++ ++static size_t ++get_basic_type_size (unsigned short type) ++{ ++ switch (type) ++ { ++ case FFI_TYPE_FLOAT: ++ return sizeof (UINT32); ++ case FFI_TYPE_DOUBLE: ++ return sizeof (UINT64); ++ case FFI_TYPE_LONGDOUBLE: ++ return sizeof (long double); ++ case FFI_TYPE_UINT8: ++ return sizeof (UINT8); ++ case FFI_TYPE_SINT8: ++ return sizeof (SINT8); ++ case FFI_TYPE_UINT16: ++ return sizeof (UINT16); ++ case FFI_TYPE_SINT16: ++ return sizeof (SINT16); ++ case FFI_TYPE_UINT32: ++ return sizeof (UINT32); ++ case FFI_TYPE_INT: ++ case FFI_TYPE_SINT32: ++ return sizeof (SINT32); ++ case FFI_TYPE_POINTER: ++ case FFI_TYPE_UINT64: ++ return sizeof (UINT64); ++ case FFI_TYPE_SINT64: ++ return sizeof (SINT64); ++ ++ default: ++ FFI_ASSERT (0); ++ return 0; ++ } ++} ++ ++extern void ++ffi_call_SYSV (unsigned (*)(struct call_context *context, unsigned char *, ++ extended_cif *), ++ struct call_context *context, ++ extended_cif *, ++ unsigned, ++ void (*fn)(void)); ++ ++extern void ++ffi_closure_SYSV (ffi_closure *); ++ ++/* Test for an FFI floating point representation. */ ++ ++static unsigned ++is_floating_type (unsigned short type) ++{ ++ return (type == FFI_TYPE_FLOAT || type == FFI_TYPE_DOUBLE ++ || type == FFI_TYPE_LONGDOUBLE); ++} ++ ++/* Test for a homogeneous structure. */ ++ ++static unsigned short ++get_homogeneous_type (ffi_type *ty) ++{ ++ if (ty->type == FFI_TYPE_STRUCT && ty->elements) ++ { ++ unsigned i; ++ unsigned short candidate_type ++ = get_homogeneous_type (ty->elements[0]); ++ for (i =1; ty->elements[i]; i++) ++ { ++ unsigned short iteration_type = 0; ++ /* If we have a nested struct, we must find its homogeneous type. ++ If that fits with our candidate type, we are still ++ homogeneous. */ ++ if (ty->elements[i]->type == FFI_TYPE_STRUCT ++ && ty->elements[i]->elements) ++ { ++ iteration_type = get_homogeneous_type (ty->elements[i]); ++ } ++ else ++ { ++ iteration_type = ty->elements[i]->type; ++ } ++ ++ /* If we are not homogeneous, return FFI_TYPE_STRUCT. */ ++ if (candidate_type != iteration_type) ++ return FFI_TYPE_STRUCT; ++ } ++ return candidate_type; ++ } ++ ++ /* Base case, we have no more levels of nesting, so we ++ are a basic type, and so, trivially homogeneous in that type. */ ++ return ty->type; ++} ++ ++/* Determine the number of elements within a STRUCT. ++ ++ Note, we must handle nested structs. ++ ++ If ty is not a STRUCT this function will return 0. */ ++ ++static unsigned ++element_count (ffi_type *ty) ++{ ++ if (ty->type == FFI_TYPE_STRUCT && ty->elements) ++ { ++ unsigned n; ++ unsigned elems = 0; ++ for (n = 0; ty->elements[n]; n++) ++ { ++ if (ty->elements[n]->type == FFI_TYPE_STRUCT ++ && ty->elements[n]->elements) ++ elems += element_count (ty->elements[n]); ++ else ++ elems++; ++ } ++ return elems; ++ } ++ return 0; ++} ++ ++/* Test for a homogeneous floating point aggregate. ++ ++ A homogeneous floating point aggregate is a homogeneous aggregate of ++ a half- single- or double- precision floating point type with one ++ to four elements. Note that this includes nested structs of the ++ basic type. */ ++ ++static int ++is_hfa (ffi_type *ty) ++{ ++ if (ty->type == FFI_TYPE_STRUCT ++ && ty->elements[0] ++ && is_floating_type (get_homogeneous_type (ty))) ++ { ++ unsigned n = element_count (ty); ++ return n >= 1 && n <= 4; ++ } ++ return 0; ++} ++ ++/* Test if an ffi_type is a candidate for passing in a register. ++ ++ This test does not check that sufficient registers of the ++ appropriate class are actually available, merely that IFF ++ sufficient registers are available then the argument will be passed ++ in register(s). ++ ++ Note that an ffi_type that is deemed to be a register candidate ++ will always be returned in registers. ++ ++ Returns 1 if a register candidate else 0. */ ++ ++static int ++is_register_candidate (ffi_type *ty) ++{ ++ switch (ty->type) ++ { ++ case FFI_TYPE_VOID: ++ case FFI_TYPE_FLOAT: ++ case FFI_TYPE_DOUBLE: ++ case FFI_TYPE_LONGDOUBLE: ++ case FFI_TYPE_UINT8: ++ case FFI_TYPE_UINT16: ++ case FFI_TYPE_UINT32: ++ case FFI_TYPE_UINT64: ++ case FFI_TYPE_POINTER: ++ case FFI_TYPE_SINT8: ++ case FFI_TYPE_SINT16: ++ case FFI_TYPE_SINT32: ++ case FFI_TYPE_INT: ++ case FFI_TYPE_SINT64: ++ return 1; ++ ++ case FFI_TYPE_STRUCT: ++ if (is_hfa (ty)) ++ { ++ return 1; ++ } ++ else if (ty->size > 16) ++ { ++ /* Too large. Will be replaced with a pointer to memory. The ++ pointer MAY be passed in a register, but the value will ++ not. This test specifically fails since the argument will ++ never be passed by value in registers. */ ++ return 0; ++ } ++ else ++ { ++ /* Might be passed in registers depending on the number of ++ registers required. */ ++ return (ty->size + 7) / 8 < N_X_ARG_REG; ++ } ++ break; ++ ++ default: ++ FFI_ASSERT (0); ++ break; ++ } ++ ++ return 0; ++} ++ ++/* Test if an ffi_type argument or result is a candidate for a vector ++ register. */ ++ ++static int ++is_v_register_candidate (ffi_type *ty) ++{ ++ return is_floating_type (ty->type) ++ || (ty->type == FFI_TYPE_STRUCT && is_hfa (ty)); ++} ++ ++/* Representation of the procedure call argument marshalling ++ state. ++ ++ The terse state variable names match the names used in the AARCH64 ++ PCS. */ ++ ++struct arg_state ++{ ++ unsigned ngrn; /* Next general-purpose register number. */ ++ unsigned nsrn; /* Next vector register number. */ ++ unsigned nsaa; /* Next stack offset. */ ++}; ++ ++/* Initialize a procedure call argument marshalling state. */ ++static void ++arg_init (struct arg_state *state, unsigned call_frame_size) ++{ ++ state->ngrn = 0; ++ state->nsrn = 0; ++ state->nsaa = 0; ++} ++ ++/* Return the number of available consecutive core argument ++ registers. */ ++ ++static unsigned ++available_x (struct arg_state *state) ++{ ++ return N_X_ARG_REG - state->ngrn; ++} ++ ++/* Return the number of available consecutive vector argument ++ registers. */ ++ ++static unsigned ++available_v (struct arg_state *state) ++{ ++ return N_V_ARG_REG - state->nsrn; ++} ++ ++static void * ++allocate_to_x (struct call_context *context, struct arg_state *state) ++{ ++ FFI_ASSERT (state->ngrn < N_X_ARG_REG) ++ return get_x_addr (context, (state->ngrn)++); ++} ++ ++static void * ++allocate_to_s (struct call_context *context, struct arg_state *state) ++{ ++ FFI_ASSERT (state->nsrn < N_V_ARG_REG) ++ return get_s_addr (context, (state->nsrn)++); ++} ++ ++static void * ++allocate_to_d (struct call_context *context, struct arg_state *state) ++{ ++ FFI_ASSERT (state->nsrn < N_V_ARG_REG) ++ return get_d_addr (context, (state->nsrn)++); ++} ++ ++static void * ++allocate_to_v (struct call_context *context, struct arg_state *state) ++{ ++ FFI_ASSERT (state->nsrn < N_V_ARG_REG) ++ return get_v_addr (context, (state->nsrn)++); ++} ++ ++/* Allocate an aligned slot on the stack and return a pointer to it. */ ++static void * ++allocate_to_stack (struct arg_state *state, void *stack, unsigned alignment, ++ unsigned size) ++{ ++ void *allocation; ++ ++ /* Round up the NSAA to the larger of 8 or the natural ++ alignment of the argument's type. */ ++ state->nsaa = ALIGN (state->nsaa, alignment); ++ state->nsaa = ALIGN (state->nsaa, alignment); ++ state->nsaa = ALIGN (state->nsaa, 8); ++ ++ allocation = stack + state->nsaa; ++ ++ state->nsaa += size; ++ return allocation; ++} ++ ++static void ++copy_basic_type (void *dest, void *source, unsigned short type) ++{ ++ /* This is neccessary to ensure that basic types are copied ++ sign extended to 64-bits as libffi expects. */ ++ switch (type) ++ { ++ case FFI_TYPE_FLOAT: ++ *(float *) dest = *(float *) source; ++ break; ++ case FFI_TYPE_DOUBLE: ++ *(double *) dest = *(double *) source; ++ break; ++ case FFI_TYPE_LONGDOUBLE: ++ *(long double *) dest = *(long double *) source; ++ break; ++ case FFI_TYPE_UINT8: ++ *(ffi_arg *) dest = *(UINT8 *) source; ++ break; ++ case FFI_TYPE_SINT8: ++ *(ffi_sarg *) dest = *(SINT8 *) source; ++ break; ++ case FFI_TYPE_UINT16: ++ *(ffi_arg *) dest = *(UINT16 *) source; ++ break; ++ case FFI_TYPE_SINT16: ++ *(ffi_sarg *) dest = *(SINT16 *) source; ++ break; ++ case FFI_TYPE_UINT32: ++ *(ffi_arg *) dest = *(UINT32 *) source; ++ break; ++ case FFI_TYPE_INT: ++ case FFI_TYPE_SINT32: ++ *(ffi_sarg *) dest = *(SINT32 *) source; ++ break; ++ case FFI_TYPE_POINTER: ++ case FFI_TYPE_UINT64: ++ *(ffi_arg *) dest = *(UINT64 *) source; ++ break; ++ case FFI_TYPE_SINT64: ++ *(ffi_sarg *) dest = *(SINT64 *) source; ++ break; ++ ++ default: ++ FFI_ASSERT (0); ++ } ++} ++ ++static void ++copy_hfa_to_reg_or_stack (void *memory, ++ ffi_type *ty, ++ struct call_context *context, ++ unsigned char *stack, ++ struct arg_state *state) ++{ ++ unsigned elems = element_count (ty); ++ if (available_v (state) < elems) ++ { ++ /* There are insufficient V registers. Further V register allocations ++ are prevented, the NSAA is adjusted (by allocate_to_stack ()) ++ and the argument is copied to memory at the adjusted NSAA. */ ++ state->nsrn = N_V_ARG_REG; ++ memcpy (allocate_to_stack (state, stack, ty->alignment, ty->size), ++ memory, ++ ty->size); ++ } ++ else ++ { ++ int i; ++ unsigned short type = get_homogeneous_type (ty); ++ unsigned elems = element_count (ty); ++ for (i = 0; i < elems; i++) ++ { ++ void *reg = allocate_to_v (context, state); ++ copy_basic_type (reg, memory, type); ++ memory += get_basic_type_size (type); ++ } ++ } ++} ++ ++/* Either allocate an appropriate register for the argument type, or if ++ none are available, allocate a stack slot and return a pointer ++ to the allocated space. */ ++ ++static void * ++allocate_to_register_or_stack (struct call_context *context, ++ unsigned char *stack, ++ struct arg_state *state, ++ unsigned short type) ++{ ++ size_t alignment = get_basic_type_alignment (type); ++ size_t size = alignment; ++ switch (type) ++ { ++ case FFI_TYPE_FLOAT: ++ /* This is the only case for which the allocated stack size ++ should not match the alignment of the type. */ ++ size = sizeof (UINT32); ++ /* Fall through. */ ++ case FFI_TYPE_DOUBLE: ++ if (state->nsrn < N_V_ARG_REG) ++ return allocate_to_d (context, state); ++ state->nsrn = N_V_ARG_REG; ++ break; ++ case FFI_TYPE_LONGDOUBLE: ++ if (state->nsrn < N_V_ARG_REG) ++ return allocate_to_v (context, state); ++ state->nsrn = N_V_ARG_REG; ++ break; ++ case FFI_TYPE_UINT8: ++ case FFI_TYPE_SINT8: ++ case FFI_TYPE_UINT16: ++ case FFI_TYPE_SINT16: ++ case FFI_TYPE_UINT32: ++ case FFI_TYPE_SINT32: ++ case FFI_TYPE_INT: ++ case FFI_TYPE_POINTER: ++ case FFI_TYPE_UINT64: ++ case FFI_TYPE_SINT64: ++ if (state->ngrn < N_X_ARG_REG) ++ return allocate_to_x (context, state); ++ state->ngrn = N_X_ARG_REG; ++ break; ++ default: ++ FFI_ASSERT (0); ++ } ++ ++ return allocate_to_stack (state, stack, alignment, size); ++} ++ ++/* Copy a value to an appropriate register, or if none are ++ available, to the stack. */ ++ ++static void ++copy_to_register_or_stack (struct call_context *context, ++ unsigned char *stack, ++ struct arg_state *state, ++ void *value, ++ unsigned short type) ++{ ++ copy_basic_type ( ++ allocate_to_register_or_stack (context, stack, state, type), ++ value, ++ type); ++} ++ ++/* Marshall the arguments from FFI representation to procedure call ++ context and stack. */ ++ ++static unsigned ++aarch64_prep_args (struct call_context *context, unsigned char *stack, ++ extended_cif *ecif) ++{ ++ int i; ++ struct arg_state state; ++ ++ arg_init (&state, ALIGN(ecif->cif->bytes, 16)); ++ ++ for (i = 0; i < ecif->cif->nargs; i++) ++ { ++ ffi_type *ty = ecif->cif->arg_types[i]; ++ switch (ty->type) ++ { ++ case FFI_TYPE_VOID: ++ FFI_ASSERT (0); ++ break; ++ ++ /* If the argument is a basic type the argument is allocated to an ++ appropriate register, or if none are available, to the stack. */ ++ case FFI_TYPE_FLOAT: ++ case FFI_TYPE_DOUBLE: ++ case FFI_TYPE_LONGDOUBLE: ++ case FFI_TYPE_UINT8: ++ case FFI_TYPE_SINT8: ++ case FFI_TYPE_UINT16: ++ case FFI_TYPE_SINT16: ++ case FFI_TYPE_UINT32: ++ case FFI_TYPE_INT: ++ case FFI_TYPE_SINT32: ++ case FFI_TYPE_POINTER: ++ case FFI_TYPE_UINT64: ++ case FFI_TYPE_SINT64: ++ copy_to_register_or_stack (context, stack, &state, ++ ecif->avalue[i], ty->type); ++ break; ++ ++ case FFI_TYPE_STRUCT: ++ if (is_hfa (ty)) ++ { ++ copy_hfa_to_reg_or_stack (ecif->avalue[i], ty, context, ++ stack, &state); ++ } ++ else if (ty->size > 16) ++ { ++ /* If the argument is a composite type that is larger than 16 ++ bytes, then the argument has been copied to memory, and ++ the argument is replaced by a pointer to the copy. */ ++ ++ copy_to_register_or_stack (context, stack, &state, ++ &(ecif->avalue[i]), FFI_TYPE_POINTER); ++ } ++ else if (available_x (&state) >= (ty->size + 7) / 8) ++ { ++ /* If the argument is a composite type and the size in ++ double-words is not more than the number of available ++ X registers, then the argument is copied into consecutive ++ X registers. */ ++ int j; ++ for (j = 0; j < (ty->size + 7) / 8; j++) ++ { ++ memcpy (allocate_to_x (context, &state), ++ &(((UINT64 *) ecif->avalue[i])[j]), ++ sizeof (UINT64)); ++ } ++ } ++ else ++ { ++ /* Otherwise, there are insufficient X registers. Further X ++ register allocations are prevented, the NSAA is adjusted ++ (by allocate_to_stack ()) and the argument is copied to ++ memory at the adjusted NSAA. */ ++ state.ngrn = N_X_ARG_REG; ++ ++ memcpy (allocate_to_stack (&state, stack, ty->alignment, ++ ty->size), ecif->avalue + i, ty->size); ++ } ++ break; ++ ++ default: ++ FFI_ASSERT (0); ++ break; ++ } ++ } ++ ++ return ecif->cif->aarch64_flags; ++} ++ ++ffi_status ++ffi_prep_cif_machdep (ffi_cif *cif) ++{ ++ /* Round the stack up to a multiple of the stack alignment requirement. */ ++ cif->bytes = ++ (cif->bytes + (AARCH64_STACK_ALIGN - 1)) & ~ (AARCH64_STACK_ALIGN - 1); ++ ++ /* Initialize our flags. We are interested if this CIF will touch a ++ vector register, if so we will enable context save and load to ++ those registers, otherwise not. This is intended to be friendly ++ to lazy float context switching in the kernel. */ ++ cif->aarch64_flags = 0; ++ ++ if (is_v_register_candidate (cif->rtype)) ++ { ++ cif->aarch64_flags |= AARCH64_FFI_WITH_V; ++ } ++ else ++ { ++ int i; ++ for (i = 0; i < cif->nargs; i++) ++ if (is_v_register_candidate (cif->arg_types[i])) ++ { ++ cif->aarch64_flags |= AARCH64_FFI_WITH_V; ++ break; ++ } ++ } ++ ++ return FFI_OK; ++} ++ ++/* Call a function with the provided arguments and capture the return ++ value. */ ++void ++ffi_call (ffi_cif *cif, void (*fn)(void), void *rvalue, void **avalue) ++{ ++ extended_cif ecif; ++ ++ ecif.cif = cif; ++ ecif.avalue = avalue; ++ ecif.rvalue = rvalue; ++ ++ switch (cif->abi) ++ { ++ case FFI_SYSV: ++ { ++ struct call_context context; ++ unsigned stack_bytes; ++ ++ /* Figure out the total amount of stack space we need, the ++ above call frame space needs to be 16 bytes aligned to ++ ensure correct alignment of the first object inserted in ++ that space hence the ALIGN applied to cif->bytes.*/ ++ stack_bytes = ALIGN(cif->bytes, 16); ++ ++ memset (&context, 0, sizeof (context)); ++ if (is_register_candidate (cif->rtype)) ++ { ++ ffi_call_SYSV (aarch64_prep_args, &context, &ecif, stack_bytes, fn); ++ switch (cif->rtype->type) ++ { ++ case FFI_TYPE_VOID: ++ case FFI_TYPE_FLOAT: ++ case FFI_TYPE_DOUBLE: ++ case FFI_TYPE_LONGDOUBLE: ++ case FFI_TYPE_UINT8: ++ case FFI_TYPE_SINT8: ++ case FFI_TYPE_UINT16: ++ case FFI_TYPE_SINT16: ++ case FFI_TYPE_UINT32: ++ case FFI_TYPE_SINT32: ++ case FFI_TYPE_POINTER: ++ case FFI_TYPE_UINT64: ++ case FFI_TYPE_INT: ++ case FFI_TYPE_SINT64: ++ { ++ void *addr = get_basic_type_addr (cif->rtype->type, ++ &context, 0); ++ copy_basic_type (rvalue, addr, cif->rtype->type); ++ break; ++ } ++ ++ case FFI_TYPE_STRUCT: ++ if (is_hfa (cif->rtype)) ++ { ++ int j; ++ unsigned short type = get_homogeneous_type (cif->rtype); ++ unsigned elems = element_count (cif->rtype); ++ for (j = 0; j < elems; j++) ++ { ++ void *reg = get_basic_type_addr (type, &context, j); ++ copy_basic_type (rvalue, reg, type); ++ rvalue += get_basic_type_size (type); ++ } ++ } ++ else if ((cif->rtype->size + 7) / 8 < N_X_ARG_REG) ++ { ++ unsigned size = ALIGN (cif->rtype->size, sizeof (UINT64)); ++ memcpy (rvalue, get_x_addr (&context, 0), size); ++ } ++ else ++ { ++ FFI_ASSERT (0); ++ } ++ break; ++ ++ default: ++ FFI_ASSERT (0); ++ break; ++ } ++ } ++ else ++ { ++ memcpy (get_x_addr (&context, 8), &rvalue, sizeof (UINT64)); ++ ffi_call_SYSV (aarch64_prep_args, &context, &ecif, ++ stack_bytes, fn); ++ } ++ break; ++ } ++ ++ default: ++ FFI_ASSERT (0); ++ break; ++ } ++} ++ ++static unsigned char trampoline [] = ++{ 0x70, 0x00, 0x00, 0x58, /* ldr x16, 1f */ ++ 0x91, 0x00, 0x00, 0x10, /* adr x17, 2f */ ++ 0x00, 0x02, 0x1f, 0xd6 /* br x16 */ ++}; ++ ++/* Build a trampoline. */ ++ ++#define FFI_INIT_TRAMPOLINE(TRAMP,FUN,CTX,FLAGS) \ ++ ({unsigned char *__tramp = (unsigned char*)(TRAMP); \ ++ UINT64 __fun = (UINT64)(FUN); \ ++ UINT64 __ctx = (UINT64)(CTX); \ ++ UINT64 __flags = (UINT64)(FLAGS); \ ++ memcpy (__tramp, trampoline, sizeof (trampoline)); \ ++ memcpy (__tramp + 12, &__fun, sizeof (__fun)); \ ++ memcpy (__tramp + 20, &__ctx, sizeof (__ctx)); \ ++ memcpy (__tramp + 28, &__flags, sizeof (__flags)); \ ++ __clear_cache(__tramp, __tramp + FFI_TRAMPOLINE_SIZE); \ ++ }) ++ ++ffi_status ++ffi_prep_closure_loc (ffi_closure* closure, ++ ffi_cif* cif, ++ void (*fun)(ffi_cif*,void*,void**,void*), ++ void *user_data, ++ void *codeloc) ++{ ++ if (cif->abi != FFI_SYSV) ++ return FFI_BAD_ABI; ++ ++ FFI_INIT_TRAMPOLINE (&closure->tramp[0], &ffi_closure_SYSV, codeloc, ++ cif->aarch64_flags); ++ ++ closure->cif = cif; ++ closure->user_data = user_data; ++ closure->fun = fun; ++ ++ return FFI_OK; ++} ++ ++/* Primary handler to setup and invoke a function within a closure. ++ ++ A closure when invoked enters via the assembler wrapper ++ ffi_closure_SYSV(). The wrapper allocates a call context on the ++ stack, saves the interesting registers (from the perspective of ++ the calling convention) into the context then passes control to ++ ffi_closure_SYSV_inner() passing the saved context and a pointer to ++ the stack at the point ffi_closure_SYSV() was invoked. ++ ++ On the return path the assembler wrapper will reload call context ++ regsiters. ++ ++ ffi_closure_SYSV_inner() marshalls the call context into ffi value ++ desriptors, invokes the wrapped function, then marshalls the return ++ value back into the call context. */ ++ ++void ++ffi_closure_SYSV_inner (ffi_closure *closure, struct call_context *context, ++ void *stack) ++{ ++ ffi_cif *cif = closure->cif; ++ void **avalue = (void**) alloca (cif->nargs * sizeof (void*)); ++ void *rvalue = NULL; ++ int i; ++ struct arg_state state; ++ ++ arg_init (&state, ALIGN(cif->bytes, 16)); ++ ++ for (i = 0; i < cif->nargs; i++) ++ { ++ ffi_type *ty = cif->arg_types[i]; ++ ++ switch (ty->type) ++ { ++ case FFI_TYPE_VOID: ++ FFI_ASSERT (0); ++ break; ++ ++ case FFI_TYPE_UINT8: ++ case FFI_TYPE_SINT8: ++ case FFI_TYPE_UINT16: ++ case FFI_TYPE_SINT16: ++ case FFI_TYPE_UINT32: ++ case FFI_TYPE_SINT32: ++ case FFI_TYPE_INT: ++ case FFI_TYPE_POINTER: ++ case FFI_TYPE_UINT64: ++ case FFI_TYPE_SINT64: ++ case FFI_TYPE_FLOAT: ++ case FFI_TYPE_DOUBLE: ++ case FFI_TYPE_LONGDOUBLE: ++ avalue[i] = allocate_to_register_or_stack (context, stack, ++ &state, ty->type); ++ break; ++ ++ case FFI_TYPE_STRUCT: ++ if (is_hfa (ty)) ++ { ++ unsigned n = element_count (ty); ++ if (available_v (&state) < n) ++ { ++ state.nsrn = N_V_ARG_REG; ++ avalue[i] = allocate_to_stack (&state, stack, ty->alignment, ++ ty->size); ++ } ++ else ++ { ++ switch (get_homogeneous_type (ty)) ++ { ++ case FFI_TYPE_FLOAT: ++ { ++ /* Eeek! We need a pointer to the structure, ++ however the homogeneous float elements are ++ being passed in individual S registers, ++ therefore the structure is not represented as ++ a contiguous sequence of bytes in our saved ++ register context. We need to fake up a copy ++ of the structure layed out in memory ++ correctly. The fake can be tossed once the ++ closure function has returned hence alloca() ++ is sufficient. */ ++ int j; ++ UINT32 *p = avalue[i] = alloca (ty->size); ++ for (j = 0; j < element_count (ty); j++) ++ memcpy (&p[j], ++ allocate_to_s (context, &state), ++ sizeof (*p)); ++ break; ++ } ++ ++ case FFI_TYPE_DOUBLE: ++ { ++ /* Eeek! We need a pointer to the structure, ++ however the homogeneous float elements are ++ being passed in individual S registers, ++ therefore the structure is not represented as ++ a contiguous sequence of bytes in our saved ++ register context. We need to fake up a copy ++ of the structure layed out in memory ++ correctly. The fake can be tossed once the ++ closure function has returned hence alloca() ++ is sufficient. */ ++ int j; ++ UINT64 *p = avalue[i] = alloca (ty->size); ++ for (j = 0; j < element_count (ty); j++) ++ memcpy (&p[j], ++ allocate_to_d (context, &state), ++ sizeof (*p)); ++ break; ++ } ++ ++ case FFI_TYPE_LONGDOUBLE: ++ memcpy (&avalue[i], ++ allocate_to_v (context, &state), ++ sizeof (*avalue)); ++ break; ++ ++ default: ++ FFI_ASSERT (0); ++ break; ++ } ++ } ++ } ++ else if (ty->size > 16) ++ { ++ /* Replace Composite type of size greater than 16 with a ++ pointer. */ ++ memcpy (&avalue[i], ++ allocate_to_register_or_stack (context, stack, ++ &state, FFI_TYPE_POINTER), ++ sizeof (avalue[i])); ++ } ++ else if (available_x (&state) >= (ty->size + 7) / 8) ++ { ++ avalue[i] = get_x_addr (context, state.ngrn); ++ state.ngrn += (ty->size + 7) / 8; ++ } ++ else ++ { ++ state.ngrn = N_X_ARG_REG; ++ ++ avalue[i] = allocate_to_stack (&state, stack, ty->alignment, ++ ty->size); ++ } ++ break; ++ ++ default: ++ FFI_ASSERT (0); ++ break; ++ } ++ } ++ ++ /* Figure out where the return value will be passed, either in ++ registers or in a memory block allocated by the caller and passed ++ in x8. */ ++ ++ if (is_register_candidate (cif->rtype)) ++ { ++ /* Register candidates are *always* returned in registers. */ ++ ++ /* Allocate a scratchpad for the return value, we will let the ++ callee scrible the result into the scratch pad then move the ++ contents into the appropriate return value location for the ++ call convention. */ ++ rvalue = alloca (cif->rtype->size); ++ (closure->fun) (cif, rvalue, avalue, closure->user_data); ++ ++ /* Copy the return value into the call context so that it is returned ++ as expected to our caller. */ ++ switch (cif->rtype->type) ++ { ++ case FFI_TYPE_VOID: ++ break; ++ ++ case FFI_TYPE_UINT8: ++ case FFI_TYPE_UINT16: ++ case FFI_TYPE_UINT32: ++ case FFI_TYPE_POINTER: ++ case FFI_TYPE_UINT64: ++ case FFI_TYPE_SINT8: ++ case FFI_TYPE_SINT16: ++ case FFI_TYPE_INT: ++ case FFI_TYPE_SINT32: ++ case FFI_TYPE_SINT64: ++ case FFI_TYPE_FLOAT: ++ case FFI_TYPE_DOUBLE: ++ case FFI_TYPE_LONGDOUBLE: ++ { ++ void *addr = get_basic_type_addr (cif->rtype->type, context, 0); ++ copy_basic_type (addr, rvalue, cif->rtype->type); ++ break; ++ } ++ case FFI_TYPE_STRUCT: ++ if (is_hfa (cif->rtype)) ++ { ++ int i; ++ unsigned short type = get_homogeneous_type (cif->rtype); ++ unsigned elems = element_count (cif->rtype); ++ for (i = 0; i < elems; i++) ++ { ++ void *reg = get_basic_type_addr (type, context, i); ++ copy_basic_type (reg, rvalue, type); ++ rvalue += get_basic_type_size (type); ++ } ++ } ++ else if ((cif->rtype->size + 7) / 8 < N_X_ARG_REG) ++ { ++ unsigned size = ALIGN (cif->rtype->size, sizeof (UINT64)) ; ++ memcpy (get_x_addr (context, 0), rvalue, size); ++ } ++ else ++ { ++ FFI_ASSERT (0); ++ } ++ break; ++ default: ++ FFI_ASSERT (0); ++ break; ++ } ++ } ++ else ++ { ++ memcpy (&rvalue, get_x_addr (context, 8), sizeof (UINT64)); ++ (closure->fun) (cif, rvalue, avalue, closure->user_data); ++ } ++} ++ +Index: b/src/libffi/src/aarch64/ffitarget.h +=================================================================== +--- /dev/null ++++ b/src/libffi/src/aarch64/ffitarget.h +@@ -0,0 +1,59 @@ ++/* Copyright (c) 2009, 2010, 2011, 2012 ARM Ltd. ++ ++Permission is hereby granted, free of charge, to any person obtaining ++a copy of this software and associated documentation files (the ++``Software''), to deal in the Software without restriction, including ++without limitation the rights to use, copy, modify, merge, publish, ++distribute, sublicense, and/or sell copies of the Software, and to ++permit persons to whom the Software is furnished to do so, subject to ++the following conditions: ++ ++The above copyright notice and this permission notice shall be ++included in all copies or substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED ``AS IS'', WITHOUT WARRANTY OF ANY KIND, ++EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ++IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY ++CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE ++SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ ++ ++#ifndef LIBFFI_TARGET_H ++#define LIBFFI_TARGET_H ++ ++#ifndef LIBFFI_H ++#error "Please do not include ffitarget.h directly into your source. Use ffi.h instead." ++#endif ++ ++#ifndef LIBFFI_ASM ++typedef unsigned long ffi_arg; ++typedef signed long ffi_sarg; ++ ++typedef enum ffi_abi ++ { ++ FFI_FIRST_ABI = 0, ++ FFI_SYSV, ++ FFI_LAST_ABI, ++ FFI_DEFAULT_ABI = FFI_SYSV ++ } ffi_abi; ++#endif ++ ++/* ---- Definitions for closures ----------------------------------------- */ ++ ++#define FFI_CLOSURES 1 ++#define FFI_TRAMPOLINE_SIZE 36 ++#define FFI_NATIVE_RAW_API 0 ++ ++/* ---- Internal ---- */ ++ ++ ++#define FFI_EXTRA_CIF_FIELDS unsigned aarch64_flags ++ ++#define AARCH64_FFI_WITH_V_BIT 0 ++ ++#define AARCH64_N_XREG 32 ++#define AARCH64_N_VREG 32 ++#define AARCH64_CALL_CONTEXT_SIZE (AARCH64_N_XREG * 8 + AARCH64_N_VREG * 16) ++ ++#endif +Index: b/src/libffi/src/aarch64/sysv.S +=================================================================== +--- /dev/null ++++ b/src/libffi/src/aarch64/sysv.S +@@ -0,0 +1,307 @@ ++/* Copyright (c) 2009, 2010, 2011, 2012 ARM Ltd. ++ ++Permission is hereby granted, free of charge, to any person obtaining ++a copy of this software and associated documentation files (the ++``Software''), to deal in the Software without restriction, including ++without limitation the rights to use, copy, modify, merge, publish, ++distribute, sublicense, and/or sell copies of the Software, and to ++permit persons to whom the Software is furnished to do so, subject to ++the following conditions: ++ ++The above copyright notice and this permission notice shall be ++included in all copies or substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED ``AS IS'', WITHOUT WARRANTY OF ANY KIND, ++EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ++IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY ++CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE ++SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ ++ ++#define LIBFFI_ASM ++#include ++#include ++ ++#define cfi_adjust_cfa_offset(off) .cfi_adjust_cfa_offset off ++#define cfi_rel_offset(reg, off) .cfi_rel_offset reg, off ++#define cfi_restore(reg) .cfi_restore reg ++#define cfi_def_cfa_register(reg) .cfi_def_cfa_register reg ++ ++ .text ++ .globl ffi_call_SYSV ++ .type ffi_call_SYSV, #function ++ ++/* ffi_call_SYSV() ++ ++ Create a stack frame, setup an argument context, call the callee ++ and extract the result. ++ ++ The maximum required argument stack size is provided, ++ ffi_call_SYSV() allocates that stack space then calls the ++ prepare_fn to populate register context and stack. The ++ argument passing registers are loaded from the register ++ context and the callee called, on return the register passing ++ register are saved back to the context. Our caller will ++ extract the return value from the final state of the saved ++ register context. ++ ++ Prototype: ++ ++ extern unsigned ++ ffi_call_SYSV (void (*)(struct call_context *context, unsigned char *, ++ extended_cif *), ++ struct call_context *context, ++ extended_cif *, ++ unsigned required_stack_size, ++ void (*fn)(void)); ++ ++ Therefore on entry we have: ++ ++ x0 prepare_fn ++ x1 &context ++ x2 &ecif ++ x3 bytes ++ x4 fn ++ ++ This function uses the following stack frame layout: ++ ++ == ++ saved x30(lr) ++ x29(fp)-> saved x29(fp) ++ saved x24 ++ saved x23 ++ saved x22 ++ sp' -> saved x21 ++ ... ++ sp -> (constructed callee stack arguments) ++ == ++ ++ Voila! */ ++ ++#define ffi_call_SYSV_FS (8 * 4) ++ ++ .cfi_startproc ++ffi_call_SYSV: ++ stp x29, x30, [sp, #-16]! ++ cfi_adjust_cfa_offset (16) ++ cfi_rel_offset (x29, 0) ++ cfi_rel_offset (x30, 8) ++ ++ mov x29, sp ++ cfi_def_cfa_register (x29) ++ sub sp, sp, #ffi_call_SYSV_FS ++ ++ stp x21, x22, [sp, 0] ++ cfi_rel_offset (x21, 0 - ffi_call_SYSV_FS) ++ cfi_rel_offset (x22, 8 - ffi_call_SYSV_FS) ++ ++ stp x23, x24, [sp, 16] ++ cfi_rel_offset (x23, 16 - ffi_call_SYSV_FS) ++ cfi_rel_offset (x24, 24 - ffi_call_SYSV_FS) ++ ++ mov x21, x1 ++ mov x22, x2 ++ mov x24, x4 ++ ++ /* Allocate the stack space for the actual arguments, many ++ arguments will be passed in registers, but we assume ++ worst case and allocate sufficient stack for ALL of ++ the arguments. */ ++ sub sp, sp, x3 ++ ++ /* unsigned (*prepare_fn) (struct call_context *context, ++ unsigned char *stack, extended_cif *ecif); ++ */ ++ mov x23, x0 ++ mov x0, x1 ++ mov x1, sp ++ /* x2 already in place */ ++ blr x23 ++ ++ /* Preserve the flags returned. */ ++ mov x23, x0 ++ ++ /* Figure out if we should touch the vector registers. */ ++ tbz x23, #AARCH64_FFI_WITH_V_BIT, 1f ++ ++ /* Load the vector argument passing registers. */ ++ ldp q0, q1, [x21, #8*32 + 0] ++ ldp q2, q3, [x21, #8*32 + 32] ++ ldp q4, q5, [x21, #8*32 + 64] ++ ldp q6, q7, [x21, #8*32 + 96] ++1: ++ /* Load the core argument passing registers. */ ++ ldp x0, x1, [x21, #0] ++ ldp x2, x3, [x21, #16] ++ ldp x4, x5, [x21, #32] ++ ldp x6, x7, [x21, #48] ++ ++ /* Don't forget x8 which may be holding the address of a return buffer. ++ */ ++ ldr x8, [x21, #8*8] ++ ++ blr x24 ++ ++ /* Save the core argument passing registers. */ ++ stp x0, x1, [x21, #0] ++ stp x2, x3, [x21, #16] ++ stp x4, x5, [x21, #32] ++ stp x6, x7, [x21, #48] ++ ++ /* Note nothing useful ever comes back in x8! */ ++ ++ /* Figure out if we should touch the vector registers. */ ++ tbz x23, #AARCH64_FFI_WITH_V_BIT, 1f ++ ++ /* Save the vector argument passing registers. */ ++ stp q0, q1, [x21, #8*32 + 0] ++ stp q2, q3, [x21, #8*32 + 32] ++ stp q4, q5, [x21, #8*32 + 64] ++ stp q6, q7, [x21, #8*32 + 96] ++1: ++ /* All done, unwind our stack frame. */ ++ ldp x21, x22, [x29, # - ffi_call_SYSV_FS] ++ cfi_restore (x21) ++ cfi_restore (x22) ++ ++ ldp x23, x24, [x29, # - ffi_call_SYSV_FS + 16] ++ cfi_restore (x23) ++ cfi_restore (x24) ++ ++ mov sp, x29 ++ cfi_def_cfa_register (sp) ++ ++ ldp x29, x30, [sp], #16 ++ cfi_adjust_cfa_offset (-16) ++ cfi_restore (x29) ++ cfi_restore (x30) ++ ++ ret ++ ++ .cfi_endproc ++ .size ffi_call_SYSV, .-ffi_call_SYSV ++ ++#define ffi_closure_SYSV_FS (8 * 2 + AARCH64_CALL_CONTEXT_SIZE) ++ ++/* ffi_closure_SYSV ++ ++ Closure invocation glue. This is the low level code invoked directly by ++ the closure trampoline to setup and call a closure. ++ ++ On entry x17 points to a struct trampoline_data, x16 has been clobbered ++ all other registers are preserved. ++ ++ We allocate a call context and save the argument passing registers, ++ then invoked the generic C ffi_closure_SYSV_inner() function to do all ++ the real work, on return we load the result passing registers back from ++ the call context. ++ ++ On entry ++ ++ extern void ++ ffi_closure_SYSV (struct trampoline_data *); ++ ++ struct trampoline_data ++ { ++ UINT64 *ffi_closure; ++ UINT64 flags; ++ }; ++ ++ This function uses the following stack frame layout: ++ ++ == ++ saved x30(lr) ++ x29(fp)-> saved x29(fp) ++ saved x22 ++ saved x21 ++ ... ++ sp -> call_context ++ == ++ ++ Voila! */ ++ ++ .text ++ .globl ffi_closure_SYSV ++ .cfi_startproc ++ffi_closure_SYSV: ++ stp x29, x30, [sp, #-16]! ++ cfi_adjust_cfa_offset (16) ++ cfi_rel_offset (x29, 0) ++ cfi_rel_offset (x30, 8) ++ ++ mov x29, sp ++ ++ sub sp, sp, #ffi_closure_SYSV_FS ++ cfi_adjust_cfa_offset (ffi_closure_SYSV_FS) ++ ++ stp x21, x22, [x29, #-16] ++ cfi_rel_offset (x21, 0) ++ cfi_rel_offset (x22, 8) ++ ++ /* Load x21 with &call_context. */ ++ mov x21, sp ++ /* Preserve our struct trampoline_data * */ ++ mov x22, x17 ++ ++ /* Save the rest of the argument passing registers. */ ++ stp x0, x1, [x21, #0] ++ stp x2, x3, [x21, #16] ++ stp x4, x5, [x21, #32] ++ stp x6, x7, [x21, #48] ++ /* Don't forget we may have been given a result scratch pad address. ++ */ ++ str x8, [x21, #64] ++ ++ /* Figure out if we should touch the vector registers. */ ++ ldr x0, [x22, #8] ++ tbz x0, #AARCH64_FFI_WITH_V_BIT, 1f ++ ++ /* Save the argument passing vector registers. */ ++ stp q0, q1, [x21, #8*32 + 0] ++ stp q2, q3, [x21, #8*32 + 32] ++ stp q4, q5, [x21, #8*32 + 64] ++ stp q6, q7, [x21, #8*32 + 96] ++1: ++ /* Load &ffi_closure.. */ ++ ldr x0, [x22, #0] ++ mov x1, x21 ++ /* Compute the location of the stack at the point that the ++ trampoline was called. */ ++ add x2, x29, #16 ++ ++ bl ffi_closure_SYSV_inner ++ ++ /* Figure out if we should touch the vector registers. */ ++ ldr x0, [x22, #8] ++ tbz x0, #AARCH64_FFI_WITH_V_BIT, 1f ++ ++ /* Load the result passing vector registers. */ ++ ldp q0, q1, [x21, #8*32 + 0] ++ ldp q2, q3, [x21, #8*32 + 32] ++ ldp q4, q5, [x21, #8*32 + 64] ++ ldp q6, q7, [x21, #8*32 + 96] ++1: ++ /* Load the result passing core registers. */ ++ ldp x0, x1, [x21, #0] ++ ldp x2, x3, [x21, #16] ++ ldp x4, x5, [x21, #32] ++ ldp x6, x7, [x21, #48] ++ /* Note nothing usefull is returned in x8. */ ++ ++ /* We are done, unwind our frame. */ ++ ldp x21, x22, [x29, #-16] ++ cfi_restore (x21) ++ cfi_restore (x22) ++ ++ mov sp, x29 ++ cfi_adjust_cfa_offset (-ffi_closure_SYSV_FS) ++ ++ ldp x29, x30, [sp], #16 ++ cfi_adjust_cfa_offset (-16) ++ cfi_restore (x29) ++ cfi_restore (x30) ++ ++ ret ++ .cfi_endproc ++ .size ffi_closure_SYSV, .-ffi_closure_SYSV +Index: b/src/libffi/Makefile.am +=================================================================== +--- a/src/libffi/Makefile.am ++++ b/src/libffi/Makefile.am +@@ -6,6 +6,7 @@ + SUBDIRS = include testsuite man + + EXTRA_DIST = LICENSE ChangeLog.v1 ChangeLog.libgcj configure.host \ ++ src/aarch64/ffi.c src/aarch64/ffitarget.h \ + src/alpha/ffi.c src/alpha/osf.S src/alpha/ffitarget.h \ + src/arm/ffi.c src/arm/sysv.S src/arm/ffitarget.h \ + src/avr32/ffi.c src/avr32/sysv.S src/avr32/ffitarget.h \ +@@ -134,6 +135,9 @@ + if POWERPC_FREEBSD + nodist_libffi_la_SOURCES += src/powerpc/ffi.c src/powerpc/sysv.S src/powerpc/ppc_closure.S + endif ++if AARCH64 ++nodist_libffi_la_SOURCES += src/aarch64/sysv.S src/aarch64/ffi.c ++endif + if ARM + nodist_libffi_la_SOURCES += src/arm/sysv.S src/arm/ffi.c + endif +Index: b/src/libffi/configure.ac +=================================================================== +--- a/src/libffi/configure.ac ++++ b/src/libffi/configure.ac +@@ -41,6 +41,10 @@ + + TARGETDIR="unknown" + case "$host" in ++ aarch64*-*-*) ++ TARGET=AARCH64; TARGETDIR=aarch64 ++ ;; ++ + alpha*-*-*) + TARGET=ALPHA; TARGETDIR=alpha; + # Support 128-bit long double, changeable via command-line switch. +@@ -204,6 +208,7 @@ + AM_CONDITIONAL(POWERPC_AIX, test x$TARGET = xPOWERPC_AIX) + AM_CONDITIONAL(POWERPC_DARWIN, test x$TARGET = xPOWERPC_DARWIN) + AM_CONDITIONAL(POWERPC_FREEBSD, test x$TARGET = xPOWERPC_FREEBSD) ++AM_CONDITIONAL(AARCH64, test x$TARGET = xAARCH64) + AM_CONDITIONAL(ARM, test x$TARGET = xARM) + AM_CONDITIONAL(AVR32, test x$TARGET = xAVR32) + AM_CONDITIONAL(LIBFFI_CRIS, test x$TARGET = xLIBFFI_CRIS) +Index: b/src/libffi/Makefile.in +=================================================================== +--- a/src/libffi/Makefile.in ++++ b/src/libffi/Makefile.in +@@ -50,16 +50,17 @@ + @POWERPC_AIX_TRUE@am__append_13 = src/powerpc/ffi_darwin.c src/powerpc/aix.S src/powerpc/aix_closure.S + @POWERPC_DARWIN_TRUE@am__append_14 = src/powerpc/ffi_darwin.c src/powerpc/darwin.S src/powerpc/darwin_closure.S + @POWERPC_FREEBSD_TRUE@am__append_15 = src/powerpc/ffi.c src/powerpc/sysv.S src/powerpc/ppc_closure.S +-@ARM_TRUE@am__append_16 = src/arm/sysv.S src/arm/ffi.c +-@AVR32_TRUE@am__append_17 = src/avr32/sysv.S src/avr32/ffi.c +-@LIBFFI_CRIS_TRUE@am__append_18 = src/cris/sysv.S src/cris/ffi.c +-@FRV_TRUE@am__append_19 = src/frv/eabi.S src/frv/ffi.c +-@S390_TRUE@am__append_20 = src/s390/sysv.S src/s390/ffi.c +-@X86_64_TRUE@am__append_21 = src/x86/ffi64.c src/x86/unix64.S src/x86/ffi.c src/x86/sysv.S +-@SH_TRUE@am__append_22 = src/sh/sysv.S src/sh/ffi.c +-@SH64_TRUE@am__append_23 = src/sh64/sysv.S src/sh64/ffi.c +-@PA_LINUX_TRUE@am__append_24 = src/pa/linux.S src/pa/ffi.c +-@PA_HPUX_TRUE@am__append_25 = src/pa/hpux32.S src/pa/ffi.c ++@AARCH64_TRUE@am__append_16 = src/aarch64/sysv.S src/aarch64/ffi.c ++@ARM_TRUE@am__append_17 = src/arm/sysv.S src/arm/ffi.c ++@AVR32_TRUE@am__append_18 = src/avr32/sysv.S src/avr32/ffi.c ++@LIBFFI_CRIS_TRUE@am__append_19 = src/cris/sysv.S src/cris/ffi.c ++@FRV_TRUE@am__append_20 = src/frv/eabi.S src/frv/ffi.c ++@S390_TRUE@am__append_21 = src/s390/sysv.S src/s390/ffi.c ++@X86_64_TRUE@am__append_22 = src/x86/ffi64.c src/x86/unix64.S src/x86/ffi.c src/x86/sysv.S ++@SH_TRUE@am__append_23 = src/sh/sysv.S src/sh/ffi.c ++@SH64_TRUE@am__append_24 = src/sh64/sysv.S src/sh64/ffi.c ++@PA_LINUX_TRUE@am__append_25 = src/pa/linux.S src/pa/ffi.c ++@PA_HPUX_TRUE@am__append_26 = src/pa/hpux32.S src/pa/ffi.c + subdir = . + DIST_COMMON = README ChangeLog $(srcdir)/Makefile.in \ + $(srcdir)/Makefile.am $(top_srcdir)/configure \ +@@ -137,17 +138,18 @@ + @POWERPC_FREEBSD_TRUE@am__objects_15 = src/powerpc/ffi.lo \ + @POWERPC_FREEBSD_TRUE@ src/powerpc/sysv.lo \ + @POWERPC_FREEBSD_TRUE@ src/powerpc/ppc_closure.lo +-@ARM_TRUE@am__objects_16 = src/arm/sysv.lo src/arm/ffi.lo +-@AVR32_TRUE@am__objects_17 = src/avr32/sysv.lo src/avr32/ffi.lo +-@LIBFFI_CRIS_TRUE@am__objects_18 = src/cris/sysv.lo src/cris/ffi.lo +-@FRV_TRUE@am__objects_19 = src/frv/eabi.lo src/frv/ffi.lo +-@S390_TRUE@am__objects_20 = src/s390/sysv.lo src/s390/ffi.lo +-@X86_64_TRUE@am__objects_21 = src/x86/ffi64.lo src/x86/unix64.lo \ ++@AARCH64_TRUE@am__objects_16 = src/aarch64/sysv.lo src/aarch64/ffi.lo ++@ARM_TRUE@am__objects_17 = src/arm/sysv.lo src/arm/ffi.lo ++@AVR32_TRUE@am__objects_18 = src/avr32/sysv.lo src/avr32/ffi.lo ++@LIBFFI_CRIS_TRUE@am__objects_19 = src/cris/sysv.lo src/cris/ffi.lo ++@FRV_TRUE@am__objects_20 = src/frv/eabi.lo src/frv/ffi.lo ++@S390_TRUE@am__objects_21 = src/s390/sysv.lo src/s390/ffi.lo ++@X86_64_TRUE@am__objects_22 = src/x86/ffi64.lo src/x86/unix64.lo \ + @X86_64_TRUE@ src/x86/ffi.lo src/x86/sysv.lo +-@SH_TRUE@am__objects_22 = src/sh/sysv.lo src/sh/ffi.lo +-@SH64_TRUE@am__objects_23 = src/sh64/sysv.lo src/sh64/ffi.lo +-@PA_LINUX_TRUE@am__objects_24 = src/pa/linux.lo src/pa/ffi.lo +-@PA_HPUX_TRUE@am__objects_25 = src/pa/hpux32.lo src/pa/ffi.lo ++@SH_TRUE@am__objects_23 = src/sh/sysv.lo src/sh/ffi.lo ++@SH64_TRUE@am__objects_24 = src/sh64/sysv.lo src/sh64/ffi.lo ++@PA_LINUX_TRUE@am__objects_25 = src/pa/linux.lo src/pa/ffi.lo ++@PA_HPUX_TRUE@am__objects_26 = src/pa/hpux32.lo src/pa/ffi.lo + nodist_libffi_la_OBJECTS = $(am__objects_1) $(am__objects_2) \ + $(am__objects_3) $(am__objects_4) $(am__objects_5) \ + $(am__objects_6) $(am__objects_7) $(am__objects_8) \ +@@ -156,17 +158,17 @@ + $(am__objects_15) $(am__objects_16) $(am__objects_17) \ + $(am__objects_18) $(am__objects_19) $(am__objects_20) \ + $(am__objects_21) $(am__objects_22) $(am__objects_23) \ +- $(am__objects_24) $(am__objects_25) ++ $(am__objects_24) $(am__objects_25) $(am__objects_26) + libffi_la_OBJECTS = $(am_libffi_la_OBJECTS) \ + $(nodist_libffi_la_OBJECTS) + libffi_la_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ + $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ + $(libffi_la_LDFLAGS) $(LDFLAGS) -o $@ + libffi_convenience_la_LIBADD = +-am__objects_26 = src/debug.lo src/prep_cif.lo src/types.lo \ ++am__objects_27 = src/debug.lo src/prep_cif.lo src/types.lo \ + src/raw_api.lo src/java_raw_api.lo src/closures.lo +-am_libffi_convenience_la_OBJECTS = $(am__objects_26) +-am__objects_27 = $(am__objects_1) $(am__objects_2) $(am__objects_3) \ ++am_libffi_convenience_la_OBJECTS = $(am__objects_27) ++am__objects_28 = $(am__objects_1) $(am__objects_2) $(am__objects_3) \ + $(am__objects_4) $(am__objects_5) $(am__objects_6) \ + $(am__objects_7) $(am__objects_8) $(am__objects_9) \ + $(am__objects_10) $(am__objects_11) $(am__objects_12) \ +@@ -174,8 +176,8 @@ + $(am__objects_16) $(am__objects_17) $(am__objects_18) \ + $(am__objects_19) $(am__objects_20) $(am__objects_21) \ + $(am__objects_22) $(am__objects_23) $(am__objects_24) \ +- $(am__objects_25) +-nodist_libffi_convenience_la_OBJECTS = $(am__objects_27) ++ $(am__objects_25) $(am__objects_26) ++nodist_libffi_convenience_la_OBJECTS = $(am__objects_28) + libffi_convenience_la_OBJECTS = $(am_libffi_convenience_la_OBJECTS) \ + $(nodist_libffi_convenience_la_OBJECTS) + DEFAULT_INCLUDES = -I.@am__isrc@ +@@ -350,6 +352,7 @@ + ACLOCAL_AMFLAGS = -I .. -I ../config + SUBDIRS = include testsuite man + EXTRA_DIST = LICENSE ChangeLog.v1 ChangeLog.libgcj configure.host \ ++ src/aarch64/ffi.c src/aarch64/ffitarget.h \ + src/alpha/ffi.c src/alpha/osf.S src/alpha/ffitarget.h \ + src/arm/ffi.c src/arm/sysv.S src/arm/ffitarget.h \ + src/avr32/ffi.c src/avr32/sysv.S src/avr32/ffitarget.h \ +@@ -432,7 +435,7 @@ + $(am__append_15) $(am__append_16) $(am__append_17) \ + $(am__append_18) $(am__append_19) $(am__append_20) \ + $(am__append_21) $(am__append_22) $(am__append_23) \ +- $(am__append_24) $(am__append_25) ++ $(am__append_24) $(am__append_25) $(am__append_26) + libffi_convenience_la_SOURCES = $(libffi_la_SOURCES) + nodist_libffi_convenience_la_SOURCES = $(nodist_libffi_la_SOURCES) + AM_CFLAGS = -Wall -g -fexceptions +@@ -660,6 +663,16 @@ + src/powerpc/$(DEPDIR)/$(am__dirstamp) + src/powerpc/darwin_closure.lo: src/powerpc/$(am__dirstamp) \ + src/powerpc/$(DEPDIR)/$(am__dirstamp) ++src/aarch64/$(am__dirstamp): ++ @$(MKDIR_P) src/aarch64 ++ @: > src/aarch64/$(am__dirstamp) ++src/aarch64/$(DEPDIR)/$(am__dirstamp): ++ @$(MKDIR_P) src/aarch64/$(DEPDIR) ++ @: > src/aarch64/$(DEPDIR)/$(am__dirstamp) ++src/aarch64/sysv.lo: src/aarch64/$(am__dirstamp) \ ++ src/aarch64/$(DEPDIR)/$(am__dirstamp) ++src/aarch64/ffi.lo: src/aarch64/$(am__dirstamp) \ ++ src/aarch64/$(DEPDIR)/$(am__dirstamp) + src/arm/$(am__dirstamp): + @$(MKDIR_P) src/arm + @: > src/arm/$(am__dirstamp) +@@ -749,6 +762,10 @@ + + mostlyclean-compile: + -rm -f *.$(OBJEXT) ++ -rm -f src/aarch64/ffi.$(OBJEXT) ++ -rm -f src/aarch64/ffi.lo ++ -rm -f src/aarch64/sysv.$(OBJEXT) ++ -rm -f src/aarch64/sysv.lo + -rm -f src/alpha/ffi.$(OBJEXT) + -rm -f src/alpha/ffi.lo + -rm -f src/alpha/osf.$(OBJEXT) +@@ -871,6 +888,8 @@ + @AMDEP_TRUE@@am__include@ @am__quote@src/$(DEPDIR)/prep_cif.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@src/$(DEPDIR)/raw_api.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@src/$(DEPDIR)/types.Plo@am__quote@ ++@AMDEP_TRUE@@am__include@ @am__quote@src/aarch64/$(DEPDIR)/ffi.Plo@am__quote@ ++@AMDEP_TRUE@@am__include@ @am__quote@src/aarch64/$(DEPDIR)/sysv.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@src/alpha/$(DEPDIR)/ffi.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@src/alpha/$(DEPDIR)/osf.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@src/arm/$(DEPDIR)/ffi.Plo@am__quote@ +@@ -976,6 +995,7 @@ + clean-libtool: + -rm -rf .libs _libs + -rm -rf src/.libs src/_libs ++ -rm -rf src/aarch64/.libs src/aarch64/_libs + -rm -rf src/alpha/.libs src/alpha/_libs + -rm -rf src/arm/.libs src/arm/_libs + -rm -rf src/avr32/.libs src/avr32/_libs +@@ -1178,6 +1198,8 @@ + -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES) + -rm -f src/$(DEPDIR)/$(am__dirstamp) + -rm -f src/$(am__dirstamp) ++ -rm -f src/aarch64/$(DEPDIR)/$(am__dirstamp) ++ -rm -f src/aarch64/$(am__dirstamp) + -rm -f src/alpha/$(DEPDIR)/$(am__dirstamp) + -rm -f src/alpha/$(am__dirstamp) + -rm -f src/arm/$(DEPDIR)/$(am__dirstamp) +@@ -1221,7 +1243,7 @@ + + distclean: distclean-multi distclean-recursive + -rm -f $(am__CONFIG_DISTCLEAN_FILES) +- -rm -rf src/$(DEPDIR) src/alpha/$(DEPDIR) src/arm/$(DEPDIR) src/avr32/$(DEPDIR) src/cris/$(DEPDIR) src/frv/$(DEPDIR) src/ia64/$(DEPDIR) src/m32r/$(DEPDIR) src/m68k/$(DEPDIR) src/mips/$(DEPDIR) src/pa/$(DEPDIR) src/powerpc/$(DEPDIR) src/s390/$(DEPDIR) src/sh/$(DEPDIR) src/sh64/$(DEPDIR) src/sparc/$(DEPDIR) src/x86/$(DEPDIR) ++ -rm -rf src/$(DEPDIR) src/aarch64/$(DEPDIR) src/alpha/$(DEPDIR) src/arm/$(DEPDIR) src/avr32/$(DEPDIR) src/cris/$(DEPDIR) src/frv/$(DEPDIR) src/ia64/$(DEPDIR) src/m32r/$(DEPDIR) src/m68k/$(DEPDIR) src/mips/$(DEPDIR) src/pa/$(DEPDIR) src/powerpc/$(DEPDIR) src/s390/$(DEPDIR) src/sh/$(DEPDIR) src/sh64/$(DEPDIR) src/sparc/$(DEPDIR) src/x86/$(DEPDIR) + -rm -f Makefile + distclean-am: clean-am distclean-compile distclean-generic \ + distclean-hdr distclean-libtool distclean-tags +@@ -1269,7 +1291,7 @@ + maintainer-clean: maintainer-clean-multi maintainer-clean-recursive + -rm -f $(am__CONFIG_DISTCLEAN_FILES) + -rm -rf $(top_srcdir)/autom4te.cache +- -rm -rf src/$(DEPDIR) src/alpha/$(DEPDIR) src/arm/$(DEPDIR) src/avr32/$(DEPDIR) src/cris/$(DEPDIR) src/frv/$(DEPDIR) src/ia64/$(DEPDIR) src/m32r/$(DEPDIR) src/m68k/$(DEPDIR) src/mips/$(DEPDIR) src/pa/$(DEPDIR) src/powerpc/$(DEPDIR) src/s390/$(DEPDIR) src/sh/$(DEPDIR) src/sh64/$(DEPDIR) src/sparc/$(DEPDIR) src/x86/$(DEPDIR) ++ -rm -rf src/$(DEPDIR) src/aarch64/$(DEPDIR) src/alpha/$(DEPDIR) src/arm/$(DEPDIR) src/avr32/$(DEPDIR) src/cris/$(DEPDIR) src/frv/$(DEPDIR) src/ia64/$(DEPDIR) src/m32r/$(DEPDIR) src/m68k/$(DEPDIR) src/mips/$(DEPDIR) src/pa/$(DEPDIR) src/powerpc/$(DEPDIR) src/s390/$(DEPDIR) src/sh/$(DEPDIR) src/sh64/$(DEPDIR) src/sparc/$(DEPDIR) src/x86/$(DEPDIR) + -rm -f Makefile + maintainer-clean-am: distclean-am maintainer-clean-generic + diff -Nru gcc-4.7-4.7.2/debian/patches/aarch64-multiarch.diff gcc-4.7-4.7.3/debian/patches/aarch64-multiarch.diff --- gcc-4.7-4.7.2/debian/patches/aarch64-multiarch.diff 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/aarch64-multiarch.diff 2013-07-25 18:49:34.000000000 +0000 @@ -0,0 +1,27 @@ +# DP: Define MULTIARCH_TUPLE for arm64. + +--- a/src/gcc/config/aarch64/aarch64-linux.h ++++ b/src/gcc/config/aarch64/aarch64-linux.h +@@ -21,6 +21,14 @@ + #ifndef GCC_AARCH64_LINUX_H + #define GCC_AARCH64_LINUX_H + ++#define MULTIARCH_TUPLE "aarch64-linux-gnu" ++ ++#undef STANDARD_STARTFILE_PREFIX_1 ++#define STANDARD_STARTFILE_PREFIX_1 "/lib/" MULTIARCH_TUPLE "/" ++ ++#undef STANDARD_STARTFILE_PREFIX_2 ++#define STANDARD_STARTFILE_PREFIX_2 "/usr/lib/" MULTIARCH_TUPLE "/" ++ + #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64.so.1" + + #define LINUX_TARGET_LINK_SPEC "%{h*} \ +--- a/src/gcc/config/aarch64/t-aarch64-linux ++++ b/src/gcc/config/aarch64/t-aarch64-linux +@@ -20,3 +20,5 @@ + + LIB1ASMSRC = aarch64/lib1funcs.asm + LIB1ASMFUNCS = _aarch64_sync_cache_range ++ ++MULTIARCH_DIRNAME = $(call if_multiarch,aarch64-linux-gnu) diff -Nru gcc-4.7-4.7.2/debian/patches/ada-link-shlib.diff gcc-4.7-4.7.3/debian/patches/ada-link-shlib.diff --- gcc-4.7-4.7.2/debian/patches/ada-link-shlib.diff 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/ada-link-shlib.diff 2013-07-25 18:49:34.000000000 +0000 @@ -0,0 +1,85 @@ +# DP: In gnatlink, pass the options and libraries after objects to the +# DP: linker to avoid link failures with --as-needed. Closes: #680292. + +--- a/src/gcc/ada/mlib-tgt-specific-linux.adb ++++ b/src/gcc/ada/mlib-tgt-specific-linux.adb +@@ -81,19 +81,54 @@ + Version_Arg : String_Access; + Symbolic_Link_Needed : Boolean := False; + ++ N_Options : Argument_List := Options; ++ Options_Last : Natural := N_Options'Last; ++ -- After moving -lxxx to Options_2, N_Options up to index Options_Last ++ -- will contain the Options to pass to MLib.Utl.Gcc. ++ ++ Real_Options_2 : Argument_List (1 .. Options'Length); ++ Real_Options_2_Last : Natural := 0; ++ -- Real_Options_2 up to index Real_Options_2_Last will contain the ++ -- Options_2 to pass to MLib.Utl.Gcc. ++ + begin + if Opt.Verbose_Mode then + Write_Str ("building relocatable shared library "); + Write_Line (Lib_Path); + end if; + ++ -- Move all -lxxx to Options_2 ++ ++ declare ++ Index : Natural := N_Options'First; ++ Arg : String_Access; ++ ++ begin ++ while Index <= Options_Last loop ++ Arg := N_Options (Index); ++ ++ if Arg'Length > 2 ++ and then Arg (Arg'First .. Arg'First + 1) = "-l" ++ then ++ Real_Options_2_Last := Real_Options_2_Last + 1; ++ Real_Options_2 (Real_Options_2_Last) := Arg; ++ N_Options (Index .. Options_Last - 1) := ++ N_Options (Index + 1 .. Options_Last); ++ Options_Last := Options_Last - 1; ++ ++ else ++ Index := Index + 1; ++ end if; ++ end loop; ++ end; ++ + if Lib_Version = "" then + Utl.Gcc + (Output_File => Lib_Path, + Objects => Ofiles, +- Options => Options, ++ Options => N_Options (N_Options'First .. Options_Last), + Driver_Name => Driver_Name, +- Options_2 => No_Argument_List); ++ Options_2 => Real_Options_2 (1 .. Real_Options_2_Last)); + + else + declare +@@ -111,18 +146,18 @@ + Utl.Gcc + (Output_File => Lib_Version, + Objects => Ofiles, +- Options => Options & Version_Arg, ++ Options => N_Options (N_Options'First .. Options_Last) & Version_Arg, + Driver_Name => Driver_Name, +- Options_2 => No_Argument_List); ++ Options_2 => Real_Options_2 (1 .. Real_Options_2_Last)); + Symbolic_Link_Needed := Lib_Version /= Lib_Path; + + else + Utl.Gcc + (Output_File => Lib_Dir & Directory_Separator & Lib_Version, + Objects => Ofiles, +- Options => Options & Version_Arg, ++ Options => N_Options (N_Options'First .. Options_Last) & Version_Arg, + Driver_Name => Driver_Name, +- Options_2 => No_Argument_List); ++ Options_2 => Real_Options_2 (1 .. Real_Options_2_Last)); + Symbolic_Link_Needed := + Lib_Dir & Directory_Separator & Lib_Version /= Lib_Path; + end if; diff -Nru gcc-4.7-4.7.2/debian/patches/ada-mips.diff gcc-4.7-4.7.3/debian/patches/ada-mips.diff --- gcc-4.7-4.7.2/debian/patches/ada-mips.diff 2013-07-25 18:49:32.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/ada-mips.diff 2013-07-25 18:49:34.000000000 +0000 @@ -1,8 +1,10 @@ # DP: Improve support for mips. +Index: b/src/gcc/ada/gcc-interface/Makefile.in +=================================================================== --- a/src/gcc/ada/gcc-interface/Makefile.in +++ b/src/gcc/ada/gcc-interface/Makefile.in -@@ -1666,7 +1666,7 @@ +@@ -1708,10 +1708,15 @@ s-taprop.adb&2 exit 1 -@@ -3094,6 +3102,9 @@ +@@ -3176,6 +3184,9 @@ "" \ | arm | thumb ) #OK @@ -37,8 +37,8 @@ echo "Unknown mode used in --with-mode=$with_mode" Index: b/src/gcc/config/arm/linux-eabi.h =================================================================== ---- a/src/gcc/config/arm/linux-eabi.h 2012-05-02 10:24:10.585842104 +0000 -+++ b/src/gcc/config/arm/linux-eabi.h 2012-05-02 10:26:55.141848227 +0000 +--- a/src/gcc/config/arm/linux-eabi.h ++++ b/src/gcc/config/arm/linux-eabi.h @@ -34,7 +34,21 @@ /* We default to a soft-float ABI so that binaries can run on all target hardware. */ diff -Nru gcc-4.7-4.7.2/debian/patches/arm-multilib-soft.diff gcc-4.7-4.7.3/debian/patches/arm-multilib-soft.diff --- gcc-4.7-4.7.2/debian/patches/arm-multilib-soft.diff 2013-07-25 18:49:32.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/arm-multilib-soft.diff 2013-07-25 18:49:34.000000000 +0000 @@ -2,9 +2,9 @@ Index: b/src/gcc/config/arm/t-linux-eabi =================================================================== ---- a/src/gcc/config/arm/t-linux-eabi 2011-01-03 20:52:22.000000000 +0000 -+++ b/src/gcc/config/arm/t-linux-eabi 2011-08-21 21:08:47.583351817 +0000 -@@ -24,6 +24,20 @@ +--- a/src/gcc/config/arm/t-linux-eabi ++++ b/src/gcc/config/arm/t-linux-eabi +@@ -21,6 +21,20 @@ MULTILIB_OPTIONS = MULTILIB_DIRNAMES = diff -Nru gcc-4.7-4.7.2/debian/patches/arm-no-va_list-warn.diff gcc-4.7-4.7.3/debian/patches/arm-no-va_list-warn.diff --- gcc-4.7-4.7.2/debian/patches/arm-no-va_list-warn.diff 2013-07-25 18:49:32.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/arm-no-va_list-warn.diff 2013-07-25 18:49:34.000000000 +0000 @@ -7,11 +7,11 @@ * config/arm/arm.c (arm_mangle_type): Don't warn anymore that 4.4 has changed the `va_list' mangling. -Index: gcc/config/arm/arm.c +Index: b/src/gcc/config/arm/arm.c =================================================================== ---- a/src/gcc/config/arm/arm.c (revision 191609) -+++ b/src/gcc/config/arm/arm.c (revision 191610) -@@ -25072,16 +25072,7 @@ +--- a/src/gcc/config/arm/arm.c ++++ b/src/gcc/config/arm/arm.c +@@ -24495,16 +24495,7 @@ has to be managled as if it is in the "std" namespace. */ if (TARGET_AAPCS_BASED && lang_hooks.types_compatible_p (CONST_CAST_TREE (type), va_list_type)) diff -Nru gcc-4.7-4.7.2/debian/patches/armhf-triplet-trunk.diff gcc-4.7-4.7.3/debian/patches/armhf-triplet-trunk.diff --- gcc-4.7-4.7.2/debian/patches/armhf-triplet-trunk.diff 2013-07-25 18:49:32.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/armhf-triplet-trunk.diff 1970-01-01 00:00:00.000000000 +0000 @@ -1,84 +0,0 @@ -# DP: add support for arm-linux-*eabi* triplets; useful for armhf - ---- a/src/libjava/configure.ac.orig -+++ b/src/libjava/configure.ac -@@ -924,7 +924,7 @@ - # on Darwin -single_module speeds up loading of the dynamic libraries. - extra_ldflags_libjava=-Wl,-single_module - ;; --arm*linux*eabi) -+arm*-*-linux-*eabi*) - # Some of the ARM unwinder code is actually in libstdc++. We - # could in principle replicate it in libgcj, but it's better to - # have a dependency on libstdc++. ---- a/src/gcc/testsuite/lib/target-supports.exp.orig -+++ b/src/gcc/testsuite/lib/target-supports.exp -@@ -3235,7 +3235,7 @@ - || [istarget i?86-*-*] - || [istarget x86_64-*-*] - || [istarget alpha*-*-*] -- || [istarget arm*-*-linux-gnueabi] -+ || [istarget arm*-*-linux-*eabi*] - || [istarget bfin*-*linux*] - || [istarget hppa*-*linux*] - || [istarget s390*-*-*] -@@ -3266,7 +3266,7 @@ - || [istarget i?86-*-*] - || [istarget x86_64-*-*] - || [istarget alpha*-*-*] -- || [istarget arm*-*-linux-gnueabi] -+ || [istarget arm*-*-linux-*eabi*] - || [istarget hppa*-*linux*] - || [istarget s390*-*-*] - || [istarget powerpc*-*-*] ---- a/src/gcc/ada/gcc-interface/Makefile.in.orig -+++ b/src/gcc/ada/gcc-interface/Makefile.in -@@ -1846,7 +1846,7 @@ - LIBRARY_VERSION := $(LIB_VERSION) - endif - --ifeq ($(strip $(filter-out arm% linux-gnueabi,$(arch) $(osys)-$(word 4,$(targ)))),) -+ifeq ($(strip $(filter-out arm%-linux,$(arch)-$(osys)) $(if $(findstring eabi,$(word 4,$(targ))),,$(word 4,$(targ)))),) - LIBGNAT_TARGET_PAIRS = \ - a-intnam.ads - // ---- a/src/libstdc++-v3/testsuite/20_util/make_signed/requirements/typedefs-2.cc.orig -+++ b/src/libstdc++-v3/testsuite/20_util/make_signed/requirements/typedefs-2.cc -@@ -1,5 +1,5 @@ - // { dg-options "-std=gnu++0x -funsigned-char -fshort-enums" } --// { dg-options "-std=gnu++0x -funsigned-char -fshort-enums -Wl,--no-enum-size-warning" { target arm*-*-linux*eabi } } -+// { dg-options "-std=gnu++0x -funsigned-char -fshort-enums -Wl,--no-enum-size-warning" { target arm*-*-linux-*eabi* } } - - // 2007-05-03 Benjamin Kosnik - // ---- a/src/libgcc/config.host -+++ b/src/libgcc/config.host -@@ -334,7 +334,7 @@ - arm*-*-linux*) # ARM GNU/Linux with ELF - tmake_file="${tmake_file} arm/t-arm t-fixedpoint-gnu-prefix" - case ${host} in -- arm*-*-linux-*eabi) -+ arm*-*-linux-*eabi*) - tmake_file="${tmake_file} arm/t-elf arm/t-bpabi arm/t-linux-eabi t-slibgcc-libgcc" - tm_file="$tm_file arm/bpabi-lib.h" - unwind_header=config/arm/unwind-arm.h diff -Nru gcc-4.7-4.7.2/debian/patches/armhf-triplet.diff gcc-4.7-4.7.3/debian/patches/armhf-triplet.diff --- gcc-4.7-4.7.2/debian/patches/armhf-triplet.diff 2013-07-25 18:49:32.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/armhf-triplet.diff 2013-07-25 18:49:34.000000000 +0000 @@ -1,8 +1,10 @@ # DP: add support for arm-linux-*eabi* triplets; useful for armhf ---- a/src/libjava/configure.ac.orig +Index: b/src/libjava/configure.ac +=================================================================== +--- a/src/libjava/configure.ac +++ b/src/libjava/configure.ac -@@ -924,7 +924,7 @@ +@@ -933,7 +933,7 @@ # on Darwin -single_module speeds up loading of the dynamic libraries. extra_ldflags_libjava=-Wl,-single_module ;; @@ -11,38 +13,42 @@ # Some of the ARM unwinder code is actually in libstdc++. We # could in principle replicate it in libgcj, but it's better to # have a dependency on libstdc++. ---- a/src/gcc/config.gcc.orig +Index: b/src/gcc/config.gcc +=================================================================== +--- a/src/gcc/config.gcc +++ b/src/gcc/config.gcc -@@ -822,7 +822,7 @@ +@@ -907,7 +907,7 @@ esac - tmake_file="${tmake_file} t-linux arm/t-arm" + tmake_file="${tmake_file} arm/t-arm" case ${target} in - arm*-*-linux-*eabi) + arm*-*-linux-*eabi*) tm_file="$tm_file arm/bpabi.h arm/linux-eabi.h" - tm_file="$tm_file ../../libgcc/config/arm/bpabi-lib.h" - tmake_file="$tmake_file arm/t-arm-elf arm/t-bpabi arm/t-linux-eabi t-slibgcc-libgcc" -@@ -850,7 +850,7 @@ + tmake_file="$tmake_file arm/t-arm-elf arm/t-bpabi arm/t-linux-eabi" + # Define multilib configuration for arm-linux-androideabi. +@@ -934,7 +934,7 @@ tm_file="dbxelf.h elfos.h arm/unknown-elf.h arm/elf.h arm/linux-gas.h arm/uclinux-elf.h glibc-stdint.h" tmake_file="arm/t-arm arm/t-arm-elf" case ${target} in - arm*-*-uclinux*eabi) + arm*-*-uclinux*eabi*) tm_file="$tm_file arm/bpabi.h arm/uclinux-eabi.h" - tm_file="$tm_file ../../libgcc/config/arm/bpabi-lib.h" tmake_file="$tmake_file arm/t-bpabi" ---- a/src/gcc/testsuite/lib/target-supports.exp.orig + # The BPABI long long divmod functions return a 128-bit value in +Index: b/src/gcc/testsuite/lib/target-supports.exp +=================================================================== +--- a/src/gcc/testsuite/lib/target-supports.exp +++ b/src/gcc/testsuite/lib/target-supports.exp -@@ -3235,7 +3235,7 @@ - || [istarget i?86-*-*] +@@ -3890,7 +3890,7 @@ || [istarget x86_64-*-*] + || [istarget aarch64*-*-*] || [istarget alpha*-*-*] - || [istarget arm*-*-linux-gnueabi] + || [istarget arm*-*-linux-*eabi*] || [istarget bfin*-*linux*] || [istarget hppa*-*linux*] || [istarget s390*-*-*] -@@ -3266,7 +3266,7 @@ +@@ -3921,7 +3921,7 @@ || [istarget i?86-*-*] || [istarget x86_64-*-*] || [istarget alpha*-*-*] @@ -51,9 +57,11 @@ || [istarget hppa*-*linux*] || [istarget s390*-*-*] || [istarget powerpc*-*-*] ---- a/src/gcc/ada/gcc-interface/Makefile.in.orig +Index: b/src/gcc/ada/gcc-interface/Makefile.in +=================================================================== +--- a/src/gcc/ada/gcc-interface/Makefile.in +++ b/src/gcc/ada/gcc-interface/Makefile.in -@@ -1846,7 +1846,7 @@ +@@ -1866,7 +1866,7 @@ LIBRARY_VERSION := $(LIB_VERSION) endif @@ -62,9 +70,11 @@ LIBGNAT_TARGET_PAIRS = \ a-intnam.ads // ---- a/src/libstdc++-v3/testsuite/20_util/make_signed/requirements/typedefs-2.cc.orig +Index: b/src/libstdc++-v3/testsuite/20_util/make_signed/requirements/typedefs-2.cc +=================================================================== +--- a/src/libstdc++-v3/testsuite/20_util/make_signed/requirements/typedefs-2.cc +++ b/src/libstdc++-v3/testsuite/20_util/make_signed/requirements/typedefs-2.cc @@ -1,5 +1,5 @@ // { dg-options "-std=gnu++0x -funsigned-char -fshort-enums" } @@ -91,9 +105,11 @@ // 2007-05-03 Benjamin Kosnik // +Index: b/src/libgcc/config.host +=================================================================== --- a/src/libgcc/config.host +++ b/src/libgcc/config.host -@@ -334,7 +334,7 @@ +@@ -340,7 +340,7 @@ arm*-*-linux*) # ARM GNU/Linux with ELF tmake_file="${tmake_file} arm/t-arm t-fixedpoint-gnu-prefix" case ${host} in diff -Nru gcc-4.7-4.7.2/debian/patches/cell-branch-doc.diff gcc-4.7-4.7.3/debian/patches/cell-branch-doc.diff --- gcc-4.7-4.7.2/debian/patches/cell-branch-doc.diff 2013-07-25 18:49:32.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/cell-branch-doc.diff 1970-01-01 00:00:00.000000000 +0000 @@ -1,2 +0,0 @@ -# DP: Updates from the cell-4_5-branch (documentation) up to 2010xxxx - diff -Nru gcc-4.7-4.7.2/debian/patches/cell-branch.diff gcc-4.7-4.7.3/debian/patches/cell-branch.diff --- gcc-4.7-4.7.2/debian/patches/cell-branch.diff 2013-07-25 18:49:32.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/cell-branch.diff 1970-01-01 00:00:00.000000000 +0000 @@ -1,4 +0,0 @@ -# DP: Updates from the cell-4_5-branch up to 2010xxxx - -svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_5-branch@xxxx svn://gcc.gnu.org/svn/gcc/branches/cell-4_5-branch - diff -Nru gcc-4.7-4.7.2/debian/patches/config-ml.diff gcc-4.7-4.7.3/debian/patches/config-ml.diff --- gcc-4.7-4.7.2/debian/patches/config-ml.diff 2013-07-25 18:49:32.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/config-ml.diff 2013-07-25 18:49:34.000000000 +0000 @@ -1,35 +1,11 @@ -# DP: disable some biarch libraries for biarch builds - ---- - config-ml.in | 45 ++++++++++++++++++++++++++++++++++++++++++++- - 1 files changed, 44 insertions(+), 1 deletions(-) +# DP: - Disable some biarch libraries for biarch builds. +# DP: - Fix multilib builds on kernels which don't support all multilibs. +Index: b/src/config-ml.in +=================================================================== --- a/src/config-ml.in +++ b/src/config-ml.in -@@ -306,6 +306,11 @@ - done - fi - ;; -+i[34567]86-*-*) -+ case " $multidirs " in -+ *" 64 "*) ac_configure_args="${ac_configure_args} --host=x86_64-linux-gnu" -+ esac -+ ;; - m68*-*-*) - if [ x$enable_softfloat = xno ] - then -@@ -477,9 +482,36 @@ - esac - done - fi -+ case " $multidirs " in -+ *" 64 "*) ac_configure_args="${ac_configure_args} --host=powerpc64-linux-gnu" -+ esac -+ ;; -+s390-*-*) -+ case " $multidirs " in -+ *" 64 "*) ac_configure_args="${ac_configure_args} --host=s390x-linux-gnu" -+ esac +@@ -467,6 +467,25 @@ ;; esac @@ -43,7 +19,7 @@ +multidirs="" +for x in ${old_multidirs}; do + case " $x " in -+ " 32 "|" n32 "|" 64 "|" hf "|" sf ") ++ " 32 "|" n32 "|" x32 "|" 64 "|" hf "|" sf ") + case "$biarch_multidir_names" in + *"$ml_srcbase"*) multidirs="${multidirs} ${x}" ;; + esac @@ -55,7 +31,43 @@ # Remove extraneous blanks from multidirs. # Tests like `if [ -n "$multidirs" ]' require it. multidirs=`echo "$multidirs" | sed -e 's/^[ ][ ]*//' -e 's/[ ][ ]*$//' -e 's/[ ][ ]*/ /g'` -@@ -871,9 +903,20 @@ +@@ -654,6 +673,35 @@ + + for ml_dir in ${multidirs}; do + ++ # a native build fails if the running kernel doesn't support the multilib ++ # variant; force cross compilation for these cases. ++ ml_host_arg= ++ case "${host}" in ++ i[34567]86-*-linux*) ++ case "${ml_dir}" in ++ 64) ml_host_arg="--host=x86_64-linux-gnu";; ++ x32) ml_host_arg="--host=x86_64-linux-gnux32";; ++ esac ++ ;; ++ powerpc-*-linux*) ++ case "${ml_dir}" in ++ 64) ml_host_arg="--host=powerpc64-linux-gnu" ++ esac ++ ;; ++ s390-*-linux*) ++ case "${ml_dir}" in ++ 64) ml_host_arg="--host=s390x-linux-gnu" ++ esac ++ ;; ++ x86_64-*-linux*) ++ case "${ml_dir}" in ++ x32) ml_host_arg="--host=x86_64-linux-gnux32" ++ esac ++ esac ++ if [ -n "${ml_host_arg}" ]; then ++ ml_host_arg="${ml_host_arg} --with-default-host-alias=${host_alias}" ++ fi ++ + if [ "${ml_verbose}" = --verbose ]; then + echo "Running configure in multilib subdir ${ml_dir}" + echo "pwd: `${PWDCMD-pwd}`" +@@ -858,9 +906,20 @@ fi fi @@ -73,7 +85,76 @@ if eval ${ml_config_env} ${ml_config_shell} ${ml_recprog} \ --with-multisubdir=${ml_dir} --with-multisrctop=${multisrctop} \ - ${ac_configure_args} ${ml_config_env} ${ml_srcdiroption} ; then -+ ${ac_configure_args} ${ml_configure_args} ${ml_srcdiroption} ; then ++ ${ac_configure_args} ${ml_configure_args} ${ml_host_arg} ${ml_srcdiroption} ; then true else exit 1 +Index: b/src/libstdc++-v3/include/Makefile.am +=================================================================== +--- a/src/libstdc++-v3/include/Makefile.am ++++ b/src/libstdc++-v3/include/Makefile.am +@@ -821,8 +821,9 @@ + endif + + host_srcdir = ${glibcxx_srcdir}/$(OS_INC_SRCDIR) +-host_builddir = ./${host_alias}/bits +-host_installdir = ${gxx_include_dir}/${host_alias}$(MULTISUBDIR)/bits ++default_host_alias = @default_host_alias@ ++host_builddir = ./${default_host_alias}/bits ++host_installdir = ${gxx_include_dir}/${default_host_alias}$(MULTISUBDIR)/bits + host_headers = \ + ${host_srcdir}/ctype_base.h \ + ${host_srcdir}/ctype_inline.h \ +@@ -1042,6 +1043,7 @@ + + stamp-${host_alias}: + @-mkdir -p ${host_builddir} ++ @test ${default_host_alias} = ${host_alias} || ln -sf ${default_host_alias} ${host_alias} + @$(STAMP) stamp-${host_alias} + + # Host includes static. +Index: b/src/libstdc++-v3/include/Makefile.in +=================================================================== +--- a/src/libstdc++-v3/include/Makefile.in ++++ b/src/libstdc++-v3/include/Makefile.in +@@ -1066,8 +1066,9 @@ + # For --enable-cheaders=c_std + @GLIBCXX_C_HEADERS_COMPATIBILITY_TRUE@c_compatibility_headers_extra = ${c_compatibility_headers} + host_srcdir = ${glibcxx_srcdir}/$(OS_INC_SRCDIR) +-host_builddir = ./${host_alias}/bits +-host_installdir = ${gxx_include_dir}/${host_alias}$(MULTISUBDIR)/bits ++default_host_alias = @default_host_alias@ ++host_builddir = ./${default_host_alias}/bits ++host_installdir = ${gxx_include_dir}/${default_host_alias}$(MULTISUBDIR)/bits + host_headers = \ + ${host_srcdir}/ctype_base.h \ + ${host_srcdir}/ctype_inline.h \ +@@ -1445,6 +1446,7 @@ + + stamp-${host_alias}: + @-mkdir -p ${host_builddir} ++ @test ${default_host_alias} = ${host_alias} || ln -sf ${default_host_alias} ${host_alias} + @$(STAMP) stamp-${host_alias} + + # Host includes static. +Index: b/src/libstdc++-v3/configure.ac +=================================================================== +--- a/src/libstdc++-v3/configure.ac ++++ b/src/libstdc++-v3/configure.ac +@@ -447,6 +447,16 @@ + multilib_arg= + fi + ++AC_ARG_WITH(default-host-alias, ++[AS_HELP_STRING([--with-default-host-alias=TRIPLET], ++ [specifies host triplet used for the default multilib build])], ++[case "${withval}" in ++yes) AC_MSG_ERROR(bad value ${withval} given for default host triplet) ;; ++no) default_host_alias='${host_alias}' ;; ++*) default_host_alias=${withval} ;; ++esac],[default_host_alias='${host_alias}']) ++AC_SUBST(default_host_alias) ++ + # Export all the install information. + GLIBCXX_EXPORT_INSTALL_INFO + diff -Nru gcc-4.7-4.7.2/debian/patches/cross-fixes.diff gcc-4.7-4.7.3/debian/patches/cross-fixes.diff --- gcc-4.7-4.7.2/debian/patches/cross-fixes.diff 2013-07-25 18:49:32.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/cross-fixes.diff 2013-07-25 18:49:34.000000000 +0000 @@ -1,32 +1,17 @@ # DP: Fix the linker error when creating an xcc for ia64 --- - gcc/config/alpha/linux-unwind.h | 3 +++ gcc/config/ia64/fde-glibc.c | 3 +++ gcc/config/ia64/unwind-ia64.c | 3 ++- gcc/unwind-compat.c | 2 ++ gcc/unwind-generic.h | 2 ++ 6 files changed, 14 insertions(+), 1 deletions(-) ---- a/src/libgcc/config/alpha/linux-unwind.h -+++ b/src/libgcc/config/alpha/linux-unwind.h -@@ -29,6 +29,7 @@ Boston, MA 02110-1301, USA. */ - /* Do code reading to identify a signal frame, and set the frame - state data appropriately. See unwind-dw2.c for the structs. */ - -+#ifndef inhibit_libc - #include - #include - -@@ -80,3 +81,5 @@ alpha_fallback_frame_state (struct _Unwind_Context *context, - fs->retaddr_column = 64; - return _URC_NO_REASON; - } -+ -+#endif +Index: b/src/libgcc/config/ia64/fde-glibc.c +=================================================================== --- a/src/libgcc/config/ia64/fde-glibc.c +++ b/src/libgcc/config/ia64/fde-glibc.c -@@ -31,6 +31,7 @@ +@@ -28,6 +28,7 @@ #ifndef _GNU_SOURCE #define _GNU_SOURCE 1 #endif @@ -34,54 +19,60 @@ #include "config.h" #include #include -@@ -162,3 +163,5 @@ _Unwind_FindTableEntry (void *pc, unsigned long *segment_base, - +@@ -160,3 +161,5 @@ + return data.ret; } + +#endif +Index: b/src/libgcc/config/ia64/unwind-ia64.c +=================================================================== --- a/src/libgcc/config/ia64/unwind-ia64.c +++ b/src/libgcc/config/ia64/unwind-ia64.c @@ -27,6 +27,7 @@ - This exception does not however invalidate any other reasons why - the executable file might be covered by the GNU General Public License. */ - + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +#ifndef inhibit_libc #include "tconfig.h" #include "tsystem.h" #include "coretypes.h" -@@ -2417,3 +2417,4 @@ alias (_Unwind_SetIP); +@@ -2469,3 +2470,4 @@ #endif - + #endif +#endif +Index: b/src/libgcc/unwind-compat.c +=================================================================== --- a/src/libgcc/unwind-compat.c +++ b/src/libgcc/unwind-compat.c -@@ -29,6 +29,7 @@ - 02110-1301, USA. */ - +@@ -24,6 +24,7 @@ + . */ + #if defined (USE_GAS_SYMVER) && defined (USE_LIBUNWIND_EXCEPTIONS) +#ifndef inhibit_libc #include "tconfig.h" #include "tsystem.h" #include "unwind.h" -@@ -213,3 +214,4 @@ _Unwind_SetIP (struct _Unwind_Context *context, _Unwind_Ptr val) +@@ -208,3 +209,4 @@ } symver (_Unwind_SetIP, GCC_3.0); #endif +#endif +Index: b/src/libgcc/unwind-generic.h +=================================================================== --- a/src/libgcc/unwind-generic.h +++ b/src/libgcc/unwind-generic.h -@@ -214,6 +214,7 @@ _Unwind_SjLj_Resume_or_Rethrow (struct _Unwind_Exception *); +@@ -211,6 +211,7 @@ compatible with the standard ABI for IA-64, we inline these. */ - + #ifdef __ia64__ +#ifndef inhibit_libc #include - + static inline _Unwind_Ptr -@@ -232,6 +233,7 @@ _Unwind_GetTextRelBase (struct _Unwind_Context *_C __attribute__ ((__unused__))) - +@@ -229,6 +230,7 @@ + /* @@@ Retrieve the Backing Store Pointer of the given context. */ extern _Unwind_Word _Unwind_GetBSP (struct _Unwind_Context *); +#endif diff -Nru gcc-4.7-4.7.2/debian/patches/cross-include.diff gcc-4.7-4.7.3/debian/patches/cross-include.diff --- gcc-4.7-4.7.2/debian/patches/cross-include.diff 2013-07-25 18:49:32.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/cross-include.diff 1970-01-01 00:00:00.000000000 +0000 @@ -1,18 +0,0 @@ -# DP: Set cross include path to .../include, not .../sys-include -# DP: This should be a fix for famous limits.h issue - ---- - gcc/configure.ac | 2 +- - 1 files changed, 1 insertions(+), 1 deletions(-) - ---- a/src/gcc/configure.ac -+++ b/src/gcc/configure.ac -@@ -764,7 +764,7 @@ AC_ARG_WITH(sysroot, - ], [ - TARGET_SYSTEM_ROOT= - TARGET_SYSTEM_ROOT_DEFINE= -- CROSS_SYSTEM_HEADER_DIR='$(gcc_tooldir)/sys-include' -+ CROSS_SYSTEM_HEADER_DIR='/usr/$(target_noncanonical)/include' - ]) - AC_SUBST(TARGET_SYSTEM_ROOT) - AC_SUBST(TARGET_SYSTEM_ROOT_DEFINE) diff -Nru gcc-4.7-4.7.2/debian/patches/cross-install-location.diff gcc-4.7-4.7.3/debian/patches/cross-install-location.diff --- gcc-4.7-4.7.2/debian/patches/cross-install-location.diff 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/cross-install-location.diff 2013-07-25 18:49:34.000000000 +0000 @@ -0,0 +1,335 @@ +--- a/src/libmudflap/Makefile.in 2012-12-08 08:32:41.301881153 +0100 ++++ b/src/libmudflap/Makefile.in 2012-12-08 08:58:29.281874520 +0100 +@@ -269,7 +269,7 @@ + @LIBMUDFLAPTH_FALSE@libmudflapth = + @LIBMUDFLAPTH_TRUE@libmudflapth = libmudflapth.la + toolexeclib_LTLIBRARIES = libmudflap.la $(libmudflapth) +-libsubincludedir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version)/include ++libsubincludedir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version)/include + nobase_libsubinclude_HEADERS = mf-runtime.h + libmudflap_la_SOURCES = \ + mf-runtime.c \ +--- a/src/libmudflap/Makefile.am 2012-12-08 08:32:41.301881153 +0100 ++++ b/src/libmudflap/Makefile.am 2012-12-08 08:58:04.633876182 +0100 +@@ -23,7 +23,7 @@ + + toolexeclib_LTLIBRARIES = libmudflap.la $(libmudflapth) + target_noncanonical = @target_noncanonical@ +-libsubincludedir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version)/include ++libsubincludedir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version)/include + nobase_libsubinclude_HEADERS = mf-runtime.h + + +--- a/src/fixincludes/Makefile.in 2011-01-03 21:52:22.000000000 +0100 ++++ b/src/fixincludes/Makefile.in 2012-12-08 08:53:27.029874709 +0100 +@@ -52,9 +52,9 @@ + gcc_version := $(shell cat $(srcdir)/../gcc/BASE-VER) + + # Directory in which the compiler finds libraries etc. +-libsubdir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version) ++libsubdir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version) + # Directory in which the compiler finds executables +-libexecsubdir = $(libexecdir)/gcc/$(target_noncanonical)/$(gcc_version) ++libexecsubdir = $(libexecdir)/gcc-cross/$(target_noncanonical)/$(gcc_version) + # Where our executable files go + itoolsdir = $(libexecsubdir)/install-tools + # Where our data files go +--- a/src/libgfortran/Makefile.in 2012-09-20 09:23:55.000000000 +0200 ++++ b/src/libgfortran/Makefile.in 2012-12-08 08:50:26.369874316 +0100 +@@ -499,12 +499,12 @@ + + libgfortran_la_DEPENDENCIES = $(version_dep) libgfortran.spec $(LIBQUADLIB_DEP) + myexeclib_LTLIBRARIES = libgfortranbegin.la +-myexeclibdir = $(libdir)/gcc/$(target_alias)/$(gcc_version)$(MULTISUBDIR) ++myexeclibdir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)$(MULTISUBDIR) + libgfortranbegin_la_SOURCES = fmain.c + libgfortranbegin_la_LDFLAGS = -static + libgfortranbegin_la_LINK = $(LINK) $(libgfortranbegin_la_LDFLAGS) + cafexeclib_LTLIBRARIES = libcaf_single.la +-cafexeclibdir = $(libdir)/gcc/$(target_alias)/$(gcc_version)$(MULTISUBDIR) ++cafexeclibdir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)$(MULTISUBDIR) + libcaf_single_la_SOURCES = caf/single.c + libcaf_single_la_LDFLAGS = -static + libcaf_single_la_DEPENDENCIES = caf/libcaf.h +--- a/src/libgfortran/Makefile.am 2012-01-09 17:02:36.000000000 +0100 ++++ b/src/libgfortran/Makefile.am 2012-12-08 08:49:41.957876998 +0100 +@@ -42,13 +42,13 @@ + libgfortran_la_DEPENDENCIES = $(version_dep) libgfortran.spec $(LIBQUADLIB_DEP) + + myexeclib_LTLIBRARIES = libgfortranbegin.la +-myexeclibdir = $(libdir)/gcc/$(target_alias)/$(gcc_version)$(MULTISUBDIR) ++myexeclibdir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)$(MULTISUBDIR) + libgfortranbegin_la_SOURCES = fmain.c + libgfortranbegin_la_LDFLAGS = -static + libgfortranbegin_la_LINK = $(LINK) $(libgfortranbegin_la_LDFLAGS) + + cafexeclib_LTLIBRARIES = libcaf_single.la +-cafexeclibdir = $(libdir)/gcc/$(target_alias)/$(gcc_version)$(MULTISUBDIR) ++cafexeclibdir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)$(MULTISUBDIR) + libcaf_single_la_SOURCES = caf/single.c + libcaf_single_la_LDFLAGS = -static + libcaf_single_la_DEPENDENCIES = caf/libcaf.h +--- a/src/lto-plugin/Makefile.in 2011-08-10 10:48:37.000000000 +0200 ++++ b/src/lto-plugin/Makefile.in 2012-12-08 09:00:17.861873944 +0100 +@@ -227,7 +227,7 @@ + ACLOCAL_AMFLAGS = -I .. -I ../config + AUTOMAKE_OPTIONS = no-dependencies + gcc_version := $(shell cat $(top_srcdir)/../gcc/BASE-VER) +-libexecsubdir := $(libexecdir)/gcc/$(target_noncanonical)/$(gcc_version) ++libexecsubdir := $(libexecdir)/gcc-cross/$(target_noncanonical)/$(gcc_version) + AM_CPPFLAGS = -I$(top_srcdir)/../include $(DEFS) + AM_CFLAGS = @ac_lto_plugin_warn_cflags@ + AM_LIBTOOLFLAGS = --tag=disable-static +--- a/src/lto-plugin/Makefile.am 2011-08-10 10:48:37.000000000 +0200 ++++ b/src/lto-plugin/Makefile.am 2012-12-08 08:59:54.621875067 +0100 +@@ -5,7 +5,7 @@ + + gcc_version := $(shell cat $(top_srcdir)/../gcc/BASE-VER) + target_noncanonical := @target_noncanonical@ +-libexecsubdir := $(libexecdir)/gcc/$(target_noncanonical)/$(gcc_version) ++libexecsubdir := $(libexecdir)/gcc-cross/$(target_noncanonical)/$(gcc_version) + + AM_CPPFLAGS = -I$(top_srcdir)/../include $(DEFS) + AM_CFLAGS = @ac_lto_plugin_warn_cflags@ +--- a/src/libitm/Makefile.in 2012-12-08 08:32:40.093881158 +0100 ++++ b/src/libitm/Makefile.in 2012-12-08 08:54:51.929875619 +0100 +@@ -306,8 +306,8 @@ + gcc_version := $(shell cat $(top_srcdir)/../gcc/BASE-VER) + abi_version = -fabi-version=4 + search_path = $(addprefix $(top_srcdir)/config/, $(config_path)) $(top_srcdir) +-fincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/finclude +-libsubincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/include ++fincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/finclude ++libsubincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include + AM_CPPFLAGS = $(addprefix -I, $(search_path)) + AM_CFLAGS = $(XCFLAGS) + AM_CXXFLAGS = $(XCFLAGS) -std=gnu++0x -funwind-tables -fno-exceptions \ +--- a/src/libitm/Makefile.am 2012-02-14 14:14:27.000000000 +0100 ++++ b/src/libitm/Makefile.am 2012-12-08 08:53:58.341873782 +0100 +@@ -11,8 +11,8 @@ + config_path = @config_path@ + search_path = $(addprefix $(top_srcdir)/config/, $(config_path)) $(top_srcdir) + +-fincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/finclude +-libsubincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/include ++fincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/finclude ++libsubincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include + + vpath % $(strip $(search_path)) + +--- a/src/gcc/gcc.c 2012-08-06 16:34:27.000000000 +0200 ++++ b/src/gcc/gcc.c 2012-12-08 08:42:06.353877392 +0100 +@@ -3621,7 +3621,7 @@ + GCC_EXEC_PREFIX is typically a directory name with a trailing + / (which is ignored by make_relative_prefix), so append a + program name. */ +- char *tmp_prefix = concat (gcc_exec_prefix, "gcc", NULL); ++ char *tmp_prefix = concat (gcc_exec_prefix, "gcc-cross", NULL); + gcc_libexec_prefix = get_relative_prefix (tmp_prefix, + standard_exec_prefix, + standard_libexec_prefix); +@@ -3647,15 +3647,15 @@ + { + int len = strlen (gcc_exec_prefix); + +- if (len > (int) sizeof ("/lib/gcc/") - 1 ++ if (len > (int) sizeof ("/lib/gcc-cross/") - 1 + && (IS_DIR_SEPARATOR (gcc_exec_prefix[len-1]))) + { +- temp = gcc_exec_prefix + len - sizeof ("/lib/gcc/") + 1; ++ temp = gcc_exec_prefix + len - sizeof ("/lib/gcc-cross/") + 1; + if (IS_DIR_SEPARATOR (*temp) + && filename_ncmp (temp + 1, "lib", 3) == 0 + && IS_DIR_SEPARATOR (temp[4]) +- && filename_ncmp (temp + 5, "gcc", 3) == 0) +- len -= sizeof ("/lib/gcc/") - 1; ++ && filename_ncmp (temp + 5, "gcc-cross", 3) == 0) ++ len -= sizeof ("/lib/gcc-cross/") - 1; + } + + set_std_prefix (gcc_exec_prefix, len); +--- a/src/gcc/Makefile.in 2012-12-08 08:32:41.337881153 +0100 ++++ b/src/gcc/Makefile.in 2012-12-08 08:36:18.493883559 +0100 +@@ -566,9 +566,9 @@ + # -------- + + # Directory in which the compiler finds libraries etc. +-libsubdir = $(libdir)/gcc/$(target_noncanonical)/$(version) ++libsubdir = $(libdir)/gcc-cross/$(target_noncanonical)/$(version) + # Directory in which the compiler finds executables +-libexecsubdir = $(libexecdir)/gcc/$(target_noncanonical)/$(version) ++libexecsubdir = $(libexecdir)/gcc-cross/$(target_noncanonical)/$(version) + # Directory in which all plugin resources are installed + plugin_resourcesdir = $(libsubdir)/plugin + # Directory in which plugin headers are installed +@@ -2079,8 +2079,8 @@ + + DRIVER_DEFINES = \ + -DSTANDARD_STARTFILE_PREFIX=\"$(unlibsubdir)/\" \ +- -DSTANDARD_EXEC_PREFIX=\"$(libdir)/gcc/\" \ +- -DSTANDARD_LIBEXEC_PREFIX=\"$(libexecdir)/gcc/\" \ ++ -DSTANDARD_EXEC_PREFIX=\"$(libdir)/gcc-cross/\" \ ++ -DSTANDARD_LIBEXEC_PREFIX=\"$(libexecdir)/gcc-cross/\" \ + -DDEFAULT_TARGET_VERSION=\"$(version)\" \ + -DDEFAULT_TARGET_MACHINE=\"$(target_noncanonical)\" \ + -DSTANDARD_BINDIR_PREFIX=\"$(bindir)/\" \ +@@ -3980,7 +3980,7 @@ + -DTOOL_INCLUDE_DIR=\"$(gcc_tooldir)/include\" \ + -DNATIVE_SYSTEM_HEADER_DIR=\"$(NATIVE_SYSTEM_HEADER_DIR)\" \ + -DPREFIX=\"$(prefix)/\" \ +- -DSTANDARD_EXEC_PREFIX=\"$(libdir)/gcc/\" \ ++ -DSTANDARD_EXEC_PREFIX=\"$(libdir)/gcc-cross/\" \ + @TARGET_SYSTEM_ROOT_DEFINE@ + + CFLAGS-cppbuiltin.o += $(PREPROCESSOR_DEFINES) -DBASEVER=$(FULLVER_s) +--- a/src/libssp/Makefile.in 2011-02-13 12:45:53.000000000 +0100 ++++ b/src/libssp/Makefile.in 2012-12-08 08:59:07.469875025 +0100 +@@ -259,7 +259,7 @@ + @LIBSSP_USE_SYMVER_SUN_TRUE@@LIBSSP_USE_SYMVER_TRUE@version_dep = ssp.map-sun + AM_CFLAGS = -Wall + toolexeclib_LTLIBRARIES = libssp.la libssp_nonshared.la +-libsubincludedir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version)/include ++libsubincludedir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version)/include + nobase_libsubinclude_HEADERS = ssp/ssp.h ssp/string.h ssp/stdio.h ssp/unistd.h + libssp_la_SOURCES = \ + ssp.c gets-chk.c memcpy-chk.c memmove-chk.c mempcpy-chk.c \ +--- a/src/libssp/Makefile.am 2010-12-06 01:50:04.000000000 +0100 ++++ b/src/libssp/Makefile.am 2012-12-08 08:58:51.241873553 +0100 +@@ -39,7 +39,7 @@ + toolexeclib_LTLIBRARIES = libssp.la libssp_nonshared.la + + target_noncanonical = @target_noncanonical@ +-libsubincludedir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version)/include ++libsubincludedir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version)/include + nobase_libsubinclude_HEADERS = ssp/ssp.h ssp/string.h ssp/stdio.h ssp/unistd.h + + libssp_la_SOURCES = \ +--- a/src/libquadmath/Makefile.in 2011-09-21 16:36:03.000000000 +0200 ++++ b/src/libquadmath/Makefile.in 2012-12-08 08:49:10.557875680 +0100 +@@ -319,7 +319,7 @@ + + @BUILD_LIBQUADMATH_TRUE@libquadmath_la_DEPENDENCIES = $(version_dep) $(libquadmath_la_LIBADD) + @BUILD_LIBQUADMATH_TRUE@nodist_libsubinclude_HEADERS = quadmath.h quadmath_weak.h +-@BUILD_LIBQUADMATH_TRUE@libsubincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/include ++@BUILD_LIBQUADMATH_TRUE@libsubincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include + @BUILD_LIBQUADMATH_TRUE@libquadmath_la_SOURCES = \ + @BUILD_LIBQUADMATH_TRUE@ math/acoshq.c math/fmodq.c math/acosq.c math/frexpq.c \ + @BUILD_LIBQUADMATH_TRUE@ math/rem_pio2q.c math/asinhq.c math/hypotq.c math/remainderq.c \ +--- a/src/libquadmath/Makefile.am 2011-09-21 16:36:03.000000000 +0200 ++++ b/src/libquadmath/Makefile.am 2012-12-08 08:48:25.553878276 +0100 +@@ -40,7 +40,7 @@ + libquadmath_la_DEPENDENCIES = $(version_dep) $(libquadmath_la_LIBADD) + + nodist_libsubinclude_HEADERS = quadmath.h quadmath_weak.h +-libsubincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/include ++libsubincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include + + libquadmath_la_SOURCES = \ + math/acoshq.c math/fmodq.c math/acosq.c math/frexpq.c \ +--- a/src/libobjc/Makefile.in 2011-11-02 16:28:43.000000000 +0100 ++++ b/src/libobjc/Makefile.in 2012-12-08 08:50:47.241873110 +0100 +@@ -51,7 +51,7 @@ + -include ../boehm-gc/threads.mk + + libdir = $(exec_prefix)/lib +-libsubdir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version) ++libsubdir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version) + + # Multilib support variables. + MULTISRCTOP = +--- a/src/libada/Makefile.in 2012-08-06 16:34:27.000000000 +0200 ++++ b/src/libada/Makefile.in 2012-12-08 08:53:01.321876031 +0100 +@@ -62,7 +62,7 @@ + + target_noncanonical:=@target_noncanonical@ + version := $(shell cat $(srcdir)/../gcc/BASE-VER) +-libsubdir := $(libdir)/gcc/$(target_noncanonical)/$(version)$(MULTISUBDIR) ++libsubdir := $(libdir)/gcc-cross/$(target_noncanonical)/$(version)$(MULTISUBDIR) + ADA_RTS_DIR=$(GCC_DIR)/ada/rts$(subst /,_,$(MULTISUBDIR)) + ADA_RTS_SUBDIR=./rts$(subst /,_,$(MULTISUBDIR)) + +--- a/src/libgomp/Makefile.in 2012-09-20 09:23:55.000000000 +0200 ++++ b/src/libgomp/Makefile.in 2012-12-08 08:45:32.157878288 +0100 +@@ -291,8 +291,8 @@ + SUBDIRS = testsuite + gcc_version := $(shell cat $(top_srcdir)/../gcc/BASE-VER) + search_path = $(addprefix $(top_srcdir)/config/, $(config_path)) $(top_srcdir) +-fincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/finclude +-libsubincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/include ++fincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/finclude ++libsubincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include + AM_CPPFLAGS = $(addprefix -I, $(search_path)) + AM_CFLAGS = $(XCFLAGS) + AM_LDFLAGS = $(XLDFLAGS) $(SECTION_LDFLAGS) $(OPT_LDFLAGS) +--- a/src/libgomp/Makefile.am 2012-02-27 14:51:50.000000000 +0100 ++++ b/src/libgomp/Makefile.am 2012-12-08 08:44:48.913867574 +0100 +@@ -9,8 +9,8 @@ + config_path = @config_path@ + search_path = $(addprefix $(top_srcdir)/config/, $(config_path)) $(top_srcdir) + +-fincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/finclude +-libsubincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/include ++fincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/finclude ++libsubincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include + + vpath % $(strip $(search_path)) + +--- a/src/libgcc/Makefile.in 2012-12-08 08:32:41.249881153 +0100 ++++ b/src/libgcc/Makefile.in 2012-12-08 08:43:50.201879083 +0100 +@@ -178,7 +178,7 @@ + STRIP_FOR_TARGET = $(STRIP) + + # Directory in which the compiler finds libraries etc. +-libsubdir = $(libdir)/gcc/$(host_noncanonical)/$(version) ++libsubdir = $(libdir)/gcc-cross/$(host_noncanonical)/$(version) + # Used to install the shared libgcc. + slibdir = @slibdir@ + # Maybe used for DLLs on Windows targets. +--- a/src/libjava/Makefile.in 2012-12-08 08:32:41.249881153 +0100 ++++ b/src/libjava/Makefile.in 2012-12-08 08:51:43.365881984 +0100 +@@ -785,8 +785,8 @@ + + + # This is required by TL_AC_GXX_INCLUDE_DIR. +-libsubdir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version) +-libexecsubdir = $(libexecdir)/gcc/$(target_noncanonical)/$(gcc_version) ++libsubdir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version) ++libexecsubdir = $(libexecdir)/gcc-cross/$(target_noncanonical)/$(gcc_version) + toolexeclib_LTLIBRARIES = libgcj.la libgij.la libgcj-tools.la \ + $(am__append_2) $(am__append_3) $(am__append_4) + toolexecmainlib_DATA = libgcj.spec +--- a/src/libjava/Makefile.am 2012-12-08 08:32:41.241881153 +0100 ++++ b/src/libjava/Makefile.am 2012-12-08 08:51:13.481876463 +0100 +@@ -34,9 +34,9 @@ + target_noncanonical = @target_noncanonical@ + + # This is required by TL_AC_GXX_INCLUDE_DIR. +-libsubdir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version) ++libsubdir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version) + +-libexecsubdir = $(libexecdir)/gcc/$(target_noncanonical)/$(gcc_version) ++libexecsubdir = $(libexecdir)/gcc-cross/$(target_noncanonical)/$(gcc_version) + + ## + ## What gets installed, and where. +--- a/src/libffi/include/Makefile.am 2006-09-12 18:51:43.000000000 +0200 ++++ b/src/libffi/include/Makefile.am 2012-12-08 09:42:12.313863513 +0100 +@@ -7,6 +7,6 @@ + + # Where generated headers like ffitarget.h get installed. + gcc_version := $(shell cat $(top_srcdir)/../gcc/BASE-VER) +-toollibffidir := $(libdir)/gcc/$(target_alias)/$(gcc_version)/include ++toollibffidir := $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include + + toollibffi_HEADERS = ffi.h ffitarget.h +--- a/src/libffi/include/Makefile.in 2012-12-08 09:12:36.913870891 +0100 ++++ b/src/libffi/include/Makefile.in 2012-12-08 09:42:24.901862621 +0100 +@@ -213,7 +213,7 @@ + + # Where generated headers like ffitarget.h get installed. + gcc_version := $(shell cat $(top_srcdir)/../gcc/BASE-VER) +-toollibffidir := $(libdir)/gcc/$(target_alias)/$(gcc_version)/include ++toollibffidir := $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include + toollibffi_HEADERS = ffi.h ffitarget.h + all: all-am + diff -Nru gcc-4.7-4.7.2/debian/patches/cross-ma-install-location.diff gcc-4.7-4.7.3/debian/patches/cross-ma-install-location.diff --- gcc-4.7-4.7.2/debian/patches/cross-ma-install-location.diff 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/cross-ma-install-location.diff 2013-07-25 18:49:34.000000000 +0000 @@ -0,0 +1,306 @@ +--- a/src/boehm-gc/configure.ac ++++ b/src/boehm-gc/configure.ac +@@ -493,14 +493,8 @@ + AC_DEFINE(USE_MMAP, 1, [use MMAP instead of sbrk to get new memory]) + fi + +-if test -n "$with_cross_host" && +- test x"$with_cross_host" != x"no"; then +- toolexecdir='$(exec_prefix)/$(target_noncanonical)' +- toolexeclibdir='$(toolexecdir)/lib' +-else +- toolexecdir='$(libdir)/gcc-lib/$(target_noncanonical)' +- toolexeclibdir='$(libdir)' +-fi ++toolexecdir='$(libdir)/gcc-lib/$(target_noncanonical)' ++toolexeclibdir='$(libdir)' + multi_os_directory=`$CC -print-multi-os-directory` + case $multi_os_directory in + .) ;; # Avoid trailing /. +--- a/src/libada/configure.ac ++++ b/src/libada/configure.ac +@@ -65,15 +65,8 @@ + toolexeclibdir='$(toolexecdir)/$(gcc_version)$(MULTISUBDIR)' + ;; + no) +- if test -n "$with_cross_host" && +- test x"$with_cross_host" != x"no"; then +- # Install a library built with a cross compiler in tooldir, not libdir. +- toolexecdir='$(exec_prefix)/$(target_alias)' +- toolexeclibdir='$(toolexecdir)/lib' +- else +- toolexecdir='$(libdir)/gcc-lib/$(target_alias)' +- toolexeclibdir='$(libdir)' +- fi ++ toolexecdir='$(libdir)/gcc-lib/$(target_alias)' ++ toolexeclibdir='$(libdir)' + multi_os_directory=`$CC -print-multi-os-directory` + case $multi_os_directory in + .) ;; # Avoid trailing /. +--- a/src/libffi/configure.ac ++++ b/src/libffi/configure.ac +@@ -421,14 +421,9 @@ + AC_DEFINE(USING_PURIFY, 1, [Define this if you are using Purify and want to suppress spurious messages.]) + fi) + +-if test -n "$with_cross_host" && +- test x"$with_cross_host" != x"no"; then +- toolexecdir='$(exec_prefix)/$(target_alias)' +- toolexeclibdir='$(toolexecdir)/lib' +-else +- toolexecdir='$(libdir)/gcc-lib/$(target_alias)' +- toolexeclibdir='$(libdir)' +-fi ++toolexecdir='$(libdir)/gcc-lib/$(target_alias)' ++toolexeclibdir='$(libdir)' ++ + multi_os_directory=`$CC -print-multi-os-directory` + case $multi_os_directory in + .) ;; # Avoid trailing /. +--- a/src/libgcc/configure.ac ++++ b/src/libgcc/configure.ac +@@ -83,8 +83,6 @@ + slibdir="$with_slibdir", + if test "${version_specific_libs}" = yes; then + slibdir='$(libsubdir)' +-elif test -n "$with_cross_host" && test x"$with_cross_host" != x"no"; then +- slibdir='$(exec_prefix)/$(host_noncanonical)/lib' + else + slibdir='$(libdir)' + fi) +@@ -129,15 +127,8 @@ + toolexeclibdir='$(toolexecdir)/$(gcc_version)$(MULTISUBDIR)' + ;; + no) +- if test -n "$with_cross_host" && +- test x"$with_cross_host" != x"no"; then +- # Install a library built with a cross compiler in tooldir, not libdir. +- toolexecdir='$(exec_prefix)/$(target_noncanonical)' +- toolexeclibdir='$(toolexecdir)/lib' +- else +- toolexecdir='$(libdir)/gcc-lib/$(target_noncanonical)' +- toolexeclibdir='$(libdir)' +- fi ++ toolexecdir='$(libdir)/gcc-lib/$(target_noncanonical)' ++ toolexeclibdir='$(libdir)' + multi_os_directory=`$CC -print-multi-os-directory` + case $multi_os_directory in + .) ;; # Avoid trailing /. +--- a/src/libgfortran/configure.ac ++++ b/src/libgfortran/configure.ac +@@ -98,15 +98,8 @@ + toolexeclibdir='$(toolexecdir)/$(gcc_version)$(MULTISUBDIR)' + ;; + no) +- if test -n "$with_cross_host" && +- test x"$with_cross_host" != x"no"; then +- # Install a library built with a cross compiler in tooldir, not libdir. +- toolexecdir='$(exec_prefix)/$(target_alias)' +- toolexeclibdir='$(toolexecdir)/lib' +- else +- toolexecdir='$(libdir)/gcc-lib/$(target_alias)' +- toolexeclibdir='$(libdir)' +- fi ++ toolexecdir='$(libdir)/gcc-lib/$(target_alias)' ++ toolexeclibdir='$(libdir)' + multi_os_directory=`$CC -print-multi-os-directory` + case $multi_os_directory in + .) ;; # Avoid trailing /. +--- a/src/libgo/configure.ac ++++ b/src/libgo/configure.ac +@@ -77,14 +77,8 @@ + + # Calculate glibgo_toolexecdir, glibgo_toolexeclibdir + # Install a library built with a cross compiler in tooldir, not libdir. +-if test -n "$with_cross_host" && +- test x"$with_cross_host" != x"no"; then +- nover_glibgo_toolexecdir='${exec_prefix}/${host_alias}' +- nover_glibgo_toolexeclibdir='${toolexecdir}/lib' +-else +- nover_glibgo_toolexecdir='${libdir}/gcc/${host_alias}' +- nover_glibgo_toolexeclibdir='${libdir}' +-fi ++nover_glibgo_toolexecdir='${libdir}/gcc/${host_alias}' ++nover_glibgo_toolexeclibdir='${libdir}' + multi_os_directory=`$CC -print-multi-os-directory` + case $multi_os_directory in + .) ;; # Avoid trailing /. +--- a/src/libgomp/configure.ac ++++ b/src/libgomp/configure.ac +@@ -76,15 +76,8 @@ + toolexeclibdir='$(toolexecdir)/$(gcc_version)$(MULTISUBDIR)' + ;; + no) +- if test -n "$with_cross_host" && +- test x"$with_cross_host" != x"no"; then +- # Install a library built with a cross compiler in tooldir, not libdir. +- toolexecdir='$(exec_prefix)/$(target_alias)' +- toolexeclibdir='$(toolexecdir)/lib' +- else +- toolexecdir='$(libdir)/gcc-lib/$(target_alias)' +- toolexeclibdir='$(libdir)' +- fi ++ toolexecdir='$(libdir)/gcc-lib/$(target_alias)' ++ toolexeclibdir='$(libdir)' + multi_os_directory=`$CC -print-multi-os-directory` + case $multi_os_directory in + .) ;; # Avoid trailing /. +--- a/src/libitm/configure.ac ++++ b/src/libitm/configure.ac +@@ -89,15 +89,8 @@ + toolexeclibdir='$(toolexecdir)/$(gcc_version)$(MULTISUBDIR)' + ;; + no) +- if test -n "$with_cross_host" && +- test x"$with_cross_host" != x"no"; then +- # Install a library built with a cross compiler in tooldir, not libdir. +- toolexecdir='$(exec_prefix)/$(target_alias)' +- toolexeclibdir='$(toolexecdir)/lib' +- else +- toolexecdir='$(libdir)/gcc-lib/$(target_alias)' +- toolexeclibdir='$(libdir)' +- fi ++ toolexecdir='$(libdir)/gcc-lib/$(target_alias)' ++ toolexeclibdir='$(libdir)' + multi_os_directory=`$CC -print-multi-os-directory` + case $multi_os_directory in + .) ;; # Avoid trailing /. +--- a/src/libjava/configure.ac ++++ b/src/libjava/configure.ac +@@ -1589,15 +1589,8 @@ + toolexeclibdir=$toolexecmainlibdir + ;; + no) +- if test -n "$with_cross_host" && +- test x"$with_cross_host" != x"no"; then +- # Install a library built with a cross compiler in tooldir, not libdir. +- toolexecdir='$(exec_prefix)/$(target_noncanonical)' +- toolexecmainlibdir='$(toolexecdir)/lib' +- else +- toolexecdir='$(libdir)/gcc-lib/$(target_noncanonical)' +- toolexecmainlibdir='$(libdir)' +- fi ++ toolexecdir='$(libdir)/gcc-lib/$(target_noncanonical)' ++ toolexecmainlibdir='$(libdir)' + multi_os_directory=`$CC -print-multi-os-directory` + case $multi_os_directory in + .) toolexeclibdir=$toolexecmainlibdir ;; # Avoid trailing /. +--- a/src/libmudflap/configure.ac ++++ b/src/libmudflap/configure.ac +@@ -157,15 +157,8 @@ + toolexeclibdir='$(toolexecdir)/$(gcc_version)$(MULTISUBDIR)' + ;; + no) +- if test -n "$with_cross_host" && +- test x"$with_cross_host" != x"no"; then +- # Install a library built with a cross compiler in tooldir, not libdir. +- toolexecdir='$(exec_prefix)/$(target_alias)' +- toolexeclibdir='$(toolexecdir)/lib' +- else +- toolexecdir='$(libdir)/gcc-lib/$(target_alias)' +- toolexeclibdir='$(libdir)' +- fi ++ toolexecdir='$(libdir)/gcc-lib/$(target_alias)' ++ toolexeclibdir='$(libdir)' + multi_os_directory=`$CC -print-multi-os-directory` + case $multi_os_directory in + .) ;; # Avoid trailing /. +--- a/src/libobjc/configure.ac ++++ b/src/libobjc/configure.ac +@@ -116,15 +116,8 @@ + toolexeclibdir='$(toolexecdir)/$(gcc_version)$(MULTISUBDIR)' + ;; + no) +- if test -n "$with_cross_host" && +- test x"$with_cross_host" != x"no"; then +- # Install a library built with a cross compiler in tooldir, not libdir. +- toolexecdir='$(exec_prefix)/$(target_noncanonical)' +- toolexeclibdir='$(toolexecdir)/lib' +- else +- toolexecdir='$(libdir)/gcc-lib/$(target_noncanonical)' +- toolexeclibdir='$(libdir)' +- fi ++ toolexecdir='$(libdir)/gcc-lib/$(target_noncanonical)' ++ toolexeclibdir='$(libdir)' + multi_os_directory=`$CC -print-multi-os-directory` + case $multi_os_directory in + .) ;; # Avoid trailing /. +--- a/src/libquadmath/configure.ac ++++ b/src/libquadmath/configure.ac +@@ -93,15 +93,8 @@ + toolexeclibdir='$(toolexecdir)/$(gcc_version)$(MULTISUBDIR)' + ;; + no) +- if test -n "$with_cross_host" && +- test x"$with_cross_host" != x"no"; then +- # Install a library built with a cross compiler in tooldir, not libdir. +- toolexecdir='$(exec_prefix)/$(target_alias)' +- toolexeclibdir='$(toolexecdir)/lib' +- else +- toolexecdir='$(libdir)/gcc-lib/$(target_alias)' +- toolexeclibdir='$(libdir)' +- fi ++ toolexecdir='$(libdir)/gcc-lib/$(target_alias)' ++ toolexeclibdir='$(libdir)' + multi_os_directory=`$CC -print-multi-os-directory` + case $multi_os_directory in + .) ;; # Avoid trailing /. +--- a/src/libssp/configure.ac ++++ b/src/libssp/configure.ac +@@ -170,15 +170,8 @@ + toolexeclibdir='$(toolexecdir)/$(gcc_version)$(MULTISUBDIR)' + ;; + no) +- if test -n "$with_cross_host" && +- test x"$with_cross_host" != x"no"; then +- # Install a library built with a cross compiler in tooldir, not libdir. +- toolexecdir='$(exec_prefix)/$(target_alias)' +- toolexeclibdir='$(toolexecdir)/lib' +- else +- toolexecdir='$(libdir)/gcc-lib/$(target_alias)' +- toolexeclibdir='$(libdir)' +- fi ++ toolexecdir='$(libdir)/gcc-lib/$(target_alias)' ++ toolexeclibdir='$(libdir)' + multi_os_directory=`$CC -print-multi-os-directory` + case $multi_os_directory in + .) ;; # Avoid trailing /. +--- a/src/libstdc++-v3/acinclude.m4 ++++ b/src/libstdc++-v3/acinclude.m4 +@@ -804,14 +804,8 @@ + # Calculate glibcxx_toolexecdir, glibcxx_toolexeclibdir + # Install a library built with a cross compiler in tooldir, not libdir. + if test x"$glibcxx_toolexecdir" = x"no"; then +- if test -n "$with_cross_host" && +- test x"$with_cross_host" != x"no"; then +- glibcxx_toolexecdir='${exec_prefix}/${host_alias}' +- glibcxx_toolexeclibdir='${toolexecdir}/lib' +- else +- glibcxx_toolexecdir='${libdir}/gcc/${host_alias}' +- glibcxx_toolexeclibdir='${libdir}' +- fi ++ glibcxx_toolexecdir='${libdir}/gcc/${host_alias}' ++ glibcxx_toolexeclibdir='${libdir}' + multi_os_directory=`$CXX -print-multi-os-directory` + case $multi_os_directory in + .) ;; # Avoid trailing /. +--- a/src/zlib/configure.ac ++++ b/src/zlib/configure.ac +@@ -91,14 +91,9 @@ + + AC_CHECK_HEADERS(unistd.h) + +-if test -n "$with_cross_host" && +- test x"$with_cross_host" != x"no"; then +- toolexecdir='$(exec_prefix)/$(target_alias)' +- toolexeclibdir='$(toolexecdir)/lib' +-else +- toolexecdir='$(libdir)/gcc-lib/$(target_alias)' +- toolexeclibdir='$(libdir)' +-fi ++toolexecdir='$(libdir)/gcc-lib/$(target_alias)' ++toolexeclibdir='$(libdir)' ++ + if test "$GCC" = yes && $CC -print-multi-os-directory > /dev/null 2>&1; then + multiosdir=/`$CC -print-multi-os-directory` + case $multiosdir in diff -Nru gcc-4.7-4.7.2/debian/patches/cross-no-locale-include.diff gcc-4.7-4.7.3/debian/patches/cross-no-locale-include.diff --- gcc-4.7-4.7.2/debian/patches/cross-no-locale-include.diff 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/cross-no-locale-include.diff 2013-07-25 18:49:34.000000000 +0000 @@ -0,0 +1,17 @@ +# DP: Don't add /usr/local/include for cross compilers. Assume that +# DP: /usr/include is ready for multiarch, but not /usr/local/include. + +--- a/src/gcc/cppdefault.c ++++ b/src/gcc/cppdefault.c +@@ -66,8 +66,11 @@ + #ifdef LOCAL_INCLUDE_DIR + /* /usr/local/include comes before the fixincluded header files. */ + { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 2 }, ++#if 0 ++ /* Unsafe to assume that /usr/local/include is ready for multiarch. */ + { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 0 }, + #endif ++#endif + #ifdef PREFIX_INCLUDE_DIR + { PREFIX_INCLUDE_DIR, 0, 0, 1, 0, 0 }, + #endif diff -Nru gcc-4.7-4.7.2/debian/patches/g++-multiarch-incdir.diff gcc-4.7-4.7.3/debian/patches/g++-multiarch-incdir.diff --- gcc-4.7-4.7.2/debian/patches/g++-multiarch-incdir.diff 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/g++-multiarch-incdir.diff 2013-07-25 18:49:34.000000000 +0000 @@ -0,0 +1,118 @@ +# DP: Use /usr/include//c++/4.x as the include directory +# DP: for host dependent c++ header files. + +Index: b/src/libstdc++-v3/include/Makefile.am +=================================================================== +--- a/src/libstdc++-v3/include/Makefile.am ++++ b/src/libstdc++-v3/include/Makefile.am +@@ -823,7 +823,7 @@ + host_srcdir = ${glibcxx_srcdir}/$(OS_INC_SRCDIR) + default_host_alias = @default_host_alias@ + host_builddir = ./${default_host_alias}/bits +-host_installdir = ${gxx_include_dir}/${default_host_alias}$(MULTISUBDIR)/bits ++host_installdir = $(if $(shell $(CC) -print-multiarch),/usr/include/$(shell $(filter-out -m%,$(CC)) -print-multiarch)/c++/$(notdir ${gxx_include_dir})$(MULTISUBDIR)/bits,${gxx_include_dir}/${default_host_alias}$(MULTISUBDIR)/bits) + host_headers = \ + ${host_srcdir}/ctype_base.h \ + ${host_srcdir}/ctype_inline.h \ +Index: b/src/libstdc++-v3/include/Makefile.in +=================================================================== +--- a/src/libstdc++-v3/include/Makefile.in ++++ b/src/libstdc++-v3/include/Makefile.in +@@ -1068,7 +1068,7 @@ + host_srcdir = ${glibcxx_srcdir}/$(OS_INC_SRCDIR) + default_host_alias = @default_host_alias@ + host_builddir = ./${default_host_alias}/bits +-host_installdir = ${gxx_include_dir}/${default_host_alias}$(MULTISUBDIR)/bits ++host_installdir = $(if $(shell $(CC) -print-multiarch),/usr/include/$(shell $(filter-out -m%,$(CC)) -print-multiarch)/c++/$(notdir ${gxx_include_dir})$(MULTISUBDIR)/bits,${gxx_include_dir}/${default_host_alias}$(MULTISUBDIR)/bits) + host_headers = \ + ${host_srcdir}/ctype_base.h \ + ${host_srcdir}/ctype_inline.h \ +Index: b/src/gcc/Makefile.in +=================================================================== +--- a/src/gcc/Makefile.in ++++ b/src/gcc/Makefile.in +@@ -1118,6 +1118,7 @@ + "prefix=$(prefix)" \ + "local_prefix=$(local_prefix)" \ + "gxx_include_dir=$(gcc_gxx_include_dir)" \ ++ "gxx_tool_include_dir=$(gcc_gxx_tool_include_dir)" \ + "build_tooldir=$(build_tooldir)" \ + "gcc_tooldir=$(gcc_tooldir)" \ + "bindir=$(bindir)" \ +@@ -1546,6 +1547,14 @@ + include $(xmake_file) + endif + ++# Directory in which the compiler finds target-dependent g++ includes. ++ifneq ($(call if_multiarch,non-empty),) ++ gcc_gxx_tool_include_dir = /usr/include/$(MULTIARCH_DIRNAME)/c++/$(BASEVER_c) ++else ++ gcc_gxx_tool_include_dir = $(gcc_gxx_include_dir)/$(target_noncanonical) ++endif ++ ++ + # all-tree.def includes all the tree.def files. + all-tree.def: s-alltree; @true + s-alltree: Makefile +@@ -3978,7 +3987,7 @@ + -DFIXED_INCLUDE_DIR=\"$(libsubdir)/include-fixed\" \ + -DGPLUSPLUS_INCLUDE_DIR=\"$(gcc_gxx_include_dir)\" \ + -DGPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT=$(gcc_gxx_include_dir_add_sysroot) \ +- -DGPLUSPLUS_TOOL_INCLUDE_DIR=\"$(gcc_gxx_include_dir)/$(target_noncanonical)\" \ ++ -DGPLUSPLUS_TOOL_INCLUDE_DIR=\"$(gcc_gxx_tool_include_dir)\" \ + -DGPLUSPLUS_BACKWARD_INCLUDE_DIR=\"$(gcc_gxx_include_dir)/backward\" \ + -DLOCAL_INCLUDE_DIR=\"$(local_includedir)\" \ + -DCROSS_INCLUDE_DIR=\"$(CROSS_SYSTEM_HEADER_DIR)\" \ +Index: b/src/gcc/cppdefault.c +=================================================================== +--- a/src/gcc/cppdefault.c ++++ b/src/gcc/cppdefault.c +@@ -51,6 +51,8 @@ + /* Pick up GNU C++ target-dependent include files. */ + { GPLUSPLUS_TOOL_INCLUDE_DIR, "G++", 1, 1, + GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 1 }, ++ { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1, ++ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 2 }, + #endif + #ifdef GPLUSPLUS_BACKWARD_INCLUDE_DIR + /* Pick up GNU C++ backward and deprecated include files. */ +Index: b/src/gcc/incpath.c +=================================================================== +--- a/src/gcc/incpath.c ++++ b/src/gcc/incpath.c +@@ -156,7 +156,16 @@ + { + if (!imultiarch) + continue; +- str = concat (str, dir_separator_str, imultiarch, NULL); ++ if (p->cplusplus) ++ { ++ char *suffix = strstr (str, "/c++/"); ++ *suffix++ = '\0'; ++ suffix = xstrdup (suffix); ++ str = concat (str, dir_separator_str, imultiarch, ++ dir_separator_str, suffix, NULL); ++ } ++ else ++ str = concat (str, dir_separator_str, imultiarch, NULL); + } + add_path (str, SYSTEM, p->cxx_aware, false); + } +@@ -215,7 +224,16 @@ + { + if (!imultiarch) + continue; +- str = concat (str, dir_separator_str, imultiarch, NULL); ++ if (p->cplusplus) ++ { ++ char *suffix = strstr (str, "/c++/"); ++ *suffix++ = '\0'; ++ suffix = xstrdup (suffix); ++ str = concat (str, dir_separator_str, imultiarch, ++ dir_separator_str, suffix, NULL); ++ } ++ else ++ str = concat (str, dir_separator_str, imultiarch, NULL); + } + + add_path (str, SYSTEM, p->cxx_aware, false); diff -Nru gcc-4.7-4.7.2/debian/patches/gcc-as-needed.diff gcc-4.7-4.7.3/debian/patches/gcc-as-needed.diff --- gcc-4.7-4.7.2/debian/patches/gcc-as-needed.diff 2013-07-25 18:49:32.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/gcc-as-needed.diff 2013-07-25 18:49:34.000000000 +0000 @@ -1,49 +1,134 @@ # DP: On linux targets pass --as-needed by default to the linker. ---- a/src/gcc/config/rs6000/sysv4.h -+++ b/src/gcc/config/rs6000/sysv4.h -@@ -836,7 +836,7 @@ - - #if defined(HAVE_LD_EH_FRAME_HDR) - # undef LINK_EH_SPEC --# define LINK_EH_SPEC "--no-add-needed %{!static:--eh-frame-hdr} " -+# define LINK_EH_SPEC "--no-add-needed --as-needed %{!static:--eh-frame-hdr} " - #endif - - #define CPP_OS_LINUX_SPEC "-D__unix__ -D__gnu_linux__ -D__linux__ \ ---- a/src/gcc/config/gnu-user.h -+++ b/src/gcc/config/gnu-user.h -@@ -82,9 +82,9 @@ - #define LIB_SPEC GNU_USER_TARGET_LIB_SPEC - - #if defined(HAVE_LD_EH_FRAME_HDR) --#define LINK_EH_SPEC "--no-add-needed %{!static:--eh-frame-hdr} " -+#define LINK_EH_SPEC "--no-add-needed --as-needed %{!static:--eh-frame-hdr} " - #else --#define LINK_EH_SPEC "--no-add-needed " -+#define LINK_EH_SPEC "--no-add-needed --as-needed " - #endif - - #undef LINK_GCC_C_SEQUENCE_SPEC ---- a/src/gcc/config/alpha/elf.h -+++ b/src/gcc/config/alpha/elf.h -@@ -438,7 +438,7 @@ - I imagine that other systems will catch up. In the meantime, it - doesn't harm to make sure that the data exists to be used later. */ - #if defined(HAVE_LD_EH_FRAME_HDR) --#define LINK_EH_SPEC "--no-add-needed %{!static:--eh-frame-hdr} " -+#define LINK_EH_SPEC "--no-add-needed --as-needed %{!static:--eh-frame-hdr} " - #endif - - /* A C statement (sans semicolon) to output to the stdio stream STREAM +Index: b/src/gcc/config/aarch64/aarch64-linux.h +=================================================================== +--- a/src/gcc/config/aarch64/aarch64-linux.h ++++ b/src/gcc/config/aarch64/aarch64-linux.h +@@ -33,6 +33,7 @@ + + #define LINUX_TARGET_LINK_SPEC "%{h*} \ + --hash-style=gnu \ ++ --as-needed \ + %{static:-Bstatic} \ + %{shared:-shared} \ + %{symbolic:-Bsymbolic} \ +Index: b/src/gcc/config/ia64/linux.h +=================================================================== --- a/src/gcc/config/ia64/linux.h +++ b/src/gcc/config/ia64/linux.h -@@ -82,7 +82,7 @@ - Signalize that because we have fde-glibc, we don't need all C shared libs - linked against -lgcc_s. */ - #undef LINK_EH_SPEC --#define LINK_EH_SPEC "--no-add-needed " -+#define LINK_EH_SPEC "--no-add-needed --as-needed " +@@ -59,7 +59,7 @@ + #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-ia64.so.2" - #define MD_UNWIND_SUPPORT "config/ia64/linux-unwind.h" + #undef LINK_SPEC +-#define LINK_SPEC " --hash-style=gnu \ ++#define LINK_SPEC " --hash-style=gnu --as-needed \ + %{shared:-shared} \ + %{!shared: \ + %{!static: \ +Index: b/src/gcc/config/sparc/linux.h +=================================================================== +--- a/src/gcc/config/sparc/linux.h ++++ b/src/gcc/config/sparc/linux.h +@@ -87,7 +87,7 @@ + #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2" + + #undef LINK_SPEC +-#define LINK_SPEC "-m elf32_sparc --hash-style=gnu -Y P,/usr/lib %{shared:-shared} \ ++#define LINK_SPEC "-m elf32_sparc --hash-style=gnu --as-needed -Y P,/usr/lib %{shared:-shared} \ + %{!mno-relax:%{!r:-relax}} \ + %{!shared: \ + %{!static: \ +Index: b/src/gcc/config/s390/linux.h +=================================================================== +--- a/src/gcc/config/s390/linux.h ++++ b/src/gcc/config/s390/linux.h +@@ -66,7 +66,7 @@ + + #undef LINK_SPEC + #define LINK_SPEC \ +- "%{m31:-m elf_s390}%{m64:-m elf64_s390} --hash-style=gnu \ ++ "%{m31:-m elf_s390}%{m64:-m elf64_s390} --hash-style=gnu --as-needed \ + %{shared:-shared} \ + %{!shared: \ + %{static:-static} \ +Index: b/src/gcc/config/rs6000/linux64.h +=================================================================== +--- a/src/gcc/config/rs6000/linux64.h ++++ b/src/gcc/config/rs6000/linux64.h +@@ -375,11 +375,11 @@ + CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER64, UCLIBC_DYNAMIC_LINKER64) + + +-#define LINK_OS_LINUX_SPEC32 "-m elf32ppclinux --hash-style=gnu %{!shared: %{!static: \ ++#define LINK_OS_LINUX_SPEC32 "-m elf32ppclinux --hash-style=gnu --as-needed %{!shared: %{!static: \ + %{rdynamic:-export-dynamic} \ + -dynamic-linker " GNU_USER_DYNAMIC_LINKER32 "}}" + +-#define LINK_OS_LINUX_SPEC64 "-m elf64ppc --hash-style=gnu %{!shared: %{!static: \ ++#define LINK_OS_LINUX_SPEC64 "-m elf64ppc --hash-style=gnu --as-needed %{!shared: %{!static: \ + %{rdynamic:-export-dynamic} \ + -dynamic-linker " GNU_USER_DYNAMIC_LINKER64 "}}" + +Index: b/src/gcc/config/rs6000/sysv4.h +=================================================================== +--- a/src/gcc/config/rs6000/sysv4.h ++++ b/src/gcc/config/rs6000/sysv4.h +@@ -814,7 +814,7 @@ + #define GNU_USER_DYNAMIC_LINKER \ + CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER) + +-#define LINK_OS_LINUX_SPEC "-m elf32ppclinux --hash-style=gnu %{!shared: %{!static: \ ++#define LINK_OS_LINUX_SPEC "-m elf32ppclinux --hash-style=gnu --as-needed %{!shared: %{!static: \ + %{rdynamic:-export-dynamic} \ + -dynamic-linker " GNU_USER_DYNAMIC_LINKER "}}" + +Index: b/src/gcc/config/i386/gnu-user64.h +=================================================================== +--- a/src/gcc/config/i386/gnu-user64.h ++++ b/src/gcc/config/i386/gnu-user64.h +@@ -82,6 +82,7 @@ + %{" SPEC_32 ":-m " GNU_USER_LINK_EMULATION32 "} \ + %{" SPEC_X32 ":-m " GNU_USER_LINK_EMULATIONX32 "} \ + --hash-style=gnu \ ++ --as-needed \ + %{shared:-shared} \ + %{!shared: \ + %{!static: \ +Index: b/src/gcc/config/i386/gnu-user.h +=================================================================== +--- a/src/gcc/config/i386/gnu-user.h ++++ b/src/gcc/config/i386/gnu-user.h +@@ -98,7 +98,7 @@ + { "dynamic_linker", GNU_USER_DYNAMIC_LINKER } + + #undef LINK_SPEC +-#define LINK_SPEC "-m %(link_emulation) --hash-style=gnu %{shared:-shared} \ ++#define LINK_SPEC "-m %(link_emulation) --hash-style=gnu --as-needed %{shared:-shared} \ + %{!shared: \ + %{!static: \ + %{rdynamic:-export-dynamic} \ +Index: b/src/gcc/config/alpha/linux-elf.h +=================================================================== +--- a/src/gcc/config/alpha/linux-elf.h ++++ b/src/gcc/config/alpha/linux-elf.h +@@ -38,7 +38,7 @@ + + #define ELF_DYNAMIC_LINKER GNU_USER_DYNAMIC_LINKER + +-#define LINK_SPEC "-m elf64alpha --hash-style=gnu %{G*} %{relax:-relax} \ ++#define LINK_SPEC "-m elf64alpha --hash-style=gnu --as-needed %{G*} %{relax:-relax} \ + %{O*:-O3} %{!O*:-O1} \ + %{shared:-shared} \ + %{!shared: \ +Index: b/src/gcc/config/arm/linux-elf.h +=================================================================== +--- a/src/gcc/config/arm/linux-elf.h ++++ b/src/gcc/config/arm/linux-elf.h +@@ -69,6 +69,7 @@ + -dynamic-linker " GNU_USER_DYNAMIC_LINKER " \ + -X \ + --hash-style=gnu \ ++ --as-needed \ + %{mbig-endian:-EB} %{mlittle-endian:-EL}" \ + SUBTARGET_EXTRA_LINK_SPEC diff -Nru gcc-4.7-4.7.2/debian/patches/gcc-base-version.diff gcc-4.7-4.7.3/debian/patches/gcc-base-version.diff --- gcc-4.7-4.7.2/debian/patches/gcc-base-version.diff 2013-07-25 18:49:32.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/gcc-base-version.diff 2013-07-25 18:49:34.000000000 +0000 @@ -5,19 +5,19 @@ --- a/src/gcc/BASE-VER +++ b/src/gcc/BASE-VER @@ -1 +1 @@ --4.7.2 +-4.7.3 +4.7 Index: b/src/gcc/FULL-VER =================================================================== --- /dev/null +++ b/src/gcc/FULL-VER @@ -0,0 +1 @@ -+4.7.2 ++4.7.3 Index: b/src/gcc/Makefile.in =================================================================== --- a/src/gcc/Makefile.in +++ b/src/gcc/Makefile.in -@@ -792,11 +792,13 @@ +@@ -808,11 +808,13 @@ TM_H = $(GTM_H) insn-flags.h $(OPTIONS_H) # Variables for version information. @@ -32,7 +32,7 @@ BASEVER_c := $(shell cat $(BASEVER)) DEVPHASE_c := $(shell cat $(DEVPHASE)) DATESTAMP_c := $(shell cat $(DATESTAMP)) -@@ -815,7 +817,7 @@ +@@ -831,7 +833,7 @@ # development phase collapsed to the empty string in release mode # (i.e. if DEVPHASE_c is empty). The space immediately after the # comma in the $(if ...) constructs is significant - do not remove it. @@ -41,7 +41,7 @@ DEVPHASE_s := "\"$(if $(DEVPHASE_c), ($(DEVPHASE_c)))\"" DATESTAMP_s := "\"$(if $(DEVPHASE_c), $(DATESTAMP_c))\"" PKGVERSION_s:= "\"@PKGVERSION@\"" -@@ -2066,9 +2068,9 @@ +@@ -2083,9 +2085,9 @@ intl.h prefix.h coretypes.h $(TM_H) cppdefault.h $(TARGET_H) \ $(MACHMODE_H) @@ -53,7 +53,7 @@ # Language-independent files. -@@ -2146,11 +2148,11 @@ +@@ -2163,11 +2165,11 @@ dumpvers: dumpvers.c @@ -67,7 +67,7 @@ gtype-desc.o: gtype-desc.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ $(HASHTAB_H) $(SPLAY_TREE_H) $(OBSTACK_H) $(BITMAP_H) \ -@@ -2736,10 +2738,10 @@ +@@ -2753,10 +2755,10 @@ coretypes.h $(INPUT_H) $(TM_H) $(COMMON_TARGET_H) common/common-targhooks.h bversion.h: s-bversion; @true @@ -82,7 +82,7 @@ echo "#define BUILDING_GCC_VERSION (BUILDING_GCC_MAJOR * 1000 + BUILDING_GCC_MINOR)" >> bversion.h $(STAMP) s-bversion -@@ -3791,9 +3793,9 @@ +@@ -3808,9 +3810,9 @@ ## build/version.o is compiled by the $(COMPILER_FOR_BUILD) but needs ## several C macro definitions, just like version.o build/version.o: version.c version.h \ @@ -94,7 +94,7 @@ -DREVISION=$(REVISION_s) \ -DDEVPHASE=$(DEVPHASE_s) -DPKGVERSION=$(PKGVERSION_s) \ -DBUGURL=$(BUGURL_s) -o $@ $< -@@ -3968,7 +3970,7 @@ +@@ -3986,7 +3988,7 @@ -DSTANDARD_EXEC_PREFIX=\"$(libdir)/gcc/\" \ @TARGET_SYSTEM_ROOT_DEFINE@ @@ -103,7 +103,7 @@ cppbuiltin.o: cppbuiltin.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ $(TREE_H) cppbuiltin.h Makefile -@@ -3988,8 +3990,8 @@ +@@ -4006,8 +4008,8 @@ build/gcov-iov.o -o $@ gcov-iov.h: s-iov @@ -114,7 +114,7 @@ > tmp-gcov-iov.h $(SHELL) $(srcdir)/../move-if-change tmp-gcov-iov.h gcov-iov.h $(STAMP) s-iov -@@ -4229,8 +4231,8 @@ +@@ -4272,8 +4274,8 @@ TEXI_CPPINT_FILES = cppinternals.texi gcc-common.texi gcc-vers.texi # gcc-vers.texi is generated from the version files. @@ -125,7 +125,7 @@ if [ "$(DEVPHASE_c)" = "experimental" ]; \ then echo "@set DEVELOPMENT"; \ else echo "@clear DEVELOPMENT"; \ -@@ -4624,9 +4626,11 @@ +@@ -4647,9 +4649,11 @@ install-driver: installdirs xgcc$(exeext) -rm -f $(DESTDIR)$(bindir)/$(GCC_INSTALL_NAME)$(exeext) -$(INSTALL_PROGRAM) xgcc$(exeext) $(DESTDIR)$(bindir)/$(GCC_INSTALL_NAME)$(exeext) @@ -176,6 +176,8 @@ ifeq ($(decimal_float),yes) ifeq ($(enable_decimal_float),bid) +Index: b/src/libjava/testsuite/lib/libjava.exp +=================================================================== --- a/src/libjava/testsuite/lib/libjava.exp +++ b/src/libjava/testsuite/lib/libjava.exp @@ -177,7 +177,7 @@ diff -Nru gcc-4.7-4.7.2/debian/patches/gcc-cloog-dl.diff gcc-4.7-4.7.3/debian/patches/gcc-cloog-dl.diff --- gcc-4.7-4.7.2/debian/patches/gcc-cloog-dl.diff 2013-07-25 18:49:32.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/gcc-cloog-dl.diff 2013-07-25 18:49:34.000000000 +0000 @@ -1,7 +1,7 @@ # DP: Link against -ldl instead of -lcloog -lppl. Exit with an error when using # DP: the Graphite loop transformation infrastructure without having the -# DP: libcloog-ppl0 package installed. Packages using these optimizations -# DP: should build-depend on libcloog-ppl0. +# DP: libcloog-ppl[01] package installed. Packages using these optimizations +# DP: should build-depend on libcloog-ppl1 | libcloog-ppl0. 2011-01-04 Jakub Jelinek @@ -18,9 +18,11 @@ stmt_for argument to stmt_fora. * graphite-poly.h: Include graphite-cloog-util.h. ---- a/src/gcc/Makefile.in.jj 2011-01-03 13:44:14.163900902 +0100 -+++ b/src/gcc/Makefile.in 2011-01-04 17:48:53.588775911 +0100 -@@ -962,6 +962,8 @@ GCC_PLUGIN_H = gcc-plugin.h highlev-plug +Index: b/src/gcc/Makefile.in +=================================================================== +--- a/src/gcc/Makefile.in ++++ b/src/gcc/Makefile.in +@@ -980,6 +980,8 @@ PLUGIN_H = plugin.h $(GCC_PLUGIN_H) PLUGIN_VERSION_H = plugin-version.h configargs.h LIBFUNCS_H = libfuncs.h $(HASHTAB_H) @@ -29,7 +31,7 @@ # # Now figure out from those variables how to compile and link. -@@ -1016,7 +1018,7 @@ BUILD_LIBDEPS= $(BUILD_LIBIBERTY) +@@ -1034,7 +1036,7 @@ # and the system's installed libraries. LIBS = @LIBS@ libcommon.a $(CPPLIB) $(LIBINTL) $(LIBICONV) $(LIBIBERTY) \ $(LIBDECNUMBER) $(HOST_LIBS) @@ -38,7 +40,7 @@ $(ZLIB) # Any system libraries needed just for GNAT. SYSLIBS = @GNAT_LIBEXC@ -@@ -2602,40 +2604,40 @@ sese.o : sese.c sese.h $(CONFIG_H) $(SYS +@@ -2621,40 +2623,40 @@ $(TREE_FLOW_H) $(CFGLOOP_H) $(TREE_DATA_REF_H) tree-pass.h value-prof.h graphite.o : graphite.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(DIAGNOSTIC_CORE_H) \ $(TREE_FLOW_H) $(TREE_DUMP_H) $(CFGLOOP_H) $(TREE_DATA_REF_H) sese.h \ @@ -93,7 +95,7 @@ graphite-sese-to-poly.h tree-vect-loop.o: tree-vect-loop.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \ $(TM_H) $(GGC_H) $(TREE_H) $(BASIC_BLOCK_H) $(DIAGNOSTIC_H) $(TREE_FLOW_H) \ -@@ -3454,6 +3456,15 @@ $(common_out_object_file): $(common_out_ +@@ -3473,6 +3475,15 @@ $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) \ $< $(OUTPUT_OPTION) @@ -109,9 +111,11 @@ # Build auxiliary files that support ecoff format. mips-tfile: mips-tfile.o $(LIBDEPS) $(LINKER) $(LINKERFLAGS) $(LDFLAGS) -o $@ \ ---- a/src/gcc/graphite-cloog-compat.h.jj 2011-01-03 12:53:05.000000000 +0100 -+++ b/src/gcc/graphite-cloog-compat.h 2011-01-04 17:34:09.857757544 +0100 -@@ -272,4 +272,279 @@ static inline int cloog_matrix_nrows (Cl +Index: b/src/gcc/graphite-cloog-compat.h +=================================================================== +--- a/src/gcc/graphite-cloog-compat.h ++++ b/src/gcc/graphite-cloog-compat.h +@@ -272,4 +272,279 @@ return m->NbRows; } #endif /* CLOOG_ORG */ @@ -391,9 +395,11 @@ + + #endif /* GRAPHITE_CLOOG_COMPAT_H */ ---- a/src/gcc/graphite.c.jj 2011-01-03 12:53:05.194056513 +0100 -+++ b/src/gcc/graphite.c 2011-01-04 16:18:32.385007767 +0100 -@@ -56,6 +56,35 @@ along with GCC; see the file COPYING3. +Index: b/src/gcc/graphite.c +=================================================================== +--- a/src/gcc/graphite.c ++++ b/src/gcc/graphite.c +@@ -56,6 +56,37 @@ CloogState *cloog_state; @@ -406,7 +412,9 @@ + + if (cloog_pointers__.inited) + return cloog_pointers__.h != NULL; -+ h = dlopen ("libcloog-debian.so.0", RTLD_LAZY); ++ h = dlopen ("libcloog-ppl.so.1", RTLD_LAZY); ++ if (!h) ++ h = dlopen ("libcloog-ppl.so.0", RTLD_LAZY); + cloog_pointers__.h = h; + if (h == NULL) + return false; @@ -429,22 +437,24 @@ /* Print global statistics to FILE. */ static void -@@ -201,6 +230,12 @@ graphite_initialize (void) +@@ -201,6 +232,12 @@ return false; } + if (!init_cloog_pointers ()) + { -+ sorry ("Graphite loop optimizations can only be used if the libcloog-ppl0 package is installed"); ++ sorry ("Graphite loop optimizations can only be used if the libcloog-ppl1 or libcloog-ppl0 package is installed"); + return false; + } + scev_reset (); recompute_all_dominators (); initialize_original_copy_tables (); ---- a/src/gcc/graphite-clast-to-gimple.c.jj 2011-01-03 12:53:05.000000000 +0100 -+++ b/src/gcc/graphite-clast-to-gimple.c 2011-01-04 16:29:55.738007463 +0100 -@@ -836,7 +836,7 @@ clast_get_body_of_loop (struct clast_stm +Index: b/src/gcc/graphite-clast-to-gimple.c +=================================================================== +--- a/src/gcc/graphite-clast-to-gimple.c ++++ b/src/gcc/graphite-clast-to-gimple.c +@@ -836,7 +836,7 @@ from STMT_FOR. */ static tree @@ -453,7 +463,7 @@ { mpz_t bound_one, bound_two; tree lb_type, ub_type; -@@ -844,8 +844,8 @@ type_for_clast_for (struct clast_for *st +@@ -844,8 +844,8 @@ mpz_init (bound_one); mpz_init (bound_two); @@ -464,9 +474,11 @@ mpz_clear (bound_one); mpz_clear (bound_two); ---- a/src/gcc/graphite-poly.h.jj 2011-01-03 12:53:05.000000000 +0100 -+++ b/src/gcc/graphite-poly.h 2011-01-04 17:35:53.308788629 +0100 -@@ -22,6 +22,8 @@ along with GCC; see the file COPYING3. +Index: b/src/gcc/graphite-poly.h +=================================================================== +--- a/src/gcc/graphite-poly.h ++++ b/src/gcc/graphite-poly.h +@@ -22,6 +22,8 @@ #ifndef GCC_GRAPHITE_POLY_H #define GCC_GRAPHITE_POLY_H diff -Nru gcc-4.7-4.7.2/debian/patches/gcc-d-lang.diff gcc-4.7-4.7.3/debian/patches/gcc-d-lang.diff --- gcc-4.7-4.7.2/debian/patches/gcc-d-lang.diff 2013-07-25 18:49:32.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/gcc-d-lang.diff 2013-07-25 18:49:34.000000000 +0000 @@ -1,7 +1,9 @@ # DP: Add D options and specs for the gcc driver. ---- /dev/null 2011-07-23 10:07:44.175344374 +0100 -+++ b/src/gcc/d/lang-specs.h 2011-07-09 23:51:52.807002983 +0100 +Index: b/src/gcc/d/lang-specs.h +=================================================================== +--- /dev/null ++++ b/src/gcc/d/lang-specs.h @@ -0,0 +1,53 @@ +/* GDC -- D front-end for GCC + Copyright (C) 2004 David Friedman @@ -56,8 +58,10 @@ + %{M} %{MM} %{!fsyntax-only:%(invoke_as)}}", D_D_SPEC, 1, 0 }, +#endif + ---- /dev/null 2011-07-23 10:07:44.175344374 +0100 -+++ b/src/gcc/d/lang.opt 2011-07-24 15:48:56.848040870 +0100 +Index: b/src/gcc/d/lang.opt +=================================================================== +--- /dev/null ++++ b/src/gcc/d/lang.opt @@ -0,0 +1,215 @@ +; GDC -- D front-end for GCC +; Copyright (C) 2004 David Friedman @@ -274,9 +278,11 @@ + +static_libphobos +Driver ---- a/src/gcc/gcc.c 2011-02-23 02:04:43.000000000 +0000 -+++ b/src/gcc/gcc.c 2011-07-12 21:55:05.805144355 +0100 -@@ -373,6 +373,7 @@ or with constant text in a single argume +Index: b/src/gcc/gcc.c +=================================================================== +--- a/src/gcc/gcc.c ++++ b/src/gcc/gcc.c +@@ -375,6 +375,7 @@ assembler has done its job. %D Dump out a -L option for each directory in startfile_prefixes. If multilib_dir is set, extra entries are generated with it affixed. @@ -284,7 +290,7 @@ %l process LINK_SPEC as a spec. %L process LIB_SPEC as a spec. %G process LIBGCC_SPEC as a spec. -@@ -5095,6 +5096,17 @@ do_spec_1 (const char *spec, int inswitc +@@ -5140,6 +5141,17 @@ return value; break; diff -Nru gcc-4.7-4.7.2/debian/patches/gcc-default-fortify-source.diff gcc-4.7-4.7.3/debian/patches/gcc-default-fortify-source.diff --- gcc-4.7-4.7.2/debian/patches/gcc-default-fortify-source.diff 2013-07-25 18:49:32.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/gcc-default-fortify-source.diff 2013-07-25 18:49:34.000000000 +0000 @@ -1,4 +1,5 @@ -# DP: Turn on -D_FORTIFY_SOURCE=2 by default for C, C++, ObjC, ObjC++. +# DP: Turn on -D_FORTIFY_SOURCE=2 by default for C, C++, ObjC, ObjC++, +# DP: if the optimization level is > 0 --- gcc/doc/invoke.texi | 6 ++++++ @@ -22,12 +23,13 @@ Optimize yet more. @option{-O3} turns on all optimizations specified --- a/src/gcc/c-family/c-cppbuiltin.c +++ b/src/gcc/c-family/c-cppbuiltin.c -@@ -731,6 +731,9 @@ +@@ -731,6 +731,10 @@ builtin_define_with_value ("__REGISTER_PREFIX__", REGISTER_PREFIX, 0); builtin_define_with_value ("__USER_LABEL_PREFIX__", user_label_prefix, 0); -+ /* Fortify Source enabled by default */ -+ builtin_define_with_int_value ("_FORTIFY_SOURCE", 2); ++ /* Fortify Source enabled by default for optimization levels > 0 */ ++ if (optimize) ++ builtin_define_with_int_value ("_FORTIFY_SOURCE", 2); + /* Misc. */ if (flag_gnu89_inline) diff -Nru gcc-4.7-4.7.2/debian/patches/gcc-default-relro.diff gcc-4.7-4.7.3/debian/patches/gcc-default-relro.diff --- gcc-4.7-4.7.2/debian/patches/gcc-default-relro.diff 2013-07-25 18:49:32.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/gcc-default-relro.diff 2013-07-25 18:49:34.000000000 +0000 @@ -19,11 +19,11 @@ Pretend the symbol @var{symbol} is undefined, to force linking of --- a/src/gcc/gcc.c +++ b/src/gcc/gcc.c -@@ -661,6 +661,7 @@ - }"PLUGIN_COND_CLOSE" \ - %{flto|flto=*:%= MIN_FATAL_STATUS) { @@ -60,7 +62,7 @@ if (WEXITSTATUS (status) > greatest_status) greatest_status = WEXITSTATUS (status); ret_code = -1; -@@ -2748,6 +2763,9 @@ +@@ -2808,6 +2821,9 @@ } } @@ -70,7 +72,7 @@ return ret_code; } } -@@ -5874,6 +5892,227 @@ +@@ -5919,6 +5935,227 @@ switches[switchnum].validated = 1; } @@ -298,6 +300,8 @@ /* Search for a file named NAME trying various prefixes including the user's -B prefix and some standard ones. Return the absolute file name found. If nothing is found, return NAME. */ +Index: b/src/gcc/diagnostic.c +=================================================================== --- a/src/gcc/diagnostic.c +++ b/src/gcc/diagnostic.c @@ -247,7 +247,7 @@ diff -Nru gcc-4.7-4.7.2/debian/patches/gcc-linaro-doc.diff gcc-4.7-4.7.3/debian/patches/gcc-linaro-doc.diff --- gcc-4.7-4.7.2/debian/patches/gcc-linaro-doc.diff 2013-07-25 18:49:32.000000000 +0000 +++ gcc-4.7-4.7.3/debian/patches/gcc-linaro-doc.diff 2013-07-25 18:49:34.000000000 +0000 @@ -1,15 +1,38 @@ -# DP: Changes for the Linaro 4.7-2012.09 release (documentation). +# DP: Changes for the Linaro 4.7-2013.04 release (documentation). +--- a/src/gcc/doc/extend.texi ++++ b/src/gcc/doc/extend.texi +@@ -8575,12 +8575,17 @@ + are @code{long double}. + @end deftypefn + +-@deftypefn {Built-in Function} int32_t __builtin_bswap32 (int32_t x) ++@deftypefn {Built-in Function} int16_t __builtin_bswap16 (int16_t x) + Returns @var{x} with the order of the bytes reversed; for example, +-@code{0xaabbccdd} becomes @code{0xddccbbaa}. Byte here always means ++@code{0xaabb} becomes @code{0xbbaa}. Byte here always means + exactly 8 bits. + @end deftypefn + ++@deftypefn {Built-in Function} int32_t __builtin_bswap32 (int32_t x) ++Similar to @code{__builtin_bswap16}, except the argument and return types ++are 32-bit. ++@end deftypefn ++ + @deftypefn {Built-in Function} int64_t __builtin_bswap64 (int64_t x) + Similar to @code{__builtin_bswap32}, except the argument and return types + are 64-bit. +@@ -13466,7 +13471,6 @@ + double __builtin_recipdiv (double, double); + double __builtin_rsqrt (double); + long __builtin_bpermd (long, long); +-int __builtin_bswap16 (int); + @end smallexample + + The @code{vec_rsqrt}, @code{__builtin_rsqrt}, and --- a/src/gcc/doc/fragments.texi +++ b/src/gcc/doc/fragments.texi -@@ -1,5 +1,5 @@ - @c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, --@c 1999, 2000, 2001, 2003, 2004, 2005, 2008, 2011 -+@c 1999, 2000, 2001, 2003, 2004, 2005, 2008, 2011, 2012 - @c Free Software Foundation, Inc. - @c This is part of the GCC manual. - @c For copying conditions, see the file gcc.texi. -@@ -121,6 +121,29 @@ +@@ -127,6 +127,29 @@ *mthumb/*mhard-float* @end smallexample @@ -39,33 +62,35 @@ @findex MULTILIB_EXTRA_OPTS @item MULTILIB_EXTRA_OPTS Sometimes it is desirable that when building multiple versions of ---- a/src/gcc/doc/fsf-funding.7 -+++ b/src/gcc/doc/fsf-funding.7 -@@ -1,4 +1,4 @@ --.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) -+.\" Automatically generated by Pod::Man 2.22 (Pod::Simple 3.07) - .\" - .\" Standard preamble: - .\" ======================================================================== ---- a/src/gcc/doc/gfdl.7 -+++ b/src/gcc/doc/gfdl.7 -@@ -1,4 +1,4 @@ --.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) -+.\" Automatically generated by Pod::Man 2.22 (Pod::Simple 3.07) - .\" - .\" Standard preamble: - .\" ======================================================================== ---- a/src/gcc/doc/gpl.7 -+++ b/src/gcc/doc/gpl.7 -@@ -1,4 +1,4 @@ --.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) -+.\" Automatically generated by Pod::Man 2.22 (Pod::Simple 3.07) - .\" - .\" Standard preamble: - .\" ======================================================================== +--- a/src/gcc/doc/install.texi ++++ b/src/gcc/doc/install.texi +@@ -1047,6 +1047,15 @@ + conventions, etc.@: should not be built. The default is to build a + predefined set of them. + ++@item --enable-multiarch ++Specify whether to enable or disable multiarch support. The default is ++to check for glibc start files in a multiarch location, and enable it ++if the files are found. The auto detection is enabled for native builds, ++and for cross builds configured with @option{--with-sysroot}, and without ++@option{--with-native-system-header-dir}. ++More documentation about multiarch can be found at ++@uref{http://wiki.debian.org/Multiarch}. ++ + Some targets provide finer-grained control over which multilibs are built + (e.g., @option{--disable-softfloat}): + @table @code --- a/src/gcc/doc/invoke.texi +++ b/src/gcc/doc/invoke.texi -@@ -409,7 +409,8 @@ +@@ -403,13 +403,15 @@ + -fsplit-ivs-in-unroller -fsplit-wide-types -fstack-protector @gol + -fstack-protector-all -fstrict-aliasing -fstrict-overflow @gol + -fthread-jumps -ftracer -ftree-bit-ccp @gol +--ftree-builtin-call-dce -ftree-ccp -ftree-ch -ftree-copy-prop @gol ++-ftree-builtin-call-dce -ftree-ccp -ftree-ch @gol ++-ftree-coalesce-inline-vars -ftree-coalesce-vars -ftree-copy-prop @gol + -ftree-copyrename -ftree-dce -ftree-dominator-opts -ftree-dse @gol + -ftree-forwprop -ftree-fre -ftree-loop-if-convert @gol -ftree-loop-if-convert-stores -ftree-loop-im @gol -ftree-phiprop -ftree-loop-distribution -ftree-loop-distribute-patterns @gol -ftree-loop-ivcanon -ftree-loop-linear -ftree-loop-optimize @gol @@ -75,7 +100,33 @@ -ftree-sink -ftree-sra -ftree-switch-conversion -ftree-tail-merge @gol -ftree-ter -ftree-vect-loop-version -ftree-vectorize -ftree-vrp @gol -funit-at-a-time -funroll-all-loops -funroll-loops @gol -@@ -6233,8 +6234,8 @@ +@@ -460,6 +462,15 @@ + @c Try and put the significant identifier (CPU or system) first, + @c so users have a clue at guessing where the ones they want will be. + ++@emph{AArch64 Options} ++@gccoptlist{-mbig-endian -mlittle-endian @gol ++-mgeneral-regs-only @gol ++-mcmodel=tiny -mcmodel=small -mcmodel=large @gol ++-mstrict-align @gol ++-momit-leaf-frame-pointer -mno-omit-leaf-frame-pointer @gol ++-mtls-dialect=desc -mtls-dialect=traditional @gol ++-march=@var{name} -mcpu=@var{name} -mtune=@var{name}} ++ + @emph{Adapteva Epiphany Options} + @gccoptlist{-mhalf-reg-file -mprefer-short-insn-regs @gol + -mbranch-cost=@var{num} -mcmove -mnops=@var{num} -msoft-cmpsf @gol +@@ -494,7 +505,8 @@ + -mtp=@var{name} -mtls-dialect=@var{dialect} @gol + -mword-relocations @gol + -mfix-cortex-m3-ldrd @gol +--munaligned-access} ++-munaligned-access @gol ++-mneon-for-64bits} + + @emph{AVR Options} + @gccoptlist{-mmcu=@var{mcu} -maccumulate-args -mbranch-cost=@var{cost} @gol +@@ -6237,8 +6249,8 @@ Optimize yet more. @option{-O3} turns on all optimizations specified by @option{-O2} and also turns on the @option{-finline-functions}, @option{-funswitch-loops}, @option{-fpredictive-commoning}, @@ -86,7 +137,7 @@ @item -O0 @opindex O0 -@@ -7029,6 +7030,11 @@ +@@ -7033,6 +7045,11 @@ Perform partial redundancy elimination (PRE) on trees. This flag is enabled by default at @option{-O2} and @option{-O3}. @@ -98,19943 +149,379 @@ @item -ftree-forwprop @opindex ftree-forwprop Perform forward propagation on trees. This flag is enabled by default ---- a/src/gcc/doc/invoke.texi.orig -+++ b/src/gcc/doc/invoke.texi.orig -@@ -0,0 +1,19937 @@ -+@c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, -+@c 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012 -+@c Free Software Foundation, Inc. -+@c This is part of the GCC manual. -+@c For copying conditions, see the file gcc.texi. -+ -+@ignore -+@c man begin INCLUDE -+@include gcc-vers.texi -+@c man end -+ -+@c man begin COPYRIGHT -+Copyright @copyright{} 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, -+1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, -+2012 -+Free Software Foundation, Inc. -+ -+Permission is granted to copy, distribute and/or modify this document -+under the terms of the GNU Free Documentation License, Version 1.3 or -+any later version published by the Free Software Foundation; with the -+Invariant Sections being ``GNU General Public License'' and ``Funding -+Free Software'', the Front-Cover texts being (a) (see below), and with -+the Back-Cover Texts being (b) (see below). A copy of the license is -+included in the gfdl(7) man page. -+ -+(a) The FSF's Front-Cover Text is: -+ -+ A GNU Manual -+ -+(b) The FSF's Back-Cover Text is: -+ -+ You have freedom to copy and modify this GNU Manual, like GNU -+ software. Copies published by the Free Software Foundation raise -+ funds for GNU development. -+@c man end -+@c Set file name and title for the man page. -+@setfilename gcc -+@settitle GNU project C and C++ compiler -+@c man begin SYNOPSIS -+gcc [@option{-c}|@option{-S}|@option{-E}] [@option{-std=}@var{standard}] -+ [@option{-g}] [@option{-pg}] [@option{-O}@var{level}] -+ [@option{-W}@var{warn}@dots{}] [@option{-pedantic}] -+ [@option{-I}@var{dir}@dots{}] [@option{-L}@var{dir}@dots{}] -+ [@option{-D}@var{macro}[=@var{defn}]@dots{}] [@option{-U}@var{macro}] -+ [@option{-f}@var{option}@dots{}] [@option{-m}@var{machine-option}@dots{}] -+ [@option{-o} @var{outfile}] [@@@var{file}] @var{infile}@dots{} -+ -+Only the most useful options are listed here; see below for the -+remainder. @samp{g++} accepts mostly the same options as @samp{gcc}. -+@c man end -+@c man begin SEEALSO -+gpl(7), gfdl(7), fsf-funding(7), -+cpp(1), gcov(1), as(1), ld(1), gdb(1), adb(1), dbx(1), sdb(1) -+and the Info entries for @file{gcc}, @file{cpp}, @file{as}, -+@file{ld}, @file{binutils} and @file{gdb}. -+@c man end -+@c man begin BUGS -+For instructions on reporting bugs, see -+@w{@value{BUGURL}}. -+@c man end -+@c man begin AUTHOR -+See the Info entry for @command{gcc}, or -+@w{@uref{http://gcc.gnu.org/onlinedocs/gcc/Contributors.html}}, -+for contributors to GCC@. -+@c man end -+@end ignore -+ -+@node Invoking GCC -+@chapter GCC Command Options -+@cindex GCC command options -+@cindex command options -+@cindex options, GCC command -+ -+@c man begin DESCRIPTION -+When you invoke GCC, it normally does preprocessing, compilation, -+assembly and linking. The ``overall options'' allow you to stop this -+process at an intermediate stage. For example, the @option{-c} option -+says not to run the linker. Then the output consists of object files -+output by the assembler. -+ -+Other options are passed on to one stage of processing. Some options -+control the preprocessor and others the compiler itself. Yet other -+options control the assembler and linker; most of these are not -+documented here, since you rarely need to use any of them. -+ -+@cindex C compilation options -+Most of the command-line options that you can use with GCC are useful -+for C programs; when an option is only useful with another language -+(usually C++), the explanation says so explicitly. If the description -+for a particular option does not mention a source language, you can use -+that option with all supported languages. -+ -+@cindex C++ compilation options -+@xref{Invoking G++,,Compiling C++ Programs}, for a summary of special -+options for compiling C++ programs. -+ -+@cindex grouping options -+@cindex options, grouping -+The @command{gcc} program accepts options and file names as operands. Many -+options have multi-letter names; therefore multiple single-letter options -+may @emph{not} be grouped: @option{-dv} is very different from @w{@samp{-d -+-v}}. -+ -+@cindex order of options -+@cindex options, order -+You can mix options and other arguments. For the most part, the order -+you use doesn't matter. Order does matter when you use several -+options of the same kind; for example, if you specify @option{-L} more -+than once, the directories are searched in the order specified. Also, -+the placement of the @option{-l} option is significant. -+ -+Many options have long names starting with @samp{-f} or with -+@samp{-W}---for example, -+@option{-fmove-loop-invariants}, @option{-Wformat} and so on. Most of -+these have both positive and negative forms; the negative form of -+@option{-ffoo} would be @option{-fno-foo}. This manual documents -+only one of these two forms, whichever one is not the default. -+ -+@c man end -+ -+@xref{Option Index}, for an index to GCC's options. -+ -+@menu -+* Option Summary:: Brief list of all options, without explanations. -+* Overall Options:: Controlling the kind of output: -+ an executable, object files, assembler files, -+ or preprocessed source. -+* Invoking G++:: Compiling C++ programs. -+* C Dialect Options:: Controlling the variant of C language compiled. -+* C++ Dialect Options:: Variations on C++. -+* Objective-C and Objective-C++ Dialect Options:: Variations on Objective-C -+ and Objective-C++. -+* Language Independent Options:: Controlling how diagnostics should be -+ formatted. -+* Warning Options:: How picky should the compiler be? -+* Debugging Options:: Symbol tables, measurements, and debugging dumps. -+* Optimize Options:: How much optimization? -+* Preprocessor Options:: Controlling header files and macro definitions. -+ Also, getting dependency information for Make. -+* Assembler Options:: Passing options to the assembler. -+* Link Options:: Specifying libraries and so on. -+* Directory Options:: Where to find header files and libraries. -+ Where to find the compiler executable files. -+* Spec Files:: How to pass switches to sub-processes. -+* Target Options:: Running a cross-compiler, or an old version of GCC. -+* Submodel Options:: Specifying minor hardware or convention variations, -+ such as 68010 vs 68020. -+* Code Gen Options:: Specifying conventions for function calls, data layout -+ and register usage. -+* Environment Variables:: Env vars that affect GCC. -+* Precompiled Headers:: Compiling a header once, and using it many times. -+@end menu -+ -+@c man begin OPTIONS -+ -+@node Option Summary -+@section Option Summary -+ -+Here is a summary of all the options, grouped by type. Explanations are -+in the following sections. -+ -+@table @emph -+@item Overall Options -+@xref{Overall Options,,Options Controlling the Kind of Output}. -+@gccoptlist{-c -S -E -o @var{file} -no-canonical-prefixes @gol -+-pipe -pass-exit-codes @gol -+-x @var{language} -v -### --help@r{[}=@var{class}@r{[},@dots{}@r{]]} --target-help @gol -+--version -wrapper @@@var{file} -fplugin=@var{file} -fplugin-arg-@var{name}=@var{arg} @gol -+-fdump-ada-spec@r{[}-slim@r{]} -fdump-go-spec=@var{file}} -+ -+@item C Language Options -+@xref{C Dialect Options,,Options Controlling C Dialect}. -+@gccoptlist{-ansi -std=@var{standard} -fgnu89-inline @gol -+-aux-info @var{filename} -fallow-parameterless-variadic-functions @gol -+-fno-asm -fno-builtin -fno-builtin-@var{function} @gol -+-fhosted -ffreestanding -fopenmp -fms-extensions -fplan9-extensions @gol -+-trigraphs -no-integrated-cpp -traditional -traditional-cpp @gol -+-fallow-single-precision -fcond-mismatch -flax-vector-conversions @gol -+-fsigned-bitfields -fsigned-char @gol -+-funsigned-bitfields -funsigned-char} -+ -+@item C++ Language Options -+@xref{C++ Dialect Options,,Options Controlling C++ Dialect}. -+@gccoptlist{-fabi-version=@var{n} -fno-access-control -fcheck-new @gol -+-fconserve-space -fconstexpr-depth=@var{n} -ffriend-injection @gol -+-fno-elide-constructors @gol -+-fno-enforce-eh-specs @gol -+-ffor-scope -fno-for-scope -fno-gnu-keywords @gol -+-fno-implicit-templates @gol -+-fno-implicit-inline-templates @gol -+-fno-implement-inlines -fms-extensions @gol -+-fno-nonansi-builtins -fnothrow-opt -fno-operator-names @gol -+-fno-optional-diags -fpermissive @gol -+-fno-pretty-templates @gol -+-frepo -fno-rtti -fstats -ftemplate-depth=@var{n} @gol -+-fno-threadsafe-statics -fuse-cxa-atexit -fno-weak -nostdinc++ @gol -+-fno-default-inline -fvisibility-inlines-hidden @gol -+-fvisibility-ms-compat @gol -+-Wabi -Wconversion-null -Wctor-dtor-privacy @gol -+-Wdelete-non-virtual-dtor -Wnarrowing -Wnoexcept @gol -+-Wnon-virtual-dtor -Wreorder @gol -+-Weffc++ -Wstrict-null-sentinel @gol -+-Wno-non-template-friend -Wold-style-cast @gol -+-Woverloaded-virtual -Wno-pmf-conversions @gol -+-Wsign-promo} -+ -+@item Objective-C and Objective-C++ Language Options -+@xref{Objective-C and Objective-C++ Dialect Options,,Options Controlling -+Objective-C and Objective-C++ Dialects}. -+@gccoptlist{-fconstant-string-class=@var{class-name} @gol -+-fgnu-runtime -fnext-runtime @gol -+-fno-nil-receivers @gol -+-fobjc-abi-version=@var{n} @gol -+-fobjc-call-cxx-cdtors @gol -+-fobjc-direct-dispatch @gol -+-fobjc-exceptions @gol -+-fobjc-gc @gol -+-fobjc-nilcheck @gol -+-fobjc-std=objc1 @gol -+-freplace-objc-classes @gol -+-fzero-link @gol -+-gen-decls @gol -+-Wassign-intercept @gol -+-Wno-protocol -Wselector @gol -+-Wstrict-selector-match @gol -+-Wundeclared-selector} -+ -+@item Language Independent Options -+@xref{Language Independent Options,,Options to Control Diagnostic Messages Formatting}. -+@gccoptlist{-fmessage-length=@var{n} @gol -+-fdiagnostics-show-location=@r{[}once@r{|}every-line@r{]} @gol -+-fno-diagnostics-show-option} -+ -+@item Warning Options -+@xref{Warning Options,,Options to Request or Suppress Warnings}. -+@gccoptlist{-fsyntax-only -fmax-errors=@var{n} -pedantic @gol -+-pedantic-errors @gol -+-w -Wextra -Wall -Waddress -Waggregate-return -Warray-bounds @gol -+-Wno-attributes -Wno-builtin-macro-redefined @gol -+-Wc++-compat -Wc++11-compat -Wcast-align -Wcast-qual @gol -+-Wchar-subscripts -Wclobbered -Wcomment @gol -+-Wconversion -Wcoverage-mismatch -Wno-cpp -Wno-deprecated @gol -+-Wno-deprecated-declarations -Wdisabled-optimization @gol -+-Wno-div-by-zero -Wdouble-promotion -Wempty-body -Wenum-compare @gol -+-Wno-endif-labels -Werror -Werror=* @gol -+-Wfatal-errors -Wfloat-equal -Wformat -Wformat=2 @gol -+-Wno-format-contains-nul -Wno-format-extra-args -Wformat-nonliteral @gol -+-Wformat-security -Wformat-y2k @gol -+-Wframe-larger-than=@var{len} -Wno-free-nonheap-object -Wjump-misses-init @gol -+-Wignored-qualifiers @gol -+-Wimplicit -Wimplicit-function-declaration -Wimplicit-int @gol -+-Winit-self -Winline -Wmaybe-uninitialized @gol -+-Wno-int-to-pointer-cast -Wno-invalid-offsetof @gol -+-Winvalid-pch -Wlarger-than=@var{len} -Wunsafe-loop-optimizations @gol -+-Wlogical-op -Wlong-long @gol -+-Wmain -Wmaybe-uninitialized -Wmissing-braces -Wmissing-field-initializers @gol -+-Wmissing-format-attribute -Wmissing-include-dirs @gol -+-Wno-mudflap @gol -+-Wno-multichar -Wnonnull -Wno-overflow @gol -+-Woverlength-strings -Wpacked -Wpacked-bitfield-compat -Wpadded @gol -+-Wparentheses -Wpedantic-ms-format -Wno-pedantic-ms-format @gol -+-Wpointer-arith -Wno-pointer-to-int-cast @gol -+-Wredundant-decls @gol -+-Wreturn-type -Wsequence-point -Wshadow @gol -+-Wsign-compare -Wsign-conversion -Wstack-protector @gol -+-Wstack-usage=@var{len} -Wstrict-aliasing -Wstrict-aliasing=n @gol -+-Wstrict-overflow -Wstrict-overflow=@var{n} @gol -+-Wsuggest-attribute=@r{[}pure@r{|}const@r{|}noreturn@r{]} @gol -+-Wswitch -Wswitch-default -Wswitch-enum -Wsync-nand @gol -+-Wsystem-headers -Wtrampolines -Wtrigraphs -Wtype-limits -Wundef @gol -+-Wuninitialized -Wunknown-pragmas -Wno-pragmas @gol -+-Wunsuffixed-float-constants -Wunused -Wunused-function @gol -+-Wunused-label -Wunused-local-typedefs -Wunused-parameter @gol -+-Wno-unused-result -Wunused-value @gol -Wunused-variable @gol -+-Wunused-but-set-parameter -Wunused-but-set-variable @gol -+-Wvariadic-macros -Wvector-operation-performance -Wvla -+-Wvolatile-register-var -Wwrite-strings -Wzero-as-null-pointer-constant} -+ -+@item C and Objective-C-only Warning Options -+@gccoptlist{-Wbad-function-cast -Wmissing-declarations @gol -+-Wmissing-parameter-type -Wmissing-prototypes -Wnested-externs @gol -+-Wold-style-declaration -Wold-style-definition @gol -+-Wstrict-prototypes -Wtraditional -Wtraditional-conversion @gol -+-Wdeclaration-after-statement -Wpointer-sign} -+ -+@item Debugging Options -+@xref{Debugging Options,,Options for Debugging Your Program or GCC}. -+@gccoptlist{-d@var{letters} -dumpspecs -dumpmachine -dumpversion @gol -+-fdbg-cnt-list -fdbg-cnt=@var{counter-value-list} @gol -+-fdisable-ipa-@var{pass_name} @gol -+-fdisable-rtl-@var{pass_name} @gol -+-fdisable-rtl-@var{pass-name}=@var{range-list} @gol -+-fdisable-tree-@var{pass_name} @gol -+-fdisable-tree-@var{pass-name}=@var{range-list} @gol -+-fdump-noaddr -fdump-unnumbered -fdump-unnumbered-links @gol -+-fdump-translation-unit@r{[}-@var{n}@r{]} @gol -+-fdump-class-hierarchy@r{[}-@var{n}@r{]} @gol -+-fdump-ipa-all -fdump-ipa-cgraph -fdump-ipa-inline @gol -+-fdump-passes @gol -+-fdump-statistics @gol -+-fdump-tree-all @gol -+-fdump-tree-original@r{[}-@var{n}@r{]} @gol -+-fdump-tree-optimized@r{[}-@var{n}@r{]} @gol -+-fdump-tree-cfg -fdump-tree-vcg -fdump-tree-alias @gol -+-fdump-tree-ch @gol -+-fdump-tree-ssa@r{[}-@var{n}@r{]} -fdump-tree-pre@r{[}-@var{n}@r{]} @gol -+-fdump-tree-ccp@r{[}-@var{n}@r{]} -fdump-tree-dce@r{[}-@var{n}@r{]} @gol -+-fdump-tree-gimple@r{[}-raw@r{]} -fdump-tree-mudflap@r{[}-@var{n}@r{]} @gol -+-fdump-tree-dom@r{[}-@var{n}@r{]} @gol -+-fdump-tree-dse@r{[}-@var{n}@r{]} @gol -+-fdump-tree-phiprop@r{[}-@var{n}@r{]} @gol -+-fdump-tree-phiopt@r{[}-@var{n}@r{]} @gol -+-fdump-tree-forwprop@r{[}-@var{n}@r{]} @gol -+-fdump-tree-copyrename@r{[}-@var{n}@r{]} @gol -+-fdump-tree-nrv -fdump-tree-vect @gol -+-fdump-tree-sink @gol -+-fdump-tree-sra@r{[}-@var{n}@r{]} @gol -+-fdump-tree-forwprop@r{[}-@var{n}@r{]} @gol -+-fdump-tree-fre@r{[}-@var{n}@r{]} @gol -+-fdump-tree-vrp@r{[}-@var{n}@r{]} @gol -+-ftree-vectorizer-verbose=@var{n} @gol -+-fdump-tree-storeccp@r{[}-@var{n}@r{]} @gol -+-fdump-final-insns=@var{file} @gol -+-fcompare-debug@r{[}=@var{opts}@r{]} -fcompare-debug-second @gol -+-feliminate-dwarf2-dups -feliminate-unused-debug-types @gol -+-feliminate-unused-debug-symbols -femit-class-debug-always @gol -+-fenable-@var{kind}-@var{pass} @gol -+-fenable-@var{kind}-@var{pass}=@var{range-list} @gol -+-fdebug-types-section @gol -+-fmem-report -fpre-ipa-mem-report -fpost-ipa-mem-report -fprofile-arcs @gol -+-frandom-seed=@var{string} -fsched-verbose=@var{n} @gol -+-fsel-sched-verbose -fsel-sched-dump-cfg -fsel-sched-pipelining-verbose @gol -+-fstack-usage -ftest-coverage -ftime-report -fvar-tracking @gol -+-fvar-tracking-assignments -fvar-tracking-assignments-toggle @gol -+-g -g@var{level} -gtoggle -gcoff -gdwarf-@var{version} @gol -+-ggdb -grecord-gcc-switches -gno-record-gcc-switches @gol -+-gstabs -gstabs+ -gstrict-dwarf -gno-strict-dwarf @gol -+-gvms -gxcoff -gxcoff+ @gol -+-fno-merge-debug-strings -fno-dwarf2-cfi-asm @gol -+-fdebug-prefix-map=@var{old}=@var{new} @gol -+-femit-struct-debug-baseonly -femit-struct-debug-reduced @gol -+-femit-struct-debug-detailed@r{[}=@var{spec-list}@r{]} @gol -+-p -pg -print-file-name=@var{library} -print-libgcc-file-name @gol -+-print-multi-directory -print-multi-lib -print-multi-os-directory @gol -+-print-prog-name=@var{program} -print-search-dirs -Q @gol -+-print-sysroot -print-sysroot-headers-suffix @gol -+-save-temps -save-temps=cwd -save-temps=obj -time@r{[}=@var{file}@r{]}} -+ -+@item Optimization Options -+@xref{Optimize Options,,Options that Control Optimization}. -+@gccoptlist{-falign-functions[=@var{n}] -falign-jumps[=@var{n}] @gol -+-falign-labels[=@var{n}] -falign-loops[=@var{n}] -fassociative-math @gol -+-fauto-inc-dec -fbranch-probabilities -fbranch-target-load-optimize @gol -+-fbranch-target-load-optimize2 -fbtr-bb-exclusive -fcaller-saves @gol -+-fcheck-data-deps -fcombine-stack-adjustments -fconserve-stack @gol -+-fcompare-elim -fcprop-registers -fcrossjumping @gol -+-fcse-follow-jumps -fcse-skip-blocks -fcx-fortran-rules @gol -+-fcx-limited-range @gol -+-fdata-sections -fdce -fdelayed-branch @gol -+-fdelete-null-pointer-checks -fdevirtualize -fdse @gol -+-fearly-inlining -fipa-sra -fexpensive-optimizations -ffat-lto-objects @gol -+-ffast-math -ffinite-math-only -ffloat-store -fexcess-precision=@var{style} @gol -+-fforward-propagate -ffp-contract=@var{style} -ffunction-sections @gol -+-fgcse -fgcse-after-reload -fgcse-las -fgcse-lm -fgraphite-identity @gol -+-fgcse-sm -fif-conversion -fif-conversion2 -findirect-inlining @gol -+-finline-functions -finline-functions-called-once -finline-limit=@var{n} @gol -+-finline-small-functions -fipa-cp -fipa-cp-clone -fipa-matrix-reorg @gol -+-fipa-pta -fipa-profile -fipa-pure-const -fipa-reference @gol -+-fira-algorithm=@var{algorithm} @gol -+-fira-region=@var{region} @gol -+-fira-loop-pressure -fno-ira-share-save-slots @gol -+-fno-ira-share-spill-slots -fira-verbose=@var{n} @gol -+-fivopts -fkeep-inline-functions -fkeep-static-consts @gol -+-floop-block -floop-flatten -floop-interchange -floop-strip-mine @gol -+-floop-parallelize-all -flto -flto-compression-level @gol -+-flto-partition=@var{alg} -flto-report -fmerge-all-constants @gol -+-fmerge-constants -fmodulo-sched -fmodulo-sched-allow-regmoves @gol -+-fmove-loop-invariants fmudflap -fmudflapir -fmudflapth -fno-branch-count-reg @gol -+-fno-default-inline @gol -+-fno-defer-pop -fno-function-cse -fno-guess-branch-probability @gol -+-fno-inline -fno-math-errno -fno-peephole -fno-peephole2 @gol -+-fno-sched-interblock -fno-sched-spec -fno-signed-zeros @gol -+-fno-toplevel-reorder -fno-trapping-math -fno-zero-initialized-in-bss @gol -+-fomit-frame-pointer -foptimize-register-move -foptimize-sibling-calls @gol -+-fpartial-inlining -fpeel-loops -fpredictive-commoning @gol -+-fprefetch-loop-arrays @gol -+-fprofile-correction -fprofile-dir=@var{path} -fprofile-generate @gol -+-fprofile-generate=@var{path} @gol -+-fprofile-use -fprofile-use=@var{path} -fprofile-values @gol -+-freciprocal-math -free -fregmove -frename-registers -freorder-blocks @gol -+-freorder-blocks-and-partition -freorder-functions @gol -+-frerun-cse-after-loop -freschedule-modulo-scheduled-loops @gol -+-frounding-math -fsched2-use-superblocks -fsched-pressure @gol -+-fsched-spec-load -fsched-spec-load-dangerous @gol -+-fsched-stalled-insns-dep[=@var{n}] -fsched-stalled-insns[=@var{n}] @gol -+-fsched-group-heuristic -fsched-critical-path-heuristic @gol -+-fsched-spec-insn-heuristic -fsched-rank-heuristic @gol -+-fsched-last-insn-heuristic -fsched-dep-count-heuristic @gol -+-fschedule-insns -fschedule-insns2 -fsection-anchors @gol -+-fselective-scheduling -fselective-scheduling2 @gol -+-fsel-sched-pipelining -fsel-sched-pipelining-outer-loops @gol -+-fshrink-wrap -fsignaling-nans -fsingle-precision-constant @gol -+-fsplit-ivs-in-unroller -fsplit-wide-types -fstack-protector @gol -+-fstack-protector-all -fstrict-aliasing -fstrict-overflow @gol -+-fthread-jumps -ftracer -ftree-bit-ccp @gol -+-ftree-builtin-call-dce -ftree-ccp -ftree-ch -ftree-copy-prop @gol -+-ftree-copyrename -ftree-dce -ftree-dominator-opts -ftree-dse @gol -+-ftree-forwprop -ftree-fre -ftree-loop-if-convert @gol -+-ftree-loop-if-convert-stores -ftree-loop-im @gol -+-ftree-phiprop -ftree-loop-distribution -ftree-loop-distribute-patterns @gol -+-ftree-loop-ivcanon -ftree-loop-linear -ftree-loop-optimize @gol -+-ftree-parallelize-loops=@var{n} -ftree-pre -ftree-partial-pre -ftree-pta @gol -+-ftree-reassoc @gol -+-ftree-sink -ftree-sra -ftree-switch-conversion -ftree-tail-merge @gol -+-ftree-ter -ftree-vect-loop-version -ftree-vectorize -ftree-vrp @gol -+-funit-at-a-time -funroll-all-loops -funroll-loops @gol -+-funsafe-loop-optimizations -funsafe-math-optimizations -funswitch-loops @gol -+-fvariable-expansion-in-unroller -fvect-cost-model -fvpt -fweb @gol -+-fwhole-program -fwpa -fuse-linker-plugin @gol -+--param @var{name}=@var{value} -+-O -O0 -O1 -O2 -O3 -Os -Ofast} -+ -+@item Preprocessor Options -+@xref{Preprocessor Options,,Options Controlling the Preprocessor}. -+@gccoptlist{-A@var{question}=@var{answer} @gol -+-A-@var{question}@r{[}=@var{answer}@r{]} @gol -+-C -dD -dI -dM -dN @gol -+-D@var{macro}@r{[}=@var{defn}@r{]} -E -H @gol -+-idirafter @var{dir} @gol -+-include @var{file} -imacros @var{file} @gol -+-iprefix @var{file} -iwithprefix @var{dir} @gol -+-iwithprefixbefore @var{dir} -isystem @var{dir} @gol -+-imultilib @var{dir} -isysroot @var{dir} @gol -+-M -MM -MF -MG -MP -MQ -MT -nostdinc @gol -+-P -fdebug-cpp -ftrack-macro-expansion -fworking-directory @gol -+-remap -trigraphs -undef -U@var{macro} @gol -+-Wp,@var{option} -Xpreprocessor @var{option}} -+ -+@item Assembler Option -+@xref{Assembler Options,,Passing Options to the Assembler}. -+@gccoptlist{-Wa,@var{option} -Xassembler @var{option}} -+ -+@item Linker Options -+@xref{Link Options,,Options for Linking}. -+@gccoptlist{@var{object-file-name} -l@var{library} @gol -+-nostartfiles -nodefaultlibs -nostdlib -pie -rdynamic @gol -+-s -static -static-libgcc -static-libstdc++ -shared @gol -+-shared-libgcc -symbolic @gol -+-T @var{script} -Wl,@var{option} -Xlinker @var{option} @gol -+-u @var{symbol}} -+ -+@item Directory Options -+@xref{Directory Options,,Options for Directory Search}. -+@gccoptlist{-B@var{prefix} -I@var{dir} -iplugindir=@var{dir} @gol -+-iquote@var{dir} -L@var{dir} -specs=@var{file} -I- @gol -+--sysroot=@var{dir}} -+ -+@item Machine Dependent Options -+@xref{Submodel Options,,Hardware Models and Configurations}. -+@c This list is ordered alphanumerically by subsection name. -+@c Try and put the significant identifier (CPU or system) first, -+@c so users have a clue at guessing where the ones they want will be. -+ -+@emph{Adapteva Epiphany Options} -+@gccoptlist{-mhalf-reg-file -mprefer-short-insn-regs @gol -+-mbranch-cost=@var{num} -mcmove -mnops=@var{num} -msoft-cmpsf @gol -+-msplit-lohi -mpost-inc -mpost-modify -mstack-offset=@var{num} @gol -+-mround-nearest -mlong-calls -mshort-calls -msmall16 @gol -+-mfp-mode=@var{mode} -mvect-double -max-vect-align=@var{num} @gol -+-msplit-vecmove-early -m1reg-@var{reg}} -+ -+@emph{ARM Options} -+@gccoptlist{-mapcs-frame -mno-apcs-frame @gol -+-mabi=@var{name} @gol -+-mapcs-stack-check -mno-apcs-stack-check @gol -+-mapcs-float -mno-apcs-float @gol -+-mapcs-reentrant -mno-apcs-reentrant @gol -+-msched-prolog -mno-sched-prolog @gol -+-mlittle-endian -mbig-endian -mwords-little-endian @gol -+-mfloat-abi=@var{name} -mfpe @gol -+-mfp16-format=@var{name} -+-mthumb-interwork -mno-thumb-interwork @gol -+-mcpu=@var{name} -march=@var{name} -mfpu=@var{name} @gol -+-mstructure-size-boundary=@var{n} @gol -+-mabort-on-noreturn @gol -+-mlong-calls -mno-long-calls @gol -+-msingle-pic-base -mno-single-pic-base @gol -+-mpic-register=@var{reg} @gol -+-mnop-fun-dllimport @gol -+-mcirrus-fix-invalid-insns -mno-cirrus-fix-invalid-insns @gol -+-mpoke-function-name @gol -+-mthumb -marm @gol -+-mtpcs-frame -mtpcs-leaf-frame @gol -+-mcaller-super-interworking -mcallee-super-interworking @gol -+-mtp=@var{name} -mtls-dialect=@var{dialect} @gol -+-mword-relocations @gol -+-mfix-cortex-m3-ldrd @gol -+-munaligned-access} -+ -+@emph{AVR Options} -+@gccoptlist{-mmcu=@var{mcu} -maccumulate-args -mbranch-cost=@var{cost} @gol -+-mcall-prologues -mint8 -mno-interrupts -mrelax -mshort-calls @gol -+-mstrict-X -mtiny-stack} -+ -+@emph{Blackfin Options} -+@gccoptlist{-mcpu=@var{cpu}@r{[}-@var{sirevision}@r{]} @gol -+-msim -momit-leaf-frame-pointer -mno-omit-leaf-frame-pointer @gol -+-mspecld-anomaly -mno-specld-anomaly -mcsync-anomaly -mno-csync-anomaly @gol -+-mlow-64k -mno-low64k -mstack-check-l1 -mid-shared-library @gol -+-mno-id-shared-library -mshared-library-id=@var{n} @gol -+-mleaf-id-shared-library -mno-leaf-id-shared-library @gol -+-msep-data -mno-sep-data -mlong-calls -mno-long-calls @gol -+-mfast-fp -minline-plt -mmulticore -mcorea -mcoreb -msdram @gol -+-micplb} -+ -+@emph{C6X Options} -+@gccoptlist{-mbig-endian -mlittle-endian -march=@var{cpu} @gol -+-msim -msdata=@var{sdata-type}} -+ -+@emph{CRIS Options} -+@gccoptlist{-mcpu=@var{cpu} -march=@var{cpu} -mtune=@var{cpu} @gol -+-mmax-stack-frame=@var{n} -melinux-stacksize=@var{n} @gol -+-metrax4 -metrax100 -mpdebug -mcc-init -mno-side-effects @gol -+-mstack-align -mdata-align -mconst-align @gol -+-m32-bit -m16-bit -m8-bit -mno-prologue-epilogue -mno-gotplt @gol -+-melf -maout -melinux -mlinux -sim -sim2 @gol -+-mmul-bug-workaround -mno-mul-bug-workaround} -+ -+@emph{CR16 Options} -+@gccoptlist{-mmac @gol -+-mcr16cplus -mcr16c @gol -+-msim -mint32 -mbit-ops -+-mdata-model=@var{model}} -+ -+@emph{Darwin Options} -+@gccoptlist{-all_load -allowable_client -arch -arch_errors_fatal @gol -+-arch_only -bind_at_load -bundle -bundle_loader @gol -+-client_name -compatibility_version -current_version @gol -+-dead_strip @gol -+-dependency-file -dylib_file -dylinker_install_name @gol -+-dynamic -dynamiclib -exported_symbols_list @gol -+-filelist -flat_namespace -force_cpusubtype_ALL @gol -+-force_flat_namespace -headerpad_max_install_names @gol -+-iframework @gol -+-image_base -init -install_name -keep_private_externs @gol -+-multi_module -multiply_defined -multiply_defined_unused @gol -+-noall_load -no_dead_strip_inits_and_terms @gol -+-nofixprebinding -nomultidefs -noprebind -noseglinkedit @gol -+-pagezero_size -prebind -prebind_all_twolevel_modules @gol -+-private_bundle -read_only_relocs -sectalign @gol -+-sectobjectsymbols -whyload -seg1addr @gol -+-sectcreate -sectobjectsymbols -sectorder @gol -+-segaddr -segs_read_only_addr -segs_read_write_addr @gol -+-seg_addr_table -seg_addr_table_filename -seglinkedit @gol -+-segprot -segs_read_only_addr -segs_read_write_addr @gol -+-single_module -static -sub_library -sub_umbrella @gol -+-twolevel_namespace -umbrella -undefined @gol -+-unexported_symbols_list -weak_reference_mismatches @gol -+-whatsloaded -F -gused -gfull -mmacosx-version-min=@var{version} @gol -+-mkernel -mone-byte-bool} -+ -+@emph{DEC Alpha Options} -+@gccoptlist{-mno-fp-regs -msoft-float -malpha-as -mgas @gol -+-mieee -mieee-with-inexact -mieee-conformant @gol -+-mfp-trap-mode=@var{mode} -mfp-rounding-mode=@var{mode} @gol -+-mtrap-precision=@var{mode} -mbuild-constants @gol -+-mcpu=@var{cpu-type} -mtune=@var{cpu-type} @gol -+-mbwx -mmax -mfix -mcix @gol -+-mfloat-vax -mfloat-ieee @gol -+-mexplicit-relocs -msmall-data -mlarge-data @gol -+-msmall-text -mlarge-text @gol -+-mmemory-latency=@var{time}} -+ -+@emph{DEC Alpha/VMS Options} -+@gccoptlist{-mvms-return-codes -mdebug-main=@var{prefix} -mmalloc64} -+ -+@emph{FR30 Options} -+@gccoptlist{-msmall-model -mno-lsim} -+ -+@emph{FRV Options} -+@gccoptlist{-mgpr-32 -mgpr-64 -mfpr-32 -mfpr-64 @gol -+-mhard-float -msoft-float @gol -+-malloc-cc -mfixed-cc -mdword -mno-dword @gol -+-mdouble -mno-double @gol -+-mmedia -mno-media -mmuladd -mno-muladd @gol -+-mfdpic -minline-plt -mgprel-ro -multilib-library-pic @gol -+-mlinked-fp -mlong-calls -malign-labels @gol -+-mlibrary-pic -macc-4 -macc-8 @gol -+-mpack -mno-pack -mno-eflags -mcond-move -mno-cond-move @gol -+-moptimize-membar -mno-optimize-membar @gol -+-mscc -mno-scc -mcond-exec -mno-cond-exec @gol -+-mvliw-branch -mno-vliw-branch @gol -+-mmulti-cond-exec -mno-multi-cond-exec -mnested-cond-exec @gol -+-mno-nested-cond-exec -mtomcat-stats @gol -+-mTLS -mtls @gol -+-mcpu=@var{cpu}} -+ -+@emph{GNU/Linux Options} -+@gccoptlist{-mglibc -muclibc -mbionic -mandroid @gol -+-tno-android-cc -tno-android-ld} -+ -+@emph{H8/300 Options} -+@gccoptlist{-mrelax -mh -ms -mn -mint32 -malign-300} -+ -+@emph{HPPA Options} -+@gccoptlist{-march=@var{architecture-type} @gol -+-mbig-switch -mdisable-fpregs -mdisable-indexing @gol -+-mfast-indirect-calls -mgas -mgnu-ld -mhp-ld @gol -+-mfixed-range=@var{register-range} @gol -+-mjump-in-delay -mlinker-opt -mlong-calls @gol -+-mlong-load-store -mno-big-switch -mno-disable-fpregs @gol -+-mno-disable-indexing -mno-fast-indirect-calls -mno-gas @gol -+-mno-jump-in-delay -mno-long-load-store @gol -+-mno-portable-runtime -mno-soft-float @gol -+-mno-space-regs -msoft-float -mpa-risc-1-0 @gol -+-mpa-risc-1-1 -mpa-risc-2-0 -mportable-runtime @gol -+-mschedule=@var{cpu-type} -mspace-regs -msio -mwsio @gol -+-munix=@var{unix-std} -nolibdld -static -threads} -+ -+@emph{i386 and x86-64 Options} -+@gccoptlist{-mtune=@var{cpu-type} -march=@var{cpu-type} @gol -+-mfpmath=@var{unit} @gol -+-masm=@var{dialect} -mno-fancy-math-387 @gol -+-mno-fp-ret-in-387 -msoft-float @gol -+-mno-wide-multiply -mrtd -malign-double @gol -+-mpreferred-stack-boundary=@var{num} @gol -+-mincoming-stack-boundary=@var{num} @gol -+-mcld -mcx16 -msahf -mmovbe -mcrc32 @gol -+-mrecip -mrecip=@var{opt} @gol -+-mvzeroupper @gol -+-mmmx -msse -msse2 -msse3 -mssse3 -msse4.1 -msse4.2 -msse4 -mavx @gol -+-mavx2 -maes -mpclmul -mfsgsbase -mrdrnd -mf16c -mfma @gol -+-msse4a -m3dnow -mpopcnt -mabm -mbmi -mtbm -mfma4 -mxop -mlzcnt @gol -+-mbmi2 -mlwp -mthreads -mno-align-stringops -minline-all-stringops @gol -+-minline-stringops-dynamically -mstringop-strategy=@var{alg} @gol -+-mpush-args -maccumulate-outgoing-args -m128bit-long-double @gol -+-m96bit-long-double -mregparm=@var{num} -msseregparm @gol -+-mveclibabi=@var{type} -mvect8-ret-in-mem @gol -+-mpc32 -mpc64 -mpc80 -mstackrealign @gol -+-momit-leaf-frame-pointer -mno-red-zone -mno-tls-direct-seg-refs @gol -+-mcmodel=@var{code-model} -mabi=@var{name} @gol -+-m32 -m64 -mx32 -mlarge-data-threshold=@var{num} @gol -+-msse2avx -mfentry -m8bit-idiv @gol -+-mavx256-split-unaligned-load -mavx256-split-unaligned-store} -+ -+@emph{i386 and x86-64 Windows Options} -+@gccoptlist{-mconsole -mcygwin -mno-cygwin -mdll @gol -+-mnop-fun-dllimport -mthread @gol -+-municode -mwin32 -mwindows -fno-set-stack-executable} -+ -+@emph{IA-64 Options} -+@gccoptlist{-mbig-endian -mlittle-endian -mgnu-as -mgnu-ld -mno-pic @gol -+-mvolatile-asm-stop -mregister-names -msdata -mno-sdata @gol -+-mconstant-gp -mauto-pic -mfused-madd @gol -+-minline-float-divide-min-latency @gol -+-minline-float-divide-max-throughput @gol -+-mno-inline-float-divide @gol -+-minline-int-divide-min-latency @gol -+-minline-int-divide-max-throughput @gol -+-mno-inline-int-divide @gol -+-minline-sqrt-min-latency -minline-sqrt-max-throughput @gol -+-mno-inline-sqrt @gol -+-mdwarf2-asm -mearly-stop-bits @gol -+-mfixed-range=@var{register-range} -mtls-size=@var{tls-size} @gol -+-mtune=@var{cpu-type} -milp32 -mlp64 @gol -+-msched-br-data-spec -msched-ar-data-spec -msched-control-spec @gol -+-msched-br-in-data-spec -msched-ar-in-data-spec -msched-in-control-spec @gol -+-msched-spec-ldc -msched-spec-control-ldc @gol -+-msched-prefer-non-data-spec-insns -msched-prefer-non-control-spec-insns @gol -+-msched-stop-bits-after-every-cycle -msched-count-spec-in-critical-path @gol -+-msel-sched-dont-check-control-spec -msched-fp-mem-deps-zero-cost @gol -+-msched-max-memory-insns-hard-limit -msched-max-memory-insns=@var{max-insns}} -+ -+@emph{IA-64/VMS Options} -+@gccoptlist{-mvms-return-codes -mdebug-main=@var{prefix} -mmalloc64} -+ -+@emph{LM32 Options} -+@gccoptlist{-mbarrel-shift-enabled -mdivide-enabled -mmultiply-enabled @gol -+-msign-extend-enabled -muser-enabled} -+ -+@emph{M32R/D Options} -+@gccoptlist{-m32r2 -m32rx -m32r @gol -+-mdebug @gol -+-malign-loops -mno-align-loops @gol -+-missue-rate=@var{number} @gol -+-mbranch-cost=@var{number} @gol -+-mmodel=@var{code-size-model-type} @gol -+-msdata=@var{sdata-type} @gol -+-mno-flush-func -mflush-func=@var{name} @gol -+-mno-flush-trap -mflush-trap=@var{number} @gol -+-G @var{num}} -+ -+@emph{M32C Options} -+@gccoptlist{-mcpu=@var{cpu} -msim -memregs=@var{number}} -+ -+@emph{M680x0 Options} -+@gccoptlist{-march=@var{arch} -mcpu=@var{cpu} -mtune=@var{tune} -+-m68000 -m68020 -m68020-40 -m68020-60 -m68030 -m68040 @gol -+-m68060 -mcpu32 -m5200 -m5206e -m528x -m5307 -m5407 @gol -+-mcfv4e -mbitfield -mno-bitfield -mc68000 -mc68020 @gol -+-mnobitfield -mrtd -mno-rtd -mdiv -mno-div -mshort @gol -+-mno-short -mhard-float -m68881 -msoft-float -mpcrel @gol -+-malign-int -mstrict-align -msep-data -mno-sep-data @gol -+-mshared-library-id=n -mid-shared-library -mno-id-shared-library @gol -+-mxgot -mno-xgot} -+ -+@emph{MCore Options} -+@gccoptlist{-mhardlit -mno-hardlit -mdiv -mno-div -mrelax-immediates @gol -+-mno-relax-immediates -mwide-bitfields -mno-wide-bitfields @gol -+-m4byte-functions -mno-4byte-functions -mcallgraph-data @gol -+-mno-callgraph-data -mslow-bytes -mno-slow-bytes -mno-lsim @gol -+-mlittle-endian -mbig-endian -m210 -m340 -mstack-increment} -+ -+@emph{MeP Options} -+@gccoptlist{-mabsdiff -mall-opts -maverage -mbased=@var{n} -mbitops @gol -+-mc=@var{n} -mclip -mconfig=@var{name} -mcop -mcop32 -mcop64 -mivc2 @gol -+-mdc -mdiv -meb -mel -mio-volatile -ml -mleadz -mm -mminmax @gol -+-mmult -mno-opts -mrepeat -ms -msatur -msdram -msim -msimnovec -mtf @gol -+-mtiny=@var{n}} -+ -+@emph{MicroBlaze Options} -+@gccoptlist{-msoft-float -mhard-float -msmall-divides -mcpu=@var{cpu} @gol -+-mmemcpy -mxl-soft-mul -mxl-soft-div -mxl-barrel-shift @gol -+-mxl-pattern-compare -mxl-stack-check -mxl-gp-opt -mno-clearbss @gol -+-mxl-multiply-high -mxl-float-convert -mxl-float-sqrt @gol -+-mxl-mode-@var{app-model}} -+ -+@emph{MIPS Options} -+@gccoptlist{-EL -EB -march=@var{arch} -mtune=@var{arch} @gol -+-mips1 -mips2 -mips3 -mips4 -mips32 -mips32r2 @gol -+-mips64 -mips64r2 @gol -+-mips16 -mno-mips16 -mflip-mips16 @gol -+-minterlink-mips16 -mno-interlink-mips16 @gol -+-mabi=@var{abi} -mabicalls -mno-abicalls @gol -+-mshared -mno-shared -mplt -mno-plt -mxgot -mno-xgot @gol -+-mgp32 -mgp64 -mfp32 -mfp64 -mhard-float -msoft-float @gol -+-msingle-float -mdouble-float -mdsp -mno-dsp -mdspr2 -mno-dspr2 @gol -+-mfpu=@var{fpu-type} @gol -+-msmartmips -mno-smartmips @gol -+-mpaired-single -mno-paired-single -mdmx -mno-mdmx @gol -+-mips3d -mno-mips3d -mmt -mno-mt -mllsc -mno-llsc @gol -+-mlong64 -mlong32 -msym32 -mno-sym32 @gol -+-G@var{num} -mlocal-sdata -mno-local-sdata @gol -+-mextern-sdata -mno-extern-sdata -mgpopt -mno-gopt @gol -+-membedded-data -mno-embedded-data @gol -+-muninit-const-in-rodata -mno-uninit-const-in-rodata @gol -+-mcode-readable=@var{setting} @gol -+-msplit-addresses -mno-split-addresses @gol -+-mexplicit-relocs -mno-explicit-relocs @gol -+-mcheck-zero-division -mno-check-zero-division @gol -+-mdivide-traps -mdivide-breaks @gol -+-mmemcpy -mno-memcpy -mlong-calls -mno-long-calls @gol -+-mmad -mno-mad -mfused-madd -mno-fused-madd -nocpp @gol -+-mfix-24k -mno-fix-24k @gol -+-mfix-r4000 -mno-fix-r4000 -mfix-r4400 -mno-fix-r4400 @gol -+-mfix-r10000 -mno-fix-r10000 -mfix-vr4120 -mno-fix-vr4120 @gol -+-mfix-vr4130 -mno-fix-vr4130 -mfix-sb1 -mno-fix-sb1 @gol -+-mflush-func=@var{func} -mno-flush-func @gol -+-mbranch-cost=@var{num} -mbranch-likely -mno-branch-likely @gol -+-mfp-exceptions -mno-fp-exceptions @gol -+-mvr4130-align -mno-vr4130-align -msynci -mno-synci @gol -+-mrelax-pic-calls -mno-relax-pic-calls -mmcount-ra-address} -+ -+@emph{MMIX Options} -+@gccoptlist{-mlibfuncs -mno-libfuncs -mepsilon -mno-epsilon -mabi=gnu @gol -+-mabi=mmixware -mzero-extend -mknuthdiv -mtoplevel-symbols @gol -+-melf -mbranch-predict -mno-branch-predict -mbase-addresses @gol -+-mno-base-addresses -msingle-exit -mno-single-exit} -+ -+@emph{MN10300 Options} -+@gccoptlist{-mmult-bug -mno-mult-bug @gol -+-mno-am33 -mam33 -mam33-2 -mam34 @gol -+-mtune=@var{cpu-type} @gol -+-mreturn-pointer-on-d0 @gol -+-mno-crt0 -mrelax -mliw -msetlb} -+ -+@emph{PDP-11 Options} -+@gccoptlist{-mfpu -msoft-float -mac0 -mno-ac0 -m40 -m45 -m10 @gol -+-mbcopy -mbcopy-builtin -mint32 -mno-int16 @gol -+-mint16 -mno-int32 -mfloat32 -mno-float64 @gol -+-mfloat64 -mno-float32 -mabshi -mno-abshi @gol -+-mbranch-expensive -mbranch-cheap @gol -+-munix-asm -mdec-asm} -+ -+@emph{picoChip Options} -+@gccoptlist{-mae=@var{ae_type} -mvliw-lookahead=@var{N} @gol -+-msymbol-as-address -mno-inefficient-warnings} -+ -+@emph{PowerPC Options} -+See RS/6000 and PowerPC Options. -+ -+@emph{RL78 Options} -+@gccoptlist{-msim -mmul=none -mmul=g13 -mmul=rl78} -+ -+@emph{RS/6000 and PowerPC Options} -+@gccoptlist{-mcpu=@var{cpu-type} @gol -+-mtune=@var{cpu-type} @gol -+-mcmodel=@var{code-model} @gol -+-mpower -mno-power -mpower2 -mno-power2 @gol -+-mpowerpc -mpowerpc64 -mno-powerpc @gol -+-maltivec -mno-altivec @gol -+-mpowerpc-gpopt -mno-powerpc-gpopt @gol -+-mpowerpc-gfxopt -mno-powerpc-gfxopt @gol -+-mmfcrf -mno-mfcrf -mpopcntb -mno-popcntb -mpopcntd -mno-popcntd @gol -+-mfprnd -mno-fprnd @gol -+-mcmpb -mno-cmpb -mmfpgpr -mno-mfpgpr -mhard-dfp -mno-hard-dfp @gol -+-mnew-mnemonics -mold-mnemonics @gol -+-mfull-toc -mminimal-toc -mno-fp-in-toc -mno-sum-in-toc @gol -+-m64 -m32 -mxl-compat -mno-xl-compat -mpe @gol -+-malign-power -malign-natural @gol -+-msoft-float -mhard-float -mmultiple -mno-multiple @gol -+-msingle-float -mdouble-float -msimple-fpu @gol -+-mstring -mno-string -mupdate -mno-update @gol -+-mavoid-indexed-addresses -mno-avoid-indexed-addresses @gol -+-mfused-madd -mno-fused-madd -mbit-align -mno-bit-align @gol -+-mstrict-align -mno-strict-align -mrelocatable @gol -+-mno-relocatable -mrelocatable-lib -mno-relocatable-lib @gol -+-mtoc -mno-toc -mlittle -mlittle-endian -mbig -mbig-endian @gol -+-mdynamic-no-pic -maltivec -mswdiv -msingle-pic-base @gol -+-mprioritize-restricted-insns=@var{priority} @gol -+-msched-costly-dep=@var{dependence_type} @gol -+-minsert-sched-nops=@var{scheme} @gol -+-mcall-sysv -mcall-netbsd @gol -+-maix-struct-return -msvr4-struct-return @gol -+-mabi=@var{abi-type} -msecure-plt -mbss-plt @gol -+-mblock-move-inline-limit=@var{num} @gol -+-misel -mno-isel @gol -+-misel=yes -misel=no @gol -+-mspe -mno-spe @gol -+-mspe=yes -mspe=no @gol -+-mpaired @gol -+-mgen-cell-microcode -mwarn-cell-microcode @gol -+-mvrsave -mno-vrsave @gol -+-mmulhw -mno-mulhw @gol -+-mdlmzb -mno-dlmzb @gol -+-mfloat-gprs=yes -mfloat-gprs=no -mfloat-gprs=single -mfloat-gprs=double @gol -+-mprototype -mno-prototype @gol -+-msim -mmvme -mads -myellowknife -memb -msdata @gol -+-msdata=@var{opt} -mvxworks -G @var{num} -pthread @gol -+-mrecip -mrecip=@var{opt} -mno-recip -mrecip-precision @gol -+-mno-recip-precision @gol -+-mveclibabi=@var{type} -mfriz -mno-friz @gol -+-mpointers-to-nested-functions -mno-pointers-to-nested-functions @gol -+-msave-toc-indirect -mno-save-toc-indirect} -+ -+@emph{RX Options} -+@gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu@gol -+-mcpu=@gol -+-mbig-endian-data -mlittle-endian-data @gol -+-msmall-data @gol -+-msim -mno-sim@gol -+-mas100-syntax -mno-as100-syntax@gol -+-mrelax@gol -+-mmax-constant-size=@gol -+-mint-register=@gol -+-mpid@gol -+-msave-acc-in-interrupts} -+ -+@emph{S/390 and zSeries Options} -+@gccoptlist{-mtune=@var{cpu-type} -march=@var{cpu-type} @gol -+-mhard-float -msoft-float -mhard-dfp -mno-hard-dfp @gol -+-mlong-double-64 -mlong-double-128 @gol -+-mbackchain -mno-backchain -mpacked-stack -mno-packed-stack @gol -+-msmall-exec -mno-small-exec -mmvcle -mno-mvcle @gol -+-m64 -m31 -mdebug -mno-debug -mesa -mzarch @gol -+-mtpf-trace -mno-tpf-trace -mfused-madd -mno-fused-madd @gol -+-mwarn-framesize -mwarn-dynamicstack -mstack-size -mstack-guard} -+ -+@emph{Score Options} -+@gccoptlist{-meb -mel @gol -+-mnhwloop @gol -+-muls @gol -+-mmac @gol -+-mscore5 -mscore5u -mscore7 -mscore7d} -+ -+@emph{SH Options} -+@gccoptlist{-m1 -m2 -m2e @gol -+-m2a-nofpu -m2a-single-only -m2a-single -m2a @gol -+-m3 -m3e @gol -+-m4-nofpu -m4-single-only -m4-single -m4 @gol -+-m4a-nofpu -m4a-single-only -m4a-single -m4a -m4al @gol -+-m5-64media -m5-64media-nofpu @gol -+-m5-32media -m5-32media-nofpu @gol -+-m5-compact -m5-compact-nofpu @gol -+-mb -ml -mdalign -mrelax @gol -+-mbigtable -mfmovd -mhitachi -mrenesas -mno-renesas -mnomacsave @gol -+-mieee -mno-ieee -mbitops -misize -minline-ic_invalidate -mpadstruct @gol -+-mspace -mprefergot -musermode -multcost=@var{number} -mdiv=@var{strategy} @gol -+-mdivsi3_libfunc=@var{name} -mfixed-range=@var{register-range} @gol -+-madjust-unroll -mindexed-addressing -mgettrcost=@var{number} -mpt-fixed @gol -+-maccumulate-outgoing-args -minvalid-symbols -msoft-atomic @gol -+-mbranch-cost=@var{num} -mcbranchdi -mcmpeqdi -mfused-madd -mpretend-cmove} -+ -+@emph{Solaris 2 Options} -+@gccoptlist{-mimpure-text -mno-impure-text @gol -+-pthreads -pthread} -+ -+@emph{SPARC Options} -+@gccoptlist{-mcpu=@var{cpu-type} @gol -+-mtune=@var{cpu-type} @gol -+-mcmodel=@var{code-model} @gol -+-mmemory-model=@var{mem-model} @gol -+-m32 -m64 -mapp-regs -mno-app-regs @gol -+-mfaster-structs -mno-faster-structs -mflat -mno-flat @gol -+-mfpu -mno-fpu -mhard-float -msoft-float @gol -+-mhard-quad-float -msoft-quad-float @gol -+-mlittle-endian @gol -+-mstack-bias -mno-stack-bias @gol -+-munaligned-doubles -mno-unaligned-doubles @gol -+-mv8plus -mno-v8plus -mvis -mno-vis @gol -+-mvis2 -mno-vis2 -mvis3 -mno-vis3 @gol -+-mfmaf -mno-fmaf -mpopc -mno-popc @gol -+-mfix-at697f} -+ -+@emph{SPU Options} -+@gccoptlist{-mwarn-reloc -merror-reloc @gol -+-msafe-dma -munsafe-dma @gol -+-mbranch-hints @gol -+-msmall-mem -mlarge-mem -mstdmain @gol -+-mfixed-range=@var{register-range} @gol -+-mea32 -mea64 @gol -+-maddress-space-conversion -mno-address-space-conversion @gol -+-mcache-size=@var{cache-size} @gol -+-matomic-updates -mno-atomic-updates} -+ -+@emph{System V Options} -+@gccoptlist{-Qy -Qn -YP,@var{paths} -Ym,@var{dir}} -+ -+@emph{TILE-Gx Options} -+@gccoptlist{-mcpu=CPU -m32 -m64} -+ -+@emph{TILEPro Options} -+@gccoptlist{-mcpu=CPU -m32} -+ -+@emph{V850 Options} -+@gccoptlist{-mlong-calls -mno-long-calls -mep -mno-ep @gol -+-mprolog-function -mno-prolog-function -mspace @gol -+-mtda=@var{n} -msda=@var{n} -mzda=@var{n} @gol -+-mapp-regs -mno-app-regs @gol -+-mdisable-callt -mno-disable-callt @gol -+-mv850e2v3 @gol -+-mv850e2 @gol -+-mv850e1 -mv850es @gol -+-mv850e @gol -+-mv850 -mbig-switch} -+ -+@emph{VAX Options} -+@gccoptlist{-mg -mgnu -munix} -+ -+@emph{VxWorks Options} -+@gccoptlist{-mrtp -non-static -Bstatic -Bdynamic @gol -+-Xbind-lazy -Xbind-now} -+ -+@emph{x86-64 Options} -+See i386 and x86-64 Options. -+ -+@emph{Xstormy16 Options} -+@gccoptlist{-msim} -+ -+@emph{Xtensa Options} -+@gccoptlist{-mconst16 -mno-const16 @gol -+-mfused-madd -mno-fused-madd @gol -+-mforce-no-pic @gol -+-mserialize-volatile -mno-serialize-volatile @gol -+-mtext-section-literals -mno-text-section-literals @gol -+-mtarget-align -mno-target-align @gol -+-mlongcalls -mno-longcalls} -+ -+@emph{zSeries Options} -+See S/390 and zSeries Options. -+ -+@item Code Generation Options -+@xref{Code Gen Options,,Options for Code Generation Conventions}. -+@gccoptlist{-fcall-saved-@var{reg} -fcall-used-@var{reg} @gol -+-ffixed-@var{reg} -fexceptions @gol -+-fnon-call-exceptions -funwind-tables @gol -+-fasynchronous-unwind-tables @gol -+-finhibit-size-directive -finstrument-functions @gol -+-finstrument-functions-exclude-function-list=@var{sym},@var{sym},@dots{} @gol -+-finstrument-functions-exclude-file-list=@var{file},@var{file},@dots{} @gol -+-fno-common -fno-ident @gol -+-fpcc-struct-return -fpic -fPIC -fpie -fPIE @gol -+-fno-jump-tables @gol -+-frecord-gcc-switches @gol -+-freg-struct-return -fshort-enums @gol -+-fshort-double -fshort-wchar @gol -+-fverbose-asm -fpack-struct[=@var{n}] -fstack-check @gol -+-fstack-limit-register=@var{reg} -fstack-limit-symbol=@var{sym} @gol -+-fno-stack-limit -fsplit-stack @gol -+-fleading-underscore -ftls-model=@var{model} @gol -+-ftrapv -fwrapv -fbounds-check @gol -+-fvisibility -fstrict-volatile-bitfields} -+@end table -+ -+@menu -+* Overall Options:: Controlling the kind of output: -+ an executable, object files, assembler files, -+ or preprocessed source. -+* C Dialect Options:: Controlling the variant of C language compiled. -+* C++ Dialect Options:: Variations on C++. -+* Objective-C and Objective-C++ Dialect Options:: Variations on Objective-C -+ and Objective-C++. -+* Language Independent Options:: Controlling how diagnostics should be -+ formatted. -+* Warning Options:: How picky should the compiler be? -+* Debugging Options:: Symbol tables, measurements, and debugging dumps. -+* Optimize Options:: How much optimization? -+* Preprocessor Options:: Controlling header files and macro definitions. -+ Also, getting dependency information for Make. -+* Assembler Options:: Passing options to the assembler. -+* Link Options:: Specifying libraries and so on. -+* Directory Options:: Where to find header files and libraries. -+ Where to find the compiler executable files. -+* Spec Files:: How to pass switches to sub-processes. -+* Target Options:: Running a cross-compiler, or an old version of GCC. -+@end menu -+ -+@node Overall Options -+@section Options Controlling the Kind of Output -+ -+Compilation can involve up to four stages: preprocessing, compilation -+proper, assembly and linking, always in that order. GCC is capable of -+preprocessing and compiling several files either into several -+assembler input files, or into one assembler input file; then each -+assembler input file produces an object file, and linking combines all -+the object files (those newly compiled, and those specified as input) -+into an executable file. +@@ -7428,6 +7445,24 @@ + variable names which more closely resemble the original variables. This flag + is enabled by default at @option{-O} and higher. + ++@item -ftree-coalesce-inlined-vars ++Tell the copyrename pass (see @option{-ftree-copyrename}) to attempt to ++combine small user-defined variables too, but only if they were inlined ++from other functions. It is a more limited form of ++@option{-ftree-coalesce-vars}. This may harm debug information of such ++inlined variables, but it will keep variables of the inlined-into ++function apart from each other, such that they are more likely to ++contain the expected values in a debugging session. This was the ++default in GCC versions older than 4.7. ++ ++@item -ftree-coalesce-vars ++Tell the copyrename pass (see @option{-ftree-copyrename}) to attempt to ++combine small user-defined variables too, instead of just compiler ++temporaries. This may severely limit the ability to debug an optimized ++program compiled with @option{-fno-var-tracking-assignments}. In the ++negated form, this flag prevents SSA coalescing of user variables, ++including inlined ones. This option is enabled by default. ++ + @item -ftree-ter + @opindex ftree-ter + Perform temporary expression replacement during the SSA->normal phase. Single +@@ -10329,6 +10364,7 @@ + @c in Machine Dependent Options + + @menu ++* AArch64 Options:: + * Adapteva Epiphany Options:: + * ARM Options:: + * AVR Options:: +@@ -10537,6 +10573,125 @@ + + @end table + ++@node AArch64 Options ++@subsection AArch64 Options ++@cindex AArch64 Options + -+@cindex file name suffix -+For any given input file, the file name suffix determines what kind of -+compilation is done: ++These options are defined for AArch64 implementations: + +@table @gcctabopt -+@item @var{file}.c -+C source code that must be preprocessed. -+ -+@item @var{file}.i -+C source code that should not be preprocessed. -+ -+@item @var{file}.ii -+C++ source code that should not be preprocessed. -+ -+@item @var{file}.m -+Objective-C source code. Note that you must link with the @file{libobjc} -+library to make an Objective-C program work. -+ -+@item @var{file}.mi -+Objective-C source code that should not be preprocessed. -+ -+@item @var{file}.mm -+@itemx @var{file}.M -+Objective-C++ source code. Note that you must link with the @file{libobjc} -+library to make an Objective-C++ program work. Note that @samp{.M} refers -+to a literal capital M@. -+ -+@item @var{file}.mii -+Objective-C++ source code that should not be preprocessed. -+ -+@item @var{file}.h -+C, C++, Objective-C or Objective-C++ header file to be turned into a -+precompiled header (default), or C, C++ header file to be turned into an -+Ada spec (via the @option{-fdump-ada-spec} switch). + -+@item @var{file}.cc -+@itemx @var{file}.cp -+@itemx @var{file}.cxx -+@itemx @var{file}.cpp -+@itemx @var{file}.CPP -+@itemx @var{file}.c++ -+@itemx @var{file}.C -+C++ source code that must be preprocessed. Note that in @samp{.cxx}, -+the last two letters must both be literally @samp{x}. Likewise, -+@samp{.C} refers to a literal capital C@. -+ -+@item @var{file}.mm -+@itemx @var{file}.M -+Objective-C++ source code that must be preprocessed. -+ -+@item @var{file}.mii -+Objective-C++ source code that should not be preprocessed. -+ -+@item @var{file}.hh -+@itemx @var{file}.H -+@itemx @var{file}.hp -+@itemx @var{file}.hxx -+@itemx @var{file}.hpp -+@itemx @var{file}.HPP -+@itemx @var{file}.h++ -+@itemx @var{file}.tcc -+C++ header file to be turned into a precompiled header or Ada spec. ++@item -mbig-endian ++@opindex mbig-endian ++Generate big-endian code. This is the default when GCC is configured for an ++@samp{aarch64_be-*-*} target. + -+@item @var{file}.f -+@itemx @var{file}.for -+@itemx @var{file}.ftn -+Fixed form Fortran source code that should not be preprocessed. ++@item -mgeneral-regs-only ++@opindex mgeneral-regs-only ++Generate code which uses only the general registers. + -+@item @var{file}.F -+@itemx @var{file}.FOR -+@itemx @var{file}.fpp -+@itemx @var{file}.FPP -+@itemx @var{file}.FTN -+Fixed form Fortran source code that must be preprocessed (with the traditional -+preprocessor). ++@item -mlittle-endian ++@opindex mlittle-endian ++Generate little-endian code. This is the default when GCC is configured for an ++@samp{aarch64-*-*} but not an @samp{aarch64_be-*-*} target. + -+@item @var{file}.f90 -+@itemx @var{file}.f95 -+@itemx @var{file}.f03 -+@itemx @var{file}.f08 -+Free form Fortran source code that should not be preprocessed. ++@item -mcmodel=tiny ++@opindex mcmodel=tiny ++Generate code for the tiny code model. The program and its statically defined ++symbols must be within 1GB of each other. Pointers are 64 bits. Programs can ++be statically or dynamically linked. This model is not fully implemented and ++mostly treated as "small". + -+@item @var{file}.F90 -+@itemx @var{file}.F95 -+@itemx @var{file}.F03 -+@itemx @var{file}.F08 -+Free form Fortran source code that must be preprocessed (with the -+traditional preprocessor). ++@item -mcmodel=small ++@opindex mcmodel=small ++Generate code for the small code model. The program and its statically defined ++symbols must be within 4GB of each other. Pointers are 64 bits. Programs can ++be statically or dynamically linked. This is the default code model. + -+@item @var{file}.go -+Go source code. ++@item -mcmodel=large ++@opindex mcmodel=large ++Generate code for the large code model. This makes no assumptions about ++addresses and sizes of sections. Pointers are 64 bits. Programs can be ++statically linked only. + -+@c FIXME: Descriptions of Java file types. -+@c @var{file}.java -+@c @var{file}.class -+@c @var{file}.zip -+@c @var{file}.jar ++@item -mstrict-align ++@opindex mstrict-align ++Do not assume that unaligned memory references will be handled by the system. + -+@item @var{file}.ads -+Ada source code file that contains a library unit declaration (a -+declaration of a package, subprogram, or generic, or a generic -+instantiation), or a library unit renaming declaration (a package, -+generic, or subprogram renaming declaration). Such files are also -+called @dfn{specs}. ++@item -momit-leaf-frame-pointer ++@item -mno-omit-leaf-frame-pointer ++@opindex momit-leaf-frame-pointer ++@opindex mno-omit-leaf-frame-pointer ++Omit or keep the frame pointer in leaf functions. The former behaviour is the ++default. + -+@item @var{file}.adb -+Ada source code file containing a library unit body (a subprogram or -+package body). Such files are also called @dfn{bodies}. ++@item -mtls-dialect=desc ++@opindex mtls-dialect=desc ++Use TLS descriptors as the thread-local storage mechanism for dynamic accesses ++of TLS variables. This is the default. ++ ++@item -mtls-dialect=traditional ++@opindex mtls-dialect=traditional ++Use traditional TLS as the thread-local storage mechanism for dynamic accesses ++of TLS variables. + -+@c GCC also knows about some suffixes for languages not yet included: -+@c Pascal: -+@c @var{file}.p -+@c @var{file}.pas -+@c Ratfor: -+@c @var{file}.r ++@item -march=@var{name} ++@opindex march ++Specify the name of the target architecture, optionally suffixed by one or ++more feature modifiers. This option has the form ++@option{-march=@var{arch}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}, where the ++only value for @var{arch} is @samp{armv8-a}. The possible values for ++@var{feature} are documented in the sub-section below. + -+@item @var{file}.s -+Assembler code. ++Where conflicting feature modifiers are specified, the right-most feature is ++used. + -+@item @var{file}.S -+@itemx @var{file}.sx -+Assembler code that must be preprocessed. ++GCC uses this name to determine what kind of instructions it can emit when ++generating assembly code. This option can be used in conjunction with or ++instead of the @option{-mcpu=} option. + -+@item @var{other} -+An object file to be fed straight into linking. -+Any file name with no recognized suffix is treated this way. -+@end table ++@item -mcpu=@var{name} ++@opindex mcpu ++Specify the name of the target processor, optionally suffixed by one or more ++feature modifiers. This option has the form ++@option{-mcpu=@var{cpu}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}, where the ++possible values for @var{cpu} are @samp{generic}, @samp{large}. The ++possible values for @var{feature} are documented in the sub-section ++below. + -+@opindex x -+You can specify the input language explicitly with the @option{-x} option: ++Where conflicting feature modifiers are specified, the right-most feature is ++used. + -+@table @gcctabopt -+@item -x @var{language} -+Specify explicitly the @var{language} for the following input files -+(rather than letting the compiler choose a default based on the file -+name suffix). This option applies to all following input files until -+the next @option{-x} option. Possible values for @var{language} are: -+@smallexample -+c c-header cpp-output -+c++ c++-header c++-cpp-output -+objective-c objective-c-header objective-c-cpp-output -+objective-c++ objective-c++-header objective-c++-cpp-output -+assembler assembler-with-cpp -+ada -+f77 f77-cpp-input f95 f95-cpp-input -+go -+java -+@end smallexample ++GCC uses this name to determine what kind of instructions it can emit when ++generating assembly code. + -+@item -x none -+Turn off any specification of a language, so that subsequent files are -+handled according to their file name suffixes (as they are if @option{-x} -+has not been used at all). ++@item -mtune=@var{name} ++@opindex mtune ++Specify the name of the processor to tune the performance for. The code will ++be tuned as if the target processor were of the type specified in this option, ++but still using instructions compatible with the target processor specified ++by a @option{-mcpu=} option. This option cannot be suffixed by feature ++modifiers. + -+@item -pass-exit-codes -+@opindex pass-exit-codes -+Normally the @command{gcc} program will exit with the code of 1 if any -+phase of the compiler returns a non-success return code. If you specify -+@option{-pass-exit-codes}, the @command{gcc} program will instead return with -+numerically highest error produced by any phase that returned an error -+indication. The C, C++, and Fortran frontends return 4, if an internal -+compiler error is encountered. +@end table + -+If you only want some of the stages of compilation, you can use -+@option{-x} (or filename suffixes) to tell @command{gcc} where to start, and -+one of the options @option{-c}, @option{-S}, or @option{-E} to say where -+@command{gcc} is to stop. Note that some combinations (for example, -+@samp{-x cpp-output -E}) instruct @command{gcc} to do nothing at all. -+ -+@table @gcctabopt -+@item -c -+@opindex c -+Compile or assemble the source files, but do not link. The linking -+stage simply is not done. The ultimate output is in the form of an -+object file for each source file. -+ -+By default, the object file name for a source file is made by replacing -+the suffix @samp{.c}, @samp{.i}, @samp{.s}, etc., with @samp{.o}. -+ -+Unrecognized input files, not requiring compilation or assembly, are -+ignored. -+ -+@item -S -+@opindex S -+Stop after the stage of compilation proper; do not assemble. The output -+is in the form of an assembler code file for each non-assembler input -+file specified. -+ -+By default, the assembler file name for a source file is made by -+replacing the suffix @samp{.c}, @samp{.i}, etc., with @samp{.s}. -+ -+Input files that don't require compilation are ignored. -+ -+@item -E -+@opindex E -+Stop after the preprocessing stage; do not run the compiler proper. The -+output is in the form of preprocessed source code, which is sent to the -+standard output. -+ -+Input files that don't require preprocessing are ignored. -+ -+@cindex output file option -+@item -o @var{file} -+@opindex o -+Place output in file @var{file}. This applies regardless to whatever -+sort of output is being produced, whether it be an executable file, -+an object file, an assembler file or preprocessed C code. -+ -+If @option{-o} is not specified, the default is to put an executable -+file in @file{a.out}, the object file for -+@file{@var{source}.@var{suffix}} in @file{@var{source}.o}, its -+assembler file in @file{@var{source}.s}, a precompiled header file in -+@file{@var{source}.@var{suffix}.gch}, and all preprocessed C source on -+standard output. -+ -+@item -v -+@opindex v -+Print (on standard error output) the commands executed to run the stages -+of compilation. Also print the version number of the compiler driver -+program and of the preprocessor and the compiler proper. ++@subsubsection @option{-march} and @option{-mcpu} feature modifiers ++@cindex @option{-march} feature modifiers ++@cindex @option{-mcpu} feature modifiers ++Feature modifiers used with @option{-march} and @option{-mcpu} can be one ++the following: ++ ++@table @samp ++@item crypto ++Enable Crypto extension. This implies Advanced SIMD is enabled. ++@item fp ++Enable floating-point instructions. ++@item simd ++Enable Advanced SIMD instructions. This implies floating-point instructions ++are enabled. This is the default for all current possible values for options ++@option{-march} and @option{-mcpu=}. ++@end table ++ + @node ARM Options + @subsection ARM Options + @cindex ARM options +@@ -10948,6 +11103,11 @@ + preprocessor symbol @code{__ARM_FEATURE_UNALIGNED} will also be + defined. + ++@item -mneon-for-64bits ++@opindex mneon-for-64bits ++Enables using Neon to handle scalar 64-bits operations. This is ++disabled by default since the cost of moving data from core registers ++to Neon is high. + @end table + + @node AVR Options +--- a/src/gcc/doc/md.texi ++++ b/src/gcc/doc/md.texi +@@ -1653,6 +1653,62 @@ + the meanings of that architecture's constraints. + + @table @emph ++@item AArch64 family---@file{config/aarch64/constraints.md} ++@table @code ++@item k ++The stack pointer register (@code{SP}) + -+@item -### -+@opindex ### -+Like @option{-v} except the commands are not executed and arguments -+are quoted unless they contain only alphanumeric characters or @code{./-_}. -+This is useful for shell scripts to capture the driver-generated command lines. ++@item w ++Floating point or SIMD vector register + -+@item -pipe -+@opindex pipe -+Use pipes rather than temporary files for communication between the -+various stages of compilation. This fails to work on some systems where -+the assembler is unable to read from a pipe; but the GNU assembler has -+no trouble. ++@item I ++Integer constant that is valid as an immediate operand in an @code{ADD} ++instruction + -+@item --help -+@opindex help -+Print (on the standard output) a description of the command-line options -+understood by @command{gcc}. If the @option{-v} option is also specified -+then @option{--help} will also be passed on to the various processes -+invoked by @command{gcc}, so that they can display the command-line options -+they accept. If the @option{-Wextra} option has also been specified -+(prior to the @option{--help} option), then command-line options that -+have no documentation associated with them will also be displayed. ++@item J ++Integer constant that is valid as an immediate operand in a @code{SUB} ++instruction (once negated) + -+@item --target-help -+@opindex target-help -+Print (on the standard output) a description of target-specific command-line -+options for each tool. For some targets extra target-specific -+information may also be printed. ++@item K ++Integer constant that can be used with a 32-bit logical instruction + -+@item --help=@{@var{class}@r{|[}^@r{]}@var{qualifier}@}@r{[},@dots{}@r{]} -+Print (on the standard output) a description of the command-line -+options understood by the compiler that fit into all specified classes -+and qualifiers. These are the supported classes: ++@item L ++Integer constant that can be used with a 64-bit logical instruction + -+@table @asis -+@item @samp{optimizers} -+This will display all of the optimization options supported by the -+compiler. ++@item M ++Integer constant that is valid as an immediate operand in a 32-bit @code{MOV} ++pseudo instruction. The @code{MOV} may be assembled to one of several different ++machine instructions depending on the value + -+@item @samp{warnings} -+This will display all of the options controlling warning messages -+produced by the compiler. ++@item N ++Integer constant that is valid as an immediate operand in a 64-bit @code{MOV} ++pseudo instruction + -+@item @samp{target} -+This will display target-specific options. Unlike the -+@option{--target-help} option however, target-specific options of the -+linker and assembler will not be displayed. This is because those -+tools do not currently support the extended @option{--help=} syntax. ++@item S ++An absolute symbolic address or a label reference + -+@item @samp{params} -+This will display the values recognized by the @option{--param} -+option. ++@item Y ++Floating point constant zero + -+@item @var{language} -+This will display the options supported for @var{language}, where -+@var{language} is the name of one of the languages supported in this -+version of GCC. ++@item Z ++Integer constant zero + -+@item @samp{common} -+This will display the options that are common to all languages. -+@end table ++@item Usa ++An absolute symbolic address + -+These are the supported qualifiers: ++@item Ush ++The high part (bits 12 and upwards) of the pc-relative address of a symbol ++within 4GB of the instruction + -+@table @asis -+@item @samp{undocumented} -+Display only those options that are undocumented. ++@item Q ++A memory address which uses a single base register with no offset + -+@item @samp{joined} -+Display options taking an argument that appears after an equal -+sign in the same continuous piece of text, such as: -+@samp{--help=target}. ++@item Ump ++A memory address suitable for a load/store pair instruction in SI, DI, SF and ++DF modes + -+@item @samp{separate} -+Display options taking an argument that appears as a separate word -+following the original option, such as: @samp{-o output-file}. +@end table + -+Thus for example to display all the undocumented target-specific -+switches supported by the compiler the following can be used: -+ -+@smallexample -+--help=target,undocumented -+@end smallexample -+ -+The sense of a qualifier can be inverted by prefixing it with the -+@samp{^} character, so for example to display all binary warning -+options (i.e., ones that are either on or off and that do not take an -+argument) that have a description, use: -+ -+@smallexample -+--help=warnings,^joined,^undocumented -+@end smallexample -+ -+The argument to @option{--help=} should not consist solely of inverted -+qualifiers. -+ -+Combining several classes is possible, although this usually -+restricts the output by so much that there is nothing to display. One -+case where it does work however is when one of the classes is -+@var{target}. So for example to display all the target-specific -+optimization options the following can be used: -+ -+@smallexample -+--help=target,optimizers -+@end smallexample -+ -+The @option{--help=} option can be repeated on the command line. Each -+successive use will display its requested class of options, skipping -+those that have already been displayed. + @item ARM family---@file{config/arm/arm.h} + @table @code + @item f +@@ -4736,6 +4792,10 @@ + Vector shift and rotate instructions that take vectors as operand 2 + instead of a scalar type. + ++@cindex @code{bswap@var{m}2} instruction pattern ++@item @samp{bswap@var{m}2} ++Reverse the order of bytes of operand 1 and store the result in operand 0. ++ + @cindex @code{neg@var{m}2} instruction pattern + @cindex @code{ssneg@var{m}2} instruction pattern + @cindex @code{usneg@var{m}2} instruction pattern +@@ -8888,6 +8948,7 @@ + @menu + * Mode Iterators:: Generating variations of patterns for different modes. + * Code Iterators:: Doing the same for codes. ++* Int Iterators:: Doing the same for integers. + @end menu + + @node Mode Iterators +@@ -9159,4 +9220,81 @@ + @dots{} + @end smallexample + ++@node Int Iterators ++@subsection Int Iterators ++@cindex int iterators in @file{.md} files ++@findex define_int_iterator ++@findex define_int_attr + -+If the @option{-Q} option appears on the command line before the -+@option{--help=} option, then the descriptive text displayed by -+@option{--help=} is changed. Instead of describing the displayed -+options, an indication is given as to whether the option is enabled, -+disabled or set to a specific value (assuming that the compiler -+knows this at the point where the @option{--help=} option is used). ++Int iterators operate in a similar way to code iterators. @xref{Code Iterators}. + -+Here is a truncated example from the ARM port of @command{gcc}: ++The construct: + +@smallexample -+ % gcc -Q -mabi=2 --help=target -c -+ The following options are target specific: -+ -mabi= 2 -+ -mabort-on-noreturn [disabled] -+ -mapcs [disabled] ++(define_int_iterator @var{name} [(@var{int1} "@var{cond1}") @dots{} (@var{intn} "@var{condn}")]) +@end smallexample + -+The output is sensitive to the effects of previous command-line -+options, so for example it is possible to find out which optimizations -+are enabled at @option{-O2} by using: ++defines a pseudo integer constant @var{name} that can be instantiated as ++@var{inti} if condition @var{condi} is true. Each @var{int} ++must have the same rtx format. @xref{RTL Classes}. Int iterators can appear ++in only those rtx fields that have 'i' as the specifier. This means that ++each @var{int} has to be a constant defined using define_constant or ++define_c_enum. + -+@smallexample -+-Q -O2 --help=optimizers -+@end smallexample ++As with mode and code iterators, each pattern that uses @var{name} will be ++expanded @var{n} times, once with all uses of @var{name} replaced by ++@var{int1}, once with all uses replaced by @var{int2}, and so on. ++@xref{Defining Mode Iterators}. + -+Alternatively you can discover which binary optimizations are enabled -+by @option{-O3} by using: ++It is possible to define attributes for ints as well as for codes and modes. ++Attributes are defined using: + +@smallexample -+gcc -c -Q -O3 --help=optimizers > /tmp/O3-opts -+gcc -c -Q -O2 --help=optimizers > /tmp/O2-opts -+diff /tmp/O2-opts /tmp/O3-opts | grep enabled ++(define_int_attr @var{name} [(@var{int1} "@var{value1}") @dots{} (@var{intn} "@var{valuen}")]) +@end smallexample + -+@item -no-canonical-prefixes -+@opindex no-canonical-prefixes -+Do not expand any symbolic links, resolve references to @samp{/../} -+or @samp{/./}, or make the path absolute when generating a relative -+prefix. -+ -+@item --version -+@opindex version -+Display the version number and copyrights of the invoked GCC@. -+ -+@item -wrapper -+@opindex wrapper -+Invoke all subcommands under a wrapper program. The name of the -+wrapper program and its parameters are passed as a comma separated -+list. ++Here's an example of int iterators in action, taken from the ARM port: + +@smallexample -+gcc -c t.c -wrapper gdb,--args -+@end smallexample -+ -+This will invoke all subprograms of @command{gcc} under -+@samp{gdb --args}, thus the invocation of @command{cc1} will be -+@samp{gdb --args cc1 @dots{}}. -+ -+@item -fplugin=@var{name}.so -+Load the plugin code in file @var{name}.so, assumed to be a -+shared object to be dlopen'd by the compiler. The base name of -+the shared object file is used to identify the plugin for the -+purposes of argument parsing (See -+@option{-fplugin-arg-@var{name}-@var{key}=@var{value}} below). -+Each plugin should define the callback functions specified in the -+Plugins API. -+ -+@item -fplugin-arg-@var{name}-@var{key}=@var{value} -+Define an argument called @var{key} with a value of @var{value} -+for the plugin called @var{name}. -+ -+@item -fdump-ada-spec@r{[}-slim@r{]} -+For C and C++ source and include files, generate corresponding Ada -+specs. @xref{Generating Ada Bindings for C and C++ headers,,, gnat_ugn, -+GNAT User's Guide}, which provides detailed documentation on this feature. -+ -+@item -fdump-go-spec=@var{file} -+For input files in any language, generate corresponding Go -+declarations in @var{file}. This generates Go @code{const}, -+@code{type}, @code{var}, and @code{func} declarations which may be a -+useful way to start writing a Go interface to code written in some -+other language. -+ -+@include @value{srcdir}/../libiberty/at-file.texi -+@end table -+ -+@node Invoking G++ -+@section Compiling C++ Programs -+ -+@cindex suffixes for C++ source -+@cindex C++ source file suffixes -+C++ source files conventionally use one of the suffixes @samp{.C}, -+@samp{.cc}, @samp{.cpp}, @samp{.CPP}, @samp{.c++}, @samp{.cp}, or -+@samp{.cxx}; C++ header files often use @samp{.hh}, @samp{.hpp}, -+@samp{.H}, or (for shared template code) @samp{.tcc}; and -+preprocessed C++ files use the suffix @samp{.ii}. GCC recognizes -+files with these names and compiles them as C++ programs even if you -+call the compiler the same way as for compiling C programs (usually -+with the name @command{gcc}). -+ -+@findex g++ -+@findex c++ -+However, the use of @command{gcc} does not add the C++ library. -+@command{g++} is a program that calls GCC and treats @samp{.c}, -+@samp{.h} and @samp{.i} files as C++ source files instead of C source -+files unless @option{-x} is used, and automatically specifies linking -+against the C++ library. This program is also useful when -+precompiling a C header file with a @samp{.h} extension for use in C++ -+compilations. On many systems, @command{g++} is also installed with -+the name @command{c++}. -+ -+@cindex invoking @command{g++} -+When you compile C++ programs, you may specify many of the same -+command-line options that you use for compiling programs in any -+language; or command-line options meaningful for C and related -+languages; or options that are meaningful only for C++ programs. -+@xref{C Dialect Options,,Options Controlling C Dialect}, for -+explanations of options for languages related to C@. -+@xref{C++ Dialect Options,,Options Controlling C++ Dialect}, for -+explanations of options that are meaningful only for C++ programs. -+ -+@node C Dialect Options -+@section Options Controlling C Dialect -+@cindex dialect options -+@cindex language dialect options -+@cindex options, dialect -+ -+The following options control the dialect of C (or languages derived -+from C, such as C++, Objective-C and Objective-C++) that the compiler -+accepts: -+ -+@table @gcctabopt -+@cindex ANSI support -+@cindex ISO support -+@item -ansi -+@opindex ansi -+In C mode, this is equivalent to @samp{-std=c90}. In C++ mode, it is -+equivalent to @samp{-std=c++98}. -+ -+This turns off certain features of GCC that are incompatible with ISO -+C90 (when compiling C code), or of standard C++ (when compiling C++ code), -+such as the @code{asm} and @code{typeof} keywords, and -+predefined macros such as @code{unix} and @code{vax} that identify the -+type of system you are using. It also enables the undesirable and -+rarely used ISO trigraph feature. For the C compiler, -+it disables recognition of C++ style @samp{//} comments as well as -+the @code{inline} keyword. -+ -+The alternate keywords @code{__asm__}, @code{__extension__}, -+@code{__inline__} and @code{__typeof__} continue to work despite -+@option{-ansi}. You would not want to use them in an ISO C program, of -+course, but it is useful to put them in header files that might be included -+in compilations done with @option{-ansi}. Alternate predefined macros -+such as @code{__unix__} and @code{__vax__} are also available, with or -+without @option{-ansi}. -+ -+The @option{-ansi} option does not cause non-ISO programs to be -+rejected gratuitously. For that, @option{-pedantic} is required in -+addition to @option{-ansi}. @xref{Warning Options}. -+ -+The macro @code{__STRICT_ANSI__} is predefined when the @option{-ansi} -+option is used. Some header files may notice this macro and refrain -+from declaring certain functions or defining certain macros that the -+ISO standard doesn't call for; this is to avoid interfering with any -+programs that might use these names for other things. -+ -+Functions that would normally be built in but do not have semantics -+defined by ISO C (such as @code{alloca} and @code{ffs}) are not built-in -+functions when @option{-ansi} is used. @xref{Other Builtins,,Other -+built-in functions provided by GCC}, for details of the functions -+affected. -+ -+@item -std= -+@opindex std -+Determine the language standard. @xref{Standards,,Language Standards -+Supported by GCC}, for details of these standard versions. This option -+is currently only supported when compiling C or C++. -+ -+The compiler can accept several base standards, such as @samp{c90} or -+@samp{c++98}, and GNU dialects of those standards, such as -+@samp{gnu90} or @samp{gnu++98}. By specifying a base standard, the -+compiler will accept all programs following that standard and those -+using GNU extensions that do not contradict it. For example, -+@samp{-std=c90} turns off certain features of GCC that are -+incompatible with ISO C90, such as the @code{asm} and @code{typeof} -+keywords, but not other GNU extensions that do not have a meaning in -+ISO C90, such as omitting the middle term of a @code{?:} -+expression. On the other hand, by specifying a GNU dialect of a -+standard, all features the compiler support are enabled, even when -+those features change the meaning of the base standard and some -+strict-conforming programs may be rejected. The particular standard -+is used by @option{-pedantic} to identify which features are GNU -+extensions given that version of the standard. For example -+@samp{-std=gnu90 -pedantic} would warn about C++ style @samp{//} -+comments, while @samp{-std=gnu99 -pedantic} would not. -+ -+A value for this option must be provided; possible values are -+ -+@table @samp -+@item c90 -+@itemx c89 -+@itemx iso9899:1990 -+Support all ISO C90 programs (certain GNU extensions that conflict -+with ISO C90 are disabled). Same as @option{-ansi} for C code. -+ -+@item iso9899:199409 -+ISO C90 as modified in amendment 1. -+ -+@item c99 -+@itemx c9x -+@itemx iso9899:1999 -+@itemx iso9899:199x -+ISO C99. Note that this standard is not yet fully supported; see -+@w{@uref{http://gcc.gnu.org/gcc-4.7/c99status.html}} for more information. The -+names @samp{c9x} and @samp{iso9899:199x} are deprecated. -+ -+@item c11 -+@itemx c1x -+@itemx iso9899:2011 -+ISO C11, the 2011 revision of the ISO C standard. -+Support is incomplete and experimental. The name @samp{c1x} is -+deprecated. -+ -+@item gnu90 -+@itemx gnu89 -+GNU dialect of ISO C90 (including some C99 features). This -+is the default for C code. -+ -+@item gnu99 -+@itemx gnu9x -+GNU dialect of ISO C99. When ISO C99 is fully implemented in GCC, -+this will become the default. The name @samp{gnu9x} is deprecated. -+ -+@item gnu11 -+@item gnu1x -+GNU dialect of ISO C11. Support is incomplete and experimental. The -+name @samp{gnu1x} is deprecated. -+ -+@item c++98 -+The 1998 ISO C++ standard plus amendments. Same as @option{-ansi} for -+C++ code. -+ -+@item gnu++98 -+GNU dialect of @option{-std=c++98}. This is the default for -+C++ code. -+ -+@item c++11 -+The 2011 ISO C++ standard plus amendments. Support for C++11 is still -+experimental, and may change in incompatible ways in future releases. -+ -+@item gnu++11 -+GNU dialect of @option{-std=c++11}. Support for C++11 is still -+experimental, and may change in incompatible ways in future releases. -+@end table -+ -+@item -fgnu89-inline -+@opindex fgnu89-inline -+The option @option{-fgnu89-inline} tells GCC to use the traditional -+GNU semantics for @code{inline} functions when in C99 mode. -+@xref{Inline,,An Inline Function is As Fast As a Macro}. This option -+is accepted and ignored by GCC versions 4.1.3 up to but not including -+4.3. In GCC versions 4.3 and later it changes the behavior of GCC in -+C99 mode. Using this option is roughly equivalent to adding the -+@code{gnu_inline} function attribute to all inline functions -+(@pxref{Function Attributes}). -+ -+The option @option{-fno-gnu89-inline} explicitly tells GCC to use the -+C99 semantics for @code{inline} when in C99 or gnu99 mode (i.e., it -+specifies the default behavior). This option was first supported in -+GCC 4.3. This option is not supported in @option{-std=c90} or -+@option{-std=gnu90} mode. -+ -+The preprocessor macros @code{__GNUC_GNU_INLINE__} and -+@code{__GNUC_STDC_INLINE__} may be used to check which semantics are -+in effect for @code{inline} functions. @xref{Common Predefined -+Macros,,,cpp,The C Preprocessor}. -+ -+@item -aux-info @var{filename} -+@opindex aux-info -+Output to the given filename prototyped declarations for all functions -+declared and/or defined in a translation unit, including those in header -+files. This option is silently ignored in any language other than C@. -+ -+Besides declarations, the file indicates, in comments, the origin of -+each declaration (source file and line), whether the declaration was -+implicit, prototyped or unprototyped (@samp{I}, @samp{N} for new or -+@samp{O} for old, respectively, in the first character after the line -+number and the colon), and whether it came from a declaration or a -+definition (@samp{C} or @samp{F}, respectively, in the following -+character). In the case of function definitions, a K&R-style list of -+arguments followed by their declarations is also provided, inside -+comments, after the declaration. -+ -+@item -fallow-parameterless-variadic-functions -+Accept variadic functions without named parameters. -+ -+Although it is possible to define such a function, this is not very -+useful as it is not possible to read the arguments. This is only -+supported for C as this construct is allowed by C++. -+ -+@item -fno-asm -+@opindex fno-asm -+Do not recognize @code{asm}, @code{inline} or @code{typeof} as a -+keyword, so that code can use these words as identifiers. You can use -+the keywords @code{__asm__}, @code{__inline__} and @code{__typeof__} -+instead. @option{-ansi} implies @option{-fno-asm}. -+ -+In C++, this switch only affects the @code{typeof} keyword, since -+@code{asm} and @code{inline} are standard keywords. You may want to -+use the @option{-fno-gnu-keywords} flag instead, which has the same -+effect. In C99 mode (@option{-std=c99} or @option{-std=gnu99}), this -+switch only affects the @code{asm} and @code{typeof} keywords, since -+@code{inline} is a standard keyword in ISO C99. -+ -+@item -fno-builtin -+@itemx -fno-builtin-@var{function} -+@opindex fno-builtin -+@cindex built-in functions -+Don't recognize built-in functions that do not begin with -+@samp{__builtin_} as prefix. @xref{Other Builtins,,Other built-in -+functions provided by GCC}, for details of the functions affected, -+including those which are not built-in functions when @option{-ansi} or -+@option{-std} options for strict ISO C conformance are used because they -+do not have an ISO standard meaning. ++(define_int_iterator QABSNEG [UNSPEC_VQABS UNSPEC_VQNEG]) + -+GCC normally generates special code to handle certain built-in functions -+more efficiently; for instance, calls to @code{alloca} may become single -+instructions which adjust the stack directly, and calls to @code{memcpy} -+may become inline copy loops. The resulting code is often both smaller -+and faster, but since the function calls no longer appear as such, you -+cannot set a breakpoint on those calls, nor can you change the behavior -+of the functions by linking with a different library. In addition, -+when a function is recognized as a built-in function, GCC may use -+information about that function to warn about problems with calls to -+that function, or to generate more efficient code, even if the -+resulting code still contains calls to that function. For example, -+warnings are given with @option{-Wformat} for bad calls to -+@code{printf}, when @code{printf} is built in, and @code{strlen} is -+known not to modify global memory. ++(define_int_attr absneg [(UNSPEC_VQABS "abs") (UNSPEC_VQNEG "neg")]) + -+With the @option{-fno-builtin-@var{function}} option -+only the built-in function @var{function} is -+disabled. @var{function} must not begin with @samp{__builtin_}. If a -+function is named that is not built-in in this version of GCC, this -+option is ignored. There is no corresponding -+@option{-fbuiltin-@var{function}} option; if you wish to enable -+built-in functions selectively when using @option{-fno-builtin} or -+@option{-ffreestanding}, you may define macros such as: ++(define_insn "neon_vq" ++ [(set (match_operand:VDQIW 0 "s_register_operand" "=w") ++ (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w") ++ (match_operand:SI 2 "immediate_operand" "i")] ++ QABSNEG))] ++ "TARGET_NEON" ++ "vq.\t%0, %1" ++ [(set_attr "neon_type" "neon_vqneg_vqabs")] ++) + -+@smallexample -+#define abs(n) __builtin_abs ((n)) -+#define strcpy(d, s) __builtin_strcpy ((d), (s)) +@end smallexample + -+@item -fhosted -+@opindex fhosted -+@cindex hosted environment -+ -+Assert that compilation takes place in a hosted environment. This implies -+@option{-fbuiltin}. A hosted environment is one in which the -+entire standard library is available, and in which @code{main} has a return -+type of @code{int}. Examples are nearly everything except a kernel. -+This is equivalent to @option{-fno-freestanding}. -+ -+@item -ffreestanding -+@opindex ffreestanding -+@cindex hosted environment -+ -+Assert that compilation takes place in a freestanding environment. This -+implies @option{-fno-builtin}. A freestanding environment -+is one in which the standard library may not exist, and program startup may -+not necessarily be at @code{main}. The most obvious example is an OS kernel. -+This is equivalent to @option{-fno-hosted}. -+ -+@xref{Standards,,Language Standards Supported by GCC}, for details of -+freestanding and hosted environments. -+ -+@item -fopenmp -+@opindex fopenmp -+@cindex OpenMP parallel -+Enable handling of OpenMP directives @code{#pragma omp} in C/C++ and -+@code{!$omp} in Fortran. When @option{-fopenmp} is specified, the -+compiler generates parallel code according to the OpenMP Application -+Program Interface v3.0 @w{@uref{http://www.openmp.org/}}. This option -+implies @option{-pthread}, and thus is only supported on targets that -+have support for @option{-pthread}. -+ -+@item -fgnu-tm -+@opindex fgnu-tm -+When the option @option{-fgnu-tm} is specified, the compiler will -+generate code for the Linux variant of Intel's current Transactional -+Memory ABI specification document (Revision 1.1, May 6 2009). This is -+an experimental feature whose interface may change in future versions -+of GCC, as the official specification changes. Please note that not -+all architectures are supported for this feature. -+ -+For more information on GCC's support for transactional memory, -+@xref{Enabling libitm,,The GNU Transactional Memory Library,libitm,GNU -+Transactional Memory Library}. -+ -+Note that the transactional memory feature is not supported with -+non-call exceptions (@option{-fnon-call-exceptions}). -+ -+@item -fms-extensions -+@opindex fms-extensions -+Accept some non-standard constructs used in Microsoft header files. -+ -+In C++ code, this allows member names in structures to be similar -+to previous types declarations. ++This is equivalent to: + +@smallexample -+typedef int UOW; -+struct ABC @{ -+ UOW UOW; -+@}; -+@end smallexample -+ -+Some cases of unnamed fields in structures and unions are only -+accepted with this option. @xref{Unnamed Fields,,Unnamed struct/union -+fields within structs/unions}, for details. -+ -+@item -fplan9-extensions -+Accept some non-standard constructs used in Plan 9 code. -+ -+This enables @option{-fms-extensions}, permits passing pointers to -+structures with anonymous fields to functions that expect pointers to -+elements of the type of the field, and permits referring to anonymous -+fields declared using a typedef. @xref{Unnamed Fields,,Unnamed -+struct/union fields within structs/unions}, for details. This is only -+supported for C, not C++. -+ -+@item -trigraphs -+@opindex trigraphs -+Support ISO C trigraphs. The @option{-ansi} option (and @option{-std} -+options for strict ISO C conformance) implies @option{-trigraphs}. ++(define_insn "neon_vqabs" ++ [(set (match_operand:VDQIW 0 "s_register_operand" "=w") ++ (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w") ++ (match_operand:SI 2 "immediate_operand" "i")] ++ UNSPEC_VQABS))] ++ "TARGET_NEON" ++ "vqabs.\t%0, %1" ++ [(set_attr "neon_type" "neon_vqneg_vqabs")] ++) + -+@item -no-integrated-cpp -+@opindex no-integrated-cpp -+Performs a compilation in two passes: preprocessing and compiling. This -+option allows a user supplied "cc1", "cc1plus", or "cc1obj" via the -+@option{-B} option. The user supplied compilation step can then add in -+an additional preprocessing step after normal preprocessing but before -+compiling. The default is to use the integrated cpp (internal cpp) ++(define_insn "neon_vqneg" ++ [(set (match_operand:VDQIW 0 "s_register_operand" "=w") ++ (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w") ++ (match_operand:SI 2 "immediate_operand" "i")] ++ UNSPEC_VQNEG))] ++ "TARGET_NEON" ++ "vqneg.\t%0, %1" ++ [(set_attr "neon_type" "neon_vqneg_vqabs")] ++) + -+The semantics of this option will change if "cc1", "cc1plus", and -+"cc1obj" are merged. -+ -+@cindex traditional C language -+@cindex C language, traditional -+@item -traditional -+@itemx -traditional-cpp -+@opindex traditional-cpp -+@opindex traditional -+Formerly, these options caused GCC to attempt to emulate a pre-standard -+C compiler. They are now only supported with the @option{-E} switch. -+The preprocessor continues to support a pre-standard mode. See the GNU -+CPP manual for details. -+ -+@item -fcond-mismatch -+@opindex fcond-mismatch -+Allow conditional expressions with mismatched types in the second and -+third arguments. The value of such an expression is void. This option -+is not supported for C++. -+ -+@item -flax-vector-conversions -+@opindex flax-vector-conversions -+Allow implicit conversions between vectors with differing numbers of -+elements and/or incompatible element types. This option should not be -+used for new code. -+ -+@item -funsigned-char -+@opindex funsigned-char -+Let the type @code{char} be unsigned, like @code{unsigned char}. -+ -+Each kind of machine has a default for what @code{char} should -+be. It is either like @code{unsigned char} by default or like -+@code{signed char} by default. -+ -+Ideally, a portable program should always use @code{signed char} or -+@code{unsigned char} when it depends on the signedness of an object. -+But many programs have been written to use plain @code{char} and -+expect it to be signed, or expect it to be unsigned, depending on the -+machines they were written for. This option, and its inverse, let you -+make such a program work with the opposite default. -+ -+The type @code{char} is always a distinct type from each of -+@code{signed char} or @code{unsigned char}, even though its behavior -+is always just like one of those two. -+ -+@item -fsigned-char -+@opindex fsigned-char -+Let the type @code{char} be signed, like @code{signed char}. -+ -+Note that this is equivalent to @option{-fno-unsigned-char}, which is -+the negative form of @option{-funsigned-char}. Likewise, the option -+@option{-fno-signed-char} is equivalent to @option{-funsigned-char}. -+ -+@item -fsigned-bitfields -+@itemx -funsigned-bitfields -+@itemx -fno-signed-bitfields -+@itemx -fno-unsigned-bitfields -+@opindex fsigned-bitfields -+@opindex funsigned-bitfields -+@opindex fno-signed-bitfields -+@opindex fno-unsigned-bitfields -+These options control whether a bit-field is signed or unsigned, when the -+declaration does not use either @code{signed} or @code{unsigned}. By -+default, such a bit-field is signed, because this is consistent: the -+basic integer types such as @code{int} are signed types. -+@end table -+ -+@node C++ Dialect Options -+@section Options Controlling C++ Dialect -+ -+@cindex compiler options, C++ -+@cindex C++ options, command-line -+@cindex options, C++ -+This section describes the command-line options that are only meaningful -+for C++ programs; but you can also use most of the GNU compiler options -+regardless of what language your program is in. For example, you -+might compile a file @code{firstClass.C} like this: -+ -+@smallexample -+g++ -g -frepo -O -c firstClass.C +@end smallexample + -+@noindent -+In this example, only @option{-frepo} is an option meant -+only for C++ programs; you can use the other options with any -+language supported by GCC@. + @end ifset +--- a/src/gcc/doc/sourcebuild.texi ++++ b/src/gcc/doc/sourcebuild.texi +@@ -1502,11 +1502,19 @@ + @item arm_neon_hw + Test system supports executing NEON instructions. + ++@item arm_neonv2_hw ++Test system supports executing NEON v2 instructions. + -+Here is a list of options that are @emph{only} for compiling C++ programs: -+ -+@table @gcctabopt -+ -+@item -fabi-version=@var{n} -+@opindex fabi-version -+Use version @var{n} of the C++ ABI@. Version 2 is the version of the -+C++ ABI that first appeared in G++ 3.4. Version 1 is the version of -+the C++ ABI that first appeared in G++ 3.2. Version 0 will always be -+the version that conforms most closely to the C++ ABI specification. -+Therefore, the ABI obtained using version 0 will change as ABI bugs -+are fixed. -+ -+The default is version 2. -+ -+Version 3 corrects an error in mangling a constant address as a -+template argument. -+ -+Version 4, which first appeared in G++ 4.5, implements a standard -+mangling for vector types. -+ -+Version 5, which first appeared in G++ 4.6, corrects the mangling of -+attribute const/volatile on function pointer types, decltype of a -+plain decl, and use of a function parameter in the declaration of -+another parameter. -+ -+Version 6, which first appeared in G++ 4.7, corrects the promotion -+behavior of C++11 scoped enums and the mangling of template argument -+packs, const/static_cast, prefix ++ and --, and a class scope function -+used as a template argument. -+ -+See also @option{-Wabi}. -+ -+@item -fno-access-control -+@opindex fno-access-control -+Turn off all access checking. This switch is mainly useful for working -+around bugs in the access control code. -+ -+@item -fcheck-new -+@opindex fcheck-new -+Check that the pointer returned by @code{operator new} is non-null -+before attempting to modify the storage allocated. This check is -+normally unnecessary because the C++ standard specifies that -+@code{operator new} will only return @code{0} if it is declared -+@samp{throw()}, in which case the compiler will always check the -+return value even without this option. In all other cases, when -+@code{operator new} has a non-empty exception specification, memory -+exhaustion is signalled by throwing @code{std::bad_alloc}. See also -+@samp{new (nothrow)}. -+ -+@item -fconserve-space -+@opindex fconserve-space -+Put uninitialized or run-time-initialized global variables into the -+common segment, as C does. This saves space in the executable at the -+cost of not diagnosing duplicate definitions. If you compile with this -+flag and your program mysteriously crashes after @code{main()} has -+completed, you may have an object that is being destroyed twice because -+two definitions were merged. -+ -+This option is no longer useful on most targets, now that support has -+been added for putting variables into BSS without making them common. -+ -+@item -fconstexpr-depth=@var{n} -+@opindex fconstexpr-depth -+Set the maximum nested evaluation depth for C++11 constexpr functions -+to @var{n}. A limit is needed to detect endless recursion during -+constant expression evaluation. The minimum specified by the standard -+is 512. -+ -+@item -fdeduce-init-list -+@opindex fdeduce-init-list -+Enable deduction of a template type parameter as -+std::initializer_list from a brace-enclosed initializer list, i.e. -+ -+@smallexample -+template auto forward(T t) -> decltype (realfn (t)) -+@{ -+ return realfn (t); -+@} -+ -+void f() -+@{ -+ forward(@{1,2@}); // call forward> -+@} -+@end smallexample -+ -+This deduction was implemented as a possible extension to the -+originally proposed semantics for the C++11 standard, but was not part -+of the final standard, so it is disabled by default. This option is -+deprecated, and may be removed in a future version of G++. -+ -+@item -ffriend-injection -+@opindex ffriend-injection -+Inject friend functions into the enclosing namespace, so that they are -+visible outside the scope of the class in which they are declared. -+Friend functions were documented to work this way in the old Annotated -+C++ Reference Manual, and versions of G++ before 4.1 always worked -+that way. However, in ISO C++ a friend function that is not declared -+in an enclosing scope can only be found using argument dependent -+lookup. This option causes friends to be injected as they were in -+earlier releases. -+ -+This option is for compatibility, and may be removed in a future -+release of G++. -+ -+@item -fno-elide-constructors -+@opindex fno-elide-constructors -+The C++ standard allows an implementation to omit creating a temporary -+that is only used to initialize another object of the same type. -+Specifying this option disables that optimization, and forces G++ to -+call the copy constructor in all cases. -+ -+@item -fno-enforce-eh-specs -+@opindex fno-enforce-eh-specs -+Don't generate code to check for violation of exception specifications -+at run time. This option violates the C++ standard, but may be useful -+for reducing code size in production builds, much like defining -+@samp{NDEBUG}. This does not give user code permission to throw -+exceptions in violation of the exception specifications; the compiler -+will still optimize based on the specifications, so throwing an -+unexpected exception will result in undefined behavior. -+ -+@item -ffor-scope -+@itemx -fno-for-scope -+@opindex ffor-scope -+@opindex fno-for-scope -+If @option{-ffor-scope} is specified, the scope of variables declared in -+a @i{for-init-statement} is limited to the @samp{for} loop itself, -+as specified by the C++ standard. -+If @option{-fno-for-scope} is specified, the scope of variables declared in -+a @i{for-init-statement} extends to the end of the enclosing scope, -+as was the case in old versions of G++, and other (traditional) -+implementations of C++. -+ -+The default if neither flag is given to follow the standard, -+but to allow and give a warning for old-style code that would -+otherwise be invalid, or have different behavior. -+ -+@item -fno-gnu-keywords -+@opindex fno-gnu-keywords -+Do not recognize @code{typeof} as a keyword, so that code can use this -+word as an identifier. You can use the keyword @code{__typeof__} instead. -+@option{-ansi} implies @option{-fno-gnu-keywords}. -+ -+@item -fno-implicit-templates -+@opindex fno-implicit-templates -+Never emit code for non-inline templates that are instantiated -+implicitly (i.e.@: by use); only emit code for explicit instantiations. -+@xref{Template Instantiation}, for more information. -+ -+@item -fno-implicit-inline-templates -+@opindex fno-implicit-inline-templates -+Don't emit code for implicit instantiations of inline templates, either. -+The default is to handle inlines differently so that compiles with and -+without optimization will need the same set of explicit instantiations. -+ -+@item -fno-implement-inlines -+@opindex fno-implement-inlines -+To save space, do not emit out-of-line copies of inline functions -+controlled by @samp{#pragma implementation}. This will cause linker -+errors if these functions are not inlined everywhere they are called. -+ -+@item -fms-extensions -+@opindex fms-extensions -+Disable pedantic warnings about constructs used in MFC, such as implicit -+int and getting a pointer to member function via non-standard syntax. -+ -+@item -fno-nonansi-builtins -+@opindex fno-nonansi-builtins -+Disable built-in declarations of functions that are not mandated by -+ANSI/ISO C@. These include @code{ffs}, @code{alloca}, @code{_exit}, -+@code{index}, @code{bzero}, @code{conjf}, and other related functions. -+ -+@item -fnothrow-opt -+@opindex fnothrow-opt -+Treat a @code{throw()} exception specification as though it were a -+@code{noexcept} specification to reduce or eliminate the text size -+overhead relative to a function with no exception specification. If -+the function has local variables of types with non-trivial -+destructors, the exception specification will actually make the -+function smaller because the EH cleanups for those variables can be -+optimized away. The semantic effect is that an exception thrown out of -+a function with such an exception specification will result in a call -+to @code{terminate} rather than @code{unexpected}. -+ -+@item -fno-operator-names -+@opindex fno-operator-names -+Do not treat the operator name keywords @code{and}, @code{bitand}, -+@code{bitor}, @code{compl}, @code{not}, @code{or} and @code{xor} as -+synonyms as keywords. -+ -+@item -fno-optional-diags -+@opindex fno-optional-diags -+Disable diagnostics that the standard says a compiler does not need to -+issue. Currently, the only such diagnostic issued by G++ is the one for -+a name having multiple meanings within a class. -+ -+@item -fpermissive -+@opindex fpermissive -+Downgrade some diagnostics about nonconformant code from errors to -+warnings. Thus, using @option{-fpermissive} will allow some -+nonconforming code to compile. -+ -+@item -fno-pretty-templates -+@opindex fno-pretty-templates -+When an error message refers to a specialization of a function -+template, the compiler will normally print the signature of the -+template followed by the template arguments and any typedefs or -+typenames in the signature (e.g. @code{void f(T) [with T = int]} -+rather than @code{void f(int)}) so that it's clear which template is -+involved. When an error message refers to a specialization of a class -+template, the compiler will omit any template arguments that match -+the default template arguments for that template. If either of these -+behaviors make it harder to understand the error message rather than -+easier, using @option{-fno-pretty-templates} will disable them. -+ -+@item -frepo -+@opindex frepo -+Enable automatic template instantiation at link time. This option also -+implies @option{-fno-implicit-templates}. @xref{Template -+Instantiation}, for more information. -+ -+@item -fno-rtti -+@opindex fno-rtti -+Disable generation of information about every class with virtual -+functions for use by the C++ run-time type identification features -+(@samp{dynamic_cast} and @samp{typeid}). If you don't use those parts -+of the language, you can save some space by using this flag. Note that -+exception handling uses the same information, but it will generate it as -+needed. The @samp{dynamic_cast} operator can still be used for casts that -+do not require run-time type information, i.e.@: casts to @code{void *} or to -+unambiguous base classes. -+ -+@item -fstats -+@opindex fstats -+Emit statistics about front-end processing at the end of the compilation. -+This information is generally only useful to the G++ development team. -+ -+@item -fstrict-enums -+@opindex fstrict-enums -+Allow the compiler to optimize using the assumption that a value of -+enumerated type can only be one of the values of the enumeration (as -+defined in the C++ standard; basically, a value that can be -+represented in the minimum number of bits needed to represent all the -+enumerators). This assumption may not be valid if the program uses a -+cast to convert an arbitrary integer value to the enumerated type. -+ -+@item -ftemplate-depth=@var{n} -+@opindex ftemplate-depth -+Set the maximum instantiation depth for template classes to @var{n}. -+A limit on the template instantiation depth is needed to detect -+endless recursions during template class instantiation. ANSI/ISO C++ -+conforming programs must not rely on a maximum depth greater than 17 -+(changed to 1024 in C++11). The default value is 900, as the compiler -+can run out of stack space before hitting 1024 in some situations. -+ -+@item -fno-threadsafe-statics -+@opindex fno-threadsafe-statics -+Do not emit the extra code to use the routines specified in the C++ -+ABI for thread-safe initialization of local statics. You can use this -+option to reduce code size slightly in code that doesn't need to be -+thread-safe. -+ -+@item -fuse-cxa-atexit -+@opindex fuse-cxa-atexit -+Register destructors for objects with static storage duration with the -+@code{__cxa_atexit} function rather than the @code{atexit} function. -+This option is required for fully standards-compliant handling of static -+destructors, but will only work if your C library supports -+@code{__cxa_atexit}. -+ -+@item -fno-use-cxa-get-exception-ptr -+@opindex fno-use-cxa-get-exception-ptr -+Don't use the @code{__cxa_get_exception_ptr} runtime routine. This -+will cause @code{std::uncaught_exception} to be incorrect, but is necessary -+if the runtime routine is not available. -+ -+@item -fvisibility-inlines-hidden -+@opindex fvisibility-inlines-hidden -+This switch declares that the user does not attempt to compare -+pointers to inline functions or methods where the addresses of the two functions -+were taken in different shared objects. -+ -+The effect of this is that GCC may, effectively, mark inline methods with -+@code{__attribute__ ((visibility ("hidden")))} so that they do not -+appear in the export table of a DSO and do not require a PLT indirection -+when used within the DSO@. Enabling this option can have a dramatic effect -+on load and link times of a DSO as it massively reduces the size of the -+dynamic export table when the library makes heavy use of templates. -+ -+The behavior of this switch is not quite the same as marking the -+methods as hidden directly, because it does not affect static variables -+local to the function or cause the compiler to deduce that -+the function is defined in only one shared object. -+ -+You may mark a method as having a visibility explicitly to negate the -+effect of the switch for that method. For example, if you do want to -+compare pointers to a particular inline method, you might mark it as -+having default visibility. Marking the enclosing class with explicit -+visibility will have no effect. -+ -+Explicitly instantiated inline methods are unaffected by this option -+as their linkage might otherwise cross a shared library boundary. -+@xref{Template Instantiation}. -+ -+@item -fvisibility-ms-compat -+@opindex fvisibility-ms-compat -+This flag attempts to use visibility settings to make GCC's C++ -+linkage model compatible with that of Microsoft Visual Studio. -+ -+The flag makes these changes to GCC's linkage model: -+ -+@enumerate -+@item -+It sets the default visibility to @code{hidden}, like -+@option{-fvisibility=hidden}. -+ -+@item -+Types, but not their members, are not hidden by default. -+ -+@item -+The One Definition Rule is relaxed for types without explicit -+visibility specifications that are defined in more than one different -+shared object: those declarations are permitted if they would have -+been permitted when this option was not used. -+@end enumerate -+ -+In new code it is better to use @option{-fvisibility=hidden} and -+export those classes that are intended to be externally visible. -+Unfortunately it is possible for code to rely, perhaps accidentally, -+on the Visual Studio behavior. -+ -+Among the consequences of these changes are that static data members -+of the same type with the same name but defined in different shared -+objects will be different, so changing one will not change the other; -+and that pointers to function members defined in different shared -+objects may not compare equal. When this flag is given, it is a -+violation of the ODR to define types with the same name differently. -+ -+@item -fno-weak -+@opindex fno-weak -+Do not use weak symbol support, even if it is provided by the linker. -+By default, G++ will use weak symbols if they are available. This -+option exists only for testing, and should not be used by end-users; -+it will result in inferior code and has no benefits. This option may -+be removed in a future release of G++. -+ -+@item -nostdinc++ -+@opindex nostdinc++ -+Do not search for header files in the standard directories specific to -+C++, but do still search the other standard directories. (This option -+is used when building the C++ library.) -+@end table -+ -+In addition, these optimization, warning, and code generation options -+have meanings only for C++ programs: -+ -+@table @gcctabopt -+@item -fno-default-inline -+@opindex fno-default-inline -+Do not assume @samp{inline} for functions defined inside a class scope. -+@xref{Optimize Options,,Options That Control Optimization}. Note that these -+functions will have linkage like inline functions; they just won't be -+inlined by default. -+ -+@item -Wabi @r{(C, Objective-C, C++ and Objective-C++ only)} -+@opindex Wabi -+@opindex Wno-abi -+Warn when G++ generates code that is probably not compatible with the -+vendor-neutral C++ ABI@. Although an effort has been made to warn about -+all such cases, there are probably some cases that are not warned about, -+even though G++ is generating incompatible code. There may also be -+cases where warnings are emitted even though the code that is generated -+will be compatible. -+ -+You should rewrite your code to avoid these warnings if you are -+concerned about the fact that code generated by G++ may not be binary -+compatible with code generated by other compilers. -+ -+The known incompatibilities in @option{-fabi-version=2} (the default) include: -+ -+@itemize @bullet -+ -+@item -+A template with a non-type template parameter of reference type is -+mangled incorrectly: -+@smallexample -+extern int N; -+template struct S @{@}; -+void n (S) @{2@} -+@end smallexample -+ -+This is fixed in @option{-fabi-version=3}. -+ -+@item -+SIMD vector types declared using @code{__attribute ((vector_size))} are -+mangled in a non-standard way that does not allow for overloading of -+functions taking vectors of different sizes. -+ -+The mangling is changed in @option{-fabi-version=4}. -+@end itemize -+ -+The known incompatibilities in @option{-fabi-version=1} include: -+ -+@itemize @bullet -+ -+@item -+Incorrect handling of tail-padding for bit-fields. G++ may attempt to -+pack data into the same byte as a base class. For example: -+ -+@smallexample -+struct A @{ virtual void f(); int f1 : 1; @}; -+struct B : public A @{ int f2 : 1; @}; -+@end smallexample -+ -+@noindent -+In this case, G++ will place @code{B::f2} into the same byte -+as@code{A::f1}; other compilers will not. You can avoid this problem -+by explicitly padding @code{A} so that its size is a multiple of the -+byte size on your platform; that will cause G++ and other compilers to -+layout @code{B} identically. -+ -+@item -+Incorrect handling of tail-padding for virtual bases. G++ does not use -+tail padding when laying out virtual bases. For example: -+ -+@smallexample -+struct A @{ virtual void f(); char c1; @}; -+struct B @{ B(); char c2; @}; -+struct C : public A, public virtual B @{@}; -+@end smallexample -+ -+@noindent -+In this case, G++ will not place @code{B} into the tail-padding for -+@code{A}; other compilers will. You can avoid this problem by -+explicitly padding @code{A} so that its size is a multiple of its -+alignment (ignoring virtual base classes); that will cause G++ and other -+compilers to layout @code{C} identically. -+ -+@item -+Incorrect handling of bit-fields with declared widths greater than that -+of their underlying types, when the bit-fields appear in a union. For -+example: -+ -+@smallexample -+union U @{ int i : 4096; @}; -+@end smallexample -+ -+@noindent -+Assuming that an @code{int} does not have 4096 bits, G++ will make the -+union too small by the number of bits in an @code{int}. -+ -+@item -+Empty classes can be placed at incorrect offsets. For example: -+ -+@smallexample -+struct A @{@}; -+ -+struct B @{ -+ A a; -+ virtual void f (); -+@}; -+ -+struct C : public B, public A @{@}; -+@end smallexample -+ -+@noindent -+G++ will place the @code{A} base class of @code{C} at a nonzero offset; -+it should be placed at offset zero. G++ mistakenly believes that the -+@code{A} data member of @code{B} is already at offset zero. -+ -+@item -+Names of template functions whose types involve @code{typename} or -+template template parameters can be mangled incorrectly. -+ -+@smallexample -+template -+void f(typename Q::X) @{@} -+ -+template