diff -Nru xserver-xorg-video-intel-2.21.6+git20130502.5637c173/.lastcommit xserver-xorg-video-intel-2.21.6+git20130514.3ee42de0/.lastcommit --- xserver-xorg-video-intel-2.21.6+git20130502.5637c173/.lastcommit 2013-05-02 18:21:48.000000000 +0000 +++ xserver-xorg-video-intel-2.21.6+git20130514.3ee42de0/.lastcommit 2013-05-14 14:33:04.000000000 +0000 @@ -1 +1 @@ -commit 5637c173f85a5bb9a77572e4c070e0d612e6f49d +commit 3ee42de066e4629f78e254c27d07dc33e16dbc02 diff -Nru xserver-xorg-video-intel-2.21.6+git20130502.5637c173/ChangeLog xserver-xorg-video-intel-2.21.6+git20130514.3ee42de0/ChangeLog --- xserver-xorg-video-intel-2.21.6+git20130502.5637c173/ChangeLog 2013-05-02 18:22:02.000000000 +0000 +++ xserver-xorg-video-intel-2.21.6+git20130514.3ee42de0/ChangeLog 2013-05-14 14:33:47.000000000 +0000 @@ -1,9 +1,114 @@ -commit 2e78ed5f97994dbf25e490b4a827bc0810589922 +commit b38e60a61e8955b584c7e5b93302c4a0daf2ec15 Author: Robert Hooker -Date: Thu May 2 14:21:48 2013 -0400 +Date: Tue May 14 10:33:04 2013 -0400 Add debian tree from origin/ubuntu +commit 3ee42de066e4629f78e254c27d07dc33e16dbc02 +Author: Rodrigo Vivi +Date: Mon May 13 17:56:30 2013 -0300 + + Adding more reserved PCI IDs for Haswell. + + As Chris mentioned there is a tendency for us to find out more + PCI IDs only when users report. So let's add all new reserved Haswell IDs. + I didn't have better names for this reserved ids and didn't want to use rsvd1 + and rsvd2 groups, so I decided to use "B" and "E" that stands for the last + id digit. + + Cc: Chris Wilson + Signed-off-by: Rodrigo Vivi + +commit ee96de8b1e7e4a305ee31c0ece1d9d38df8328f9 +Author: Rodrigo Vivi +Date: Mon May 13 17:56:29 2013 -0300 + + Fix Haswell GT3 names. + + When publishing first HSW ids we weren't allowed to use "GT3" codname. + But this is the correct codname and Mesa is using it already. + So to avoid people getting confused why in Mesa it is called GT3 and here + it is called GT2_PLUS let's fix this name in a standard and correct way. + + Signed-off-by: Rodrigo Vivi + +commit 979d2f8d0038aa621e1c75200b10a3819e024a66 +Author: Chris Wilson +Date: Mon Apr 22 18:00:32 2013 +0100 + + sna/gen4: Tidy testing for an active vertex buffer id + + Signed-off-by: Chris Wilson + +commit 7ba63307058337af5a120ad01c93b423a3e422eb +Author: Chris Wilson +Date: Mon Apr 22 17:43:21 2013 +0100 + + sna/gen4: Drop unused gen parameter to SF state setup + + Signed-off-by: Chris Wilson + +commit 2217f6356b53263b6ce8f92b5c29c0614d4ef2a5 +Author: Chris Wilson +Date: Thu May 9 13:46:11 2013 +0100 + + sna/trapezoids: Fix the determination of the trapezoid origin + + "src-x and src-y register the pattern to + the floor of the top x and y coordinate of the left edge of the + first trapezoid," + + Bugzilla: https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-intel/+bug/1178020 + Signed-off-by: Chris Wilson + +commit 6e98df06fa9d218a6139730140a83a1940b05980 +Author: Chris Wilson +Date: Thu May 9 13:45:38 2013 +0100 + + sna: Add more debugging to unaligned trapezoids + + Signed-off-by: Chris Wilson + +commit 5d62ec25937ad296114bf890a7a5ac11ff03508c +Author: Chris Wilson +Date: Thu May 9 13:44:24 2013 +0100 + + sna/gen7: Add DBG for channel setup for render source + + Signed-off-by: Chris Wilson + +commit debdcd6a09464251324238ccbd935a6ade265d94 +Author: Chris Wilson +Date: Thu May 9 13:43:57 2013 +0100 + + sna: Add DBG statements for choice of spans vertex emitter + + Signed-off-by: Chris Wilson + +commit c6e4088dcb261d89fa0065eb7d9b62eada049dbd +Author: Chris Wilson +Date: Thu May 9 11:30:05 2013 +0100 + + sna: Handle cached upload buffers for partial migration to GPU + + Since the extended use of move_area_to_gpu for partial migration of + render sources, we exposed the lack of handling of upload caches along + that path. + + Reported-by: Zdenek Kabelac + Signed-off-by: Chris Wilson + +commit 262ee1ef1e98cb84fa0af6e679c8cd61dc93f008 +Author: Chris Wilson +Date: Tue May 7 10:35:53 2013 +0100 + + sna: Do not attempt to clean an active scanout + + For simplicity, skip buffers that are still in use by the batch - they + will be removed later. + + Signed-off-by: Chris Wilson + commit 5637c173f85a5bb9a77572e4c070e0d612e6f49d Author: Chris Wilson Date: Wed May 1 15:14:55 2013 +0100 diff -Nru xserver-xorg-video-intel-2.21.6+git20130502.5637c173/debian/changelog xserver-xorg-video-intel-2.21.6+git20130514.3ee42de0/debian/changelog --- xserver-xorg-video-intel-2.21.6+git20130502.5637c173/debian/changelog 2013-05-14 14:50:20.000000000 +0000 +++ xserver-xorg-video-intel-2.21.6+git20130514.3ee42de0/debian/changelog 2013-05-14 14:50:21.000000000 +0000 @@ -1,12 +1,12 @@ -xserver-xorg-video-intel (2:2.21.6+git20130502.5637c173-0ubuntu0sarvatt~quantal) quantal; urgency=critical +xserver-xorg-video-intel (2:2.21.6+git20130514.3ee42de0-0ubuntu0sarvatt~quantal) quantal; urgency=low - * Checkout from git 20130502 (master branch) up to commit - 5637c173f85a5bb9a77572e4c070e0d612e6f49d + * Checkout from git 20130514 (master branch) up to commit + 3ee42de066e4629f78e254c27d07dc33e16dbc02 * Only added debian/ tree from origin/ubuntu * hook: Refresh 0002-Update-manpage-for-new-accelmethod-option.patch * hook: Drop sna-flush-scanout-cache-after-resizing.patch (upstream) - -- Robert Hooker Thu, 02 May 2013 14:22:02 -0400 + -- Robert Hooker Tue, 14 May 2013 10:33:48 -0400 xserver-xorg-video-intel (2:2.21.6-0ubuntu4) raring-proposed; urgency=low diff -Nru xserver-xorg-video-intel-2.21.6+git20130502.5637c173/src/intel_driver.h xserver-xorg-video-intel-2.21.6+git20130514.3ee42de0/src/intel_driver.h --- xserver-xorg-video-intel-2.21.6+git20130502.5637c173/src/intel_driver.h 2013-05-02 18:21:48.000000000 +0000 +++ xserver-xorg-video-intel-2.21.6+git20130514.3ee42de0/src/intel_driver.h 2013-05-14 14:33:04.000000000 +0000 @@ -194,55 +194,67 @@ #define PCI_CHIP_HASWELL_D_GT1 0x0402 #define PCI_CHIP_HASWELL_D_GT2 0x0412 -#define PCI_CHIP_HASWELL_D_GT2_PLUS 0x0422 +#define PCI_CHIP_HASWELL_D_GT3 0x0422 #define PCI_CHIP_HASWELL_M_GT1 0x0406 #define PCI_CHIP_HASWELL_M_GT2 0x0416 -#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426 +#define PCI_CHIP_HASWELL_M_GT3 0x0426 #define PCI_CHIP_HASWELL_S_GT1 0x040A #define PCI_CHIP_HASWELL_S_GT2 0x041A -#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A -#define PCI_CHIP_HASWELL_GT1_RSVD 0x040E -#define PCI_CHIP_HASWELL_GT2_RSVD 0x041E -#define PCI_CHIP_HASWELL_GT2_PLUS_RSVD 0x042E +#define PCI_CHIP_HASWELL_S_GT3 0x042A +#define PCI_CHIP_HASWELL_B_GT1 0x040B +#define PCI_CHIP_HASWELL_B_GT2 0x041B +#define PCI_CHIP_HASWELL_B_GT3 0x042B +#define PCI_CHIP_HASWELL_E_GT1 0x040E +#define PCI_CHIP_HASWELL_E_GT2 0x041E +#define PCI_CHIP_HASWELL_E_GT3 0x042E #define PCI_CHIP_HASWELL_SDV_D_GT1 0x0C02 #define PCI_CHIP_HASWELL_SDV_D_GT2 0x0C12 -#define PCI_CHIP_HASWELL_SDV_D_GT2_PLUS 0x0C22 +#define PCI_CHIP_HASWELL_SDV_D_GT3 0x0C22 #define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 #define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16 -#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26 +#define PCI_CHIP_HASWELL_SDV_M_GT3 0x0C26 #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A -#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A -#define PCI_CHIP_HASWELL_SDV_GT1_RSVD 0x0C0E -#define PCI_CHIP_HASWELL_SDV_GT2_RSVD 0x0C1E -#define PCI_CHIP_HASWELL_SDV_GT2_PLUS_RSVD 0x0C2E +#define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A +#define PCI_CHIP_HASWELL_SDV_B_GT1 0x0C0E +#define PCI_CHIP_HASWELL_SDV_B_GT2 0x0C1E +#define PCI_CHIP_HASWELL_SDV_B_GT3 0x0C2E +#define PCI_CHIP_HASWELL_SDV_E_GT1 0x0C0E +#define PCI_CHIP_HASWELL_SDV_E_GT2 0x0C1E +#define PCI_CHIP_HASWELL_SDV_E_GT3 0x0C2E #define PCI_CHIP_HASWELL_ULT_D_GT1 0x0A02 #define PCI_CHIP_HASWELL_ULT_D_GT2 0x0A12 -#define PCI_CHIP_HASWELL_ULT_D_GT2_PLUS 0x0A22 +#define PCI_CHIP_HASWELL_ULT_D_GT3 0x0A22 #define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 #define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16 -#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26 +#define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26 #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A -#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A -#define PCI_CHIP_HASWELL_ULT_GT1_RSVD 0x0A0E -#define PCI_CHIP_HASWELL_ULT_GT2_RSVD 0x0A1E -#define PCI_CHIP_HASWELL_ULT_GT2_PLUS_RSVD 0x0A2E +#define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A +#define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B +#define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B +#define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B +#define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E +#define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E +#define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E #define PCI_CHIP_HASWELL_CRW_D_GT1 0x0D02 #define PCI_CHIP_HASWELL_CRW_D_GT2 0x0D12 -#define PCI_CHIP_HASWELL_CRW_D_GT2_PLUS 0x0D22 +#define PCI_CHIP_HASWELL_CRW_D_GT3 0x0D22 #define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 #define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16 -#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D26 +#define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26 #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A -#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A -#define PCI_CHIP_HASWELL_CRW_GT1_RSVD 0x0D0E -#define PCI_CHIP_HASWELL_CRW_GT2_RSVD 0x0D1E -#define PCI_CHIP_HASWELL_CRW_GT2_PLUS_RSVD 0x0D2E +#define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A +#define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B +#define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B +#define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B +#define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E +#define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E +#define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 #define PCI_CHIP_VALLEYVIEW_1 0x0f31 diff -Nru xserver-xorg-video-intel-2.21.6+git20130502.5637c173/src/intel_module.c xserver-xorg-video-intel-2.21.6+git20130514.3ee42de0/src/intel_module.c --- xserver-xorg-video-intel-2.21.6+git20130502.5637c173/src/intel_module.c 2013-05-02 18:21:48.000000000 +0000 +++ xserver-xorg-video-intel-2.21.6+git20130514.3ee42de0/src/intel_module.c 2013-05-14 14:33:04.000000000 +0000 @@ -162,40 +162,64 @@ {PCI_CHIP_IVYBRIDGE_S_GT2, "Ivybridge Server (GT2)" }, {PCI_CHIP_HASWELL_D_GT1, "Haswell Desktop (GT1)" }, {PCI_CHIP_HASWELL_D_GT2, "Haswell Desktop (GT2)" }, - {PCI_CHIP_HASWELL_D_GT2_PLUS, "Haswell Desktop (GT2+)" }, + {PCI_CHIP_HASWELL_D_GT3, "Haswell Desktop (GT3)" }, {PCI_CHIP_HASWELL_M_GT1, "Haswell Mobile (GT1)" }, {PCI_CHIP_HASWELL_M_GT2, "Haswell Mobile (GT2)" }, - {PCI_CHIP_HASWELL_M_GT2_PLUS, "Haswell Mobile (GT2+)" }, + {PCI_CHIP_HASWELL_M_GT3, "Haswell Mobile (GT3)" }, {PCI_CHIP_HASWELL_S_GT1, "Haswell Server (GT1)" }, {PCI_CHIP_HASWELL_S_GT2, "Haswell Server (GT2)" }, - {PCI_CHIP_HASWELL_S_GT2_PLUS, "Haswell Server (GT2+)" }, + {PCI_CHIP_HASWELL_S_GT3, "Haswell Server (GT3)" }, + {PCI_CHIP_HASWELL_B_GT1, "Haswell (GT1)" }, + {PCI_CHIP_HASWELL_B_GT2, "Haswell (GT2)" }, + {PCI_CHIP_HASWELL_B_GT3, "Haswell (GT3)" }, + {PCI_CHIP_HASWELL_E_GT1, "Haswell (GT1)" }, + {PCI_CHIP_HASWELL_E_GT2, "Haswell (GT2)" }, + {PCI_CHIP_HASWELL_E_GT3, "Haswell (GT3)" }, {PCI_CHIP_HASWELL_SDV_D_GT1, "Haswell SDV Desktop (GT1)" }, {PCI_CHIP_HASWELL_SDV_D_GT2, "Haswell SDV Desktop (GT2)" }, - {PCI_CHIP_HASWELL_SDV_D_GT2_PLUS, "Haswell SDV Desktop (GT2+)" }, + {PCI_CHIP_HASWELL_SDV_D_GT3, "Haswell SDV Desktop (GT3)" }, {PCI_CHIP_HASWELL_SDV_M_GT1, "Haswell SDV Mobile (GT1)" }, {PCI_CHIP_HASWELL_SDV_M_GT2, "Haswell SDV Mobile (GT2)" }, - {PCI_CHIP_HASWELL_SDV_M_GT2_PLUS, "Haswell SDV Mobile (GT2+)" }, + {PCI_CHIP_HASWELL_SDV_M_GT3, "Haswell SDV Mobile (GT3)" }, {PCI_CHIP_HASWELL_SDV_S_GT1, "Haswell SDV Server (GT1)" }, {PCI_CHIP_HASWELL_SDV_S_GT2, "Haswell SDV Server (GT2)" }, - {PCI_CHIP_HASWELL_SDV_S_GT2_PLUS, "Haswell SDV Server (GT2+)" }, + {PCI_CHIP_HASWELL_SDV_S_GT3, "Haswell SDV Server (GT3)" }, + {PCI_CHIP_HASWELL_SDV_B_GT1, "Haswell SDV (GT1)" }, + {PCI_CHIP_HASWELL_SDV_B_GT2, "Haswell SDV (GT2)" }, + {PCI_CHIP_HASWELL_SDV_B_GT3, "Haswell SDV (GT3)" }, + {PCI_CHIP_HASWELL_SDV_E_GT1, "Haswell SDV (GT1)" }, + {PCI_CHIP_HASWELL_SDV_E_GT2, "Haswell SDV (GT2)" }, + {PCI_CHIP_HASWELL_SDV_E_GT3, "Haswell SDV (GT3)" }, {PCI_CHIP_HASWELL_ULT_D_GT1, "Haswell ULT Desktop (GT1)" }, {PCI_CHIP_HASWELL_ULT_D_GT2, "Haswell ULT Desktop (GT2)" }, - {PCI_CHIP_HASWELL_ULT_D_GT2_PLUS, "Haswell ULT Desktop (GT2+)" }, + {PCI_CHIP_HASWELL_ULT_D_GT3, "Haswell ULT Desktop (GT3)" }, {PCI_CHIP_HASWELL_ULT_M_GT1, "Haswell ULT Mobile (GT1)" }, {PCI_CHIP_HASWELL_ULT_M_GT2, "Haswell ULT Mobile (GT2)" }, - {PCI_CHIP_HASWELL_ULT_M_GT2_PLUS, "Haswell ULT Mobile (GT2+)" }, + {PCI_CHIP_HASWELL_ULT_M_GT3, "Haswell ULT Mobile (GT3)" }, {PCI_CHIP_HASWELL_ULT_S_GT1, "Haswell ULT Server (GT1)" }, {PCI_CHIP_HASWELL_ULT_S_GT2, "Haswell ULT Server (GT2)" }, - {PCI_CHIP_HASWELL_ULT_S_GT2_PLUS, "Haswell ULT Server (GT2+)" }, + {PCI_CHIP_HASWELL_ULT_S_GT3, "Haswell ULT Server (GT3)" }, + {PCI_CHIP_HASWELL_ULT_B_GT1, "Haswell ULT (GT1)" }, + {PCI_CHIP_HASWELL_ULT_B_GT2, "Haswell ULT (GT2)" }, + {PCI_CHIP_HASWELL_ULT_B_GT3, "Haswell ULT (GT3)" }, + {PCI_CHIP_HASWELL_ULT_E_GT1, "Haswell ULT (GT1)" }, + {PCI_CHIP_HASWELL_ULT_E_GT2, "Haswell ULT (GT2)" }, + {PCI_CHIP_HASWELL_ULT_E_GT3, "Haswell ULT (GT3)" }, {PCI_CHIP_HASWELL_CRW_D_GT1, "Haswell CRW Desktop (GT1)" }, {PCI_CHIP_HASWELL_CRW_D_GT2, "Haswell CRW Desktop (GT2)" }, - {PCI_CHIP_HASWELL_CRW_D_GT2_PLUS, "Haswell CRW Desktop (GT2+)" }, + {PCI_CHIP_HASWELL_CRW_D_GT3, "Haswell CRW Desktop (GT3)" }, {PCI_CHIP_HASWELL_CRW_M_GT1, "Haswell CRW Mobile (GT1)" }, {PCI_CHIP_HASWELL_CRW_M_GT2, "Haswell CRW Mobile (GT2)" }, - {PCI_CHIP_HASWELL_CRW_M_GT2_PLUS, "Haswell CRW Mobile (GT2+)" }, + {PCI_CHIP_HASWELL_CRW_M_GT3, "Haswell CRW Mobile (GT3)" }, {PCI_CHIP_HASWELL_CRW_S_GT1, "Haswell CRW Server (GT1)" }, {PCI_CHIP_HASWELL_CRW_S_GT2, "Haswell CRW Server (GT2)" }, - {PCI_CHIP_HASWELL_CRW_S_GT2_PLUS, "Haswell CRW Server (GT2+)" }, + {PCI_CHIP_HASWELL_CRW_S_GT3, "Haswell CRW Server (GT3)" }, + {PCI_CHIP_HASWELL_CRW_B_GT1, "Haswell CRW (GT1)" }, + {PCI_CHIP_HASWELL_CRW_B_GT2, "Haswell CRW (GT2)" }, + {PCI_CHIP_HASWELL_CRW_B_GT3, "Haswell CRW (GT3)" }, + {PCI_CHIP_HASWELL_CRW_E_GT1, "Haswell CRW (GT1)" }, + {PCI_CHIP_HASWELL_CRW_E_GT2, "Haswell CRW (GT2)" }, + {PCI_CHIP_HASWELL_CRW_E_GT3, "Haswell CRW (GT3)" }, {PCI_CHIP_VALLEYVIEW_PO, "ValleyView PO board" }, {-1, NULL} }; @@ -270,54 +294,67 @@ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT1, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2, &intel_haswell_info ), - INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2_PLUS, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT3, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT1, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2, &intel_haswell_info ), - INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2_PLUS, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT3, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT1, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2, &intel_haswell_info ), - INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2_PLUS, &intel_haswell_info ), - INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_GT1_RSVD, &intel_haswell_info ), - INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_GT2_RSVD, &intel_haswell_info ), - INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_GT2_PLUS_RSVD, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT3, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_B_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_B_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_B_GT3, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_E_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_E_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_E_GT3, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT1, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2, &intel_haswell_info ), - INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2_PLUS, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT3, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT1, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2, &intel_haswell_info ), - INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2_PLUS, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT3, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT1, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2, &intel_haswell_info ), - INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2_PLUS, &intel_haswell_info ), - INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_GT1_RSVD, &intel_haswell_info ), - INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_GT2_RSVD, &intel_haswell_info ), - INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_GT2_PLUS_RSVD, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT3, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_B_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_B_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_B_GT3, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_E_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_E_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_E_GT3, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT1, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2, &intel_haswell_info ), - INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2_PLUS, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT3, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT1, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2, &intel_haswell_info ), - INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2_PLUS, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT3, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT1, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2, &intel_haswell_info ), - INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2_PLUS, &intel_haswell_info ), - INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_GT1_RSVD, &intel_haswell_info ), - INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_GT2_RSVD, &intel_haswell_info ), - INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_GT2_PLUS_RSVD, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT3, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_B_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_B_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_B_GT3, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_E_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_E_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_E_GT3, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT1, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2, &intel_haswell_info ), - INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2_PLUS, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT3, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT1, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2, &intel_haswell_info ), - INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2_PLUS, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT3, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT1, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2, &intel_haswell_info ), - INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2_PLUS, &intel_haswell_info ), - INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_GT1_RSVD, &intel_haswell_info ), - INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_GT2_RSVD, &intel_haswell_info ), - INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_GT2_PLUS_RSVD, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT3, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_B_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_B_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_B_GT3, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_E_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_E_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_E_GT3, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_PO, &intel_valleyview_info ), INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_1, &intel_valleyview_info ), diff -Nru xserver-xorg-video-intel-2.21.6+git20130502.5637c173/src/sna/gen4_render.c xserver-xorg-video-intel-2.21.6+git20130514.3ee42de0/src/sna/gen4_render.c --- xserver-xorg-video-intel-2.21.6+git20130502.5637c173/src/sna/gen4_render.c 2013-04-12 14:45:15.000000000 +0000 +++ xserver-xorg-video-intel-2.21.6+git20130514.3ee42de0/src/sna/gen4_render.c 2013-05-14 14:33:04.000000000 +0000 @@ -586,7 +586,7 @@ static bool gen4_rectangle_begin(struct sna *sna, const struct sna_composite_op *op) { - int id = op->u.gen4.ve_id; + unsigned int id = 1 << op->u.gen4.ve_id; int ndwords; if (sna_vertex_wait__locked(&sna->render) && sna->render.vertex_offset) @@ -594,13 +594,13 @@ /* 7xpipelined pointers + 6xprimitive + 1xflush */ ndwords = op->need_magic_ca_pass? 20 : 6; - if ((sna->render.vb_id & (1 << id)) == 0) + if ((sna->render.vb_id & id) == 0) ndwords += 5; if (!kgem_check_batch(&sna->kgem, ndwords)) return false; - if ((sna->render.vb_id & (1 << id)) == 0) + if ((sna->render.vb_id & id) == 0) gen4_emit_vertex_buffer(sna, op); if (sna->render.vertex_offset == 0) gen4_emit_primitive(sna); @@ -2946,7 +2946,7 @@ } static uint32_t gen4_create_sf_state(struct sna_static_stream *stream, - int gen, uint32_t kernel) + uint32_t kernel) { struct gen4_sf_unit_state *sf; @@ -3100,7 +3100,7 @@ } state->vs = gen4_create_vs_unit_state(&general); - state->sf = gen4_create_sf_state(&general, sna->kgem.gen, sf); + state->sf = gen4_create_sf_state(&general, sf); wm_state = sna_static_stream_map(&general, sizeof(*wm_state) * KERNEL_COUNT * diff -Nru xserver-xorg-video-intel-2.21.6+git20130502.5637c173/src/sna/gen4_vertex.c xserver-xorg-video-intel-2.21.6+git20130514.3ee42de0/src/sna/gen4_vertex.c --- xserver-xorg-video-intel-2.21.6+git20130502.5637c173/src/sna/gen4_vertex.c 2013-04-12 14:45:15.000000000 +0000 +++ xserver-xorg-video-intel-2.21.6+git20130514.3ee42de0/src/sna/gen4_vertex.c 2013-05-14 14:33:04.000000000 +0000 @@ -2923,11 +2923,13 @@ unsigned vb; if (tmp->base.src.is_solid) { + DBG(("%s: solid source\n", __FUNCTION__)); tmp->prim_emit = emit_span_solid; tmp->emit_boxes = emit_span_boxes_solid; tmp->base.floats_per_vertex = 3; vb = 1 << 2 | 1; } else if (tmp->base.src.is_linear) { + DBG(("%s: linear source\n", __FUNCTION__)); #if defined(avx2) if (sna->cpu_features & AVX2) { tmp->prim_emit = emit_span_linear__avx2; @@ -2947,6 +2949,7 @@ tmp->base.floats_per_vertex = 3; vb = 1 << 2 | 1; } else if (tmp->base.src.transform == NULL) { + DBG(("%s: identity transform\n", __FUNCTION__)); #if defined(avx2) if (sna->cpu_features & AVX2) { tmp->prim_emit = emit_span_identity__avx2; @@ -2969,6 +2972,7 @@ tmp->base.src.scale[0] /= tmp->base.src.transform->matrix[2][2]; tmp->base.src.scale[1] /= tmp->base.src.transform->matrix[2][2]; if (!sna_affine_transform_is_rotation(tmp->base.src.transform)) { + DBG(("%s: simple (unrotated affine) transform\n", __FUNCTION__)); #if defined(avx2) if (sna->cpu_features & AVX2) { tmp->prim_emit = emit_span_simple__avx2; @@ -2986,6 +2990,7 @@ tmp->emit_boxes = emit_span_boxes_simple; } } else { + DBG(("%s: affine transform\n", __FUNCTION__)); #if defined(avx2) if (sna->cpu_features & AVX2) { tmp->prim_emit = emit_span_affine__avx2; @@ -3006,6 +3011,7 @@ tmp->base.floats_per_vertex = 4; vb = 1 << 2 | 2; } else { + DBG(("%s: projective transform\n", __FUNCTION__)); tmp->prim_emit = emit_composite_spans_primitive; tmp->base.floats_per_vertex = 5; vb = 1 << 2 | 3; diff -Nru xserver-xorg-video-intel-2.21.6+git20130502.5637c173/src/sna/gen7_render.c xserver-xorg-video-intel-2.21.6+git20130514.3ee42de0/src/sna/gen7_render.c --- xserver-xorg-video-intel-2.21.6+git20130502.5637c173/src/sna/gen7_render.c 2013-05-02 18:21:48.000000000 +0000 +++ xserver-xorg-video-intel-2.21.6+git20130514.3ee42de0/src/sna/gen7_render.c 2013-05-14 14:33:04.000000000 +0000 @@ -1953,6 +1953,25 @@ x, y, w, h, dst_x, dst_y); } + DBG(("%s: pixmap, repeat=%d, filter=%d, transform?=%d [affine? %d], format=%08x\n", + __FUNCTION__, + channel->repeat, channel->filter, + channel->transform != NULL, channel->is_affine, + channel->pict_format)); + if (channel->transform) { + DBG(("%s: transform=[%f %f %f, %f %f %f, %f %f %f]\n", + __FUNCTION__, + channel->transform->matrix[0][0] / 65536., + channel->transform->matrix[0][1] / 65536., + channel->transform->matrix[0][2] / 65536., + channel->transform->matrix[1][0] / 65536., + channel->transform->matrix[1][1] / 65536., + channel->transform->matrix[1][2] / 65536., + channel->transform->matrix[2][0] / 65536., + channel->transform->matrix[2][1] / 65536., + channel->transform->matrix[2][2] / 65536.)); + } + return sna_render_pixmap_bo(sna, channel, pixmap, x, y, w, h, dst_x, dst_y); } diff -Nru xserver-xorg-video-intel-2.21.6+git20130502.5637c173/src/sna/kgem.c xserver-xorg-video-intel-2.21.6+git20130514.3ee42de0/src/sna/kgem.c --- xserver-xorg-video-intel-2.21.6+git20130502.5637c173/src/sna/kgem.c 2013-05-02 18:21:48.000000000 +0000 +++ xserver-xorg-video-intel-2.21.6+git20130514.3ee42de0/src/sna/kgem.c 2013-05-14 14:33:04.000000000 +0000 @@ -2807,7 +2807,7 @@ struct kgem_bo *bo; bo = list_first_entry(&kgem->scanout, struct kgem_bo, list); - if (__kgem_busy(kgem, bo->handle)) + if (bo->exec || __kgem_busy(kgem, bo->handle)) break; list_del(&bo->list); diff -Nru xserver-xorg-video-intel-2.21.6+git20130502.5637c173/src/sna/sna_accel.c xserver-xorg-video-intel-2.21.6+git20130514.3ee42de0/src/sna/sna_accel.c --- xserver-xorg-video-intel-2.21.6+git20130502.5637c173/src/sna/sna_accel.c 2013-05-02 18:21:48.000000000 +0000 +++ xserver-xorg-video-intel-2.21.6+git20130514.3ee42de0/src/sna/sna_accel.c 2013-05-14 14:33:04.000000000 +0000 @@ -2491,6 +2491,14 @@ goto done; } + if (flags & MOVE_WRITE && priv->gpu_bo && priv->gpu_bo->proxy) { + DBG(("%s: discarding cached upload buffer\n", __FUNCTION__)); + assert(priv->gpu_damage == NULL); + assert(!priv->pinned); + kgem_bo_destroy(&sna->kgem, priv->gpu_bo); + priv->gpu_bo = NULL; + } + if ((flags & MOVE_READ) == 0) sna_damage_subtract_box(&priv->cpu_damage, box); @@ -2528,12 +2536,12 @@ DBG(("%s: created gpu bo\n", __FUNCTION__)); } - assert(priv->gpu_bo->proxy == NULL); - if (priv->mapped) { - assert(!priv->shm); - pixmap->devPrivate.ptr = NULL; - priv->mapped = false; + if (priv->gpu_bo->proxy) { + DBG(("%s: reusing cached upload\n", __FUNCTION__)); + assert((flags & MOVE_WRITE) == 0); + assert(priv->gpu_damage == NULL); + return priv; } if (priv->shm) { @@ -2541,6 +2549,7 @@ sna_add_flush_pixmap(sna, priv, priv->cpu_bo); } + assert(priv->cpu_damage); region_set(&r, box); if (MIGRATE_ALL || region_subsumes_damage(&r, priv->cpu_damage)) { int n; @@ -2662,6 +2671,8 @@ pixmap->drawable.width, pixmap->drawable.height); } + if (DAMAGE_IS_ALL(priv->gpu_damage)) + sna_pixmap_free_cpu(sna, priv); } if (priv->cpu_damage == NULL && priv->flush) list_del(&priv->list); diff -Nru xserver-xorg-video-intel-2.21.6+git20130502.5637c173/src/sna/sna_composite.c xserver-xorg-video-intel-2.21.6+git20130514.3ee42de0/src/sna/sna_composite.c --- xserver-xorg-video-intel-2.21.6+git20130502.5637c173/src/sna/sna_composite.c 2013-03-22 21:00:42.000000000 +0000 +++ xserver-xorg-video-intel-2.21.6+git20130514.3ee42de0/src/sna/sna_composite.c 2013-05-14 14:33:04.000000000 +0000 @@ -404,8 +404,8 @@ static void apply_damage(struct sna_composite_op *op, RegionPtr region) { - DBG(("%s: damage=%p, region=%ld [(%d, %d), (%d, %d) + (%d, %d)]\n", - __FUNCTION__, op->damage, RegionNumRects(region), + DBG(("%s: damage=%p, region=%d [(%d, %d), (%d, %d) + (%d, %d)]\n", + __FUNCTION__, op->damage, (int)RegionNumRects(region), region->extents.x1, region->extents.y1, region->extents.x2, region->extents.y2, op->dst.x, op->dst.y)); @@ -995,8 +995,9 @@ color->alpha, dst->format); priv->clear = ok; - DBG(("%s: marking clear [%08x]? %d\n", - __FUNCTION__, priv->clear_color, ok)); + DBG(("%s: pixmap=%ld marking clear [%08x]? %d\n", + __FUNCTION__, pixmap->drawable.serialNumber, + priv->clear_color, ok)); } } goto done; diff -Nru xserver-xorg-video-intel-2.21.6+git20130502.5637c173/src/sna/sna_trapezoids.c xserver-xorg-video-intel-2.21.6+git20130514.3ee42de0/src/sna/sna_trapezoids.c --- xserver-xorg-video-intel-2.21.6+git20130502.5637c173/src/sna/sna_trapezoids.c 2013-03-22 21:00:42.000000000 +0000 +++ xserver-xorg-video-intel-2.21.6+git20130514.3ee42de0/src/sna/sna_trapezoids.c 2013-05-14 14:33:04.000000000 +0000 @@ -2476,6 +2476,17 @@ pixman_image_unref(image); } +inline static void trapezoid_origin(const xLineFixed *l, int16_t *x, int16_t *y) +{ + if (l->p1.y < l->p2.y) { + *x = pixman_fixed_to_int(l->p1.x); + *y = pixman_fixed_to_int(l->p1.y); + } else { + *x = pixman_fixed_to_int(l->p2.x); + *y = pixman_fixed_to_int(l->p2.y); + } +} + static void trapezoids_fallback(struct sna *sna, CARD8 op, PicturePtr src, PicturePtr dst, @@ -2494,8 +2505,7 @@ pixman_format_code_t format; int error; - dst_x = pixman_fixed_to_int(traps[0].left.p1.x); - dst_y = pixman_fixed_to_int(traps[0].left.p1.y); + trapezoid_origin(&traps[0].left, &dst_x, &dst_y); trapezoids_bounds(ntrap, traps, &bounds); if (bounds.y1 >= bounds.y2 || bounds.x1 >= bounds.x2) @@ -2671,7 +2681,7 @@ PicturePtr dst, PictFormatPtr maskFormat, INT16 src_x, INT16 src_y, - int ntrap, xTrapezoid *traps, + int ntrap, const xTrapezoid *traps, bool force_fallback) { BoxRec stack_boxes[64], *boxes; @@ -2888,7 +2898,7 @@ inline static void composite_unaligned_trap_row(struct sna *sna, struct sna_composite_spans_op *tmp, - xTrapezoid *trap, int dx, + const xTrapezoid *trap, int dx, int y1, int y2, int covered, pixman_region16_t *clip) { @@ -2966,7 +2976,7 @@ flatten static void composite_unaligned_trap(struct sna *sna, struct sna_composite_spans_op *tmp, - xTrapezoid *trap, + const xTrapezoid *trap, int dx, int dy, pixman_region16_t *clip) { @@ -2975,6 +2985,8 @@ y1 = dy + pixman_fixed_to_int(trap->top); y2 = dy + pixman_fixed_to_int(trap->bottom); + DBG(("%s: y1=%d, y2=%d\n", __FUNCTION__, y1, y2)); + if (y1 == y2) { composite_unaligned_trap_row(sna, tmp, trap, dx, y1, y1 + 1, @@ -3006,9 +3018,9 @@ BoxRec box; box.x1 = dx + pixman_fixed_to_int(trap->left.p1.x); - box.x2 = dx + pixman_fixed_to_int(trap->right.p1.x); - box.y1 = y1; - box.y2 = y2 + (pixman_fixed_frac(trap->bottom) != 0); + box.x2 = dx + pixman_fixed_to_int(trap->right.p1.x + pixman_fixed_1_minus_e); + box.y1 = dy + pixman_fixed_to_int(trap->top); + box.y2 = dy + pixman_fixed_to_int(trap->bottom + pixman_fixed_1_minus_e); if (clip) { pixman_region16_t region; @@ -3058,7 +3070,7 @@ static void blt_unaligned_box_row(PixmapPtr scratch, BoxPtr extents, - xTrapezoid *trap, + const xTrapezoid *trap, int y1, int y2, int covered) { @@ -3188,7 +3200,7 @@ static void lerp32_unaligned_box_row(PixmapPtr scratch, uint32_t color, const BoxRec *extents, - xTrapezoid *trap, int16_t dx, + const xTrapezoid *trap, int16_t dx, int16_t y, int16_t h, uint8_t covered) { @@ -3286,7 +3298,7 @@ static void pixsolid_unaligned_box_row(struct pixman_inplace *pi, const BoxRec *extents, - xTrapezoid *trap, + const xTrapezoid *trap, int16_t y, int16_t h, uint8_t covered) { @@ -3320,7 +3332,8 @@ static bool composite_unaligned_boxes_inplace__solid(struct sna *sna, CARD8 op, uint32_t color, - PicturePtr dst, int n, xTrapezoid *t, + PicturePtr dst, + int n, const xTrapezoid *t, bool force_fallback) { PixmapPtr pixmap; @@ -3646,7 +3659,7 @@ composite_unaligned_boxes_inplace(struct sna *sna, CARD8 op, PicturePtr src, int16_t src_x, int16_t src_y, - PicturePtr dst, int n, xTrapezoid *t, + PicturePtr dst, int n, const xTrapezoid *t, bool force_fallback) { if (!force_fallback && @@ -3800,7 +3813,7 @@ PicturePtr src, PicturePtr dst, INT16 src_x, INT16 src_y, - int ntrap, xTrapezoid *traps, + int ntrap, const xTrapezoid *traps, bool force_fallback) { ScreenPtr screen = dst->pDrawable->pScreen; @@ -3820,12 +3833,11 @@ force_fallback)) return true; - dst_x = pixman_fixed_to_int(traps[0].left.p1.x); - dst_y = pixman_fixed_to_int(traps[0].left.p1.y); + trapezoid_origin(&traps[0].left, &dst_x, &dst_y); dx = dst->pDrawable->x; dy = dst->pDrawable->y; for (n = 0; n < ntrap; n++) { - xTrapezoid *t = &traps[n]; + const xTrapezoid *t = &traps[n]; PixmapPtr scratch; PicturePtr mask; BoxRec extents; @@ -3915,21 +3927,21 @@ PicturePtr dst, PictFormatPtr maskFormat, INT16 src_x, INT16 src_y, - int ntrap, xTrapezoid *traps, + int ntrap, const xTrapezoid *traps, bool force_fallback) { BoxRec extents; struct sna_composite_spans_op tmp; struct sna_pixmap *priv; pixman_region16_t clip, *c; - int dst_x, dst_y; + int16_t dst_x, dst_y; int dx, dy, n; if (NO_UNALIGNED_BOXES) return false; - DBG(("%s: force_fallback=%d, mask=%x, n=%d\n", - __FUNCTION__, force_fallback, maskFormat ? (int)maskFormat->format : 0, ntrap)); + DBG(("%s: force_fallback=%d, mask=%x, n=%d, op=%d\n", + __FUNCTION__, force_fallback, maskFormat ? (int)maskFormat->format : 0, ntrap, op)); /* need a span converter to handle overlapping traps */ if (ntrap > 1 && maskFormat) @@ -3945,9 +3957,11 @@ force_fallback); } - dst_x = extents.x1 = pixman_fixed_to_int(traps[0].left.p1.x); + trapezoid_origin(&traps[0].left, &dst_x, &dst_y); + + extents.x1 = pixman_fixed_to_int(traps[0].left.p1.x); extents.x2 = pixman_fixed_to_int(traps[0].right.p1.x + pixman_fixed_1_minus_e); - dst_y = extents.y1 = pixman_fixed_to_int(traps[0].top); + extents.y1 = pixman_fixed_to_int(traps[0].top); extents.y2 = pixman_fixed_to_int(traps[0].bottom + pixman_fixed_1_minus_e); DBG(("%s: src=(%d, %d), dst=(%d, %d)\n", @@ -3996,8 +4010,10 @@ c = NULL; if (extents.x2 - extents.x1 > clip.extents.x2 - clip.extents.x1 || - extents.y2 - extents.y1 > clip.extents.y2 - clip.extents.y1) + extents.y2 - extents.y1 > clip.extents.y2 - clip.extents.y1) { + DBG(("%s: forcing clip\n", __FUNCTION__)); c = &clip; + } extents = *RegionExtents(&clip); dx = dst->pDrawable->x; @@ -4016,18 +4032,23 @@ case PictOpOver: priv = sna_pixmap(get_drawable_pixmap(dst->pDrawable)); assert(priv != NULL); - if (priv->clear && priv->clear_color == 0) + if (priv->clear && priv->clear_color == 0) { + DBG(("%s: converting %d to PictOpSrc\n", + __FUNCTION__, op)); op = PictOpSrc; + } break; case PictOpIn: priv = sna_pixmap(get_drawable_pixmap(dst->pDrawable)); assert(priv != NULL); - if (priv->clear && priv->clear_color == 0) + if (priv->clear && priv->clear_color == 0) { + DBG(("%s: clear destination using In, skipping\n", + __FUNCTION__)); return true; + } break; } - memset(&tmp, 0, sizeof(tmp)); if (!sna->render.composite_spans(sna, op, src, dst, src_x + extents.x1 - dst_x - dx, src_y + extents.y1 - dst_y - dy, @@ -4035,7 +4056,7 @@ extents.x2 - extents.x1, extents.y2 - extents.y1, COMPOSITE_SPANS_RECTILINEAR, - &tmp)) { + memset(&tmp, 0, sizeof(tmp)))) { DBG(("%s: composite spans render op not supported\n", __FUNCTION__)); REGION_UNINIT(NULL, &clip); @@ -4202,8 +4223,7 @@ if (NO_SCAN_CONVERTER) return false; - dst_x = pixman_fixed_to_int(traps[0].left.p1.x); - dst_y = pixman_fixed_to_int(traps[0].left.p1.y); + trapezoid_origin(&traps[0].left, &dst_x, &dst_y); trapezoids_bounds(ntrap, traps, &extents); if (extents.y1 >= extents.y2 || extents.x1 >= extents.x2) @@ -4558,8 +4578,7 @@ return false; } - dst_x = pixman_fixed_to_int(traps[0].left.p1.x); - dst_y = pixman_fixed_to_int(traps[0].left.p1.y); + trapezoid_origin(&traps[0].left, &dst_x, &dst_y); trapezoids_bounds(ntrap, traps, &extents); if (extents.y1 >= extents.y2 || extents.x1 >= extents.x2)